--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4
+-- Module Version: 5.8
+--/d/jspc29/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n fifo_9x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo3c00f -type ebfifo -depth 1024 -width 9 -rwidth 9 -regout -resetmode SYNC -no_enable -pe 10 -pf 1000 -sync_reset
+
+-- Thu Jan 7 15:37:39 2016
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library MACHXO3L;
+use MACHXO3L.components.all;
+-- synopsys translate_on
+
+entity fifo_9x2k_oreg is
+ port (
+ Data: in std_logic_vector(8 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(8 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_9x2k_oreg;
+
+architecture Structure of fifo_9x2k_oreg is
+
+ -- internal signal declarations
+ signal Empty_int: std_logic;
+ signal Full_int: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FIFO8KB
+ generic (FULLPOINTER1 : in String; FULLPOINTER : in String;
+ AFPOINTER1 : in String; AFPOINTER : in String;
+ AEPOINTER1 : in String; AEPOINTER : in String;
+ ASYNC_RESET_RELEASE : in String; RESETMODE : in String;
+ GSR : in String; CSDECODE_R : in String;
+ CSDECODE_W : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSR0: in std_logic; CSR1: in std_logic;
+ FULLI: in std_logic; EMPTYI: in std_logic;
+ WE: in std_logic; RE: in std_logic; ORE: in std_logic;
+ CLKW: in std_logic; CLKR: in std_logic; RST: in std_logic;
+ RPRST: in std_logic; DO0: out std_logic;
+ DO1: out std_logic; DO2: out std_logic;
+ DO3: out std_logic; DO4: out std_logic;
+ DO5: out std_logic; DO6: out std_logic;
+ DO7: out std_logic; DO8: out std_logic;
+ DO9: out std_logic; DO10: out std_logic;
+ DO11: out std_logic; DO12: out std_logic;
+ DO13: out std_logic; DO14: out std_logic;
+ DO15: out std_logic; DO16: out std_logic;
+ DO17: out std_logic; EF: out std_logic;
+ AEF: out std_logic; AFF: out std_logic; FF: out std_logic);
+ end component;
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ fifo_9x2k_oreg_0_0: FIFO8KB
+ generic map (FULLPOINTER1=> "0b01111111111000", FULLPOINTER=> "0b10000000000000",
+ AFPOINTER1=> "0b01111100111000", AFPOINTER=> "0b01111101000000",
+ AEPOINTER1=> "0b00000001011000", AEPOINTER=> "0b00000001010000",
+ ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE=> "OUTREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11",
+ DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 9)
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, CSW0=>scuba_vhi, CSW1=>scuba_vhi,
+ CSR0=>RdEn, CSR1=>scuba_vhi, FULLI=>Full_int,
+ EMPTYI=>Empty_int, WE=>WrEn, RE=>scuba_vhi, ORE=>scuba_vhi,
+ CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, RPRST=>RPReset,
+ DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), DO4=>Q(4),
+ DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8), DO9=>open,
+ DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open,
+ DO15=>open, DO16=>open, DO17=>open, EF=>Empty_int,
+ AEF=>AlmostEmpty, AFF=>AlmostFull, FF=>Full_int);
+
+ Empty <= Empty_int;
+ Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library MACHXO3L;
+configuration Structure_CON of fifo_9x2k_oreg is
+ for Structure
+ for all:VHI use entity MACHXO3L.VHI(V); end for;
+ for all:VLO use entity MACHXO3L.VLO(V); end for;
+ for all:FIFO8KB use entity MACHXO3L.FIFO8KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+--Media interface for Lattice ECP5 using PCS at 2GHz
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.med_sync_define.all;
+
+entity med_ecp5_sfp_sync is
+ generic(
+ SERDES_NUM : integer range 0 to 3 := 0;
+ IS_SYNC_SLAVE : integer := c_YES --select slave mode
+ );
+ port(
+ CLK_REF_FULL : in std_logic; -- 200 MHz reference clock
+ CLK_INTERNAL_FULL : in std_logic; -- internal 200 MHz, always on
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ --Internal Connection TX
+ MEDIA_MED2INT : out MED2INT;
+ MEDIA_INT2MED : in INT2MED;
+
+ --Sync operation
+ RX_DLM : out std_logic := '0';
+ RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
+ TX_DLM : in std_logic := '0';
+ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
+
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic := '0';
+ SD_RXD_N_IN : in std_logic := '0';
+ SD_TXD_P_OUT : out std_logic := '0';
+ SD_TXD_N_OUT : out std_logic := '0';
+ SD_REFCLK_P_IN : in std_logic; --not used
+ SD_REFCLK_N_IN : in std_logic; --not used
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+ --Control Interface
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+
+ -- Status and control port
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
+ );
+end entity;
+
+
+architecture med_ecp5_sfp_sync_arch of med_ecp5_sfp_sync is
+
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of med_ecp5_sfp_sync_arch : architecture is "media_interface_group";
+ attribute syn_sharing : string;
+ attribute syn_sharing of med_ecp5_sfp_sync_arch : architecture is "off";
+ attribute syn_hier : string;
+ attribute syn_hier of med_ecp5_sfp_sync_arch : architecture is "hard";
+
+-- signal clk_200_i : std_logic;
+signal clk_200_ref : std_logic;
+signal clk_rx_full, clk_rx_half : std_logic;
+signal clk_tx_full, clk_tx_half : std_logic;
+
+signal tx_data : std_logic_vector(7 downto 0);
+signal tx_k : std_logic;
+signal rx_data : std_logic_vector(7 downto 0);
+signal rx_k : std_logic;
+signal rx_error : std_logic;
+
+signal rst_n : std_logic;
+signal rx_serdes_rst : std_logic;
+signal tx_serdes_rst : std_logic;
+signal tx_pcs_rst : std_logic;
+signal rx_pcs_rst : std_logic;
+signal rst_qd : std_logic;
+signal serdes_rst_qd : std_logic;
+
+signal rx_los_low : std_logic;
+signal lsm_status : std_logic;
+signal rx_cdr_lol : std_logic;
+signal tx_pll_lol : std_logic;
+
+signal sci_ch_i : std_logic_vector(4 downto 0);
+signal sci_addr_i : std_logic_vector(5 downto 0);
+signal sci_data_in_i : std_logic_vector(7 downto 0);
+signal sci_data_out_i : std_logic_vector(7 downto 0);
+signal sci_read_i : std_logic;
+signal sci_write_i : std_logic;
+
+signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";
+signal wa_position_sel : std_logic_vector(3 downto 0);
+
+signal stat_rx_control_i : std_logic_vector(31 downto 0);
+signal stat_tx_control_i : std_logic_vector(31 downto 0);
+signal debug_rx_control_i : std_logic_vector(31 downto 0);
+signal debug_tx_control_i : std_logic_vector(31 downto 0);
+signal stat_fsm_reset_i : std_logic_vector(31 downto 0);
+
+signal hdinp, hdinn, hdoutp, hdoutn : std_logic;
+attribute nopad : string;
+attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true";
+
+
+begin
+
+clk_200_ref <= CLK_REF_FULL;
+
+SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
+
+-- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
+-- clk_200_i <= clk_rx_full;
+-- end generate;
+--
+-- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
+-- clk_200_i <= clk_200_internal;
+-- end generate;
+
+
+-------------------------------------------------
+-- Serdes
+-------------------------------------------------
+gen_pcs0 : if SERDES_NUM = 0 generate
+ THE_SERDES : entity work.serdes_sync_0
+ port map(
+ hdinp => hdinp,
+ hdinn => hdinn,
+ hdoutp => hdoutp,
+ hdoutn => hdoutn,
+ rxrefclk => CLK_INTERNAL_FULL,
+ rx_pclk => clk_rx_full,
+ tx_pclk => clk_tx_full,
+
+ txdata => tx_data,
+ tx_k(0) => tx_k,
+ tx_force_disp(0) => '0',
+ tx_disp_sel(0) => '0',
+ rxdata => rx_data,
+ rx_k(0) => rx_k,
+ rx_disp_err(0) => open,
+ rx_cv_err(0) => rx_error,
+
+ tx_idle_c => '0',
+ signal_detect_c => '0', --?
+ rx_los_low_s => rx_los_low,
+ lsm_status_s => lsm_status,
+ rx_cdr_lol_s => rx_cdr_lol,
+ rx_pcs_rst_c => rx_pcs_rst,
+ tx_pcs_rst_c => tx_pcs_rst,
+ rx_serdes_rst_c => rx_serdes_rst,
+
+
+ sci_wrdata => sci_data_in_i,
+ sci_rddata => sci_data_out_i,
+ sci_addr => sci_addr_i,
+ sci_en_dual => '1', --?
+ sci_sel_dual => sci_ch_i(4),
+ sci_en => '1' --?
+ sci_sel => sci_ch_i(0),
+ sci_rd => sci_read_i,
+ sci_wrn => sci_write_i,
+ sci_int => open,
+
+ cyawstn => '0', --?
+ rst_dual_c => rst_qd,
+ serdes_rst_dual_c => '0',
+ tx_pwrup_c => '1',
+ rx_pwrup_c => '1',
+ serdes_pdb => '1',
+ tx_serdes_rst_c => '0',
+
+ pll_refclki => '0',
+ sli_rst => '0',
+ pll_lol => tx_pll_lol
+ );
+end generate;
+
+ tx_serdes_rst <= '0'; --no function
+ serdes_rst_qd <= '0'; --included in rst_qd
+ wa_position_sel <= x"0";
+-- wa_position_sel <= wa_position(3 downto 0) when SERDES_NUM = 0
+-- else wa_position(15 downto 12) when SERDES_NUM = 3;
+
+THE_MED_CONTROL : entity work.med_sync_control
+ generic map(
+ IS_SYNC_SLAVE => IS_SYNC_SLAVE,
+ IS_TX_RESET => 1
+ )
+ port map(
+ CLK_SYS => SYSCLK,
+ CLK_RXI => clk_rx_full, --clk_rx_full,
+ CLK_RXHALF => clk_rx_half,
+ CLK_TXI => clk_200_ref, --clk_200_internal, --clk_tx_full, JM150706
+ CLK_REF => CLK_INTERNAL_FULL,
+ RESET => RESET,
+ CLEAR => CLEAR,
+
+ SFP_LOS => SD_LOS_IN,
+ TX_LOL => tx_pll_lol,
+ RX_CDR_LOL => rx_cdr_lol,
+ RX_LOS => rx_los_low,
+ WA_POSITION => wa_position_sel,
+
+ RX_SERDES_RST => rx_serdes_rst,
+ RX_PCS_RST => rx_pcs_rst,
+ QUAD_RST => rst_qd,
+ TX_PCS_RST => tx_pcs_rst,
+
+ MEDIA_MED2INT => MEDIA_MED2INT,
+ MEDIA_INT2MED => MEDIA_INT2MED,
+
+ TX_DATA => tx_data,
+ TX_K => tx_k,
+ RX_DATA => rx_data,
+ RX_K => rx_k,
+
+ TX_DLM_WORD => TX_DLM_WORD,
+ TX_DLM => TX_DLM,
+ RX_DLM_WORD => RX_DLM_WORD,
+ RX_DLM => RX_DLM,
+
+ STAT_TX_CONTROL => stat_tx_control_i,
+ STAT_RX_CONTROL => stat_rx_control_i,
+ DEBUG_TX_CONTROL => debug_tx_control_i,
+ DEBUG_RX_CONTROL => debug_rx_control_i,
+ STAT_RESET => stat_fsm_reset_i
+ );
+
+THE_SCI_READER : entity work.sci_reader
+ port map(
+ CLK => SYSCLK,
+ RESET => RESET,
+
+ --SCI
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i,
+ SCI_SEL => sci_ch_i,
+ SCI_RD => sci_read_i,
+ SCI_WR => sci_write_i,
+
+ WA_POS_OUT => wa_position,
+
+ --Slowcontrol
+ BUS_RX => BUS_RX,
+ BUS_TX => BUS_TX,
+
+ MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i,
+ MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i,
+ MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i,
+ MEDIA_STATUS_REG_IN(127 downto 96) => (others => '0'),
+ DEBUG_OUT => open
+ );
+
+-- STAT_DEBUG(4 downto 0) <= debug_rx_control_i(4 downto 0);
+-- STAT_DEBUG(6 downto 5) <= stat_fsm_reset_i(9 downto 8);
+-- STAT_DEBUG(7) <= '0';
+-- STAT_DEBUG(15 downto 8) <= stat_fsm_reset_i(7 downto 0);
+-- STAT_DEBUG(15 downto 0) <= debug_tx_control_i(31 downto 16);
+STAT_DEBUG(15 downto 0) <= debug_rx_control_i(15 downto 0);
+
+end architecture;
+
jspc29 / trbnet.git / commitdiff