still working

diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd
index 8cba59b5f77489c785a3e8f3db360a367ca57536..a3123fd642f5596ad8eacd9a80f5d6ecd2b0418b 100644 (file)
--- a/media_interfaces/sync/med_sync_control.vhd
+++ b/media_interfaces/sync/med_sync_control.vhd
@@ -117,7 +117,8 @@ signal DEBUG_OUT_i        : std_logic_vector(31 downto 0);
 
 signal last_FORCE_CRC_ERROR_IN : std_logic;
 signal crc_error_delay : std_logic_vector(3 downto 0) := "0000";
-signal tx_got_force_error : std_logic := '0';
+signal tx_got_force_error : std_logic;
+signal tx_got_force_error_100 : std_logic := '0';
 signal tx_force_crc_error : std_logic := '0';
 signal tx_force_pak_error : std_logic := '0';
       
@@ -139,6 +140,8 @@ reset_i   <=     (RESET or sd_los_i or make_link_reset_real_i);
 last_FORCE_CRC_ERROR_IN  <= FORCE_CRC_ERROR_IN when rising_edge(CLK_SYS);
 DEBUG_RETRANS_OUT <= start_retr_counter & request_retr_counter when rising_edge(CLK_SYS);
 
+tx_got_force_error_100 <= tx_got_force_error when rising_edge(CLK_SYS);
+
 media_med2int_i.clk_half <= CLK_RXHALF;
 media_med2int_i.clk_full <= CLK_RXI;
 
@@ -255,7 +258,8 @@ PROC_REG : process begin
     BUS_TX.ack <= '1';
     case BUS_RX.addr(1 downto 0) is
       when "00"   => BUS_TX.data <= x"00000" & "00" & tx_force_pak_error & tx_force_crc_error & crc_error_delay & "000" & force_crc_error;
-      when "01"   => BUS_TX.data <= request_retr_counter & start_retr_counter;    
+      when "01"   => BUS_TX.data <= request_retr_counter & start_retr_counter;
+      when "11"   => BUS_TX.data <= x"000000" & DEBUG_RX_CONTROL_i(31 downto 24);
       when others => BUS_TX.unknown <= '1';
     end case;
   end if;
@@ -266,7 +270,7 @@ PROC_REG : process begin
     force_crc_error <= '0';
   end if;
 
-  if tx_got_force_error = '1' then
+  if tx_got_force_error_100 = '1' then
     tx_force_crc_error <= '0';
     tx_force_pak_error <= '0';
   end if;

diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd
index 3416fed1001e7f23167ad6c839cdb0fa42d514ac..5a997468d29df5acdb74fc1f262c0efad69543cf 100644 (file)
--- a/media_interfaces/sync/rx_control.vhd
+++ b/media_interfaces/sync/rx_control.vhd
@@ -99,27 +99,24 @@ signal pulse_bad_100       : std_logic;
 signal waiting_for_retr    : std_logic := '0';
 signal good_pos_counter    : std_logic_vector(7 downto 0) := (others => '0');
 signal num_pakets          : unsigned(3 downto 0) := (others => '0');
+signal reg_num_pakets          : unsigned(3 downto 0) := (others => '0');
 
 signal use_crc             : std_logic := '0';
+signal use_crc_200         : std_logic := '0';
 signal last_use_crc        : std_logic := '0';
 signal load_use_crc        : std_logic := '0';
+signal load_use_crc_sys    : std_logic := '0';
 signal disable_crc         : std_logic := '0';
 
 signal num_crc          : unsigned(3 downto 0) := (others => '0');
 signal num_pak          : unsigned(3 downto 0) := (others => '0');
 signal resub_mode       : std_logic := '0';
---signal last_good_pos_counter    : std_logic_vector(7 downto 0) := (others => '0');
---signal last_send_link_reset_i  : std_logic;
-signal reset_retrans   : std_logic;
+signal reset_retrans    : std_logic;
 signal force_crc_error_int : std_logic := '0';
+signal force_crc_error_200 : std_logic := '0';
 
---signal num_count : unsigned(7 downto 0) := (others => '0');
---signal max_count : unsigned(7 downto 0) := (others => '0');
---signal bad_crc      : std_logic_vector(7 downto 0);
---signal good_crc      : std_logic_vector(7 downto 0);
---signal store_crc   : std_logic := '0';
 signal CRC_ERROR_DELAY_cnt : std_logic_vector(3 downto 0) := (others => '0');
-
+signal CRC_ERROR_DELAY_200 : std_logic_vector(3 downto 0) := (others => '0');
 
 
 begin
@@ -142,6 +139,10 @@ last_ct_fifo_read  <= ct_fifo_read  when rising_edge(CLK_100);
 last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_100);
 last_use_crc  <= use_crc  when rising_edge(CLK_100);
 reset_retrans <= RESET_RETRANSMIT_IN when rising_edge(CLK_100);
+load_use_crc_sys <= load_use_crc when rising_edge(CLK_100);
+force_crc_error_200 <= force_crc_error when rising_edge(CLK_200);
+CRC_ERROR_DELAY_200 <= CRC_ERROR_DELAY when rising_edge(CLK_200);
+use_crc_200 <= use_crc  when rising_edge(CLK_200);
 
 process begin
   wait until rising_edge(CLK_100);
@@ -149,7 +150,7 @@ process begin
   if ct_fifo_empty = '1' then
     got_pulse_bad <= '0';
     got_pulse_good <= '0';
-    if load_use_crc = '1' then
+    if load_use_crc_sys = '1' then
       use_crc <= '1';
     else
       use_crc <= '0';
@@ -263,7 +264,7 @@ PROC_RX_FSM : process begin
             resub_mode      <= '0';
           when K_RST =>
             rx_state        <= MAKE_RESET;
-            reset_cnt <= x"000";
+            reset_cnt       <= x"000";
           when K_DLM =>
             rx_state        <= GET_DLM;
           when K_REQ =>
@@ -278,6 +279,9 @@ PROC_RX_FSM : process begin
         rx_state            <= GET_DATA;
         crc_en              <= '1';
       end if;
+      if force_crc_error_int = '1' then 
+        rx_state            <= GET_CRC;
+      end if;
       
     when GET_IDLE =>
       rx_state_bits         <= x"3";
@@ -286,70 +290,84 @@ PROC_RX_FSM : process begin
       if  reg_rx_k_in = '0' and reg_rx_data_in = D_IDLE1 then
         idle_hist_i(0)      <= '1';
         got_link_ready_i    <= got_link_ready_i or (idle_hist_i(1) and idle_hist_i(3));
-      elsif  reg_rx_k_in = '1' then
-        rx_state <= FIRST; -- SLEEP;
+      else
+        if reg_rx_k_in = '1' then
+          rx_state <= FIRST;
+        end if;
+        if use_crc_200 = '1' and force_crc_error_int = '0' then
+          rx_state            <= FIRST; 
+          force_crc_error_int <= '1';
+        end if;
       end if;
-      if use_crc = '1' and num_pakets /= 0 and force_crc_error_int = '0' then
+      if use_crc_200 = '1' and num_pakets /= 0 and force_crc_error_int = '0' then
         -- IDLE only allowed after CRC
-        rx_state <= GET_CRC;
+        rx_state            <= FIRST; 
+        --reg_num_pakets      <= num_pakets; --debug
         force_crc_error_int <= '1';
       end if;
       
     when GET_DATA =>
+      num_pakets            <= num_pakets+1;
       rx_state_bits         <= x"4";
       crc_en                <= '1';
       if reg_rx_k_in = '0' then
-         next_sop            <= '0';
+        next_sop            <= '0';
         rx_data(15 downto 8)<= reg_rx_data_in;
         rx_data(16)         <= next_sop;
         rx_data(17)         <= '0';
         ct_fifo_write       <= '1';
-        num_pakets          <= num_pakets+1;
         rx_state            <= FIRST;
       else
-        rx_state <= FIRST; -- SLEEP;        
-
+        rx_state            <= FIRST; -- SLEEP;        
       end if;
 
     when GET_CRC =>
-      if use_crc = '0' then
+      if use_crc_200 = '0' then
         -- first time
         load_use_crc        <= '1';
         disable_crc         <= '0';
         force_crc_error_int <= '0';
       else
-        if (crc_q /= reg_rx_data_in or waiting_for_retr = '1' or --- or num_pakets /= 5)
-          (force_crc_error = '1' and CRC_ERROR_DELAY_cnt = "0000") or force_crc_error_int = '1') and disable_crc = '0' then
+        if (crc_q /= reg_rx_data_in
+            or (force_crc_error_200 = '1' and CRC_ERROR_DELAY_cnt = "0000")
+            or waiting_for_retr = '1'
+            --- or num_pakets /= 5
+            or force_crc_error_int = '1') and disable_crc = '0' then 
           -- bad
-          pulse_bad        <= '1';
+          if force_crc_error_int = '1' then --debug
+            reg_num_pakets <= reg_num_pakets + 1; 
+          else
+            pulse_bad        <= '1';
+          end if;
           if waiting_for_retr = '0' then
-            if crc_q /= reg_rx_data_in then
-              num_crc <= num_crc+1;
-            else
-              num_pak <= num_pak+1;
-            end if;
-             req_retr_i       <= '1';
+            --if crc_q /= reg_rx_data_in then --debug
+              --num_crc <= num_crc+1;
+            --else
+              --num_pak <= num_pak+1;
+            --end if;
+            req_retr_i       <= '1';
             waiting_for_retr <= '1';
-          end if;          
+          --end if;
+          end if;
+          force_crc_error_int <= '0'; 
         else
           -- good
           pulse_good          <= '1';
           force_crc_error_int <= '0';
-          if force_crc_error = '0' then
-            CRC_ERROR_DELAY_cnt <= CRC_ERROR_DELAY;
+          if force_crc_error_200 = '0' then
+            CRC_ERROR_DELAY_cnt <= CRC_ERROR_DELAY_200;
             disable_crc <= '0';
+          elsif CRC_ERROR_DELAY_cnt /= "0000" then
+            CRC_ERROR_DELAY_cnt <= std_logic_vector(unsigned(CRC_ERROR_DELAY_cnt) - 1);
           end if;                    
         end if;
       end if;
-      crc_reset          <= '1';
-      rx_state           <= FIRST;
-      num_pakets <= (others => '0'); 
-      if force_crc_error = '1' then
-        CRC_ERROR_DELAY_cnt <= std_logic_vector(unsigned(CRC_ERROR_DELAY_cnt) - 1);
-      end if;
-      
+      crc_reset   <= '1';
+      rx_state    <= FIRST;
+      num_pakets  <= (others => '0');
+            
     when GET_RETR =>
-      if force_crc_error = '1' then
+      if force_crc_error_200 = '1' then
         disable_crc <= '1';
       end if;
       rx_state              <= FIRST;
@@ -377,6 +395,7 @@ PROC_RX_FSM : process begin
       waiting_for_retr      <= '0';
       num_pakets            <= (others => '0');
       resub_mode            <= '0';
+      force_crc_error_int   <= '0';
       if reg_rx_k_in = '1' and reg_rx_data_in = K_RST then
         send_link_reset_i   <= '1';
         make_reset_i        <= '0';
@@ -506,12 +525,13 @@ DEBUG_OUT(17)           <= make_reset_i;
 DEBUG_OUT(18)           <= send_link_reset_i;
 DEBUG_OUT(19)           <= '1' when rx_state_bits = x"f" else '0';
 
-DEBUG_OUT(20)           <= use_crc;
-
-DEBUG_OUT(23 downto 21) <= (others => '0');
-DEBUG_OUT(31 downto 28) <= num_pak;
-DEBUG_OUT(27 downto 24) <= num_crc;
-
+DEBUG_OUT(23 downto 20) <= (others => '0');
+--DEBUG_OUT(31 downto 28) <= num_pak;
+--DEBUG_OUT(27 downto 24) <= num_crc;
+DEBUG_OUT(24) <= force_crc_error_int when rising_edge(clk_100);
+DEBUG_OUT(25) <= use_crc;
+DEBUG_OUT(27 downto 26) <= (others => '0');
+DEBUG_OUT(31 downto 28) <= reg_num_pakets when rising_edge(clk_100);
 
 
 -- DEBUG_OUT(23 downto 16) <= rx_data(7 downto 0);

diff --git a/media_interfaces/sync/sci_reader.vhd b/media_interfaces/sync/sci_reader.vhd
index 61310f821ddb3afbd5eb86361ce263084f6e9410..e450e2badeb253409b72aecd8d19f5acbf4c3204 100644 (file)
--- a/media_interfaces/sync/sci_reader.vhd
+++ b/media_interfaces/sync/sci_reader.vhd
@@ -115,7 +115,6 @@ begin
       if sci_reg_i = '1' then
         --BUS_TX.data   <= MEDIA_STATUS_REG_IN(32*(to_integer(unsigned(BUS_RX.addr(4 downto 0))))+31 downto 32*(to_integer(unsigned(BUS_RX.addr(4 downto 0)))));
         --BUS_TX.ack    <= '1';
-        BUS_TX.data <= x"12341234";
         LOC_BUS_RX.read  <= BUS_RX.read;
         LOC_BUS_RX.write <= BUS_RX.write;
         SCI_WR        <= '0';

diff --git a/media_interfaces/sync/tx_control.vhd b/media_interfaces/sync/tx_control.vhd
index 6e19ec8cf1884b9f1425742add2ac6cf90f021e9..0a53b656e993d366ac6fe9964c9620fa8f3b43ab 100644 (file)
--- a/media_interfaces/sync/tx_control.vhd
+++ b/media_interfaces/sync/tx_control.vhd
@@ -122,7 +122,9 @@ architecture arch of tx_control is
   --signal num_pak          : unsigned(15 downto 0) := (others => '0');
   signal resub_mode    : std_logic := '0';
   signal reset_retrans : std_logic;
-  
+
+  signal FORCE_CRC_ERROR_200 : std_logic := '0';
+  signal FORCE_PAK_ERROR_200 : std_logic := '0';
 
 begin
 
@@ -162,7 +164,10 @@ begin
   
   last_ct_fifo_read   <= ct_fifo_read  when rising_edge(CLK_200);
   last_ct_fifo_empty  <= ct_fifo_empty when rising_edge(CLK_200);
-  
+
+  FORCE_CRC_ERROR_200 <= FORCE_CRC_ERROR when rising_edge(CLK_200);
+  FORCE_PAK_ERROR_200 <= FORCE_PAK_ERROR when rising_edge(CLK_200);
+    
   save_sop <= '1' when (TX_PACKET_NUMBER_IN = c_H0) else '0';
   save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0';
 
@@ -266,7 +271,7 @@ begin
           when SEND_IDLE_L =>
             TX_DATA_OUT        <= K_IDLE;
             TX_K_OUT           <= '1';
-            if FORCE_PAK_ERROR = '1' then
+            if FORCE_PAK_ERROR_200 = '1' and GOT_FORCE_ERROR = '0' then
               GOT_FORCE_ERROR <= '1';
               current_state      <= SEND_DATA_H;
             else
@@ -308,9 +313,10 @@ begin
             current_state      <= SEND_CHKSUM_H;
 
           when SEND_CHKSUM_H =>
-            if FORCE_CRC_ERROR = '1' then
+            if FORCE_CRC_ERROR_200 = '1' and GOT_FORCE_ERROR = '0' then
               GOT_FORCE_ERROR  <= '1';
-              TX_DATA_OUT      <= std_logic_vector(unsigned(crc_q) + 1);
+              --TX_DATA_OUT      <= std_logic_vector(unsigned(crc_q) + 1);
+              TX_DATA_OUT      <= x"ff";
             else
               TX_DATA_OUT      <= crc_q;
             end if;
@@ -398,7 +404,7 @@ begin
       if reset_retrans = '1' then
         resub_mode <= '0';
       end if;
-      if FORCE_PAK_ERROR = '0' and FORCE_CRC_ERROR = '0' then
+      if FORCE_PAK_ERROR_200 = '0' and FORCE_CRC_ERROR_200 = '0' then
         GOT_FORCE_ERROR <= '0';
       end if;
       
@@ -494,7 +500,7 @@ begin
         elsif start_retransmit_i = '1' then
           make_restart_i         <= '1';
           restart_position_i     <= restart_position_q;
-          load_read_pointer_i <= '1'; --prepare load at the same time
+          load_read_pointer_i    <= '1'; --prepare load at the same time
         elsif current_state = SEND_START_L then
           make_restart_i         <= '0';
         elsif current_state = SEND_START_H then