how to set up a new VHDL project, JM

diff --git a/trb3/VhdlProjectSetup.tex b/trb3/VhdlProjectSetup.tex
new file mode 100644 (file)
index 0000000..185f58f
--- /dev/null
+++ b/trb3/VhdlProjectSetup.tex
@@ -0,0 +1,31 @@
+A not complete list of steps how to create a new TRB3 VHDL project.
+\begin{itemize*}
+\item Choose a projectname. It has to start with \files{trb3\_periph\_*} or \files{trb3\_central\_*}.
+\item Create a new subdirectory inside \cmdname{./trb3/}. Choose a short, descriptive name for the project. Change to this directory.
+\item Create subdirectories  
+\begin{description*}
+\item[\files{workdir}] where all generated files during synthesis, map and par are stored
+\item[\files{code}] for your own vhd codes for this project
+\item[\files{cores}] for generated ipcores
+\item[\files{sim}] for the simulation project
+\item[\files{project}] if you want to create a Lattice Diamond Project
+\end{description*}
+\item Go to workdir and execute \cmdname{../../base/linkdesignfiles.sh}. This has to be repeated in \files{project/\$projectname}.
+\item Copy necessary files from another project. Choose one using the same FPGA you want to create your project and if possible one that uses the same pinout.
+\begin{description*}
+\item[\files{compile*.pl}] The main script that runs synthesis, map, par...
+\item[\files{}]
+\end{description*}
+\item Edit \files{compile*.pl}
+\begin{itemize*}
+\item Set the \cmdname{\$projectname}
+\item Check that all configuration options (the marked block in the beginning of the file) match your local environment.
+\item Check the 2 to 4 lines generating the constraint file if it accesses the correct files.
+\end{itemize*}
+\item Edit \files{\$projectname.prj}
+\begin{itemize*}
+\item Set your projectname (four places in total)
+\item Add / Remove source files as necessary
+\end{itemize*}
+\item Try to run the compile script.
+\end{itemize*}

diff --git a/trb3/main.pdf b/trb3/main.pdf
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diff --git a/trb3/main.tex b/trb3/main.tex
index 219b9cdf49a1b7324b791948c3eedceb361c81cb..61309d0191559199e0725eb68b5df75c8a4b3e8b 100644 (file)
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -79,7 +79,7 @@
 \author{Grzegorz Korcyl, Ludwig Maier, Jan Michel, Marek Palka, \\Manuel Penschuck, Pawel Strzempek, Michael Traxler, Cahit Ugur}
 
 
-\newcommand{\files}[1]{\textit{#1}}
+\newcommand{\files}[1]{\texttt{#1}}
 \newcommand{\signal}[1]{\textsc{#1}}
 \newcommand{\genericname}[1]{\textsc{#1}}
 \newcommand{\constname}[1]{\textsc{#1}}
@@ -162,6 +162,8 @@
   \cleardoublepage
 
 \part{Design Components}
+  \section{New VHDL Project}
+  \input{VhdlProjectSetup}
   \section{TDC}
     \subsection{Building Blocks}
       \input{TdcBuildingBlocks}