added correct PLL for 200MHz calibration oscillator, mt

diff --git a/dirich5s/config_compile_giessen.pl b/dirich5s/config_compile_giessen.pl
index b692b37d51a370164c8c5b3d4d51e97c195747ba..9a42f04d8899709aa3b0db4fa3026113e8f70583 100644 (file)
--- a/dirich5s/config_compile_giessen.pl
+++ b/dirich5s/config_compile_giessen.pl
@@ -3,7 +3,6 @@ Devicename  => 'LFE5UM-85F',
 Package     => 'CABGA381',
 Speedgrade  => '8',
 
-
 TOPNAME                      => "dirich5s",
 lm_license_file_for_synplify => "7788\@fb07pc-u102325",
 lm_license_file_for_par      => "7788\@fb07pc-u102325",

diff --git a/dirich5s/config_compile_gsi.pl b/dirich5s/config_compile_gsi.pl
index 902dc11b8ee53e1f9a482ad4855afdbd9d2b09a5..1af88c94061a6e42b61c680bf630c0df0419ef13 100644 (file)
--- a/dirich5s/config_compile_gsi.pl
+++ b/dirich5s/config_compile_gsi.pl
@@ -1,6 +1,6 @@
 Familyname  => 'ECP5UM',
 Devicename  => 'LFE5UM-85F',
-Package     => 'CABGA756',
+Package     => 'CABGA381',
 Speedgrade  => '8',
 
 TOPNAME                      => "dirich5s",

diff --git a/dirich5s/dirich5s.prj b/dirich5s/dirich5s.prj
index 8de4dd8d156e5d52ba24e521b7a51253e0f01674..0f11128765fdab3dc426cb6f7c47dc2f09f936f5 100644 (file)
--- a/dirich5s/dirich5s.prj
+++ b/dirich5s/dirich5s.prj
@@ -213,8 +213,11 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FI
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.vhd"
 #add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd"
+#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd"
+#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in125_out50.vhd"
+
 
 ### Triggering
 add_file -vhdl -lib work "./code/stretched_OR_trigger.vhd"

diff --git a/dirich5s/dirich5s.vhd b/dirich5s/dirich5s.vhd
index 1628beed5c632becce5ad6d28497f619760f621d..085878ef139c9714f67958391899a7e2f4638b31 100644 (file)
--- a/dirich5s/dirich5s.vhd
+++ b/dirich5s/dirich5s.vhd
@@ -166,7 +166,8 @@ begin
 --     end if;
 --   end process;
 
-THE_CAL_PLL : entity work.pll_in3125_out50
+--THE_CAL_PLL : entity work.pll_in3125_out50
+THE_CAL_PLL : entity work.pll_in200_out50
   port map(
     CLKI  => CLOCK_CAL,
     CLKOP => clk_cal

diff --git a/dirich5s/nodelist_hades69.txt b/dirich5s/nodelist_hades69.txt
new file mode 100644 (file)
index 0000000..44b6ae0
--- /dev/null
+++ b/dirich5s/nodelist_hades69.txt
@@ -0,0 +1,7 @@
+// nodes file for parallel place&route
+
+[localhost]
+SYSTEM = linux
+CORENUM = 12
+ENV = /home/hadaq/bin/diamond_env
+WORKDIR = /home/hadaq/vhdl/dirich/dirich5s/workdir

diff --git a/dirich5s/par.p2t b/dirich5s/par.p2t
index edb14a594748acbb2dc717608bf8aefa9ae155f6..fae8f59d395b42e06b53c758fd5d29ee2ab3a02a 100644 (file)
--- a/dirich5s/par.p2t
+++ b/dirich5s/par.p2t
@@ -5,7 +5,7 @@
 #-n 2                          # Controlled by the compile.pl script.
 -s 10
 #-t 96
--t 70
+-t 60
 -c 2
 -e 2
 -i 10
@@ -68,4 +68,4 @@
 #                    parHold. 
 #  parPlcInLimit              Cannot find in the online help
 #  parPlcInNeighborSize        Cannot find in the online help
--exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1
+-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=ON:paruseNBR=1