-const char trbnet_version[] = "$Revision: 2.42 $";
+const char trbnet_version[] = "$Revision: 2.43 $";
#include <stdio.h>
#include <stdlib.h>
/* ---------------------------------------------------------------------- */
/* Used for blocking Signals SIGINT and SIGTERM */
-static sigset_t blockSet;
+static sigset_t blockSet;
static sigset_t blockSetOld;
/* Semaphore handling */
static inline void write32_to_FPGA(uint16_t address, uint32_t value)
{
/* writes a 32bit word to a given address on a given device */
-
+
/* set address RW_WRITE */
- writePC((address & 0x7fff) | (fifoToggleBit ^ FIFO_TOGGLE_BIT));
-
+ fifoToggleBit ^= FIFO_TOGGLE_BIT;
+ writePC((address & 0x7fff) | fifoToggleBit);
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+
+
+
+
+
/* write value */
+ fifoToggleBit ^= FIFO_TOGGLE_BIT;
writePC((value >> 16) | fifoToggleBit);
+
fifoToggleBit ^= FIFO_TOGGLE_BIT;
writePC((value & 0xffff) | fifoToggleBit);
}
static inline void read32_from_FPGA(uint16_t address, uint32_t* value)
{
/* reads a 32bit word from a given address on a given device */
-
+
/* set address RW_READ */
- writePC((address | 0x8000) | (fifoToggleBit ^ FIFO_TOGGLE_BIT));
-
+ fifoToggleBit ^= FIFO_TOGGLE_BIT;
+ writePC((address | 0x8000) | fifoToggleBit);
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+
+
+
+
/* read value */
+ fifoToggleBit ^= FIFO_TOGGLE_BIT;
*value = ((readPB() << 16));
writePC(fifoToggleBit);
}
static inline int read32_from_FPGA_dma(uint16_t fifo_address,
- uint32_t* values,
+ uint32_t* values,
uint32_t size)
{
/* Do Not Used */
/* Read FIFO-Buffer, copy to User-Buffer */
while ((*tmp & MASK_FIFO_VALID) != 0) {
fifoDebugCtr++;
-
+
if (((*tmp & MASK_FIFO_TYPE) >> SHIFT_FIFO_TYPE) == FIFO_TYPE_IS_HEADER) {
/* TRBNet HEADER */
if ((counter % 5) == 0) {
}
packageCtr++;
counter = 0;
-
+
/* DEBUG INFO */
if (trb_debug > 1) {
fprintf(stderr, "FIFO_%03d: 0x%08x\n",
}
} else {
/* Error: invalid buffer content, flush FIFO-BUFFER and exit */
-
+
/* DEBUG INFO */
if (trb_debug > 1) {
fprintf(stderr, "FIFO_%03d: 0x%08x\n",
fifoDebugCtr, *tmp);
}
-
+
fifo_flush(channel);
trb_errno = TRB_FIFO_INCOMPLETE_PACKAGE;
return -1;
}
} else {
/* TRBNet Data Word */
-
+
/* DEBUG INFO */
if (trb_debug > 1) {
fprintf(stderr, "FIFO_%03d: 0x%08x\n",
fifoDebugCtr, *tmp);
}
-
+
if ((trb_lazy == 0) &&
- (((*tmp & MASK_FIFO_TYPE) >> SHIFT_FIFO_TYPE) !=
+ (((*tmp & MASK_FIFO_TYPE) >> SHIFT_FIFO_TYPE) !=
(counter - 1) % 2)) {
/* Error: invalid sequence (not 0, 1, .), flush FIFO-BUFFER and exit */
fifo_flush(channel);
-1, /* sem_op: decrement semaphore by 1, i.e. lock it */
SEM_UNDO /* sem_flg: remove lock if process gets killed */
};
-
+
/* Wait for semaphore and lock it */
if (semop(semid, &sops, 1) == -1) {
trb_errno = TRB_SEMAPHORE;
/* Get FifoToggleBit-Status, needed by read32_from_FPGA ... */
fifoToggleBit = readPC() & FIFO_TOGGLE_BIT;
-
+
return 0;
}
1, /* sem_op: decrement semaphore, i.e. unlock it */
SEM_UNDO /* */
};
-
+
/* Unblock Signals */
sigprocmask(SIG_SETMASK, &blockSetOld, NULL);
-
+
/* Release semaphore */
if (semop(semid, &sops, 1) == -1) {
trb_errno = TRB_SEMAPHORE;
return -1;
}
-
+
return 0;
}
return -1;
}
- /* Get / Create semaphore */
- if ((semid = semget(sem_key, 1,
- IPC_CREAT | IPC_EXCL |
- S_IRUSR | S_IWUSR |
- S_IRGRP | S_IWGRP |
- S_IROTH | S_IWOTH)) == -1) {
+ /* Get / Create semaphore */
+ if ((semid = semget(sem_key, 1,
+ IPC_CREAT | IPC_EXCL |
+ S_IRUSR | S_IWUSR |
+ S_IRGRP | S_IWGRP |
+ S_IROTH | S_IWOTH)) == -1) {
if (errno == EEXIST) {
/* Semaphore already exist, so just open it */
if ((semid = semget(sem_key, 1, 0)) == -1) {
return -1;
}
}
-
+
/* Do we really need this, Jan?? */
com_reset();
if (trb_debug > 1) {
fprintf(stderr, "Flushing FIFO of channel# %d\n", channel);
}
-
+
if (lockPorts() == -1) return -1;
fifo_flush(channel);
-
+
if (unlockPorts() == -1) return -1;
return 0;
if (trb_debug > 0) {
fprintf(stderr, "Init_Transfer done.\n");
}
-
+
/* Build up package and start transfer */
write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
status = trb_fifo_read(3, FIFO_MODE_REG_READ, data, dsize);
if (unlockPorts() == -1) return -1;
-
+
if ((status > 0) && (status % 2 != 0)) {
trb_errno = TRB_INVALID_PKG_NUMBER;
return -1;
if (trb_debug > 0) {
fprintf(stderr, "Init_Tranfer done.\n");
}
-
+
/* Build up package and start transfer */
write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
uint32_t value)
{
int status;
-
+
trb_errno = TRB_NONE;
if (lockPorts() == -1) return -1;
-
+
/* Init transfer */
if (trb_init_transfer(3) == -1) {
unlockPorts();
}
if (lockPorts() == -1) return -1;
-
+
/* Init transfer */
if (trb_init_transfer(3) == -1) {
unlockPorts();
}
status = trb_fifo_read(3, FIFO_MODE_SET_ADDRESS, NULL, 0);
-
+
if (unlockPorts() == -1) return -1;
if (status == -1) return -1;
if (data == NULL) return -1;
if (lockPorts() == -1) return -1;
-
+
/* Init transfer IPU Channel */
if (trb_init_transfer(1) == -1) {
unlockPorts();
/* Check for replay packets (trigger) */
status = trb_fifo_read(0, FIFO_MODE_NONE, NULL, 0);
-
+
if (unlockPorts() == -1) return -1;
-
+
if (status == -1) return -1;
return 0;
/* Check for replay packets (trigger) */
status = trb_fifo_read(0, FIFO_MODE_NONE, NULL, 0);
-
+
if (unlockPorts() == -1) return -1;
if (status == -1) return -1;
int fpga_register_read(uint16_t reg_address, uint32_t* value)
{
trb_errno = TRB_NONE;
-
+
if (lockPorts() == -1) return -1;
-
+
/* DEBUG INFO */
if (trb_debug > 0) {
fprintf(stderr, "fpga_register_read started.\n");
}
-
+
read32_from_FPGA(reg_address, value);
if (unlockPorts() == -1) return -1;
int fpga_register_write(uint16_t reg_address, uint32_t value)
{
trb_errno = TRB_NONE;
-
+
if (lockPorts() == -1) return -1;
-
+
/* DEBUG INFO */
if (trb_debug > 0) {
fprintf(stderr, "fpga_register_write started.\n");
}
-
+
write32_to_FPGA(reg_address, value);
if (unlockPorts() == -1) return -1;