--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
+-- Module Version: 5.1
+--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n fifo_2x64k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 65536 -width 2 -depth 65536 -regout -no_enable -pe -1 -pf -1 -fill
+
+-- Wed Dec 27 12:32:28 2023
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity fifo_2x64k_oreg is
+ port (
+ Data: in std_logic_vector(1 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(1 downto 0);
+ WCNT: out std_logic_vector(16 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end fifo_2x64k_oreg;
+
+architecture Structure of fifo_2x64k_oreg is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal rden_i_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal rcount_14_ff: std_logic;
+ signal rcount_15_ff: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal ifcount_11: std_logic;
+ signal co4: std_logic;
+ signal ifcount_12: std_logic;
+ signal ifcount_13: std_logic;
+ signal co5: std_logic;
+ signal ifcount_14: std_logic;
+ signal ifcount_15: std_logic;
+ signal co6: std_logic;
+ signal ifcount_16: std_logic;
+ signal co8: std_logic;
+ signal cnt_con: std_logic;
+ signal co7: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal co4_1: std_logic;
+ signal co5_1: std_logic;
+ signal co6_1: std_logic;
+ signal co7_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_2: std_logic;
+ signal fcount_10: std_logic;
+ signal fcount_11: std_logic;
+ signal co5_2: std_logic;
+ signal fcount_12: std_logic;
+ signal fcount_13: std_logic;
+ signal co6_2: std_logic;
+ signal wren_i: std_logic;
+ signal fcount_14: std_logic;
+ signal fcount_15: std_logic;
+ signal co7_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_16: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co4_3: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_11: std_logic;
+ signal iwcount_12: std_logic;
+ signal iwcount_13: std_logic;
+ signal co5_3: std_logic;
+ signal wcount_12: std_logic;
+ signal wcount_13: std_logic;
+ signal iwcount_14: std_logic;
+ signal iwcount_15: std_logic;
+ signal co6_3: std_logic;
+ signal wcount_14: std_logic;
+ signal wcount_15: std_logic;
+ signal iwcount_16: std_logic;
+ signal co8_1: std_logic;
+ signal co7_3: std_logic;
+ signal wcount_16: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_4: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co3_4: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal ircount_10: std_logic;
+ signal ircount_11: std_logic;
+ signal co4_4: std_logic;
+ signal rcount_10: std_logic;
+ signal rcount_11: std_logic;
+ signal ircount_12: std_logic;
+ signal ircount_13: std_logic;
+ signal co5_4: std_logic;
+ signal rcount_12: std_logic;
+ signal rcount_13: std_logic;
+ signal ircount_14: std_logic;
+ signal ircount_15: std_logic;
+ signal co6_4: std_logic;
+ signal rcount_14: std_logic;
+ signal rcount_15: std_logic;
+ signal ircount_16: std_logic;
+ signal co8_2: std_logic;
+ signal co7_4: std_logic;
+ signal rcount_16: std_logic;
+ signal scuba_vlo: std_logic;
+ signal mdout1_3_0: std_logic;
+ signal mdout1_2_0: std_logic;
+ signal mdout1_1_0: std_logic;
+ signal mdout1_0_0: std_logic;
+ signal rcount_15_ff2: std_logic;
+ signal rcount_14_ff2: std_logic;
+ signal mdout1_3_1: std_logic;
+ signal mdout1_2_1: std_logic;
+ signal mdout1_1_1: std_logic;
+ signal mdout1_0_1: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component MUX41
+ port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
+ D3: in std_logic; SD1: in std_logic; SD2: in std_logic;
+ Z: out std_logic);
+ end component;
+ component ROM16X1A
+ generic (INITVAL : in std_logic_vector(15 downto 0));
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KC
+ generic (GSR : in String; WRITEMODE_B : in String;
+ WRITEMODE_A : in String; CSDECODE_B : in String;
+ CSDECODE_A : in String; REGMODE_B : in String;
+ REGMODE_A : in String; DATA_WIDTH_B : in Integer;
+ DATA_WIDTH_A : in Integer);
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
+ WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
+ WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_2x64k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is "";
+ attribute RESETMODE of pdp_ram_0_0_7 : label is "SYNC";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_2x64k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is "";
+ attribute RESETMODE of pdp_ram_0_1_6 : label is "SYNC";
+ attribute MEM_LPC_FILE of pdp_ram_1_0_5 : label is "fifo_2x64k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_0_5 : label is "";
+ attribute RESETMODE of pdp_ram_1_0_5 : label is "SYNC";
+ attribute MEM_LPC_FILE of pdp_ram_1_1_4 : label is "fifo_2x64k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_1_4 : label is "";
+ attribute RESETMODE of pdp_ram_1_1_4 : label is "SYNC";
+ attribute MEM_LPC_FILE of pdp_ram_2_0_3 : label is "fifo_2x64k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_0_3 : label is "";
+ attribute RESETMODE of pdp_ram_2_0_3 : label is "SYNC";
+ attribute MEM_LPC_FILE of pdp_ram_2_1_2 : label is "fifo_2x64k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_1_2 : label is "";
+ attribute RESETMODE of pdp_ram_2_1_2 : label is "SYNC";
+ attribute MEM_LPC_FILE of pdp_ram_3_0_1 : label is "fifo_2x64k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_0_1 : label is "";
+ attribute RESETMODE of pdp_ram_3_0_1 : label is "SYNC";
+ attribute MEM_LPC_FILE of pdp_ram_3_1_0 : label is "fifo_2x64k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_1_0 : label is "";
+ attribute RESETMODE of pdp_ram_3_1_0 : label is "SYNC";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t3: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_3: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t2: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_2: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ AND2_t1: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t0: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_1: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ pdp_ram_0_0_7: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>wcount_0, ADA1=>wcount_1, ADA2=>wcount_2,
+ ADA3=>wcount_3, ADA4=>wcount_4, ADA5=>wcount_5,
+ ADA6=>wcount_6, ADA7=>wcount_7, ADA8=>wcount_8,
+ ADA9=>wcount_9, ADA10=>wcount_10, ADA11=>wcount_11,
+ ADA12=>wcount_12, ADA13=>wcount_13, CEA=>wren_i, CLKA=>Clock,
+ OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wcount_14,
+ CSA1=>wcount_15, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>rcount_0, ADB1=>rcount_1, ADB2=>rcount_2,
+ ADB3=>rcount_3, ADB4=>rcount_4, ADB5=>rcount_5,
+ ADB6=>rcount_6, ADB7=>rcount_7, ADB8=>rcount_8,
+ ADB9=>rcount_9, ADB10=>rcount_10, ADB11=>rcount_11,
+ ADB12=>rcount_12, ADB13=>rcount_13, CEB=>rden_i, CLKB=>Clock,
+ OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>rcount_14,
+ CSB1=>rcount_15, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0,
+ DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open,
+ DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_0_1_6: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>wcount_0, ADA1=>wcount_1, ADA2=>wcount_2,
+ ADA3=>wcount_3, ADA4=>wcount_4, ADA5=>wcount_5,
+ ADA6=>wcount_6, ADA7=>wcount_7, ADA8=>wcount_8,
+ ADA9=>wcount_9, ADA10=>wcount_10, ADA11=>wcount_11,
+ ADA12=>wcount_12, ADA13=>wcount_13, CEA=>wren_i, CLKA=>Clock,
+ OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wcount_14,
+ CSA1=>wcount_15, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>rcount_0, ADB1=>rcount_1, ADB2=>rcount_2,
+ ADB3=>rcount_3, ADB4=>rcount_4, ADB5=>rcount_5,
+ ADB6=>rcount_6, ADB7=>rcount_7, ADB8=>rcount_8,
+ ADB9=>rcount_9, ADB10=>rcount_10, ADB11=>rcount_11,
+ ADB12=>rcount_12, ADB13=>rcount_13, CEB=>rden_i, CLKB=>Clock,
+ OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>rcount_14,
+ CSB1=>rcount_15, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_1,
+ DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open,
+ DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_1_0_5: DP16KC
+ generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>wcount_0, ADA1=>wcount_1, ADA2=>wcount_2,
+ ADA3=>wcount_3, ADA4=>wcount_4, ADA5=>wcount_5,
+ ADA6=>wcount_6, ADA7=>wcount_7, ADA8=>wcount_8,
+ ADA9=>wcount_9, ADA10=>wcount_10, ADA11=>wcount_11,
+ ADA12=>wcount_12, ADA13=>wcount_13, CEA=>wren_i, CLKA=>Clock,
+ OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wcount_14,
+ CSA1=>wcount_15, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>rcount_0, ADB1=>rcount_1, ADB2=>rcount_2,
+ ADB3=>rcount_3, ADB4=>rcount_4, ADB5=>rcount_5,
+ ADB6=>rcount_6, ADB7=>rcount_7, ADB8=>rcount_8,
+ ADB9=>rcount_9, ADB10=>rcount_10, ADB11=>rcount_11,
+ ADB12=>rcount_12, ADB13=>rcount_13, CEB=>rden_i, CLKB=>Clock,
+ OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>rcount_14,
+ CSB1=>rcount_15, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0,
+ DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open,
+ DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_1_1_4: DP16KC
+ generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>wcount_0, ADA1=>wcount_1, ADA2=>wcount_2,
+ ADA3=>wcount_3, ADA4=>wcount_4, ADA5=>wcount_5,
+ ADA6=>wcount_6, ADA7=>wcount_7, ADA8=>wcount_8,
+ ADA9=>wcount_9, ADA10=>wcount_10, ADA11=>wcount_11,
+ ADA12=>wcount_12, ADA13=>wcount_13, CEA=>wren_i, CLKA=>Clock,
+ OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wcount_14,
+ CSA1=>wcount_15, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>rcount_0, ADB1=>rcount_1, ADB2=>rcount_2,
+ ADB3=>rcount_3, ADB4=>rcount_4, ADB5=>rcount_5,
+ ADB6=>rcount_6, ADB7=>rcount_7, ADB8=>rcount_8,
+ ADB9=>rcount_9, ADB10=>rcount_10, ADB11=>rcount_11,
+ ADB12=>rcount_12, ADB13=>rcount_13, CEB=>rden_i, CLKB=>Clock,
+ OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>rcount_14,
+ CSB1=>rcount_15, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_1,
+ DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open,
+ DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_2_0_3: DP16KC
+ generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>wcount_0, ADA1=>wcount_1, ADA2=>wcount_2,
+ ADA3=>wcount_3, ADA4=>wcount_4, ADA5=>wcount_5,
+ ADA6=>wcount_6, ADA7=>wcount_7, ADA8=>wcount_8,
+ ADA9=>wcount_9, ADA10=>wcount_10, ADA11=>wcount_11,
+ ADA12=>wcount_12, ADA13=>wcount_13, CEA=>wren_i, CLKA=>Clock,
+ OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wcount_14,
+ CSA1=>wcount_15, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>rcount_0, ADB1=>rcount_1, ADB2=>rcount_2,
+ ADB3=>rcount_3, ADB4=>rcount_4, ADB5=>rcount_5,
+ ADB6=>rcount_6, ADB7=>rcount_7, ADB8=>rcount_8,
+ ADB9=>rcount_9, ADB10=>rcount_10, ADB11=>rcount_11,
+ ADB12=>rcount_12, ADB13=>rcount_13, CEB=>rden_i, CLKB=>Clock,
+ OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>rcount_14,
+ CSB1=>rcount_15, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0,
+ DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open,
+ DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_2_1_2: DP16KC
+ generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>wcount_0, ADA1=>wcount_1, ADA2=>wcount_2,
+ ADA3=>wcount_3, ADA4=>wcount_4, ADA5=>wcount_5,
+ ADA6=>wcount_6, ADA7=>wcount_7, ADA8=>wcount_8,
+ ADA9=>wcount_9, ADA10=>wcount_10, ADA11=>wcount_11,
+ ADA12=>wcount_12, ADA13=>wcount_13, CEA=>wren_i, CLKA=>Clock,
+ OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wcount_14,
+ CSA1=>wcount_15, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>rcount_0, ADB1=>rcount_1, ADB2=>rcount_2,
+ ADB3=>rcount_3, ADB4=>rcount_4, ADB5=>rcount_5,
+ ADB6=>rcount_6, ADB7=>rcount_7, ADB8=>rcount_8,
+ ADB9=>rcount_9, ADB10=>rcount_10, ADB11=>rcount_11,
+ ADB12=>rcount_12, ADB13=>rcount_13, CEB=>rden_i, CLKB=>Clock,
+ OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>rcount_14,
+ CSB1=>rcount_15, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_2_1,
+ DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open,
+ DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_3_0_1: DP16KC
+ generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>wcount_0, ADA1=>wcount_1, ADA2=>wcount_2,
+ ADA3=>wcount_3, ADA4=>wcount_4, ADA5=>wcount_5,
+ ADA6=>wcount_6, ADA7=>wcount_7, ADA8=>wcount_8,
+ ADA9=>wcount_9, ADA10=>wcount_10, ADA11=>wcount_11,
+ ADA12=>wcount_12, ADA13=>wcount_13, CEA=>wren_i, CLKA=>Clock,
+ OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wcount_14,
+ CSA1=>wcount_15, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>rcount_0, ADB1=>rcount_1, ADB2=>rcount_2,
+ ADB3=>rcount_3, ADB4=>rcount_4, ADB5=>rcount_5,
+ ADB6=>rcount_6, ADB7=>rcount_7, ADB8=>rcount_8,
+ ADB9=>rcount_9, ADB10=>rcount_10, ADB11=>rcount_11,
+ ADB12=>rcount_12, ADB13=>rcount_13, CEB=>rden_i, CLKB=>Clock,
+ OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>rcount_14,
+ CSB1=>rcount_15, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0,
+ DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open,
+ DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_3_1_0: DP16KC
+ generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>wcount_0, ADA1=>wcount_1, ADA2=>wcount_2,
+ ADA3=>wcount_3, ADA4=>wcount_4, ADA5=>wcount_5,
+ ADA6=>wcount_6, ADA7=>wcount_7, ADA8=>wcount_8,
+ ADA9=>wcount_9, ADA10=>wcount_10, ADA11=>wcount_11,
+ ADA12=>wcount_12, ADA13=>wcount_13, CEA=>wren_i, CLKA=>Clock,
+ OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wcount_14,
+ CSA1=>wcount_15, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>rcount_0, ADB1=>rcount_1, ADB2=>rcount_2,
+ ADB3=>rcount_3, ADB4=>rcount_4, ADB5=>rcount_5,
+ ADB6=>rcount_6, ADB7=>rcount_7, ADB8=>rcount_8,
+ ADB9=>rcount_9, ADB10=>rcount_10, ADB11=>rcount_11,
+ ADB12=>rcount_12, ADB13=>rcount_13, CEB=>rden_i, CLKB=>Clock,
+ OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>rcount_14,
+ CSB1=>rcount_15, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_3_1,
+ DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open,
+ DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ FF_56: FD1P3DX
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_55: FD1P3DX
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_54: FD1P3DX
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_53: FD1P3DX
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_52: FD1P3DX
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_51: FD1P3DX
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_50: FD1P3DX
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_49: FD1P3DX
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_48: FD1P3DX
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_47: FD1P3DX
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_46: FD1P3DX
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_45: FD1P3DX
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_11);
+
+ FF_44: FD1P3DX
+ port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_12);
+
+ FF_43: FD1P3DX
+ port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_13);
+
+ FF_42: FD1P3DX
+ port map (D=>ifcount_14, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_14);
+
+ FF_41: FD1P3DX
+ port map (D=>ifcount_15, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_15);
+
+ FF_40: FD1P3DX
+ port map (D=>ifcount_16, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_16);
+
+ FF_39: FD1S3BX
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_38: FD1S3DX
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_37: FD1P3DX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_0);
+
+ FF_36: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_35: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_34: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_33: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_32: FD1P3DX
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_31: FD1P3DX
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_30: FD1P3DX
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_29: FD1P3DX
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_28: FD1P3DX
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_27: FD1P3DX
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_26: FD1P3DX
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_25: FD1P3DX
+ port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_12);
+
+ FF_24: FD1P3DX
+ port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_13);
+
+ FF_23: FD1P3DX
+ port map (D=>iwcount_14, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_14);
+
+ FF_22: FD1P3DX
+ port map (D=>iwcount_15, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_15);
+
+ FF_21: FD1P3DX
+ port map (D=>iwcount_16, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_16);
+
+ FF_20: FD1P3DX
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_0);
+
+ FF_19: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_18: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_17: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_16: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_15: FD1P3DX
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_14: FD1P3DX
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_13: FD1P3DX
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_12: FD1P3DX
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_11: FD1P3DX
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_10: FD1P3DX
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_9: FD1P3DX
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_11);
+
+ FF_8: FD1P3DX
+ port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_12);
+
+ FF_7: FD1P3DX
+ port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_13);
+
+ FF_6: FD1P3DX
+ port map (D=>ircount_14, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_14);
+
+ FF_5: FD1P3DX
+ port map (D=>ircount_15, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_15);
+
+ FF_4: FD1P3DX
+ port map (D=>ircount_16, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_16);
+
+ FF_3: FD1P3DX
+ port map (D=>rcount_14, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rcount_14_ff);
+
+ FF_2: FD1P3DX
+ port map (D=>rcount_15, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rcount_15_ff);
+
+ FF_1: FD1P3DX
+ port map (D=>rcount_14_ff, SP=>scuba_vhi, CK=>Clock,
+ CD=>scuba_vlo, Q=>rcount_14_ff2);
+
+ FF_0: FD1P3DX
+ port map (D=>rcount_15_ff, SP=>scuba_vhi, CK=>Clock,
+ CD=>scuba_vlo, Q=>rcount_15_ff2);
+
+ bdcnt_bctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+
+ bdcnt_bctr_5: CB2
+ port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con,
+ CO=>co5, NC0=>ifcount_10, NC1=>ifcount_11);
+
+ bdcnt_bctr_6: CB2
+ port map (CI=>co5, PC0=>fcount_12, PC1=>fcount_13, CON=>cnt_con,
+ CO=>co6, NC0=>ifcount_12, NC1=>ifcount_13);
+
+ bdcnt_bctr_7: CB2
+ port map (CI=>co6, PC0=>fcount_14, PC1=>fcount_15, CON=>cnt_con,
+ CO=>co7, NC0=>ifcount_14, NC1=>ifcount_15);
+
+ bdcnt_bctr_8: CB2
+ port map (CI=>co7, PC0=>fcount_16, PC1=>scuba_vlo, CON=>cnt_con,
+ CO=>co8, NC0=>ifcount_16, NC1=>open);
+
+ e_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ S1=>open);
+
+ e_cmp_0: ALEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ CI=>cmp_ci, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+ e_cmp_5: ALEB2
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co4_1, LE=>co5_1);
+
+ e_cmp_6: ALEB2
+ port map (A0=>fcount_12, A1=>fcount_13, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co5_1, LE=>co6_1);
+
+ e_cmp_7: ALEB2
+ port map (A0=>fcount_14, A1=>fcount_15, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co6_1, LE=>co7_1);
+
+ e_cmp_8: ALEB2
+ port map (A0=>fcount_16, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co7_1, LE=>cmp_le_1_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ S1=>open);
+
+ g_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ S1=>open);
+
+ g_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ CI=>cmp_ci_1, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
+ CI=>co3_2, GE=>co4_2);
+
+ g_cmp_5: AGEB2
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i,
+ CI=>co4_2, GE=>co5_2);
+
+ g_cmp_6: AGEB2
+ port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i, B1=>wren_i,
+ CI=>co5_2, GE=>co6_2);
+
+ g_cmp_7: AGEB2
+ port map (A0=>fcount_14, A1=>fcount_15, B0=>wren_i, B1=>wren_i,
+ CI=>co6_2, GE=>co7_2);
+
+ g_cmp_8: AGEB2
+ port map (A0=>fcount_16, A1=>scuba_vlo, B0=>wren_i_inv,
+ B1=>scuba_vlo, CI=>co7_2, GE=>cmp_ge_d1_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ S1=>open);
+
+ w_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ S1=>open);
+
+ w_ctr_0: CU2
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_ctr_5: CU2
+ port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_3,
+ NC0=>iwcount_10, NC1=>iwcount_11);
+
+ w_ctr_6: CU2
+ port map (CI=>co5_3, PC0=>wcount_12, PC1=>wcount_13, CO=>co6_3,
+ NC0=>iwcount_12, NC1=>iwcount_13);
+
+ w_ctr_7: CU2
+ port map (CI=>co6_3, PC0=>wcount_14, PC1=>wcount_15, CO=>co7_3,
+ NC0=>iwcount_14, NC1=>iwcount_15);
+
+ w_ctr_8: CU2
+ port map (CI=>co7_3, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8_1,
+ NC0=>iwcount_16, NC1=>open);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ S1=>open);
+
+ r_ctr_0: CU2
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ r_ctr_5: CU2
+ port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_4,
+ NC0=>ircount_10, NC1=>ircount_11);
+
+ r_ctr_6: CU2
+ port map (CI=>co5_4, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_4,
+ NC0=>ircount_12, NC1=>ircount_13);
+
+ r_ctr_7: CU2
+ port map (CI=>co6_4, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_4,
+ NC0=>ircount_14, NC1=>ircount_15);
+
+ r_ctr_8: CU2
+ port map (CI=>co7_4, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_2,
+ NC0=>ircount_16, NC1=>open);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ mux_1: MUX41
+ port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
+ D3=>mdout1_3_0, SD1=>rcount_14_ff2, SD2=>rcount_15_ff2,
+ Z=>Q(0));
+
+ mux_0: MUX41
+ port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
+ D3=>mdout1_3_1, SD1=>rcount_14_ff2, SD2=>rcount_15_ff2,
+ Z=>Q(1));
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ WCNT(10) <= fcount_10;
+ WCNT(11) <= fcount_11;
+ WCNT(12) <= fcount_12;
+ WCNT(13) <= fcount_13;
+ WCNT(14) <= fcount_14;
+ WCNT(15) <= fcount_15;
+ WCNT(16) <= fcount_16;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of fifo_2x64k_oreg is
+ for Structure
+ for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+ for all:ALEB2 use entity ecp3.ALEB2(V); end for;
+ for all:AND2 use entity ecp3.AND2(V); end for;
+ for all:CU2 use entity ecp3.CU2(V); end for;
+ for all:CB2 use entity ecp3.CB2(V); end for;
+ for all:FADD2B use entity ecp3.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+ for all:INV use entity ecp3.INV(V); end for;
+ for all:MUX41 use entity ecp3.MUX41(V); end for;
+ for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:XOR2 use entity ecp3.XOR2(V); end for;
+ for all:DP16KC use entity ecp3.DP16KC(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
jspc29 / trbnet.git / commitdiff