Source TX-FIFO removed; mostly stable: when it works, it keeps on working

Observed calibration delays (clocks): x3e, x3f and x40

diff --git a/source/serdes_sync_downstream.ipx b/source/serdes_sync_downstream.ipx
index b1e45595e7807f5135e1960e3c47603b4a8f3c1a..d3573a35ed74da7a846b87c6e63b6593084af1aa 100644 (file)
--- a/source/serdes_sync_downstream.ipx
+++ b/source/serdes_sync_downstream.ipx
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 01 16 15:03:46.952" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 01 21 12:02:05.297" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
   <Package>
-               <File name="serdes_sync_downstream.lpc" type="lpc" modified="2014 01 16 15:03:44.000"/>
-               <File name="serdes_sync_downstream.pp" type="pp" modified="2014 01 16 15:03:44.000"/>
-               <File name="serdes_sync_downstream.sym" type="sym" modified="2014 01 16 15:03:44.000"/>
-               <File name="serdes_sync_downstream.tft" type="tft" modified="2014 01 16 15:02:59.000"/>
-               <File name="serdes_sync_downstream.txt" type="pcs_module" modified="2014 01 16 15:03:44.000"/>
-               <File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2014 01 16 15:02:59.000"/>
+               <File name="serdes_sync_downstream.lpc" type="lpc" modified="2014 01 21 12:02:01.000"/>
+               <File name="serdes_sync_downstream.pp" type="pp" modified="2014 01 21 12:02:01.000"/>
+               <File name="serdes_sync_downstream.sym" type="sym" modified="2014 01 21 12:02:01.000"/>
+               <File name="serdes_sync_downstream.tft" type="tft" modified="2014 01 21 12:02:01.000"/>
+               <File name="serdes_sync_downstream.txt" type="pcs_module" modified="2014 01 21 12:02:01.000"/>
+               <File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2014 01 21 12:02:01.000"/>
   </Package>
 </DiamondModule>

diff --git a/source/serdes_sync_downstream.lpc b/source/serdes_sync_downstream.lpc
index 34c8b3452d4c9825e06fa231af5db78d7d97d590..9f4ab45bace4dbfd6a95226dd669bae0d79bef33 100644 (file)
--- a/source/serdes_sync_downstream.lpc
+++ b/source/serdes_sync_downstream.lpc
@@ -16,8 +16,8 @@ CoreRevision=8.1
 ModuleName=serdes_sync_downstream
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=01/16/2014
-Time=15:03:44
+Date=01/21/2014
+Time=12:02:01
 
 [Parameters]
 Verilog=0
@@ -55,7 +55,7 @@ _tx_data_width0=8
 _tx_data_width1=8
 _tx_data_width2=8
 _tx_data_width3=8
-_tx_fifo0=ENABLED
+_tx_fifo0=DISABLED
 _tx_fifo1=ENABLED
 _tx_fifo2=ENABLED
 _tx_fifo3=ENABLED

diff --git a/source/serdes_sync_downstream.txt b/source/serdes_sync_downstream.txt
index 4432978e61796458ca8853016fbd33bd2545c696..ec77632c4cf42b6a21b4f46b5808a095da25c09a 100644 (file)
--- a/source/serdes_sync_downstream.txt
+++ b/source/serdes_sync_downstream.txt
@@ -19,7 +19,7 @@ CH0_RX_DATA_RATE        "FULL"
 CH0_TX_DATA_RATE        "FULL"
 CH0_TX_DATA_WIDTH       "8"
 CH0_RX_DATA_WIDTH        "8"
-CH0_TX_FIFO       "ENABLED"
+CH0_TX_FIFO       "DISABLED"
 CH0_RX_FIFO        "DISABLED"
 CH0_TDRV      "0"
 #CH0_TX_FICLK_RATE      200