updating template to latest version

diff --git a/code/lcd.vhd b/code/lcd.vhd
new file mode 100644 (file)
index 0000000..c033ce1
--- /dev/null
+++ b/code/lcd.vhd
@@ -0,0 +1,487 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.config.all;
+
+entity lcd is
+  port(
+    CLK   : in std_logic;
+    RESET : in std_logic;
+    
+    MOSI : out std_logic;
+    SCK  : out std_logic;
+    DC   : out std_logic;
+    CS   : out std_logic;
+    RST  : out std_logic;
+    
+    INPUT : in  std_logic_vector(511 downto 0);
+    DEBUG : out std_logic_vector( 15 downto 0)
+    
+    );
+end entity;
+
+
+
+architecture base of lcd is
+--     Font size in bytes  : 2002
+--     Font width          : 10
+--     Font height         : 16
+--     Font first char     : 0x20
+--     Font last char      : 0x7E
+type fontram_t is array (0 to 2047) of std_logic_vector(7 downto 0);
+constant fontram : fontram_t := (    
+    x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", 
+    x"00", x"00", x"00", x"00",
+    x"00", x"00", x"00", x"00", x"00", x"00", x"FF", x"33", x"FF", x"33", x"FF", x"33", x"00", x"00", x"00", x"00", 
+    x"00", x"00", x"00", x"00", x"00", x"00", x"1F", x"00", x"1F", x"00", x"1F", x"00", x"00", x"00", x"00", x"00", 
+    x"1F", x"00", x"1F", x"00", x"1F", x"00", x"00", x"00", x"00", x"32", x"20", x"3F", x"F8", x"0F", x"FE", x"02", 
+    x"26", x"32", x"A0", x"3F", x"F8", x"0F", x"7E", x"02", x"26", x"02", x"20", x"00", x"38", x"30", x"7C", x"70", 
+    x"FE", x"60", x"C6", x"60", x"FF", x"FF", x"FF", x"FF", x"06", x"63", x"06", x"3F", x"04", x"1C", x"00", x"00", 
+    x"3C", x"60", x"7E", x"38", x"42", x"1C", x"7E", x"0E", x"FE", x"3F", x"FC", x"7F", x"70", x"7E", x"38", x"42", 
+    x"1C", x"7E", x"06", x"3C", x"00", x"1E", x"00", x"3F", x"BC", x"7F", x"FE", x"71", x"FE", x"63", x"E6", x"67", 
+    x"3E", x"7F", x"1C", x"7C", x"00", x"7F", x"00", x"47", x"00", x"00", x"00", x"00", x"00", x"00", x"1F", x"00", 
+    x"1F", x"00", x"1F", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"C0", x"03", 
+    x"F0", x"0F", x"FC", x"3F", x"3E", x"7C", x"0E", x"70", x"07", x"E0", x"03", x"C0", x"03", x"C0", x"00", x"00", 
+    x"00", x"00", x"03", x"C0", x"03", x"C0", x"07", x"E0", x"0E", x"70", x"3E", x"7C", x"FC", x"3F", x"F0", x"0F", 
+    x"C0", x"03", x"00", x"00", x"18", x"00", x"98", x"00", x"D8", x"01", x"DE", x"01", x"4E", x"00", x"DE", x"01", 
+    x"D8", x"01", x"98", x"00", x"18", x"00", x"00", x"00", x"00", x"00", x"00", x"03", x"00", x"03", x"00", x"03", 
+    x"F0", x"3F", x"F0", x"3F", x"F0", x"3F", x"00", x"03", x"00", x"03", x"00", x"03", x"00", x"00", x"00", x"4E", 
+    x"00", x"7E", x"00", x"7E", x"00", x"1E", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", 
+    x"00", x"00", x"80", x"01", x"80", x"01", x"80", x"01", x"80", x"01", x"80", x"01", x"80", x"01", x"80", x"01", 
+    x"80", x"01", x"00", x"00", x"00", x"00", x"00", x"38", x"00", x"38", x"00", x"38", x"00", x"38", x"00", x"00", 
+    x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"60", x"00", x"78", x"00", x"7F", 
+    x"E0", x"1F", x"F8", x"07", x"FE", x"00", x"1E", x"00", x"06", x"00", x"00", x"00", x"F0", x"0F", x"F8", x"1F", 
+    x"FC", x"3F", x"1E", x"78", x"06", x"60", x"06", x"60", x"1E", x"78", x"FC", x"3F", x"FC", x"1F", x"F0", x"0F", 
+    x"00", x"60", x"18", x"60", x"1C", x"60", x"0C", x"60", x"FE", x"7F", x"FE", x"7F", x"FE", x"7F", x"00", x"60", 
+    x"00", x"60", x"00", x"60", x"0C", x"70", x"0E", x"78", x"06", x"7C", x"06", x"6E", x"06", x"67", x"8E", x"63", 
+    x"FE", x"61", x"FC", x"60", x"78", x"60", x"00", x"60", x"00", x"00", x"0C", x"60", x"CE", x"60", x"C6", x"60", 
+    x"C6", x"60", x"E6", x"71", x"FE", x"7F", x"BE", x"3F", x"1C", x"1E", x"00", x"00", x"00", x"06", x"80", x"07", 
+    x"C0", x"07", x"E0", x"06", x"78", x"06", x"1C", x"06", x"FE", x"7F", x"FE", x"7F", x"FE", x"7F", x"00", x"06", 
+    x"00", x"00", x"FE", x"60", x"FE", x"60", x"FE", x"60", x"C6", x"60", x"C6", x"71", x"C6", x"7F", x"86", x"3F", 
+    x"06", x"1F", x"06", x"0E", x"E0", x"0F", x"F8", x"3F", x"FC", x"3F", x"9E", x"71", x"CE", x"60", x"C6", x"60", 
+    x"C6", x"71", x"C6", x"7F", x"84", x"3F", x"00", x"1F", x"06", x"00", x"06", x"60", x"06", x"7C", x"06", x"7F", 
+    x"C6", x"1F", x"F6", x"03", x"FE", x"00", x"3E", x"00", x"0E", x"00", x"06", x"00", x"00", x"1E", x"3C", x"3F", 
+    x"7C", x"7F", x"FE", x"71", x"E6", x"61", x"C6", x"61", x"FE", x"73", x"7E", x"7F", x"3C", x"3F", x"00", x"1E", 
+    x"F8", x"00", x"FC", x"21", x"FE", x"63", x"8E", x"63", x"06", x"63", x"06", x"73", x"8E", x"79", x"FC", x"3F", 
+    x"FC", x"1F", x"F0", x"07", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"1C", x"38", x"1C", x"38", x"1C", 
+    x"38", x"1C", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"9C", x"38", x"FC", x"38", x"FC", 
+    x"38", x"3C", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"80", x"01", x"80", x"01", 
+    x"C0", x"03", x"E0", x"07", x"60", x"06", x"70", x"0E", x"30", x"0C", x"38", x"1C", x"18", x"18", x"18", x"18", 
+    x"30", x"03", x"30", x"03", x"30", x"03", x"30", x"03", x"30", x"03", x"30", x"03", x"30", x"03", x"30", x"03", 
+    x"30", x"03", x"30", x"03", x"18", x"18", x"18", x"18", x"38", x"1C", x"30", x"0C", x"70", x"0E", x"60", x"06", 
+    x"E0", x"07", x"C0", x"03", x"80", x"01", x"80", x"01", x"0E", x"00", x"0E", x"00", x"06", x"00", x"06", x"66", 
+    x"06", x"67", x"86", x"67", x"CE", x"01", x"FE", x"00", x"7C", x"00", x"3C", x"00", x"F0", x"0F", x"FC", x"3F", 
+    x"1C", x"38", x"C6", x"67", x"E2", x"4F", x"32", x"4C", x"36", x"4C", x"3E", x"6C", x"FC", x"6F", x"F8", x"0F", 
+    x"00", x"38", x"80", x"3F", x"E0", x"1F", x"FC", x"07", x"3C", x"06", x"3C", x"06", x"FC", x"07", x"E0", x"1F", 
+    x"80", x"3F", x"00", x"38", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"8C", x"31", x"8C", x"31", x"8C", x"31", 
+    x"CC", x"33", x"FC", x"3F", x"78", x"1F", x"78", x"1E", x"E0", x"07", x"F0", x"0F", x"F8", x"1F", x"38", x"1C", 
+    x"1C", x"38", x"0C", x"30", x"0C", x"30", x"0C", x"30", x"1C", x"30", x"18", x"10", x"FC", x"3F", x"FC", x"3F", 
+    x"FC", x"3F", x"0C", x"30", x"0C", x"30", x"1C", x"38", x"3C", x"3C", x"F8", x"1F", x"F8", x"0F", x"E0", x"07", 
+    x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"8C", x"31", x"8C", x"31", x"8C", x"31", x"8C", x"31", x"8C", x"31", 
+    x"0C", x"30", x"0C", x"30", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"8C", x"01", x"8C", x"01", x"8C", x"01", 
+    x"8C", x"01", x"8C", x"01", x"0C", x"00", x"0C", x"00", x"E0", x"07", x"F0", x"0F", x"F8", x"1F", x"38", x"1C", 
+    x"1C", x"38", x"0C", x"30", x"8C", x"31", x"8C", x"31", x"9C", x"3F", x"98", x"1F", x"FC", x"3F", x"FC", x"3F", 
+    x"FC", x"3F", x"80", x"01", x"80", x"01", x"80", x"01", x"80", x"01", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", 
+    x"0C", x"30", x"0C", x"30", x"0C", x"30", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"0C", x"30", x"0C", x"30", 
+    x"0C", x"30", x"00", x"00", x"00", x"00", x"00", x"30", x"0C", x"30", x"0C", x"30", x"0C", x"30", x"0C", x"38", 
+    x"FC", x"3F", x"FC", x"1F", x"FC", x"0F", x"00", x"00", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"C0", x"03", 
+    x"E0", x"07", x"78", x"0F", x"3C", x"1E", x"1C", x"3C", x"0C", x"38", x"04", x"30", x"FC", x"3F", x"FC", x"3F", 
+    x"FC", x"3F", x"00", x"30", x"00", x"30", x"00", x"30", x"00", x"30", x"00", x"30", x"00", x"30", x"00", x"00", 
+    x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"F8", x"00", x"F0", x"07", x"C0", x"07", x"E0", x"07", x"F8", x"00", 
+    x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"F8", x"00", x"F0", x"03", x"C0", x"0F", 
+    x"00", x"1F", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"E0", x"07", x"F8", x"1F", x"F8", x"1F", x"1C", x"38", 
+    x"0C", x"30", x"0C", x"30", x"1C", x"38", x"F8", x"1F", x"F8", x"1F", x"E0", x"07", x"FC", x"3F", x"FC", x"3F", 
+    x"FC", x"3F", x"8C", x"01", x"8C", x"01", x"8C", x"01", x"CC", x"01", x"FC", x"01", x"F8", x"00", x"78", x"00", 
+    x"E0", x"07", x"F8", x"0F", x"F8", x"1F", x"1C", x"38", x"0C", x"30", x"0C", x"70", x"1C", x"F8", x"F8", x"DF", 
+    x"F8", x"CF", x"E0", x"87", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"8C", x"01", x"8C", x"03", x"CC", x"07", 
+    x"FC", x"1F", x"FC", x"3E", x"78", x"38", x"00", x"30", x"78", x"18", x"F8", x"38", x"FC", x"38", x"CC", x"30", 
+    x"8C", x"31", x"8C", x"31", x"8C", x"33", x"1C", x"3F", x"18", x"1F", x"00", x"0E", x"00", x"00", x"0C", x"00", 
+    x"0C", x"00", x"0C", x"00", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"0C", x"00", x"0C", x"00", x"0C", x"00", 
+    x"FC", x"0F", x"FC", x"1F", x"FC", x"3F", x"00", x"38", x"00", x"30", x"00", x"30", x"00", x"38", x"FC", x"3F", 
+    x"FC", x"1F", x"FC", x"0F", x"0C", x"00", x"FC", x"00", x"F8", x"03", x"E0", x"1F", x"80", x"3F", x"00", x"3C", 
+    x"80", x"3F", x"E0", x"1F", x"FC", x"03", x"3C", x"00", x"00", x"00", x"FC", x"07", x"FC", x"1F", x"00", x"3F", 
+    x"C0", x"1F", x"E0", x"07", x"C0", x"1F", x"00", x"3F", x"FC", x"1F", x"FC", x"07", x"00", x"00", x"0C", x"30", 
+    x"1C", x"38", x"78", x"1E", x"E0", x"07", x"C0", x"03", x"E0", x"07", x"78", x"1E", x"1C", x"38", x"0C", x"30", 
+    x"00", x"00", x"1C", x"00", x"7C", x"00", x"F0", x"00", x"E0", x"3F", x"80", x"3F", x"E0", x"3F", x"F0", x"00", 
+    x"7C", x"00", x"1C", x"00", x"0C", x"38", x"0C", x"3C", x"0C", x"3E", x"0C", x"3F", x"8C", x"37", x"CC", x"33", 
+    x"EC", x"31", x"FC", x"30", x"7C", x"30", x"1C", x"30", x"00", x"00", x"00", x"00", x"FF", x"FF", x"FF", x"FF", 
+    x"FF", x"FF", x"03", x"C0", x"03", x"C0", x"03", x"C0", x"03", x"C0", x"00", x"00", x"00", x"00", x"07", x"00", 
+    x"1F", x"00", x"FF", x"00", x"F8", x"07", x"E0", x"1F", x"00", x"FF", x"00", x"F8", x"00", x"E0", x"00", x"00", 
+    x"00", x"00", x"03", x"C0", x"03", x"C0", x"03", x"C0", x"03", x"C0", x"FF", x"FF", x"FF", x"FF", x"FF", x"FF", 
+    x"00", x"00", x"00", x"00", x"00", x"00", x"80", x"01", x"E0", x"01", x"FC", x"00", x"1E", x"00", x"1E", x"00", 
+    x"FC", x"00", x"E0", x"01", x"80", x"01", x"00", x"00", x"00", x"C0", x"00", x"C0", x"00", x"C0", x"00", x"C0", 
+    x"00", x"C0", x"00", x"C0", x"00", x"C0", x"00", x"C0", x"00", x"C0", x"00", x"C0", x"00", x"00", x"00", x"00", 
+    x"00", x"00", x"02", x"00", x"06", x"00", x"06", x"00", x"04", x"00", x"00", x"00", x"00", x"00", x"00", x"00", 
+    x"00", x"1C", x"60", x"3E", x"70", x"3F", x"30", x"33", x"30", x"31", x"30", x"39", x"F0", x"1F", x"F0", x"3F", 
+    x"E0", x"3F", x"00", x"30", x"FE", x"3F", x"FE", x"3F", x"FE", x"3F", x"60", x"38", x"30", x"30", x"30", x"30", 
+    x"70", x"38", x"F0", x"3F", x"E0", x"1F", x"C0", x"07", x"80", x"07", x"E0", x"1F", x"E0", x"1F", x"70", x"38", 
+    x"30", x"38", x"30", x"30", x"30", x"30", x"30", x"30", x"30", x"30", x"20", x"10", x"80", x"0F", x"E0", x"1F", 
+    x"F0", x"3F", x"70", x"38", x"30", x"30", x"30", x"30", x"70", x"38", x"FE", x"3F", x"FE", x"3F", x"FE", x"3F", 
+    x"80", x"0F", x"E0", x"1F", x"E0", x"1F", x"70", x"3B", x"30", x"33", x"30", x"33", x"70", x"33", x"F0", x"33", 
+    x"E0", x"3B", x"C0", x"1B", x"60", x"00", x"60", x"00", x"60", x"00", x"FC", x"3F", x"FE", x"3F", x"FF", x"3F", 
+    x"63", x"00", x"63", x"00", x"63", x"00", x"63", x"00", x"80", x"0F", x"E0", x"4F", x"F0", x"DF", x"70", x"DC", 
+    x"30", x"D8", x"30", x"D8", x"70", x"D8", x"F0", x"FF", x"F0", x"FF", x"F0", x"7F", x"FE", x"3F", x"FE", x"3F", 
+    x"FE", x"3F", x"60", x"00", x"70", x"00", x"30", x"00", x"30", x"00", x"F0", x"3F", x"F0", x"3F", x"E0", x"3F", 
+    x"00", x"00", x"30", x"00", x"30", x"00", x"30", x"00", x"30", x"00", x"F3", x"3F", x"F3", x"3F", x"F3", x"3F", 
+    x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"60", x"30", x"E0", x"30", x"C0", x"30", x"C0", x"30", x"C0", 
+    x"F3", x"FF", x"F3", x"7F", x"F3", x"3F", x"00", x"00", x"FE", x"3F", x"FE", x"3F", x"FE", x"3F", x"80", x"07", 
+    x"E0", x"0F", x"F0", x"1F", x"70", x"3C", x"30", x"38", x"10", x"30", x"00", x"20", x"00", x"00", x"06", x"00", 
+    x"06", x"00", x"06", x"00", x"06", x"00", x"FE", x"3F", x"FE", x"3F", x"FE", x"3F", x"00", x"00", x"00", x"00", 
+    x"F0", x"3F", x"F0", x"3F", x"F0", x"3F", x"70", x"00", x"F0", x"3F", x"E0", x"3F", x"70", x"00", x"F0", x"3F", 
+    x"F0", x"3F", x"E0", x"3F", x"F0", x"3F", x"F0", x"3F", x"F0", x"3F", x"60", x"00", x"70", x"00", x"30", x"00", 
+    x"30", x"00", x"F0", x"3F", x"F0", x"3F", x"E0", x"3F", x"80", x"07", x"E0", x"1F", x"E0", x"1F", x"70", x"38", 
+    x"30", x"30", x"30", x"30", x"70", x"38", x"E0", x"1F", x"E0", x"1F", x"80", x"07", x"F0", x"FF", x"F0", x"FF", 
+    x"F0", x"FF", x"70", x"1C", x"30", x"18", x"30", x"18", x"70", x"1C", x"F0", x"1F", x"E0", x"0F", x"C0", x"07", 
+    x"80", x"07", x"E0", x"0F", x"F0", x"1F", x"70", x"1C", x"30", x"18", x"30", x"18", x"70", x"1C", x"F0", x"FF", 
+    x"F0", x"FF", x"F0", x"FF", x"00", x"00", x"F0", x"3F", x"F0", x"3F", x"F0", x"3F", x"70", x"00", x"30", x"00", 
+    x"30", x"00", x"70", x"00", x"70", x"00", x"00", x"00", x"E0", x"18", x"F0", x"39", x"F0", x"31", x"B0", x"33", 
+    x"30", x"33", x"30", x"33", x"30", x"3F", x"30", x"1E", x"00", x"1C", x"00", x"00", x"30", x"00", x"30", x"00", 
+    x"30", x"00", x"FC", x"1F", x"FC", x"3F", x"FC", x"3F", x"30", x"30", x"30", x"30", x"30", x"30", x"30", x"30", 
+    x"F0", x"1F", x"F0", x"3F", x"F0", x"3F", x"00", x"30", x"00", x"30", x"00", x"38", x"00", x"18", x"F0", x"3F", 
+    x"F0", x"3F", x"F0", x"3F", x"10", x"00", x"F0", x"00", x"F0", x"03", x"E0", x"1F", x"00", x"3F", x"00", x"3C", 
+    x"C0", x"3F", x"F0", x"0F", x"F0", x"01", x"30", x"00", x"30", x"00", x"F0", x"0F", x"E0", x"3F", x"00", x"1E", 
+    x"C0", x"03", x"C0", x"03", x"00", x"1E", x"E0", x"3F", x"F0", x"0F", x"30", x"00", x"10", x"20", x"30", x"30", 
+    x"F0", x"3C", x"F0", x"1F", x"C0", x"07", x"C0", x"0F", x"E0", x"3F", x"F0", x"3C", x"30", x"30", x"10", x"20", 
+    x"10", x"00", x"F0", x"00", x"F0", x"C3", x"E0", x"CF", x"00", x"FF", x"00", x"7F", x"C0", x"0F", x"F0", x"01", 
+    x"F0", x"00", x"10", x"00", x"30", x"30", x"30", x"38", x"30", x"3C", x"30", x"3E", x"30", x"37", x"B0", x"33", 
+    x"F0", x"31", x"F0", x"30", x"70", x"30", x"30", x"30", x"00", x"00", x"80", x"01", x"80", x"01", x"FE", x"7F", 
+    x"FF", x"FF", x"7F", x"FE", x"03", x"C0", x"03", x"C0", x"03", x"C0", x"00", x"00", x"00", x"00", x"00", x"00", 
+    x"00", x"00", x"FF", x"FF", x"FF", x"FF", x"FF", x"FF", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", 
+    x"00", x"00", x"03", x"C0", x"03", x"C0", x"03", x"C0", x"7F", x"FE", x"FF", x"FF", x"FE", x"7F", x"80", x"01", 
+    x"80", x"01", x"00", x"00", x"00", x"03", x"80", x"03", x"80", x"01", x"80", x"01", x"80", x"03", x"80", x"03", 
+    x"00", x"03", x"00", x"03", x"80", x"03", x"80", x"01", others => x"00");
+
+  type initdc_t   is array (0 to 15) of std_logic;
+  constant initdc   : initdc_t   := ('0','1','0','1','0','0','1','1','1','1','0','1','1','1','1','0');
+
+
+    
+  signal timer : unsigned(27 downto 0) := (others => '0');
+  --2**16: 2.5ms
+  --2**20: 40ms
+  
+  type state_t is (RSTIDLE, RSTRESET, RSTWAIT, RSTSELECT, 
+                   RSTCONFIG1, RSTCONFIG2, 
+                   RSTCLEAR, RSTCLEAR2, RSTFINISH, WAITSTART,
+                   WAITSTART1, TSTART, WRITEFONT, SETWINDOW,
+                   WRITEWAIT, WRITESECONDBYTE, GETNIBBLE, 
+                   GETHEX, NEXTCHAR);
+  type spistate_t is (SPIIDLE, SPISEND1, SPISEND2);
+
+  signal state     : state_t;
+  signal spistate  : spistate_t;  
+  signal spitime   : unsigned(3 downto 0);
+
+  signal cnt      : integer range 0 to 200000 := 0; --general purpose counter
+  signal datapos  : integer range 0 to 1023;      --pointer in data ROM
+  signal fontpos  : integer range 0 to 2047;      --pointer in font ROM
+  
+  signal spi_data : std_logic_vector(7 downto 0);
+  signal spi_dc   : std_logic;
+  signal spi_send : std_logic;
+  signal spi_idle : std_logic;
+  signal spi_busy : std_logic;
+  signal spi_cnt  : integer range 0 to 7 := 0;
+  signal spi_buf  : std_logic_vector(7 downto 0);
+  
+  signal poscol   : integer range 0 to 239 := 0;  --horizontal position
+  signal posrow   : integer range 0 to 19 := 0;   --vertical position in 16px steps
+  
+  signal curdata_t: std_logic_vector(7 downto 0); --output FF of data ROM
+  signal curdata  : std_logic_vector(7 downto 0); --current byte in data ROM
+  signal curfont  : std_logic_vector(7 downto 0); --curent font byte
+  signal nibble   : unsigned        (7 downto 0); --var. nibble to show
+  signal varcnt   : integer range 0 to 4  := 0;   --position within variable
+  
+  signal pixcnt   : integer range 0 to 15 := 0;   --Pixel count when plotting fonts
+  signal bytecnt  : integer range 0 to 1  := 0;   --high or low byte when plotting fonts
+  signal colcnt   : integer range 0 to 15 := 0;   --number of cols in current char
+  
+begin
+
+spi_idle <= not spi_busy and not spi_send;
+
+
+spi_fsm : process begin
+  wait until rising_edge(CLK);
+  spitime <= spitime + 1;
+  case spistate is
+    when SPIIDLE =>
+      MOSI <= '0';
+      SCK  <= '0';
+      spi_busy <= '0';
+      if spi_send = '1' then
+        spistate <= SPISEND1;
+        spi_buf  <= spi_data;
+        spi_busy <= '1';
+        spi_cnt  <= 7;
+        spitime  <= x"0";
+        DC       <= spi_dc;
+      end if;
+    when SPISEND1 =>  
+      if spitime = x"7" then
+        spistate <= SPISEND2;
+        spitime  <= x"0";
+      end if;
+      SCK      <= '0';
+      MOSI     <= spi_buf(spi_cnt);
+    when SPISEND2 =>  
+      SCK      <= '1';
+      MOSI     <= spi_buf(spi_cnt);
+      if spitime = x"7" then
+        if spi_cnt = 0 then
+          spistate <= SPIIDLE;
+        else
+          spistate <= SPISEND1;
+          spitime  <= x"0";
+          spi_cnt  <= spi_cnt - 1;
+        end if;
+      end if;
+  end case;
+  if RESET = '1' then
+    spistate <= SPIIDLE;
+  end if;
+end process;
+
+
+fsm : process begin
+  wait until rising_edge(CLK);
+  timer    <= timer + 1;
+  RST      <= '1';
+  CS       <= '0';
+  spi_send <= '0';
+  DEBUG(0)   <= '1';
+  case state is
+--------------------------------------------------------------      
+--  Reset sequence
+--------------------------------------------------------------   
+    when RSTIDLE =>
+      RST <= '1';
+      CS  <= '1';
+      if timer = x"4000000" then --2500ms
+        state <= RSTRESET;
+        timer <= (others => '0');
+      end if;  
+    when RSTRESET =>
+      RST <= '0';
+      CS  <= '1';
+      if timer = x"0300000" then --120ms
+        state <= RSTWAIT;
+        timer <= (others => '0');
+      end if;  
+    when RSTWAIT =>
+      RST <= '1';
+      CS  <= '1';
+      if timer = x"0300000" then  --120ms
+        state <= RSTSELECT;
+        timer <= (others => '0');
+      end if;  
+    when RSTSELECT =>
+      if timer = x"000000F" then  --short...
+        state <= RSTCONFIG1;
+        spi_data <= x"11";
+        spi_dc   <= '0';
+        spi_send <= '1';
+        timer <= (others => '0');
+      end if;
+    when RSTCONFIG1 =>
+      if timer = x"0200000" then --80ms
+        state <= RSTCONFIG2;
+        timer <= (others => '0');
+        datapos   <= 0;
+      end if;
+--------------------------------------------------------------      
+--  Load config & clear display
+--------------------------------------------------------------       
+    when RSTCONFIG2 =>
+      if spi_idle = '1' then
+        if datapos = 15 then
+          state <= RSTCLEAR;
+          datapos <= 0;
+        else
+          datapos <= datapos + 1;
+        end if;
+        spi_data <= curdata;
+        spi_dc   <= initdc(datapos);
+        spi_send <= '1';
+      end if;
+    when RSTCLEAR =>
+      if spi_idle = '1' then
+        cnt <= cnt + 1;
+        spi_data <= x"20";
+        spi_dc   <= '1';
+        spi_send <= '1';
+        state   <= RSTCLEAR2;
+        if cnt = 320*240*2-1 then
+          state <= RSTFINISH;
+        end if;
+      end if;
+    when RSTCLEAR2 =>
+      if spi_idle = '1' then
+        cnt <= cnt + 1;
+        spi_data <= x"8B";
+        spi_dc   <= '1';
+        spi_send <= '1';
+        state   <= RSTCLEAR;
+        if cnt = 320*240*2-1 then
+          state <= RSTFINISH;
+        end if;
+      end if;
+    when RSTFINISH =>
+      DEBUG(0)  <= '0';
+      poscol  <= 0;
+      posrow  <= 0;
+      datapos <= 32; --start of text section
+      varcnt  <= 4;  --no nibble active
+      state   <= WAITSTART;
+      
+--------------------------------------------------------------      
+--  Write text from memory
+--------------------------------------------------------------     
+    when NEXTCHAR =>
+      state <= WAITSTART1;
+      if varcnt = 0 or varcnt = 4 then
+        datapos <= datapos + 1;
+        varcnt  <= 4;
+      end if;
+    when WAITSTART1 =>
+      state <= WAITSTART;
+    when WAITSTART =>
+      state <= TSTART;
+    when TSTART =>
+      if curdata >= x"20" and curdata <= x"7E" then  --plain text
+        state   <= SETWINDOW;
+        cnt     <= 0;
+        colcnt  <= 0;
+        bytecnt <= 0;
+        varcnt  <= 4; 
+        fontpos <= (to_integer(unsigned(curdata)) - 32)*20;
+      elsif curdata(7 downto 5) = "100" then  --show a variable
+        state   <= GETNIBBLE;
+        varcnt  <= varcnt - 1;               --here: range 4..1
+        nibble  <= x"0" & unsigned(INPUT(to_integer(unsigned(curdata(4 downto 0)))*16+varcnt*4-1 downto 
+                                         to_integer(unsigned(curdata(4 downto 0)))*16+varcnt*4-4));
+      elsif curdata = x"0a" then   --line break
+        poscol  <= 0;
+        posrow  <= posrow + 1;
+        datapos <= datapos + 1;
+        state <= WAITSTART1;
+      elsif curdata = x"00" then   --end of string
+        state <= RSTFINISH;
+      else                         --error, skip
+        datapos <= datapos + 1;
+        state   <= WAITSTART1;
+      end if;
+    
+    when GETNIBBLE =>
+      state <= GETHEX;
+      if nibble < x"0a" then
+        nibble <= nibble + x"30";
+      else
+        nibble <= nibble + x"57";
+      end if;
+      
+    when GETHEX =>
+      state   <= SETWINDOW;
+      cnt     <= 0;
+      colcnt  <= 0;
+      bytecnt <= 0;
+      fontpos <= (to_integer(nibble) - 32)*20;
+    
+    when SETWINDOW =>
+      if cnt < 11 then
+        if spi_idle = '1' then
+          cnt <= cnt + 1;
+          spi_send <= '1';
+          case cnt is
+            when 0 => spi_dc <= '0'; spi_data <= x"2A";
+            when 1 => spi_dc <= '1'; spi_data <= x"00";
+            when 2 => spi_dc <= '1'; spi_data <= std_logic_vector(to_unsigned(poscol,8));
+            when 3 => spi_dc <= '1'; spi_data <= x"00";
+            when 4 => spi_dc <= '1'; spi_data <= std_logic_vector(to_unsigned(poscol,8));
+            when 5 => spi_dc <= '0'; spi_data <= x"2B";
+            when 6 => spi_dc <= '1'; spi_data <= std_logic_vector(to_unsigned(posrow/16,8));
+            when 7 => spi_dc <= '1'; spi_data <= std_logic_vector(to_unsigned(posrow*16,8));
+            when 8 => spi_dc <= '1'; spi_data <= std_logic_vector(to_unsigned((posrow*16+15)/256,8));
+            when 9 => spi_dc <= '1'; spi_data <= std_logic_vector(to_unsigned(posrow*16+15,8));
+            when 10=> spi_dc <= '0'; spi_data <= x"2C";
+          end case;
+        end if;
+      else
+        state  <= WRITEFONT;
+        spi_dc <= '1';
+        bytecnt<= 0;
+        pixcnt <= 0;
+      end if;
+
+    when WRITEWAIT =>
+      state <= WRITEFONT;
+    when WRITEFONT =>
+      if pixcnt = 8 and bytecnt = 1 and colcnt < 10 then --end of column
+        state   <= SETWINDOW;
+        cnt     <= 0;
+        poscol  <= poscol + 1;
+        colcnt  <= colcnt + 1;
+        fontpos <= fontpos + 1;
+      elsif pixcnt = 8 and bytecnt = 1 and colcnt = 10 then --end of character
+        state   <= NEXTCHAR;
+        poscol  <= poscol + 1;
+      elsif spi_idle = '1' then
+        if pixcnt < 8 then
+          state <= WRITESECONDBYTE;
+          if colcnt < 10 and curfont(pixcnt) = '1' then
+            if varcnt = 4 then
+              spi_data <= x"FD";
+            else
+              spi_data <= x"FF";
+            end if;
+          else
+            spi_data <= x"20";
+          end if;
+          spi_send <= '1';
+        else
+          state   <= WRITEWAIT;
+          fontpos <= fontpos + 1;
+          pixcnt  <= 0;
+          bytecnt <= 1;  
+        end if;
+      end if;
+    when WRITESECONDBYTE =>
+      if spi_idle = '1' then
+        spi_send <= '1';
+        pixcnt   <= pixcnt + 1;
+        if colcnt < 10 and curfont(pixcnt) = '1' then
+          if varcnt = 4 then
+            spi_data <= x"40";
+          else
+            spi_data <= x"FF";
+          end if;
+        else
+          spi_data <= x"8B";
+        end if;
+        state <= WRITEFONT;
+      end if;
+      
+      
+  end case;
+  if RESET = '1' then
+    state <= RSTIDLE;
+    datapos <= 0;
+  end if;
+end process;
+
+ram : process begin
+  wait until rising_edge(CLK);
+  curdata_t <= LCD_DATA(datapos);
+  curdata   <= curdata_t;
+  curfont   <= fontram(fontpos);
+end process;
+
+DEBUG(1) <= spi_idle;
+DEBUG(2) <= not spi_dc;
+DEBUG(3) <= not spi_send;
+DEBUG(15 downto 4) <= (others => '0');
+  
+end architecture;

diff --git a/code/trb3sc_tools.vhd b/code/trb3sc_tools.vhd
index 277584d88e6360b9af29d41e47bf8f500da71416..965bb0813906270fc54503e286b1d1f47a787103 100644 (file)
--- a/code/trb3sc_tools.vhd
+++ b/code/trb3sc_tools.vhd
@@ -26,10 +26,12 @@ entity trb3sc_tools is
     SPI_MOSI_OUT: out std_logic_vector(15 downto 0);
     SPI_MISO_IN : in  std_logic_vector(15 downto 0) := (others => '0');
     SPI_CLK_OUT : out std_logic_vector(15 downto 0);
+
+    --LCD
+    LCD_DATA_IN : in  std_logic_vector(511 downto 0) := (others => '0');
     
-    --UART
-    UART_TX     : out std_logic;
-    UART_RX     : in  std_logic := '0';
+    --HDR_IO
+    HEADER_IO   : inout std_logic_vector(10 downto 1);
     
     --ADC
     ADC_CS      : out std_logic := '0';
@@ -39,7 +41,7 @@ entity trb3sc_tools is
     
     --SED
     SED_ERROR_OUT : out std_logic;
-   
+
     --Slowcontrol
     BUS_RX     : in  CTRLBUS_RX;
     BUS_TX     : out CTRLBUS_TX;
@@ -57,6 +59,8 @@ signal busflash_tx, busspi_tx, busadc_tx, bussed_tx, busuart_tx : CTRLBUS_TX;
 
 signal spi_sdi, spi_sdo, spi_sck : std_logic;
 signal spi_cs                    : std_logic_vector(15 downto 0);
+signal lcd_cs, lcd_dc, lcd_mosi, lcd_sck, lcd_rst : std_logic;
+signal uart_rx, uart_tx          : std_logic;
 
 begin
 
@@ -134,7 +138,26 @@ begin
   busadc_tx.ack     <= '0';
   busadc_tx.data    <= (others => '0');
 
-  
+
+---------------------------------------------------------------------------
+-- ADC
+---------------------------------------------------------------------------        
+gen_lcd : if INCLUDE_LCD = 1 generate
+  THE_LCD : entity work.lcd
+    port map(
+      CLK   => CLK,
+      RESET => RESET,
+      
+      MOSI  => lcd_mosi,
+      SCK   => lcd_sck,
+      DC    => lcd_dc,
+      CS    => lcd_cs,
+      RST   => lcd_rst,
+      
+      INPUT => LCD_DATA_IN,
+      DEBUG => open
+    );
+end generate;  
 
 ---------------------------------------------------------------------------
 -- SPI
@@ -161,7 +184,7 @@ begin
     SPI_CS_OUT   <= spi_cs;
     SPI_CLK_OUT  <= (others => spi_sck);
     SPI_MOSI_OUT <= (others => spi_sdo);
-    spi_sdi      <= (ADC_MISO and not spi_cs(7)) or or_all(SPI_MISO_IN and not spi_cs and x"ff7f");
+    spi_sdi      <= (HEADER_IO(4) and not spi_cs(8)) or (ADC_MISO and not spi_cs(7)) or or_all(SPI_MISO_IN and not spi_cs and x"fe7f");
     
     ADC_CLK <= not spi_sck;
     ADC_CS  <= spi_cs(7);
@@ -182,14 +205,52 @@ begin
       port map(
         CLK       => CLK,
         RESET     => RESET,
-        UART_RX(0)   => UART_RX,
-        UART_TX(0)   => UART_TX, 
+        UART_RX(0)   => uart_rx,
+        UART_TX(0)   => uart_tx, 
         BUS_RX    => busuart_rx,
         BUS_TX    => busuart_tx
         );
   end generate;      
       
-      
-      
+---------------------------------------------------------------------------
+-- HEADER_IO
+---------------------------------------------------------------------------         
+-- 1   UART TX
+-- 2   UART RX
+-- 3   SPI MOSI
+-- 4   SPI MISO
+-- 5   SPI CLK
+-- 6   SPI CS
+-- 7   lcd_dc
+-- 8   lcd_rst
+-- 9   
+-- 10  
+-- 11  3.3V
+-- 12  3.3V
+-- 13  GND
+-- 14  GND
+
+HEADER_IO(1)  <= uart_tx;
+uart_rx       <= HEADER_IO(2);
+
+gen_lcdio : if INCLUDE_LCD = 1 generate
+  HEADER_IO(3)  <= lcd_mosi;
+  HEADER_IO(5)  <= lcd_sck;
+  HEADER_IO(6)  <= lcd_cs;
+end generate;
+gen_nolcdio : if INCLUDE_LCD = 0 generate
+  HEADER_IO(3)  <= spi_sdo;
+  -- HEADER_IO(4)  <= ;
+  HEADER_IO(5)  <= spi_sck;
+  HEADER_IO(6)  <= spi_cs;
+end generate;
+
+
+HEADER_IO(7)  <= lcd_dc;
+HEADER_IO(8)  <= lcd_rst;
+HEADER_IO(9)  <= 'Z';
+HEADER_IO(10) <= 'Z';
+
+
       
 end architecture;
\ No newline at end of file

diff --git a/pulser/config.vhd b/pulser/config.vhd
index ec818527075dd8b048cdbf958559bfd1c8a94264..5719dad584072503bd878dfd041add3c0fa5837f 100644 (file)
--- a/pulser/config.vhd
+++ b/pulser/config.vhd
@@ -24,12 +24,27 @@ package config is
 
     constant INCLUDE_UART           : integer  := c_YES;
     constant INCLUDE_SPI            : integer  := c_YES;
+    constant INCLUDE_LCD            : integer  := c_YES;
    
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
 
 
+  type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+  constant LCD_DATA : data_t := (
+      x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch
+      x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch
+      x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+      x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+      
+      x"54", x"72", x"62", x"33", x"73", x"63", x"0a", 
+      x"0a",
+      x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80",                     x"0a", 
+      x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82",                      x"81",                     x"0a",
+      others => x"00");
+
+
 ------------------------------------------------------------------------------
 --Select settings by configuration 
 ------------------------------------------------------------------------------

diff --git a/pulser/trb3sc_pulser.prj b/pulser/trb3sc_pulser.prj
index a165503e0a9bd493f9a173038287d906f0a0c5ed..a4761dbe1b129012f725cfefbfe7432df21948cb 100644 (file)
--- a/pulser/trb3sc_pulser.prj
+++ b/pulser/trb3sc_pulser.prj
@@ -107,6 +107,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
 add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"

diff --git a/pulser/trb3sc_pulser.vhd b/pulser/trb3sc_pulser.vhd
index 59e54e77cde59cb064f6e423cd4bcfa6d73085e6..06a6840341ea964540f89259c2332373fa207ed7 100644 (file)
--- a/pulser/trb3sc_pulser.vhd
+++ b/pulser/trb3sc_pulser.vhd
@@ -148,10 +148,10 @@ architecture trb3sc_arch of trb3sc_pulser is
   signal clock_select   : std_logic;
   
   signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
-  signal uart_tx, uart_rx : std_logic;
+--   signal uart_tx, uart_rx : std_logic;
 
   signal timer          : TIMERS;
-
+  signal lcd_data       : std_logic_vector(511 downto 0);
   
   attribute syn_keep of GSR_N     : signal is true;
   attribute syn_preserve of GSR_N : signal is true;  
@@ -331,9 +331,10 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
       SPI_MOSI_OUT=> spi_mosi,
       SPI_MISO_IN => spi_miso,
       SPI_CLK_OUT => spi_clk,
-      --UART
-      UART_TX     => uart_tx,
-      UART_RX     => uart_rx,
+      --Header
+      HEADER_IO   => HDR_IO,
+      --LCD
+      LCD_DATA_IN => lcd_data,
       --ADC
       ADC_CS      => ADC_CS,
       ADC_MOSI    => ADC_DIN,
@@ -348,7 +349,9 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
       DEBUG_OUT  => open
       );
 
-      
+---------------------------------------------------------------------------
+-- The part that actually does something
+---------------------------------------------------------------------------      
 THE_PULSER : entity work.pulser
   port map(
     SYSCLK     => clk_sys,
@@ -392,18 +395,15 @@ THE_PULSER : entity work.pulser
 ---------------------------------------------------------------------------
 -- I/O
 ---------------------------------------------------------------------------
-  HDR_IO(1)           <= uart_tx;
-  uart_rx             <= HDR_IO(2);
-  HDR_IO(3)           <= spi_mosi(8);
-  spi_miso(8)         <= HDR_IO(4);
-  HDR_IO(5)           <= spi_clk(8);
-  HDR_IO(6)           <= spi_cs(8);
-  HDR_IO(10 downto 7) <= (others => '0');
 
 
   RJ_IO               <= "0000";
 
   
+  lcd_data(15 downto 0)    <= timer.network_address;
+  lcd_data(47 downto 16)   <= timer.microsecond;
+  lcd_data(511 downto 48)  <= (others => '0');
+  
 ---------------------------------------------------------------------------
 -- LED
 ---------------------------------------------------------------------------
@@ -415,10 +415,6 @@ THE_PULSER : entity work.pulser
   LED_WHITE            <= led;  
   LED_SFP_GREEN        <= not med2int(0).stat_op(9) & '1';  --SFP Link Status
   LED_SFP_RED          <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1';  --SFP RX/TX
-
---   DEBUG_OUT(0)  <= pll_int_lock;
--- DEBUG_OUT(1)  <= pll_ext_lock;
--- DEBUG_OUT(2)  <= clock_select;
   
 ---------------------------------------------------------------------------
 -- Test Circuits
@@ -431,8 +427,8 @@ THE_PULSER : entity work.pulser
     end if;
   end process;  
 
-  led(0) <= time_counter(26) and time_counter(19);
-  led(1) <= time_counter(20);
+  led(0) <= time_counter(26) and time_counter(14);
+  led(1) <= not reset_i;
   
   
 TEST_LINE <= med_stat_debug(15 downto 0);

diff --git a/template/config.vhd b/template/config.vhd
index 0d7909f7ab7c81bd795d358bab30637d79d76441..2f2ec1f548353f84f9a5ca4622be7494fa0e745b 100644 (file)
--- a/template/config.vhd
+++ b/template/config.vhd
@@ -24,12 +24,27 @@ package config is
 
     constant INCLUDE_UART           : integer  := c_YES;
     constant INCLUDE_SPI            : integer  := c_YES;
+    constant INCLUDE_LCD            : integer  := c_YES;
    
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
 
 
+  type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+  constant LCD_DATA : data_t := (
+      x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch
+      x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch
+      x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+      x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+      
+      x"54", x"72", x"62", x"33", x"73", x"63", x"0a",
+      x"0a",
+      x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80",                     x"0a",                            
+      x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84",                      x"83",                     x"0a", 
+      x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82",                      x"81",                     x"0a",
+      others => x"00");
+
 ------------------------------------------------------------------------------
 --Select settings by configuration 
 ------------------------------------------------------------------------------

diff --git a/template/config_compile_frankfurt.pl b/template/config_compile_frankfurt.pl
index 19a7f88c67dce24cffe92222a4d3d070d84200d4..877b174ca534e2221ef532a6c9bf470476139995 100644 (file)
--- a/template/config_compile_frankfurt.pl
+++ b/template/config_compile_frankfurt.pl
@@ -1,9 +1,9 @@
 TOPNAME                      => "trb3sc_basic",
 lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
-lattice_path                 => '/d/jspc29/lattice/diamond/3.4_x64',
+lattice_path                 => '/d/jspc29/lattice/diamond/3.5_x64',
 synplify_path                => '/d/jspc29/lattice/synplify/J-2014.09-SP2/',
-synplify_command             => "/d/jspc29/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options",
+synplify_command             => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
 #synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
 
 nodelist_file                => 'nodelist_frankfurt.txt',

diff --git a/template/trb3sc_basic.prj b/template/trb3sc_basic.prj
index 1417925c50dc9314ed863081fc20a2d153628464..00d82b390e3c5da08fdf286ad1250d5e8bb7d400 100644 (file)
--- a/template/trb3sc_basic.prj
+++ b/template/trb3sc_basic.prj
@@ -107,6 +107,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
 add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"

diff --git a/template/trb3sc_basic.vhd b/template/trb3sc_basic.vhd
index 8ad559446d66a9ca9d3f5fcf195fb8d5f117cd5c..5f1afede001437ffd2f01bfefcca102fad371bbb 100644 (file)
--- a/template/trb3sc_basic.vhd
+++ b/template/trb3sc_basic.vhd
@@ -134,17 +134,17 @@ architecture trb3sc_arch of trb3sc_basic is
   signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx  : CTRLBUS_RX;
   signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx  : CTRLBUS_TX;
   
-  signal common_stat_reg         : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
-  signal common_ctrl_reg         : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+  signal common_stat_reg   : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+  signal common_ctrl_reg   : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
   
-  signal sed_error_i    : std_logic;
-  signal clock_select   : std_logic;
+  signal sed_error_i       : std_logic;
+  signal clock_select      : std_logic;
   
   signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
-  signal uart_tx, uart_rx : std_logic;
-
-  signal timer          : TIMERS;
+  signal uart_tx, uart_rx  : std_logic;
 
+  signal timer             : TIMERS;
+  signal lcd_data          : std_logic_vector(511 downto 0);
   
   attribute syn_keep of GSR_N     : signal is true;
   attribute syn_preserve of GSR_N : signal is true;  
@@ -322,9 +322,10 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
       SPI_MOSI_OUT=> spi_mosi,
       SPI_MISO_IN => spi_miso,
       SPI_CLK_OUT => spi_clk,
-      --UART
-      UART_TX     => uart_tx,
-      UART_RX     => uart_rx,
+      --Header
+      HEADER_IO   => HDR_IO,
+      --LCD
+      LCD_DATA_IN => lcd_data,
       --ADC
       ADC_CS      => ADC_CS,
       ADC_MOSI    => ADC_DIN,
@@ -351,19 +352,21 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
 ---------------------------------------------------------------------------
 -- I/O
 ---------------------------------------------------------------------------
-  HDR_IO(1)           <= uart_tx;
-  uart_rx             <= HDR_IO(2);
-  HDR_IO(3)           <= spi_mosi(8);
-  spi_miso(8)         <= HDR_IO(4);
-  HDR_IO(5)           <= spi_clk(8);
-  HDR_IO(6)           <= spi_cs(8);
-  HDR_IO(10 downto 7) <= (others => '0');
 
   RJ_IO               <= "0000";
   
   BACK_GPIO           <= (others => 'Z');
   BACK_LVDS           <= (others => '0');
   BACK_3V3            <= (others => 'Z');
+
+  
+---------------------------------------------------------------------------
+-- LCD Data to display
+---------------------------------------------------------------------------  
+  lcd_data(15 downto 0)    <= timer.network_address;
+  lcd_data(47 downto 16)   <= timer.microsecond;
+  lcd_data(79 downto 48)   <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32));
+  lcd_data(511 downto 80)  <= (others => '0');  
   
 ---------------------------------------------------------------------------
 -- LED
@@ -373,14 +376,11 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
   LED_ORANGE           <= debug_clock_reset(1);
   LED_RED              <= not sed_error_i;
   LED_YELLOW           <= debug_clock_reset(2);
-  LED_WHITE            <= led;  
+  LED_WHITE(0)         <= time_counter(26) and time_counter(19);  
+  LED_WHITE(1)         <= time_counter(20);
   LED_SFP_GREEN        <= not med2int(0).stat_op(9) & '1';  --SFP Link Status
   LED_SFP_RED          <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1';  --SFP RX/TX
 
---   DEBUG_OUT(0)  <= pll_int_lock;
--- DEBUG_OUT(1)  <= pll_ext_lock;
--- DEBUG_OUT(2)  <= clock_select;
-  
 ---------------------------------------------------------------------------
 -- Test Circuits
 ---------------------------------------------------------------------------
@@ -392,9 +392,6 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
     end if;
   end process;  
 
-  led(0) <= time_counter(26) and time_counter(19);
-  led(1) <= time_counter(20);
-  
   
 --   TEST_LINE <= med_stat_debug(15 downto 0);