]> jspc29.x-matter.uni-frankfurt.de Git - trbnet.git/commitdiff
for LVL1 handler, taken from ADCMv3
authorhadaq <hadaq>
Thu, 1 Jul 2010 09:18:26 +0000 (09:18 +0000)
committerhadaq <hadaq>
Thu, 1 Jul 2010 09:18:26 +0000 (09:18 +0000)
basics/pulse_stretch.vhd [new file with mode: 0755]

diff --git a/basics/pulse_stretch.vhd b/basics/pulse_stretch.vhd
new file mode 100755 (executable)
index 0000000..4b633f1
--- /dev/null
@@ -0,0 +1,62 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity pulse_stretch is\r
+port(\r
+       CLK_IN      : in    std_logic;\r
+       RESET_IN    : in    std_logic;\r
+       START_IN    : in    std_logic;\r
+       PULSE_OUT   : out   std_logic;\r
+       DEBUG_OUT   : out   std_logic_vector(15 downto 0)\r
+);\r
+end;\r
+\r
+architecture behavioral of pulse_stretch is\r
+\r
+-- normal signals\r
+signal pulse_cnt        : unsigned(3 downto 0);\r
+signal pulse_cnt_ce     : std_logic;\r
+signal pulse_x          : std_logic;\r
+signal pulse            : std_logic;\r
+\r
+begin\r
+\r
+-- Pulse length counter\r
+THE_PULSE_LENGTH_CTR: process( CLK_IN )\r
+begin\r
+       if( rising_edge(CLK_IN) ) then\r
+               if   ( RESET_IN = '1' ) then\r
+                       pulse_cnt    <= (others => '0');\r
+               elsif( pulse_cnt_ce = '1' ) then\r
+                       pulse_cnt    <= pulse_cnt + 1;\r
+               end if;\r
+       end if;\r
+end process THE_PULSE_LENGTH_CTR;\r
+\r
+pulse_cnt_ce <= '1' when ( (START_IN = '1') or (pulse_cnt /= x"0") ) else '0';\r
+\r
+pulse_x      <= '1' when ( (pulse_cnt(2) = '1') or (pulse_cnt(3) = '1') ) else '0';\r
+\r
+-- Syanchronize it\r
+THE_SYNC_PROC: process( CLK_IN )\r
+begin\r
+       if( rising_edge(CLK_IN) ) then\r
+               if( RESET_IN = '1' ) then\r
+                       pulse <= '0';\r
+               else\r
+                       pulse <= pulse_x;\r
+               end if;\r
+       end if;\r
+end process THE_SYNC_PROC;\r
+\r
+\r
+-- output signals\r
+PULSE_OUT               <= pulse;\r
+DEBUG_OUT(15 downto 4)  <= (others => '0');\r
+DEBUG_OUT(3 downto 0)   <= std_logic_vector(pulse_cnt);\r
+\r
+end behavioral;\r