moved unused files to subfolder, Jan

diff --git a/L12TrigBusInterface.vhd b/oldfiles/L12TrigBusInterface.vhd
similarity index 100%
rename from L12TrigBusInterface.vhd
rename to oldfiles/L12TrigBusInterface.vhd

diff --git a/trb_net_18_to_16_converter.vhd b/oldfiles/trb_net_18_to_16_converter.vhd
similarity index 100%
rename from trb_net_18_to_16_converter.vhd
rename to oldfiles/trb_net_18_to_16_converter.vhd

diff --git a/trb_net_55_to_18_converter.vhd b/oldfiles/trb_net_55_to_18_converter.vhd
similarity index 100%
rename from trb_net_55_to_18_converter.vhd
rename to oldfiles/trb_net_55_to_18_converter.vhd

diff --git a/trb_net_64_to_18_converter.vhd b/oldfiles/trb_net_64_to_18_converter.vhd
similarity index 100%
rename from trb_net_64_to_18_converter.vhd
rename to oldfiles/trb_net_64_to_18_converter.vhd

diff --git a/trb_net_active_api.vhd b/oldfiles/trb_net_active_api.vhd
similarity index 100%
rename from trb_net_active_api.vhd
rename to oldfiles/trb_net_active_api.vhd

diff --git a/trb_net_active_apimbuf.vhd b/oldfiles/trb_net_active_apimbuf.vhd
similarity index 100%
rename from trb_net_active_apimbuf.vhd
rename to oldfiles/trb_net_active_apimbuf.vhd

diff --git a/trb_net_apimbuf_fast_lvds.vhd b/oldfiles/trb_net_apimbuf_fast_lvds.vhd
similarity index 100%
rename from trb_net_apimbuf_fast_lvds.vhd
rename to oldfiles/trb_net_apimbuf_fast_lvds.vhd

diff --git a/trb_net_base_api.vhd b/oldfiles/trb_net_base_api.vhd
similarity index 100%
rename from trb_net_base_api.vhd
rename to oldfiles/trb_net_base_api.vhd

diff --git a/trb_net_endpoint_3ch.vhd b/oldfiles/trb_net_endpoint_3ch.vhd
similarity index 100%
rename from trb_net_endpoint_3ch.vhd
rename to oldfiles/trb_net_endpoint_3ch.vhd

diff --git a/trb_net_fanout_hub.vhd b/oldfiles/trb_net_fanout_hub.vhd
similarity index 100%
rename from trb_net_fanout_hub.vhd
rename to oldfiles/trb_net_fanout_hub.vhd

diff --git a/trb_net_ibuf.vhd b/oldfiles/trb_net_ibuf.vhd
similarity index 100%
rename from trb_net_ibuf.vhd
rename to oldfiles/trb_net_ibuf.vhd

diff --git a/trb_net_io_multiplexer.vhd b/oldfiles/trb_net_io_multiplexer.vhd
similarity index 100%
rename from trb_net_io_multiplexer.vhd
rename to oldfiles/trb_net_io_multiplexer.vhd

diff --git a/trb_net_iobuf.vhd b/oldfiles/trb_net_iobuf.vhd
similarity index 100%
rename from trb_net_iobuf.vhd
rename to oldfiles/trb_net_iobuf.vhd

diff --git a/trb_net_med_13bit_slow.vhd b/oldfiles/trb_net_med_13bit_slow.vhd
similarity index 100%
rename from trb_net_med_13bit_slow.vhd
rename to oldfiles/trb_net_med_13bit_slow.vhd

diff --git a/trb_net_med_32lvds.vhd b/oldfiles/trb_net_med_32lvds.vhd
similarity index 100%
rename from trb_net_med_32lvds.vhd
rename to oldfiles/trb_net_med_32lvds.vhd

diff --git a/trb_net_med_tlkx501.vhd b/oldfiles/trb_net_med_tlkx501.vhd
similarity index 100%
rename from trb_net_med_tlkx501.vhd
rename to oldfiles/trb_net_med_tlkx501.vhd

diff --git a/trb_net_obuf.vhd b/oldfiles/trb_net_obuf.vhd
similarity index 100%
rename from trb_net_obuf.vhd
rename to oldfiles/trb_net_obuf.vhd

diff --git a/trb_net_old_to_new.vhd b/oldfiles/trb_net_old_to_new.vhd
similarity index 100%
rename from trb_net_old_to_new.vhd
rename to oldfiles/trb_net_old_to_new.vhd

diff --git a/trb_net_passive_api.vhd b/oldfiles/trb_net_passive_api.vhd
similarity index 100%
rename from trb_net_passive_api.vhd
rename to oldfiles/trb_net_passive_api.vhd

diff --git a/trb_net_passive_apimbuf.vhd b/oldfiles/trb_net_passive_apimbuf.vhd
similarity index 100%
rename from trb_net_passive_apimbuf.vhd
rename to oldfiles/trb_net_passive_apimbuf.vhd

diff --git a/trb_net_term_ibuf.vhd b/oldfiles/trb_net_term_ibuf.vhd
similarity index 100%
rename from trb_net_term_ibuf.vhd
rename to oldfiles/trb_net_term_ibuf.vhd

diff --git a/trb_net_term_mbuf.vhd b/oldfiles/trb_net_term_mbuf.vhd
similarity index 100%
rename from trb_net_term_mbuf.vhd
rename to oldfiles/trb_net_term_mbuf.vhd

diff --git a/trb_net_trigger_reader.vhd b/oldfiles/trb_net_trigger_reader.vhd
similarity index 100%
rename from trb_net_trigger_reader.vhd
rename to oldfiles/trb_net_trigger_reader.vhd

diff --git a/trb_net_trigger_sender.vhd b/oldfiles/trb_net_trigger_sender.vhd
similarity index 100%
rename from trb_net_trigger_sender.vhd
rename to oldfiles/trb_net_trigger_sender.vhd

diff --git a/trbnetendpoint.vhd b/oldfiles/trbnetendpoint.vhd
similarity index 100%
rename from trbnetendpoint.vhd
rename to oldfiles/trbnetendpoint.vhd

diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd
index b83ebd066f8c8094be4bc3d4b0bb9c3bb9e32450..27235f24a850ef852a632f0ccb7a874253f953b5 100644 (file)
--- a/trb_net16_hub_base.vhd
+++ b/trb_net16_hub_base.vhd
@@ -1,450 +1,461 @@
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.std_logic_ARITH.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-\r
-use work.trb_net_std.all;\r
-\r
-\r
-entity trb_net16_hub_base is\r
-  generic{\r
-  --media interfaces\r
-    MII_NUMBER              : integer range 2 to 16 := 2;\r
-    MII_INIT_DEPTH          : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000";\r
-    MII_REPLY_DEPTH         : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000";\r
-  -- settings for apis\r
-    API_NUMBER              : integer range 0 to 16 := 1;\r
-    API_CHANNELS            : bit_vector(API_NUMBER*4-1 downto 0) := x"3";\r
-                                --channel, each api is connected to\r
-    API_TYPE                : bit_vector(API_NUMBER*4-1 downto 0) := x"1";\r
-    API_INIT_DEPTH          : bit_vector(API_NUMBER*4-1 downto 0) := x"1";\r
-    API_REPLY_DEPTH         : bit_vector(API_NUMBER*4-1 downto 0) := x"1";\r
-    API_FIFO_TO_INT_DEPTH   : bit_vector(API_NUMBER*4-1 downto 0) := x"1";\r
-    API_FIFO_TO_APL_DEPTH   : bit_vector(API_NUMBER*4-1 downto 0) := x"1";\r
-  --trigger reading interfaces\r
-    TRG_NUMBER              : integer range 0 to 16 := 2;\r
-    TRG_CHANNELS            : bit_vector(API_NUMBER*4-1 downto 0) := x"10";\r
-  --general settings\r
-    MUX_SECURE_MODE         : integer range 0 to 1 := 0;\r
-    MUX_WIDTH               : integer range 1 to 5 := 3;\r
-    MUX_CTRL_CHANNEL        : integer range 0 to 2**(MUX_WIDTH-1)-1 := 3;\r
-    DATA_WIDTH              : integer range 16 to 16 := 16;\r
-    NUM_WIDTH               : integer range 2 to 2 := 2\r
-    }\r
-  port {\r
-    CLK    : in std_logic;\r
-         RESET  : in std_logic;\r
-         CLK_EN : in std_logic;\r
-         \r
-    --Media interfacces\r
-    --each port is one bit bigger than actually necessary to avoid error messages\r
-       MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER downto 0);\r
-    MED_DATA_OUT      : out std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0);\r
-    MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0);\r
-    MED_READ_IN       : in  std_logic_vector (MII_NUMBER downto 0);\r
-    MED_DATAREADY_IN  : in  std_logic_vector (MII_NUMBER downto 0);\r
-    MED_DATA_IN       : in  std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0);\r
-    MED_PACKET_NUM_IN : in  std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0);\r
-    MED_READ_OUT      : out std_logic_vector (MII_NUMBER downto 0); -- buffer reads a word from media\r
-    MED_ERROR_IN      : in  std_logic_vector (MII_NUMBER*3 downto 0);\r
-    --API: interfaces\r
-    APL_DATA_IN       : in  std_logic_vector (APL_NUMBER*DATA_WIDTH downto 0);\r
-    APL_PACKET_NUM_IN : in  std_logic_vector (APL_NUMBER*NUM_WIDTH downto 0);\r
-    APL_WRITE_IN      : in  std_logic_vector (APL_NUMBER downto 0);\r
-    APL_FIFO_FULL_OUT : out std_logic_vector (APL_NUMBER downto 0);\r
-    APL_SHORT_TRANSFER_IN : in  std_logic_vector (APL_NUMBER downto 0);\r
-    APL_DTYPE_IN      : in  std_logic_vector (APL_NUMBER*4 downto 0);\r
-    APL_ERROR_PATTERN_IN : in  std_logic_vector (APL_NUMBER*32 downto 0);\r
-    APL_SEND_IN       : in  std_logic_vector (APL_NUMBER downto 0);\r
-    APL_TARGET_ADDRESS_IN : in  std_logic_vector (APL_NUMBER*16 downto 0);\r
-    APL_DATA_OUT      : out std_logic_vector (APL_NUMBER*16 downto 0);\r
-    APL_PACKET_NUM_OUT: out std_logic_vector (APL_NUMBER*NUM_WIDTH downto 0);\r
-    APL_TYP_OUT       : out std_logic_vector (APL_NUMBER*3 downto 0);\r
-    APL_DATAREADY_OUT : out std_logic_vector (APL_NUMBER downto 0);\r
-    APL_READ_IN       : in  std_logic_vector (APL_NUMBER downto 0);\r
-    APL_RUN_OUT       : out std_logic_vector (APL_NUMBER downto 0);\r
-    APL_MY_ADDRESS_IN : in  std_logic_vector (APL_NUMBRT*16 downto 0);\r
-    APL_SEQNR_OUT     : out std_logic_vector (APL_NUMBER*8 downto 0);\r
-    --TRG interfaces\r
-    TRG_GOT_TRIGGER_OUT   : out std_logic_vector (TRG_NUMBER downto 0);\r
-    TRG_ERROR_PATTERN_OUT : out std_logic_vector (TRG_NUMBER*32 downto 0);\r
-    TRG_DTYPE_OUT         : out std_logic_vector (TRG_NUMBER*4 downto 0);\r
-    TRG_SEQNR_OUT         : out std_logic_vector (TRG_NUMBER*8 downto 0);\r
-    TRG_ERROR_PATTERN_IN  : in  std_logic_vector (TRG_NUMBER*32 downto 0);\r
-    TRG_RELEASE_IN        : in  std_logic_vector (TRG_NUMBER downto 0);\r
-    --Status ports (for debugging)\r
-    HUB_CHANNEL_STAT   : out std_logic_vector (2**(MUX_WIDTH-1)*16 downto 0);\r
-    HUB_GEN_STAT       : out std_logic_vector (31 downto 0);\r
-    MPLEX_CTRL         : out std_logic_vector (MII_NUMBER*32-1 downto 0);\r
-    \r
-    }\r
-end entity;\r
-\r
-architecture trb_net16_hub_base_arch of trb_net16_hub_base is\r
-\r
-  signal m_DATAREADY_OUT : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);\r
-  signal m_DATA_OUT      : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0);\r
-  signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0);\r
-  signal m_READ_IN       : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);\r
-  signal m_DATAREADY_IN  : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);\r
-  signal m_DATA_IN       : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0);\r
-  signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0);\r
-  signal m_READ_OUT      : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);\r
-\r
-  signal hub_to_buf_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
-  signal hub_to_buf_INIT_DATA     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);\r
-  signal hub_to_buf_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);\r
-  signal hub_to_buf_INIT_READ     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
-\r
-  signal buf_to_hub_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
-  signal buf_to_hub_INIT_DATA     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);\r
-  signal buf_to_hub_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);\r
-  signal buf_to_hub_INIT_READ     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
-\r
-  signal hub_to_buf_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
-  signal hub_to_buf_REPLY_DATA     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);\r
-  signal hub_to_buf_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);\r
-  signal hub_to_buf_REPLY_READ     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
-\r
-  signal buf_to_hub_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
-  signal buf_to_hub_REPLY_DATA     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);\r
-  signal buf_to_hub_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);\r
-  signal buf_to_hub_REPLY_READ     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);  \r
-  \r
-  component trb_net16_base_hub_logic is\r
-  generic (\r
-  --media interfaces\r
-    POINT_NUMBER        : integer range 2 to 16 := 2;\r
-    INIT_DEPTH          : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111";\r
-    REPLY_DEPTH         : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111";\r
-  --general settings\r
-    DATA_WIDTH          : integer range 16 to 16 := 16;\r
-    NUM_WIDTH           : integer range 2 to 2 := 2\r
-    );\r
-  port (\r
-    CLK    : in std_logic;\r
-         RESET  : in std_logic;\r
-         CLK_EN : in std_logic;\r
-    INIT_DATAREADY_IN     : in  std_logic_vector (POINT_NUMBER downto 0);\r
-    INIT_DATA_IN          : in  std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0);\r
-    INIT_PACKET_NUM_IN    : in  std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0);\r
-    INIT_READ_OUT         : out std_logic_vector (POINT_NUMBER downto 0);\r
-    INIT_DATAREADY_OUT    : out std_logic_vector (POINT_NUMBER downto 0);\r
-    INIT_DATA_OUT         : out std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0);\r
-    INIT_PACKET_NUM_OUT   : out std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0);\r
-    INIT_READ_IN          : in  std_logic_vector (POINT_NUMBER downto 0);\r
-    REPLY_HEADER_OUT      : out std_logic_vector (POINT_NUMBER downto 0);\r
-    REPLY_DATAREADY_IN    : in  std_logic_vector (POINT_NUMBER downto 0);\r
-    REPLY_DATA_IN         : in  std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0);\r
-    REPLY_PACKET_NUM_IN   : in  std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0);\r
-    REPLY_READ_OUT        : out std_logic_vector (POINT_NUMBER downto 0);\r
-    REPLY_DATAREADY_OUT   : out std_logic_vector (POINT_NUMBER downto 0);\r
-    REPLY_DATA_OUT        : out std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0);\r
-    REPLY_PACKET_NUM_OUT  : out std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0);\r
-    REPLY_READ_IN         : in  std_logic_vector (POINT_NUMBER downto 0);\r
-    STAT_CHANNEL       : out std_logic_vector (15 downto 0);\r
-    STAT_GEN           : out std_logic_vector (31 downto 0);\r
-    CTRL_CHANNEL       : in  std_logic_vector (31 downto 0);\r
-    CTRL_GEN           : in  std_logic_vector (31 downto 0)    \r
-    );\r
-end component;\r
-\r
- \r
-  component trb_net16_io_multiplexer is\r
-    generic (\r
-      DATA_WIDTH : integer := 16;\r
-      NUM_WIDTH : integer := 2;\r
-      MUX_WIDTH : integer range 1 to 5 := 3;\r
-      MUX_SECURE_MODE : integer range 0 to 1 := 0\r
-      );\r
-    port(\r
-      --  Misc\r
-      CLK    : in std_logic;\r
-      RESET  : in std_logic;\r
-      CLK_EN : in std_logic;\r
-      --  Media direction port\r
-      MED_DATAREADY_IN:  in  std_logic;\r
-      MED_DATA_IN:       in  std_logic_vector (DATA_WIDTH-1 downto 0);\r
-      MED_PACKET_NUM_IN: in  std_logic_vector (NUM_WIDTH-1 downto 0);\r
-      MED_READ_OUT:      out std_logic;\r
-      MED_DATAREADY_OUT: out std_logic;\r
-      MED_DATA_OUT:      out std_logic_vector (DATA_WIDTH-1 downto 0);\r
-      MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0);\r
-      MED_READ_IN:       in  std_logic;\r
-      -- Internal direction port\r
-      INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);\r
-      INT_DATA_OUT:      out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);\r
-      INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);\r
-      INT_READ_IN:       in  std_logic_vector (2**MUX_WIDTH-1 downto 0);\r
-      INT_DATAREADY_IN:  in  std_logic_vector (2**MUX_WIDTH-1 downto 0);\r
-      INT_DATA_IN:       in  std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);\r
-      INT_PACKET_NUM_IN: in  std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);\r
-      INT_READ_OUT:      out std_logic_vector (2**MUX_WIDTH-1 downto 0);\r
-      -- Status and control port\r
-      CTRL:              in  std_logic_vector (31 downto 0);\r
-      STAT:              out std_logic_vector (31 downto 0)\r
-      );\r
-  end component;\r
-\r
-  component trb_net16_iobuf is\r
-    generic (\r
-      INIT_DEPTH : integer := 1;\r
-      REPLY_DEPTH : integer := 1\r
-      );\r
-    port(\r
-      --  Misc\r
-      CLK    : in std_logic;      \r
-      RESET  : in std_logic;    \r
-      CLK_EN : in std_logic;\r
-      --  Media direction port\r
-      MED_INIT_DATAREADY_OUT: out std_logic;  --Data word ready to be read out\r
-      MED_INIT_DATA_OUT:      out std_logic_vector (15 downto 0); -- Data word\r
-      MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);\r
-      MED_INIT_READ_IN:       in  std_logic; -- Media is reading\r
-      MED_INIT_DATAREADY_IN:  in  std_logic; -- Data word is offered by the Media\r
-      MED_INIT_DATA_IN:       in  std_logic_vector (15 downto 0); -- Data word\r
-      MED_INIT_PACKET_NUM_IN: in  std_logic_vector (1 downto 0);\r
-      MED_INIT_READ_OUT:      out std_logic; -- buffer reads a word from media\r
-      MED_INIT_ERROR_IN:      in  std_logic_vector (2 downto 0);  -- Status bits\r
-      MED_REPLY_DATAREADY_OUT: out std_logic;  --Data word ready to be read out\r
-      MED_REPLY_DATA_OUT:      out std_logic_vector (15 downto 0); -- Data word\r
-      MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);\r
-      MED_REPLY_READ_IN:       in  std_logic; -- Media is reading\r
-      MED_REPLY_DATAREADY_IN:  in  std_logic; -- Data word is offered by the Media\r
-      MED_REPLY_DATA_IN:       in  std_logic_vector (15 downto 0); -- Data word\r
-      MED_REPLY_PACKET_NUM_IN: in  std_logic_vector (1 downto 0);\r
-      MED_REPLY_READ_OUT:      out std_logic; -- buffer reads a word from media\r
-      MED_REPLY_ERROR_IN:      in  std_logic_vector (2 downto 0);  -- Status bits\r
-      -- Internal direction port\r
-      INT_INIT_DATAREADY_OUT: out std_logic;\r
-      INT_INIT_DATA_OUT:      out std_logic_vector (15 downto 0); -- Data word\r
-      INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);\r
-      INT_INIT_READ_IN:       in  std_logic;\r
-      INT_INIT_DATAREADY_IN:  in  std_logic;\r
-      INT_INIT_DATA_IN:       in  std_logic_vector (15 downto 0); -- Data word\r
-      INT_INIT_PACKET_NUM_IN: in  std_logic_vector (1 downto 0);\r
-      INT_INIT_READ_OUT:      out std_logic;\r
-      INT_REPLY_HEADER_IN:     in  std_logic;\r
-      INT_REPLY_DATAREADY_OUT: out std_logic;\r
-      INT_REPLY_DATA_OUT:      out std_logic_vector (15 downto 0); -- Data word\r
-      INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);\r
-      INT_REPLY_READ_IN:       in  std_logic;\r
-      INT_REPLY_DATAREADY_IN:  in  std_logic;\r
-      INT_REPLY_DATA_IN:       in  std_logic_vector (15 downto 0); -- Data word\r
-      INT_REPLY_PACKET_NUM_IN: in  std_logic_vector (1 downto 0);\r
-      INT_REPLY_READ_OUT:      out std_logic;\r
-      -- Status and control port\r
-      STAT_GEN:          out std_logic_vector (31 downto 0); -- General Status\r
-      STAT_LOCKED:       out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control\r
-      STAT_INIT_BUFFER:  out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control\r
-      STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status\r
-      CTRL_GEN:          in  std_logic_vector (31 downto 0);\r
-      CTRL_LOCKED:       in  std_logic_vector (31 downto 0);\r
-      STAT_CTRL_INIT_BUFFER:  in  std_logic_vector (31 downto 0);\r
-      STAT_CTRL_REPLY_BUFFER: in  std_logic_vector (31 downto 0)\r
-      );\r
-  end component;\r
-  \r
-  \r
-  component trb_net16_base_api is\r
-    generic (\r
-      API_TYPE : integer := API_TYPE;\r
-      FIFO_TO_INT_DEPTH : integer := 1;\r
-      FIFO_TO_APL_DEPTH : integer := 1;\r
-      FIFO_TERM_BUFFER_DEPTH  : integer := 0);\r
-    port(\r
-      --  Misc\r
-      CLK    : in std_logic;\r
-      RESET  : in std_logic;\r
-      CLK_EN : in std_logic;\r
-      -- APL Transmitter port\r
-      APL_DATA_IN           : in  std_logic_vector (15 downto 0); -- Data word "application to network"\r
-      APL_PACKET_NUM_IN     : in  std_logic_vector (1 downto 0);\r
-      APL_WRITE_IN          : in  std_logic; -- Data word is valid and should be transmitted\r
-      APL_FIFO_FULL_OUT     : out std_logic; -- Stop transfer, the fifo is full\r
-      APL_SHORT_TRANSFER_IN : in  std_logic; --\r
-      APL_DTYPE_IN          : in  std_logic_vector (3 downto 0);  -- see NewTriggerBusNetworkDescr\r
-      APL_ERROR_PATTERN_IN  : in  std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr\r
-      APL_SEND_IN           : in  std_logic; -- Release sending of the data\r
-      APL_TARGET_ADDRESS_IN : in  std_logic_vector (15 downto 0); -- Address of\r
-      -- Receiver port\r
-      APL_DATA_OUT          : out std_logic_vector (15 downto 0); -- Data word "network to application"\r
-      APL_PACKET_NUM_OUT    : out std_logic_vector (1 downto 0);\r
-      APL_TYP_OUT           : out std_logic_vector (2 downto 0);  -- Which kind of data word: DAT, HDR or TRM\r
-      APL_DATAREADY_OUT     : out std_logic; -- Data word is valid and might be read out\r
-      APL_READ_IN           : in  std_logic; -- Read data word\r
-      -- APL Control port\r
-      APL_RUN_OUT           : out std_logic; -- Data transfer is running\r
-      APL_MY_ADDRESS_IN     : in  std_logic_vector (15 downto 0);  -- My own address (temporary solution!!!)\r
-      APL_SEQNR_OUT         : out std_logic_vector (7 downto 0);\r
-      -- Internal direction port\r
-      INT_MASTER_DATAREADY_OUT  : out std_logic;\r
-      INT_MASTER_DATA_OUT       : out std_logic_vector (15 downto 0); -- Data word\r
-      INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);\r
-      INT_MASTER_READ_IN        : in  std_logic;\r
-      INT_MASTER_DATAREADY_IN   : in  std_logic;\r
-      INT_MASTER_DATA_IN        : in  std_logic_vector (15 downto 0); -- Data word\r
-      INT_MASTER_PACKET_NUM_IN  : in  std_logic_vector (1 downto 0);\r
-      INT_MASTER_READ_OUT       : out std_logic;\r
-      INT_SLAVE_HEADER_IN       : in  std_logic; -- Concentrator kindly asks to resend the last HDR\r
-      INT_SLAVE_DATAREADY_OUT   : out std_logic;\r
-      INT_SLAVE_DATA_OUT        : out std_logic_vector (15 downto 0); -- Data word\r
-      INT_SLAVE_PACKET_NUM_OUT  : out std_logic_vector (1 downto 0);\r
-      INT_SLAVE_READ_IN         : in  std_logic;\r
-      INT_SLAVE_DATAREADY_IN    : in  std_logic;\r
-      INT_SLAVE_DATA_IN         : in  std_logic_vector (15 downto 0); -- Data word\r
-      INT_SLAVE_PACKET_NUM_IN   : in  std_logic_vector (1 downto 0);\r
-      INT_SLAVE_READ_OUT        : out std_logic;\r
-      -- Status and control port\r
-      STAT_FIFO_TO_INT          : out std_logic_vector(31 downto 0);\r
-      STAT_FIFO_TO_APL          : out std_logic_vector(31 downto 0)\r
-      );\r
-  end component;\r
-  \r
-  \r
-  \r
-begin\r
-\r
---generate multiplexers\r
-  gen_muxes: for i in 0 to MII_NUMBER-1 generate\r
-    MPLEX: trb_net16_io_multiplexer\r
-      generic map (\r
-        DATA_WIDTH  => DATA_WIDTH,\r
-        NUM_WIDTH   => NUM_WIDTH,\r
-        MUX_WIDTH   => MUX_WIDTH,\r
-        MUX_SECURE_MODE => MUX_SECURE_MODE\r
-        )\r
-      port map (\r
-        CLK      => CLK,\r
-        RESET    => RESET,\r
-        CLK_EN   => CLK_EN,\r
-        MED_DATAREADY_IN   => MED_DATAREADY_IN(i*2+1 downto i*2),\r
-        MED_DATA_IN        => MED_DATA_IN((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
-        MED_PACKET_NUM_IN  => MED_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
-        MED_READ_OUT       => MED_READ_OUT(i*2+1 downto i*2),\r
-        MED_DATAREADY_OUT  => MED_DATAREADY_OUT(i*2+1 downto i*2),\r
-        MED_DATA_OUT       => MED_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
-        MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
-        MED_READ_IN        => MED_READ_IN(i*2+1 downto i*2),\r
-        INT_DATAREADY_OUT  => m_DATAREADY_IN(i*2+1 downto i*2),\r
-        INT_DATA_OUT       => m_DATA_IN((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
-        INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
-        INT_READ_IN        => m_READ_OUT(i*2+1 downto i*2),\r
-        INT_DATAREADY_IN   => m_DATAREADY_OUT(i*2+1 downto i*2),\r
-        INT_DATA_IN        => m_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
-        INT_PACKET_NUM_IN  => m_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
-        INT_READ_OUT       => m_READ_IN(i*2+1 downto i*2),\r
-        CTRL               => MPLEX_CTRL((i+1)*32-1) downto i*32)\r
-        );\r
-  end generate;\r
-\r
---generate IOBufs for MII\r
-  gen_iobufs: for i in 0 to 2**(MUX_WIDTH-1)*MII_NUMBER-1 generate\r
-    IOBUF: trb_net16_iobuf\r
-      generic map (\r
-        INIT_DEPTH =>  to_integer(MII_INIT_DEPTH((i+1)*4-1 downto i)),\r
-        REPLY_DEPTH => to_integer(MII_REPLY_DEPTH((i+1)*4-1 downto i))\r
-        )\r
-      port map (\r
-        --  Misc\r
-        CLK     => CLK ,\r
-        RESET   => RESET,\r
-        CLK_EN  => CLK_EN,\r
-        --  Media direction port\r
-        MED_INIT_DATAREADY_OUT  => m_DATAREADY_OUT(i*2),\r
-        MED_INIT_DATA_OUT       => m_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
-        MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
-        MED_INIT_READ_IN        => m_READ_IN(i*2),\r
-        \r
-        MED_INIT_DATAREADY_IN   => m_DATAREADY_IN(i*2),\r
-        MED_INIT_DATA_IN        => m_DATA_�N((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
-        MED_INIT_PACKET_NUM_IN  => m_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
-        MED_INIT_READ_OUT       => m_READ_OUT(i*2),\r
-        MED_INIT_ERROR_IN       => m_ERROR_IN((i+1)*3-1 downto i*3),\r
-\r
-        MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),\r
-        MED_REPLY_DATA_OUT      => m_DATA_OUT((i+2)*DATA_WIDTH*2-1 downto (i+1)*DATA_WIDTH*2),\r
-        MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i+2)*NUM_WIDTH*2-1 downto (i+1)*NUM_WIDTH*2),\r
-        MED_REPLY_READ_IN       => m_READ_IN(i*2+1),\r
-        \r
-        MED_REPLY_DATAREADY_IN  => m_DATAREADY_OUT(i*2+1),\r
-        MED_REPLY_DATA_IN       => m_DATA_OUT((i+2)*DATA_WIDTH*2-1 downto (i+1)*DATA_WIDTH*2),\r
-        MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_OUT((i+2)*NUM_WIDTH*2-1 downto (i+1)*NUM_WIDTH*2),\r
-        MED_REPLY_READ_OUT      => m_READ_IN(i*2+1),\r
-        MED_REPLY_ERROR_IN      => m_ERROR_IN((i+1)*3-1 downto i*3),\r
-        \r
-        -- Internal direction port\r
-\r
-        INT_INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i),\r
-        INT_INIT_DATA_OUT      => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
-        INT_INIT_PACKET_NUM_OUT=> buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
-        INT_INIT_READ_IN       => buf_to_hub_INIT_READ(i),\r
-\r
-        INT_INIT_DATAREADY_IN  => hub_to_buf_INIT_DATAREADY(i),\r
-        INT_INIT_DATA_IN       => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
-        INT_INIT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
-        INT_INIT_READ_OUT      => hub_to_buf_INIT_READ(i),\r
-        \r
-        INT_REPLY_HEADER_IN     => buf_to_hub_REPLY_SEND_HEADER(i),\r
-        INT_REPLY_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i),\r
-        INT_REPLY_DATA_OUT      => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
-        INT_REPLY_PACKET_NUM_OUT=> buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
-        INT_REPLY_READ_IN       => buf_to_hub_REPLY_READ(i),\r
-\r
-        INT_REPLY_DATAREADY_IN  => hub_to_buf_REPLY_DATAREADY(i),\r
-        INT_REPLY_DATA_IN       => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
-        INT_REPLY_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
-        INT_REPLY_READ_OUT      => hub_to_buf_REPLY_READ(i),\r
-\r
-        -- Status and control port\r
-        STAT_GEN               => IOBUF_STAT_GEN((i+1)*32 downto i*32),\r
-        STAT_LOCKED            => IOBUF_STAT_LOCKED((i+1)*32 downto i*32),\r
-        STAT_INIT_BUFFER       => IOBUF_buf_STAT_INIT_BUFFER((i+1)*32 downto i*32),\r
-        STAT_REPLY_BUFFER      => IOBUF_STAT_REPLY_BUFFER((i+1)*32 downto i*32),\r
-        CTRL_GEN               => IOBUF_CTRL_GEN((i+1)*32 downto i*32),\r
-        CTRL_LOCKED            => IOBUF_CTRL_LOCKED((i+1)*32 downto i*32),\r
-        STAT_CTRL_INIT_BUFFER  => IOBUF_STAT_CTRL_INIT_BUFFER((i+1)*32 downto i*32),\r
-        STAT_CTRL_REPLY_BUFFER => IOBUF_STAT_CTRL_REPLY_BUFFER((i+1)*32 downto i*32)\r
-        );\r
-  end generate;\r
-  \r
-  gen_hub_logic: for i in 0 to 2**(MUX_WIDTH-1)-1 generate\r
-    HUBLOGIC : trb_net16_base_hub_logic\r
-      generic map{\r
-      --media interfaces\r
-        POINT_NUMBER        => MII_NUMBER,\r
-        INIT_DEPTH          => MII_INIT_DEPTH((i+1)*4 downto i*4),\r
-        REPLY_DEPTH         => MII_REPLY_DEPTH((i+1)*4 downto i*4),\r
-      --general settings\r
-        DATA_WIDTH          => DATA_WIDTH,\r
-        NUM_WIDTH           => NUM_WIDTH\r
-        )\r
-      port map(\r
-        CLK    => CLK,\r
-         RESET  => RESET,\r
-         CLK_EN => CLK_EN,\r
-        INIT_DATAREADY_IN    => buf_to_hub_INIT_DATAREADY(i),\r
-        INIT_DATA_IN         => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
-        INIT_PACKET_NUM_IN   => buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
-        INIT_READ_OUT        => buf_to_hub_INIT_READ(i),\r
-        INIT_DATAREADY_OUT   => buf_to_hub_INIT_DATAREADY(i),\r
-        INIT_DATA_OUT        => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
-        INIT_PACKET_NUM_OUT  => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
-        INIT_READ_IN         => hub_to_buf_INIT_READ(i),\r
-        REPLY_HEADER_OUT     => hub_to_buf_REPLY_HEADER_OUT(i),\r
-        REPLY_DATAREADY_IN   => buf_to_hub_REPLY_DATAREADY(i),\r
-        REPLY_DATA_IN        => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
-        REPLY_PACKET_NUM_IN  => buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
-        REPLY_READ_OUT       => buf_to_hub_REPLY_READ(i),\r
-        REPLY_DATAREADY_OUT  => hub_to_buf_REPLY_DATAREADY(i),\r
-        REPLY_DATA_OUT       => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
-        REPLY_PACKET_NUM_OUT => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
-        REPLY_READ_IN        => hub_to_buf_REPLY_READ(i),\r
-        STAT_INTERFACE           => HUB_STAT_CHANNEL((i+1)*32-1 downto i*32),\r
-        STAT_GEN                 => HUB_STAT_GEN((i+1)*32-1 downto i*32),\r
-        CTRL_INTERFACE           => HUB_CTRL_CHANNEL((i+1)*32-1 downto i*32),\r
-        CTRL_GEN                 => HUB_CTRL_GEN((i+1)*32-1 downto i*32)\r
-        )\r
-  end generate;\r
-  \r
-end architecture;\r
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+USE IEEE.numeric_std.ALL;
+
+use work.trb_net_std.all;
+
+
+entity trb_net16_hub_base is
+  generic (
+  --general settings
+    MUX_SECURE_MODE         : integer range 0 to 1 := 0;
+    MUX_WIDTH               : integer range 1 to 5 := 3;
+    MUX_CTRL_CHANNEL        : integer range 0 to 2**(MUX_WIDTH-1)-1 := 3;
+    DATA_WIDTH              : integer range 16 to 16 := 16;
+    NUM_WIDTH               : integer range 2 to 2 := 2;
+  --media interfaces
+    MII_NUMBER              : integer range 2 to 16 := 2;
+    MII_INIT_DEPTH          : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000";
+    MII_REPLY_DEPTH         : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000";
+  -- settings for apis
+    API_NUMBER              : integer range 0 to 16 := 1;
+    API_CHANNELS            : bit_vector(API_NUMBER*4-1 downto 0) := x"3";
+                                --channel, each api is connected to
+    API_TYPE                : bit_vector(API_NUMBER*4-1 downto 0) := x"1";
+    API_INIT_DEPTH          : bit_vector(API_NUMBER*4-1 downto 0) := x"1";
+    API_REPLY_DEPTH         : bit_vector(API_NUMBER*4-1 downto 0) := x"1";
+    API_FIFO_TO_INT_DEPTH   : bit_vector(API_NUMBER*4-1 downto 0) := x"1";
+    API_FIFO_TO_APL_DEPTH   : bit_vector(API_NUMBER*4-1 downto 0) := x"1";
+  --trigger reading interfaces
+    TRG_NUMBER              : integer range 0 to 16 := 2;
+    TRG_CHANNELS            : bit_vector(API_NUMBER*4-1 downto 0) := x"10"
+    );
+  port (
+    CLK    : in std_logic;
+         RESET  : in std_logic;
+         CLK_EN : in std_logic;
+         
+    --Media interfacces
+    --each port is one bit bigger than actually necessary to avoid error messages
+       MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER downto 0);
+    MED_DATA_OUT      : out std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0);
+    MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0);
+    MED_READ_IN       : in  std_logic_vector (MII_NUMBER downto 0);
+    MED_DATAREADY_IN  : in  std_logic_vector (MII_NUMBER downto 0);
+    MED_DATA_IN       : in  std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0);
+    MED_PACKET_NUM_IN : in  std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0);
+    MED_READ_OUT      : out std_logic_vector (MII_NUMBER downto 0); -- buffer reads a word from media
+    MED_ERROR_IN      : in  std_logic_vector (MII_NUMBER*3 downto 0);
+    --API: interfaces
+    APL_DATA_IN       : in  std_logic_vector (API_NUMBER*DATA_WIDTH downto 0);
+    APL_PACKET_NUM_IN : in  std_logic_vector (API_NUMBER*NUM_WIDTH downto 0);
+    APL_WRITE_IN      : in  std_logic_vector (API_NUMBER downto 0);
+    APL_FIFO_FULL_OUT : out std_logic_vector (API_NUMBER downto 0);
+    APL_SHORT_TRANSFER_IN : in  std_logic_vector (API_NUMBER downto 0);
+    APL_DTYPE_IN      : in  std_logic_vector (API_NUMBER*4 downto 0);
+    APL_ERROR_PATTERN_IN : in  std_logic_vector (API_NUMBER*32 downto 0);
+    APL_SEND_IN       : in  std_logic_vector (API_NUMBER downto 0);
+    APL_TARGET_ADDRESS_IN : in  std_logic_vector (API_NUMBER*16 downto 0);
+    APL_DATA_OUT      : out std_logic_vector (API_NUMBER*16 downto 0);
+    APL_PACKET_NUM_OUT: out std_logic_vector (API_NUMBER*NUM_WIDTH downto 0);
+    APL_TYP_OUT       : out std_logic_vector (API_NUMBER*3 downto 0);
+    APL_DATAREADY_OUT : out std_logic_vector (API_NUMBER downto 0);
+    APL_READ_IN       : in  std_logic_vector (API_NUMBER downto 0);
+    APL_RUN_OUT       : out std_logic_vector (API_NUMBER downto 0);
+    APL_MY_ADDRESS_IN : in  std_logic_vector (API_NUMBER*16 downto 0);
+    APL_SEQNR_OUT     : out std_logic_vector (API_NUMBER*8 downto 0);
+    --TRG interfaces
+    TRG_GOT_TRIGGER_OUT   : out std_logic_vector (TRG_NUMBER downto 0);
+    TRG_ERROR_PATTERN_OUT : out std_logic_vector (TRG_NUMBER*32 downto 0);
+    TRG_DTYPE_OUT         : out std_logic_vector (TRG_NUMBER*4 downto 0);
+    TRG_SEQNR_OUT         : out std_logic_vector (TRG_NUMBER*8 downto 0);
+    TRG_ERROR_PATTERN_IN  : in  std_logic_vector (TRG_NUMBER*32 downto 0);
+    TRG_RELEASE_IN        : in  std_logic_vector (TRG_NUMBER downto 0);
+    --Status ports (for debugging)
+    HUB_STAT_CHANNEL   : out std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0);
+    HUB_STAT_GEN       : out std_logic_vector (31 downto 0);
+    HUB_CTRL_CHANNEL   : in  std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0);
+    HUB_CTRL_GEN       : in  std_logic_vector (31 downto 0);
+    MPLEX_CTRL         : in  std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0);
+    MPLEX_STAT         : out std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0);
+    IOBUF_STAT_GEN     : out std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0);
+    IOBUF_STAT_LOCKED  : out std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0);
+    IOBUF_STAT_INIT_BUFFER       : out std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0);
+    IOBUF_STAT_REPLY_BUFFER      : out std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0);
+    IOBUF_CTRL_GEN               : in  std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0);
+    IOBUF_CTRL_LOCKED            : in  std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0);
+    IOBUF_STAT_CTRL_INIT_BUFFER  : in  std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0);
+    IOBUF_STAT_CTRL_REPLY_BUFFER : in  std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0)
+    );
+end entity;
+
+architecture trb_net16_hub_base_arch of trb_net16_hub_base is
+
+  signal m_DATAREADY_OUT : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);
+  signal m_DATA_OUT      : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0);
+  signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
+  signal m_READ_IN       : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);
+  signal m_DATAREADY_IN  : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);
+  signal m_DATA_IN       : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0);
+  signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
+  signal m_READ_OUT      : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);
+  signal m_ERROR_IN      : std_logic_vector (MII_NUMBER*3*2**MUX_WIDTH-1 downto 0);
+
+  signal hub_to_buf_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);
+  signal hub_to_buf_INIT_DATA     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);
+  signal hub_to_buf_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);
+  signal hub_to_buf_INIT_READ     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);
+
+  signal buf_to_hub_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);
+  signal buf_to_hub_INIT_DATA     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);
+  signal buf_to_hub_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);
+  signal buf_to_hub_INIT_READ     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);
+
+  signal hub_to_buf_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);
+  signal hub_to_buf_REPLY_DATA     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);
+  signal hub_to_buf_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);
+  signal hub_to_buf_REPLY_READ     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);
+  signal hub_to_buf_REPLY_SEND_HEADER : std_logic_vector(2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);
+  
+  signal buf_to_hub_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);
+  signal buf_to_hub_REPLY_DATA     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);
+  signal buf_to_hub_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);
+  signal buf_to_hub_REPLY_READ     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);
+  signal buf_to_hub_REPLY_SEND_HEADER : std_logic_vector(2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);
+  
+  component trb_net16_hub_logic is
+  generic (
+  --media interfaces
+    POINT_NUMBER        : integer range 2 to 16 := 2;
+    INIT_DEPTH          : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111";
+    REPLY_DEPTH         : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111";
+  --general settings
+    DATA_WIDTH          : integer range 16 to 16 := 16;
+    NUM_WIDTH           : integer range 2 to 2 := 2
+    );
+  port (
+    CLK    : in std_logic;
+         RESET  : in std_logic;
+         CLK_EN : in std_logic;
+    INIT_DATAREADY_IN     : in  std_logic_vector (POINT_NUMBER-1 downto 0);
+    INIT_DATA_IN          : in  std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0);
+    INIT_PACKET_NUM_IN    : in  std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0);
+    INIT_READ_OUT         : out std_logic_vector (POINT_NUMBER-1 downto 0);
+    INIT_DATAREADY_OUT    : out std_logic_vector (POINT_NUMBER-1 downto 0);
+    INIT_DATA_OUT         : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0);
+    INIT_PACKET_NUM_OUT   : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0);
+    INIT_READ_IN          : in  std_logic_vector (POINT_NUMBER-1 downto 0);
+    REPLY_HEADER_OUT      : out std_logic_vector (POINT_NUMBER-1 downto 0);
+    REPLY_DATAREADY_IN    : in  std_logic_vector (POINT_NUMBER-1 downto 0);
+    REPLY_DATA_IN         : in  std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0);
+    REPLY_PACKET_NUM_IN   : in  std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0);
+    REPLY_READ_OUT        : out std_logic_vector (POINT_NUMBER-1 downto 0);
+    REPLY_DATAREADY_OUT   : out std_logic_vector (POINT_NUMBER-1 downto 0);
+    REPLY_DATA_OUT        : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0);
+    REPLY_PACKET_NUM_OUT  : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0);
+    REPLY_READ_IN         : in  std_logic_vector (POINT_NUMBER-1 downto 0);
+    STAT                  : out std_logic_vector (31 downto 0);
+    CTRL                  : in  std_logic_vector (31 downto 0)
+    );
+end component;
+
+ 
+  component trb_net16_io_multiplexer is
+    generic (
+      DATA_WIDTH : integer := 16;
+      NUM_WIDTH : integer := 2;
+      MUX_WIDTH : integer range 1 to 5 := 3;
+      MUX_SECURE_MODE : integer range 0 to 1 := 0
+      );
+    port(
+      --  Misc
+      CLK    : in std_logic;
+      RESET  : in std_logic;
+      CLK_EN : in std_logic;
+      --  Media direction port
+      MED_DATAREADY_IN:  in  std_logic;
+      MED_DATA_IN:       in  std_logic_vector (DATA_WIDTH-1 downto 0);
+      MED_PACKET_NUM_IN: in  std_logic_vector (NUM_WIDTH-1 downto 0);
+      MED_READ_OUT:      out std_logic;
+      MED_DATAREADY_OUT: out std_logic;
+      MED_DATA_OUT:      out std_logic_vector (DATA_WIDTH-1 downto 0);
+      MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0);
+      MED_READ_IN:       in  std_logic;
+      -- Internal direction port
+      INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
+      INT_DATA_OUT:      out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+      INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
+      INT_READ_IN:       in  std_logic_vector (2**MUX_WIDTH-1 downto 0);
+      INT_DATAREADY_IN:  in  std_logic_vector (2**MUX_WIDTH-1 downto 0);
+      INT_DATA_IN:       in  std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+      INT_PACKET_NUM_IN: in  std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
+      INT_READ_OUT:      out std_logic_vector (2**MUX_WIDTH-1 downto 0);
+      -- Status and control port
+      CTRL:              in  std_logic_vector (31 downto 0);
+      STAT:              out std_logic_vector (31 downto 0)
+      );
+  end component;
+
+  component trb_net16_iobuf is
+    generic (
+      INIT_DEPTH : integer := 1;
+      REPLY_DEPTH : integer := 1
+      );
+    port(
+      --  Misc
+      CLK    : in std_logic;      
+      RESET  : in std_logic;    
+      CLK_EN : in std_logic;
+      --  Media direction port
+      MED_INIT_DATAREADY_OUT: out std_logic;  --Data word ready to be read out
+      MED_INIT_DATA_OUT:      out std_logic_vector (15 downto 0); -- Data word
+      MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+      MED_INIT_READ_IN:       in  std_logic; -- Media is reading
+      MED_INIT_DATAREADY_IN:  in  std_logic; -- Data word is offered by the Media
+      MED_INIT_DATA_IN:       in  std_logic_vector (15 downto 0); -- Data word
+      MED_INIT_PACKET_NUM_IN: in  std_logic_vector (1 downto 0);
+      MED_INIT_READ_OUT:      out std_logic; -- buffer reads a word from media
+      MED_INIT_ERROR_IN:      in  std_logic_vector (2 downto 0);  -- Status bits
+      MED_REPLY_DATAREADY_OUT: out std_logic;  --Data word ready to be read out
+      MED_REPLY_DATA_OUT:      out std_logic_vector (15 downto 0); -- Data word
+      MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+      MED_REPLY_READ_IN:       in  std_logic; -- Media is reading
+      MED_REPLY_DATAREADY_IN:  in  std_logic; -- Data word is offered by the Media
+      MED_REPLY_DATA_IN:       in  std_logic_vector (15 downto 0); -- Data word
+      MED_REPLY_PACKET_NUM_IN: in  std_logic_vector (1 downto 0);
+      MED_REPLY_READ_OUT:      out std_logic; -- buffer reads a word from media
+      MED_REPLY_ERROR_IN:      in  std_logic_vector (2 downto 0);  -- Status bits
+      -- Internal direction port
+      INT_INIT_DATAREADY_OUT: out std_logic;
+      INT_INIT_DATA_OUT:      out std_logic_vector (15 downto 0); -- Data word
+      INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+      INT_INIT_READ_IN:       in  std_logic;
+      INT_INIT_DATAREADY_IN:  in  std_logic;
+      INT_INIT_DATA_IN:       in  std_logic_vector (15 downto 0); -- Data word
+      INT_INIT_PACKET_NUM_IN: in  std_logic_vector (1 downto 0);
+      INT_INIT_READ_OUT:      out std_logic;
+      INT_REPLY_HEADER_IN:     in  std_logic;
+      INT_REPLY_DATAREADY_OUT: out std_logic;
+      INT_REPLY_DATA_OUT:      out std_logic_vector (15 downto 0); -- Data word
+      INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+      INT_REPLY_READ_IN:       in  std_logic;
+      INT_REPLY_DATAREADY_IN:  in  std_logic;
+      INT_REPLY_DATA_IN:       in  std_logic_vector (15 downto 0); -- Data word
+      INT_REPLY_PACKET_NUM_IN: in  std_logic_vector (1 downto 0);
+      INT_REPLY_READ_OUT:      out std_logic;
+      -- Status and control port
+      STAT_GEN:          out std_logic_vector (31 downto 0); -- General Status
+      STAT_LOCKED:       out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+      STAT_INIT_BUFFER:  out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+      STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
+      CTRL_GEN:          in  std_logic_vector (31 downto 0);
+      CTRL_LOCKED:       in  std_logic_vector (31 downto 0);
+      STAT_CTRL_INIT_BUFFER:  in  std_logic_vector (31 downto 0);
+      STAT_CTRL_REPLY_BUFFER: in  std_logic_vector (31 downto 0)
+      );
+  end component;
+  
+  
+  component trb_net16_base_api is
+    generic (
+      API_TYPE : integer := 1;
+      FIFO_TO_INT_DEPTH : integer := 1;
+      FIFO_TO_APL_DEPTH : integer := 1;
+      FIFO_TERM_BUFFER_DEPTH  : integer := 0);
+    port(
+      --  Misc
+      CLK    : in std_logic;
+      RESET  : in std_logic;
+      CLK_EN : in std_logic;
+      -- APL Transmitter port
+      APL_DATA_IN           : in  std_logic_vector (15 downto 0); -- Data word "application to network"
+      APL_PACKET_NUM_IN     : in  std_logic_vector (1 downto 0);
+      APL_WRITE_IN          : in  std_logic; -- Data word is valid and should be transmitted
+      APL_FIFO_FULL_OUT     : out std_logic; -- Stop transfer, the fifo is full
+      APL_SHORT_TRANSFER_IN : in  std_logic; --
+      APL_DTYPE_IN          : in  std_logic_vector (3 downto 0);  -- see NewTriggerBusNetworkDescr
+      APL_ERROR_PATTERN_IN  : in  std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+      APL_SEND_IN           : in  std_logic; -- Release sending of the data
+      APL_TARGET_ADDRESS_IN : in  std_logic_vector (15 downto 0); -- Address of
+      -- Receiver port
+      APL_DATA_OUT          : out std_logic_vector (15 downto 0); -- Data word "network to application"
+      APL_PACKET_NUM_OUT    : out std_logic_vector (1 downto 0);
+      APL_TYP_OUT           : out std_logic_vector (2 downto 0);  -- Which kind of data word: DAT, HDR or TRM
+      APL_DATAREADY_OUT     : out std_logic; -- Data word is valid and might be read out
+      APL_READ_IN           : in  std_logic; -- Read data word
+      -- APL Control port
+      APL_RUN_OUT           : out std_logic; -- Data transfer is running
+      APL_MY_ADDRESS_IN     : in  std_logic_vector (15 downto 0);  -- My own address (temporary solution!!!)
+      APL_SEQNR_OUT         : out std_logic_vector (7 downto 0);
+      -- Internal direction port
+      INT_MASTER_DATAREADY_OUT  : out std_logic;
+      INT_MASTER_DATA_OUT       : out std_logic_vector (15 downto 0); -- Data word
+      INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+      INT_MASTER_READ_IN        : in  std_logic;
+      INT_MASTER_DATAREADY_IN   : in  std_logic;
+      INT_MASTER_DATA_IN        : in  std_logic_vector (15 downto 0); -- Data word
+      INT_MASTER_PACKET_NUM_IN  : in  std_logic_vector (1 downto 0);
+      INT_MASTER_READ_OUT       : out std_logic;
+      INT_SLAVE_HEADER_IN       : in  std_logic; -- Concentrator kindly asks to resend the last HDR
+      INT_SLAVE_DATAREADY_OUT   : out std_logic;
+      INT_SLAVE_DATA_OUT        : out std_logic_vector (15 downto 0); -- Data word
+      INT_SLAVE_PACKET_NUM_OUT  : out std_logic_vector (1 downto 0);
+      INT_SLAVE_READ_IN         : in  std_logic;
+      INT_SLAVE_DATAREADY_IN    : in  std_logic;
+      INT_SLAVE_DATA_IN         : in  std_logic_vector (15 downto 0); -- Data word
+      INT_SLAVE_PACKET_NUM_IN   : in  std_logic_vector (1 downto 0);
+      INT_SLAVE_READ_OUT        : out std_logic;
+      -- Status and control port
+      STAT_FIFO_TO_INT          : out std_logic_vector(31 downto 0);
+      STAT_FIFO_TO_APL          : out std_logic_vector(31 downto 0)
+      );
+  end component;
+  
+  
+  
+begin
+
+--generate multiplexers
+  gen_muxes: for i in 0 to MII_NUMBER-1 generate
+    MPLEX: trb_net16_io_multiplexer
+      generic map (
+        DATA_WIDTH  => DATA_WIDTH,
+        NUM_WIDTH   => NUM_WIDTH,
+        MUX_WIDTH   => MUX_WIDTH,
+        MUX_SECURE_MODE => MUX_SECURE_MODE
+        )
+      port map (
+        CLK      => CLK,
+        RESET    => RESET,
+        CLK_EN   => CLK_EN,
+        MED_DATAREADY_IN   => MED_DATAREADY_IN(i),
+        MED_DATA_IN        => MED_DATA_IN((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),
+        MED_PACKET_NUM_IN  => MED_PACKET_NUM_IN((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),
+        MED_READ_OUT       => MED_READ_OUT(i),
+        MED_DATAREADY_OUT  => MED_DATAREADY_OUT(i),
+        MED_DATA_OUT       => MED_DATA_OUT((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),
+        MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),
+        MED_READ_IN        => MED_READ_IN(i),
+        INT_DATAREADY_OUT  => m_DATAREADY_IN((i+1)*2**MUX_WIDTH-1 downto i*2**MUX_WIDTH),
+        INT_DATA_OUT       => m_DATA_IN((i+1)*DATA_WIDTH*2**MUX_WIDTH-1 downto i*DATA_WIDTH*2**MUX_WIDTH),
+        INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*NUM_WIDTH*2**MUX_WIDTH-1 downto i*NUM_WIDTH*2**MUX_WIDTH),
+        INT_READ_IN        => m_READ_OUT((i+1)*2**MUX_WIDTH-1 downto i*2**MUX_WIDTH),
+        INT_DATAREADY_IN   => m_DATAREADY_OUT((i+1)*2**MUX_WIDTH-1 downto i*2**MUX_WIDTH),
+        INT_DATA_IN        => m_DATA_OUT((i+1)*DATA_WIDTH*2**MUX_WIDTH-1 downto i*DATA_WIDTH*2**MUX_WIDTH),
+        INT_PACKET_NUM_IN  => m_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2**MUX_WIDTH-1 downto i*NUM_WIDTH*2**MUX_WIDTH),
+        INT_READ_OUT       => m_READ_IN((i+1)*2**MUX_WIDTH-1 downto i*2**MUX_WIDTH),
+        CTRL               => MPLEX_CTRL((i+1)*32-1 downto i*32),
+        STAT               => MPLEX_STAT((i+1)*32-1 downto i*32)
+        );
+  end generate;
+
+--generate IOBufs for MII
+  gen_iobufs: for i in 0 to 2**(MUX_WIDTH-1)*MII_NUMBER-1 generate
+    IOBUF: trb_net16_iobuf
+      generic map (
+        INIT_DEPTH =>  conv_integer(to_stdlogicvector(MII_INIT_DEPTH((i+1)*4-1 downto i*4))),
+        REPLY_DEPTH => conv_integer(to_stdlogicvector(MII_REPLY_DEPTH((i+1)*4-1 downto i*4)))
+        )
+      port map (
+        --  Misc
+        CLK     => CLK ,
+        RESET   => RESET,
+        CLK_EN  => CLK_EN,
+        --  Media direction port
+        MED_INIT_DATAREADY_OUT  => m_DATAREADY_OUT(i*2),
+        MED_INIT_DATA_OUT       => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*2*DATA_WIDTH),
+        MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*NUM_WIDTH-1 downto i*2*NUM_WIDTH),
+        MED_INIT_READ_IN        => m_READ_IN(i*2),
+        
+        MED_INIT_DATAREADY_IN   => m_DATAREADY_IN(i*2),
+        MED_INIT_DATA_IN        => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*2*DATA_WIDTH),
+        MED_INIT_PACKET_NUM_IN  => m_PACKET_NUM_IN((i*2+1)*NUM_WIDTH-1 downto i*2*NUM_WIDTH),
+        MED_INIT_READ_OUT       => m_READ_OUT(i*2),
+        MED_INIT_ERROR_IN       => m_ERROR_IN((i+1)*3-1 downto i*3),
+
+        MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),
+        MED_REPLY_DATA_OUT      => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
+        MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*NUM_WIDTH-1 downto (i*2+1)*NUM_WIDTH),
+        MED_REPLY_READ_IN       => m_READ_IN(i*2+1),
+        
+        MED_REPLY_DATAREADY_IN  => m_DATAREADY_IN(i*2+1),
+        MED_REPLY_DATA_IN       => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
+        MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN((i*2+2)*NUM_WIDTH-1 downto (i*2+1)*NUM_WIDTH),
+        MED_REPLY_READ_OUT      => m_READ_OUT(i*2+1),
+        MED_REPLY_ERROR_IN      => m_ERROR_IN((i+1)*3-1 downto i*3),
+        
+        -- Internal direction port
+
+        INT_INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i),
+        INT_INIT_DATA_OUT      => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),
+        INT_INIT_PACKET_NUM_OUT=> buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),
+        INT_INIT_READ_IN       => buf_to_hub_INIT_READ(i),
+
+        INT_INIT_DATAREADY_IN  => hub_to_buf_INIT_DATAREADY(i),
+        INT_INIT_DATA_IN       => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),
+        INT_INIT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),
+        INT_INIT_READ_OUT      => hub_to_buf_INIT_READ(i),
+        
+        INT_REPLY_HEADER_IN     => buf_to_hub_REPLY_SEND_HEADER(i),
+        INT_REPLY_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i),
+        INT_REPLY_DATA_OUT      => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),
+        INT_REPLY_PACKET_NUM_OUT=> buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),
+        INT_REPLY_READ_IN       => buf_to_hub_REPLY_READ(i),
+
+        INT_REPLY_DATAREADY_IN  => hub_to_buf_REPLY_DATAREADY(i),
+        INT_REPLY_DATA_IN       => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),
+        INT_REPLY_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),
+        INT_REPLY_READ_OUT      => hub_to_buf_REPLY_READ(i),
+
+        -- Status and control port
+        STAT_GEN               => IOBUF_STAT_GEN((i+1)*32-1 downto i*32),
+        STAT_LOCKED            => IOBUF_STAT_LOCKED((i+1)*32-1 downto i*32),
+        STAT_INIT_BUFFER       => IOBUF_STAT_INIT_BUFFER((i+1)*32-1 downto i*32),
+        STAT_REPLY_BUFFER      => IOBUF_STAT_REPLY_BUFFER((i+1)*32-1 downto i*32),
+        CTRL_GEN               => IOBUF_CTRL_GEN((i+1)*32-1 downto i*32),
+        CTRL_LOCKED            => IOBUF_CTRL_LOCKED((i+1)*32-1 downto i*32),
+        STAT_CTRL_INIT_BUFFER  => IOBUF_STAT_CTRL_INIT_BUFFER((i+1)*32-1 downto i*32),
+        STAT_CTRL_REPLY_BUFFER => IOBUF_STAT_CTRL_REPLY_BUFFER((i+1)*32-1 downto i*32)
+        );
+  end generate;
+  
+  gen_hub_logic: for i in 0 to 2**(MUX_WIDTH-1)-1 generate
+    HUBLOGIC : trb_net16_hub_logic
+      generic map (
+      --media interfaces
+        POINT_NUMBER        => MII_NUMBER,
+        INIT_DEPTH          => MII_INIT_DEPTH((i+1)*4 downto i*4),
+        REPLY_DEPTH         => MII_REPLY_DEPTH((i+1)*4 downto i*4),
+      --general settings
+        DATA_WIDTH          => DATA_WIDTH,
+        NUM_WIDTH           => NUM_WIDTH
+        )
+      port map(
+        CLK    => CLK,
+        RESET  => RESET,
+        CLK_EN => CLK_EN,
+        INIT_DATAREADY_IN    => buf_to_hub_INIT_DATAREADY((i+1)*MII_NUMBER-1 downto i*MII_NUMBER),
+        INIT_DATA_IN         => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH*MII_NUMBER-1 downto i*DATA_WIDTH*MII_NUMBER),
+        INIT_PACKET_NUM_IN   => buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH*MII_NUMBER-1 downto i*NUM_WIDTH*MII_NUMBER),
+        INIT_READ_OUT        => buf_to_hub_INIT_READ((i+1)*MII_NUMBER-1 downto i*MII_NUMBER),
+        INIT_DATAREADY_OUT   => hub_to_buf_INIT_DATAREADY((i+1)*MII_NUMBER-1 downto i*MII_NUMBER),
+        INIT_DATA_OUT        => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH*MII_NUMBER-1 downto i*DATA_WIDTH*MII_NUMBER),
+        INIT_PACKET_NUM_OUT  => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH*MII_NUMBER-1 downto i*NUM_WIDTH*MII_NUMBER),
+        INIT_READ_IN         => hub_to_buf_INIT_READ((i+1)*MII_NUMBER-1 downto i*MII_NUMBER),
+        REPLY_HEADER_OUT     => hub_to_buf_REPLY_SEND_HEADER((i+1)*MII_NUMBER-1 downto i*MII_NUMBER),
+        REPLY_DATAREADY_IN   => buf_to_hub_REPLY_DATAREADY((i+1)*MII_NUMBER-1 downto i*MII_NUMBER),
+        REPLY_DATA_IN        => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH*MII_NUMBER-1 downto i*DATA_WIDTH*MII_NUMBER),
+        REPLY_PACKET_NUM_IN  => buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH*MII_NUMBER-1 downto i*NUM_WIDTH*MII_NUMBER),
+        REPLY_READ_OUT       => buf_to_hub_REPLY_READ((i+1)*MII_NUMBER-1 downto i*MII_NUMBER),
+        REPLY_DATAREADY_OUT  => hub_to_buf_REPLY_DATAREADY((i+1)*MII_NUMBER-1 downto i*MII_NUMBER),
+        REPLY_DATA_OUT       => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH*MII_NUMBER-1 downto i*DATA_WIDTH*MII_NUMBER),
+        REPLY_PACKET_NUM_OUT => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH*MII_NUMBER-1 downto i*NUM_WIDTH*MII_NUMBER),
+        REPLY_READ_IN        => hub_to_buf_REPLY_READ((i+1)*MII_NUMBER-1 downto i*MII_NUMBER*MII_NUMBER),
+        STAT                 => HUB_STAT_CHANNEL((i+1)*32-1 downto i*32),
+        CTRL                 => HUB_CTRL_CHANNEL((i+1)*32-1 downto i*32)
+        );
+  end generate;
+  
+end architecture;

diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd
index 9211b7014fc3ea478c7cee6069113ff68566e585..42641c744476e3f6487ef4e927c5ce979f45cec6 100644 (file)
--- a/trb_net16_hub_logic.vhd
+++ b/trb_net16_hub_logic.vhd
@@ -9,7 +9,7 @@ use work.trb_net_std.all;
 entity trb_net16_hub_logic is\r
   generic (\r
   --media interfaces\r
-    POINT_NUMBER        : integer range 2 to 16 := 2;\r
+    POINT_NUMBER        : integer range 2 to 16 := 10;\r
     INIT_DEPTH          : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111";\r
     REPLY_DEPTH         : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111";\r
   --general settings\r
@@ -18,90 +18,162 @@ entity trb_net16_hub_logic is
     );\r
   port (\r
     CLK    : in std_logic;\r
-         RESET  : in std_logic;\r
-         CLK_EN : in std_logic;\r
+    RESET  : in std_logic;\r
+    CLK_EN : in std_logic;\r
     --Internal interfaccs to IOBufs\r
-    INIT_DATAREADY_IN     : in  std_logic_vector (PONUMBER downto 0);\r
-    INIT_DATA_IN          : in  std_logic_vector (DATA_WIDTH*PONUMBER downto 0);\r
-    INIT_PACKET_NUM_IN    : in  std_logic_vector (NUM_WIDTH*PONUMBER downto 0);\r
-    INIT_READ_OUT         : out std_logic_vector (PONUMBER downto 0);\r
-    INIT_DATAREADY_OUT    : out std_logic_vector (PONUMBER downto 0);\r
-    INIT_DATA_OUT         : out std_logic_vector (DATA_WIDTH*PONUMBER downto 0);\r
-    INIT_PACKET_NUM_OUT   : out std_logic_vector (NUM_WIDTH*PONUMBER downto 0);\r
-    INIT_READ_IN          : in  std_logic_vector (PONUMBER downto 0);\r
-    REPLY_HEADER_OUT      : out std_logic_vector (PONUMBER downto 0);\r
-    REPLY_DATAREADY_IN    : in  std_logic_vector (PONUMBER downto 0);\r
-    REPLY_DATA_IN         : in  std_logic_vector (DATA_WIDTH*PONUMBER downto 0);\r
-    REPLY_PACKET_NUM_IN   : in  std_logic_vector (NUM_WIDTH*PONUMBER downto 0);\r
-    REPLY_READ_OUT        : out std_logic_vector (PONUMBER downto 0);\r
-    REPLY_DATAREADY_OUT   : out std_logic_vector (PONUMBER downto 0);\r
-    REPLY_DATA_OUT        : out std_logic_vector (DATA_WIDTH*PONUMBER downto 0);\r
-    REPLY_PACKET_NUM_OUT  : out std_logic_vector (NUM_WIDTH*PONUMBER downto 0);\r
-    REPLY_READ_IN         : in  std_logic_vector (PONUMBER downto 0);\r
+    INIT_DATAREADY_IN     : in  std_logic_vector (POINT_NUMBER-1 downto 0);\r
+    INIT_DATA_IN          : in  std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0);\r
+    INIT_PACKET_NUM_IN    : in  std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0);\r
+    INIT_READ_OUT         : out std_logic_vector (POINT_NUMBER-1 downto 0);\r
+    INIT_DATAREADY_OUT    : out std_logic_vector (POINT_NUMBER-1 downto 0);\r
+    INIT_DATA_OUT         : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0);\r
+    INIT_PACKET_NUM_OUT   : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0);\r
+    INIT_READ_IN          : in  std_logic_vector (POINT_NUMBER-1 downto 0);\r
+    REPLY_HEADER_OUT      : out std_logic_vector (POINT_NUMBER-1 downto 0);\r
+    REPLY_DATAREADY_IN    : in  std_logic_vector (POINT_NUMBER-1 downto 0);\r
+    REPLY_DATA_IN         : in  std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0);\r
+    REPLY_PACKET_NUM_IN   : in  std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0);\r
+    REPLY_READ_OUT        : out std_logic_vector (POINT_NUMBER-1 downto 0);\r
+    REPLY_DATAREADY_OUT   : out std_logic_vector (POINT_NUMBER-1 downto 0);\r
+    REPLY_DATA_OUT        : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0);\r
+    REPLY_PACKET_NUM_OUT  : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0);\r
+    REPLY_READ_IN         : in  std_logic_vector (POINT_NUMBER-1 downto 0);\r
     --Status ports (for debugging)\r
-    STAT_CHANNEL       : out std_logic_vector (15 downto 0);\r
-    STAT_GEN           : out std_logic_vector (31 downto 0);\r
-    CTRL_CHANNEL       : in  std_logic_vector (31 downto 0);\r
-    CTRL_GEN           : in  std_logic_vector (31 downto 0) \r
+    STAT               : out std_logic_vector (31 downto 0);\r
+    CTRL               : in  std_logic_vector (31 downto 0)\r
     );\r
 end entity;\r
 \r
 architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is\r
+\r
+--signals init_pool\r
+  signal INIT_POOL_DATAREADY                 : std_logic;\r
+  signal INIT_POOL_READ                      : std_logic;\r
+  signal INIT_POOL_DATA                      : std_logic_vector(DATA_WIDTH-1 downto 0);\r
+  signal INIT_POOL_PACKET_NUM                : std_logic_vector(NUM_WIDTH-1  downto 0);\r
+  signal init_has_read_from_pool             : std_logic_vector(POINT_NUMBER-1  downto 0);\r
+  signal saved_INIT_TYPE, current_INIT_TYPE  : std_logic_vector(2 downto 0);\r
+\r
+\r
+  signal REPLY_POOL_DATAREADY                  : std_logic;\r
+  signal REPLY_POOL_READ                       : std_logic;\r
+  signal REPLY_POOL_DATA                       : std_logic_vector(DATA_WIDTH-1 downto 0);\r
+  signal REPLY_POOL_PACKET_NUM                 : std_logic_vector(NUM_WIDTH-1  downto 0);\r
+  signal saved_REPLY_TYPE , current_REPLY_TYPE : std_logic_vector(2 downto 0);\r
+\r
+--general signals\r
+  signal locked, next_locked                 : std_logic;\r
+  signal get_locked, release_locked          : std_logic;\r
+  signal locking_point, next_locking_point   : std_logic_vector(POINT_NUMBER-1  downto 0);\r
+\r
 begin\r
+\r
+STAT <= (others => '0');\r
+\r
+\r
 --Datapool for Init-Channel\r
-  INIT_POOL_DATAREADY <= or_all(INIT_DATAREADY_IN(POINT_NUMBER-1 downto 0);\r
+  INIT_POOL_DATAREADY <= or_all(INIT_DATAREADY_IN(POINT_NUMBER-1 downto 0));\r
   INIT_POOL_READ <=\r
-        and_all(INIT_READ_IN(POINT_NUMBER-1 downto 0) or init_pool_has_read(POINT_NUMBER-1 downto 0));\r
+        and_all(INIT_READ_IN(POINT_NUMBER-1 downto 0) or init_has_read_from_pool(POINT_NUMBER-1 downto 0));\r
     \r
   gen_init_pool_data0: for i in 0 to DATA_WIDTH-1 generate\r
     process(INIT_DATA_IN)\r
       variable VAR_INIT_POOL_DATA : std_logic;\r
-    begin\r
-      VAR_INIT_POOL_DATA := 0;\r
-      gen_init_pool_data1: for j in 0 to POINT_NUMBER-1 loop\r
-        VAR_INIT_POOL_DATA := VAR_INIT_POOL_DATA or INIT_DATA_IN(j*DATA_WIDTH+i);\r
-      end loop;\r
-      INIT_POOL_DATA(i) <= VAR_INIT_POOL_DATA;\r
-    end process;\r
+      begin\r
+        VAR_INIT_POOL_DATA := '0';\r
+        gen_init_pool_data1: for j in 0 to POINT_NUMBER-1 loop\r
+          VAR_INIT_POOL_DATA := VAR_INIT_POOL_DATA or INIT_DATA_IN(j*DATA_WIDTH+i);\r
+        end loop;\r
+        INIT_POOL_DATA(i) <= VAR_INIT_POOL_DATA;\r
+      end process;\r
   end generate;\r
 \r
---Data for obuf output\r
-  gen_init_dataready_out: for i in 0 to POINT_NUMBER-1 generate  \r
-    INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_pool_has_read(i);\r
+  gen_init_pool_data2: for i in 0 to NUM_WIDTH-1 generate\r
+    process(INIT_PACKET_NUM_IN)\r
+      variable VAR_INIT_POOL_PACKET_NUM : std_logic;\r
+      begin\r
+        VAR_INIT_POOL_PACKET_NUM := '0';\r
+        gen_init_pool_data3: for j in 0 to POINT_NUMBER-1 loop\r
+          VAR_INIT_POOL_PACKET_NUM := VAR_INIT_POOL_PACKET_NUM or INIT_PACKET_NUM_IN(j*NUM_WIDTH+i);\r
+        end loop;\r
+        INIT_POOL_PACKET_NUM(i) <= VAR_INIT_POOL_PACKET_NUM;\r
+      end process;\r
   end generate;\r
 \r
-  gen_init_data_out: for i in 0 to POINT_NUMBER-1 generate  \r
+--has-read signal\r
+  gen_hasread: for i in 0 to POINT_NUMBER-1 generate\r
+    process(CLK)\r
+      begin\r
+        if rising_edge(CLK) then\r
+          if RESET = '1' or INIT_POOL_READ = '1' then\r
+            init_has_read_from_pool(i) <= '0';\r
+          else\r
+            if INIT_POOL_DATAREADY = '1' and INIT_READ_IN(i) = '1' then\r
+              init_has_read_from_pool(i) <= '1';\r
+            end if;\r
+          end if;\r
+        end if;\r
+      end process;\r
+  end generate;\r
+\r
+--signals to ibufs\r
+  INIT_READ_OUT <= (others => INIT_POOL_READ);\r
+\r
+--signals to obufs\r
+  gen_init_data_out: for i in 0 to POINT_NUMBER-1 generate\r
+    INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_has_read_from_pool(i);\r
     INIT_DATA_OUT((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH) <= INIT_POOL_DATA;\r
+    INIT_PACKET_NUM_OUT((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH) <= INIT_POOL_PACKET_NUM;\r
   end generate;  \r
-  \r
-  gen_init_read_in\r
-  \r
-  --DATAREADY for each OBUF is dataready from all ibufs and not already have been reading this word\r
-  -- gen_init_datapool_c: for CHANNEL in 0 to 2**(MUX_WIDTH-1)-1 generate\r
-    -- gen_init_datapool_m: for MEDIA in 0 to MII_NUMBER-1 generate\r
-      -- hub_to_buf_INIT_DATAREADY(CHANNEL*MII_NUMBER+MEDIA) <= \r
-                -- or_all(buf_to_hub_DATAREADY((CHANNEL+1)*MII_NUMBER-1 downto CHANNEL*MII_NUMBER) \r
-                -- and not buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA);\r
-      -- hub_to_buf_INIT_DATA((CHANNEL*MII_NUMBER+MEDIA)*(DATA_WIDTH+1)-1 downto CHANNEL*MII_NUMBER+MEDIA)*(DATA_WIDTH)) <=\r
-                -- or_all(\r
-    -- end generate;\r
-  -- end generate;\r
-\r
-  -- gen_init_has_read_c: for CHANNEL in 0 to 2**(MUX_WIDTH-1)-1 generate\r
-    -- gen_init_has_read_m: for MEDIA in 0 to MII_NUMBER-1 generate\r
-      -- process(CLK)\r
-        -- begin\r
-          -- if rising_edge(CLK) then\r
-            -- if RESET = '1' or buf_to_hub_INIT_CHANNEL_READ(CHANNEL) = '1' then\r
-              -- buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA) <= '0';\r
-            -- else\r
-              -- if hub_to_buf_INIT_DATAREADY(CHANNEL*MII_NUMBER+MEDIA) = '1' \r
-                    -- and hub_to_buf_INIT_READ(CHANNEL*MII_NUMBER+MEDIA) = '1' then\r
-                -- buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA) <= '1';\r
-              -- end if;\r
-            -- end if;\r
-          -- end if;\r
-        -- end process;\r
-    -- end generate;\r
-  -- end generate; \r
+\r
+\r
+\r
+--locked signals\r
+  release_locked <= '1' when (saved_REPLY_TYPE = TYPE_TRM) and REPLY_POOL_PACKET_NUM = "11" else '0';\r
+  get_locked     <= INIT_POOL_DATAREADY;\r
+  next_locked    <= (get_locked or locked) and not release_locked;\r
+  next_locking_point <= INIT_DATAREADY_IN when locked = '0' else locking_point;\r
+\r
+  process(CLK)\r
+    begin\r
+      if rising_edge(CLK) then\r
+        if RESET = '1' then\r
+          locked <= '0';\r
+          locking_point <= (others => '0');\r
+        else\r
+          locked <= next_locked;\r
+          locking_point <= next_locking_point;\r
+        end if;\r
+      end if;\r
+    end process;\r
+\r
+--saving packet types\r
+  process(CLK)\r
+    begin\r
+      if rising_edge(CLK) then\r
+        if RESET = '1' then\r
+          saved_INIT_TYPE <= TYPE_ILLEGAL;\r
+        elsif INIT_POOL_DATAREADY = '1' and INIT_POOL_PACKET_NUM = "00" then\r
+          saved_INIT_TYPE <= INIT_POOL_DATA(2 downto 0);\r
+        end if;\r
+      end if;\r
+    end process;\r
+  process(CLK)\r
+    begin\r
+      if rising_edge(CLK) then\r
+        if RESET = '1' then\r
+          saved_REPLY_TYPE <= TYPE_ILLEGAL;\r
+        elsif REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = "00" then\r
+          saved_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0);\r
+        end if;\r
+      end if;\r
+    end process;\r
+  current_INIT_TYPE <= INIT_POOL_DATA(2 downto 0) when INIT_POOL_DATAREADY = '1' and INIT_POOL_PACKET_NUM = "00"\r
+                       else saved_INIT_TYPE;\r
+  current_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0) when REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = "00"\r
+                       else saved_REPLY_TYPE;\r
+\r
+\r
+\r
+\r
 end architecture;
\ No newline at end of file