High precision Time-to-Digital converters (TDCs) are mainly used in high energy
physics, where timing plays a crucial part in particle identification. For this
purpose setups with combinations of particle-sensitive materials (e.g.
-Scintillator, Cerenkov) and photosensitive devices (photomultiplier,
-multipixel photon counter) are used to measure the energy deposited in the
+Scintillator, Cherenkov) and photosensitive devices (photomultiplier,
+multi-pixel photon counter) are used to measure the energy deposited in the
material by reconstructing a given property of the output pulse - the total
charge collected, the pulse amplitude, etc \cite{tot}. Because of the recent
developments of high precision TDCs and the superiority of the ToT measurements
\section{Architecture}
As explained in our previous paper the architecture of the TDC is based on the
interpolation method \cite{kalisz}, where the interpolator is built as a tapped
-delay line with the wave union laucher \cite{WUL} for the precision enhancement.
+delay line with the wave union launcher \cite{WUL} for the precision
+enhancement.
The full architecture of the TDC and a diagram of the tapped delay line method
can be seen in figure~\ref{fig:tdcArch}. The start signal for the delay line is
the digital output signal from the front-end electronics (FEE), where as the
\begin{figure}[tbp]
\centering
-\begin{subfigure}[b]{.75\textwidth}
+\begin{subfigure}[b]{.7\textwidth}
\includegraphics[width=1\linewidth]
{../figures/tdc/stretcher_timing_semiAsync.eps}
\caption{Timing diagram of the ToT method without the delay circuit}
\label{fig:stretcherTimingSemi}
\end{subfigure}%
-\begin{subfigure}[b]{.75\textwidth}
+\begin{subfigure}[b]{.7\textwidth}
\includegraphics[width=1\linewidth]
{../figures/tdc/stretcher_timing_fullAsync.eps}
\caption{Timing diagram of the ToT method with the delay circuit}
\begin{figure}[tbp]
\centering
- \includegraphics[width=.6\textwidth]
+ \includegraphics[width=.5\textwidth]
{../figures/tdc/9ps_res.eps}
\caption{The precision of a sample channel for leading edge measurement.}
\label{fig:precisionLeading}
\begin{figure}[tbp]
\begin{subfigure}{.5\textwidth}
\centering
- \includegraphics[width=.9\linewidth]
+ \includegraphics[width=.8\linewidth]
{../figures/tdc/t_diff_tot_alternating.eps}
\caption{ToT measurement with conventional method.}
\label{fig:precisionToTalt}
\end{subfigure}%
\begin{subfigure}{.5\textwidth}
\centering
- \includegraphics[width=.9\linewidth]
+ \includegraphics[width=.8\linewidth]
{../figures/tdc/t_diff_tot_stretcher_high_precision.eps}
\caption{ToT measurement with novel method.}
\label{fig:precisionToTstretch}
\begin{figure}[tbp]
\centering
- \includegraphics[width=.69\textwidth]{../figures/tdc/tot_sweep.pdf}
+ \includegraphics[width=.6\textwidth]{../figures/tdc/tot_sweep.pdf}
\caption{ToT sweep with $1.6~ns$ granularity.}
\label{fig:totSweep}
\end{figure}
In figure~\ref{fig:rmsWITHdcdc} the precision of a channel as a function of the
measured interval is shown. It was observed that over a microsecond time
interval the precision value oscillates with an amplitude of $48~ps$ and this
-effect was thought to be from the DC-DC converters. Next, the board was stripped
-down of the converters and the FPGA was powered with a linear power supply
-(HMP4040). The test was repeated to be observed that the main oscillation had
-disappeared but there was a secondary oscillation with an amplitude of
-$\sim3~ps$ and a frequency of $25~MHz$ (figure~\ref{fig:rmsNOdcdc}). This
-trivial oscillation is not further investigated as the amplitude is negligible.
+effect was thought to be from the DC-DC converters. Next, the board was
+stripped down of the converters and the FPGA was powered with a linear power
+supply (HMP4040). The test was repeated to be noted that the oscillation
+amplitude is improved by a factor of $\sim12$. The exposed secondary oscillation
+has an amplitude of $\sim3~ps$ and a frequency of $25~MHz$
+(figure~\ref{fig:rmsNOdcdc}). This trivial oscillation is not further
+investigated as the amplitude is negligible.
\begin{figure}[tbp]
\begin{subfigure}{.5\textwidth}
\centering
- \includegraphics[width=.9\linewidth]
+ \includegraphics[width=.8\linewidth]
{../figures/tdc/rms_trb3_with_dcdc.eps}
\caption{With DC-DC converters to power the FPGA.}
\label{fig:rmsWITHdcdc}
\end{subfigure}%
\begin{subfigure}{.5\textwidth}
\centering
- \includegraphics[width=.9\linewidth]
+ \includegraphics[width=.8\linewidth]
{../figures/tdc/rms_trb3_without_dcdc.eps}
\caption{Linear power supply to power the FPGA.}
\label{fig:rmsNOdcdc}
\caption{ToT shift $@42.8^{\circ}C$ as a function of stretcher offset.}
\label{fig:totVSoffset}
\end{subfigure}%
-\caption{The effect of temperature is seen more drasticall on channels with
+\caption{The effect of temperature is seen more drastically on channels with
longer stretcher offsets.}
\label{fig:temp}
\end{figure}
\section{Conclusion}
-
-
+In this paper we presented our novel way of measuring ToT on an FPGA TDC using
+a single channel. Based on the conducted tests precision of the leading edge
+measurement is recorded as low as $8.7~ps$, suggesting $6.15~ps$ error on a
+single channel. The precisions for ToT measurements with the conventional and
+novel methods are recorded as $12.2~ps$ and $12.1~ps$ respectively. The novel
+method is investigated further to find out, that the ToT value differs maximum
+$38~ps$ from the oscilloscope measurements once the stretcher offset is
+eliminated. It is also discovered that the deterioration in the long time
+interval measurement precision can be limited to $3~ps$, if the FPGA is powered
+with a linear power supply. The effect of the temperature change on the ToT
+measurement is also assessed and the degeneration is improved by a factor of
+$\sim10$ and limited to $\sim50ps$ with a correction model.
\href{http://arxiv.org/abs/1412.1743}
{\emph{arXiv:1412.1743}} (2014).
+\bibitem{WUL}
+J. Wu, Z. Shi,
+\emph{The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell
+delay}
+\href{http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4775079}
+{\emph{Nuclear Science Symposium Conference Record}, 3440-3446, (Oct., 2008).}
+
\bibitem{tdc_counter}
M. Buchele et al.,
\emph{A 128-channel time-to-digital converter (TDC) inside a Virtex-5 FPGA on
\href{http://stacks.iop.org/0026-1394/41/i=1/a=004}
{\emph{Metrologia}, 41, 17, (2004).}
-\bibitem{WUL}
-J. Wu, Z. Shi,
-\emph{The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell
-delay}
-\href{http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4775079}
-{\emph{Nuclear Science Symposium Conference Record}, 3440-3446, (Oct., 2008).}
-
\bibitem{trbnet}
J. Michel et al.,
\emph{The HADES trigger and readout board network (TrbNet)}
jspc29 / publication.git / commitdiff