added correct PLL for 200MHz and 150MHz calibration oscillator, mt

diff --git a/base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.cst b/base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.cst
new file mode 100644 (file)
index 0000000..1761833
--- /dev/null
+++ b/base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.cst
@@ -0,0 +1,3 @@
+Date=10/17/2022
+Time=16:28:09
+

diff --git a/base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.fdc b/base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.lpc b/base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.lpc
new file mode 100644 (file)
index 0000000..f08200f
--- /dev/null
+++ b/base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.lpc
@@ -0,0 +1,93 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll_in150_out50
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=10/17/2022
+Time=16:28:09
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+CLKI_FREQ=150
+CLKI_DIV=3
+ENABLE_HBW=DISABLED
+REFERENCE=0
+IOBUF=LVDS
+CLKOP_FREQ=50
+CLKOP_TOL=0.0
+CLKOP_DIV=12
+CLKOP_ACTUAL_FREQ=50.000000
+CLKOP_MUXA=DISABLED
+CLKOS_Enable=DISABLED
+CLKOS_FREQ=100.00
+CLKOS_TOL=0.0
+CLKOS_DIV=1
+CLKOS_ACTUAL_FREQ=
+CLKOS_MUXB=DISABLED
+CLKOS2_Enable=DISABLED
+CLKOS2_FREQ=100.00
+CLKOS2_TOL=0.0
+CLKOS2_DIV=1
+CLKOS2_ACTUAL_FREQ=
+CLKOS2_MUXC=DISABLED
+CLKOS3_Enable=DISABLED
+CLKOS3_FREQ=100.00
+CLKOS3_TOL=0.0
+CLKOS3_DIV=1
+CLKOS3_ACTUAL_FREQ=
+CLKOS3_MUXD=DISABLED
+FEEDBK_PATH=CLKOP
+CLKFB_DIV=1
+FRACN_ENABLE=DISABLED
+FRACN_DIV=
+VCO_RATE=600.000
+PLL_BW=6.207
+CLKOP_DPHASE=0
+CLKOP_APHASE=0.00
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+CLKOS_DPHASE=0
+CLKOS_APHASE=0.00
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+CLKOS2_DPHASE=0
+CLKOS2_APHASE=0.00
+CLKOS2_TRIM_POL=Rising
+CLKOS2_TRIM_DELAY=0
+CLKOS3_DPHASE=0
+CLKOS3_APHASE=0.00
+CLKOS3_TRIM_POL=Rising
+CLKOS3_TRIM_DELAY=0
+CLKSEL_ENA=DISABLED
+DPHASE_SOURCE=STATIC
+ENABLE_CLKOP=DISABLED
+ENABLE_CLKOS=DISABLED
+ENABLE_CLKOS2=DISABLED
+ENABLE_CLKOS3=DISABLED
+STDBY_ENABLE=DISABLED
+PLLRST_ENA=DISABLED
+PLL_LOCK_MODE=DISABLED
+PLL_LOCK_STK=DISABLED
+PLL_USE_SMI=DISABLED
+
+[Command]
+cmd_line= -w -n pll_in150_out50 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 150 -fclkop 50 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1

diff --git a/base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.vhd b/base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.vhd
new file mode 100644 (file)
index 0000000..f0247b1
--- /dev/null
+++ b/base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.vhd
@@ -0,0 +1,71 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
+-- Module  Version: 5.7
+--/opt/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll_in150_out50 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 150 -fclkop 50 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/hadaq/dirich5s_test/clarity1/pll_in150_out50/pll_in150_out50.fdc 
+
+-- Mon Oct 17 16:28:10 2022
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity pll_in150_out50 is
+    port (
+        CLKI: in  std_logic; 
+        CLKOP: out  std_logic);
+end pll_in150_out50;
+
+architecture Structure of pll_in150_out50 is
+
+    -- internal signal declarations
+    signal REFCLK: std_logic;
+    signal LOCK: std_logic;
+    signal CLKOP_t: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute ICP_CURRENT : string; 
+    attribute LPF_RESISTOR : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "50.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "150.000000";
+    attribute ICP_CURRENT of PLLInst_0 : label is "12";
+    attribute LPF_RESISTOR of PLLInst_0 : label is "8";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLL
+        generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", 
+        STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", 
+        CLKOS3_FPHASE=>  0, CLKOS3_CPHASE=>  0, CLKOS2_FPHASE=>  0, 
+        CLKOS2_CPHASE=>  0, CLKOS_FPHASE=>  0, CLKOS_CPHASE=>  0, 
+        CLKOP_FPHASE=>  0, CLKOP_CPHASE=>  11, PLL_LOCK_MODE=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "FALLING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "FALLING", 
+        OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", 
+        OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", 
+        OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", 
+        OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=>  1, 
+        CLKOS2_DIV=>  1, CLKOS_DIV=>  1, CLKOP_DIV=>  12, CLKFB_DIV=>  1, 
+        CLKI_DIV=>  3, FEEDBK_PATH=> "CLKOP")
+        port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, 
+            PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, 
+            PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, 
+            STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, 
+            ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, 
+            ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, 
+            CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, 
+            REFCLK=>REFCLK, CLKINTFB=>open);
+
+    CLKOP <= CLKOP_t;
+end Structure;

diff --git a/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.cst b/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.cst
new file mode 100644 (file)
index 0000000..dd25079
--- /dev/null
+++ b/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.cst
@@ -0,0 +1,3 @@
+Date=10/13/2022
+Time=11:27:14
+

diff --git a/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.fdc b/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.lpc b/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.lpc
new file mode 100644 (file)
index 0000000..8c962ba
--- /dev/null
+++ b/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.lpc
@@ -0,0 +1,93 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll_in200_out50
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=10/13/2022
+Time=11:27:14
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+CLKI_FREQ=200
+CLKI_DIV=4
+ENABLE_HBW=DISABLED
+REFERENCE=0
+IOBUF=LVDS
+CLKOP_FREQ=50
+CLKOP_TOL=0.0
+CLKOP_DIV=12
+CLKOP_ACTUAL_FREQ=50.000000
+CLKOP_MUXA=DISABLED
+CLKOS_Enable=DISABLED
+CLKOS_FREQ=100.00
+CLKOS_TOL=0.0
+CLKOS_DIV=1
+CLKOS_ACTUAL_FREQ=
+CLKOS_MUXB=DISABLED
+CLKOS2_Enable=DISABLED
+CLKOS2_FREQ=100.00
+CLKOS2_TOL=0.0
+CLKOS2_DIV=1
+CLKOS2_ACTUAL_FREQ=
+CLKOS2_MUXC=DISABLED
+CLKOS3_Enable=DISABLED
+CLKOS3_FREQ=100.00
+CLKOS3_TOL=0.0
+CLKOS3_DIV=1
+CLKOS3_ACTUAL_FREQ=
+CLKOS3_MUXD=DISABLED
+FEEDBK_PATH=INT_OP
+CLKFB_DIV=1
+FRACN_ENABLE=DISABLED
+FRACN_DIV=
+VCO_RATE=600.000
+PLL_BW=6.207
+CLKOP_DPHASE=0
+CLKOP_APHASE=0.00
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+CLKOS_DPHASE=0
+CLKOS_APHASE=0.00
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+CLKOS2_DPHASE=0
+CLKOS2_APHASE=0.00
+CLKOS2_TRIM_POL=Rising
+CLKOS2_TRIM_DELAY=0
+CLKOS3_DPHASE=0
+CLKOS3_APHASE=0.00
+CLKOS3_TRIM_POL=Rising
+CLKOS3_TRIM_DELAY=0
+CLKSEL_ENA=DISABLED
+DPHASE_SOURCE=STATIC
+ENABLE_CLKOP=DISABLED
+ENABLE_CLKOS=DISABLED
+ENABLE_CLKOS2=DISABLED
+ENABLE_CLKOS3=DISABLED
+STDBY_ENABLE=DISABLED
+PLLRST_ENA=DISABLED
+PLL_LOCK_MODE=DISABLED
+PLL_LOCK_STK=DISABLED
+PLL_USE_SMI=DISABLED
+
+[Command]
+cmd_line= -w -n pll_in200_out50 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 50 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 5

diff --git a/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.vhd b/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.vhd
new file mode 100644 (file)
index 0000000..5f1a4bc
--- /dev/null
+++ b/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.vhd
@@ -0,0 +1,72 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
+-- Module  Version: 5.7
+--/opt/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll_in200_out50 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 50 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 5 -fdc /home/hadaq/dirich5s_test/clarity1/pll_in200_out50/pll_in200_out50.fdc 
+
+-- Thu Oct 13 11:28:37 2022
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity pll_in200_out50 is
+    port (
+        CLKI: in  std_logic; 
+        CLKOP: out  std_logic);
+end pll_in200_out50;
+
+architecture Structure of pll_in200_out50 is
+
+    -- internal signal declarations
+    signal REFCLK: std_logic;
+    signal LOCK: std_logic;
+    signal CLKOP_t: std_logic;
+    signal CLKFB_t: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute ICP_CURRENT : string; 
+    attribute LPF_RESISTOR : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "50.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+    attribute ICP_CURRENT of PLLInst_0 : label is "12";
+    attribute LPF_RESISTOR of PLLInst_0 : label is "8";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLL
+        generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", 
+        STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", 
+        CLKOS3_FPHASE=>  0, CLKOS3_CPHASE=>  0, CLKOS2_FPHASE=>  0, 
+        CLKOS2_CPHASE=>  0, CLKOS_FPHASE=>  0, CLKOS_CPHASE=>  0, 
+        CLKOP_FPHASE=>  0, CLKOP_CPHASE=>  11, PLL_LOCK_MODE=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "FALLING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "FALLING", 
+        OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", 
+        OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", 
+        OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", 
+        OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=>  1, 
+        CLKOS2_DIV=>  1, CLKOS_DIV=>  1, CLKOP_DIV=>  12, CLKFB_DIV=>  1, 
+        CLKI_DIV=>  4, FEEDBK_PATH=> "INT_OP")
+        port map (CLKI=>CLKI, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo, 
+            PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, 
+            PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, 
+            STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, 
+            ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, 
+            ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, 
+            CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, 
+            REFCLK=>REFCLK, CLKINTFB=>CLKFB_t);
+
+    CLKOP <= CLKOP_t;
+end Structure;