);
end component;
- component TDC
+ component TDC is
generic (
CHANNEL_NUMBER : integer range 2 to 65;
CONTROL_REG_NR : integer range 0 to 6);
HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1);
TRG_WIN_PRE : in std_logic_vector(10 downto 0);
TRG_WIN_POST : in std_logic_vector(10 downto 0);
- TRG_DATA_VALID_IN : in std_logic;
- VALID_TIMING_TRG_IN : in std_logic;
- VALID_NOTIMING_TRG_IN : in std_logic;
- INVALID_TRG_IN : in std_logic;
- TMGTRG_TIMEOUT_IN : in std_logic;
- SPIKE_DETECTED_IN : in std_logic;
- MULTI_TMG_TRG_IN : in std_logic;
- SPURIOUS_TRG_IN : in std_logic;
- TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
- TRG_CODE_IN : in std_logic_vector(7 downto 0);
- TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
- TRG_TYPE_IN : in std_logic_vector(3 downto 0);
+ TRG_DATA_VALID_IN : in std_logic := '0';
+ VALID_TIMING_TRG_IN : in std_logic := '0';
+ VALID_NOTIMING_TRG_IN : in std_logic := '0';
+ INVALID_TRG_IN : in std_logic := '0';
+ TMGTRG_TIMEOUT_IN : in std_logic := '0';
+ SPIKE_DETECTED_IN : in std_logic := '0';
+ MULTI_TMG_TRG_IN : in std_logic := '0';
+ SPURIOUS_TRG_IN : in std_logic := '0';
+ TRG_NUMBER_IN : in std_logic_vector(15 downto 0) := (others => '0');
+ TRG_CODE_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ TRG_INFORMATION_IN : in std_logic_vector(23 downto 0) := (others => '0');
+ TRG_TYPE_IN : in std_logic_vector(3 downto 0) := (others => '0');
TRG_RELEASE_OUT : out std_logic;
TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0);
DATA_OUT : out std_logic_vector(31 downto 0);
ESB_DATA_OUT : out std_logic_vector(31 downto 0);
ESB_DATAREADY_OUT : out std_logic;
ESB_UNKNOWN_ADDR_OUT : out std_logic;
- FWB_READ_EN_IN : in std_logic;
- FWB_WRITE_EN_IN : in std_logic;
- FWB_ADDR_IN : in std_logic_vector(6 downto 0);
- FWB_DATA_OUT : out std_logic_vector(31 downto 0);
- FWB_DATAREADY_OUT : out std_logic;
- FWB_UNKNOWN_ADDR_OUT : out std_logic;
+ EFB_READ_EN_IN : in std_logic;
+ EFB_WRITE_EN_IN : in std_logic;
+ EFB_ADDR_IN : in std_logic_vector(6 downto 0);
+ EFB_DATA_OUT : out std_logic_vector(31 downto 0);
+ EFB_DATAREADY_OUT : out std_logic;
+ EFB_UNKNOWN_ADDR_OUT : out std_logic;
LHB_READ_EN_IN : in std_logic;
LHB_WRITE_EN_IN : in std_logic;
LHB_ADDR_IN : in std_logic_vector(6 downto 0);
LHB_UNKNOWN_ADDR_OUT : out std_logic;
LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0);
CONTROL_REG_IN : in std_logic_vector(32*CONTROL_REG_NR-1 downto 0));
- end component;
+ end component TDC;
component Reference_Channel
generic (
COARSE_COUNTER_IN : in std_logic_vector(10 downto 0));
end component;
- component Channel
+ component Channel is
generic (
CHANNEL_ID : integer range 0 to 64);
port (
CLK_200 : in std_logic;
CLK_100 : in std_logic;
HIT_IN : in std_logic;
- TRIGGER_IN : in std_logic;
- SCALER_IN : in std_logic;
TRIGGER_WIN_END_IN : in std_logic;
READ_EN_IN : in std_logic;
FIFO_DATA_OUT : out std_logic_vector(35 downto 0);
FIFO_ALMOST_FULL_OUT : out std_logic;
COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0);
- DATA_FINISHED_IN : in std_logic;
LOST_HIT_NUMBER : out std_logic_vector(23 downto 0);
HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0);
- FIFO_WR_NUMBER : out std_logic_vector(23 downto 0);
ENCODER_START_NUMBER : out std_logic_vector(23 downto 0);
ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0);
Channel_DEBUG : out std_logic_vector(31 downto 0));
- end component;
-
- component Channel_200
+ end component Channel;
+
+ component Channel_200 is
generic (
CHANNEL_ID : integer range 0 to 64);
port (
CLK_100 : in std_logic;
RESET_100 : in std_logic;
HIT_IN : in std_logic;
- TRIGGER_IN : in std_logic;
- SCALER_IN : in std_logic;
TRIGGER_WIN_END_IN : in std_logic;
EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0);
- DATA_FINISHED_IN : in std_logic;
COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
READ_EN_IN : in std_logic;
FIFO_DATA_OUT : out std_logic_vector(35 downto 0);
FIFO_EMPTY_OUT : out std_logic;
FIFO_FULL_OUT : out std_logic;
FIFO_ALMOST_FULL_OUT : out std_logic;
- FIFO_WR_OUT : out std_logic;
ENCODER_START_OUT : out std_logic;
ENCODER_FINISHED_OUT : out std_logic);
- end component;
-
- component Readout
+ end component Channel_200;
+
+ component Readout is
generic (
CHANNEL_NUMBER : integer range 2 to 65);
port (
TRG_CODE_IN : in std_logic_vector(7 downto 0);
TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
TRG_TYPE_IN : in std_logic_vector(3 downto 0);
+ DATA_LIMIT_IN : in unsigned(7 downto 0);
TRG_RELEASE_OUT : out std_logic;
TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0);
DATA_OUT : out std_logic_vector(31 downto 0);
DATA_WRITE_OUT : out std_logic;
DATA_FINISHED_OUT : out std_logic;
READ_EN_OUT : out std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1);
- READOUT_BUSY_OUT : out std_logic;
TRIGGER_WIN_END_OUT : out std_logic;
STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to 18);
READOUT_DEBUG : out std_logic_vector(31 downto 0));
- end component;
+ end component Readout;
component LogicAnalyser
generic (
signal tdc_ctrl_read : std_logic;
signal last_tdc_ctrl_read : std_logic;
signal tdc_ctrl_write : std_logic;
- signal tdc_ctrl_addr : std_logic_vector(1 downto 0);
+ signal tdc_ctrl_addr : std_logic_vector(2 downto 0);
signal tdc_ctrl_data_in : std_logic_vector(31 downto 0);
signal tdc_ctrl_data_out : std_logic_vector(31 downto 0);
signal tdc_ctrl_reg : std_logic_vector(5*32-1 downto 0);
-- -- x"4" - Wasa AddOn
--edge_type_i <= x"0"; -- x"0" - single edge
-- -- x"1" - double edge
+ -- -- x"8" - double edge on consecutive channels
--tdc_channel_no_i <= x"6"; -- 2^n channels
THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
BROADCAST_BITMASK => x"FF",
BROADCAST_SPECIAL_ADDR => x"48",
REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"91000060", -- regio_hardware_version_i,
+ REGIO_HARDWARE_VERSION => x"91000860", -- regio_hardware_version_i,
REGIO_INIT_ADDRESS => x"f305",
REGIO_USE_VAR_ENDPOINT_ID => c_YES,
CLOCK_FREQUENCY => 125,
generic map(
PORT_NUMBER => 9,
PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", others => x"0000"),
- PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 2, others => 0)
+ PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 3, others => 0)
)
port map(
CLK => clk_100_i,
BUS_READ_ENABLE_OUT(8) => tdc_ctrl_read,
BUS_WRITE_ENABLE_OUT(8) => tdc_ctrl_write,
BUS_DATA_OUT(8*32+31 downto 8*32) => tdc_ctrl_data_in,
- BUS_ADDR_OUT(8*16+1 downto 8*16) => tdc_ctrl_addr,
- BUS_ADDR_OUT(8*16+15 downto 8*16+2) => open,
+ BUS_ADDR_OUT(8*16+2 downto 8*16) => tdc_ctrl_addr,
+ BUS_ADDR_OUT(8*16+15 downto 8*16+3) => open,
BUS_TIMEOUT_OUT(8) => open,
BUS_DATA_IN(8*32+31 downto 8*32) => tdc_ctrl_data_out,
BUS_DATAREADY_IN(8) => last_tdc_ctrl_read,
THE_TDC : TDC
generic map (
- CHANNEL_NUMBER => 5, -- Number of TDC channels
- CONTROL_REG_NR => 5) -- Number of control regs
+ CHANNEL_NUMBER => 65, -- Number of TDC channels
+ CONTROL_REG_NR => 5) -- Number of control regs - higher than 8 check tdc_ctrl_addr
port map (
RESET => reset_i,
CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement
CLK_READOUT => clk_100_i, -- Clock for the readout
- REFERENCE_TIME => timing_trg_received_i, -- Reference time input
- HIT_IN => hit_in_i(4 downto 1), -- Channel start signals
+ REFERENCE_TIME => timing_trg_received_i, -- Reference time input
+ HIT_IN => hit_in_i(64 downto 1), -- Channel start signals
TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width
TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width
--
jspc29 / trb3.git / commitdiff