--If the timing seems to be correct but the trbnet trb_net doesn't react, try
--shifting the clock by 180 degrees.
-
+--Version with spare bits at end, using 18_to16 was 1.8
--
-- Constraints for timing on hadcom dev board:
-- NET "LVDS_IN<13>" TNM_NET = LVDS_IN_CLK_GRP;
-- INST "LVDS_OUT<*>" TNM = "OUT_DDR";
-- INST lvds1/buf_MED_IN_fal* TNM = "falling_reg";
-- TIMEGRP "OUT_DDR" OFFSET = OUT 8 ns AFTER "CLK_IN";
--- TIMEGRP "IN_DDR" OFFSET = IN -7 ns VALID 1 BEFORE "LVDS_IN<13>";
--- TIMEGRP "IN_DDR" OFFSET = IN -2 ns VALID 1 BEFORE "LVDS_IN<13>" TIMEGRP "falling_reg";
+-- TIMEGRP "IN_DDR" OFFSET = IN -2 ns VALID 1 BEFORE "LVDS_IN<13>";
+-- TIMEGRP "IN_DDR" OFFSET = IN -7 ns VALID 1 BEFORE "LVDS_IN<13>" TIMEGRP "falling_reg";
--Constraints for timing on acromag:
-- INST "io*_*n" TNM = "OUT_DDR";
-- INST trbnetendpoint1/lvds1/buf_MED_IN_fal* TNM = "falling_reg";
--
--- TIMEGRP "IN_DDR" OFFSET = IN -7 ns VALID 1 ns BEFORE "IO59_29P";
--- TIMEGRP "IN_DDR" OFFSET = IN -2 ns VALID 1 ns BEFORE "IO59_29P" TIMEGRP "falling_reg";
+-- TIMEGRP "IN_DDR" OFFSET = IN -2 ns VALID 1 ns BEFORE "IO59_29P";
+-- TIMEGRP "IN_DDR" OFFSET = IN -7 ns VALID 1 ns BEFORE "IO59_29P" TIMEGRP "falling_reg";
-- TIMEGRP "OUT_DDR" OFFSET = OUT 6.7 ns AFTER "FPGA_CLK";
end component trb_net_fifo_16bit_bram_dualport;
-component trb_net_18_to_16_converter
- generic ( VERSION : integer := 1); --Version of included sbufs
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- D18_DATAREADY_IN: in STD_LOGIC;
- D18_PACKET_NUM_IN: in STD_LOGIC_VECTOR(1 downto 0);
- D18_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word
- D18_READ_OUT: out STD_LOGIC;
-
- D16_DATAREADY_OUT: out STD_LOGIC;
- D16_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word
- D16_READ_IN: in STD_LOGIC;
- D16_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(1 downto 0);
-
- D18_DATAREADY_OUT: out STD_LOGIC;
- D18_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(1 downto 0);
- D18_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word
- D18_READ_IN: in STD_LOGIC;
-
- D16_DATAREADY_IN: in STD_LOGIC;
- D16_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word
- D16_READ_OUT: out STD_LOGIC;
- D16_PACKET_NUM_IN: in STD_LOGIC_VECTOR(1 downto 0)
- );
-end component;
-
---component DCM
-----
--- generic (
--- DFS_FREQUENCY_MODE : string := "LOW";
--- CLKFX_DIVIDE : integer := 4; -- Min 1 Max 32 (25MHz 3/4 M/D)
--- CLKFX_MULTIPLY : integer := 2 ; -- Min 2 Max 32 (60MHz 20/11 M/D)
----- CLKFX_MULTIPLY : integer := 3 ; -- Min 2 Max 32 (63MHz 19/10 M/D)
--- CLKIN_PERIOD : real := 10.0 ; -- 30.30ns
--- STARTUP_WAIT : boolean := FALSE
--- );
---
--- port ( CLKIN : in std_logic;
--- CLKFB : in std_logic;
--- DSSEN : in std_logic;
--- PSINCDEC : in std_logic;
--- PSEN : in std_logic;
--- PSCLK : in std_logic;
--- RST : in std_logic;
--- CLK0 : out std_logic;
--- CLK90 : out std_logic;
--- CLK180 : out std_logic;
--- CLK270 : out std_logic;
--- CLK2X : out std_logic;
--- CLK2X180 : out std_logic;
--- CLKDV : out std_logic;
--- CLKFX : out std_logic;
--- CLKFX180 : out std_logic;
--- LOCKED : out std_logic;
--- PSDONE : out std_logic;
--- STATUS : out std_logic_vector(7 downto 0)
--- );
---end component;
component trb_net_sbuf
generic (DATA_WIDTH : integer := 16;
VERSION: integer := 0);
signal fifo_data_ready : std_logic;
signal buf_int_error_out, next_INT_ERROR_OUT : std_logic_vector(2 downto 0);
-
-signal CONV_DATAREADY_OUT : std_logic;
-signal CONV_DATA_OUT : std_logic_vector(15 downto 0);
-signal CONV_READ_IN: std_logic;
-signal CONV_PACKET_NR_OUT: std_logic_vector(1 downto 0);
+signal buf_INT_READ_OUT : std_logic;
signal FB_CLK, CLK_FB_Out, CLK_RECV_Out : std_logic;
signal sbuff_status : std_logic;
signal sbuff_next_read_out : std_logic;
-CONV16to18 : trb_net_18_to_16_converter
- generic map(
- VERSION => 0
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET_RECV,
- CLK_EN => CLK_EN,
-
- D18_DATAREADY_IN => INT_DATAREADY_IN,
- D18_PACKET_NUM_IN => INT_PACKET_NR_IN,
- D18_DATA_IN => INT_DATA_IN,
- D18_READ_OUT => INT_READ_OUT,
-
- D16_DATAREADY_OUT => CONV_DATAREADY_OUT,
- D16_DATA_OUT => CONV_DATA_OUT,
- D16_READ_IN => CONV_READ_IN,
- D16_PACKET_NUM_OUT => CONV_PACKET_NR_OUT,
-
- D18_DATAREADY_OUT => open,
- D18_PACKET_NUM_OUT => open,
- D18_DATA_OUT => open,
- D18_READ_IN => '0',
-
- D16_DATAREADY_IN => '0',
- D16_DATA_IN => (others => '0'),
- D16_READ_OUT => open,
- D16_PACKET_NUM_IN => "00"
- );
-
-
-----------------------------------------------------------------------
-- Getting clock from LVDS
-----------------------------------------------------------------------
--- CLK_TRANS <= not MED_TRANSMISSION_CLK_IN;
--- DCM_LOCKED <= '1';
-
--- U5_BUFG: BUFG
--- port map (
--- I => MED_TRANSMISSION_CLK_IN,
--- O => buf_MED_TRANSMISSION_CLK_IN
--- );
---the inverted clock is not really necessary,but helps sorting the data!
-
U_DCM_RECV: DCM
generic map(
);
--
U3_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK);
-U4_BUFG: BUFG port map (I => CLK_RECV_Out, O => CLK_TRANS);
---CLK_TRANS <= FB_CLK;
+--U4_BUFG: BUFG port map (I => CLK_RECV_Out, O => CLK_TRANS);
+CLK_TRANS <= FB_CLK;
-----------------------------------------------------------------------
-- Preparing incoming data for fifo
process(CLK,RESET_RECV)
begin
- if RESET_RECV = '1' then
- last_fifo_read_enable <= '0';
- buf_int_error_out <= ERROR_NC;
- buf_int_packet_nr_out <= "11";
- elsif rising_edge(CLK) then
- last_fifo_read_enable <= fifo_read_enable;
- buf_int_error_out <= next_int_error_out;
- buf_int_packet_nr_out <= next_int_packet_nr_out;
- else
- last_fifo_read_enable <= last_fifo_read_enable;
- buf_int_error_out <= buf_int_error_out;
- buf_int_packet_nr_out <= buf_int_packet_nr_out;
+ if rising_edge(CLK) then
+ if RESET_RECV = '1' then
+ last_fifo_read_enable <= '0';
+ buf_int_error_out <= ERROR_NC;
+ buf_int_packet_nr_out <= "00";
+ else
+ last_fifo_read_enable <= fifo_read_enable;
+ buf_int_error_out <= next_int_error_out;
+ buf_int_packet_nr_out <= next_int_packet_nr_out;
+ end if;
end if;
end process;
buf_comb_data_in(15 downto 0) <= fifo_data_out(15 downto 0);
buf_comb_data_in(17 downto 16) <= next_int_packet_nr_out;
+
SBUF_fifo_to_int : trb_net_sbuf
generic map(DATA_WIDTH => 18, VERSION => 0)
port map (
-- Sending data
-----------------------------------------------------------------------
-CONV_READ_IN <= DCM_LOCKED;
+buf_INT_READ_OUT <= not RESET_RECV;
+INT_READ_OUT <= buf_INT_READ_OUT;
--RESET_RECV <= RESET or not DCM_LOCKED or not MED_DATA_IN(11);
process(RESET,DCM_LOCKED,MED_DATA_IN(11))
end process;
- process(CONV_DATAREADY_OUT, CONV_DATA_OUT, CONV_PACKET_NR_OUT, CONV_READ_IN,
+ process(INT_DATAREADY_IN, INT_DATA_IN, INT_PACKET_NR_IN, buf_INT_READ_OUT,
send_data_byte1, send_data_byte2, send_packet1)
begin
next_send_data_byte1_parity <= '0'; --send_data_byte1_parity;
next_send_data_byte2_parity <= '0'; --send_data_byte2_parity;
next_send_packet1 <= '0';
- if CONV_DATAREADY_OUT = '1' and CONV_READ_IN = '1' then
- if CONV_PACKET_NR_OUT = "00" and send_packet1 = '0' then
+ if INT_DATAREADY_IN = '1' and buf_INT_READ_OUT = '1' then
+ if INT_PACKET_NR_IN = "00" and send_packet1 = '0' then
next_send_packet1 <= '1';
else
next_send_packet1 <= '0';
end if;
- next_send_data_byte1 <= CONV_DATA_OUT(15 downto 8);
- next_send_data_byte2 <= CONV_DATA_OUT(7 downto 0);
+ next_send_data_byte1 <= INT_DATA_IN(15 downto 8);
+ next_send_data_byte2 <= INT_DATA_IN(7 downto 0);
next_send_dataready <= '1';
- next_send_data_byte2_parity <= xor_all(CONV_DATA_OUT(7 downto 0));
- next_send_data_byte1_parity <= xor_all(CONV_DATA_OUT(15 downto 8));
+ next_send_data_byte2_parity <= xor_all(INT_DATA_IN(7 downto 0));
+ next_send_data_byte1_parity <= xor_all(INT_DATA_IN(15 downto 8));
end if;
end process;
process(CLK, RESET_RECV)
begin
- if RESET_RECV = '1' then
- send_data_byte1 <= (others => '0');
- send_data_byte2 <= (others => '0');
- send_data_byte1_parity <= '0';
- send_data_byte2_parity <= '0';
- send_dataready <= '0';
- send_packet1 <= '0';
- elsif rising_edge(CLK) then
- send_data_byte1 <= next_send_data_byte1 after 1 ns;
- send_data_byte2 <= next_send_data_byte2 after 1 ns;
- send_data_byte1_parity <= next_send_data_byte1_parity after 1 ns;
- send_data_byte2_parity <= next_send_data_byte2_parity after 1 ns;
- send_dataready <= next_send_dataready after 1 ns;
- send_packet1 <= next_send_packet1 after 1 ns;
- else
- send_data_byte1 <= send_data_byte1;
- send_data_byte2 <= send_data_byte2;
- send_data_byte1_parity <= send_data_byte1_parity;
- send_data_byte2_parity <= send_data_byte2_parity;
- send_dataready <= send_dataready;
- send_packet1 <= send_packet1;
+ if rising_edge(CLK) then
+ if RESET_RECV = '1' then
+ send_data_byte1 <= (others => '0');
+ send_data_byte2 <= (others => '0');
+ send_data_byte1_parity <= '0';
+ send_data_byte2_parity <= '0';
+ send_dataready <= '0';
+ send_packet1 <= '0';
+ else
+ send_data_byte1 <= next_send_data_byte1 after 1 ns;
+ send_data_byte2 <= next_send_data_byte2 after 1 ns;
+ send_data_byte1_parity <= next_send_data_byte1_parity after 1 ns;
+ send_data_byte2_parity <= next_send_data_byte2_parity after 1 ns;
+ send_dataready <= next_send_dataready after 1 ns;
+ send_packet1 <= next_send_packet1 after 1 ns;
+ end if;
end if;
end process;
jspc29 / trbnet.git / commitdiff