readme.txt explains usage.
Boris
--- /dev/null
+-- ***********************************************************************************
+-- ***********************************************************************************
+--
+-- CFG cell for FIFO controls
+-- --------------------------
+--
+-- [0] - reset
+-- [1] - ringbuffer
+-- [2] - check if differing input
+-- [3] - halt
+-- [4] - autowrite
+--
+-- ***********************************************************************************
+-- ***********************************************************************************
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.monitor_config.all;
+
+
+entity CFG_cell is
+ generic(
+ init : std_logic_vector(7 downto 0)
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ DATA_IN : in std_logic_vector(7 downto 0);
+ WRITE_IN : in std_logic;
+
+ DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0')
+ );
+end entity;
+
+architecture basic of CFG_cell is
+
+signal data, next_data : std_logic_vector(7 downto 0) := init;
+
+begin
+
+ DATA_OUT <= data;
+
+ p_write:process(WRITE_IN, RESET, data, DATA_IN)
+ begin
+ next_data <= data;
+ if RESET = '0' then
+ if WRITE_IN = '1' then
+ next_data <= DATA_IN;
+ end if;
+ end if;
+ end process;
+
+ proc_cell_logic : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ data <= next_data;
+ end if;
+ end process;
+
+end architecture;
\ No newline at end of file
--- /dev/null
+-- ***********************************************************************************
+-- ***********************************************************************************
+--
+-- FIFO storage cell
+-- -----------------
+--
+-- Architecture independent
+-- In order to assure architecture independence, set the ARCH constant
+-- in devmon_config.vhd
+-- The ARCH will be prepended to all FIFOs
+--
+-- -----------------------------------------------------------------------------------
+--
+-- TODO:
+-- -----
+-- Do fifo_reset only during 1 cycle and reset the cfg(0) to '0' after write
+-- Clean the unused signals
+--
+-- ***********************************************************************************
+-- ***********************************************************************************
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+library work;
+use work.monitor_config.all;
+use work.fifo_package.all;
+
+
+entity FIFO_cell is
+ generic(
+ fifo_type : String; -- The FIFO cell identifier, e.g. "32x512" or "8x16"
+ f_low : integer range 0 to 255; -- from 10 ns to 2560 ns, the automatic strobe signal
+ f_high : integer range 0 to 30; -- 10*2**2**f_high ns if this is set, f_low is ignored
+ t_res : integer range 0 to 31; -- from which bit on the timer will be taken
+ t_size : integer range 0 to 32; -- size of the timestamp in the package
+ d_size : integer range 0 to 32; -- size of data in the package
+ i_size : integer range 0 to 32 -- size of additional information from the external port in the package
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ DATA_IN : in std_logic_vector(FIFO_BUS-1 downto 0);
+ WRITE_IN : in std_logic;
+ READ_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(FIFO_BUS-1 downto 0) := (others => '0');
+ VALID_OUT : out std_logic := '0';
+ STATUS_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+
+ CFG_IN : in std_logic_vector(7 downto 0);
+ TIME_IN : in std_logic_vector(31 downto 0);
+ EXTERNAL_IN : in std_logic_vector(7 downto 0)
+ );
+end entity;
+
+architecture basic of FIFO_cell is
+
+signal fifo_data_in, next_fifo_data_in, fifo_data_out : std_logic_vector(31 downto 0) := (others => '0');
+signal timestamp, next_timestamp : std_logic_vector(31 downto 0) := (others => '0');
+signal next_fifo_read, fifo_read, fifo_reset, fifo_write, next_fifo_write, fifo_empty, fifo_full, fifo_valid : std_logic := '0';
+signal t1, t2, next_t1, next_t2 : std_logic := '0';
+signal next_reset : std_logic := '0';
+signal stored : std_logic_vector(15 downto 0) := (others => '0');
+signal check : std_logic := '0';
+
+signal timer, next_timer : integer := 0;
+signal stored_data, next_stored_data : std_logic_vector(FIFO_BUS-1 downto 0) := (others => '0');
+signal buf_data_in, next_buf_data_in : std_logic_vector(FIFO_BUS-1 downto 0) := (others => '0');
+signal autowrite, next_autowrite, write, next_write : std_logic := '0';
+signal hw_trigger, next_hw_trigger : std_logic := '0';
+signal buf_val_in, next_buf_val_in : std_logic := '0';
+signal buf_info_in, next_buf_info_in : std_logic_vector(7 downto 0) := x"00";
+
+begin
+
+ gen_virtex4: if ARCH="_virtex4" generate
+ gen_16x1024: if fifo_type = "fifo_16x1024" generate
+ the_16x1024_FIFO : virtex4_fifo_16x1024
+ port map(
+ clk => CLK,
+ din => fifo_data_in(15 downto 0),
+ rd_en => fifo_read,
+ rst => fifo_reset,
+ wr_en => fifo_write,
+ data_count => stored(9 downto 0),
+ dout => fifo_data_out(15 downto 0),
+ empty => fifo_empty,
+ full => fifo_full,
+ valid => fifo_valid
+ );
+ end generate;
+ gen_32x512: if fifo_type = "fifo_32x512 " generate
+ the_32x512_FIFO : virtex4_fifo_32x512
+ port map(
+ clk => CLK,
+ din => fifo_data_in(31 downto 0),
+ rd_en => fifo_read,
+ rst => fifo_reset,
+ wr_en => fifo_write,
+ data_count => stored(8 downto 0),
+ dout => fifo_data_out(31 downto 0),
+ empty => fifo_empty,
+ full => fifo_full,
+ valid => fifo_valid
+ );
+ end generate;
+ end generate;
+
+ gen_timestamp0: if t_size = 1 generate
+ next_timestamp(0) <= TIME_IN(t_res);
+ end generate;
+ gen_timestamp1: if t_size > 1 generate
+ next_timestamp(t_size-1 downto 0) <= TIME_IN(t_res + t_size - 1 downto t_res);
+ end generate;
+ proc_reg_timestamp: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ timestamp <= next_timestamp;
+ end if;
+ end process;
+
+ gen_fifo_data_no_info: if i_size = 0 generate
+ gen_timestamp_0: if t_size = 0 generate
+ next_fifo_data_in(d_size-1 downto 0) <= buf_data_in(d_size-1 downto 0);
+ end generate;
+ gen_timestamp_1: if t_size = 1 generate
+ next_fifo_data_in(d_size downto 0) <= timestamp(0) & buf_data_in(d_size-1 downto 0);
+ end generate;
+ gen_timestamp_others: if t_size > 1 generate
+ next_fifo_data_in(d_size+t_size-1 downto 0) <= timestamp(t_size-1 downto 0) & buf_data_in(d_size-1 downto 0);
+ end generate;
+ end generate;
+ gen_fifo_data_1_info: if i_size = 1 generate
+ gen_timestamp_0: if t_size = 0 generate
+ next_fifo_data_in(d_size downto 0) <= buf_info_in(0) & buf_data_in(d_size-1 downto 0);
+ end generate;
+ gen_timestamp_1: if t_size = 1 generate
+ next_fifo_data_in(d_size+1 downto 0) <= buf_info_in(0) & timestamp(0) & buf_data_in(d_size-1 downto 0);
+ end generate;
+ gen_timestamp_others: if t_size > 1 generate
+ next_fifo_data_in(d_size+t_size downto 0) <= buf_info_in(0) & timestamp(t_size-1 downto 0) & buf_data_in(d_size-1 downto 0);
+ end generate;
+ end generate;
+ gen_fifo_data_info: if i_size > 1 generate
+ gen_timestamp_0: if t_size = 0 generate
+ next_fifo_data_in(d_size+i_size-1 downto 0) <= buf_info_in(i_size-1 downto 0) & buf_data_in(d_size-1 downto 0);
+ end generate;
+ gen_timestamp_1: if t_size = 1 generate
+ next_fifo_data_in(d_size+i_size downto 0) <= buf_info_in(i_size-1 downto 0) & timestamp(0) & buf_data_in(d_size-1 downto 0);
+ end generate;
+ gen_timestamp_others: if t_size > 1 generate
+ next_fifo_data_in(d_size+t_size+i_size-1 downto 0) <= buf_info_in(i_size-1 downto 0) & timestamp(t_size-1 downto 0) & buf_data_in(d_size-1 downto 0);
+ end generate;
+ end generate;
+
+ p_autowrite: process(timer, RESET)
+ begin
+ if f_high = 0 then
+ if timer = f_low then
+ next_timer <= 0;
+ next_autowrite <= '1';
+ else
+ next_timer <= timer + 1;
+ next_autowrite <= '0';
+ end if;
+ else
+ if timer = (2**f_high)-1 then
+ next_timer <= 0;
+ next_autowrite <= '1';
+ else
+ next_timer <= timer + 1;
+ next_autowrite <= '0';
+ end if;
+ end if;
+
+ if RESET = '1' then
+ next_timer <= 0;
+ next_autowrite <= '0';
+ end if;
+ end process;
+
+ next_buf_data_in <= DATA_IN;
+ next_stored_data <= buf_data_in;
+ next_hw_trigger <= WRITE_IN;
+ next_buf_info_in <= EXTERNAL_IN;
+ proc_register_signals : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ write <= next_write;
+ autowrite <= next_autowrite;
+ fifo_write <= next_fifo_write;
+ timer <= next_timer;
+ stored_data <= next_stored_data;
+ hw_trigger <= next_hw_trigger;
+ buf_data_in <= next_buf_data_in;
+ buf_info_in <= next_buf_info_in;
+ fifo_data_in <= next_fifo_data_in;
+ end if;
+ end process;
+
+ next_fifo_write <= (autowrite and CFG_IN(4) and CFG_IN(2) and (fifo_empty) and (not CFG_IN(3)) and (not RESET))
+ or (autowrite and CFG_IN(4) and CFG_IN(2) and (not fifo_empty) and check and (not CFG_IN(3)) and (not RESET))
+ or (hw_trigger and (not CFG_IN(3)) and (not CFG_IN(2)) and (not RESET))
+ or (hw_trigger and (not CFG_IN(3)) and CFG_IN(2) and (not fifo_empty) and check and (not RESET))
+ or (hw_trigger and (not CFG_IN(3)) and CFG_IN(2) and fifo_empty and (not RESET))
+ or (autowrite and CFG_IN(4) and (not CFG_IN(2)) and (not CFG_IN(3)) and (not RESET));
+
+
+ check <= '0' when stored_data = buf_data_in else '1';
+-- p_compare:process(stored_data, buf_data_in)
+-- begin
+-- if stored_data = buf_data_in then
+-- check <= '0';
+-- else
+-- check <= '1';
+-- end if;
+-- end process;
+
+ proc_register_f : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ fifo_read <= next_fifo_read;
+ fifo_reset <= next_reset;
+ t1 <= next_t1;
+ t2 <= next_t2;
+ end if;
+ end process;
+
+ proc_cell_logic : process(stored, t1, t2, READ_IN, fifo_read, CFG_IN, RESET)
+ variable ALFULL : integer range 1 to 1024;
+ begin
+ if fifo_type = "fifo_32x512 " then
+ ALFULL := 508;
+ elsif fifo_type = "fifo_16x1024" then
+ ALFULL := 1020;
+ end if;
+
+ next_reset <= CFG_IN(0) or RESET;
+
+ -- RING BUFFER MODE
+ if CFG_IN(1) = '1' then
+ next_fifo_read <= '0';
+ next_t1 <= t1;
+ next_t2 <= t2;
+
+ if READ_IN = '1' then
+ next_fifo_read <= '1'; -- the real read
+ next_t1 <= '0'; -- mark as real
+ else
+ if std_logic_vector(to_unsigned(ALFULL,16)) < stored then -- the fifo is 'almost' full
+ next_fifo_read <= '1'; -- the fake read
+ next_t1 <= '1'; -- mark as fake
+ else
+ next_t1 <= '0'; -- no real or fake read, so reset the marker
+ end if;
+ end if;
+
+ if fifo_read = '1' then
+ if t1 = '1' then
+ next_t2 <= '1'; -- propagate the marker
+ else
+ next_t2 <= '0'; -- no fake read, so reset the second marker
+ end if;
+ end if;
+
+ -- NORMAL MODE
+ else
+ next_t1 <= '0';
+ next_t2 <= '0';
+
+ next_fifo_read <= READ_IN;
+
+ end if;
+
+ if RESET = '1' then
+ next_t1 <= '0';
+ next_t2 <= '0';
+ next_fifo_read <= '0';
+ end if;
+ end process;
+
+ p_valid:process(fifo_valid, t2)
+ begin
+ if fifo_valid = '1' then
+ VALID_OUT <= not t2;
+ else
+ VALID_OUT <= '0';
+ end if;
+ end process;
+
+ DATA_OUT <= fifo_data_out(FIFO_BUS-1 downto 0);
+
+ STATUS_OUT(0) <= fifo_full;
+ STATUS_OUT(1) <= fifo_empty;
+
+ -- DEBUG
+ STATUS_OUT(2) <= autowrite;
+ STATUS_OUT(3) <= fifo_write;
+ STATUS_OUT(4) <= fifo_read;
+ STATUS_OUT(5) <= fifo_data_in(0);
+ STATUS_OUT(6) <= fifo_data_in(1);
+ STATUS_OUT(7) <= fifo_data_in(2);
+
+end architecture;
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+
+
+package fifo_package is
+
+
+component virtex4_fifo_16x1024 IS
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(15 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(9 downto 0);
+ dout: OUT std_logic_VECTOR(15 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ valid: OUT std_logic);
+END component;
+
+component virtex4_fifo_32x512 IS
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(31 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(8 downto 0);
+ dout: OUT std_logic_VECTOR(31 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ valid: OUT std_logic);
+END component;
+
+
+
+
+end package fifo_package;
+
+
+
+package body fifo_package is
+
+end package body fifo_package;
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$2ga
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\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2009 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file virtex4_fifo_16x1024.vhd when simulating
+-- the core, virtex4_fifo_16x1024. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY virtex4_fifo_16x1024 IS
+ port (
+ clk: IN std_logic;
+ rst: IN std_logic;
+ din: IN std_logic_VECTOR(15 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(15 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic;
+ valid: OUT std_logic;
+ data_count: OUT std_logic_VECTOR(9 downto 0));
+END virtex4_fifo_16x1024;
+
+ARCHITECTURE virtex4_fifo_16x1024_a OF virtex4_fifo_16x1024 IS
+-- synthesis translate_off
+component wrapped_virtex4_fifo_16x1024
+ port (
+ clk: IN std_logic;
+ rst: IN std_logic;
+ din: IN std_logic_VECTOR(15 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(15 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic;
+ valid: OUT std_logic;
+ data_count: OUT std_logic_VECTOR(9 downto 0));
+end component;
+
+-- Configuration specification
+ for all : wrapped_virtex4_fifo_16x1024 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
+ generic map(
+ c_has_int_clk => 0,
+ c_wr_response_latency => 1,
+ c_rd_freq => 1,
+ c_has_srst => 0,
+ c_enable_rst_sync => 1,
+ c_has_rd_data_count => 0,
+ c_din_width => 16,
+ c_has_wr_data_count => 0,
+ c_full_flags_rst_val => 0,
+ c_implementation_type => 0,
+ c_family => "virtex4",
+ c_use_embedded_reg => 0,
+ c_has_wr_rst => 0,
+ c_wr_freq => 1,
+ c_use_dout_rst => 1,
+ c_underflow_low => 0,
+ c_has_meminit_file => 0,
+ c_has_overflow => 0,
+ c_preload_latency => 1,
+ c_dout_width => 16,
+ c_msgon_val => 1,
+ c_rd_depth => 1024,
+ c_default_value => "BlankString",
+ c_mif_file_name => "BlankString",
+ c_error_injection_type => 0,
+ c_has_underflow => 0,
+ c_has_rd_rst => 0,
+ c_has_almost_full => 0,
+ c_has_rst => 1,
+ c_data_count_width => 10,
+ c_has_wr_ack => 0,
+ c_use_ecc => 0,
+ c_wr_ack_low => 0,
+ c_common_clock => 1,
+ c_rd_pntr_width => 10,
+ c_use_fwft_data_count => 0,
+ c_has_almost_empty => 0,
+ c_rd_data_count_width => 10,
+ c_enable_rlocs => 0,
+ c_wr_pntr_width => 10,
+ c_overflow_low => 0,
+ c_prog_empty_type => 0,
+ c_optimization_mode => 0,
+ c_wr_data_count_width => 10,
+ c_preload_regs => 0,
+ c_dout_rst_val => "0",
+ c_has_data_count => 1,
+ c_prog_full_thresh_negate_val => 1021,
+ c_wr_depth => 1024,
+ c_prog_empty_thresh_negate_val => 3,
+ c_prog_empty_thresh_assert_val => 2,
+ c_has_valid => 1,
+ c_init_wr_pntr_val => 0,
+ c_prog_full_thresh_assert_val => 1022,
+ c_use_fifo16_flags => 0,
+ c_has_backup => 0,
+ c_valid_low => 0,
+ c_prim_fifo_type => "1kx18",
+ c_count_type => 0,
+ c_prog_full_type => 0,
+ c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_virtex4_fifo_16x1024
+ port map (
+ clk => clk,
+ rst => rst,
+ din => din,
+ wr_en => wr_en,
+ rd_en => rd_en,
+ dout => dout,
+ full => full,
+ empty => empty,
+ valid => valid,
+ data_count => data_count);
+-- synthesis translate_on
+
+END virtex4_fifo_16x1024_a;
+
--- /dev/null
+##############################################################
+#
+# Xilinx Core Generator version 12.3
+# Date: Thu Apr 28 15:37:14 2011
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc4vlx40
+SET devicefamily = virtex4
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = ff1148
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -10
+SET verilogsim = true
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.2
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=virtex4_fifo_16x1024
+CSET data_count=true
+CSET data_count_width=10
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_negate_value=3
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Common_Clock_Block_RAM
+CSET full_flags_reset_value=0
+CSET full_threshold_assert_value=1022
+CSET full_threshold_negate_value=1021
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=16
+CSET input_depth=1024
+CSET output_data_width=16
+CSET output_depth=1024
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=10
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=true
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=10
+# END Parameters
+GENERATE
+# CRC: 1af5cd03
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="virtex4_fifo_16x1024.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ </file>
+ <file xil_pn:name="virtex4_fifo_16x1024.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ <association xil_pn:name="PostMapSimulation"/>
+ <association xil_pn:name="PostRouteSimulation"/>
+ <association xil_pn:name="PostTranslateSimulation"/>
+ </file>
+ <file xil_pn:name="virtex4_fifo_16x1024.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ <association xil_pn:name="PostMapSimulation"/>
+ <association xil_pn:name="PostRouteSimulation"/>
+ <association xil_pn:name="PostTranslateSimulation"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc4vlx40" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex4" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|virtex4_fifo_16x1024|virtex4_fifo_16x1024_a" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="virtex4_fifo_16x1024.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/virtex4_fifo_16x1024" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff1148" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="virtex4_fifo_16x1024" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex4" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-04-28T17:37:16" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B24B3B152EB46CD7CE166A84F1467894" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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\7f~yxFGKr=hh7h=564g`7{GHKq;qMN_{|BC
\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2009 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file virtex4_fifo_32x512.vhd when simulating
+-- the core, virtex4_fifo_32x512. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY virtex4_fifo_32x512 IS
+ port (
+ clk: IN std_logic;
+ rst: IN std_logic;
+ din: IN std_logic_VECTOR(31 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(31 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic;
+ valid: OUT std_logic;
+ data_count: OUT std_logic_VECTOR(8 downto 0));
+END virtex4_fifo_32x512;
+
+ARCHITECTURE virtex4_fifo_32x512_a OF virtex4_fifo_32x512 IS
+-- synthesis translate_off
+component wrapped_virtex4_fifo_32x512
+ port (
+ clk: IN std_logic;
+ rst: IN std_logic;
+ din: IN std_logic_VECTOR(31 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(31 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic;
+ valid: OUT std_logic;
+ data_count: OUT std_logic_VECTOR(8 downto 0));
+end component;
+
+-- Configuration specification
+ for all : wrapped_virtex4_fifo_32x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
+ generic map(
+ c_has_int_clk => 0,
+ c_wr_response_latency => 1,
+ c_rd_freq => 1,
+ c_has_srst => 0,
+ c_enable_rst_sync => 1,
+ c_has_rd_data_count => 0,
+ c_din_width => 32,
+ c_has_wr_data_count => 0,
+ c_full_flags_rst_val => 0,
+ c_implementation_type => 0,
+ c_family => "virtex4",
+ c_use_embedded_reg => 0,
+ c_has_wr_rst => 0,
+ c_wr_freq => 1,
+ c_use_dout_rst => 1,
+ c_underflow_low => 0,
+ c_has_meminit_file => 0,
+ c_has_overflow => 0,
+ c_preload_latency => 1,
+ c_dout_width => 32,
+ c_msgon_val => 1,
+ c_rd_depth => 512,
+ c_default_value => "BlankString",
+ c_mif_file_name => "BlankString",
+ c_error_injection_type => 0,
+ c_has_underflow => 0,
+ c_has_rd_rst => 0,
+ c_has_almost_full => 0,
+ c_has_rst => 1,
+ c_data_count_width => 9,
+ c_has_wr_ack => 0,
+ c_use_ecc => 0,
+ c_wr_ack_low => 0,
+ c_common_clock => 1,
+ c_rd_pntr_width => 9,
+ c_use_fwft_data_count => 0,
+ c_has_almost_empty => 0,
+ c_rd_data_count_width => 9,
+ c_enable_rlocs => 0,
+ c_wr_pntr_width => 9,
+ c_overflow_low => 0,
+ c_prog_empty_type => 0,
+ c_optimization_mode => 0,
+ c_wr_data_count_width => 9,
+ c_preload_regs => 0,
+ c_dout_rst_val => "0",
+ c_has_data_count => 1,
+ c_prog_full_thresh_negate_val => 509,
+ c_wr_depth => 512,
+ c_prog_empty_thresh_negate_val => 3,
+ c_prog_empty_thresh_assert_val => 2,
+ c_has_valid => 1,
+ c_init_wr_pntr_val => 0,
+ c_prog_full_thresh_assert_val => 510,
+ c_use_fifo16_flags => 0,
+ c_has_backup => 0,
+ c_valid_low => 0,
+ c_prim_fifo_type => "512x36",
+ c_count_type => 0,
+ c_prog_full_type => 0,
+ c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_virtex4_fifo_32x512
+ port map (
+ clk => clk,
+ rst => rst,
+ din => din,
+ wr_en => wr_en,
+ rd_en => rd_en,
+ dout => dout,
+ full => full,
+ empty => empty,
+ valid => valid,
+ data_count => data_count);
+-- synthesis translate_on
+
+END virtex4_fifo_32x512_a;
+
--- /dev/null
+##############################################################
+#
+# Xilinx Core Generator version 12.3
+# Date: Thu Apr 28 15:34:00 2011
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc4vlx40
+SET devicefamily = virtex4
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = ff1148
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -10
+SET verilogsim = true
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.2
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=virtex4_fifo_32x512
+CSET data_count=true
+CSET data_count_width=9
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_negate_value=3
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Common_Clock_Block_RAM
+CSET full_flags_reset_value=0
+CSET full_threshold_assert_value=510
+CSET full_threshold_negate_value=509
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=32
+CSET input_depth=512
+CSET output_data_width=32
+CSET output_depth=512
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=9
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=true
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=9
+# END Parameters
+GENERATE
+# CRC: c40666b3
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="virtex4_fifo_32x512.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ </file>
+ <file xil_pn:name="virtex4_fifo_32x512.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ <association xil_pn:name="PostMapSimulation"/>
+ <association xil_pn:name="PostRouteSimulation"/>
+ <association xil_pn:name="PostTranslateSimulation"/>
+ </file>
+ <file xil_pn:name="virtex4_fifo_32x512.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ <association xil_pn:name="PostMapSimulation"/>
+ <association xil_pn:name="PostRouteSimulation"/>
+ <association xil_pn:name="PostTranslateSimulation"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc4vlx40" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex4" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|virtex4_fifo_32x512|virtex4_fifo_32x512_a" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="virtex4_fifo_32x512.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/virtex4_fifo_32x512" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff1148" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="virtex4_fifo_32x512" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex4" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-04-28T17:34:02" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BB4FCDE6B8FAAE3990DCCC7CCC391598" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
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\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file virtex4_fifo_16x1024.vhd when simulating
+-- the core, virtex4_fifo_16x1024. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY virtex4_fifo_16x1024 IS
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(15 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(9 downto 0);
+ dout: OUT std_logic_VECTOR(15 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ valid: OUT std_logic);
+END virtex4_fifo_16x1024;
+
+ARCHITECTURE virtex4_fifo_16x1024_a OF virtex4_fifo_16x1024 IS
+-- synthesis translate_off
+component wrapped_virtex4_fifo_16x1024
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(15 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(9 downto 0);
+ dout: OUT std_logic_VECTOR(15 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ valid: OUT std_logic);
+end component;
+
+-- Configuration specification
+ for all : wrapped_virtex4_fifo_16x1024 use entity XilinxCoreLib.fifo_generator_v4_2(behavioral)
+ generic map(
+ c_has_int_clk => 0,
+ c_rd_freq => 1,
+ c_wr_response_latency => 1,
+ c_has_srst => 0,
+ c_has_rd_data_count => 0,
+ c_din_width => 16,
+ c_has_wr_data_count => 0,
+ c_full_flags_rst_val => 1,
+ c_implementation_type => 0,
+ c_family => "virtex4",
+ c_use_embedded_reg => 0,
+ c_has_wr_rst => 0,
+ c_wr_freq => 1,
+ c_use_dout_rst => 1,
+ c_underflow_low => 0,
+ c_has_meminit_file => 0,
+ c_has_overflow => 0,
+ c_preload_latency => 1,
+ c_dout_width => 16,
+ c_rd_depth => 1024,
+ c_default_value => "BlankString",
+ c_mif_file_name => "BlankString",
+ c_has_underflow => 0,
+ c_has_rd_rst => 0,
+ c_has_almost_full => 0,
+ c_has_rst => 1,
+ c_data_count_width => 10,
+ c_has_wr_ack => 0,
+ c_use_ecc => 0,
+ c_wr_ack_low => 0,
+ c_common_clock => 1,
+ c_rd_pntr_width => 10,
+ c_use_fwft_data_count => 0,
+ c_has_almost_empty => 0,
+ c_rd_data_count_width => 10,
+ c_enable_rlocs => 0,
+ c_wr_pntr_width => 10,
+ c_overflow_low => 0,
+ c_prog_empty_type => 0,
+ c_optimization_mode => 0,
+ c_wr_data_count_width => 10,
+ c_preload_regs => 0,
+ c_dout_rst_val => "0",
+ c_has_data_count => 1,
+ c_prog_full_thresh_negate_val => 1021,
+ c_wr_depth => 1024,
+ c_prog_empty_thresh_negate_val => 3,
+ c_prog_empty_thresh_assert_val => 2,
+ c_has_valid => 1,
+ c_init_wr_pntr_val => 0,
+ c_prog_full_thresh_assert_val => 1022,
+ c_use_fifo16_flags => 0,
+ c_has_backup => 0,
+ c_valid_low => 0,
+ c_prim_fifo_type => "1kx18",
+ c_count_type => 0,
+ c_prog_full_type => 0,
+ c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_virtex4_fifo_16x1024
+ port map (
+ clk => clk,
+ din => din,
+ rd_en => rd_en,
+ rst => rst,
+ wr_en => wr_en,
+ data_count => data_count,
+ dout => dout,
+ empty => empty,
+ full => full,
+ valid => valid);
+-- synthesis translate_on
+
+END virtex4_fifo_16x1024_a;
+
--- /dev/null
+##############################################################
+#
+# Xilinx Core Generator version J.40
+# Date: Mon Mar 14 21:55:36 2011
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc4vlx40
+SET devicefamily = virtex4
+SET flowvendor = Foundation_iSE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = ff1148
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -10
+SET verilogsim = True
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.2
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=virtex4_fifo_16x1024
+CSET data_count=true
+CSET data_count_width=10
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_negate_value=3
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Common_Clock_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=1022
+CSET full_threshold_negate_value=1021
+CSET input_data_width=16
+CSET input_depth=1024
+CSET output_data_width=16
+CSET output_depth=1024
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=10
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=true
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=10
+# END Parameters
+GENERATE
+# CRC: 29ee2935
+
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
+$53b
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\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file virtex4_fifo_32x512.vhd when simulating
+-- the core, virtex4_fifo_32x512. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY virtex4_fifo_32x512 IS
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(31 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(8 downto 0);
+ dout: OUT std_logic_VECTOR(31 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ valid: OUT std_logic);
+END virtex4_fifo_32x512;
+
+ARCHITECTURE virtex4_fifo_32x512_a OF virtex4_fifo_32x512 IS
+-- synthesis translate_off
+component wrapped_virtex4_fifo_32x512
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(31 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(8 downto 0);
+ dout: OUT std_logic_VECTOR(31 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ valid: OUT std_logic);
+end component;
+
+-- Configuration specification
+ for all : wrapped_virtex4_fifo_32x512 use entity XilinxCoreLib.fifo_generator_v4_2(behavioral)
+ generic map(
+ c_has_int_clk => 0,
+ c_rd_freq => 1,
+ c_wr_response_latency => 1,
+ c_has_srst => 0,
+ c_has_rd_data_count => 0,
+ c_din_width => 32,
+ c_has_wr_data_count => 0,
+ c_full_flags_rst_val => 1,
+ c_implementation_type => 0,
+ c_family => "virtex4",
+ c_use_embedded_reg => 0,
+ c_has_wr_rst => 0,
+ c_wr_freq => 1,
+ c_use_dout_rst => 0,
+ c_underflow_low => 0,
+ c_has_meminit_file => 0,
+ c_has_overflow => 0,
+ c_preload_latency => 1,
+ c_dout_width => 32,
+ c_rd_depth => 512,
+ c_default_value => "BlankString",
+ c_mif_file_name => "BlankString",
+ c_has_underflow => 0,
+ c_has_rd_rst => 0,
+ c_has_almost_full => 0,
+ c_has_rst => 1,
+ c_data_count_width => 9,
+ c_has_wr_ack => 0,
+ c_use_ecc => 0,
+ c_wr_ack_low => 0,
+ c_common_clock => 1,
+ c_rd_pntr_width => 9,
+ c_use_fwft_data_count => 0,
+ c_has_almost_empty => 0,
+ c_rd_data_count_width => 9,
+ c_enable_rlocs => 0,
+ c_wr_pntr_width => 9,
+ c_overflow_low => 0,
+ c_prog_empty_type => 0,
+ c_optimization_mode => 0,
+ c_wr_data_count_width => 9,
+ c_preload_regs => 0,
+ c_dout_rst_val => "0",
+ c_has_data_count => 1,
+ c_prog_full_thresh_negate_val => 509,
+ c_wr_depth => 512,
+ c_prog_empty_thresh_negate_val => 3,
+ c_prog_empty_thresh_assert_val => 2,
+ c_has_valid => 1,
+ c_init_wr_pntr_val => 0,
+ c_prog_full_thresh_assert_val => 510,
+ c_use_fifo16_flags => 0,
+ c_has_backup => 0,
+ c_valid_low => 0,
+ c_prim_fifo_type => "512x36",
+ c_count_type => 0,
+ c_prog_full_type => 0,
+ c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_virtex4_fifo_32x512
+ port map (
+ clk => clk,
+ din => din,
+ rd_en => rd_en,
+ rst => rst,
+ wr_en => wr_en,
+ data_count => data_count,
+ dout => dout,
+ empty => empty,
+ full => full,
+ valid => valid);
+-- synthesis translate_on
+
+END virtex4_fifo_32x512_a;
+
--- /dev/null
+##############################################################
+#
+# Xilinx Core Generator version J.40
+# Date: Mon Mar 14 21:50:44 2011
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc4vlx40
+SET devicefamily = virtex4
+SET flowvendor = Foundation_iSE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = ff1148
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -10
+SET verilogsim = True
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.2
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=virtex4_fifo_32x512
+CSET data_count=true
+CSET data_count_width=9
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_negate_value=3
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Common_Clock_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=510
+CSET full_threshold_negate_value=509
+CSET input_data_width=32
+CSET input_depth=512
+CSET output_data_width=32
+CSET output_depth=512
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=9
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=false
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=true
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=9
+# END Parameters
+GENERATE
+# CRC: dde0f5a5
+
--- /dev/null
+-- ***********************************************************************************
+-- ***********************************************************************************
+--
+-- Borislav Milanovic
+--
+-- Version: 4.0
+-- -------------
+--
+-- ***********************************************************************************
+-- ***********************************************************************************
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+library work;
+use work.monitor_config.all;
+
+
+
+entity monitor is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ ADDR_IN : in std_logic_vector(9 downto 0); -- ADDR> bit 9,8 for selection, bits 7 - 0 for the cell address
+ READ_IN : in std_logic; -- READ a cell
+ WRITE_IN : in std_logic; -- WRITE CFG (FIFO control register)
+ DATA_IN : in std_logic_vector(7 downto 0); -- CFG data
+
+ DATA_OUT : out std_logic_vector(EXT_BUS-1 downto 0) := (others => '0'); -- Monitoring cell contents
+ VALID_OUT : out std_logic := '0'; -- Valid signal
+
+ STATUS_OUT : out std_logic_vector(7 downto 0) := "00000000"; -- Bits: 0-Unknown_Address, 1-EMPTY, 2-ACK, 5-Wrong_Address_Scope
+
+ -- DATA Connections
+ FIFO_DATA_IN : in std_logic_vector( (FIFO_BUS*FIFO_NUM)-1 downto 0 ); -- combined FIFO data
+ FIFO_WRITE_IN : in std_logic_vector( FIFO_NUM-1 downto 0 ); -- combined FIFO valid
+ REG_DATA_IN : in std_logic_vector( (REG_BUS*REG_NUM)-1 downto 0 ); -- combined RED data
+
+ -- TIMERS
+ TIMER0_IN : in std_logic_vector(31 downto 0);
+ TIMER1_IN : in std_logic_vector( 7 downto 0);
+ TIMER2_IN : in std_logic_vector(31 downto 0);
+
+ EXTERNAL_STAMP_IN : in std_logic_vector(7 downto 0); -- additional data marker (in addition to timestamp)
+
+ DEBUG_OUT : out std_logic_vector(31 downto 0) -- Status, tests, etc
+ );
+end entity;
+
+
+
+architecture basic of monitor is
+
+ component REG_cell is
+ generic(
+ width : integer range 1 to 32 := 32
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ DATA_IN : in std_logic_vector(REG_BUS-1 downto 0);
+ DATA_OUT : out std_logic_vector(REG_BUS-1 downto 0)
+ );
+ end component;
+
+ component FIFO_cell is
+ generic(
+ fifo_type : String; -- The FIFO cell identifier, e.g. "32x512" or "8x16"
+ f_low : integer range 0 to 255; -- from 10 ns to 2560 ns, the automatic strobe signal
+ f_high : integer range 0 to 30; -- 10*2**2**f_high ns if this is set, f_low is ignored
+ t_res : integer range 0 to 31; -- from which bit on the timer will be taken
+ t_size : integer range 0 to 32; -- size of the timestamp in the package
+ d_size : integer range 0 to 32; -- size of data in the package
+ i_size : integer range 0 to 32 -- size of additional information from the external port in the package
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ DATA_IN : in std_logic_vector(FIFO_BUS-1 downto 0);
+ WRITE_IN : in std_logic;
+ READ_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(FIFO_BUS-1 downto 0) := (others => '0');
+ VALID_OUT : out std_logic := '0';
+ STATUS_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+
+ CFG_IN : in std_logic_vector(7 downto 0);
+ TIME_IN : in std_logic_vector(31 downto 0);
+ EXTERNAL_IN : in std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ component CFG_cell is
+ generic(
+ init : std_logic_vector(7 downto 0)
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ DATA_IN : in std_logic_vector(7 downto 0);
+ WRITE_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ component rom_32x113 is
+ port(
+ CLK: IN std_logic;
+ ADDR_IN: IN std_logic_VECTOR(8 downto 0);
+ DATA_OUT: OUT std_logic_VECTOR(31 downto 0)
+ );
+ end component;
+
+ component reg_mux is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ READ_IN : in std_logic;
+ ADDR_IN : in std_logic_vector(7 downto 0);
+
+ DATA_OUT : out std_logic_vector(REG_BUS-1 downto 0);
+ VALID_OUT : out std_logic;
+ STATUS_OUT : out std_logic_vector(7 downto 0) := "00000000";
+
+ DATA_IN : in std_logic_vector( (REG_NUM*REG_BUS)-1 downto 0)
+ );
+ end component;
+
+ component cfg_mux is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ WRITE_IN : in std_logic;
+ DATA_IN : in std_logic_vector(7 downto 0);
+ ADDR_IN : in std_logic_vector(7 downto 0);
+
+ DATA_OUT : out std_logic_vector(8*FIFO_NUM-1 downto 0);
+ WRITE_OUT : out std_logic_vector( FIFO_NUM-1 downto 0);
+
+ STATUS_OUT : out std_logic_vector(7 downto 0) := "00000000"
+ );
+ end component;
+
+ component fifo_mux is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ READ_IN : in std_logic; -- Slow Control READ
+ ADDR_IN : in std_logic_vector(7 downto 0); -- Slow Control ADDR
+
+ READ_OUT : out std_logic_vector(FIFO_NUM-1 downto 0); -- MUX-to-FIFO READ
+
+ DATA_IN : in std_logic_vector(FIFO_NUM*FIFO_BUS-1 downto 0); -- FIFO data
+ VALID_IN : in std_logic_vector(FIFO_NUM-1 downto 0); -- FIFO valid
+ STATUS_IN : in std_logic_vector(8*FIFO_NUM-1 downto 0); -- FIFO stats
+
+ DATA_OUT : out std_logic_vector(FIFO_BUS-1 downto 0); -- MUX Data as received from the FIFO
+ VALID_OUT : out std_logic; -- MUX Valid
+ STATUS_OUT : out std_logic_vector(7 downto 0) := "00000000" -- MUX status bits
+ );
+ end component;
+
+ component etrax_controls is
+ port(
+
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ MODE_IN : in std_logic; -- either store all 7 subsequent outputs on trigger (repeater mode), or only when trigger occurs (trigger mode)
+ DATA_IN : in std_logic_vector(31 downto 0); -- the data that should be written to etrax registers 0-7
+
+ CTRL_IN : in std_logic_vector(31 downto 0); -- specific trigger pattern to trigger at
+ ETRAX_OUT : out std_logic_vector(8*32-1 downto 0) -- the output is written to ETRAX Regs
+
+ );
+ end component;
+
+
+
+-- General drivers
+signal combined_fifo_read : std_logic_vector(FIFO_NUM-1 downto 0) := (others => '0');
+signal combined_fifo_data : std_logic_vector(FIFO_NUM*FIFO_BUS-1 downto 0) := (others => '0');
+signal combined_fifo_val : std_logic_vector(FIFO_NUM-1 downto 0) := (others => '0');
+signal combined_fifo_status : std_logic_vector(8*FIFO_NUM-1 downto 0) := (others => '0');
+signal combined_reg_data : std_logic_vector(REG_NUM*REG_BUS-1 downto 0) := (others => '0');
+signal combined_cfg_data_in, combined_cfg_data_out : std_logic_vector(8*FIFO_NUM-1 downto 0) := (others => '0');
+signal combined_cfg_write : std_logic_vector (FIFO_NUM-1 downto 0) := (others => '0');
+signal fifo_timer_bus : std_logic_vector(FIFO_NUM*32-1 downto 0 ) := (others => '0');
+signal main_status, next_main_status, cfg_status, reg_status, fifo_status : std_logic_vector (7 downto 0) := "00000000";
+signal s_cfg, s_fifo, s_reg, s_rom : std_logic := '0';
+signal reg_data, fifo_data : std_logic_vector(EXT_BUS-1 downto 0) := (others => '0');
+signal reg_valid, fifo_valid : std_logic := '0';
+
+-- TODO (fix these)
+-- handle correct ROM access
+-- signal rom_read, rom_dataready : std_logic := '0';
+-- signal rom_addr : std_logic_vector(8 downto 0);
+-- signal rom_data : std_logic_vector(31 downto 0);
+-- -- The multiplexer signals (CFG,FIFO,REG)
+-- signal mux_read_2,mux_read_3, mux_write_1, mux_timeout_2, mux_dataready_2, mux_dataready_3, mux_ack_1, mux_nomore_2, mux_unknown_1, mux_unknown_2, mux_unknown_3 : std_logic := '0';
+-- signal mux_data_out_2,mux_data_out_3 : std_logic_vector(31 downto 0);
+-- signal mux_addr_1,mux_addr_2,mux_addr_3 : std_logic_vector(15 downto 0);
+-- signal mux_data_in_1 : std_logic_vector(CFG_WIDTH-1 downto 0);
+-- --DUMMY
+-- signal dummy_cfg : std_logic_vector(32-CFG_WIDTH-1 downto 0) := (others => '0');
+-- signal dummy_input_bit, rom_dummy_bit, bus_timeout_dummy, fifo_write_dummy : std_logic := '0';
+-- signal dummy_input_vector, bus_data_dummy, reg_data_dummy, cfg_data_dummy, fifo_data_dummy, dummy_stats : std_logic_vector(31 downto 0) := (others => '0');
+-- signal bus_addr_dummy : std_logic_vector(6 downto 0) := (others => '0');
+-- signal reg_write_dummy, reg_ack_dummy, reg_nomore_dummy, reg_timeout_dummy : std_logic := '0';
+-- signal cfg_read_dummy, cfg_timeout_dummy, cfg_rdy_dummy, cfg_nomore_dummy : std_logic := '0';
+-- signal dummy24 : std_logic_vector(23 downto 0) := (others => '0');
+--signal test_bus : std_logic_vector(32*(SIGNAL_NUM+1)-1 downto 0);
+
+
+begin
+
+
+
+-- proc_rom_ctrl : process(CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- rom_dataready <= rom_read;
+-- end if;
+-- end process;
+
+
+ gen_fifos : for i in 0 to FIFO_NUM-1 generate
+ the_FIFO : FIFO_cell
+ generic map(
+ fifo_type => fifos(i).fifo_type,
+ f_low => fifos(i).f_low,
+ f_high => fifos(i).f_high,
+ t_res => fifos(i).t_res,
+ t_size => fifos(i).t_size,
+ d_size => fifos(i).d_size,
+ i_size => fifos(i).i_size
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+
+ DATA_IN => FIFO_DATA_IN(FIFO_BUS*(i+1)-1 downto FIFO_BUS*i),
+ WRITE_IN => FIFO_WRITE_IN(i),
+ READ_IN => combined_fifo_read(i),
+ DATA_OUT => combined_fifo_data(FIFO_BUS*(i+1)-1 downto FIFO_BUS*i),
+ VALID_OUT => combined_fifo_val(i),
+ STATUS_OUT => combined_fifo_status(8*(i+1)-1 downto 8*i),
+
+ CFG_IN => combined_cfg_data_out(8*(i+1)-1 downto 8*i),
+ TIME_IN => fifo_timer_bus(32*(i+1)-1 downto 32*i),
+ EXTERNAL_IN => EXTERNAL_STAMP_IN
+ );
+ end generate;
+
+ gen_fifo_timer_bus : for i in 0 to FIFO_NUM-1 generate
+ gen_ftimertype1 : if fifos(i).timer = 0 generate
+ fifo_timer_bus(32*(i+1)-1 downto 32*i) <= TIMER0_IN;
+ end generate;
+ gen_ftimertype2 : if fifos(i).timer = 1 generate
+ fifo_timer_bus(32*(i+1)-1 downto 32*i+8) <= (others => '0');
+ fifo_timer_bus(32*(i)+7 downto 32*i) <= TIMER1_IN;
+ end generate;
+ gen_ftimertype3 : if fifos(i).timer = 2 generate
+ fifo_timer_bus(32*(i+1)-1 downto 32*i) <= TIMER2_IN;
+ end generate;
+ end generate;
+
+ gen_registers : for i in 0 to REG_NUM-1 generate
+ the_REG : REG_cell
+ generic map(
+ width => regs(i).width
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+
+ DATA_IN => REG_DATA_IN(REG_BUS*(i+1)-1 downto REG_BUS*i),
+ DATA_OUT => combined_reg_data(REG_BUS*(i+1)-1 downto REG_BUS*i)
+ );
+ end generate;
+
+ gen_cfg_cells : for i in 0 to FIFO_NUM-1 generate
+ the_CFG : CFG_cell
+ generic map(
+ init => cfgs(i).init
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+
+ DATA_IN => combined_cfg_data_in(8*(i+1)-1 downto 8*i),
+ WRITE_IN => combined_cfg_write(i),
+ DATA_OUT => combined_cfg_data_out(8*(i+1)-1 downto 8*i)
+ );
+ end generate;
+
+-- the_ROM : rom_32x113
+-- port map(
+-- CLK => CLK,
+-- ADDR_IN => rom_addr,
+-- DATA_OUT => rom_data
+-- );
+
+ the_cfg_mux : cfg_mux
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+
+ WRITE_IN => s_cfg,
+ DATA_IN => DATA_IN,
+ ADDR_IN => ADDR_IN(7 downto 0),
+
+ DATA_OUT => combined_cfg_data_in,
+ WRITE_OUT => combined_cfg_write,
+
+ STATUS_OUT => cfg_status
+ );
+
+ the_reg_mux : reg_mux
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+
+ READ_IN => s_reg,
+ ADDR_IN => ADDR_IN(7 downto 0),
+ DATA_IN => combined_reg_data,
+
+ DATA_OUT => reg_data,
+ VALID_OUT => reg_valid,
+
+ STATUS_OUT => reg_status
+ );
+
+ the_fifo_mux : fifo_mux
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+
+ READ_IN => s_fifo,
+ ADDR_IN => ADDR_IN(7 downto 0),
+
+ READ_OUT => combined_fifo_read,
+
+ DATA_IN => combined_fifo_data,
+ VALID_IN => combined_fifo_val,
+ STATUS_IN => combined_fifo_status,
+
+ DATA_OUT => fifo_data,
+ VALID_OUT => fifo_valid,
+ STATUS_OUT => fifo_status
+ );
+
+ p_MUX_RW:process(ADDR_IN, READ_IN, WRITE_IN)
+ begin
+ next_main_status(5) <= '0'; -- Wrong Address Range for the Read/Write
+ if READ_IN = '1' then
+ if ADDR_IN(9 downto 8) = "00" then
+ s_rom <= '1';
+ s_cfg <= '0';
+ s_fifo <= '0';
+ s_reg <= '0';
+ elsif ADDR_IN(9 downto 8) = "10" then
+ s_rom <= '0';
+ s_cfg <= '0';
+ s_fifo <= '1';
+ s_reg <= '0';
+ elsif ADDR_IN(9 downto 8) = "11" then
+ s_rom <= '0';
+ s_cfg <= '0';
+ s_fifo <= '0';
+ s_reg <= '1';
+ else
+ s_rom <= '0';
+ s_cfg <= '0';
+ s_fifo <= '0';
+ s_reg <= '0';
+ next_main_status(5) <= '1';
+ end if;
+ elsif WRITE_IN = '1' then
+ if ADDR_IN(9 downto 8) = "01" then
+ s_rom <= '0';
+ s_cfg <= '1';
+ s_fifo <= '0';
+ s_reg <= '0';
+ else
+ s_rom <= '0';
+ s_cfg <= '0';
+ s_fifo <= '0';
+ s_reg <= '0';
+ next_main_status(5) <= '1';
+ end if;
+ else
+ s_rom <= '0';
+ s_cfg <= '0';
+ s_fifo <= '0';
+ s_reg <= '0';
+ end if;
+ end process;
+
+ p_register: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ main_status <= next_main_status;
+ end if;
+ end process;
+
+ p_handle_data:process(reg_valid, fifo_valid, reg_data, fifo_data)
+ begin
+ VALID_OUT <= fifo_valid or reg_valid;
+ DATA_OUT <= (others => '0');
+ if fifo_valid = '1' then
+ DATA_OUT(FIFO_BUS-1 downto 0) <= fifo_data;
+ elsif reg_valid = '1' then
+ DATA_OUT(REG_BUS-1 downto 0) <= reg_data;
+ end if;
+ end process;
+
+ next_main_status(0) <= fifo_status(0) or reg_status(0) or cfg_status(0); -- Unknown Cell Address
+ next_main_status(1) <= fifo_status(1); -- FIFO empty
+ next_main_status(2) <= cfg_status(1); -- ACK
+
+ STATUS_OUT <= main_status;
+
+
+ DEBUG_OUT(7 downto 0) <= combined_fifo_status(7 downto 0);
+ DEBUG_OUT(15 downto 8) <= combined_fifo_status(15 downto 8);
+ DEBUG_OUT(23 downto 16) <= main_status;
+ DEBUG_OUT(31 downto 24) <= "00" & combined_fifo_read(1) & combined_fifo_read(0) & s_rom & s_cfg & s_fifo & s_reg;
+
+-- DEBUG_OUT(31 downto 0) <= (others => '0');
+-- DEBUG_OUT(31 downto 0) <= FIFO_DATA_IN(31 downto 0);
+
+end architecture;
\ No newline at end of file
--- /dev/null
+-- ***********************************************************************************
+-- ***********************************************************************************
+--
+-- MONITOR config file
+-- -------------------
+--
+-- This file sets up the monitoring system
+--
+--
+--
+--
+--
+--
+-- ***********************************************************************************
+-- ***********************************************************************************
+
+
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+
+
+package monitor_config is
+
+
+constant FIFO_NUM : integer range 2 to 30 := 16; -- How many FIFOs do we need?
+constant FIFO_BUS : integer range 16 to 32 := 32; -- Width of the widest FIFO (the effective port width, hence the bus)
+
+constant REG_NUM : integer range 2 to 40 := 4; -- Amount of simple Register cells
+constant REG_BUS : integer range 2 to 32 := 32; -- The width of the biggest Register, hence the reg bus
+
+constant EXT_BUS : integer range 32 to 32 := 32; -- The extrenal bus width to which the monitor will be connected
+constant ARCH : string(1 to 8) := "_virtex4";
+
+
+type fifo_generic is record
+ fifo_type : string(1 to 12); -- The FIFO cell identifier, e.g. "32x512" or "8x16"
+ f_low : integer range 0 to 255; -- from 10 ns to 2560 ns, the automatic strobe signal
+ f_high : integer range 0 to 30; -- 10*2**2**f_high ns if this is set, f_low is ignored
+ timer : integer range 0 to 2; -- timer input port
+ t_res : integer range 0 to 31; -- from which bit on the timer will be taken
+ t_size : integer range 0 to 32; -- size of the timestamp in the package
+ d_size : integer range 0 to 32; -- size of data in the package
+ i_size : integer range 0 to 32; -- size of additional information from the external port in the package
+ ref : integer range 0 to 65535; -- the global monitoring signal reference
+end record;
+
+type fifo_generics is array(0 to 29) of fifo_generic;
+
+
+
+type reg_generic is record
+ id : integer range 0 to 39;
+ width : integer range 1 to 32;
+end record;
+
+type reg_generics is array(0 to 39) of reg_generic;
+
+
+
+
+type cfg_generic is record
+ id : integer range 0 to 29;
+ init : std_logic_vector(7 downto 0);
+end record;
+
+type cfg_generics is array(0 to 29) of cfg_generic;
+
+
+
+-- FIFO cells implemented for the VIRTEX4
+--
+--
+-- 32x512 : virtex4_fifo_32x512
+-- 16x1024 : virtex4_fifo_16x1024
+--
+--
+
+
+
+constant fifo_16x1024 : string := "fifo_16x1024";
+constant fifo_32x512 : string := "fifo_32x512 ";
+
+
+
+constant fifos : fifo_generics :=
+ (
+ -- type f_low f_high timer t_res t_size d_size i_size ref
+
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 0 ),
+
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 1 ),
+
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 2 ),
+
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 3 ),
+
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 4 ),
+
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 5 ),
+
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 6 ),
+
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 7 ),
+
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 8 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 9 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 10 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 11 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 12 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 13 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 14 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 16 , 16 , 0 , 15 ),
+
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 0 , 32 , 0 , 2 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 0 , 32 , 0 , 2 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 0 , 32 , 0 , 2 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 0 , 32 , 0 , 2 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 0 , 32 , 0 , 2 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 0 , 32 , 0 , 2 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 0 , 32 , 0 , 2 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 0 , 32 , 0 , 2 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 0 , 32 , 0 , 2 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 0 , 32 , 0 , 2 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 0 , 32 , 0 , 2 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 0 , 32 , 0 , 2 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 0 , 32 , 0 , 2 ),
+ ( fifo_32x512 , 0 , 0 , 0 , 0 , 0 , 32 , 0 , 2 )
+
+
+
+ );
+
+
+
+ -- SIZE SIZE
+
+constant reg0: reg_generic := ( 0 , 32 ); constant reg20: reg_generic := ( 20 , 32 );
+constant reg1: reg_generic := ( 1 , 32 ); constant reg21: reg_generic := ( 21 , 32 );
+constant reg2: reg_generic := ( 2 , 32 ); constant reg22: reg_generic := ( 22 , 32 );
+constant reg3: reg_generic := ( 3 , 32 ); constant reg23: reg_generic := ( 23 , 32 );
+constant reg4: reg_generic := ( 4 , 32 ); constant reg24: reg_generic := ( 24 , 32 );
+constant reg5: reg_generic := ( 5 , 32 ); constant reg25: reg_generic := ( 25 , 32 );
+constant reg6: reg_generic := ( 6 , 32 ); constant reg26: reg_generic := ( 26 , 32 );
+constant reg7: reg_generic := ( 7 , 32 ); constant reg27: reg_generic := ( 27 , 32 );
+constant reg8: reg_generic := ( 8 , 32 ); constant reg28: reg_generic := ( 28 , 32 );
+constant reg9: reg_generic := ( 9 , 32 ); constant reg29: reg_generic := ( 29 , 32 );
+constant reg10: reg_generic := ( 10 , 32 ); constant reg30: reg_generic := ( 30 , 32 );
+constant reg11: reg_generic := ( 11 , 32 ); constant reg31: reg_generic := ( 31 , 32 );
+constant reg12: reg_generic := ( 12 , 32 ); constant reg32: reg_generic := ( 32 , 32 );
+constant reg13: reg_generic := ( 13 , 32 ); constant reg33: reg_generic := ( 33 , 32 );
+constant reg14: reg_generic := ( 14 , 32 ); constant reg34: reg_generic := ( 34 , 32 );
+constant reg15: reg_generic := ( 15 , 32 ); constant reg35: reg_generic := ( 35 , 32 );
+constant reg16: reg_generic := ( 16 , 32 ); constant reg36: reg_generic := ( 36 , 32 );
+constant reg17: reg_generic := ( 17 , 32 ); constant reg37: reg_generic := ( 37 , 32 );
+constant reg18: reg_generic := ( 18 , 32 ); constant reg38: reg_generic := ( 38 , 32 );
+constant reg19: reg_generic := ( 19 , 32 ); constant reg39: reg_generic := ( 39 , 32 );
+
+
+
+
+
+-- Init value: - , - , - , automatic , pause , diff , ringbuffer , reset
+
+constant cfg0 : cfg_generic := ( 0 , "00010100" );
+constant cfg1 : cfg_generic := ( 1 , "00010100" );
+constant cfg2 : cfg_generic := ( 2 , "00010100" );
+constant cfg3 : cfg_generic := ( 3 , "00010100" );
+constant cfg4 : cfg_generic := ( 4 , "00010100" );
+constant cfg5 : cfg_generic := ( 5 , "00010100" );
+constant cfg6 : cfg_generic := ( 6 , "00010100" );
+constant cfg7 : cfg_generic := ( 7 , "00010100" );
+constant cfg8 : cfg_generic := ( 8 , "00010100" );
+constant cfg9 : cfg_generic := ( 9 , "00010100" );
+constant cfg10 : cfg_generic := ( 10 , "00010100" );
+constant cfg11 : cfg_generic := ( 11 , "00010100" );
+constant cfg12 : cfg_generic := ( 12 , "00010100" );
+constant cfg13 : cfg_generic := ( 13 , "00010100" );
+constant cfg14 : cfg_generic := ( 14 , "00010100" );
+constant cfg15 : cfg_generic := ( 15 , "00010100" );
+constant cfg16 : cfg_generic := ( 16 , "00000000" );
+constant cfg17 : cfg_generic := ( 17 , "00000000" );
+constant cfg18 : cfg_generic := ( 18 , "00000000" );
+constant cfg19 : cfg_generic := ( 19 , "00000000" );
+constant cfg20 : cfg_generic := ( 20 , "00000000" );
+constant cfg21 : cfg_generic := ( 21 , "00000000" );
+constant cfg22 : cfg_generic := ( 22 , "00000000" );
+constant cfg23 : cfg_generic := ( 23 , "00000000" );
+constant cfg24 : cfg_generic := ( 24 , "00000000" );
+constant cfg25 : cfg_generic := ( 25 , "00000000" );
+constant cfg26 : cfg_generic := ( 26 , "00000000" );
+constant cfg27 : cfg_generic := ( 27 , "00000000" );
+constant cfg28 : cfg_generic := ( 28 , "00000000" );
+constant cfg29 : cfg_generic := ( 29 , "00000000" );
+
+
+
+
+
+
+
+
+
+
+
+constant regs : reg_generics :=
+ (
+ reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, reg10, reg11, reg12, reg13, reg14,
+ reg15, reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23, reg24, reg25, reg26, reg27,
+ reg28, reg29, reg30, reg31, reg32, reg33, reg34, reg35, reg36, reg37, reg38, reg39
+ );
+
+
+
+constant cfgs : cfg_generics :=
+ (
+ cfg0, cfg1, cfg2, cfg3, cfg4, cfg5, cfg6, cfg7, cfg8, cfg9, cfg10, cfg11, cfg12, cfg13, cfg14,
+ cfg15, cfg16, cfg17, cfg18, cfg19, cfg20, cfg21, cfg22, cfg23, cfg24, cfg25, cfg26, cfg27,
+ cfg28, cfg29
+ );
+
+
+
+
+function Log2_monitor( input:integer ) return integer;
+
+
+
+end package monitor_config;
+
+
+
+
+
+
+package body monitor_config is
+
+
+ function Log2_monitor( input:integer ) return integer is
+ variable temp,log:integer;
+ begin
+ temp:=input;
+ log:=0;
+ while (temp /= 0) loop
+ temp:=temp/2;
+ log:=log+1;
+ end loop;
+ return log;
+ end function Log2_monitor;
+
+
+
+end package body monitor_config;
\ No newline at end of file
--- /dev/null
+-- ***********************************************************************************
+-- ***********************************************************************************
+--
+-- CFG cell DEMUX
+-- --------------
+--
+--
+-- ***********************************************************************************
+-- ***********************************************************************************
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+library work;
+use work.monitor_config.all;
+
+
+entity cfg_mux is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ WRITE_IN : in std_logic;
+ DATA_IN : in std_logic_vector(7 downto 0);
+ ADDR_IN : in std_logic_vector(7 downto 0);
+
+ DATA_OUT : out std_logic_vector(8*FIFO_NUM-1 downto 0);
+ WRITE_OUT : out std_logic_vector( FIFO_NUM-1 downto 0);
+
+ STATUS_OUT : out std_logic_vector(7 downto 0) := "00000000"
+ );
+end entity;
+
+architecture basic of cfg_mux is
+
+signal stat, next_stat : std_logic_vector(7 downto 0) := (others => '0');
+signal buf_data_out, next_buf_data_out : std_logic_vector(8*FIFO_NUM-1 downto 0) := (others => '0');
+signal buf_write_out, next_buf_write_out : std_logic_vector(FIFO_NUM-1 downto 0) := (others => '0');
+
+begin
+
+ STATUS_OUT <= stat;
+ DATA_OUT <= buf_data_out;
+ WRITE_OUT <= buf_write_out;
+
+ proc_register : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ buf_data_out <= next_buf_data_out;
+ buf_write_out <= next_buf_write_out;
+ stat <= next_stat;
+ end if;
+ end process;
+
+ proc_MUX : process(ADDR_IN, WRITE_IN, DATA_IN, RESET)
+ variable handle : integer range 0 to 255:= 0;
+ begin
+ handle := to_integer(unsigned(ADDR_IN));
+ next_buf_write_out <= (others => '0');
+ next_stat(0) <= '0'; -- UNKNOWN ADDRESS
+ next_stat(1) <= '0'; -- ACK
+ next_buf_data_out <= (others => '0');
+ if WRITE_IN = '1' then
+ if handle < FIFO_NUM then
+ next_buf_data_out(8*(handle+1)-1 downto 8*handle) <= DATA_IN;
+ next_buf_write_out <= (others => '0');
+ next_buf_write_out(handle) <= '1';
+ next_stat(1) <= '1';
+ else
+ next_stat(0) <= '1';
+ end if;
+ end if;
+ if RESET = '1' then
+ next_stat(0) <= '0';
+ next_stat(1) <= '0';
+ next_buf_data_out <= (others => '0');
+ next_buf_write_out <= (others => '0');
+ end if;
+ end process;
+
+end architecture;
\ No newline at end of file
--- /dev/null
+-- ***********************************************************************************
+-- ***********************************************************************************
+--
+-- The FIFO MUX
+-- ------------
+--
+--
+--
+--
+--
+-- ***********************************************************************************
+-- ***********************************************************************************
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+library work;
+use work.monitor_config.all;
+
+
+entity fifo_mux is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ READ_IN : in std_logic; -- Slow Control READ
+ ADDR_IN : in std_logic_vector(7 downto 0); -- Slow Control ADDR
+
+ READ_OUT : out std_logic_vector(FIFO_NUM-1 downto 0); -- MUX-to-FIFO READ
+
+ DATA_IN : in std_logic_vector(FIFO_NUM*FIFO_BUS-1 downto 0); -- FIFO data
+ VALID_IN : in std_logic_vector(FIFO_NUM-1 downto 0); -- FIFO valid
+ STATUS_IN : in std_logic_vector(8*FIFO_NUM-1 downto 0); -- FIFO stats
+
+ DATA_OUT : out std_logic_vector(FIFO_BUS-1 downto 0); -- MUX Data as received from the FIFO
+ VALID_OUT : out std_logic; -- MUX Valid
+ STATUS_OUT : out std_logic_vector(7 downto 0) := "00000000" -- MUX status bits
+ );
+end entity;
+
+architecture basic of fifo_mux is
+
+type STATES is (IDLE, MONITOR, INIT);
+signal state,next_state : STATES := IDLE;
+
+signal buf_read_out, next_buf_read_out : std_logic_vector(FIFO_NUM-1 downto 0) := (others => '0');
+signal stat, next_stat : std_logic_vector(7 downto 0) := "00000000";
+signal buf_data_out, next_buf_data_out : std_logic_vector(31 downto 0) := (others => '0');
+signal val, next_val : std_logic := '0';
+signal handle, next_handle : integer range 0 to 255 := 0;
+
+begin
+
+ READ_OUT <= buf_read_out;
+ DATA_OUT <= buf_data_out;
+ VALID_OUT <= val;
+ STATUS_OUT <= stat;
+
+ proc_register : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ state <= next_state;
+ buf_data_out <= next_buf_data_out;
+ buf_read_out <= next_buf_read_out;
+ stat <= next_stat;
+ val <= next_val;
+ handle <= next_handle;
+ end if;
+ end process;
+
+ proc_MUX : process(state, ADDR_IN, RESET, READ_IN, DATA_IN, VALID_IN, STATUS_IN, handle)
+ begin
+ next_state <= state;
+ next_buf_read_out <= (others => '0');
+ next_stat(0) <= '0'; -- UNKNOWN ADDRESS
+ next_stat(1) <= '0'; -- FIFO_EMPTY
+ next_stat(2) <= '0'; -- FIFO_FULL
+ next_buf_data_out <= (others => '0');
+ next_val <= '0';
+ next_handle <= handle;
+
+ case state is
+ when IDLE =>
+ if READ_IN = '1' then
+ next_state <= INIT;
+ next_handle <= to_integer(unsigned(ADDR_IN));
+ end if;
+ when INIT =>
+ if handle < FIFO_NUM then
+ next_buf_read_out(handle) <= '1';
+ next_state <= MONITOR;
+ else
+ next_stat(0) <= '1';
+ next_state <= IDLE;
+ end if;
+ when MONITOR =>
+ if VALID_IN(handle) = '1' then
+ next_buf_data_out <= DATA_IN( FIFO_BUS*handle+FIFO_BUS-1 downto FIFO_BUS*handle );
+ next_val <= '1';
+ next_state <= IDLE;
+ elsif STATUS_IN(8*handle+1) = '1' then
+ next_stat(1) <= '1';
+ next_state <= IDLE;
+ end if;
+ when others =>
+ end case;
+ if RESET = '1' then
+ next_stat(0) <= '0';
+ next_stat(1) <= '0';
+ next_stat(2) <= '0';
+ next_buf_data_out <= (others => '0');
+ next_buf_read_out <= (others => '0');
+ next_val <= '0';
+ next_state <= IDLE;
+ next_handle <= 0;
+ end if;
+ end process;
+
+end architecture;
--- /dev/null
+-- ***********************************************************************************
+-- ***********************************************************************************
+--
+-- The REG MUX
+-- -----------
+--
+--
+--
+-- ***********************************************************************************
+-- ***********************************************************************************
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+library work;
+use work.monitor_config.all;
+
+
+entity reg_mux is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ READ_IN : in std_logic;
+ ADDR_IN : in std_logic_vector(7 downto 0);
+ DATA_IN : in std_logic_vector( (REG_NUM*REG_BUS)-1 downto 0);
+
+ DATA_OUT : out std_logic_vector(REG_BUS-1 downto 0);
+ VALID_OUT : out std_logic;
+
+ STATUS_OUT : out std_logic_vector(7 downto 0) := "00000000"
+ );
+end entity;
+
+architecture basic of reg_mux is
+
+signal buf_reg, next_buf_reg : std_logic_vector(REG_BUS-1 downto 0) := (others => '0');
+signal val, next_val : std_logic := '0';
+signal stat, next_stat : std_logic_vector(7 downto 0) := (others => '0');
+
+begin
+
+ DATA_OUT <= buf_reg;
+ VALID_OUT <= val;
+ STATUS_OUT <= stat;
+
+ p_register:process(CLK)
+ begin
+ if rising_edge(CLK) then
+ buf_reg <= next_buf_reg;
+ val <= next_val;
+ stat <= next_stat;
+ end if;
+ end process;
+
+ proc_MUX : process(ADDR_IN, READ_IN, DATA_IN, RESET, buf_reg)
+ variable handle : integer range 0 to 255 := 0;
+ begin
+ handle := to_integer(unsigned(ADDR_IN));
+ next_stat(0) <= '0'; -- UNKNOWN ADDRESS
+ next_val <= '0';
+ next_buf_reg <= buf_reg;
+ if READ_IN = '1' then
+ if handle < REG_NUM then
+ next_buf_reg <= DATA_IN(REG_BUS*handle+REG_BUS-1 downto REG_BUS*handle);
+ next_val <= '1';
+ else
+ next_stat(0) <= '1'; -- UNKNOWN ADDRESS True
+ end if;
+ end if;
+ if RESET = '1' then
+ next_stat(0) <= '0';
+ next_val <= '0';
+ next_buf_reg <= (others => '0');
+ end if;
+ end process;
+
+end architecture;
\ No newline at end of file
--- /dev/null
+The FEE monitor:
+
+1) Include all files into your project.
+2) Rewrite monitor_config.vhd
+3) Assign all signals to be monitored to the FIFO input port and REG input port.
+4) Read values out via trbcmd or slowcontrol
+
+Attach the monitor to the regio bus handler entity with a designated address range.
+In case of 0xb000 address space, the cells would be:
+
+ 0xb100 - 0xb1xx configuration cells, use writes to set FIFO parameter
+ write 0x1 - FIFO RESET
+ write 0x2 - Ring Buffer Mode
+ write 0x4 - Diff, check if successive inputs differ,
+ writes only new and changed values into the FIFO
+ write 0x8 - HALT the FIFO writes
+ write 0x10 - Automatic monitoring with predefined frequency
+ The frequency is set by freq_low which sais
+ how many clock cycles should be skipped and
+ freq_high which sais how many clock cycles
+ as a power of 2 should be skipped.
+ If freq_high is set, freq_low will be ignored.
+
+ If no automatic scanning is specified, use
+ FIFO_WRITE_IN port to set HW write triggers.
+ One bit per FIFO, if it is set then a write occurs.
+ Any combination of these is also possible.
+ 0xb200 - 0xb2xx FIFO cell address range, one address per FIFO
+ 0xb300 - 0xb3xx REG cell address range, one address per Register
+
+In the current version, the ROM is not implemented.
+
+
+Borislav Milanovic
--- /dev/null
+-- ***********************************************************************************
+-- ***********************************************************************************
+--
+-- REG storage cell
+-- -----------------
+--
+-- ***********************************************************************************
+-- ***********************************************************************************
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+-- Import monitor_config.vhd
+-- with all its constants and components
+library work;
+use work.monitor_config.all;
+
+
+
+entity REG_cell is
+ generic(
+ width : integer range 1 to 32 := 32 -- only 32 bit in the current version due to the readout bus
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ DATA_IN : in std_logic_vector(REG_BUS-1 downto 0); -- REG_BUS is currently a constant set to 32
+ DATA_OUT : out std_logic_vector(REG_BUS-1 downto 0) := (others => '0') -- it is defined in monitor_config.vhd which is imported
+ );
+end entity;
+
+architecture basic of REG_cell is
+
+signal data, next_data : std_logic_vector(width-1 downto 0) := (others => '0');
+
+begin
+
+ -- Define the output port
+ DATA_OUT(width-1 downto 0) <= data;
+
+ -- Calculate the cell contents based on RESET and input port
+ p_input:process(DATA_IN, RESET)
+ begin
+ if RESET = '0' then
+ next_data <= DATA_IN(width-1 downto 0);
+ else
+ next_data <= (others => '0');
+ end if;
+ end process;
+
+ -- Take the input into the D flipflop at rising clock edge
+ p_register : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ data <= next_data;
+ end if;
+ end process;
+
+end architecture;
\ No newline at end of file
--- /dev/null
+--
+--
+-- 2DO:
+-- FIT TO VERSION 4.0
+--
+--
+--
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+--USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.monitor_config.all;
+
+entity rom_32x113 is
+ generic(
+ INITX : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(FIFO_NUM,8)) & std_logic_vector(to_unsigned(REG_NUM,16)) & std_logic_vector(to_unsigned(CFG_WIDTH, 8));
+ INIT0 : std_logic_vector(31 downto 0) := fifo_generics(1).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(1).width,8)) & std_logic_vector(to_unsigned(fifo_generics(1).depth,16));
+ INIT1 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(1).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(1).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(1).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(1).time_size,8));
+ INIT2 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(1).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(1).event_size,8)) & "0000000000000000";
+ INIT3 : std_logic_vector(31 downto 0) := cfgs(1).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT4 : std_logic_vector(31 downto 0) := fifo_generics(2).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(2).width,8)) & std_logic_vector(to_unsigned(fifo_generics(2).depth,16));
+ INIT5 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(2).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(2).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(2).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(2).time_size,8));
+ INIT6 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(2).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(2).event_size,8)) & "0000000000000000";
+ INIT7 : std_logic_vector(31 downto 0) := cfgs(2).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT8 : std_logic_vector(31 downto 0) := fifo_generics(3).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(3).width,8)) & std_logic_vector(to_unsigned(fifo_generics(3).depth,16));
+ INIT9 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(3).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(3).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(3).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(3).time_size,8));
+ INIT10 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(3).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(3).event_size,8)) & "0000000000000000";
+ INIT11 : std_logic_vector(31 downto 0) := cfgs(3).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT12 : std_logic_vector(31 downto 0) := fifo_generics(4).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(4).width,8)) & std_logic_vector(to_unsigned(fifo_generics(4).depth,16));
+ INIT13 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(4).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(4).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(4).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(4).time_size,8));
+ INIT14 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(4).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(4).event_size,8)) & "0000000000000000";
+ INIT15 : std_logic_vector(31 downto 0) := cfgs(4).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT16 : std_logic_vector(31 downto 0) := fifo_generics(5).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(5).width,8)) & std_logic_vector(to_unsigned(fifo_generics(5).depth,16));
+ INIT17 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(5).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(5).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(5).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(5).time_size,8));
+ INIT18 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(5).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(5).event_size,8)) & "0000000000000000";
+ INIT19 : std_logic_vector(31 downto 0) := cfgs(5).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT20 : std_logic_vector(31 downto 0) := fifo_generics(6).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(6).width,8)) & std_logic_vector(to_unsigned(fifo_generics(6).depth,16));
+ INIT21 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(6).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(6).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(6).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(6).time_size,8));
+ INIT22 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(6).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(6).event_size,8)) & "0000000000000000";
+ INIT23 : std_logic_vector(31 downto 0) := cfgs(6).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT24 : std_logic_vector(31 downto 0) := fifo_generics(7).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(7).width,8)) & std_logic_vector(to_unsigned(fifo_generics(7).depth,16));
+ INIT25 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(7).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(7).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(7).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(7).time_size,8));
+ INIT26 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(7).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(7).event_size,8)) & "0000000000000000";
+ INIT27 : std_logic_vector(31 downto 0) := cfgs(7).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT28 : std_logic_vector(31 downto 0) := fifo_generics(8).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(8).width,8)) & std_logic_vector(to_unsigned(fifo_generics(8).depth,16));
+ INIT29 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(8).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(8).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(8).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(8).time_size,8));
+ INIT30 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(8).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(8).event_size,8)) & "0000000000000000";
+ INIT31 : std_logic_vector(31 downto 0) := cfgs(8).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT32 : std_logic_vector(31 downto 0) := fifo_generics(9).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(9).width,8)) & std_logic_vector(to_unsigned(fifo_generics(9).depth,16));
+ INIT33 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(9).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(9).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(9).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(9).time_size,8));
+ INIT34 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(9).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(9).event_size,8)) & "0000000000000000";
+ INIT35 : std_logic_vector(31 downto 0) := cfgs(9).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT36 : std_logic_vector(31 downto 0) := fifo_generics(10).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(10).width,8)) & std_logic_vector(to_unsigned(fifo_generics(10).depth,16));
+ INIT37 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(10).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(10).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(10).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(10).time_size,8));
+ INIT38 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(10).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(10).event_size,8)) & "0000000000000000";
+ INIT39 : std_logic_vector(31 downto 0) := cfgs(10).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT40 : std_logic_vector(31 downto 0) := fifo_generics(11).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(11).width,8)) & std_logic_vector(to_unsigned(fifo_generics(11).depth,16));
+ INIT41 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(11).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(11).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(11).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(11).time_size,8));
+ INIT42 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(11).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(11).event_size,8)) & "0000000000000000";
+ INIT43 : std_logic_vector(31 downto 0) := cfgs(11).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT44 : std_logic_vector(31 downto 0) := fifo_generics(12).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(12).width,8)) & std_logic_vector(to_unsigned(fifo_generics(12).depth,16));
+ INIT45 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(12).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(12).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(12).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(12).time_size,8));
+ INIT46 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(12).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(12).event_size,8)) & "0000000000000000";
+ INIT47 : std_logic_vector(31 downto 0) := cfgs(12).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT48 : std_logic_vector(31 downto 0) := fifo_generics(13).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(13).width,8)) & std_logic_vector(to_unsigned(fifo_generics(13).depth,16));
+ INIT49 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(13).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(13).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(13).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(13).time_size,8));
+ INIT50 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(13).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(13).event_size,8)) & "0000000000000000";
+ INIT51 : std_logic_vector(31 downto 0) := cfgs(13).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT52 : std_logic_vector(31 downto 0) := fifo_generics(14).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(14).width,8)) & std_logic_vector(to_unsigned(fifo_generics(14).depth,16));
+ INIT53 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(14).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(14).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(14).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(14).time_size,8));
+ INIT54 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(14).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(14).event_size,8)) & "0000000000000000";
+ INIT55 : std_logic_vector(31 downto 0) := cfgs(14).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT56 : std_logic_vector(31 downto 0) := fifo_generics(15).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(15).width,8)) & std_logic_vector(to_unsigned(fifo_generics(15).depth,16));
+ INIT57 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(15).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(15).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(15).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(15).time_size,8));
+ INIT58 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(15).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(15).event_size,8)) & "0000000000000000";
+ INIT59 : std_logic_vector(31 downto 0) := cfgs(15).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT60 : std_logic_vector(31 downto 0) := fifo_generics(16).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(16).width,8)) & std_logic_vector(to_unsigned(fifo_generics(16).depth,16));
+ INIT61 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(16).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(16).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(16).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(16).time_size,8));
+ INIT62 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(16).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(16).event_size,8)) & "0000000000000000";
+ INIT63 : std_logic_vector(31 downto 0) := cfgs(16).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT64 : std_logic_vector(31 downto 0) := fifo_generics(17).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(17).width,8)) & std_logic_vector(to_unsigned(fifo_generics(17).depth,16));
+ INIT65 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(17).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(17).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(17).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(17).time_size,8));
+ INIT66 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(17).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(17).event_size,8)) & "0000000000000000";
+ INIT67 : std_logic_vector(31 downto 0) := cfgs(17).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT68 : std_logic_vector(31 downto 0) := fifo_generics(18).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(18).width,8)) & std_logic_vector(to_unsigned(fifo_generics(18).depth,16));
+ INIT69 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(18).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(18).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(18).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(18).time_size,8));
+ INIT70 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(18).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(18).event_size,8)) & "0000000000000000";
+ INIT71 : std_logic_vector(31 downto 0) := cfgs(18).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT72 : std_logic_vector(31 downto 0) := fifo_generics(19).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(19).width,8)) & std_logic_vector(to_unsigned(fifo_generics(19).depth,16));
+ INIT73 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(19).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(19).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(19).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(19).time_size,8));
+ INIT74 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(19).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(19).event_size,8)) & "0000000000000000";
+ INIT75 : std_logic_vector(31 downto 0) := cfgs(19).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT76 : std_logic_vector(31 downto 0) := fifo_generics(20).monitoring_type & std_logic_vector(to_unsigned(fifo_generics(20).width,8)) & std_logic_vector(to_unsigned(fifo_generics(20).depth,16));
+ INIT77 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(20).frequency,8)) & std_logic_vector(to_unsigned(fifo_generics(20).timer_type,8)) & std_logic_vector(to_unsigned(fifo_generics(20).timer_resolution,8)) & std_logic_vector(to_unsigned(fifo_generics(20).time_size,8));
+ INIT78 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(fifo_generics(20).data_size,8)) & std_logic_vector(to_unsigned(fifo_generics(20).event_size,8)) & "0000000000000000";
+ INIT79 : std_logic_vector(31 downto 0) := cfgs(20).init & std_logic_vector(to_unsigned(fifo_generics(1).descriptor,16));
+ INIT80 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(1).width,8)) & x"0000" & "00000000";
+ INIT81 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(2).width,8)) & x"0000" & "00000000";
+ INIT82 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(3).width,8)) & x"0000" & "00000000";
+ INIT83 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(4).width,8)) & x"0000" & "00000000";
+ INIT84 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(5).width,8)) & x"0000" & "00000000";
+ INIT85 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(6).width,8)) & x"0000" & "00000000";
+ INIT86 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(7).width,8)) & x"0000" & "00000000";
+ INIT87 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(8).width,8)) & x"0000" & "00000000";
+ INIT88 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(9).width,8)) & x"0000" & "00000000";
+ INIT89 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(10).width,8)) & x"0000" & "00000000";
+ INIT90 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(11).width,8)) & x"0000" & "00000000";
+ INIT91 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(12).width,8)) & x"0000" & "00000000";
+ INIT92 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(13).width,8)) & x"0000" & "00000000";
+ INIT93 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(14).width,8)) & x"0000" & "00000000";
+ INIT94 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(15).width,8)) & x"0000" & "00000000";
+ INIT95 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(16).width,8)) & x"0000" & "00000000";
+ INIT96 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(17).width,8)) & x"0000" & "00000000";
+ INIT97 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(18).width,8)) & x"0000" & "00000000";
+ INIT98 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(19).width,8)) & x"0000" & "00000000";
+ INIT99 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(20).width,8)) & x"0000" & "00000000";
+ INIT100: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(21).width,8)) & x"0000" & "00000000";
+ INIT101: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(22).width,8)) & x"0000" & "00000000";
+ INIT102: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(23).width,8)) & x"0000" & "00000000";
+ INIT103: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(24).width,8)) & x"0000" & "00000000";
+ INIT104: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(25).width,8)) & x"0000" & "00000000";
+ INIT105: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(26).width,8)) & x"0000" & "00000000";
+ INIT106: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(27).width,8)) & x"0000" & "00000000";
+ INIT107: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(28).width,8)) & x"0000" & "00000000";
+ INIT108: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(29).width,8)) & x"0000" & "00000000";
+ INIT109: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(30).width,8)) & x"0000" & "00000000";
+ INIT110: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(31).width,8)) & x"0000" & "00000000";
+ INIT111: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(reg_generics(32).width,8)) & x"0000" & "00000000"
+
+ );
+ port(
+ CLK : in std_logic;
+ ADDR_IN : in std_logic_vector(8 downto 0);
+ DATA_OUT : out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+architecture rom_32x113_arch of rom_32x113 is
+ type ram_t is array(0 to 112) of std_logic_vector(31 downto 0);
+ SIGNAL rom : ram_t := (INITX, INIT0, INIT1, INIT2, INIT3, INIT4, INIT5, INIT6, INIT7, INIT8,
+ INIT9, INIT10, INIT11, INIT12, INIT13, INIT14, INIT15, INIT16,
+ INIT17, INIT18, INIT19, INIT20, INIT21, INIT22, INIT23, INIT24,
+ INIT25, INIT26, INIT27, INIT28, INIT29, INIT30, INIT31,
+ INIT32, INIT33, INIT34, INIT35, INIT36, INIT37, INIT38, INIT39, INIT40,
+ INIT41, INIT42, INIT43, INIT44, INIT45, INIT46, INIT47, INIT48,
+ INIT49, INIT50, INIT51, INIT52, INIT53, INIT54, INIT55, INIT56,
+ INIT57, INIT58, INIT59, INIT60, INIT61, INIT62, INIT63,
+ INIT64, INIT65, INIT66, INIT67, INIT68, INIT69, INIT70, INIT71,
+ INIT72, INIT73, INIT74, INIT75, INIT76, INIT77, INIT78, INIT79,
+ INIT80, INIT81, INIT82, INIT83, INIT84, INIT85, INIT86, INIT87,
+ INIT88, INIT89, INIT90, INIT91, INIT92, INIT93, INIT94, INIT95,
+ INIT96, INIT97, INIT98, INIT99, INIT100, INIT101, INIT102, INIT103,
+ INIT104, INIT105, INIT106, INIT107, INIT108, INIT109, INIT110, INIT111
+-- INIT112, INIT113, INIT114, INIT115, INIT116, INIT117, INIT118, INIT119,
+-- INIT120, INIT121, INIT122, INIT123, INIT124, INIT125, INIT126, INIT127,
+-- INIT128, INIT129, INIT130, INIT131, INIT132, INIT133, INIT134, INIT135,
+-- INIT136, INIT137, INIT138, INIT139, INIT140, INIT141, INIT142, INIT143
+ );
+
+begin
+
+
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ DATA_OUT <= rom(to_integer(unsigned(ADDR_IN)));
+ end if;
+ end process;
+
+end architecture;
\ No newline at end of file
jspc29 / trbnet.git / commitdiff