Remove unused generics in CTS, now in config.vhd if necessary

diff --git a/cts/source/cts.vhd b/cts/source/cts.vhd
index 4cc82170e0afaecb94cc9a0b916ac33054be690c..9110967dc43eb42ff202458413df5af34553e2f1 100755 (executable)
--- a/cts/source/cts.vhd
+++ b/cts/source/cts.vhd
@@ -101,18 +101,18 @@ library work;
 
 entity CTS is
    generic (
-      TRIGGER_INPUT_COUNT : integer range 0 to  8 := 4;
-      TRIGGER_COIN_COUNT  : integer range 0 to 15 := 4;
-      TRIGGER_PULSER_COUNT: integer range 0 to 15 := 4;
-      TRIGGER_RAND_PULSER : integer range 0 to  1 := 1;
+      TRIGGER_INPUT_COUNT : integer range 0 to  8 := 0;
+--       TRIGGER_COIN_COUNT  : integer range 0 to 15 := 4;
+--       TRIGGER_PULSER_COUNT: integer range 0 to 15 := 4;
+--       TRIGGER_RAND_PULSER : integer range 0 to  1 := 1;
       
-      ADDON_LINE_COUNT : integer := 22;                 -- number of lines available from add-on board
+--       ADDON_LINE_COUNT : integer := 22;                 -- number of lines available from add-on board
       
-      TRIGGER_ADDON_COUNT : integer range 0 to 15 := 2;  -- number of module instances used to patch through those lines
+--       TRIGGER_ADDON_COUNT : integer range 0 to 15 := 2;  -- number of module instances used to patch through those lines
       ADDON_GROUPS        : integer range 1 to 8 := 5;
       ADDON_GROUP_UPPER   : CTS_GROUP_CONFIG_T  := (3,7,11,12,13, others=>'0');
       
-      PERIPH_TRIGGER_COUNT: integer range 0 to 1 := 1;
+--       PERIPH_TRIGGER_COUNT: integer range 0 to 1 := 1;
       
       OUTPUT_MULTIPLEXERS : integer range 0 to 255 := 0;
       
@@ -127,7 +127,7 @@ entity CTS is
       RESET     : in  std_logic;      
       
   -- Trigger Logic
-      TRIGGERS_IN        : in std_logic_vector(max(0,TRIGGER_INPUT_COUNT-1) downto 0):= (others => '0');
+--       TRIGGERS_IN        : in std_logic_vector(max(0,TRIGGER_INPUT_COUNT-1) downto 0):= (others => '0');
       TRIGGER_BUSY_OUT   : out std_logic;
       TIME_REFERENCE_OUT : out std_logic;
       
@@ -760,7 +760,7 @@ begin
             -- round-robin active active, and a new event just started
             if eb_aggr_threshold_i = eb_aggr_counter_i then
                eb_aggr_counter_i <= (others => '0');
-               eb_selection_i <= next_eb_selection;
+               eb_selection_i <= std_logic_vector(next_eb_selection);
                get_next_eb := '1';
                
             else
@@ -807,7 +807,7 @@ begin
       CLK_1KHZ_IN => clk_1khz_i,
       RESET_IN    => RESET,
          
-      TRIGGERS_IN => TRIGGERS_IN,
+      TRIGGERS_IN => "0",
       ADDON_TRIGGERS_IN => ADDON_TRIGGERS_IN,
       ADDON_GROUP_ACTIVITY_OUT => ADDON_GROUP_ACTIVITY_OUT,
       ADDON_GROUP_SELECTED_OUT => ADDON_GROUP_SELECTED_OUT,

diff --git a/cts/source/cts_pkg.vhd b/cts/source/cts_pkg.vhd
index 06cb7ab90f658a971d8d9a8c9a490f2605eb06f5..39613c9ac107aee77c5f355fc01caec34d1163e9 100755 (executable)
--- a/cts/source/cts_pkg.vhd
+++ b/cts/source/cts_pkg.vhd
@@ -2,6 +2,9 @@ library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
 
+library work;
+   use  config.all;
+   
 package cts_pkg is
    type CTS_GROUP_CONFIG_T is array(0 to 7) of integer;
    
@@ -11,15 +14,15 @@ package cts_pkg is
    component CTS is
       generic (
          -- The total number of trigger units below has to be below 16
-         TRIGGER_INPUT_COUNT : integer range 0 to  8 := 4;
-         TRIGGER_COIN_COUNT  : integer range 0 to 15 := 2;
-         TRIGGER_PULSER_COUNT: integer range 0 to 15 := 4;
-         TRIGGER_RAND_PULSER : integer range 0 to 15 := 1;
-         TRIGGER_ADDON_COUNT : integer range 0 to 15 := 2;  -- number of module instances used to patch through those lines
-         PERIPH_TRIGGER_COUNT: integer range 0 to 15 := 2;
+--          TRIGGER_INPUT_COUNT : integer range 0 to  8 := 0;
+--          TRIGGER_COIN_COUNT  : integer range 0 to 15 := 2;
+--          TRIGGER_PULSER_COUNT: integer range 0 to 15 := 4;
+--          TRIGGER_RAND_PULSER : integer range 0 to 15 := 1;
+--          TRIGGER_ADDON_COUNT : integer range 0 to 15 := 2;  -- number of module instances used to patch through those lines
+--          PERIPH_TRIGGER_COUNT: integer range 0 to 15 := 2;
       
          ADDON_GROUPS        : integer range 1 to  8 := 5;
-         ADDON_LINE_COUNT    : integer range 0 to 255 := 22;                 -- number of lines available from add-on board
+--          ADDON_LINE_COUNT    : integer range 0 to 255 := 22;                 -- number of lines available from add-on board
          ADDON_GROUP_UPPER   : CTS_GROUP_CONFIG_T  := (3,7,11,12,13, others=>'0');
 
          
@@ -36,7 +39,7 @@ package cts_pkg is
          RESET     : in  std_logic;      
          
    -- Trigger Logic
-         TRIGGERS_IN        : in std_logic_vector(MAX(0,TRIGGER_INPUT_COUNT-1) downto 0);
+--          TRIGGERS_IN        : in std_logic_vector(MAX(0,TRIGGER_INPUT_COUNT-1) downto 0);
          TRIGGER_BUSY_OUT   : out std_logic;
          TIME_REFERENCE_OUT : out std_logic;
 

diff --git a/cts/source/cts_trg_input.vhd b/cts/source/cts_trg_input.vhd
index 14b080aa6752624411483e0cbc8f40a4c99a8dc4..7d8d81aa2b71493b9e487cd87a5260794136a67f 100644 (file)
--- a/cts/source/cts_trg_input.vhd
+++ b/cts/source/cts_trg_input.vhd
@@ -41,7 +41,7 @@ architecture rtl of CTS_TRG_INPUT is
 -- connection between stages
    signal from_inverter_i, from_delay_i, from_spike_i : std_logic;
 
-   signal delay_line_i : std_logic_vector(15 downto 0);
+   signal delay_line_i : std_logic_vector(MAX_DELAY-1 downto 0);
    signal spike_rej_counter_i : integer range 0 to MAX_SPIKE_REJ-1;
 begin
 -- inverter
@@ -56,14 +56,14 @@ begin
    proc_delay: process(CLK_IN) is
    begin
       if rising_edge(CLK_IN) then
-         if RST_IN = '1' then
-            delay_line_i <= (others => '0');
-            from_delay_i <= '0';
-         else
+--          if RST_IN = '1' then
+--             delay_line_i <= (others => '0');
+--             from_delay_i <= '0';
+--          else
             delay_line_i <= delay_line_i(delay_line_i'HIGH - 1 downto 0) 
                             & from_inverter_i;
             from_delay_i <= delay_line_i(config_delay_i);
-         end if;
+--          end if;
       end if;
    end process;
    
@@ -106,4 +106,4 @@ begin
    config_invert_i   <= CONFIG_IN(8);
    config_over_ena_i <= CONFIG_IN(9);
    config_over_val_i <= CONFIG_IN(10);
-end architecture;
\ No newline at end of file
+end architecture;

diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd
index 06e722fe45b1ae1603a048ac29eba0d633bfd0f5..e0a20b7e41cccd7b78902ccc810f60462bb0e89c 100644 (file)
--- a/cts/trb3_central.vhd
+++ b/cts/trb3_central.vhd
@@ -1383,15 +1383,15 @@ end generate;
       BUS_REG_RX => busgbereg_rx,
       BUS_REG_TX => busgbereg_tx,
 
-      FWD_DST_MAC_IN => fwd_mac,
-      FWD_DST_IP_IN => fwd_ip,
-      FWD_DST_UDP_IN => fwd_udp,
-      FWD_DATA_IN => fwd_data,
-      FWD_DATA_VALID_IN => fwd_dv,
-      FWD_SOP_IN => fwd_sop,
-      FWD_EOP_IN => fwd_eop,
-      FWD_READY_OUT => fwd_ready,
-      FWD_FULL_OUT => fwd_full,
+--       FWD_DST_MAC_IN => fwd_mac,
+--       FWD_DST_IP_IN => fwd_ip,
+--       FWD_DST_UDP_IN => fwd_udp,
+--       FWD_DATA_IN => fwd_data,
+--       FWD_DATA_VALID_IN => fwd_dv,
+--       FWD_SOP_IN => fwd_sop,
+--       FWD_EOP_IN => fwd_eop,
+--       FWD_READY_OUT => fwd_ready,
+--       FWD_FULL_OUT => fwd_full,
       
       MAKE_RESET_OUT           => reset_via_gbe,