COMMON_STAT_REGS : in std_logic_vector (std_COMSTATREG*32-1 downto 0) := (others => '0'); --Status of common STAT regs
COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
MY_ADDRESS_OUT : out std_logic_vector (15 downto 0);
+ --REGIO INTERFACE
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
+ REGIO_READ_ENABLE_OUT : out std_logic;
+ REGIO_WRITE_ENABLE_OUT : out std_logic;
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
+ REGIO_DATAREADY_IN : in std_logic := '0';
+ REGIO_NO_MORE_DATA_IN : in std_logic := '0';
+ REGIO_WRITE_ACK_IN : in std_logic := '0';
+ REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';
+ REGIO_TIMEOUT_OUT : out std_logic;
--Fixed status and control ports
HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
signal timer_us_tick : std_logic;
signal stat_ipu_fsm : std_logic_vector(15 downto 0);
+ signal DAT_ADDR_OUT : std_logic_vector(16-1 downto 0);
+ signal DAT_READ_ENABLE_OUT : std_logic;
+ signal DAT_WRITE_ENABLE_OUT : std_logic;
+ signal DAT_DATA_OUT : std_logic_vector(32-1 downto 0);
+ signal DAT_DATA_IN : std_logic_vector(32-1 downto 0) := (others => '0');
+ signal DAT_DATAREADY_IN : std_logic := '0';
+ signal DAT_NO_MORE_DATA_IN : std_logic := '0';
+ signal DAT_WRITE_ACK_IN : std_logic := '0';
+ signal DAT_UNKNOWN_ADDR_IN : std_logic := '0';
+ signal DAT_TIMEOUT_OUT : std_logic;
+
begin
USED_CTRL_REGS => "00011111",
USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
- USE_DAT_PORT => c_NO,
+ USE_DAT_PORT => c_YES,
INIT_ADDRESS => INIT_ADDRESS,
INIT_UNIQUE_ID => INIT_UNIQUE_ID,
INIT_ENDPOINT_ID => INIT_ENDPOINT_ID,
IDRAM_DATA_OUT => open,
IDRAM_ADDR_IN => IDRAM_ADDR_IN,
IDRAM_WR_IN => IDRAM_WR_IN,
- DAT_ADDR_OUT => open,
- DAT_READ_ENABLE_OUT => open,
- DAT_WRITE_ENABLE_OUT=> open,
- DAT_DATA_OUT => open,
- DAT_DATA_IN => x"00000000",
- DAT_DATAREADY_IN => '0',
- DAT_NO_MORE_DATA_IN => '0',
- DAT_UNKNOWN_ADDR_IN => '0',
- DAT_TIMEOUT_OUT => open,
+ DAT_ADDR_OUT => DAT_ADDR_OUT,
+ DAT_READ_ENABLE_OUT => DAT_READ_ENABLE_OUT,
+ DAT_WRITE_ENABLE_OUT=> DAT_WRITE_ENABLE_OUT,
+ DAT_DATA_OUT => DAT_DATA_OUT,
+ DAT_DATA_IN => DAT_DATA_IN,
+ DAT_DATAREADY_IN => DAT_DATAREADY_IN,
+ DAT_NO_MORE_DATA_IN => DAT_NO_MORE_DATA_IN,
+ DAT_UNKNOWN_ADDR_IN => DAT_UNKNOWN_ADDR_IN,
+ DAT_TIMEOUT_OUT => DAT_TIMEOUT_OUT,
DAT_WRITE_ACK_IN => '0'
);
+
+
+THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 1,
+ PORT_ADDRESSES => (0 => x"C000"),
+ PORT_ADDR_MASK => (0 => 14)
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+
+ DAT_ADDR_IN => DAT_ADDR_OUT,
+ DAT_DATA_IN => DAT_DATA_OUT,
+ DAT_DATA_OUT => DAT_DATA_IN,
+ DAT_READ_ENABLE_IN => DAT_READ_ENABLE_OUT,
+ DAT_WRITE_ENABLE_IN => DAT_WRITE_ENABLE_OUT,
+ DAT_TIMEOUT_IN => DAT_TIMEOUT_OUT,
+ DAT_DATAREADY_OUT => DAT_DATAREADY_IN,
+ DAT_WRITE_ACK_OUT => DAT_WRITE_ACK_IN,
+ DAT_NO_MORE_DATA_OUT => DAT_NO_MORE_DATA_IN,
+ DAT_UNKNOWN_ADDR_OUT => DAT_UNKNOWN_ADDR_IN,
+
+ BUS_ADDR_OUT(15 downto 0) => REGIO_ADDR_OUT,
+ BUS_DATA_OUT(31 downto 0) => REGIO_DATA_OUT,
+ BUS_READ_ENABLE_OUT(0) => REGIO_READ_ENABLE_OUT,
+ BUS_WRITE_ENABLE_OUT(0) => REGIO_WRITE_ENABLE_OUT,
+ BUS_TIMEOUT_OUT(0) => REGIO_TIMEOUT_OUT,
+ BUS_DATA_IN(31 downto 0) => REGIO_DATA_IN,
+ BUS_DATAREADY_IN(0) => REGIO_DATAREADY_IN,
+ BUS_WRITE_ACK_IN(0) => REGIO_WRITE_ACK_IN,
+ BUS_NO_MORE_DATA_IN(0) => REGIO_NO_MORE_DATA_IN,
+ BUS_UNKNOWN_ADDR_IN(0) => REGIO_UNKNOWN_ADDR_IN,
+
+ STAT_DEBUG => open
+ );
+
+
---------------------------------------------------------------------
--1-wire interface
---------------------------------------------------------------------
INT_REPLY_DATA_IN : in std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0');
INT_REPLY_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0');
INT_REPLY_READ_OUT : out std_logic_vector (INT_NUMBER downto 0);
+ --REGIO INTERFACE
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
+ REGIO_READ_ENABLE_OUT : out std_logic;
+ REGIO_WRITE_ENABLE_OUT : out std_logic;
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
+ REGIO_DATAREADY_IN : in std_logic := '0';
+ REGIO_NO_MORE_DATA_IN : in std_logic := '0';
+ REGIO_WRITE_ACK_IN : in std_logic := '0';
+ REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';
+ REGIO_TIMEOUT_OUT : out std_logic;
+
ONEWIRE : inout std_logic;
ONEWIRE_MONITOR_IN : in std_logic;
ONEWIRE_MONITOR_OUT : out std_logic;
- component trb_net16_hub_streaming is
- generic(
- --hub control
- HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL;
- HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;
- HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES);
- USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES);
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
- INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
- CLOCK_FREQUENCY : integer range 1 to 200 := 100;
- USE_ONEWIRE : integer range 0 to 2 := c_YES;
- --media interfaces
- MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12;
- MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
- MII_IS_UPLINK : hub_mii_config_t := (others => c_YES);
- MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES)
- );
-
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
+component trb_net16_hub_streaming_port is
+ generic(
+ --hub control
+ HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL;
+ HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;
+ HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES);
+ USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES);
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
+ COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
+ COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
+ HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100;
+ USE_ONEWIRE : integer range 0 to 2 := c_YES;
+ --media interfaces
+ MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12;
+ MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
+ MII_IS_UPLINK : hub_mii_config_t := (others => c_YES);
+ MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES)
+ );
- --Media Interface
- MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
- MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
-
- --Data Output
- --Event information coming from CTS
- IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
- IPU_CODE_OUT : out std_logic_vector (7 downto 0);
- IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
- IPU_START_READOUT_OUT : out std_logic;
- --Answer sent to CTS
- APL_CTS_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_CTS_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_CTS_DATAREADY_IN : in std_logic;
- APL_CTS_READ_OUT : out std_logic;
- APL_CTS_SHORT_TRANSFER_IN : in std_logic;
- APL_CTS_DTYPE_IN : in std_logic_vector (3 downto 0);
- APL_CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
- APL_CTS_SEND_IN : in std_logic;
- APL_CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
- -- Receiver port
- APL_FEE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_FEE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_FEE_TYP_OUT : out std_logic_vector (2 downto 0);
- APL_FEE_DATAREADY_OUT : out std_logic;
- APL_FEE_READ_IN : in std_logic;
- -- APL Control port
- APL_CTS_RUN_OUT : out std_logic;
- APL_FEE_RUN_OUT : out std_logic;
- IPU_MY_ADDRESS_IN : in std_logic_vector(15 downto 0);
-
- COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
- COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
- ONEWIRE : inout std_logic;
- ONEWIRE_MONITOR_IN : in std_logic;
- MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
- --Fixed status and control ports
- HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
- HUB_STAT_GEN : out std_logic_vector (31 downto 0);
- MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
- MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
- STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
- STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
+ --Media Interface
+ MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
+ MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
+ --Event information coming from CTS
+ CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);
+ CTS_CODE_OUT : out std_logic_vector (7 downto 0);
+ CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
+ CTS_START_READOUT_OUT : out std_logic;
+
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_IN : in std_logic_vector (31 downto 0);
+ CTS_DATAREADY_IN : in std_logic;
+ CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM
+ CTS_READ_OUT : out std_logic;
+ CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
+ CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
+
+ -- Data from Frontends
+ FEE_DATA_OUT : out std_logic_vector (31 downto 0);
+ FEE_DATAREADY_OUT : out std_logic;
+ FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready
+ FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
+ FEE_BUSY_OUT : out std_logic;
+
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
+ CTRL_SEQNR_RESET : in std_logic;
+
+ COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
+ COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
+ ONEWIRE : inout std_logic;
+ ONEWIRE_MONITOR_IN : in std_logic;
+ MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
+ --REGIO INTERFACE
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
+ REGIO_READ_ENABLE_OUT : out std_logic;
+ REGIO_WRITE_ENABLE_OUT : out std_logic;
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
+ REGIO_DATAREADY_IN : in std_logic := '0';
+ REGIO_NO_MORE_DATA_IN : in std_logic := '0';
+ REGIO_WRITE_ACK_IN : in std_logic := '0';
+ REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';
+ REGIO_TIMEOUT_OUT : out std_logic;
+
+ --status and control ports
+ HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
+ HUB_STAT_GEN : out std_logic_vector (31 downto 0);
+ MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
+ MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
+ STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
+ STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
--Debugging registers
- STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
- CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
- );
+ STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
+ CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
+ );
end component;