--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144
+-- Module Version: 2.2
+--/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n mulaccsub3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type dspmmac -widtha 9 -widthb 16 -widthp 41 -area -load -macsub -signed -unsignedb -rega -regaclk CLK0 -regace CE0 -regarst RST0 -regb -regbclk CLK0 -regbce CE0 -regbrst RST0 -rego -regoclk CLK0 -regorst RST0 -regoce CE0 -enable_sync -clk0 -ce0 -rst0
+
+-- Tue Apr 23 15:13:52 2019
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity mulaccsub3 is
+ port (
+ CLK0: in std_logic;
+ CE0: in std_logic;
+ RST0: in std_logic;
+ ACCUMSLOAD: in std_logic;
+ A0: in std_logic_vector(8 downto 0);
+ B0: in std_logic_vector(15 downto 0);
+ A1: in std_logic_vector(8 downto 0);
+ B1: in std_logic_vector(15 downto 0);
+ LD: in std_logic_vector(40 downto 0);
+ OVERFLOW: out std_logic;
+ ACCUM: out std_logic_vector(40 downto 0));
+end mulaccsub3;
+
+architecture Structure of mulaccsub3 is
+
+ -- internal signal declarations
+ signal low_inv: std_logic;
+ signal mulaccsub3_alu_signedr_1_0: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_53: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_52: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_51: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_50: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_49: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_48: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_47: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_46: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_45: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_44: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_43: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_42: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_41: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_40: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_39: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_38: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_37: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_36: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_35: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_34: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_33: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_32: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_31: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_30: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_29: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_28: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_27: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_26: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_25: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_24: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_23: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_22: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_21: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_20: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_19: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_18: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_17: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_16: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_15: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_14: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_13: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_12: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_11: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_10: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_9: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_8: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_7: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_6: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_5: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_4: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_3: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_2: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_1: std_logic;
+ signal mulaccsub3_alu_output_r_1_0_0: std_logic;
+ signal mulaccsub3_alu_signedcin_1_0: std_logic;
+ signal load_inv: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_53: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_52: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_51: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_50: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_49: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_48: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_47: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_46: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_45: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_44: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_43: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_42: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_41: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_40: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_39: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_38: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_37: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_36: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_35: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_34: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_33: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_32: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_31: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_30: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_29: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_28: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_27: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_26: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_25: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_24: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_23: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_22: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_21: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_20: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_19: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_18: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_17: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_16: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_15: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_14: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_13: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_12: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_11: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_10: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_9: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_8: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_7: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_6: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_5: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_4: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_3: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_2: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_1: std_logic;
+ signal mulaccsub3_alu_in_cin_1_0_0: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_17: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_17: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_16: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_16: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_15: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_15: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_14: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_14: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_13: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_13: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_12: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_12: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_11: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_11: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_10: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_10: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_9: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_9: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_8: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_8: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_7: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_7: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_6: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_6: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_5: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_5: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_4: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_4: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_3: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_3: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_2: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_2: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_1: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_1: std_logic;
+ signal mulaccsub3_0_mult_out_rob_0_0: std_logic;
+ signal mulaccsub3_0_mult_out_roa_0_0: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_35: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_34: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_33: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_32: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_31: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_30: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_29: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_28: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_27: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_26: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_25: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_24: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_23: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_22: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_21: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_20: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_19: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_18: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_17: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_16: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_15: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_14: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_13: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_12: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_11: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_10: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_9: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_8: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_7: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_6: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_5: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_4: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_3: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_2: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_1: std_logic;
+ signal mulaccsub3_0_mult_out_p_0_0: std_logic;
+ signal mulaccsub3_0_mult_out_signedp_0: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_17: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_17: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_16: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_16: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_15: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_15: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_14: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_14: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_13: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_13: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_12: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_12: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_11: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_11: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_10: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_10: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_9: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_9: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_8: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_8: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_7: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_7: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_6: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_6: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_5: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_5: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_4: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_4: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_3: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_3: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_2: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_2: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_1: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_1: std_logic;
+ signal mulaccsub3_0_mult_out_rob_1_0: std_logic;
+ signal mulaccsub3_0_mult_out_roa_1_0: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_35: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_34: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_33: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_32: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_31: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_30: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_29: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_28: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_27: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_26: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_25: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_24: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_23: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_22: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_21: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_20: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_19: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_18: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_17: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_16: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_15: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_14: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_13: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_12: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_11: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_10: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_9: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_8: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_7: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_6: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_5: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_4: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_3: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_2: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_1: std_logic;
+ signal mulaccsub3_0_mult_out_p_1_0: std_logic;
+ signal mulaccsub3_0_mult_out_signedp_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component MULT18X18C
+ generic (RESETMODE : in String; GSR : in String;
+ MULT_BYPASS : in String; CAS_MATCH_REG : in String;
+ REG_OUTPUT_RST : in String; REG_OUTPUT_CE : in String;
+ REG_OUTPUT_CLK : in String; REG_PIPELINE_RST : in String;
+ REG_PIPELINE_CE : in String;
+ REG_PIPELINE_CLK : in String; REG_INPUTB_RST : in String;
+ REG_INPUTB_CE : in String; REG_INPUTB_CLK : in String;
+ REG_INPUTA_RST : in String; REG_INPUTA_CE : in String;
+ REG_INPUTA_CLK : in String);
+ port (A17: in std_logic; A16: in std_logic; A15: in std_logic;
+ A14: in std_logic; A13: in std_logic; A12: in std_logic;
+ A11: in std_logic; A10: in std_logic; A9: in std_logic;
+ A8: in std_logic; A7: in std_logic; A6: in std_logic;
+ A5: in std_logic; A4: in std_logic; A3: in std_logic;
+ A2: in std_logic; A1: in std_logic; A0: in std_logic;
+ B17: in std_logic; B16: in std_logic; B15: in std_logic;
+ B14: in std_logic; B13: in std_logic; B12: in std_logic;
+ B11: in std_logic; B10: in std_logic; B9: in std_logic;
+ B8: in std_logic; B7: in std_logic; B6: in std_logic;
+ B5: in std_logic; B4: in std_logic; B3: in std_logic;
+ B2: in std_logic; B1: in std_logic; B0: in std_logic;
+ SIGNEDA: in std_logic; SIGNEDB: in std_logic;
+ SOURCEA: in std_logic; SOURCEB: in std_logic;
+ CE0: in std_logic; CE1: in std_logic; CE2: in std_logic;
+ CE3: in std_logic; CLK0: in std_logic; CLK1: in std_logic;
+ CLK2: in std_logic; CLK3: in std_logic;
+ RST0: in std_logic; RST1: in std_logic;
+ RST2: in std_logic; RST3: in std_logic;
+ SRIA17: in std_logic; SRIA16: in std_logic;
+ SRIA15: in std_logic; SRIA14: in std_logic;
+ SRIA13: in std_logic; SRIA12: in std_logic;
+ SRIA11: in std_logic; SRIA10: in std_logic;
+ SRIA9: in std_logic; SRIA8: in std_logic;
+ SRIA7: in std_logic; SRIA6: in std_logic;
+ SRIA5: in std_logic; SRIA4: in std_logic;
+ SRIA3: in std_logic; SRIA2: in std_logic;
+ SRIA1: in std_logic; SRIA0: in std_logic;
+ SRIB17: in std_logic; SRIB16: in std_logic;
+ SRIB15: in std_logic; SRIB14: in std_logic;
+ SRIB13: in std_logic; SRIB12: in std_logic;
+ SRIB11: in std_logic; SRIB10: in std_logic;
+ SRIB9: in std_logic; SRIB8: in std_logic;
+ SRIB7: in std_logic; SRIB6: in std_logic;
+ SRIB5: in std_logic; SRIB4: in std_logic;
+ SRIB3: in std_logic; SRIB2: in std_logic;
+ SRIB1: in std_logic; SRIB0: in std_logic;
+ SROA17: out std_logic; SROA16: out std_logic;
+ SROA15: out std_logic; SROA14: out std_logic;
+ SROA13: out std_logic; SROA12: out std_logic;
+ SROA11: out std_logic; SROA10: out std_logic;
+ SROA9: out std_logic; SROA8: out std_logic;
+ SROA7: out std_logic; SROA6: out std_logic;
+ SROA5: out std_logic; SROA4: out std_logic;
+ SROA3: out std_logic; SROA2: out std_logic;
+ SROA1: out std_logic; SROA0: out std_logic;
+ SROB17: out std_logic; SROB16: out std_logic;
+ SROB15: out std_logic; SROB14: out std_logic;
+ SROB13: out std_logic; SROB12: out std_logic;
+ SROB11: out std_logic; SROB10: out std_logic;
+ SROB9: out std_logic; SROB8: out std_logic;
+ SROB7: out std_logic; SROB6: out std_logic;
+ SROB5: out std_logic; SROB4: out std_logic;
+ SROB3: out std_logic; SROB2: out std_logic;
+ SROB1: out std_logic; SROB0: out std_logic;
+ ROA17: out std_logic; ROA16: out std_logic;
+ ROA15: out std_logic; ROA14: out std_logic;
+ ROA13: out std_logic; ROA12: out std_logic;
+ ROA11: out std_logic; ROA10: out std_logic;
+ ROA9: out std_logic; ROA8: out std_logic;
+ ROA7: out std_logic; ROA6: out std_logic;
+ ROA5: out std_logic; ROA4: out std_logic;
+ ROA3: out std_logic; ROA2: out std_logic;
+ ROA1: out std_logic; ROA0: out std_logic;
+ ROB17: out std_logic; ROB16: out std_logic;
+ ROB15: out std_logic; ROB14: out std_logic;
+ ROB13: out std_logic; ROB12: out std_logic;
+ ROB11: out std_logic; ROB10: out std_logic;
+ ROB9: out std_logic; ROB8: out std_logic;
+ ROB7: out std_logic; ROB6: out std_logic;
+ ROB5: out std_logic; ROB4: out std_logic;
+ ROB3: out std_logic; ROB2: out std_logic;
+ ROB1: out std_logic; ROB0: out std_logic;
+ P35: out std_logic; P34: out std_logic;
+ P33: out std_logic; P32: out std_logic;
+ P31: out std_logic; P30: out std_logic;
+ P29: out std_logic; P28: out std_logic;
+ P27: out std_logic; P26: out std_logic;
+ P25: out std_logic; P24: out std_logic;
+ P23: out std_logic; P22: out std_logic;
+ P21: out std_logic; P20: out std_logic;
+ P19: out std_logic; P18: out std_logic;
+ P17: out std_logic; P16: out std_logic;
+ P15: out std_logic; P14: out std_logic;
+ P13: out std_logic; P12: out std_logic;
+ P11: out std_logic; P10: out std_logic; P9: out std_logic;
+ P8: out std_logic; P7: out std_logic; P6: out std_logic;
+ P5: out std_logic; P4: out std_logic; P3: out std_logic;
+ P2: out std_logic; P1: out std_logic; P0: out std_logic;
+ SIGNEDP: out std_logic);
+ end component;
+ component ALU54A
+ generic (LEGACY : in String; MULT9_MODE : in String;
+ RESETMODE : in String; GSR : in String;
+ RNDPAT : in String; MASKPAT : in String;
+ MCPAT : in String; MASK01 : in String;
+ MASKPAT_SOURCE : in String; MCPAT_SOURCE : in String;
+ REG_FLAG_RST : in String; REG_FLAG_CE : in String;
+ REG_FLAG_CLK : in String; REG_OUTPUT1_RST : in String;
+ REG_OUTPUT1_CE : in String; REG_OUTPUT1_CLK : in String;
+ REG_OUTPUT0_RST : in String; REG_OUTPUT0_CE : in String;
+ REG_OUTPUT0_CLK : in String;
+ REG_OPCODEIN_1_RST : in String;
+ REG_OPCODEIN_1_CE : in String;
+ REG_OPCODEIN_1_CLK : in String;
+ REG_OPCODEIN_0_RST : in String;
+ REG_OPCODEIN_0_CE : in String;
+ REG_OPCODEIN_0_CLK : in String;
+ REG_OPCODEOP1_1_CLK : in String;
+ REG_OPCODEOP1_0_CLK : in String;
+ REG_OPCODEOP0_1_RST : in String;
+ REG_OPCODEOP0_1_CE : in String;
+ REG_OPCODEOP0_1_CLK : in String;
+ REG_OPCODEOP0_0_RST : in String;
+ REG_OPCODEOP0_0_CE : in String;
+ REG_OPCODEOP0_0_CLK : in String;
+ REG_INPUTC1_RST : in String; REG_INPUTC1_CE : in String;
+ REG_INPUTC1_CLK : in String; REG_INPUTC0_RST : in String;
+ REG_INPUTC0_CE : in String; REG_INPUTC0_CLK : in String);
+ port (CE0: in std_logic; CE1: in std_logic; CE2: in std_logic;
+ CE3: in std_logic; CLK0: in std_logic; CLK1: in std_logic;
+ CLK2: in std_logic; CLK3: in std_logic;
+ RST0: in std_logic; RST1: in std_logic;
+ RST2: in std_logic; RST3: in std_logic;
+ SIGNEDIA: in std_logic; SIGNEDIB: in std_logic;
+ A35: in std_logic; A34: in std_logic; A33: in std_logic;
+ A32: in std_logic; A31: in std_logic; A30: in std_logic;
+ A29: in std_logic; A28: in std_logic; A27: in std_logic;
+ A26: in std_logic; A25: in std_logic; A24: in std_logic;
+ A23: in std_logic; A22: in std_logic; A21: in std_logic;
+ A20: in std_logic; A19: in std_logic; A18: in std_logic;
+ A17: in std_logic; A16: in std_logic; A15: in std_logic;
+ A14: in std_logic; A13: in std_logic; A12: in std_logic;
+ A11: in std_logic; A10: in std_logic; A9: in std_logic;
+ A8: in std_logic; A7: in std_logic; A6: in std_logic;
+ A5: in std_logic; A4: in std_logic; A3: in std_logic;
+ A2: in std_logic; A1: in std_logic; A0: in std_logic;
+ B35: in std_logic; B34: in std_logic; B33: in std_logic;
+ B32: in std_logic; B31: in std_logic; B30: in std_logic;
+ B29: in std_logic; B28: in std_logic; B27: in std_logic;
+ B26: in std_logic; B25: in std_logic; B24: in std_logic;
+ B23: in std_logic; B22: in std_logic; B21: in std_logic;
+ B20: in std_logic; B19: in std_logic; B18: in std_logic;
+ B17: in std_logic; B16: in std_logic; B15: in std_logic;
+ B14: in std_logic; B13: in std_logic; B12: in std_logic;
+ B11: in std_logic; B10: in std_logic; B9: in std_logic;
+ B8: in std_logic; B7: in std_logic; B6: in std_logic;
+ B5: in std_logic; B4: in std_logic; B3: in std_logic;
+ B2: in std_logic; B1: in std_logic; B0: in std_logic;
+ C53: in std_logic; C52: in std_logic; C51: in std_logic;
+ C50: in std_logic; C49: in std_logic; C48: in std_logic;
+ C47: in std_logic; C46: in std_logic; C45: in std_logic;
+ C44: in std_logic; C43: in std_logic; C42: in std_logic;
+ C41: in std_logic; C40: in std_logic; C39: in std_logic;
+ C38: in std_logic; C37: in std_logic; C36: in std_logic;
+ C35: in std_logic; C34: in std_logic; C33: in std_logic;
+ C32: in std_logic; C31: in std_logic; C30: in std_logic;
+ C29: in std_logic; C28: in std_logic; C27: in std_logic;
+ C26: in std_logic; C25: in std_logic; C24: in std_logic;
+ C23: in std_logic; C22: in std_logic; C21: in std_logic;
+ C20: in std_logic; C19: in std_logic; C18: in std_logic;
+ C17: in std_logic; C16: in std_logic; C15: in std_logic;
+ C14: in std_logic; C13: in std_logic; C12: in std_logic;
+ C11: in std_logic; C10: in std_logic; C9: in std_logic;
+ C8: in std_logic; C7: in std_logic; C6: in std_logic;
+ C5: in std_logic; C4: in std_logic; C3: in std_logic;
+ C2: in std_logic; C1: in std_logic; C0: in std_logic;
+ MA35: in std_logic; MA34: in std_logic;
+ MA33: in std_logic; MA32: in std_logic;
+ MA31: in std_logic; MA30: in std_logic;
+ MA29: in std_logic; MA28: in std_logic;
+ MA27: in std_logic; MA26: in std_logic;
+ MA25: in std_logic; MA24: in std_logic;
+ MA23: in std_logic; MA22: in std_logic;
+ MA21: in std_logic; MA20: in std_logic;
+ MA19: in std_logic; MA18: in std_logic;
+ MA17: in std_logic; MA16: in std_logic;
+ MA15: in std_logic; MA14: in std_logic;
+ MA13: in std_logic; MA12: in std_logic;
+ MA11: in std_logic; MA10: in std_logic; MA9: in std_logic;
+ MA8: in std_logic; MA7: in std_logic; MA6: in std_logic;
+ MA5: in std_logic; MA4: in std_logic; MA3: in std_logic;
+ MA2: in std_logic; MA1: in std_logic; MA0: in std_logic;
+ MB35: in std_logic; MB34: in std_logic;
+ MB33: in std_logic; MB32: in std_logic;
+ MB31: in std_logic; MB30: in std_logic;
+ MB29: in std_logic; MB28: in std_logic;
+ MB27: in std_logic; MB26: in std_logic;
+ MB25: in std_logic; MB24: in std_logic;
+ MB23: in std_logic; MB22: in std_logic;
+ MB21: in std_logic; MB20: in std_logic;
+ MB19: in std_logic; MB18: in std_logic;
+ MB17: in std_logic; MB16: in std_logic;
+ MB15: in std_logic; MB14: in std_logic;
+ MB13: in std_logic; MB12: in std_logic;
+ MB11: in std_logic; MB10: in std_logic; MB9: in std_logic;
+ MB8: in std_logic; MB7: in std_logic; MB6: in std_logic;
+ MB5: in std_logic; MB4: in std_logic; MB3: in std_logic;
+ MB2: in std_logic; MB1: in std_logic; MB0: in std_logic;
+ CIN53: in std_logic; CIN52: in std_logic;
+ CIN51: in std_logic; CIN50: in std_logic;
+ CIN49: in std_logic; CIN48: in std_logic;
+ CIN47: in std_logic; CIN46: in std_logic;
+ CIN45: in std_logic; CIN44: in std_logic;
+ CIN43: in std_logic; CIN42: in std_logic;
+ CIN41: in std_logic; CIN40: in std_logic;
+ CIN39: in std_logic; CIN38: in std_logic;
+ CIN37: in std_logic; CIN36: in std_logic;
+ CIN35: in std_logic; CIN34: in std_logic;
+ CIN33: in std_logic; CIN32: in std_logic;
+ CIN31: in std_logic; CIN30: in std_logic;
+ CIN29: in std_logic; CIN28: in std_logic;
+ CIN27: in std_logic; CIN26: in std_logic;
+ CIN25: in std_logic; CIN24: in std_logic;
+ CIN23: in std_logic; CIN22: in std_logic;
+ CIN21: in std_logic; CIN20: in std_logic;
+ CIN19: in std_logic; CIN18: in std_logic;
+ CIN17: in std_logic; CIN16: in std_logic;
+ CIN15: in std_logic; CIN14: in std_logic;
+ CIN13: in std_logic; CIN12: in std_logic;
+ CIN11: in std_logic; CIN10: in std_logic;
+ CIN9: in std_logic; CIN8: in std_logic;
+ CIN7: in std_logic; CIN6: in std_logic;
+ CIN5: in std_logic; CIN4: in std_logic;
+ CIN3: in std_logic; CIN2: in std_logic;
+ CIN1: in std_logic; CIN0: in std_logic;
+ SIGNEDCIN: in std_logic; OP10: in std_logic;
+ OP9: in std_logic; OP8: in std_logic; OP7: in std_logic;
+ OP6: in std_logic; OP5: in std_logic; OP4: in std_logic;
+ OP3: in std_logic; OP2: in std_logic; OP1: in std_logic;
+ OP0: in std_logic; R53: out std_logic; R52: out std_logic;
+ R51: out std_logic; R50: out std_logic;
+ R49: out std_logic; R48: out std_logic;
+ R47: out std_logic; R46: out std_logic;
+ R45: out std_logic; R44: out std_logic;
+ R43: out std_logic; R42: out std_logic;
+ R41: out std_logic; R40: out std_logic;
+ R39: out std_logic; R38: out std_logic;
+ R37: out std_logic; R36: out std_logic;
+ R35: out std_logic; R34: out std_logic;
+ R33: out std_logic; R32: out std_logic;
+ R31: out std_logic; R30: out std_logic;
+ R29: out std_logic; R28: out std_logic;
+ R27: out std_logic; R26: out std_logic;
+ R25: out std_logic; R24: out std_logic;
+ R23: out std_logic; R22: out std_logic;
+ R21: out std_logic; R20: out std_logic;
+ R19: out std_logic; R18: out std_logic;
+ R17: out std_logic; R16: out std_logic;
+ R15: out std_logic; R14: out std_logic;
+ R13: out std_logic; R12: out std_logic;
+ R11: out std_logic; R10: out std_logic; R9: out std_logic;
+ R8: out std_logic; R7: out std_logic; R6: out std_logic;
+ R5: out std_logic; R4: out std_logic; R3: out std_logic;
+ R2: out std_logic; R1: out std_logic; R0: out std_logic;
+ EQZ: out std_logic; EQZM: out std_logic;
+ EQOM: out std_logic; EQPAT: out std_logic;
+ EQPATB: out std_logic; OVER: out std_logic;
+ UNDER: out std_logic; OVERUNDER: out std_logic;
+ SIGNEDR: out std_logic);
+ end component;
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ INV_1: INV
+ port map (A=>scuba_vlo, Z=>low_inv);
+
+ INV_0: INV
+ port map (A=>ACCUMSLOAD, Z=>load_inv);
+
+ dsp_alu_0: ALU54A
+ generic map (REG_OPCODEIN_1_RST=> "RST0", REG_OPCODEIN_1_CE=> "CE0",
+ REG_OPCODEIN_1_CLK=> "NONE", REG_OPCODEIN_0_RST=> "RST0",
+ REG_OPCODEIN_0_CE=> "CE0", REG_OPCODEIN_0_CLK=> "NONE",
+ REG_OPCODEOP1_1_CLK=> "NONE", REG_OPCODEOP1_0_CLK=> "NONE",
+ REG_OPCODEOP0_1_RST=> "RST0", REG_OPCODEOP0_1_CE=> "CE0",
+ REG_OPCODEOP0_1_CLK=> "NONE", REG_OPCODEOP0_0_RST=> "RST0",
+ REG_OPCODEOP0_0_CE=> "CE0", REG_OPCODEOP0_0_CLK=> "NONE",
+ REG_INPUTC1_RST=> "RST0", REG_INPUTC1_CE=> "CE0",
+ REG_INPUTC1_CLK=> "NONE", REG_INPUTC0_RST=> "RST0",
+ REG_INPUTC0_CE=> "CE0", REG_INPUTC0_CLK=> "NONE", LEGACY=> "DISABLED",
+ REG_FLAG_RST=> "RST0", REG_FLAG_CE=> "CE0", REG_FLAG_CLK=> "CLK0",
+ REG_OUTPUT1_RST=> "RST0", REG_OUTPUT1_CE=> "CE0",
+ REG_OUTPUT1_CLK=> "CLK0", REG_OUTPUT0_RST=> "RST0",
+ REG_OUTPUT0_CE=> "CE0", REG_OUTPUT0_CLK=> "CLK0", MULT9_MODE=> "DISABLED",
+ RNDPAT=> "0x00000000000000", MASKPAT=> "0x00000000000000", MCPAT=> "0x00000000000000",
+ MASK01=> "0x27FFFFFFFFFFFF", MASKPAT_SOURCE=> "STATIC",
+ MCPAT_SOURCE=> "STATIC", RESETMODE=> "SYNC", GSR=> "ENABLED")
+ port map (CE0=>CE0, CE1=>scuba_vhi, CE2=>scuba_vhi,
+ CE3=>scuba_vhi, CLK0=>CLK0, CLK1=>scuba_vlo, CLK2=>scuba_vlo,
+ CLK3=>scuba_vlo, RST0=>RST0, RST1=>scuba_vlo,
+ RST2=>scuba_vlo, RST3=>scuba_vlo,
+ SIGNEDIA=>mulaccsub3_0_mult_out_signedp_0,
+ SIGNEDIB=>mulaccsub3_0_mult_out_signedp_1,
+ A35=>mulaccsub3_0_mult_out_rob_0_17,
+ A34=>mulaccsub3_0_mult_out_rob_0_16,
+ A33=>mulaccsub3_0_mult_out_rob_0_15,
+ A32=>mulaccsub3_0_mult_out_rob_0_14,
+ A31=>mulaccsub3_0_mult_out_rob_0_13,
+ A30=>mulaccsub3_0_mult_out_rob_0_12,
+ A29=>mulaccsub3_0_mult_out_rob_0_11,
+ A28=>mulaccsub3_0_mult_out_rob_0_10,
+ A27=>mulaccsub3_0_mult_out_rob_0_9,
+ A26=>mulaccsub3_0_mult_out_rob_0_8,
+ A25=>mulaccsub3_0_mult_out_rob_0_7,
+ A24=>mulaccsub3_0_mult_out_rob_0_6,
+ A23=>mulaccsub3_0_mult_out_rob_0_5,
+ A22=>mulaccsub3_0_mult_out_rob_0_4,
+ A21=>mulaccsub3_0_mult_out_rob_0_3,
+ A20=>mulaccsub3_0_mult_out_rob_0_2,
+ A19=>mulaccsub3_0_mult_out_rob_0_1,
+ A18=>mulaccsub3_0_mult_out_rob_0_0,
+ A17=>mulaccsub3_0_mult_out_roa_0_17,
+ A16=>mulaccsub3_0_mult_out_roa_0_16,
+ A15=>mulaccsub3_0_mult_out_roa_0_15,
+ A14=>mulaccsub3_0_mult_out_roa_0_14,
+ A13=>mulaccsub3_0_mult_out_roa_0_13,
+ A12=>mulaccsub3_0_mult_out_roa_0_12,
+ A11=>mulaccsub3_0_mult_out_roa_0_11,
+ A10=>mulaccsub3_0_mult_out_roa_0_10,
+ A9=>mulaccsub3_0_mult_out_roa_0_9,
+ A8=>mulaccsub3_0_mult_out_roa_0_8,
+ A7=>mulaccsub3_0_mult_out_roa_0_7,
+ A6=>mulaccsub3_0_mult_out_roa_0_6,
+ A5=>mulaccsub3_0_mult_out_roa_0_5,
+ A4=>mulaccsub3_0_mult_out_roa_0_4,
+ A3=>mulaccsub3_0_mult_out_roa_0_3,
+ A2=>mulaccsub3_0_mult_out_roa_0_2,
+ A1=>mulaccsub3_0_mult_out_roa_0_1,
+ A0=>mulaccsub3_0_mult_out_roa_0_0,
+ B35=>mulaccsub3_0_mult_out_rob_1_17,
+ B34=>mulaccsub3_0_mult_out_rob_1_16,
+ B33=>mulaccsub3_0_mult_out_rob_1_15,
+ B32=>mulaccsub3_0_mult_out_rob_1_14,
+ B31=>mulaccsub3_0_mult_out_rob_1_13,
+ B30=>mulaccsub3_0_mult_out_rob_1_12,
+ B29=>mulaccsub3_0_mult_out_rob_1_11,
+ B28=>mulaccsub3_0_mult_out_rob_1_10,
+ B27=>mulaccsub3_0_mult_out_rob_1_9,
+ B26=>mulaccsub3_0_mult_out_rob_1_8,
+ B25=>mulaccsub3_0_mult_out_rob_1_7,
+ B24=>mulaccsub3_0_mult_out_rob_1_6,
+ B23=>mulaccsub3_0_mult_out_rob_1_5,
+ B22=>mulaccsub3_0_mult_out_rob_1_4,
+ B21=>mulaccsub3_0_mult_out_rob_1_3,
+ B20=>mulaccsub3_0_mult_out_rob_1_2,
+ B19=>mulaccsub3_0_mult_out_rob_1_1,
+ B18=>mulaccsub3_0_mult_out_rob_1_0,
+ B17=>mulaccsub3_0_mult_out_roa_1_17,
+ B16=>mulaccsub3_0_mult_out_roa_1_16,
+ B15=>mulaccsub3_0_mult_out_roa_1_15,
+ B14=>mulaccsub3_0_mult_out_roa_1_14,
+ B13=>mulaccsub3_0_mult_out_roa_1_13,
+ B12=>mulaccsub3_0_mult_out_roa_1_12,
+ B11=>mulaccsub3_0_mult_out_roa_1_11,
+ B10=>mulaccsub3_0_mult_out_roa_1_10,
+ B9=>mulaccsub3_0_mult_out_roa_1_9,
+ B8=>mulaccsub3_0_mult_out_roa_1_8,
+ B7=>mulaccsub3_0_mult_out_roa_1_7,
+ B6=>mulaccsub3_0_mult_out_roa_1_6,
+ B5=>mulaccsub3_0_mult_out_roa_1_5,
+ B4=>mulaccsub3_0_mult_out_roa_1_4,
+ B3=>mulaccsub3_0_mult_out_roa_1_3,
+ B2=>mulaccsub3_0_mult_out_roa_1_2,
+ B1=>mulaccsub3_0_mult_out_roa_1_1,
+ B0=>mulaccsub3_0_mult_out_roa_1_0, C53=>LD(40), C52=>LD(40),
+ C51=>LD(40), C50=>LD(39), C49=>LD(38), C48=>LD(37),
+ C47=>LD(36), C46=>LD(35), C45=>LD(34), C44=>LD(33),
+ C43=>LD(32), C42=>LD(31), C41=>LD(30), C40=>LD(29),
+ C39=>LD(28), C38=>LD(27), C37=>LD(26), C36=>LD(25),
+ C35=>LD(24), C34=>LD(23), C33=>LD(22), C32=>LD(21),
+ C31=>LD(20), C30=>LD(19), C29=>LD(18), C28=>LD(17),
+ C27=>LD(16), C26=>LD(15), C25=>LD(14), C24=>LD(13),
+ C23=>LD(12), C22=>LD(11), C21=>LD(10), C20=>LD(9),
+ C19=>LD(8), C18=>LD(7), C17=>LD(6), C16=>LD(5), C15=>LD(4),
+ C14=>LD(3), C13=>LD(2), C12=>LD(1), C11=>LD(0),
+ C10=>scuba_vlo, C9=>scuba_vlo, C8=>scuba_vlo, C7=>scuba_vlo,
+ C6=>scuba_vlo, C5=>scuba_vlo, C4=>scuba_vlo, C3=>scuba_vlo,
+ C2=>scuba_vlo, C1=>scuba_vlo, C0=>scuba_vlo,
+ MA35=>mulaccsub3_0_mult_out_p_0_35,
+ MA34=>mulaccsub3_0_mult_out_p_0_34,
+ MA33=>mulaccsub3_0_mult_out_p_0_33,
+ MA32=>mulaccsub3_0_mult_out_p_0_32,
+ MA31=>mulaccsub3_0_mult_out_p_0_31,
+ MA30=>mulaccsub3_0_mult_out_p_0_30,
+ MA29=>mulaccsub3_0_mult_out_p_0_29,
+ MA28=>mulaccsub3_0_mult_out_p_0_28,
+ MA27=>mulaccsub3_0_mult_out_p_0_27,
+ MA26=>mulaccsub3_0_mult_out_p_0_26,
+ MA25=>mulaccsub3_0_mult_out_p_0_25,
+ MA24=>mulaccsub3_0_mult_out_p_0_24,
+ MA23=>mulaccsub3_0_mult_out_p_0_23,
+ MA22=>mulaccsub3_0_mult_out_p_0_22,
+ MA21=>mulaccsub3_0_mult_out_p_0_21,
+ MA20=>mulaccsub3_0_mult_out_p_0_20,
+ MA19=>mulaccsub3_0_mult_out_p_0_19,
+ MA18=>mulaccsub3_0_mult_out_p_0_18,
+ MA17=>mulaccsub3_0_mult_out_p_0_17,
+ MA16=>mulaccsub3_0_mult_out_p_0_16,
+ MA15=>mulaccsub3_0_mult_out_p_0_15,
+ MA14=>mulaccsub3_0_mult_out_p_0_14,
+ MA13=>mulaccsub3_0_mult_out_p_0_13,
+ MA12=>mulaccsub3_0_mult_out_p_0_12,
+ MA11=>mulaccsub3_0_mult_out_p_0_11,
+ MA10=>mulaccsub3_0_mult_out_p_0_10,
+ MA9=>mulaccsub3_0_mult_out_p_0_9,
+ MA8=>mulaccsub3_0_mult_out_p_0_8,
+ MA7=>mulaccsub3_0_mult_out_p_0_7,
+ MA6=>mulaccsub3_0_mult_out_p_0_6,
+ MA5=>mulaccsub3_0_mult_out_p_0_5,
+ MA4=>mulaccsub3_0_mult_out_p_0_4,
+ MA3=>mulaccsub3_0_mult_out_p_0_3,
+ MA2=>mulaccsub3_0_mult_out_p_0_2,
+ MA1=>mulaccsub3_0_mult_out_p_0_1,
+ MA0=>mulaccsub3_0_mult_out_p_0_0,
+ MB35=>mulaccsub3_0_mult_out_p_1_35,
+ MB34=>mulaccsub3_0_mult_out_p_1_34,
+ MB33=>mulaccsub3_0_mult_out_p_1_33,
+ MB32=>mulaccsub3_0_mult_out_p_1_32,
+ MB31=>mulaccsub3_0_mult_out_p_1_31,
+ MB30=>mulaccsub3_0_mult_out_p_1_30,
+ MB29=>mulaccsub3_0_mult_out_p_1_29,
+ MB28=>mulaccsub3_0_mult_out_p_1_28,
+ MB27=>mulaccsub3_0_mult_out_p_1_27,
+ MB26=>mulaccsub3_0_mult_out_p_1_26,
+ MB25=>mulaccsub3_0_mult_out_p_1_25,
+ MB24=>mulaccsub3_0_mult_out_p_1_24,
+ MB23=>mulaccsub3_0_mult_out_p_1_23,
+ MB22=>mulaccsub3_0_mult_out_p_1_22,
+ MB21=>mulaccsub3_0_mult_out_p_1_21,
+ MB20=>mulaccsub3_0_mult_out_p_1_20,
+ MB19=>mulaccsub3_0_mult_out_p_1_19,
+ MB18=>mulaccsub3_0_mult_out_p_1_18,
+ MB17=>mulaccsub3_0_mult_out_p_1_17,
+ MB16=>mulaccsub3_0_mult_out_p_1_16,
+ MB15=>mulaccsub3_0_mult_out_p_1_15,
+ MB14=>mulaccsub3_0_mult_out_p_1_14,
+ MB13=>mulaccsub3_0_mult_out_p_1_13,
+ MB12=>mulaccsub3_0_mult_out_p_1_12,
+ MB11=>mulaccsub3_0_mult_out_p_1_11,
+ MB10=>mulaccsub3_0_mult_out_p_1_10,
+ MB9=>mulaccsub3_0_mult_out_p_1_9,
+ MB8=>mulaccsub3_0_mult_out_p_1_8,
+ MB7=>mulaccsub3_0_mult_out_p_1_7,
+ MB6=>mulaccsub3_0_mult_out_p_1_6,
+ MB5=>mulaccsub3_0_mult_out_p_1_5,
+ MB4=>mulaccsub3_0_mult_out_p_1_4,
+ MB3=>mulaccsub3_0_mult_out_p_1_3,
+ MB2=>mulaccsub3_0_mult_out_p_1_2,
+ MB1=>mulaccsub3_0_mult_out_p_1_1,
+ MB0=>mulaccsub3_0_mult_out_p_1_0,
+ CIN53=>mulaccsub3_alu_in_cin_1_0_53,
+ CIN52=>mulaccsub3_alu_in_cin_1_0_52,
+ CIN51=>mulaccsub3_alu_in_cin_1_0_51,
+ CIN50=>mulaccsub3_alu_in_cin_1_0_50,
+ CIN49=>mulaccsub3_alu_in_cin_1_0_49,
+ CIN48=>mulaccsub3_alu_in_cin_1_0_48,
+ CIN47=>mulaccsub3_alu_in_cin_1_0_47,
+ CIN46=>mulaccsub3_alu_in_cin_1_0_46,
+ CIN45=>mulaccsub3_alu_in_cin_1_0_45,
+ CIN44=>mulaccsub3_alu_in_cin_1_0_44,
+ CIN43=>mulaccsub3_alu_in_cin_1_0_43,
+ CIN42=>mulaccsub3_alu_in_cin_1_0_42,
+ CIN41=>mulaccsub3_alu_in_cin_1_0_41,
+ CIN40=>mulaccsub3_alu_in_cin_1_0_40,
+ CIN39=>mulaccsub3_alu_in_cin_1_0_39,
+ CIN38=>mulaccsub3_alu_in_cin_1_0_38,
+ CIN37=>mulaccsub3_alu_in_cin_1_0_37,
+ CIN36=>mulaccsub3_alu_in_cin_1_0_36,
+ CIN35=>mulaccsub3_alu_in_cin_1_0_35,
+ CIN34=>mulaccsub3_alu_in_cin_1_0_34,
+ CIN33=>mulaccsub3_alu_in_cin_1_0_33,
+ CIN32=>mulaccsub3_alu_in_cin_1_0_32,
+ CIN31=>mulaccsub3_alu_in_cin_1_0_31,
+ CIN30=>mulaccsub3_alu_in_cin_1_0_30,
+ CIN29=>mulaccsub3_alu_in_cin_1_0_29,
+ CIN28=>mulaccsub3_alu_in_cin_1_0_28,
+ CIN27=>mulaccsub3_alu_in_cin_1_0_27,
+ CIN26=>mulaccsub3_alu_in_cin_1_0_26,
+ CIN25=>mulaccsub3_alu_in_cin_1_0_25,
+ CIN24=>mulaccsub3_alu_in_cin_1_0_24,
+ CIN23=>mulaccsub3_alu_in_cin_1_0_23,
+ CIN22=>mulaccsub3_alu_in_cin_1_0_22,
+ CIN21=>mulaccsub3_alu_in_cin_1_0_21,
+ CIN20=>mulaccsub3_alu_in_cin_1_0_20,
+ CIN19=>mulaccsub3_alu_in_cin_1_0_19,
+ CIN18=>mulaccsub3_alu_in_cin_1_0_18,
+ CIN17=>mulaccsub3_alu_in_cin_1_0_17,
+ CIN16=>mulaccsub3_alu_in_cin_1_0_16,
+ CIN15=>mulaccsub3_alu_in_cin_1_0_15,
+ CIN14=>mulaccsub3_alu_in_cin_1_0_14,
+ CIN13=>mulaccsub3_alu_in_cin_1_0_13,
+ CIN12=>mulaccsub3_alu_in_cin_1_0_12,
+ CIN11=>mulaccsub3_alu_in_cin_1_0_11,
+ CIN10=>mulaccsub3_alu_in_cin_1_0_10,
+ CIN9=>mulaccsub3_alu_in_cin_1_0_9,
+ CIN8=>mulaccsub3_alu_in_cin_1_0_8,
+ CIN7=>mulaccsub3_alu_in_cin_1_0_7,
+ CIN6=>mulaccsub3_alu_in_cin_1_0_6,
+ CIN5=>mulaccsub3_alu_in_cin_1_0_5,
+ CIN4=>mulaccsub3_alu_in_cin_1_0_4,
+ CIN3=>mulaccsub3_alu_in_cin_1_0_3,
+ CIN2=>mulaccsub3_alu_in_cin_1_0_2,
+ CIN1=>mulaccsub3_alu_in_cin_1_0_1,
+ CIN0=>mulaccsub3_alu_in_cin_1_0_0,
+ SIGNEDCIN=>mulaccsub3_alu_signedcin_1_0, OP10=>scuba_vlo,
+ OP9=>scuba_vhi, OP8=>scuba_vlo, OP7=>scuba_vhi,
+ OP6=>load_inv, OP5=>ACCUMSLOAD, OP4=>scuba_vhi,
+ OP3=>scuba_vlo, OP2=>scuba_vhi, OP1=>scuba_vlo,
+ OP0=>scuba_vhi, R53=>mulaccsub3_alu_output_r_1_0_53,
+ R52=>mulaccsub3_alu_output_r_1_0_52,
+ R51=>mulaccsub3_alu_output_r_1_0_51,
+ R50=>mulaccsub3_alu_output_r_1_0_50,
+ R49=>mulaccsub3_alu_output_r_1_0_49,
+ R48=>mulaccsub3_alu_output_r_1_0_48,
+ R47=>mulaccsub3_alu_output_r_1_0_47,
+ R46=>mulaccsub3_alu_output_r_1_0_46,
+ R45=>mulaccsub3_alu_output_r_1_0_45,
+ R44=>mulaccsub3_alu_output_r_1_0_44,
+ R43=>mulaccsub3_alu_output_r_1_0_43,
+ R42=>mulaccsub3_alu_output_r_1_0_42,
+ R41=>mulaccsub3_alu_output_r_1_0_41,
+ R40=>mulaccsub3_alu_output_r_1_0_40,
+ R39=>mulaccsub3_alu_output_r_1_0_39,
+ R38=>mulaccsub3_alu_output_r_1_0_38,
+ R37=>mulaccsub3_alu_output_r_1_0_37,
+ R36=>mulaccsub3_alu_output_r_1_0_36,
+ R35=>mulaccsub3_alu_output_r_1_0_35,
+ R34=>mulaccsub3_alu_output_r_1_0_34,
+ R33=>mulaccsub3_alu_output_r_1_0_33,
+ R32=>mulaccsub3_alu_output_r_1_0_32,
+ R31=>mulaccsub3_alu_output_r_1_0_31,
+ R30=>mulaccsub3_alu_output_r_1_0_30,
+ R29=>mulaccsub3_alu_output_r_1_0_29,
+ R28=>mulaccsub3_alu_output_r_1_0_28,
+ R27=>mulaccsub3_alu_output_r_1_0_27,
+ R26=>mulaccsub3_alu_output_r_1_0_26,
+ R25=>mulaccsub3_alu_output_r_1_0_25,
+ R24=>mulaccsub3_alu_output_r_1_0_24,
+ R23=>mulaccsub3_alu_output_r_1_0_23,
+ R22=>mulaccsub3_alu_output_r_1_0_22,
+ R21=>mulaccsub3_alu_output_r_1_0_21,
+ R20=>mulaccsub3_alu_output_r_1_0_20,
+ R19=>mulaccsub3_alu_output_r_1_0_19,
+ R18=>mulaccsub3_alu_output_r_1_0_18,
+ R17=>mulaccsub3_alu_output_r_1_0_17,
+ R16=>mulaccsub3_alu_output_r_1_0_16,
+ R15=>mulaccsub3_alu_output_r_1_0_15,
+ R14=>mulaccsub3_alu_output_r_1_0_14,
+ R13=>mulaccsub3_alu_output_r_1_0_13,
+ R12=>mulaccsub3_alu_output_r_1_0_12,
+ R11=>mulaccsub3_alu_output_r_1_0_11,
+ R10=>mulaccsub3_alu_output_r_1_0_10,
+ R9=>mulaccsub3_alu_output_r_1_0_9,
+ R8=>mulaccsub3_alu_output_r_1_0_8,
+ R7=>mulaccsub3_alu_output_r_1_0_7,
+ R6=>mulaccsub3_alu_output_r_1_0_6,
+ R5=>mulaccsub3_alu_output_r_1_0_5,
+ R4=>mulaccsub3_alu_output_r_1_0_4,
+ R3=>mulaccsub3_alu_output_r_1_0_3,
+ R2=>mulaccsub3_alu_output_r_1_0_2,
+ R1=>mulaccsub3_alu_output_r_1_0_1,
+ R0=>mulaccsub3_alu_output_r_1_0_0, EQZ=>open, EQZM=>open,
+ EQOM=>open, EQPAT=>open, EQPATB=>open, OVER=>open,
+ UNDER=>open, OVERUNDER=>OVERFLOW,
+ SIGNEDR=>mulaccsub3_alu_signedr_1_0);
+
+ dsp_mult_1: MULT18X18C
+ generic map (MULT_BYPASS=> "DISABLED", CAS_MATCH_REG=> "FALSE",
+ RESETMODE=> "SYNC", GSR=> "ENABLED", REG_OUTPUT_RST=> "RST0",
+ REG_OUTPUT_CE=> "CE0", REG_OUTPUT_CLK=> "NONE", REG_PIPELINE_RST=> "RST0",
+ REG_PIPELINE_CE=> "CE0", REG_PIPELINE_CLK=> "NONE",
+ REG_INPUTB_RST=> "RST0", REG_INPUTB_CE=> "CE0", REG_INPUTB_CLK=> "CLK0",
+ REG_INPUTA_RST=> "RST0", REG_INPUTA_CE=> "CE0", REG_INPUTA_CLK=> "CLK0")
+ port map (A17=>A0(8), A16=>A0(7), A15=>A0(6), A14=>A0(5),
+ A13=>A0(4), A12=>A0(3), A11=>A0(2), A10=>A0(1), A9=>A0(0),
+ A8=>scuba_vlo, A7=>scuba_vlo, A6=>scuba_vlo, A5=>scuba_vlo,
+ A4=>scuba_vlo, A3=>scuba_vlo, A2=>scuba_vlo, A1=>scuba_vlo,
+ A0=>scuba_vlo, B17=>B0(15), B16=>B0(14), B15=>B0(13),
+ B14=>B0(12), B13=>B0(11), B12=>B0(10), B11=>B0(9),
+ B10=>B0(8), B9=>B0(7), B8=>B0(6), B7=>B0(5), B6=>B0(4),
+ B5=>B0(3), B4=>B0(2), B3=>B0(1), B2=>B0(0), B1=>scuba_vlo,
+ B0=>scuba_vlo, SIGNEDA=>scuba_vhi, SIGNEDB=>scuba_vlo,
+ SOURCEA=>scuba_vlo, SOURCEB=>scuba_vlo, CE0=>CE0,
+ CE1=>scuba_vhi, CE2=>scuba_vhi, CE3=>scuba_vhi, CLK0=>CLK0,
+ CLK1=>scuba_vlo, CLK2=>scuba_vlo, CLK3=>scuba_vlo,
+ RST0=>RST0, RST1=>scuba_vlo, RST2=>scuba_vlo,
+ RST3=>scuba_vlo, SRIA17=>scuba_vlo, SRIA16=>scuba_vlo,
+ SRIA15=>scuba_vlo, SRIA14=>scuba_vlo, SRIA13=>scuba_vlo,
+ SRIA12=>scuba_vlo, SRIA11=>scuba_vlo, SRIA10=>scuba_vlo,
+ SRIA9=>scuba_vlo, SRIA8=>scuba_vlo, SRIA7=>scuba_vlo,
+ SRIA6=>scuba_vlo, SRIA5=>scuba_vlo, SRIA4=>scuba_vlo,
+ SRIA3=>scuba_vlo, SRIA2=>scuba_vlo, SRIA1=>scuba_vlo,
+ SRIA0=>scuba_vlo, SRIB17=>scuba_vlo, SRIB16=>scuba_vlo,
+ SRIB15=>scuba_vlo, SRIB14=>scuba_vlo, SRIB13=>scuba_vlo,
+ SRIB12=>scuba_vlo, SRIB11=>scuba_vlo, SRIB10=>scuba_vlo,
+ SRIB9=>scuba_vlo, SRIB8=>scuba_vlo, SRIB7=>scuba_vlo,
+ SRIB6=>scuba_vlo, SRIB5=>scuba_vlo, SRIB4=>scuba_vlo,
+ SRIB3=>scuba_vlo, SRIB2=>scuba_vlo, SRIB1=>scuba_vlo,
+ SRIB0=>scuba_vlo, SROA17=>open, SROA16=>open, SROA15=>open,
+ SROA14=>open, SROA13=>open, SROA12=>open, SROA11=>open,
+ SROA10=>open, SROA9=>open, SROA8=>open, SROA7=>open,
+ SROA6=>open, SROA5=>open, SROA4=>open, SROA3=>open,
+ SROA2=>open, SROA1=>open, SROA0=>open, SROB17=>open,
+ SROB16=>open, SROB15=>open, SROB14=>open, SROB13=>open,
+ SROB12=>open, SROB11=>open, SROB10=>open, SROB9=>open,
+ SROB8=>open, SROB7=>open, SROB6=>open, SROB5=>open,
+ SROB4=>open, SROB3=>open, SROB2=>open, SROB1=>open,
+ SROB0=>open, ROA17=>mulaccsub3_0_mult_out_roa_0_17,
+ ROA16=>mulaccsub3_0_mult_out_roa_0_16,
+ ROA15=>mulaccsub3_0_mult_out_roa_0_15,
+ ROA14=>mulaccsub3_0_mult_out_roa_0_14,
+ ROA13=>mulaccsub3_0_mult_out_roa_0_13,
+ ROA12=>mulaccsub3_0_mult_out_roa_0_12,
+ ROA11=>mulaccsub3_0_mult_out_roa_0_11,
+ ROA10=>mulaccsub3_0_mult_out_roa_0_10,
+ ROA9=>mulaccsub3_0_mult_out_roa_0_9,
+ ROA8=>mulaccsub3_0_mult_out_roa_0_8,
+ ROA7=>mulaccsub3_0_mult_out_roa_0_7,
+ ROA6=>mulaccsub3_0_mult_out_roa_0_6,
+ ROA5=>mulaccsub3_0_mult_out_roa_0_5,
+ ROA4=>mulaccsub3_0_mult_out_roa_0_4,
+ ROA3=>mulaccsub3_0_mult_out_roa_0_3,
+ ROA2=>mulaccsub3_0_mult_out_roa_0_2,
+ ROA1=>mulaccsub3_0_mult_out_roa_0_1,
+ ROA0=>mulaccsub3_0_mult_out_roa_0_0,
+ ROB17=>mulaccsub3_0_mult_out_rob_0_17,
+ ROB16=>mulaccsub3_0_mult_out_rob_0_16,
+ ROB15=>mulaccsub3_0_mult_out_rob_0_15,
+ ROB14=>mulaccsub3_0_mult_out_rob_0_14,
+ ROB13=>mulaccsub3_0_mult_out_rob_0_13,
+ ROB12=>mulaccsub3_0_mult_out_rob_0_12,
+ ROB11=>mulaccsub3_0_mult_out_rob_0_11,
+ ROB10=>mulaccsub3_0_mult_out_rob_0_10,
+ ROB9=>mulaccsub3_0_mult_out_rob_0_9,
+ ROB8=>mulaccsub3_0_mult_out_rob_0_8,
+ ROB7=>mulaccsub3_0_mult_out_rob_0_7,
+ ROB6=>mulaccsub3_0_mult_out_rob_0_6,
+ ROB5=>mulaccsub3_0_mult_out_rob_0_5,
+ ROB4=>mulaccsub3_0_mult_out_rob_0_4,
+ ROB3=>mulaccsub3_0_mult_out_rob_0_3,
+ ROB2=>mulaccsub3_0_mult_out_rob_0_2,
+ ROB1=>mulaccsub3_0_mult_out_rob_0_1,
+ ROB0=>mulaccsub3_0_mult_out_rob_0_0,
+ P35=>mulaccsub3_0_mult_out_p_0_35,
+ P34=>mulaccsub3_0_mult_out_p_0_34,
+ P33=>mulaccsub3_0_mult_out_p_0_33,
+ P32=>mulaccsub3_0_mult_out_p_0_32,
+ P31=>mulaccsub3_0_mult_out_p_0_31,
+ P30=>mulaccsub3_0_mult_out_p_0_30,
+ P29=>mulaccsub3_0_mult_out_p_0_29,
+ P28=>mulaccsub3_0_mult_out_p_0_28,
+ P27=>mulaccsub3_0_mult_out_p_0_27,
+ P26=>mulaccsub3_0_mult_out_p_0_26,
+ P25=>mulaccsub3_0_mult_out_p_0_25,
+ P24=>mulaccsub3_0_mult_out_p_0_24,
+ P23=>mulaccsub3_0_mult_out_p_0_23,
+ P22=>mulaccsub3_0_mult_out_p_0_22,
+ P21=>mulaccsub3_0_mult_out_p_0_21,
+ P20=>mulaccsub3_0_mult_out_p_0_20,
+ P19=>mulaccsub3_0_mult_out_p_0_19,
+ P18=>mulaccsub3_0_mult_out_p_0_18,
+ P17=>mulaccsub3_0_mult_out_p_0_17,
+ P16=>mulaccsub3_0_mult_out_p_0_16,
+ P15=>mulaccsub3_0_mult_out_p_0_15,
+ P14=>mulaccsub3_0_mult_out_p_0_14,
+ P13=>mulaccsub3_0_mult_out_p_0_13,
+ P12=>mulaccsub3_0_mult_out_p_0_12,
+ P11=>mulaccsub3_0_mult_out_p_0_11,
+ P10=>mulaccsub3_0_mult_out_p_0_10,
+ P9=>mulaccsub3_0_mult_out_p_0_9,
+ P8=>mulaccsub3_0_mult_out_p_0_8,
+ P7=>mulaccsub3_0_mult_out_p_0_7,
+ P6=>mulaccsub3_0_mult_out_p_0_6,
+ P5=>mulaccsub3_0_mult_out_p_0_5,
+ P4=>mulaccsub3_0_mult_out_p_0_4,
+ P3=>mulaccsub3_0_mult_out_p_0_3,
+ P2=>mulaccsub3_0_mult_out_p_0_2,
+ P1=>mulaccsub3_0_mult_out_p_0_1,
+ P0=>mulaccsub3_0_mult_out_p_0_0,
+ SIGNEDP=>mulaccsub3_0_mult_out_signedp_0);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ dsp_mult_0: MULT18X18C
+ generic map (MULT_BYPASS=> "DISABLED", CAS_MATCH_REG=> "FALSE",
+ RESETMODE=> "SYNC", GSR=> "ENABLED", REG_OUTPUT_RST=> "RST0",
+ REG_OUTPUT_CE=> "CE0", REG_OUTPUT_CLK=> "NONE", REG_PIPELINE_RST=> "RST0",
+ REG_PIPELINE_CE=> "CE0", REG_PIPELINE_CLK=> "NONE",
+ REG_INPUTB_RST=> "RST0", REG_INPUTB_CE=> "CE0", REG_INPUTB_CLK=> "CLK0",
+ REG_INPUTA_RST=> "RST0", REG_INPUTA_CE=> "CE0", REG_INPUTA_CLK=> "CLK0")
+ port map (A17=>A1(8), A16=>A1(7), A15=>A1(6), A14=>A1(5),
+ A13=>A1(4), A12=>A1(3), A11=>A1(2), A10=>A1(1), A9=>A1(0),
+ A8=>scuba_vlo, A7=>scuba_vlo, A6=>scuba_vlo, A5=>scuba_vlo,
+ A4=>scuba_vlo, A3=>scuba_vlo, A2=>scuba_vlo, A1=>scuba_vlo,
+ A0=>scuba_vlo, B17=>B1(15), B16=>B1(14), B15=>B1(13),
+ B14=>B1(12), B13=>B1(11), B12=>B1(10), B11=>B1(9),
+ B10=>B1(8), B9=>B1(7), B8=>B1(6), B7=>B1(5), B6=>B1(4),
+ B5=>B1(3), B4=>B1(2), B3=>B1(1), B2=>B1(0), B1=>scuba_vlo,
+ B0=>scuba_vlo, SIGNEDA=>scuba_vhi, SIGNEDB=>scuba_vlo,
+ SOURCEA=>scuba_vlo, SOURCEB=>scuba_vlo, CE0=>CE0,
+ CE1=>scuba_vhi, CE2=>scuba_vhi, CE3=>scuba_vhi, CLK0=>CLK0,
+ CLK1=>scuba_vlo, CLK2=>scuba_vlo, CLK3=>scuba_vlo,
+ RST0=>RST0, RST1=>scuba_vlo, RST2=>scuba_vlo,
+ RST3=>scuba_vlo, SRIA17=>scuba_vlo, SRIA16=>scuba_vlo,
+ SRIA15=>scuba_vlo, SRIA14=>scuba_vlo, SRIA13=>scuba_vlo,
+ SRIA12=>scuba_vlo, SRIA11=>scuba_vlo, SRIA10=>scuba_vlo,
+ SRIA9=>scuba_vlo, SRIA8=>scuba_vlo, SRIA7=>scuba_vlo,
+ SRIA6=>scuba_vlo, SRIA5=>scuba_vlo, SRIA4=>scuba_vlo,
+ SRIA3=>scuba_vlo, SRIA2=>scuba_vlo, SRIA1=>scuba_vlo,
+ SRIA0=>scuba_vlo, SRIB17=>scuba_vlo, SRIB16=>scuba_vlo,
+ SRIB15=>scuba_vlo, SRIB14=>scuba_vlo, SRIB13=>scuba_vlo,
+ SRIB12=>scuba_vlo, SRIB11=>scuba_vlo, SRIB10=>scuba_vlo,
+ SRIB9=>scuba_vlo, SRIB8=>scuba_vlo, SRIB7=>scuba_vlo,
+ SRIB6=>scuba_vlo, SRIB5=>scuba_vlo, SRIB4=>scuba_vlo,
+ SRIB3=>scuba_vlo, SRIB2=>scuba_vlo, SRIB1=>scuba_vlo,
+ SRIB0=>scuba_vlo, SROA17=>open, SROA16=>open, SROA15=>open,
+ SROA14=>open, SROA13=>open, SROA12=>open, SROA11=>open,
+ SROA10=>open, SROA9=>open, SROA8=>open, SROA7=>open,
+ SROA6=>open, SROA5=>open, SROA4=>open, SROA3=>open,
+ SROA2=>open, SROA1=>open, SROA0=>open, SROB17=>open,
+ SROB16=>open, SROB15=>open, SROB14=>open, SROB13=>open,
+ SROB12=>open, SROB11=>open, SROB10=>open, SROB9=>open,
+ SROB8=>open, SROB7=>open, SROB6=>open, SROB5=>open,
+ SROB4=>open, SROB3=>open, SROB2=>open, SROB1=>open,
+ SROB0=>open, ROA17=>mulaccsub3_0_mult_out_roa_1_17,
+ ROA16=>mulaccsub3_0_mult_out_roa_1_16,
+ ROA15=>mulaccsub3_0_mult_out_roa_1_15,
+ ROA14=>mulaccsub3_0_mult_out_roa_1_14,
+ ROA13=>mulaccsub3_0_mult_out_roa_1_13,
+ ROA12=>mulaccsub3_0_mult_out_roa_1_12,
+ ROA11=>mulaccsub3_0_mult_out_roa_1_11,
+ ROA10=>mulaccsub3_0_mult_out_roa_1_10,
+ ROA9=>mulaccsub3_0_mult_out_roa_1_9,
+ ROA8=>mulaccsub3_0_mult_out_roa_1_8,
+ ROA7=>mulaccsub3_0_mult_out_roa_1_7,
+ ROA6=>mulaccsub3_0_mult_out_roa_1_6,
+ ROA5=>mulaccsub3_0_mult_out_roa_1_5,
+ ROA4=>mulaccsub3_0_mult_out_roa_1_4,
+ ROA3=>mulaccsub3_0_mult_out_roa_1_3,
+ ROA2=>mulaccsub3_0_mult_out_roa_1_2,
+ ROA1=>mulaccsub3_0_mult_out_roa_1_1,
+ ROA0=>mulaccsub3_0_mult_out_roa_1_0,
+ ROB17=>mulaccsub3_0_mult_out_rob_1_17,
+ ROB16=>mulaccsub3_0_mult_out_rob_1_16,
+ ROB15=>mulaccsub3_0_mult_out_rob_1_15,
+ ROB14=>mulaccsub3_0_mult_out_rob_1_14,
+ ROB13=>mulaccsub3_0_mult_out_rob_1_13,
+ ROB12=>mulaccsub3_0_mult_out_rob_1_12,
+ ROB11=>mulaccsub3_0_mult_out_rob_1_11,
+ ROB10=>mulaccsub3_0_mult_out_rob_1_10,
+ ROB9=>mulaccsub3_0_mult_out_rob_1_9,
+ ROB8=>mulaccsub3_0_mult_out_rob_1_8,
+ ROB7=>mulaccsub3_0_mult_out_rob_1_7,
+ ROB6=>mulaccsub3_0_mult_out_rob_1_6,
+ ROB5=>mulaccsub3_0_mult_out_rob_1_5,
+ ROB4=>mulaccsub3_0_mult_out_rob_1_4,
+ ROB3=>mulaccsub3_0_mult_out_rob_1_3,
+ ROB2=>mulaccsub3_0_mult_out_rob_1_2,
+ ROB1=>mulaccsub3_0_mult_out_rob_1_1,
+ ROB0=>mulaccsub3_0_mult_out_rob_1_0,
+ P35=>mulaccsub3_0_mult_out_p_1_35,
+ P34=>mulaccsub3_0_mult_out_p_1_34,
+ P33=>mulaccsub3_0_mult_out_p_1_33,
+ P32=>mulaccsub3_0_mult_out_p_1_32,
+ P31=>mulaccsub3_0_mult_out_p_1_31,
+ P30=>mulaccsub3_0_mult_out_p_1_30,
+ P29=>mulaccsub3_0_mult_out_p_1_29,
+ P28=>mulaccsub3_0_mult_out_p_1_28,
+ P27=>mulaccsub3_0_mult_out_p_1_27,
+ P26=>mulaccsub3_0_mult_out_p_1_26,
+ P25=>mulaccsub3_0_mult_out_p_1_25,
+ P24=>mulaccsub3_0_mult_out_p_1_24,
+ P23=>mulaccsub3_0_mult_out_p_1_23,
+ P22=>mulaccsub3_0_mult_out_p_1_22,
+ P21=>mulaccsub3_0_mult_out_p_1_21,
+ P20=>mulaccsub3_0_mult_out_p_1_20,
+ P19=>mulaccsub3_0_mult_out_p_1_19,
+ P18=>mulaccsub3_0_mult_out_p_1_18,
+ P17=>mulaccsub3_0_mult_out_p_1_17,
+ P16=>mulaccsub3_0_mult_out_p_1_16,
+ P15=>mulaccsub3_0_mult_out_p_1_15,
+ P14=>mulaccsub3_0_mult_out_p_1_14,
+ P13=>mulaccsub3_0_mult_out_p_1_13,
+ P12=>mulaccsub3_0_mult_out_p_1_12,
+ P11=>mulaccsub3_0_mult_out_p_1_11,
+ P10=>mulaccsub3_0_mult_out_p_1_10,
+ P9=>mulaccsub3_0_mult_out_p_1_9,
+ P8=>mulaccsub3_0_mult_out_p_1_8,
+ P7=>mulaccsub3_0_mult_out_p_1_7,
+ P6=>mulaccsub3_0_mult_out_p_1_6,
+ P5=>mulaccsub3_0_mult_out_p_1_5,
+ P4=>mulaccsub3_0_mult_out_p_1_4,
+ P3=>mulaccsub3_0_mult_out_p_1_3,
+ P2=>mulaccsub3_0_mult_out_p_1_2,
+ P1=>mulaccsub3_0_mult_out_p_1_1,
+ P0=>mulaccsub3_0_mult_out_p_1_0,
+ SIGNEDP=>mulaccsub3_0_mult_out_signedp_1);
+
+ ACCUM(40) <= mulaccsub3_alu_output_r_1_0_51;
+ ACCUM(39) <= mulaccsub3_alu_output_r_1_0_50;
+ ACCUM(38) <= mulaccsub3_alu_output_r_1_0_49;
+ ACCUM(37) <= mulaccsub3_alu_output_r_1_0_48;
+ ACCUM(36) <= mulaccsub3_alu_output_r_1_0_47;
+ ACCUM(35) <= mulaccsub3_alu_output_r_1_0_46;
+ ACCUM(34) <= mulaccsub3_alu_output_r_1_0_45;
+ ACCUM(33) <= mulaccsub3_alu_output_r_1_0_44;
+ ACCUM(32) <= mulaccsub3_alu_output_r_1_0_43;
+ ACCUM(31) <= mulaccsub3_alu_output_r_1_0_42;
+ ACCUM(30) <= mulaccsub3_alu_output_r_1_0_41;
+ ACCUM(29) <= mulaccsub3_alu_output_r_1_0_40;
+ ACCUM(28) <= mulaccsub3_alu_output_r_1_0_39;
+ ACCUM(27) <= mulaccsub3_alu_output_r_1_0_38;
+ ACCUM(26) <= mulaccsub3_alu_output_r_1_0_37;
+ ACCUM(25) <= mulaccsub3_alu_output_r_1_0_36;
+ ACCUM(24) <= mulaccsub3_alu_output_r_1_0_35;
+ ACCUM(23) <= mulaccsub3_alu_output_r_1_0_34;
+ ACCUM(22) <= mulaccsub3_alu_output_r_1_0_33;
+ ACCUM(21) <= mulaccsub3_alu_output_r_1_0_32;
+ ACCUM(20) <= mulaccsub3_alu_output_r_1_0_31;
+ ACCUM(19) <= mulaccsub3_alu_output_r_1_0_30;
+ ACCUM(18) <= mulaccsub3_alu_output_r_1_0_29;
+ ACCUM(17) <= mulaccsub3_alu_output_r_1_0_28;
+ ACCUM(16) <= mulaccsub3_alu_output_r_1_0_27;
+ ACCUM(15) <= mulaccsub3_alu_output_r_1_0_26;
+ ACCUM(14) <= mulaccsub3_alu_output_r_1_0_25;
+ ACCUM(13) <= mulaccsub3_alu_output_r_1_0_24;
+ ACCUM(12) <= mulaccsub3_alu_output_r_1_0_23;
+ ACCUM(11) <= mulaccsub3_alu_output_r_1_0_22;
+ ACCUM(10) <= mulaccsub3_alu_output_r_1_0_21;
+ ACCUM(9) <= mulaccsub3_alu_output_r_1_0_20;
+ ACCUM(8) <= mulaccsub3_alu_output_r_1_0_19;
+ ACCUM(7) <= mulaccsub3_alu_output_r_1_0_18;
+ ACCUM(6) <= mulaccsub3_alu_output_r_1_0_17;
+ ACCUM(5) <= mulaccsub3_alu_output_r_1_0_16;
+ ACCUM(4) <= mulaccsub3_alu_output_r_1_0_15;
+ ACCUM(3) <= mulaccsub3_alu_output_r_1_0_14;
+ ACCUM(2) <= mulaccsub3_alu_output_r_1_0_13;
+ ACCUM(1) <= mulaccsub3_alu_output_r_1_0_12;
+ ACCUM(0) <= mulaccsub3_alu_output_r_1_0_11;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of mulaccsub3 is
+ for Structure
+ for all:INV use entity ecp3.INV(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:MULT18X18C use entity ecp3.MULT18X18C(V); end for;
+ for all:ALU54A use entity ecp3.ALU54A(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
jspc29 / trb3.git / commitdiff