RX_SERDES_RST_OUT <= '1';\r
RX_PCS_RST_OUT <= '1';\r
LINK_RX_READY_OUT <= '0';\r
+ WAP_REQ_OUT <= '0';\r
\r
rx_sm <= powerup;\r
STATE_OUT <= x"f";\r
RX_SERDES_RST_OUT <= '0'; -- needed for RX_LOS to be active\r
RX_PCS_RST_OUT <= '1';\r
LINK_RX_READY_OUT <= '0';\r
+ WAP_REQ_OUT <= '0';\r
if( (los_s = '1') ) then -- seems to work\r
cnt <= (others => '0');\r
else\r
RX_SERDES_RST_OUT <= '1';\r
RX_PCS_RST_OUT <= '1';\r
LINK_RX_READY_OUT <= '0';\r
+ WAP_REQ_OUT <= '0';\r
if( cnt(Tshort_bit) = '1' ) then\r
cnt <= (others => '0');\r
rx_sm <= WAIT_CDR_LOCK;\r
RX_SERDES_RST_OUT <= '0';\r
RX_PCS_RST_OUT <= '1';\r
LINK_RX_READY_OUT <= '0';\r
+ WAP_REQ_OUT <= '0';\r
if( cnt(Tcdr_bit) = '1' ) then\r
cnt <= (others => '0');\r
rx_sm <= TEST_CDR;\r
RX_SERDES_RST_OUT <= '0';\r
RX_PCS_RST_OUT <= '1';\r
LINK_RX_READY_OUT <= '0';\r
+ WAP_REQ_OUT <= '0';\r
if ( los_s = '1' ) then\r
rx_sm <= POWERUP; \r
cnt <= (others => '0');\r
RX_SERDES_RST_OUT <= '0';\r
RX_PCS_RST_OUT <= '1';\r
LINK_RX_READY_OUT <= '0';\r
+ WAP_REQ_OUT <= '0';\r
if ( los_s = '1' ) then\r
rx_sm <= POWERUP; \r
cnt <= (others => '0');\r
RX_SERDES_RST_OUT <= '0';\r
RX_PCS_RST_OUT <= '0';\r
LINK_RX_READY_OUT <= '0';\r
+ WAP_REQ_OUT <= '0';\r
if ( los_s = '1' ) then\r
rx_sm <= POWERUP; \r
cnt <= (others => '0');\r
RX_SERDES_RST_OUT <= '0';\r
RX_PCS_RST_OUT <= '0';\r
LINK_RX_READY_OUT <= '0';\r
+ WAP_REQ_OUT <= '1';\r
if ( los_s = '1' ) then\r
rx_sm <= POWERUP; \r
cnt <= (others => '0');\r
RX_SERDES_RST_OUT <= '0';\r
RX_PCS_RST_OUT <= '0';\r
LINK_RX_READY_OUT <= '0';\r
+ WAP_REQ_OUT <= '0';\r
cnt <= (others => '0');\r
if ( los_s = '1' ) then\r
rx_sm <= POWERUP; \r
RX_SERDES_RST_OUT <= '0';\r
RX_PCS_RST_OUT <= '0';\r
LINK_RX_READY_OUT <= '1';\r
+ WAP_REQ_OUT <= '0';\r
cnt <= (others => '0');\r
if ( los_s = '1' ) then\r
rx_sm <= POWERUP; \r
RX_SERDES_RST_OUT <= '0';\r
RX_PCS_RST_OUT <= '0';\r
LINK_RX_READY_OUT <= '0';\r
+ WAP_REQ_OUT <= '0';\r
rx_sm <= POWERUP;\r
cnt <= (others => '0');\r
\r
\r
end if;\r
end process rx_reset_proc;\r
-\r
- WAP_REQ_OUT <= '1' when ((rx_sm = TEST_RXPCS)) else '0';\r
\r
end architecture;\r
signal debug_tx_control_i : std_logic_vector(31 downto 0);
signal debug_rx_control_i : std_logic_vector(31 downto 0);
- signal link_full_done_qsys : std_logic;
- signal link_half_done_qsys : std_logic;
signal link_rx_ready_qsys : std_logic;
signal link_tx_ready_qsys : std_logic;
signal link_status : std_logic_vector(3 downto 0);
signal link_rx_null_i : std_logic;
signal link_rx_null_qref : std_logic;
+ -----
+ signal link_ready_i : std_logic;
+ signal link_ready_q : std_logic_vector(1 downto 0);
+ signal link_alive_i : std_logic;
+ signal link_alive_q : std_logic;
+ signal link_dead_i : std_logic;
+ signal link_dead_q : std_logic;
+
begin
-------------------------------------------------
-- TX_CONTROL and RX_CONTROL reset
reset_i <= RESET;
-
+
-- for syncing later
- link_tx_ready_i <= LINK_TX_READY_IN; -- usually CLK_REF based
+ link_tx_ready_i <= LINK_TX_READY_IN;
+----------------------------------------------------------------------------------------------
+-- "Link prepared" for action, used to reset certain part on
+-- link going active / inactive.
+-- Both signals are CLK_REF based.
+ link_ready_i <= link_rx_ready_i and link_tx_ready_i;
+
+ THE_REF_SHIFT_PROC: process( CLK_REF )
+ begin
+ if( rising_edge(CLK_REF) ) then
+ link_ready_q <= link_ready_q(0) & link_ready_i;
+ link_alive_q <= link_alive_i;
+ link_dead_q <= link_dead_i;
+ end if;
+ end process THE_REF_SHIFT_PROC;
+
+ link_alive_i <= link_ready_q(0) and not link_ready_q(1);
+ link_dead_i <= not link_ready_q(0) and link_ready_q(1);
+----------------------------------------------------------------------------------------------
+
-------------------------------------------------
-- Reset RX FSM
-------------------------------------------------
THE_MAIN_RX_RST: main_rx_reset_RS
port map(
- CLEAR => CLEAR, --'0', -- DO NOT USE
+ CLEAR => CLEAR, -- use GSR here
CLK_REF => CLK_REF,
CDR_LOL_IN => RX_CDR_LOL_IN,
CV_IN => RX_CV_IN,
port map(
CLK_RXI => CLK_RXI,
CLK_SYS => CLK_SYS,
- RESET => CLEAR, --'0', -- DO NOT USE
+ RESET => CLEAR, -- use GSR here
--
RX_DATA_OUT => media_med2int_i.data,
RX_PACKET_NUMBER_OUT => media_med2int_i.packet_num,
RX_RST_OUT => RX_RST_OUT,
RX_RST_WORD_OUT => RX_RST_WORD_OUT,
--
- LINK_RX_READY_IN => link_rx_ready_i, -- internally synced to CLK_RXI
- LINK_HALF_DONE_OUT => link_half_done_i, -- CLK_RXI based
- LINK_FULL_DONE_OUT => link_full_done_i, -- CLK_RXI based
+ LINK_TX_READY_IN => LINK_TX_READY_IN,
+ LINK_RX_READY_IN => link_rx_ready_i,
+ LINK_ACTIVE_OUT => link_active_i, -- CLK_RXI based
LINK_RX_NULL_OUT => link_rx_null_i, -- CLK_RXI based
--
DEBUG_OUT => debug_rx_control_i,
port map(
CLK_TXI => CLK_TXI,
CLK_SYS => CLK_SYS,
- CLEAR => CLEAR, --'0', -- DO NOT USE
+ CLEAR => CLEAR, -- use GSR here
-- Media Interface
TX_DATA_IN => MEDIA_INT2MED.data,
TX_PACKET_NUMBER_IN => MEDIA_INT2MED.packet_num,
SEND_RST_IN => TX_RST_IN,
SEND_RST_WORD_IN => TX_RST_WORD_IN,
-- link status signals, internally synced
- LINK_TX_READY_IN => link_tx_ready_i, -- internally synced to CLK_TXI
- LINK_RX_READY_IN => link_rx_ready_i, -- internally synced to CLK_TXI
- LINK_HALF_DONE_IN => link_half_done_i, -- internally synced to CLK_TXI
- LINK_FULL_DONE_IN => link_full_done_i, -- internally synced to CLK_TXI
+ LINK_TX_READY_IN => link_tx_ready_i,
+ LINK_ACTIVE_IN => link_active_i,
LINK_TX_NULL_IN => LINK_TX_NULL_IN,
-- debug
DEBUG_OUT => debug_tx_control_i,
-------------------------------------------------
-- Generate LED signals
-------------------------------------------------
- led_ok <= link_full_done_i when rising_edge(CLK_SYS);
+ led_ok <= link_active_i when rising_edge(CLK_SYS);
led_rx <= (media_med2int_i.dataready or led_rx) and not timer(20) when rising_edge(CLK_SYS);
led_tx <= (MEDIA_INT2MED.dataready or led_tx or SFP_LOS_IN) and not timer(20) when rising_edge(CLK_SYS);
media_med2int_i.stat_op(10) <= led_rx or last_led_rx; -- "LED RX"
media_med2int_i.stat_op(9) <= led_ok; -- "LED status"
media_med2int_i.stat_op(8 downto 6) <= (others => '0');
- media_med2int_i.stat_op(5) <= link_full_done_qsys; -- tx_allow
- media_med2int_i.stat_op(4) <= link_full_done_qsys; -- rx_allow
+ media_med2int_i.stat_op(5) <= link_active_qsys; -- tx_allow
+ media_med2int_i.stat_op(4) <= link_active_qsys; -- rx_allow
media_med2int_i.stat_op(3 downto 0) <= link_status_qsys;
- link_active_i <= link_rx_ready_i and link_tx_ready_i and link_half_done_i and link_full_done_i;
-
link_status <= x"0" when (link_active_i = '1' ) else x"7";
SYNC_MEDIA_SIGS : entity work.signal_sync
generic map(
- WIDTH => 9,
+ WIDTH => 7,
DEPTH => 3
)
port map(
RESET => '0',
CLK0 => CLK_SYS,
CLK1 => CLK_SYS,
- D_IN(8) => link_active_i,
- D_IN(7) => link_full_done_i,
- D_IN(6) => link_half_done_i,
+ D_IN(6) => link_active_i,
D_IN(5) => link_tx_ready_i,
D_IN(4) => link_rx_ready_i,
D_IN(3 downto 0) => link_status,
- D_OUT(8) => link_active_qsys,
- D_OUT(7) => link_full_done_qsys,
- D_OUT(6) => link_half_done_qsys,
+ D_OUT(6) => link_active_qsys,
D_OUT(5) => link_tx_ready_qsys,
D_OUT(4) => link_rx_ready_qsys,
D_OUT(3 downto 0) => link_status_qsys
DEBUG_OUT(31 downto 8) <= (others => '0');
-- these signals will be used outside!
DEBUG_OUT(7 downto 4) <= (others => '0');
- DEBUG_OUT(3) <= link_full_done_qsys;
- DEBUG_OUT(2) <= link_half_done_qsys;
+ DEBUG_OUT(3) <= '0';
+ DEBUG_OUT(2) <= link_active_qsys;
DEBUG_OUT(1) <= link_rx_ready_qsys;
DEBUG_OUT(0) <= link_tx_ready_qsys;
-
--- Some remarks on the SerDes issue:
--- - slave ports keep everything in global reset until SFP detects light on receiver (SFP_LOS = 0)
--- - master ports take the slave port global reset, if available, otherwise GSR is used
--- - the global reset connects to RST_QD_C to keep TX PLL in reset
--- - slave ports establish the uplink first, with all checks for link integrity and WAP_ZERO_IN
--- -
-
end architecture;
RX_RST_OUT : out std_logic;\r
RX_RST_WORD_OUT : out std_logic_vector(7 downto 0);\r
-- link status signals\r
+ LINK_TX_READY_IN : in std_logic;\r
LINK_RX_READY_IN : in std_logic;\r
- LINK_HALF_DONE_OUT : out std_logic;\r
- LINK_FULL_DONE_OUT : out std_logic;\r
+ LINK_ACTIVE_OUT : out std_logic;\r
LINK_RX_NULL_OUT : out std_logic;\r
-- debug\r
DEBUG_OUT : out std_logic_vector(31 downto 0);\r
CLK_SYS : in std_logic;\r
CLEAR : in std_logic;\r
-- Media Interface\r
- TX_DATA_IN : in std_logic_vector(15 downto 0); -- media interface\r
- TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); -- media interface\r
- TX_WRITE_IN : in std_logic; -- media interface\r
- TX_READ_OUT : out std_logic; -- media interface\r
+ TX_DATA_IN : in std_logic_vector(15 downto 0);\r
+ TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0);\r
+ TX_WRITE_IN : in std_logic;\r
+ TX_READ_OUT : out std_logic;\r
-- SerDes data stream\r
- TX_DATA_OUT : out std_logic_vector(7 downto 0); -- to TX SerDes\r
- TX_K_OUT : out std_logic; -- to TX SerDes\r
+ TX_DATA_OUT : out std_logic_vector(7 downto 0);\r
+ TX_K_OUT : out std_logic;\r
-- synchronous signals\r
- WORD_SYNC_IN : in std_logic; -- byte/word sync\r
+ WORD_SYNC_IN : in std_logic;\r
WORD_SYNC_OUT : out std_logic;\r
SEND_DLM_IN : in std_logic;\r
SEND_DLM_WORD_IN : in std_logic_vector(7 downto 0);\r
SEND_RST_IN : in std_logic;\r
SEND_RST_WORD_IN : in std_logic_vector(7 downto 0);\r
-- link status signals, internally synced\r
- LINK_TX_READY_IN : in std_logic; -- local ref clock\r
- LINK_RX_READY_IN : in std_logic; -- local ref clock\r
- LINK_HALF_DONE_IN : in std_logic; -- recovered RX clock\r
- LINK_FULL_DONE_IN : in std_logic; -- recovered RX clock\r
+ LINK_TX_READY_IN : in std_logic;\r
+ LINK_ACTIVE_IN : in std_logic;\r
LINK_TX_NULL_IN : in std_logic;\r
-- debug\r
DEBUG_OUT : out std_logic_vector(31 downto 0);\r
RX_RST_OUT : out std_logic;\r
RX_RST_WORD_OUT : out std_logic_vector(7 downto 0);\r
-- link status signals\r
- LINK_RX_READY_IN : in std_logic; -- used for synchronous reset\r
- LINK_HALF_DONE_OUT : out std_logic;\r
- LINK_FULL_DONE_OUT : out std_logic;\r
+ LINK_TX_READY_IN : in std_logic;\r
+ LINK_RX_READY_IN : in std_logic;\r
+ LINK_ACTIVE_OUT : out std_logic;\r
LINK_RX_NULL_OUT : out std_logic; -- link received K_NULL\r
-- debug\r
DEBUG_OUT : out std_logic_vector(31 downto 0);\r
signal sync_k_i : std_logic; -- denotes a K_IDLE detected\r
\r
signal link_rx_ready_qrx : std_logic;\r
- signal link_full_done_qrx : std_logic;\r
- signal link_full_done_qsys : std_logic;\r
+ signal link_tx_ready_qrx : std_logic;\r
\r
signal ce_idle0_ctr : std_logic;\r
signal rst_idle0_ctr : std_logic;\r
- signal ctr_idle0 : unsigned(4 downto 0);\r
- signal idle0_detected : std_logic; -- link_half_done\r
- signal ce_idle1_ctr : std_logic;\r
- signal rst_idle1_ctr : std_logic;\r
- signal ctr_idle1 : unsigned(4 downto 0);\r
- signal idle1_detected : std_logic; -- link_full_done\r
- signal rst_link_state : std_logic;\r
+ signal ctr_idle0 : unsigned(8 downto 0);\r
+ signal idle0_detected : std_logic;\r
+\r
+ signal link_active_i : std_logic;\r
+ signal link_active_qrx : std_logic;\r
+ signal link_active_qsys : std_logic;\r
\r
-- attribute syn_hier : string;\r
-- attribute syn_hier of rx_control_arch : architecture is "hard";\r
\r
begin\r
\r
- -- Syncing things\r
+ -- Syncing things (CLK_RXI)\r
SYNC_RXI: signal_sync \r
generic map( \r
- WIDTH => 1,\r
+ WIDTH => 3,\r
DEPTH => 3\r
)\r
port map(\r
CLK0 => CLK_RXI, \r
CLK1 => CLK_RXI,\r
D_IN(0) => LINK_RX_READY_IN,\r
- D_OUT(0) => link_rx_ready_qrx\r
+ D_IN(1) => LINK_TX_READY_IN,\r
+ D_IN(2) => link_active_i,\r
+ D_OUT(0) => link_rx_ready_qrx,\r
+ D_OUT(1) => link_tx_ready_qrx,\r
+ D_OUT(2) => link_active_qrx\r
);\r
\r
- -- Syncing things\r
+ -- Syncing things (CLK_SYS)\r
SYNC_SYS: signal_sync \r
generic map( \r
WIDTH => 1,\r
RESET => '0',\r
CLK0 => CLK_SYS, \r
CLK1 => CLK_SYS,\r
- D_IN(0) => idle1_detected,\r
- D_OUT(0) => link_full_done_qsys\r
+ D_IN(0) => link_active_i,\r
+ D_OUT(0) => link_active_qsys\r
);\r
\r
----------------------------------------------------------------------\r
\r
process begin\r
wait until rising_edge(CLK_SYS);\r
- if ( link_full_done_qsys = '0' ) then\r
+ if ( link_active_qsys = '0' ) then\r
rx_packet_num <= "100";\r
elsif( buf_rx_write_out = '1' ) then\r
if rx_packet_num = "100" then\r
\r
ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty;\r
\r
- ct_fifo_reset <= not idle1_detected;\r
+ ct_fifo_reset <= not link_active_qrx;\r
\r
----------------------------------------------------------------------\r
-- Read incoming data\r
rx_rst_i <= '0';\r
sync_k_i <= '0';\r
ce_idle0_ctr <= '0';\r
- ce_idle1_ctr <= '0';\r
rst_idle0_ctr <= '0';\r
- rst_idle1_ctr <= '0';\r
- rst_link_state <= '0';\r
\r
case rx_state is\r
when SLEEP =>\r
rx_state_bits <= x"1";\r
rx_data(7 downto 0) <= reg_rx_data_in;\r
rst_idle0_ctr <= '1';\r
- rst_idle1_ctr <= '1';\r
- rst_link_state <= '1';\r
--- if( (reg_rx_k_in = '1') and (reg_rx_data_in = K_IDLE) ) then\r
if( (reg_rx_k_in = '1') and (reg_rx_data_in = K_IDLE) and (link_rx_ready_qrx = '1') ) then\r
rx_state <= WAIT_1;\r
sync_k_i <= '1';\r
next_sop <= '1';\r
case reg_rx_data_in is\r
when D_IDLE0 =>\r
- -- first link establishment phase\r
ce_idle0_ctr <= '1';\r
- rst_idle1_ctr <= '1';\r
- when D_IDLE1 =>\r
- -- second link establishment phase\r
- ce_idle1_ctr <= '1';\r
- rst_idle0_ctr <= '1';\r
when others =>\r
- -- all other cases\r
- rst_idle0_ctr <= '1';\r
- rst_idle1_ctr <= '1';\r
+ rst_idle0_ctr <= '1'; -- DANGEROUS, inhibits usage of other idles\r
end case;\r
\r
when GET_DATA =>\r
end case;\r
\r
-- BUG: master ports don't reset correctly\r
+ -- might need some MASTER/SLAVE stuff\r
if( (RESET = '1') or (link_rx_ready_qrx = '0') ) then\r
rx_state <= SLEEP;\r
rx_dlm_word_i <= x"00";\r
if( rising_edge(CLK_RXI) ) then\r
if ( rst_idle0_ctr = '1' ) then\r
ctr_idle0 <= (others => '0');\r
- elsif( ce_idle0_ctr = '1' ) then\r
+ elsif( (ce_idle0_ctr = '1') and (idle0_detected = '0') ) then\r
ctr_idle0 <= ctr_idle0 + 1 ;\r
end if;\r
end if;\r
end process THE_CTR_IDLE0_PROC;\r
\r
- THE_CTR_IDLE1_PROC: process( CLK_RXI ) \r
- begin\r
- if( rising_edge(CLK_RXI) ) then\r
- if ( rst_idle1_ctr = '1' ) then\r
- ctr_idle1 <= (others => '0');\r
- elsif( ce_idle1_ctr = '1' ) then\r
- ctr_idle1 <= ctr_idle1 + 1 ;\r
- end if;\r
- end if;\r
- end process THE_CTR_IDLE1_PROC;\r
+ idle0_detected <= ctr_idle0(ctr_idle0'left);\r
+\r
+ link_active_i <= link_rx_ready_qrx and link_tx_ready_qrx and idle0_detected;\r
\r
--- IDLE detection for link establishment\r
- THE_IDLE0_DETECTED_PROC: process( CLK_RXI )\r
- begin\r
- if( rising_edge(CLK_RXI) ) then\r
- if ( rst_link_state = '1' ) then\r
- idle0_detected <= '0';\r
- elsif ( (ctr_idle0(ctr_idle0'left) = '1') and (ce_idle0_ctr = '1') ) then\r
- idle0_detected <= '1';\r
- end if;\r
- end if;\r
- end process THE_IDLE0_DETECTED_PROC;\r
- \r
- THE_IDLE1_DETECTED_PROC: process( CLK_RXI )\r
- begin\r
- if( rising_edge(CLK_RXI) ) then\r
- if ( rst_link_state = '1' ) then\r
- idle1_detected <= '0';\r
- elsif ( (ctr_idle1(ctr_idle1'left) = '1') and (ce_idle1_ctr = '1') ) then\r
- idle1_detected <= '1';\r
- end if;\r
- end if;\r
- end process THE_IDLE1_DETECTED_PROC;\r
- \r
----------------------------------------------------------------------\r
-- Signals out\r
---------------------------------------------------------------------- \r
RX_DLM_WORD_OUT <= rx_dlm_word_i when rising_edge(CLK_RXI);\r
RX_RST_OUT <= rx_rst_i when rising_edge(CLK_RXI);\r
RX_RST_WORD_OUT <= rx_rst_word_i when rising_edge(CLK_RXI);\r
-\r
- LINK_HALF_DONE_OUT <= idle0_detected;\r
- LINK_FULL_DONE_OUT <= idle1_detected;\r
- LINK_RX_NULL_OUT <= rst_link_state;\r
+ \r
+ LINK_ACTIVE_OUT <= link_active_qrx;\r
\r
----------------------------------------------------------------------\r
-- Debug and Status\r
\r
library work;\r
use work.trb_net_std.all;\r
---use work.trb_net_components.all;\r
use work.med_sync_define_RS.all;\r
\r
--- BUG: must be kept in reset while LINK_TX_READY_IN = '0' !\r
-\r
entity tx_control_RS is\r
generic(\r
IS_MODE : integer := c_IS_UNUSED\r
SEND_RST_WORD_IN : in std_logic_vector(7 downto 0);\r
-- link status signals, internally synced\r
LINK_TX_READY_IN : in std_logic; -- local ref clock\r
- LINK_RX_READY_IN : in std_logic; -- local ref clock\r
- LINK_HALF_DONE_IN : in std_logic; -- recovered RX clock\r
- LINK_FULL_DONE_IN : in std_logic; -- recovered RX clock\r
+ LINK_ACTIVE_IN : in std_logic; -- recovered RX clock\r
LINK_TX_NULL_IN : in std_logic;\r
-- debug\r
DEBUG_OUT : out std_logic_vector(31 downto 0);\r
signal save_eop : std_logic;\r
signal load_sop : std_logic;\r
signal load_eop : std_logic;\r
- signal send_steady_idle_int : std_logic;\r
signal word_sync_i : std_logic;\r
\r
signal link_tx_ready_qtx : std_logic;\r
- signal link_rx_ready_qtx : std_logic;\r
- signal link_half_done_qtx : std_logic;\r
- signal link_full_done_qtx : std_logic;\r
- signal link_active_int : std_logic;\r
signal link_active_qtx : std_logic;\r
signal link_active_qsys : std_logic;\r
signal link_tx_null_qtx : std_logic;\r
-- Sync\r
SYNC_STATUS_SIGS : entity work.signal_sync \r
generic map( \r
- WIDTH => 5,\r
+ WIDTH => 3,\r
DEPTH => 3\r
)\r
port map(\r
CLK0 => CLK_TXI, \r
CLK1 => CLK_TXI,\r
D_IN(0) => LINK_TX_READY_IN,\r
- D_IN(1) => LINK_RX_READY_IN,\r
- D_IN(2) => LINK_HALF_DONE_IN,\r
- D_IN(3) => LINK_FULL_DONE_IN,\r
- D_IN(4) => LINK_TX_NULL_IN,\r
+ D_IN(1) => LINK_ACTIVE_IN,\r
+ D_IN(2) => LINK_TX_NULL_IN,\r
D_OUT(0) => link_tx_ready_qtx,\r
- D_OUT(1) => link_rx_ready_qtx,\r
- D_OUT(2) => link_half_done_qtx,\r
- D_OUT(3) => link_full_done_qtx,\r
- D_OUT(4) => link_tx_null_qtx \r
+ D_OUT(1) => link_active_qtx,\r
+ D_OUT(2) => link_tx_null_qtx \r
);\r
\r
- -- Payload is only allowed on fully active links\r
- link_active_int <= link_tx_ready_qtx and link_rx_ready_qtx and \r
- link_half_done_qtx and link_full_done_qtx;\r
-\r
- link_active_qtx <= link_active_int when rising_edge(CLK_TXI);\r
-\r
- -- if set send IDLE1, else IDLE0\r
- send_steady_idle_int <= link_tx_ready_qtx and link_rx_ready_qtx and \r
- link_half_done_qtx when (IS_MODE = c_IS_MASTER) else\r
- link_tx_ready_qtx and link_rx_ready_qtx and\r
- link_half_done_qtx and link_full_done_qtx when (IS_MODE = c_IS_SLAVE) else\r
- '0';\r
-\r
SYNC_SYSCLK : entity work.signal_sync \r
generic map( \r
WIDTH => 1,\r
RESET => '0',\r
CLK0 => CLK_SYS, \r
CLK1 => CLK_SYS,\r
- D_IN(0) => link_active_int,\r
+ D_IN(0) => LINK_ACTIVE_IN,\r
D_OUT(0) => link_active_qsys\r
);\r
\r
end if;\r
end process;\r
\r
- ct_fifo_reset <= not link_active_qtx;\r
+ ct_fifo_reset <= not link_active_qtx; -- correct clock domain?\r
TX_READ_OUT <= buf_tx_read_out;\r
\r
ct_fifo_write <= buf_tx_read_out and TX_WRITE_IN;\r
\r
when SEND_IDLE_H =>\r
word_sync_i <= '1';\r
- if( send_steady_idle_int = '1' ) then\r
- tx_data_i <= D_IDLE1;\r
- else\r
- tx_data_i <= D_IDLE0;\r
- end if;\r
+ tx_data_i <= D_IDLE0;\r
\r
when SEND_DATA_L =>\r
tx_data_i <= ram_dout(7 downto 0);\r
DEBUG_OUT(31) <= debug_sending_dlm when rising_edge(CLK_TXI);\r
DEBUG_OUT(30) <= send_dlm_i;\r
DEBUG_OUT(29) <= debug_sending_rst when rising_edge(CLK_TXI);\r
- DEBUG_OUT(28 downto 6) <= (others => '0');\r
- DEBUG_OUT(5) <= send_steady_idle_int when rising_edge(CLK_TXI);\r
- DEBUG_OUT(4) <= '0'; --toggle_idle when rising_edge(CLK_TXI);\r
+ DEBUG_OUT(28 downto 4) <= (others => '0');\r
DEBUG_OUT(3 downto 0) <= state_bits when rising_edge(CLK_TXI);\r
\r
THE_STAT_PROC: process( CLK_SYS )\r
jspc29 / trbnet.git / commitdiff