update 32 Pin AddOn project

diff --git a/32PinAddOn/config.vhd b/32PinAddOn/config.vhd
index 84f668e442eceff21a995b30ba2833cb3e31e2e3..e671bf3830cd18b0c99e10395b4cc058c390229f 100644 (file)
--- a/32PinAddOn/config.vhd
+++ b/32PinAddOn/config.vhd
@@ -10,6 +10,7 @@ package config is
 ------------------------------------------------------------------------------
 
 --TDC settings
+  constant FPGA_TYPE               : integer  := 3;  --3: ECP3, 5: ECP5
   constant NUM_TDC_MODULES         : integer range 1 to 4  := 1;  -- number of tdc modules to implement
   constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 5; -- number of tdc channels per module
   constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 6;  --the nearest power of two, for convenience reasons

diff --git a/32PinAddOn/trb3_periph_32PinAddOn.prj b/32PinAddOn/trb3_periph_32PinAddOn.prj
index 0fe9caec2f4360bbeeea662c97c3b555453d4fa6..46ac233b7d427b59bf0e0e7478a0fee89cee34f6 100644 (file)
--- a/32PinAddOn/trb3_periph_32PinAddOn.prj
+++ b/32PinAddOn/trb3_periph_32PinAddOn.prj
@@ -169,10 +169,12 @@ add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
 add_file -vhdl -lib work "tdc_release/Channel.vhd"
 add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
 add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
+add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd"
 add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
 add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
 add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
 add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
+add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd"
 add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd"
 add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
 add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"