*** empty log message ***

diff --git a/gbe2_ecp3/tb_gbe_buf.vhd b/gbe2_ecp3/tb_gbe_buf.vhd
index 772ff46959bf88ccf41d471123845b92e1dd7276..fb1a3319bd5f53fd1c313a7dfed05cd75ccfc759 100755 (executable)
--- a/gbe2_ecp3/tb_gbe_buf.vhd
+++ b/gbe2_ecp3/tb_gbe_buf.vhd
@@ -13,75 +13,96 @@ ARCHITECTURE behavior OF testbench IS
                USE_125MHZ_EXTCLK       : integer range 0 to 1 := 1
        );
        port(
-                       CLK                                                     : in    std_logic;
+       CLK                                                     : in    std_logic;
        TEST_CLK                                        : in    std_logic; -- only for simulation!
        CLK_125_IN                              : in std_logic;  -- gk 28.04.01 used only in internal 125MHz clock mode
-RESET : IN std_logic;
-               GSR_N : IN std_logic;
-               STAGE_CTRL_REGS_IN : IN std_logic_vector(31 downto 0);
-               ------------------------
-               IP_CFG_START_IN : IN std_logic;
-               IP_CFG_BANK_SEL_IN : IN std_logic_vector(3 downto 0);
-               IP_CFG_MEM_DATA_IN : IN std_logic_vector(31 downto 0);
-               MR_RESET_IN : IN std_logic;
-               MR_MODE_IN : IN std_logic;
-               MR_RESTART_IN : IN std_logic;
-               IP_CFG_MEM_CLK_OUT : OUT std_logic;
-               IP_CFG_DONE_OUT : OUT std_logic;
-               IP_CFG_MEM_ADDR_OUT : OUT std_logic_vector(7 downto 0);
-               -- gk 29.03.10
-               SLV_ADDR_IN                  : in std_logic_vector(7 downto 0);
-               SLV_READ_IN                  : in std_logic;
-               SLV_WRITE_IN                 : in std_logic;
-               SLV_BUSY_OUT                 : out std_logic;
-               SLV_ACK_OUT                  : out std_logic;
-               SLV_DATA_IN                  : in std_logic_vector(31 downto 0);
-               SLV_DATA_OUT                 : out std_logic_vector(31 downto 0);
-               -- gk 26.04.10
-               -- registers setup interface
-               BUS_ADDR_IN               : in std_logic_vector(7 downto 0);
-               BUS_DATA_IN               : in std_logic_vector(31 downto 0);
-               BUS_DATA_OUT              : out std_logic_vector(31 downto 0);  -- gk 26.04.10
-               BUS_WRITE_EN_IN           : in std_logic;  -- gk 26.04.10
-               BUS_READ_EN_IN            : in std_logic;  -- gk 26.04.10
-               BUS_ACK_OUT               : out std_logic;  -- gk 26.04.10
-               -- gk 23.04.10
-               LED_PACKET_SENT_OUT        : out std_logic;
-               LED_AN_DONE_N_OUT            : out std_logic;
-               ------------------------
-               CTS_NUMBER_IN : IN std_logic_vector(15 downto 0);
-               CTS_CODE_IN : IN std_logic_vector(7 downto 0);
-               CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0);
-               CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0);
-               CTS_START_READOUT_IN : IN std_logic;
-               CTS_READ_IN : IN std_logic;
-               FEE_DATA_IN : IN std_logic_vector(15 downto 0);
-               FEE_DATAREADY_IN : IN std_logic;
-               FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0);
-               FEE_BUSY_IN : IN std_logic;
-               SFP_RXD_P_IN : IN std_logic;
-               SFP_RXD_N_IN : IN std_logic;
-               SFP_REFCLK_P_IN : IN std_logic;
-               SFP_REFCLK_N_IN : IN std_logic;
-               SFP_PRSNT_N_IN : IN std_logic;
-               SFP_LOS_IN : IN std_logic;          
-               STAGE_STAT_REGS_OUT : OUT std_logic_vector(31 downto 0);
-               CTS_DATA_OUT : OUT std_logic_vector(31 downto 0);
-               CTS_DATAREADY_OUT : OUT std_logic;
-               CTS_READOUT_FINISHED_OUT : OUT std_logic;
-               CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0);
-               CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);
-               FEE_READ_OUT : OUT std_logic;
-               SFP_TXD_P_OUT : OUT std_logic;
-               SFP_TXD_N_OUT : OUT std_logic;
-               SFP_TXDIS_OUT : OUT std_logic;
-                       -- for simulation of receiving part only
+       RESET                                           : in    std_logic;
+       GSR_N                                           : in    std_logic;
+       -- Debug
+       STAGE_STAT_REGS_OUT                     : out   std_logic_vector(31 downto 0);
+       STAGE_CTRL_REGS_IN                      : in    std_logic_vector(31 downto 0);
+       -- configuration interface
+       IP_CFG_START_IN                         : in    std_logic;
+       IP_CFG_BANK_SEL_IN                      : in    std_logic_vector(3 downto 0);
+       IP_CFG_DONE_OUT                         : out   std_logic;
+       IP_CFG_MEM_ADDR_OUT                     : out   std_logic_vector(7 downto 0);
+       IP_CFG_MEM_DATA_IN                      : in    std_logic_vector(31 downto 0);
+       IP_CFG_MEM_CLK_OUT                      : out   std_logic;
+       MR_RESET_IN                                     : in    std_logic;
+       MR_MODE_IN                                      : in    std_logic;
+       MR_RESTART_IN                           : in    std_logic;
+       -- gk 29.03.10
+       SLV_ADDR_IN                  : in std_logic_vector(7 downto 0);
+       SLV_READ_IN                  : in std_logic;
+       SLV_WRITE_IN                 : in std_logic;
+       SLV_BUSY_OUT                 : out std_logic;
+       SLV_ACK_OUT                  : out std_logic;
+       SLV_DATA_IN                  : in std_logic_vector(31 downto 0);
+       SLV_DATA_OUT                 : out std_logic_vector(31 downto 0);
+       -- gk 22.04.10
+       -- registers setup interface
+       BUS_ADDR_IN               : in std_logic_vector(7 downto 0);
+       BUS_DATA_IN               : in std_logic_vector(31 downto 0);
+       BUS_DATA_OUT              : out std_logic_vector(31 downto 0);  -- gk 26.04.10
+       BUS_WRITE_EN_IN           : in std_logic;  -- gk 26.04.10
+       BUS_READ_EN_IN            : in std_logic;  -- gk 26.04.10
+       BUS_ACK_OUT               : out std_logic;  -- gk 26.04.10
+       -- gk 23.04.10
+       LED_PACKET_SENT_OUT          : out std_logic;
+       LED_AN_DONE_N_OUT            : out std_logic;
+       -- CTS interface
+       CTS_NUMBER_IN                           : in    std_logic_vector (15 downto 0);
+       CTS_CODE_IN                                     : in    std_logic_vector (7  downto 0);
+       CTS_INFORMATION_IN                      : in    std_logic_vector (7  downto 0);
+       CTS_READOUT_TYPE_IN                     : in    std_logic_vector (3  downto 0);
+       CTS_START_READOUT_IN            : in    std_logic;
+       CTS_DATA_OUT                            : out   std_logic_vector (31 downto 0);
+       CTS_DATAREADY_OUT                       : out   std_logic;
+       CTS_READOUT_FINISHED_OUT        : out   std_logic;
+       CTS_READ_IN                                     : in    std_logic;
+       CTS_LENGTH_OUT                          : out   std_logic_vector (15 downto 0);
+       CTS_ERROR_PATTERN_OUT           : out   std_logic_vector (31 downto 0);
+       -- Data payload interface
+       FEE_DATA_IN                                     : in    std_logic_vector (15 downto 0);
+       FEE_DATAREADY_IN                        : in    std_logic;
+       FEE_READ_OUT                            : out   std_logic;
+       FEE_STATUS_BITS_IN                      : in    std_logic_vector (31 downto 0);
+       FEE_BUSY_IN                                     : in    std_logic;
+       --SFP Connection
+       SFP_RXD_P_IN                            : in    std_logic;
+       SFP_RXD_N_IN                            : in    std_logic;
+       SFP_TXD_P_OUT                           : out   std_logic;
+       SFP_TXD_N_OUT                           : out   std_logic;
+       SFP_REFCLK_P_IN                         : in    std_logic;
+       SFP_REFCLK_N_IN                         : in    std_logic;
+       SFP_PRSNT_N_IN                          : in    std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+       SFP_LOS_IN                                      : in    std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+       SFP_TXDIS_OUT                           : out   std_logic; -- SFP disable
+       
+       -- interface between main_controller and hub logic
+       MC_UNIQUE_ID_IN          : in std_logic_vector(63 downto 0);            
+       GSC_CLK_IN               : in std_logic;
+       GSC_INIT_DATAREADY_OUT   : out std_logic;
+       GSC_INIT_DATA_OUT        : out std_logic_vector(15 downto 0);
+       GSC_INIT_PACKET_NUM_OUT  : out std_logic_vector(2 downto 0);
+       GSC_INIT_READ_IN         : in std_logic;
+       GSC_REPLY_DATAREADY_IN   : in std_logic;
+       GSC_REPLY_DATA_IN        : in std_logic_vector(15 downto 0);
+       GSC_REPLY_PACKET_NUM_IN  : in std_logic_vector(2 downto 0);
+       GSC_REPLY_READ_OUT       : out std_logic;
+       GSC_BUSY_IN              : in std_logic;
+       
+       MAKE_RESET_OUT           : out std_logic;
+
+       -- for simulation of receiving part only
        MAC_RX_EOF_IN           : in    std_logic;
        MAC_RXD_IN              : in    std_logic_vector(7 downto 0);
        MAC_RX_EN_IN            : in    std_logic;
 
-               ANALYZER_DEBUG_OUT : OUT std_logic_vector(63 downto 0)
-               );
+
+       -- debug ports
+       ANALYZER_DEBUG_OUT                      : out   std_logic_vector(63 downto 0)
+);
        END COMPONENT;
 
        SIGNAL CLK :  std_logic;
@@ -205,6 +226,22 @@ BEGIN
                SFP_PRSNT_N_IN => SFP_PRSNT_N_IN,
                SFP_LOS_IN => SFP_LOS_IN,
                SFP_TXDIS_OUT => SFP_TXDIS_OUT,
+               
+               MC_UNIQUE_ID_IN          => (others => '0'),            
+               GSC_CLK_IN               => test_clk,
+               GSC_INIT_DATAREADY_OUT   => open,
+               GSC_INIT_DATA_OUT        => open,
+               GSC_INIT_PACKET_NUM_OUT  => open,
+               GSC_INIT_READ_IN         => '0',
+               GSC_REPLY_DATAREADY_IN   => '0',
+               GSC_REPLY_DATA_IN        => (others => '0'),
+               GSC_REPLY_PACKET_NUM_IN  => (others => '0'),
+               GSC_REPLY_READ_OUT       => open,
+               GSC_BUSY_IN              => '0',
+               
+               MAKE_RESET_OUT           => open,
+               
+               
        -- for simulation of receiving part only
        MAC_RX_EOF_IN           => MAC_RX_EOF_IN,
        MAC_RXD_IN              => MAC_RXD_IN,
@@ -323,32 +360,34 @@ begin
 -- Loop the transmissions
 -------------------------------------------------------------------------------
        trigger_counter := x"4710";
-       trigger_loop    := 10;
-
-       RECEIVE_LOOP: for J in 0 to 1 loop
-
-               wait for 200 ns;
+       trigger_loop    := 1;
        
-               -- IPU transmission starts
-               wait until rising_edge(test_clk);
-               
-               test_data2     := x"ff";
-               MY_DATA_LOOP2: for k in 0 to 200 + (J * 10) loop
-                       test_data2 := test_data2 + 1;
-                       wait until rising_edge(test_clk);
-                       MAC_RXD_IN <= std_logic_vector(test_data2); 
-                       MAC_RX_EN_IN <= '1';
-               end loop MY_DATA_LOOP2;
-
-               MAC_RX_EN_IN <= '0';
-               MAC_RXD_IN <= "00000000";
-               MAC_RX_EOF_IN <= '1';
-               wait until rising_edge(test_clk);
-               MAC_RX_EOF_IN <= '0';
-
-               --wait for 3 us;
-
-       end loop RECEIVE_LOOP;
+       wait until rising_edge(test_clk);
+
+--     RECEIVE_LOOP: for J in 0 to 1 loop
+--
+--             wait for 200 ns;
+--     
+--             -- IPU transmission starts
+--             wait until rising_edge(test_clk);
+--             
+--             test_data2     := x"ff";
+--             MY_DATA_LOOP2: for k in 0 to 200 + (J * 10) loop
+--                     test_data2 := test_data2 + 1;
+--                     wait until rising_edge(test_clk);
+--                     MAC_RXD_IN <= std_logic_vector(test_data2); 
+--                     MAC_RX_EN_IN <= '1';
+--             end loop MY_DATA_LOOP2;
+--
+--             MAC_RX_EN_IN <= '0';
+--             MAC_RXD_IN <= "00000000";
+--             MAC_RX_EOF_IN <= '1';
+--             wait until rising_edge(test_clk);
+--             MAC_RX_EOF_IN <= '0';
+--
+--             --wait for 3 us;
+--
+--     end loop RECEIVE_LOOP;
 
        MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop
                -- generate a real random byte for CTS
@@ -377,7 +416,7 @@ begin
                --test_data_len := INTEGER(TRUNC(rand * 800.0)) + 1;
                
                --test_data_len := 9685;
-               test_data_len := 400;
+               test_data_len := 200;
                
                -- calculate the needed variables
                test_loop_len := 2*(test_data_len - 1) + 1;

diff --git a/gbe2_ecp3/trb_net16_gbe_buf.vhd b/gbe2_ecp3/trb_net16_gbe_buf.vhd
index 534614727429fc5522696efc92d0e2722fbb77d3..4cdff3beb7d60f7dda78e06816b0ab7695eb12c3 100755 (executable)
--- a/gbe2_ecp3/trb_net16_gbe_buf.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_buf.vhd
@@ -814,6 +814,8 @@ port map(
        GBE_DELAY_OUT             => pc_delay,
        GBE_ALLOW_LARGE_OUT       => allow_large,  -- gk 21.07.10
        GBE_ALLOW_RX_OUT          => allow_rx,
+       GBE_ALLOW_BRDCST_ETH_OUT  => open,
+       GBE_ALLOW_BRDCST_IP_OUT   => open,
        GBE_FRAME_DELAY_OUT       => frame_delay, -- gk 09.12.10
        GBE_ALLOWED_TYPES_OUT     => fr_allowed_types,
        GBE_ALLOWED_IP_OUT        => fr_allowed_ip,
@@ -905,6 +907,8 @@ port map(
        GBE_DELAY_OUT             => pc_delay,
        GBE_ALLOW_LARGE_OUT       => open,
        GBE_ALLOW_RX_OUT          => open,
+       GBE_ALLOW_BRDCST_ETH_OUT  => open,
+       GBE_ALLOW_BRDCST_IP_OUT   => open,
        GBE_FRAME_DELAY_OUT       => frame_delay, -- gk 09.12.10
        GBE_ALLOWED_TYPES_OUT     => fr_allowed_types,
        GBE_ALLOWED_IP_OUT        => fr_allowed_ip,
@@ -948,7 +952,7 @@ port map(
        DBG_FT1_IN                => dbg_ft1,
        DBG_FT2_IN                => dbg_ft(31 downto 0),
        DBG_FR_IN                 => dbg_fr,
-       DBG_RC_IN                 => dbg_rc(31 downto 0),
+       DBG_RC_IN                 => dbg_rc,
        DBG_MC_IN                 => dbg_mc,
        DBG_TC_IN                 => dbg_tc(31 downto 0),
        DBG_FIFO_RD_EN_OUT        => dbg_rd_en,

diff --git a/gbe2_ecp3/trb_net16_gbe_setup_simplified.vhd b/gbe2_ecp3/trb_net16_gbe_setup_simplified.vhd
index 4d3881d73ef6574dbf039aed13ae44ecc05305ac..282b036520a44a86952e843f2b388670d5de6cd7 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_setup_simplified.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_setup_simplified.vhd
@@ -44,6 +44,8 @@ port(
        GBE_DELAY_OUT             : out std_logic_vector(31 downto 0);
        GBE_ALLOW_LARGE_OUT       : out std_logic;
        GBE_ALLOW_RX_OUT          : out std_logic;
+       GBE_ALLOW_BRDCST_ETH_OUT  : out std_logic;
+       GBE_ALLOW_BRDCST_IP_OUT   : out std_logic;
        GBE_FRAME_DELAY_OUT       : out std_logic_vector(31 downto 0); -- gk 09.12.10
        GBE_ALLOWED_TYPES_OUT     : out std_logic_vector(31 downto 0);
        GBE_ALLOWED_IP_OUT        : out std_logic_vector(31 downto 0);

diff --git a/gbe2_ecp3/trb_net16_gbe_transmit_control.vhd b/gbe2_ecp3/trb_net16_gbe_transmit_control.vhd
index a39fc5e9690d8229e394c4cf495abf9fab3b1cb9..9a3354795c6709f10463544115aeaf2d2517c04f 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_transmit_control.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_transmit_control.vhd
@@ -156,10 +156,14 @@ begin
        when IDLE =>
                state <= x"1";
                if (FC_READY_IN = '1') then
-                       if (MC_TRANSMIT_CTRL_IN = '1') then
-                               tx_next_state <= TRANSMIT_CTRL;
-                       elsif (MC_TRANSMIT_DATA_IN = '1') then
+                       if (MC_TRANSMIT_DATA_IN = '1') then
                                tx_next_state <= TRANSMIT_DATA;
+                       elsif (MC_TRANSMIT_CTRL_IN = '1') then
+                               tx_next_state <= TRANSMIT_CTRL;
+--                     if (MC_TRANSMIT_CTRL_IN = '1') then
+--                             tx_next_state <= TRANSMIT_CTRL;
+--                     elsif (MC_TRANSMIT_DATA_IN = '1') then
+--                             tx_next_state <= TRANSMIT_DATA;
                        else
                                tx_next_state <= IDLE;
                        end if;

diff --git a/gbe2_ecp3/trb_net16_ipu2gbe.vhd b/gbe2_ecp3/trb_net16_ipu2gbe.vhd
index 096ee40effda4b32dc92f4debc51d9eb24d921c4..0f220a37b96456cce1107fd8af11d8ff0853a3e4 100755 (executable)
--- a/gbe2_ecp3/trb_net16_ipu2gbe.vhd
+++ b/gbe2_ecp3/trb_net16_ipu2gbe.vhd
@@ -369,7 +369,7 @@ begin
        end if;
 end process saveMachineProc;
 
-saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN)
+saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN, input_data_ctr, MAX_MESSAGE_SIZE_IN)
 begin
        saveNextState      <= SIDLE;
        data_req_comb      <= '0';
@@ -634,6 +634,8 @@ port map(
        AlmostFull      => sf_afull
 );
 
+reset_split_fifo <= '1' when (saveCurrentState = RESET_FIFO or RESET = '1') else '0';
+
 ------------------------------------------------------------------------------------------
 ------------------------------------------------------------------------------------------
 ------------------------------------------------------------------------------------------
@@ -737,7 +739,8 @@ end process loadMachineProc;
 loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed,
                        PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN,
                        MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr,
-                       first_run_addr, load_eod, event_waiting, MULT_EVT_ENABLE_IN, message_size)
+                       first_run_addr, load_eod, event_waiting, MULT_EVT_ENABLE_IN, message_size, DATA_GBE_ENABLE_IN, first_event,
+                       prev_bank_select, bank_select)
 begin
        loadNextState    <= LIDLE;
        rst_rem_ctr_comb <= '0';