burst option for flash, IF

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
index f59260f9ca24dfac5dfa961305fa975ab3716651..7585f6d0933670bfaa049b2a5eb7f764c3e063a2 100644 (file)
--- a/machxo3/flash/generic_flash_ctrl.vhd
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -18,7 +18,8 @@
 --         Bit 1 : Master start (starts unpacking = booting)\r
 --  0x5D : Bits 0/1: Flash memory read buswidth:\r
 --         00 : 8 Bit, 01 : 16 Bit, 11 : 32 Bit (if available)\r
---         Bit 8: 0: Little Endian; 1: Big Endian\r
+--         Bit 4: 0: Little Endian; 1: Big Endian\r
+--         Bit 11-8 : Burst counter\r
 --  0x5E-5F : Debug registers\r
 \r
 \r
@@ -112,7 +113,7 @@ architecture arch of generic_flash_ctrl is
   signal enable_cfg_flash : std_logic;\r
   signal testreg : std_logic_vector(DATA_BUS_WIDTH-1 downto 0);\r
   signal memreg  : std_logic_vector(DATA_BUS_WIDTH-1 downto 0);\r
-  \r
+  signal burst_counter : std_logic_vector(3 downto 0);\r
 \r
   signal out_delay : std_logic_vector(2 downto 0);\r
   \r
@@ -192,7 +193,9 @@ PROC_SELECTOR : process begin
   \r
   ram_write_i <= '0';\r
   ram_data_i <= x"00";\r
-  spi_ram_addr_i <= x"0";\r
+  if (burst_counter = "0000") then\r
+    spi_ram_addr_i <= x"0";\r
+  end if;\r
   spi_flash_go <= '0';\r
 \r
   if (clean_master_start_reg = '1') then\r
@@ -242,7 +245,9 @@ PROC_SELECTOR : process begin
       -- at least 16 bit burst\r
       spi_ram_addr_i <= std_logic_vector(unsigned(spi_ram_addr_i)+1); -- prepare nibble2\r
     end if;\r
-    out_delay <= "010";\r
+    if (SPI_BUSY_IN = '0') then\r
+      out_delay <= "010";\r
+    end if;\r
   elsif (out_delay = "010") then\r
     reg_LOC_READ_OUT  <= '0';    \r
     if (memreg(0) = '0') then\r
@@ -255,7 +260,7 @@ PROC_SELECTOR : process begin
         -- at least 24 bit burst\r
         spi_ram_addr_i <= std_logic_vector(unsigned(spi_ram_addr_i)+1); --prepare nibble3\r
       end if;\r
-      if (memreg(8) = '1') then\r
+      if (memreg(4) = '1') then\r
         reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-8) <= ram_data_o;\r
       else\r
         reg_SPI_DATA_OUT(15 downto 0) <= x"00" & ram_data_o; -- write nibble1\r
@@ -264,7 +269,7 @@ PROC_SELECTOR : process begin
     end if;\r
   elsif (out_delay = "011") then\r
     reg_LOC_READ_OUT  <= '0';\r
-    if (memreg(8) = '1') then\r
+    if (memreg(4) = '1') then\r
       reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-16) <= reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-8) & ram_data_o;\r
     else\r
       reg_SPI_DATA_OUT(15 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(7 downto 0);\r
@@ -282,7 +287,7 @@ PROC_SELECTOR : process begin
   elsif (out_delay = "100" and DATA_BUS_WIDTH > 16) then\r
     reg_LOC_READ_OUT  <= '0';\r
     reg_SPI_READY_OUT <= '0';\r
-    if (memreg(8) = '1') then\r
+    if (memreg(4) = '1') then\r
       reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-24) <= reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-16) & ram_data_o;\r
     else\r
       reg_SPI_DATA_OUT(23 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(15 downto 0);\r
@@ -291,7 +296,7 @@ PROC_SELECTOR : process begin
   elsif (out_delay = "101" and DATA_BUS_WIDTH > 24) then\r
     reg_LOC_READ_OUT  <= '0';\r
     reg_SPI_READY_OUT <= '1';\r
-    if (memreg(8) = '1') then\r
+    if (memreg(4) = '1') then\r
       reg_SPI_DATA_OUT(31 downto 0) <= reg_SPI_DATA_OUT(31 downto 8) & ram_data_o;\r
     else\r
       reg_SPI_DATA_OUT(31 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(23 downto 0);\r
@@ -300,13 +305,22 @@ PROC_SELECTOR : process begin
   else\r
     out_delay <= "000";\r
   end if;\r
+\r
+  if (out_delay = "000" and burst_counter /= "0000" and SPI_BUSY_IN = '0' and reg_SPI_READY_OUT = '0') then\r
+    out_delay <= "001";\r
+    reg_LOC_READ_OUT  <= '0';\r
+    reg_SPI_READY_OUT <= '0';\r
+    spi_ram_addr_i <= std_logic_vector(unsigned(spi_ram_addr_i)+1);\r
+    burst_counter <= std_logic_vector(unsigned(burst_counter)-1);\r
+  end if;\r
   \r
   if (SPI_READ_IN = '1') then    \r
-    if (SPI_ADDR_IN(7 downto 4) = x"4") then\r
+    if (SPI_ADDR_IN(7 downto 4) = x"4" and burst_counter = "0000") then\r
       out_delay <= "001";\r
       reg_LOC_READ_OUT  <= '0';\r
       reg_SPI_READY_OUT <= '0';\r
       spi_ram_addr_i <= SPI_ADDR_IN(3 downto 0); -- prepare nibble1\r
+      burst_counter <= memreg(11 downto 8);\r
     elsif (SPI_ADDR_IN(7 downto 0) = x"5C") then\r
       reg_LOC_READ_OUT  <= '0';\r
       reg_SPI_READY_OUT <= '1';\r
@@ -315,6 +329,7 @@ PROC_SELECTOR : process begin
       reg_LOC_READ_OUT  <= '0';\r
       reg_SPI_READY_OUT <= '1';\r
       reg_SPI_DATA_OUT  <= memreg;\r
+      reg_SPI_DATA_OUT(11 downto 8) <= burst_counter;\r
       -- reg_SPI_DATA_OUT(15 downto 0) <= auto_dbg & "00" & master_flash_page;\r
     elsif (SPI_ADDR_IN(7 downto 0) = x"5e") then\r
       reg_LOC_READ_OUT  <= '0';\r