-- signal ram_data_o: std_logic_vector(7 downto 0);\r
-- signal ram_addr_i: std_logic_vector(3 downto 0);\r
signal temperature_i : std_logic_vector(11 downto 0);\r
-\r
+ signal ID_OUT : std_logic_vector(31 downto 0);\r
\r
signal pwm_i : std_logic_vector(32 downto 1);\r
signal INP_i : std_logic_vector(15 downto 0);\r
---------------------------------------------------------------------------\r
-- SPI Interface\r
--------------------------------------------------------------------------- \r
---THE_SPI_SLAVE : entity work.spi_slave\r
--- port map(\r
--- CLK => clk_i,\r
--- SPI_CLK => SPI_CLK,\r
--- SPI_CS => SPI_CS,\r
--- SPI_IN => SPI_IN,\r
--- SPI_OUT => buf_SPI_OUT,\r
--- DATA_OUT => spi_data_i,\r
--- REG00_IN => spi_reg00_i,\r
--- REG10_IN => spi_reg10_i,\r
--- REG20_IN => spi_reg20_i,\r
--- REG40_IN => spi_reg40_i,\r
--- OPERATION_OUT => spi_operation_i,\r
--- CHANNEL_OUT => spi_channel_i,\r
--- WRITE_OUT => spi_write_i,\r
--- DEBUG_OUT => spi_debug_i\r
--- );\r
-\r
---SPI_OUT <= buf_SPI_OUT; \r
-\r
---spi_reg00_i <= pwm_data_o;\r
--- spi_reg10_i <= idram(to_integer(unsigned(spi_channel_i(2 downto 0))));\r
--- spi_reg40_i <= flash_busy & flash_err & "000000" & ram_data_o;\r
---spi_reg10_i <= (others => '0');\r
---spi_reg40_i <= '0' & '0' & "000000" & ram_data_o;\r
\r
THE_SPI : entity work.spi_slave\r
port map(\r
- CLK => clk_33,\r
+ CLK => clk_i,\r
SPI_CLK => SPI_CLK,\r
SPI_CS => SPI_CS,\r
SPI_IN => SPI_IN,\r
\r
THE_FLASH_CONTROLLER : entity generic_flash_ctrl\r
port map(\r
- CLK => clk_33,\r
+\r
+ CLK_l => clk_i,\r
+ CLK_f => clk_33,\r
RESET => '0',\r
\r
SPI_DATA_IN => spi_data_out,\r
);\r
\r
\r
-\r
---------------------------------------------------------------------------\r
-- Temperature and UID reader\r
--------------------------------------------------------------------------- \r
port map(\r
clk => clk_i,\r
temperature => temperature_i,\r
- sda => I2C_SCL,\r
+ ID_OUT => ID_OUT,\r
+ sda => I2C_SDA,\r
scl => I2C_SCL\r
);\r
\r
--------------------------------------------------------------------------- \r
\r
THE_IO_REG : process begin\r
- wait until rising_edge(clk_33);\r
+ wait until rising_edge(clk_i);\r
bus_ready <= '0';\r
pwm_write_i <= '0'; \r
spi_tx_data <= x"0000";\r
pwm_addr_i <= spi_addr(3 downto 0);\r
else\r
case spi_addr is\r
+ when x"10" => spi_tx_data <= ID_OUT(7 downto 0) & "00000000" ;\r
+ when x"11" => spi_tx_data <= "00000000" & ID_OUT(31 downto 24);\r
+ when x"12" => spi_tx_data <= ID_OUT(23 downto 8);\r
+ when x"13" => spi_tx_data <= ID_OUT(7 downto 0) & "00011100"; --"0x1C"+\r
when x"14" => spi_tx_data <= "0000" & temperature_i;\r
when x"20" => spi_tx_data <= input_enable;\r
when x"21" => spi_tx_data <= inp_status;\r
---------------------------------------------------------------------------\r
-- Test Output\r
--------------------------------------------------------------------------- \r
- TEST_LINE(7 downto 0) <= selected_delay;\r
- TEST_LINE(13 downto 8) <= (others => '0');\r
+ --TEST_LINE(7 downto 0) <= selected_delay;\r
+ TEST_LINE(13) <= SPI_CLK;\r
+ TEST_LINE(12) <= SPI_out;\r
+ TEST_LINE(11) <= SPI_in;\r
+ \r
+ TEST_LINE(10 downto 8) <= (others => '0');\r
end architecture;\r
\r
\r
-
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Amps2_Interface is
generic(
clk_frequency : integer := 133_000_000;
- i2c_frequency : integer := 13_300
+ i2c_frequency : integer := 100_000
);
port(
--System clock.
- clk : in std_logic;
- reset : in std_logic;
- temperature: out std_logic_vector(11 downto 0);
+ clk : in std_logic;
+ reset : in std_logic :='0';
+ temperature : out std_logic_vector(11 downto 0);
+ ID_OUT : out std_logic_vector(31 downto 0);
--I2C signals.
- sda : inout std_logic;
- scl : inout std_logic
-
+ sda : inout std_logic;
+ scl : inout std_logic
);
end Amps2_Interface;
architecture Behavioral of Amps2_Interface is
- --The address of the TCS34725. This device has only one possible address,
- --so we won't genericize it.
- constant addr_temp_sensor : std_logic_vector := "1001000";
- constant addr_UID : std_logic_vector := "1010000";
+constant addr_temp_sensor : std_logic_vector := "1001000";
+constant addr_UID : std_logic_vector := "1010000";
--Signals for data exchange with the core I2C controller.
- signal temp_data_LSB,temp_data_MSB,data_UID,data_to_write, last_read_data : std_logic_vector(7 downto 0);
- signal reading, ena, busy : std_logic;
-signal address: std_logic_vector(6 downto 0);
+--I2C commands .
+constant temp_register_pointer : std_logic_vector := "00000000";
+constant UID_pointer : std_logic_vector := "11111100";
+ --Signals for data exchange with the core I2C controller.
+ signal address: std_logic_vector(6 downto 0);
+ signal data_to_write, last_read_data : std_logic_vector(7 downto 0);
+ signal reading, transaction_active, controller_in_use : std_logic;
+signal temp_data_MSB: std_logic_vector(7 downto 0);
+signal temp_data_LSB : std_logic_vector(7 downto 0);
--Rising edge detect for the "controller in use" signal.
--A rising edge of this signal indicates that the I2C controller has accepted our data.
signal controller_was_in_use : std_logic;
- signal controller_accepted_data : std_logic;
-
+ signal controller_accepted_data, new_data_available : std_logic;
--I2C read/write constants.
constant write : std_logic := '0';
constant read : std_logic := '1';
- --I2C commands .
- constant pointer_register : std_logic_vector := "00000000";
-
- signal current_byte_number : integer range 2 downto 0 := 0;
-
-
--Core state machine logic.
- type state_type is (startup,read_UID, wait_for_temp_sensor, send_first_command,
- wait_for_read, start_read, read_data_temp_sensor, finish_1byte_read_and_continue,
- finish_read_temp_sensor);
- signal state : state_type := startup;
-
+ type state_type is (STARTUP, SEND_POWER_COMMAND, TURN_POWER_ON,
+ WAIT_BEFORE_READING, SEND_READ_COMMAND, START_READ, FINISH_READ_AND_CONTINUE, FINISH_READ_AND_RESTART,
+ UID_send_adress,UID_WAIT_BEFORE_READING,UID_START_READ,UID_FINISH_READ_AND_CONTINUE,UID_FINISH_READ_AND_RESTART,UID_FINISH
+ );
+ signal state : state_type := STARTUP;
+
+ type byte_buffer is array(natural range <>) of std_logic_vector(7 downto 0);
+ signal read_buffer : byte_buffer(1 downto 0);
+
+ signal current_byte_number : integer range 2 downto 0 := 0;
+
+ --Create a simple read buffer for each of the sequential bytes.
+ type UID_byte_buffer is array(natural range <>) of std_logic_vector(7 downto 0);
+ signal UID_read_buffer : byte_buffer(4 downto 0);
+
+ signal UID_current_byte_number : integer range 4 downto 0 := 0;
+
begin
- --
- -- Instantiate our I2C controller.
- --
- I2C_CONTROLLER:
- entity i2c_master
+
+ I2C_CONTROLLER: entity i2c_master
generic map(
- input_clk => 133_000_000, --Our system clock speed.
- bus_clk => 13_300
+ input_clk => clk_frequency,
+ bus_clk => i2c_frequency
)
port map(
- clk => clk,
- reset_n => not(reset),
- ena => ena,
- addr => address,
- rw => reading,
- data_wr => data_to_write,
- busy => busy,
- data_rd => last_read_data,
- ack_error => open,
- sda => sda,
- scl => scl
- );
-
- controller_was_in_use <= busy when rising_edge(clk);
- controller_accepted_data <= busy and not controller_was_in_use;
-
-
-process(clk,reset)
-begin
-
- -- If our reset signal is being driven, restar the FSM.
- if (reset = '1') then
- state <= startup ;
+ clk => clk,
+ reset_n => not reset,
+ ena => transaction_active,
+ addr => address,
+ rw => reading,
+ data_wr => data_to_write,
+ busy => controller_in_use,
+ data_rd => last_read_data,
+ ack_error => open,
+ sda => sda,
+ scl => scl
+ );
+
+ controller_was_in_use <= controller_in_use when rising_edge(clk);
+ controller_accepted_data <= controller_in_use and not controller_was_in_use;
+
+ process(clk)
+ begin
+ if reset = '1' then
+ state <= state_type'left;
elsif rising_edge(clk) then
-
- --Keep the following signals low unless asserted.
data_to_write <= (others => '0');
-
- case state is
-
- when startup =>
-
- if busy = '0' then
- state <= read_UID;
- end if;
-
-
- when read_UID =>
- ena <= '1';
- reading <= read;
- address <= addr_UID;
-
- if controller_accepted_data = '1' then
- state <= wait_for_temp_sensor;
- end if;
-
-
- when wait_for_temp_sensor =>
- ena <= '0';
-
- if busy = '0' then
- state <= send_first_command;
- data_UID <= last_read_data;
- end if;
-
-
-
- when send_first_command =>
- ena <= '1';
- reading <= write;
- address <= addr_temp_sensor;
- data_to_write <= pointer_register;
-
- --Wait here for the I2C controller to accept the new transmission, and become busy.
- if controller_accepted_data = '1' then
- state <= wait_for_read;
- end if;
- when wait_for_read =>
-
- ena<='0';
- current_byte_number <=0;
- if busy = '0' then
- state <= start_read;
- end if;
-
- when start_read =>
- ena <= '1';
- reading <= read;
-
- --Wait for the controller to accept the read instruction.
- if controller_accepted_data = '1' then
-
- if current_byte_number = 2 then
- state <= finish_read_temp_sensor;
+ case state is
+
+ when STARTUP =>
+ if controller_in_use = '0' then
+ state <= WAIT_BEFORE_READING;
+ end if;
+
+ when WAIT_BEFORE_READING =>
+
+ transaction_active <= '0';
+ current_byte_number <= 0;
+ if controller_in_use = '0' then
+ state <= START_READ;
+ end if;
+
+ when START_READ =>
+ transaction_active <= '1';
+ reading <= read;
+ address <= addr_temp_sensor;
+ if controller_accepted_data = '1' then
+ if current_byte_number = read_buffer'high then
+ state <= FINISH_READ_AND_RESTART;
else
- state <= finish_1byte_read_and_continue;
+ state <= FINISH_READ_AND_CONTINUE;
end if;
-
- end if;
-
- when finish_1byte_read_and_continue =>
-
- --Wait for the I2C controller to finish reading...
- if busy = '0' then
-
- --...capture the read result.
- case current_byte_number is
- when 0 =>
- temp_data_MSB<= last_read_data;
-
- when 1 =>
- temp_data_LSB<= last_read_data;
-
- when others =>
- state <= finish_read_temp_sensor;
-
- end case;
- --... move to the next spot in the read buffer.
+ end if;
+
+ when FINISH_READ_AND_CONTINUE =>
+ if controller_in_use = '0' then
+ read_buffer(current_byte_number) <= last_read_data;
current_byte_number <= current_byte_number + 1;
-
- ---... and finish reading.
- state <= start_read;
-
- end if;
-
- when finish_read_temp_sensor =>
-
- when others =>
- ena <= '1';
-
- end case;
- end if;
- end process;
-
-
-temperature(11 downto 4)<=temp_data_MSB;
-temperature(3 downto 0)<=temp_data_LSB(7 downto 4);
-
- end Behavioral;
+ state <= START_READ;
+ end if;
+
+ when FINISH_READ_AND_RESTART =>
+ transaction_active <= '0';
+ if controller_in_use = '0' then
+ read_buffer(current_byte_number) <= last_read_data;
+ state <= UID_send_adress;
+ end if;
+ -----------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------
+ when UID_send_adress =>
+ transaction_active <= '1';
+ reading <= write;
+ data_to_write <= UID_pointer;
+ address <= addr_UID;
+ --UID_current_byte_number <= 0;
+ if controller_accepted_data = '1' then
+ state <= UID_START_READ;
+ end if;
+
+ when UID_WAIT_BEFORE_READING =>
+ transaction_active <= '0';
+ UID_current_byte_number <= 0;
+ if controller_in_use = '0' then
+ state <= UID_START_READ;
+ end if;
+
+ when UID_START_READ =>
+ transaction_active <= '1';
+ reading <= read;
+ if controller_accepted_data = '1' then
+ if UID_current_byte_number = UID_read_buffer'high then
+ state <= UID_FINISH_READ_AND_RESTART;
+ else
+ state <= UID_FINISH_READ_AND_CONTINUE;
+ end if;
+ end if;
+
+ when UID_FINISH_READ_AND_CONTINUE =>
+
+ if controller_in_use = '0' then
+ UID_read_buffer(UID_current_byte_number) <= last_read_data;
+ UID_current_byte_number <= UID_current_byte_number + 1;
+ state <= UID_START_READ;
+ end if;
+
+ when UID_FINISH_READ_AND_RESTART =>
+ transaction_active <= '0';
+ if controller_in_use = '0' then
+ UID_read_buffer(UID_current_byte_number) <= last_read_data;
+ state <= UID_FINISH;
+ end if;
+
+ when UID_FINISH =>
+ end case;
+ end if;
+ end process;
+temp_data_LSB <= read_buffer(1);
+temp_data_MSB <= read_buffer(0);
+temperature(11 downto 4) <=temp_data_MSB;
+temperature(3 downto 0) <=temp_data_LSB(7 downto 4);
+
+ID_OUT(31 downto 24) <=UID_read_buffer(0);
+ID_OUT(23 downto 16) <=UID_read_buffer(1);
+ID_OUT(15 downto 8) <=UID_read_buffer(2);
+ID_OUT(7 downto 0) <=UID_read_buffer(3);
+
+end Behavioral;
jspc29 / padiwa.git / commitdiff