added simple UART to pulser design

diff --git a/pulser/padiwa_pulser.prj b/pulser/padiwa_pulser.prj
index 5ee1d939408cdea18177d5bc3a850ebb5adedb24..1a067692158956d97da2dbe1cccb74248c94e6d7 100644 (file)
--- a/pulser/padiwa_pulser.prj
+++ b/pulser/padiwa_pulser.prj
@@ -11,6 +11,10 @@ add_file -vhdl -lib work "../source/pwm.vhd"
 add_file -vhdl -lib work "../cores/pll_shifted_clocks.vhd"
 add_file -vhdl -lib work "../cores/fifo_1kx8.vhd"
 add_file -vhdl -lib work "../source/ffarray.vhd"
+add_file -vhdl -lib work "../source/uart_rec.vhd"
+add_file -vhdl -lib work "../source/uart_trans.vhd"
+add_file -vhdl -lib work "../source/uart_sctrl.vhd"
+
 
 
 add_file -vhdl -lib work "../cores/oddr16.vhd"

diff --git a/pulser/padiwa_pulser.vhd b/pulser/padiwa_pulser.vhd
index 12d360848a5d9bc35d21764f4231a2d42df7c922..fd17b8982a83d3c7debbdc217fa24733f1e997fc 100644 (file)
--- a/pulser/padiwa_pulser.vhd
+++ b/pulser/padiwa_pulser.vhd
@@ -40,6 +40,8 @@ attribute NOM_FREQ : string;
 attribute NOM_FREQ of clk_source : label is "133.00";
 signal clk_i  : std_logic;
 
+signal led    : std_logic_vector(3 downto 0) := "1010";
+
 begin
 
 ---------------------------------------------------------------------------
@@ -55,17 +57,38 @@ clk_source: OSCH
     SEDSTDBY => open
   );
 
+  
+---------------------------------------------------------------------------
+-- UART
+---------------------------------------------------------------------------
+THE_UART : entity work.uart_sctrl
+  port map(
+    CLK     => clk_i,
+    RESET   => '0',
+    UART_RX => SPARE_LINE(0),
+    UART_TX => SPARE_LINE(2),
+    
+    DATA_OUT  => open,
+    DATA_IN   => x"00000000",
+    WRITE_OUT => open,
+    READ_OUT  => open,
+    READY_IN  => '0',
+    
+    DEBUG     => open
+    );
 
 
-SPARE_LINE(0) <= 'Z'; --TX from PC
+    
+---------------------------------------------------------------------------
+-- Other I/O
+---------------------------------------------------------------------------    
 SPARE_LINE(1) <= 'Z'; --C1 spare
-SPARE_LINE(2) <= SPARE_LINE(0) when rising_edge(clk_i); --RX to PC
 SPARE_LINE(3) <= 'Z'; --C2 spare
 
 
-LED_GREEN  <= '0';
-LED_ORANGE <= '1';
-LED_RED    <= '0';
-LED_YELLOW <= '1';
+LED_GREEN  <= led(0);
+LED_ORANGE <= led(1);
+LED_RED    <= led(2);
+LED_YELLOW <= led(3);
 
 end architecture;

diff --git a/source/uart_sctrl.vhd b/source/uart_sctrl.vhd
new file mode 100644 (file)
index 0000000..e6a968a
--- /dev/null
+++ b/source/uart_sctrl.vhd
@@ -0,0 +1,69 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.version.all;
+
+library machxo2;
+use machxo2.all;
+
+
+entity uart_sctrl is
+  port(
+    CLK     : in  std_logic;
+    RESET   : in  std_logic;
+    UART_RX : in  std_logic;
+    UART_TX : out std_logic;
+    
+    DATA_OUT  : out std_logic_vector(31 downto 0);
+    DATA_IN   : in  std_logic_vector(31 downto 0);
+    WRITE_OUT : out std_logic;
+    READ_OUT  : out std_logic;
+    READY_IN  : in  std_logic;
+    
+    DEBUG   : out std_logic_vector(15 downto 0)
+    );
+end entity;
+
+
+architecture uart_sctrl_arch of uart_sctrl is
+
+constant CLK_DIV : integer := 133000000/115200;
+
+signal rx_data   : std_logic_vector(7 downto 0);
+signal tx_data   : std_logic_vector(7 downto 0);
+signal rx_ready  : std_logic;
+signal tx_send   : std_logic;
+signal tx_ready  : std_logic;
+
+begin
+
+
+THE_RX : entity work.uart_rec
+  port map(
+    CLK_DIV      => CLK_DIV,
+    CLK          => CLK,
+    RST          => RESET,
+    RX           => UART_RX,
+    DATA_OUT     => rx_data,
+    DATA_WAITING => rx_ready
+    );
+
+THE_TX : entity work.uart_trans
+  port map(
+    CLK_DIV      => CLK_DIV,
+    CLK          => CLK,
+    RST          => RESET,
+    DATA_IN      => tx_data,
+    SEND         => tx_send,
+    READY        => tx_ready,
+    TX           => UART_TX
+    );
+    
+tx_data <= rx_data;
+tx_send <= rx_ready;
+    
+end architecture;
\ No newline at end of file

diff --git a/source/uart_trans.vhd b/source/uart_trans.vhd
index 3a10a8b0b2e28c2e98f99bba5da03d58d28ca16e..c50dc0af196d7122550a0d54afdc5a7b824c175d 100644 (file)
--- a/source/uart_trans.vhd
+++ b/source/uart_trans.vhd
@@ -135,6 +135,7 @@ DEBUG(3) <= '0';
     -- reset clock divider counters when reset signal is on 
     if RST = '1' then
       state <= idle;
+      ready_sig <= '1';
     end if;
 
   end process;