Adapt Xilinx SYSMON reader to 120 MHz clock

diff --git a/xilinx/xcku/read_sysmon.vhd b/xilinx/xcku/read_sysmon.vhd
index 9d9d106eec12162b2f341610702e0e2039e197f4..c3ccbd714215e43c50dd0e854ba90b9f1ae71d41 100644 (file)
--- a/xilinx/xcku/read_sysmon.vhd
+++ b/xilinx/xcku/read_sysmon.vhd
@@ -6,7 +6,7 @@ use unisim.vcomponents.all;
 
 entity read_sysmon is
     port (
-        CLK_100       : in  std_logic;
+        CLK           : in  std_logic;
         RESET         : in  std_logic;
         TEMP          : out std_logic_vector(15 downto 0);
         TEMP_VALID    : out std_logic;
@@ -43,8 +43,10 @@ end entity read_sysmon;
 -- the clock-conversion factor.
 
 -- Maximum ADC clock frequency is 5.2 MHz
--- -> Divide 100 MHz DRP clock by 20 for a 5 MHz ADC clock
--- -> Divider value (upper byte of register 0x42) is 0x14
+-- Maximum allowed CLK frequency is 120 MHz
+-- -> Divide 120 MHz DRP clock by 24 for a 5 MHz ADC clock
+-- -> Divider value (upper byte of register 0x42) is 0x18
+-- (Results in 4.1666 MHz in case of a 100 MHz clock)
 
 architecture structural of read_sysmon is
     type state is (wait_eos, read_temp, wait_temp, read_vccint, wait_vccint,
@@ -61,7 +63,7 @@ begin
     generic map (
         INIT_40               => X"0000",
         INIT_41               => X"0000",
-        INIT_42               => X"1400", -- f_DCLK / f_ADCCLK = 20
+        INIT_42               => X"1800", -- f_DCLK / f_ADCCLK = 24
         INIT_43               => X"0000",
         INIT_44               => X"0000",
         INIT_45               => X"0000",
@@ -141,7 +143,7 @@ begin
         VN           => '0',
         VP           => '0',
         DADDR        => daddr,
-        DCLK         => CLK_100,
+        DCLK         => CLK,
         DEN          => den,
         DI           => x"00_00",
         DWE          => '0',
@@ -152,9 +154,9 @@ begin
     -- Wait until the current sampling sequence for all sensors is finished
     -- (eos = '1'), then read out the DRP registers for each ADC value and
     -- update the outputs.
-    process (CLK_100) is
+    process (CLK) is
     begin
-        if rising_edge(CLK_100) then
+        if rising_edge(CLK) then
             den <= '0';
             daddr <= x"00";
             TEMP_VALID <= '0';

diff --git a/xilinx/xcku/trb_net_xdna.vhd b/xilinx/xcku/trb_net_xdna.vhd
index ceedede8ff601130844c9edcf76795e8c56674a0..873840d3657060d38fe5e105ba6c14252e2eac28 100644 (file)
--- a/xilinx/xcku/trb_net_xdna.vhd
+++ b/xilinx/xcku/trb_net_xdna.vhd
@@ -40,7 +40,7 @@ begin
 
     THE_SYSMON : entity work.read_sysmon
     port map (
-        CLK_100       => CLK,
+        CLK           => CLK,
         RESET         => RESET,
         TEMP          => temp_sysmon,
         TEMP_VALID    => open,