main RX reset counters changed for better timing, SCI RD polling time extended

diff --git a/media_interfaces/sync/main_rx_reset_RS.vhd b/media_interfaces/sync/main_rx_reset_RS.vhd
index 56593795a82b97c8f70c321e818b98d259017f9c..96bc90b48ca03d0584b6d98a450a1ce37982a5f1 100644 (file)
--- a/media_interfaces/sync/main_rx_reset_RS.vhd
+++ b/media_interfaces/sync/main_rx_reset_RS.vhd
@@ -29,11 +29,14 @@ architecture main_rx_reset_RS_arch of main_rx_reset_RS is
 -- Remark: work of Christian Michel. Just re-edited to reflect necessary changes for ECP3.\r
 -- Without this piece of code, many things would have been a real pain.\r
 \r
-  constant Tshort     : unsigned(31 downto 0) := x"0000000a";\r
--- @200MHz 100ms\r
-  constant Tplol      : unsigned(31 downto 0) := x"003fffff"; --x"01312d00";\r
-  constant Tcdr       : unsigned(31 downto 0) := x"003fffff"; --x"01312d00";\r
-  constant Tviol      : unsigned(31 downto 0) := x"003fffff"; --x"01312d00";\r
+  constant Tshort_bit : integer := 4; -- count up to 2^4 = 16\r
+--  constant Tshort     : unsigned(31 downto 0) := x"0000000a";\r
+  constant Tplol_bit  : integer := 22;\r
+--  constant Tplol      : unsigned(31 downto 0) := x"003fffff"; --x"01312d00";\r
+  constant Tcdr_bit   : integer := 22;\r
+--  constant Tcdr       : unsigned(31 downto 0) := x"003fffff"; --x"01312d00";\r
+  constant Tviol_bit  : integer := 22;\r
+--  constant Tviol      : unsigned(31 downto 0) := x"003fffff"; --x"01312d00";\r
 \r
   signal pll_lol_s    : std_logic;\r
   signal cdr_lol_s    : std_logic;\r
@@ -97,7 +100,8 @@ begin
           if( (pll_lol_s = '1') or (sd_los_s = '1') ) then\r
             cnt <= (others => '0');\r
           else\r
-            if( cnt = Tplol ) then\r
+--            if( cnt = Tplol ) then\r
+            if( cnt(Tplol_bit) = '1' ) then\r
               cnt <= (others => '0');\r
               rx_sm <= APPLY_CDR_RST;\r
             else\r
@@ -110,7 +114,8 @@ begin
           RX_SERDES_RST_OUT <= '1';\r
           RX_PCS_RST_OUT    <= '1';\r
           LINK_RX_READY_OUT <= '0';\r
-          if( cnt = Tshort ) then\r
+--          if( cnt = Tshort ) then\r
+          if( cnt(Tshort_bit) = '1' ) then\r
             cnt <= (others => '0');\r
             rx_sm <= WAIT_CDR_LOCK;\r
           else\r
@@ -122,7 +127,8 @@ begin
           RX_SERDES_RST_OUT <= '0';\r
           RX_PCS_RST_OUT    <= '1';\r
           LINK_RX_READY_OUT <= '0';\r
-          if( cnt = Tcdr ) then\r
+--          if( cnt = Tcdr ) then\r
+          if( cnt(Tcdr_bit) = '1' ) then\r
             cnt <= (others => '0');\r
             rx_sm <= TEST_CDR;\r
           else\r
@@ -138,7 +144,8 @@ begin
             cnt <= (others => '0');\r
             rx_sm <= APPLY_CDR_RST;\r
           else\r
-            if( cnt = Tcdr ) then\r
+--            if( cnt = Tcdr ) then\r
+            if( cnt(Tcdr_bit) = '1' ) then\r
               cnt <= (others => '0');\r
               rx_sm <= APPLY_RXPCS_RST;\r
             else\r
@@ -151,7 +158,8 @@ begin
           RX_SERDES_RST_OUT <= '0';\r
           RX_PCS_RST_OUT    <= '1';\r
           LINK_RX_READY_OUT <= '0';\r
-          if( cnt = Tshort ) then\r
+--          if( cnt = Tshort ) then\r
+          if( cnt(Tshort_bit) ) then\r
             cnt <= (others => '0');\r
             rx_sm <= WAIT_RXPCS_LOCK;\r
           else\r
@@ -163,7 +171,8 @@ begin
           RX_SERDES_RST_OUT <= '0';\r
           RX_PCS_RST_OUT    <= '0';\r
           LINK_RX_READY_OUT <= '0';\r
-          if( cnt = Tviol ) then\r
+--          if( cnt = Tviol ) then\r
+          if( cnt(Tviol_bit) = '1' ) then\r
             cnt <= (others => '0');\r
             rx_sm <= TEST_RXPCS;\r
           else\r
@@ -179,7 +188,8 @@ begin
             cnt <= (others => '0');\r
             rx_sm <= APPLY_RXPCS_RST;\r
           else\r
-            if( cnt = Tviol ) then\r
+--            if( cnt = Tviol ) then\r
+            if( cnt(Tviol_bit) = '1' ) then\r
               cnt <= (others => '0');\r
               rx_sm <= CHECK_WAP;\r
             else\r
@@ -193,7 +203,8 @@ begin
           RX_PCS_RST_OUT    <= '0';\r
           LINK_RX_READY_OUT <= '0';\r
           cnt <= (others => '0');\r
-          if( cnt = Tshort ) then\r
+--          if( cnt = Tshort ) then\r
+          if( cnt(Tshort_bit) = '1' ) then\r
             cnt <= (others => '0');\r
             if( wap_zero_s = '1' ) then\r
               rx_sm <= NORMAL_OP;\r
@@ -204,12 +215,6 @@ begin
           else\r
             cnt <= cnt + 1;  \r
           end if;\r
---          if( wap_zero_s = '1' ) then\r
---            rx_sm <= NORMAL_OP;\r
---          else\r
-----            rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK\r
---            rx_sm <= APPLY_CDR_RST;\r
---          end if;\r
      \r
         when NORMAL_OP =>\r
           STATE_OUT <= x"8";\r
@@ -228,6 +233,7 @@ begin
           RX_PCS_RST_OUT    <= '0';\r
           LINK_RX_READY_OUT <= '0';\r
           rx_sm <= POWERUP;\r
+          cnt <= (others => '0');\r
 \r
       end case;\r
   \r

diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd
index 2ea0f3f4d1840173d41cf01ba9d3e2456d2bb1ad..3178438408c3dc20230e768dba7c3a6519afef6f 100644 (file)
--- a/media_interfaces/sync/sci_reader_RS.vhd
+++ b/media_interfaces/sync/sci_reader_RS.vhd
@@ -39,23 +39,15 @@ architecture sci_reader_arch of sci_reader_RS is
 type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
 
 signal sci_state         : sci_ctrl;
-signal sci_timer         : unsigned(12 downto 0) := (others => '0');
+signal sci_timer         : unsigned(14 downto 0) := (others => '0');
 
 signal sci_reg_i         : std_logic;
 signal wa_position       : std_logic_vector(15 downto 0);
 signal next_sci_wr       : std_logic;
---signal wap_req_q         : std_logic_vector(2 downto 0);
 
 begin
 
---  THE_SYNC_PROC: process( CLK )
---  begin
---    if( rising_edge(CLK) ) then
---      wap_req_q(2 downto 0) <= wap_req_q(1 downto 0) & WA_REQ_IN;
---    end if;
---  end process THE_SYNC_PROC;
-
--------------------------------------------------      
+------------------------------------------------      
 -- SCI
 -------------------------------------------------      
 --gives access to serdes config port from slow control and reads word alignment every ~ 40 us