Update all tdctemplate config files to latest version

diff --git a/tdctemplate/config_16_crate_ada_nino.vhd b/tdctemplate/config_16_crate_ada_nino.vhd
index 5282436a0a865f95f8b7866c38b448e3c849a174..fa873b5b6f7a3086fd520c2bf342178d743aa2d3 100644 (file)
--- a/tdctemplate/config_16_crate_ada_nino.vhd
+++ b/tdctemplate/config_16_crate_ada_nino.vhd
@@ -68,7 +68,9 @@ package config is
     
     --trigger generation only on 'fast' channels from Padiwa
     constant TRIG_GEN_FAST_CHANNELS : integer := c_NO;   
-    
+   
+    constant USE_GBE                : integer := c_NO;
+        
     
 ------------------------------------------------------------------------------
 --End of design configuration
@@ -107,6 +109,7 @@ package config is
     constant CLOCK_FREQUENCY      : integer;
     constant MEDIA_FREQUENCY      : integer;
     constant INCLUDED_FEATURES      : std_logic_vector(63 downto 0);
+    constant BROADCAST_BITMASK      : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1');    
     
     
 end;
@@ -137,6 +140,7 @@ function generateIncludedFeatures return std_logic_vector is
     t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
     t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
     t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+    t(45 downto 45) := std_logic_vector(to_unsigned(USE_GBE,1));
     t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
     t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
     t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));

diff --git a/tdctemplate/config_32_sfp_kel.vhd b/tdctemplate/config_32_sfp_kel.vhd
index 52ec0d9a1905b28c9896472d74b51a2f16cab77b..2606a1859b80dcf24e64036dd88b1be09636b59c 100644 (file)
--- a/tdctemplate/config_32_sfp_kel.vhd
+++ b/tdctemplate/config_32_sfp_kel.vhd
@@ -16,6 +16,8 @@ package config is
   -- 0: 32 Pin AddOn
   -- 1: 4conn AddOn
   -- 2: 2x KEL on board
+  -- 3: ADA AddOn (plus test on KEL)
+  -- 4: every fourth channel on ADA
   
   constant PINOUT   : integer := 2;
 
@@ -33,11 +35,12 @@ package config is
   constant TDC_DATA_FORMAT         : integer := 0;                                                                  
 
   constant EVENT_BUFFER_SIZE       : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
-  constant EVENT_MAX_SIZE          : integer := 4095;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
+  constant EVENT_MAX_SIZE          : integer := 1000;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
 
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
     constant USE_200MHZOSCILLATOR   : integer := c_YES;
+    constant USE_CALIBRATION_200MHZ : integer := c_YES;
     constant USE_EXTERNAL_CLOCK     : integer := c_YES; --'no' not implemented.
     constant CLOCK_FAST_SELECT      : integer := c_NO; --fast clock select (135us) or slow (280ms)?
     
@@ -63,6 +66,12 @@ package config is
     constant TRIG_GEN_OUTPUT_NUM    : integer  := 4;
     constant MONITOR_INPUT_NUM      : integer  := 36;    
    
+    --trigger generation only on 'fast' channels from Padiwa
+    constant TRIG_GEN_FAST_CHANNELS : integer := c_NO;   
+   
+    constant USE_GBE                : integer := c_YES;
+    
+    
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
@@ -100,6 +109,7 @@ package config is
     constant CLOCK_FREQUENCY      : integer;
     constant MEDIA_FREQUENCY      : integer;
     constant INCLUDED_FEATURES      : std_logic_vector(63 downto 0);
+    constant BROADCAST_BITMASK      : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1');    
     
     
 end;
@@ -131,6 +141,7 @@ function generateIncludedFeatures return std_logic_vector is
     t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
     t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
     t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+    t(45 downto 45) := std_logic_vector(to_unsigned(USE_GBE,1));
     t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
     t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
     t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));

diff --git a/tdctemplate/config_32_sfp_kel_cal200.vhd b/tdctemplate/config_32_sfp_kel_cal200.vhd
index 32d1b8fc31eda030823511dbc42be42815710730..8aedc371bed7b84f72c41e22e153af5a035cc730 100644 (file)
--- a/tdctemplate/config_32_sfp_kel_cal200.vhd
+++ b/tdctemplate/config_32_sfp_kel_cal200.vhd
@@ -16,6 +16,8 @@ package config is
   -- 0: 32 Pin AddOn
   -- 1: 4conn AddOn
   -- 2: 2x KEL on board
+  -- 3: ADA AddOn (plus test on KEL)
+  -- 4: every fourth channel on ADA
   
   constant PINOUT   : integer := 2;
 
@@ -65,7 +67,11 @@ package config is
     constant MONITOR_INPUT_NUM      : integer  := 36;
     
     --trigger generation only on 'fast' channels from Padiwa
-    constant TRIG_GEN_FAST_CHANNELS : integer := c_NO;   
+    constant TRIG_GEN_FAST_CHANNELS : integer := c_NO;  
+   
+    constant USE_GBE                : integer := c_NO;
+        
+       
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
@@ -103,6 +109,7 @@ package config is
     constant CLOCK_FREQUENCY      : integer;
     constant MEDIA_FREQUENCY      : integer;
     constant INCLUDED_FEATURES      : std_logic_vector(63 downto 0);
+    constant BROADCAST_BITMASK      : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1');    
     
     
 end;
@@ -134,6 +141,7 @@ function generateIncludedFeatures return std_logic_vector is
     t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
     t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
     t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+    t(45 downto 45) := std_logic_vector(to_unsigned(USE_GBE,1));
     t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
     t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
     t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));

diff --git a/tdctemplate/config_48_crate_4conn.vhd b/tdctemplate/config_48_crate_4conn.vhd
index c0230f12696639795b9b901330ff818801fc0df2..048a79ab03437499c0cc6bfba03b3c54441ad614 100644 (file)
--- a/tdctemplate/config_48_crate_4conn.vhd
+++ b/tdctemplate/config_48_crate_4conn.vhd
@@ -16,6 +16,8 @@ package config is
   -- 0: 32 Pin AddOn
   -- 1: 4conn AddOn
   -- 2: 2x KEL on board
+  -- 3: ADA AddOn (plus test on KEL)
+  -- 4: every fourth channel on ADA
   
   constant PINOUT   : integer := 1;
 
@@ -65,7 +67,11 @@ package config is
     constant MONITOR_INPUT_NUM      : integer  := 52;    
    
     --trigger generation only on 'fast' channels from Padiwa
-    constant TRIG_GEN_FAST_CHANNELS : integer := c_NO;
+    constant TRIG_GEN_FAST_CHANNELS : integer := c_NO;  
+   
+    constant USE_GBE                : integer := c_NO;
+        
+    
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
@@ -103,6 +109,7 @@ package config is
     constant CLOCK_FREQUENCY      : integer;
     constant MEDIA_FREQUENCY      : integer;
     constant INCLUDED_FEATURES      : std_logic_vector(63 downto 0);
+    constant BROADCAST_BITMASK      : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1');    
     
     
 end;
@@ -134,6 +141,7 @@ function generateIncludedFeatures return std_logic_vector is
     t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
     t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
     t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+    t(45 downto 45) := std_logic_vector(to_unsigned(USE_GBE,1));
     t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
     t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
     t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));

diff --git a/tdctemplate/config_48_crate_4conn_cal200.vhd b/tdctemplate/config_48_crate_4conn_cal200.vhd
index fbb6598ab1d85dca85151dad43808871a5c0be88..38047bdc4f1167dbb9b472b7a28a997834655575 100644 (file)
--- a/tdctemplate/config_48_crate_4conn_cal200.vhd
+++ b/tdctemplate/config_48_crate_4conn_cal200.vhd
@@ -16,6 +16,8 @@ package config is
   -- 0: 32 Pin AddOn
   -- 1: 4conn AddOn
   -- 2: 2x KEL on board
+  -- 3: ADA AddOn (plus test on KEL)
+  -- 4: every fourth channel on ADA
   
   constant PINOUT   : integer := 1;
 
@@ -65,7 +67,11 @@ package config is
     constant MONITOR_INPUT_NUM      : integer  := 36;
     
     --trigger generation only on 'fast' channels from Padiwa
-    constant TRIG_GEN_FAST_CHANNELS : integer := c_NO;   
+    constant TRIG_GEN_FAST_CHANNELS : integer := c_NO;  
+   
+    constant USE_GBE                : integer := c_NO;
+        
+       
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
@@ -103,6 +109,7 @@ package config is
     constant CLOCK_FREQUENCY      : integer;
     constant MEDIA_FREQUENCY      : integer;
     constant INCLUDED_FEATURES      : std_logic_vector(63 downto 0);
+    constant BROADCAST_BITMASK      : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1');    
     
     
 end;
@@ -134,6 +141,7 @@ function generateIncludedFeatures return std_logic_vector is
     t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
     t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
     t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+    t(45 downto 45) := std_logic_vector(to_unsigned(USE_GBE,1));
     t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
     t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
     t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));

diff --git a/tdctemplate/config_48_crate_4conn_ecal.vhd b/tdctemplate/config_48_crate_4conn_ecal.vhd
index f69f9ec6ef6bc068912b7f44325f60653d1b6669..e5749f72a791bd989e6bdf51554840822d0ea668 100644 (file)
--- a/tdctemplate/config_48_crate_4conn_ecal.vhd
+++ b/tdctemplate/config_48_crate_4conn_ecal.vhd
@@ -16,6 +16,8 @@ package config is
   -- 0: 32 Pin AddOn
   -- 1: 4conn AddOn
   -- 2: 2x KEL on board
+  -- 3: ADA AddOn (plus test on KEL)
+  -- 4: every fourth channel on ADA
   
   constant PINOUT   : integer := 1;
 
@@ -65,7 +67,11 @@ package config is
     constant MONITOR_INPUT_NUM      : integer  := 52;    
    
     --trigger generation only on 'fast' channels from Padiwa
-    constant TRIG_GEN_FAST_CHANNELS : integer := c_YES;
+    constant TRIG_GEN_FAST_CHANNELS : integer := c_YES;  
+   
+    constant USE_GBE                : integer := c_NO;
+        
+    
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
@@ -103,6 +109,7 @@ package config is
     constant CLOCK_FREQUENCY      : integer;
     constant MEDIA_FREQUENCY      : integer;
     constant INCLUDED_FEATURES      : std_logic_vector(63 downto 0);
+    constant BROADCAST_BITMASK      : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1');    
     
     
 end;
@@ -134,6 +141,7 @@ function generateIncludedFeatures return std_logic_vector is
     t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
     t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
     t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+    t(45 downto 45) := std_logic_vector(to_unsigned(USE_GBE,1));
     t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
     t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
     t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));

diff --git a/tdctemplate/config_48_crate_ada_rpc_cal200.vhd b/tdctemplate/config_48_crate_ada_rpc_cal200.vhd
index 5502e46eba50e568ca561ad9047f8201f1d540c7..2c37a21d5c5ec1189f8e41ca84b2e8ae42aa7cca 100644 (file)
--- a/tdctemplate/config_48_crate_ada_rpc_cal200.vhd
+++ b/tdctemplate/config_48_crate_ada_rpc_cal200.vhd
@@ -67,8 +67,10 @@ package config is
     constant MONITOR_INPUT_NUM      : integer  := 52;
     
     --trigger generation only on 'fast' channels from Padiwa
-    constant TRIG_GEN_FAST_CHANNELS : integer := c_NO;   
-    
+    constant TRIG_GEN_FAST_CHANNELS : integer := c_NO;  
+   
+    constant USE_GBE                : integer := c_NO;
+        
     
 ------------------------------------------------------------------------------
 --End of design configuration
@@ -107,6 +109,7 @@ package config is
     constant CLOCK_FREQUENCY      : integer;
     constant MEDIA_FREQUENCY      : integer;
     constant INCLUDED_FEATURES      : std_logic_vector(63 downto 0);
+    constant BROADCAST_BITMASK      : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1');    
     
     
 end;
@@ -138,6 +141,7 @@ function generateIncludedFeatures return std_logic_vector is
     t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
     t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
     t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+    t(45 downto 45) := std_logic_vector(to_unsigned(USE_GBE,1));
     t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
     t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
     t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));

diff --git a/tdctemplate/config_48_sfp_4conn.vhd b/tdctemplate/config_48_sfp_4conn.vhd
index 053713901bb981731202e7f444db7645ab3955ab..61b2843fe1bb9bbfb45bdc2a6084b17d5722a996 100644 (file)
--- a/tdctemplate/config_48_sfp_4conn.vhd
+++ b/tdctemplate/config_48_sfp_4conn.vhd
@@ -69,6 +69,9 @@ package config is
     --trigger generation only on 'fast' channels from Padiwa
     constant TRIG_GEN_FAST_CHANNELS : integer := c_NO;   
    
+    constant USE_GBE                : integer := c_NO;
+        
+   
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
@@ -106,6 +109,7 @@ package config is
     constant CLOCK_FREQUENCY      : integer;
     constant MEDIA_FREQUENCY      : integer;
     constant INCLUDED_FEATURES      : std_logic_vector(63 downto 0);
+    constant BROADCAST_BITMASK      : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1');    
     
     
 end;
@@ -137,6 +141,7 @@ function generateIncludedFeatures return std_logic_vector is
     t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
     t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
     t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+    t(45 downto 45) := std_logic_vector(to_unsigned(USE_GBE,1));
     t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
     t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
     t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));