add option to remove data output from CTS to save memory blocks in stand-alone designs

diff --git a/special/handler_data.vhd b/special/handler_data.vhd
index 1e578cda48cfd200391e7b36d684c96ee17f26f2..830e5bfe83255ad88bdb25f8adf92c89955ddc5f 100644 (file)
--- a/special/handler_data.vhd
+++ b/special/handler_data.vhd
@@ -15,7 +15,8 @@ entity handler_data is
     DATA_BUFFER_FULL_THRESH      : integer range 0 to 2**15-1    := 2**12-256;
     TRG_RELEASE_AFTER_DATA       : integer range 0 to 1          := c_YES;
     HEADER_BUFFER_DEPTH          : integer range 8 to 15         := 9;
-    HEADER_BUFFER_FULL_THRESH    : integer range 0 to 2**15-1    := 2**9-128
+    HEADER_BUFFER_FULL_THRESH    : integer range 0 to 2**15-1    := 2**9-128;
+    RDO_SKIP_FIRST_BUFFER        : integer range 0 to 1          := c_NO    
     );
   port(
     CLOCK                        : in  std_logic;
@@ -202,7 +203,7 @@ begin
 ---------------------------------------------------------------------------
 -- Data Fifo(s)
 ---------------------------------------------------------------------------
-  gen_fifos : for i in 0 to DATA_INTERFACE_NUMBER-1 generate
+  gen_fifos : for i in RDO_SKIP_FIRST_BUFFER to DATA_INTERFACE_NUMBER-1 generate
 
     data_buffer_write(i)         <= FEE_DATA_WRITE_IN(i) and not fee_write_overflow(i) and not BUFFER_DISABLE_IN(i) when current_buffer_state(i) = BUSY else '0';
 
@@ -236,7 +237,21 @@ begin
         
   end generate;
 
-
+  gen_skip_first : if RDO_SKIP_FIRST_BUFFER = 1 generate
+    data_buffer_data_out(35 downto 0) <= (others => '0');
+    data_buffer_filllevel(DATA_BUFFER_DEPTH downto 0)  <= (others => '0');
+    data_buffer_empty(0) <= '1';
+    data_buffer_full(0) <= '0';
+    data_buffer_almost_full(0) <= '0';
+    fee_write_overflow(0) <= '0';
+    
+    length_buffer_almost_full(0) <= '0';
+    length_buffer_full(0) <= '0';
+    length_buffer_data_out(17 downto 0) <= (others => '0');
+    length_buffer_empty(0) <= '0';
+    IPU_DATA_LENGTH_OUT(15 downto 0) <= (others => '0');
+  end generate;
+  
 ---------------------------------------------------------------------------
 -- Header Fifo
 ---------------------------------------------------------------------------
@@ -265,7 +280,7 @@ begin
 ---------------------------------------------------------------------------
 -- Length FIFO
 ---------------------------------------------------------------------------
-  gen_length_fifo : for i in 0 to DATA_INTERFACE_NUMBER-1 generate
+  gen_length_fifo : for i in RDO_SKIP_FIRST_BUFFER to DATA_INTERFACE_NUMBER-1 generate
     THE_LENGTH_FIFO : fifo_var_oreg
       generic map(
         FIFO_WIDTH               => 18,

diff --git a/special/handler_trigger_and_data.vhd b/special/handler_trigger_and_data.vhd
index 74cda930b0a9bab2fadb5185b94feeb4c1ebcc64..4c401b9a3661ed74caef818c932f6a3d4cefd500 100644 (file)
--- a/special/handler_trigger_and_data.vhd
+++ b/special/handler_trigger_and_data.vhd
@@ -15,7 +15,8 @@ entity handler_trigger_and_data is
     TRG_RELEASE_AFTER_DATA       : integer range 0 to 1          := c_YES;
     DATA_0_IS_STATUS             : integer range 0 to 1          := c_NO;
     HEADER_BUFFER_DEPTH          : integer range 9 to 14         := 9;
-    HEADER_BUFFER_FULL_THRESH    : integer range 2**8 to 2**14-1 := 2**8
+    HEADER_BUFFER_FULL_THRESH    : integer range 2**8 to 2**14-1 := 2**8;
+    RDO_SKIP_FIRST_BUFFER        : integer range 0 to 1 := c_NO
     );
   port(
     CLOCK                        : in  std_logic;
@@ -165,7 +166,8 @@ begin
       DATA_BUFFER_FULL_THRESH      => DATA_BUFFER_FULL_THRESH,
       TRG_RELEASE_AFTER_DATA       => TRG_RELEASE_AFTER_DATA,
       HEADER_BUFFER_DEPTH          => HEADER_BUFFER_DEPTH,
-      HEADER_BUFFER_FULL_THRESH    => HEADER_BUFFER_FULL_THRESH
+      HEADER_BUFFER_FULL_THRESH    => HEADER_BUFFER_FULL_THRESH,
+      RDO_SKIP_FIRST_BUFFER        => RDO_SKIP_FIRST_BUFFER
       )
     port map(
       CLOCK                        => CLOCK,

diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd
index 4c533b42167434717aa51a2d15bf76347474318f..9499c8442fc51d859bd60c3630f6e50024a8dbb7 100644 (file)
--- a/trb_net16_hub_func.vhd
+++ b/trb_net16_hub_func.vhd
@@ -517,6 +517,7 @@ component trb_net16_hub_streaming_port_sctrl_cts is
     RDO_DATA_BUFFER_FULL_THRESH      : integer range 0 to 2**14-2    := 384;
     RDO_HEADER_BUFFER_DEPTH          : integer range 9 to 14         := 9;
     RDO_HEADER_BUFFER_FULL_THRESH    : integer range 2**8 to 2**14-2 := 500;
+    RDO_SKIP_FIRST_BUFFER            : integer range 0 to 1 := c_NO;
     --media interfaces & hub ports
     MII_NUMBER              : integer range 1 to c_MAX_MII_PER_HUB := 5;
     MII_IS_UPLINK           : hub_mii_config_t := (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0);

diff --git a/trb_net16_hub_streaming_port_sctrl_cts.vhd b/trb_net16_hub_streaming_port_sctrl_cts.vhd
index 49c0fb6968ad266fbb60fe15bf5d2079d3a6e2b9..c648a3c2983c173a3e526fa1c9174e35214fc5a5 100644 (file)
--- a/trb_net16_hub_streaming_port_sctrl_cts.vhd
+++ b/trb_net16_hub_streaming_port_sctrl_cts.vhd
@@ -63,6 +63,7 @@ entity trb_net16_hub_streaming_port_sctrl_cts is
     RDO_DATA_BUFFER_FULL_THRESH      : integer range 0 to 2**14-2    := 2**8;
     RDO_HEADER_BUFFER_DEPTH          : integer range 9 to 14         := 9;
     RDO_HEADER_BUFFER_FULL_THRESH    : integer range 2**8 to 2**14-2 := 2**8;
+    RDO_SKIP_FIRST_BUFFER   : integer range 0 to 1 := c_NO;
     --media interfaces & hub ports
     MII_NUMBER              : integer range 1 to c_MAX_MII_PER_HUB := 5;
     MII_IS_UPLINK           : hub_mii_config_t := (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0);
@@ -894,7 +895,8 @@ info_tx_ack_or_info_tx_wack <= info_tx.ack or info_tx.wack;
       DATA_BUFFER_FULL_THRESH    => RDO_DATA_BUFFER_FULL_THRESH,
       TRG_RELEASE_AFTER_DATA     => c_YES,
       HEADER_BUFFER_DEPTH        => RDO_HEADER_BUFFER_DEPTH,
-      HEADER_BUFFER_FULL_THRESH  => RDO_HEADER_BUFFER_FULL_THRESH
+      HEADER_BUFFER_FULL_THRESH  => RDO_HEADER_BUFFER_FULL_THRESH,
+      RDO_SKIP_FIRST_BUFFER      => RDO_SKIP_FIRST_BUFFER
       )
     port map(
       CLOCK                      => CLK,

diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index 2c35780f538ea554d32887ad74b3eb6d040ece6a..071ccd23fc205ac954481aefd1bd4dbe532ada7b 100644 (file)
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -43,6 +43,7 @@ component  gbe_wrapper is
                UP_DOWN_MODE              : integer range 0 to 1         := 0;\r
                UP_DOWN_LIMIT             : integer range 0 to 16777215  := 0;\r
                FIXED_DELAY               : integer range 0 to 16777215  := 16777215;\r
+               SLOWCTRL_BUFFER_SIZE      : integer range 1 to 2         := 2;\r
                NUMBER_OF_GBE_LINKS       : integer range 1 to 4         := 4;\r
                LINKS_ACTIVE              : std_logic_vector(3 downto 0) := "1111";\r
                LINK_HAS_PING             : std_logic_vector(3 downto 0) := "1111";\r
@@ -1383,7 +1384,8 @@ end component;
       DATA_BUFFER_FULL_THRESH   : integer range 0 to 2**14-1    := 2**8;\r
       TRG_RELEASE_AFTER_DATA    : integer range 0 to 1          := c_YES;\r
       HEADER_BUFFER_DEPTH       : integer range 9 to 14         := 9;\r
-      HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8\r
+      HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8;\r
+      RDO_SKIP_FIRST_BUFFER     : integer range 0 to 1 := c_NO      \r
       );\r
     port(\r
       CLOCK : in std_logic;\r
@@ -1535,7 +1537,8 @@ end component;
       DATA_BUFFER_FULL_THRESH   : integer range 0 to 2**15-1    := 2**8;\r
       TRG_RELEASE_AFTER_DATA    : integer range 0 to 1          := c_YES;\r
       HEADER_BUFFER_DEPTH       : integer range 9 to 14         := 9;\r
-      HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8\r
+      HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8;\r
+      RDO_SKIP_FIRST_BUFFER     : integer range 0 to 1 := c_NO\r
       );\r
     port(\r
       CLOCK     : in std_logic;\r