+++ /dev/null
-#!/usr/bin/perl
-use Data::Dumper;
-use warnings;
-use strict;
-
-
-
-
-###################################################################################
-#Settings for this project
-my $TOPNAME = "padiwa_amps"; #Name of top-level entity
-my $lattice_path = '/d/jspc29/lattice/diamond/2.2_x64';
-my $synplify_path = '/d/jspc29/lattice/synplify/G-2012.09-SP1/';
-my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
-my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
-###################################################################################
-
-
-$ENV{'PAR_DESIGN_NAME'}=$TOPNAME;
-
-#
-# set_option -technology MACHXO2
-# set_option -part LCMXO2_4000HC
-# set_option -package FTG256C
-# set_option -speed_grade -6
-# set_option -part_companion ""
-
-
-
-use FileHandle;
-
-$ENV{'SYNPLIFY'}=$synplify_path;
-$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
-
-
-
-
-my $FAMILYNAME="MACHXO2";
-my $DEVICENAME="LCMXO2-4000HC";
-my $PACKAGE="FTBGA256";
-my $SPEEDGRADE="6";
-
-# create workdir with
-# symlink for Lattice internal VHDL files
-my $WORKDIR = "workdir";
-unless(-d $WORKDIR) {
- mkdir $WORKDIR or die "can't create workdir '$WORKDIR': $!";
-}
-system("ln -sfT $lattice_path $WORKDIR/lattice-diamond");
-
-
-#create full lpf file
-system("cp ../base/".$TOPNAME.".lpf $WORKDIR/$TOPNAME.lpf");
-system("cat ".$TOPNAME."_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
-
-
-#set -e
-#set -o errexit
-
-#generate timestamp
-my $t=time;
-my $fh = new FileHandle(">version.vhd");
-die "could not open file" if (! defined $fh);
-print $fh <<EOF;
-
---## attention, automatically generated. Don't change by hand.
-library ieee;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use ieee.numeric_std.all;
-
-package version is
-
- constant VERSION_NUMBER_TIME : integer := $t;
-
-end package version;
-EOF
-$fh->close;
-
-system("env| grep LM_");
-my $r = "";
-
-my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
-$r=execute($c, "do_not_exit" );
-
-
-chdir $WORKDIR;
-$fh = new FileHandle("<$TOPNAME".".srr");
-my @a = <$fh>;
-$fh -> close;
-
-
-
-foreach (@a)
-{
- if(/\@E:/)
- {
- print "\n";
- $c="cat $TOPNAME.srr | grep \"\@E\"";
- system($c);
- print "\n\n";
- exit 129;
- }
-}
-
-
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
-
-
-$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
-execute($c);
-
-my $tpmap = $TOPNAME . "_map" ;
-
-$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
-execute($c);
-
-system("rm $TOPNAME.ncd");
-
-#$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|;
-# $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
-$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|;
-execute($c);
-# IOR IO Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-# TWR Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-# $c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
-# execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -jedec $TOPNAME.ncd $TOPNAME.jed $TOPNAME.prf|;
-# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-chdir "..";
-
-exit;
-
-sub execute {
- my ($c, $op) = @_;
- #print "option: $op \n";
- $op = "" if(!$op);
- print "\n\ncommand to execute: $c \n";
- $r=system($c);
- if($r) {
- print "$!";
- if($op ne "do_not_exit") {
- exit;
- }
- }
-
- return $r;
-
-}
+++ /dev/null
-#!/usr/bin/perl
-use Data::Dumper;
-use warnings;
-use strict;
-use FileHandle;
-
-
-
-
-###################################################################################
-#Settings for this project
-my $TOPNAME = "padiwa_amps"; #Name of top-level entity
-my $lattice_path = '/opt/lattice/diamond/2.2_x64';
-my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed
-my $synplify_path = '/opt/synplicity/F-2012.03-SP1';
-my $lm_license_file_for_synplify = '27000@lxcad01.gsi.de';
-my $lm_license_file_for_par = '1702@hadeb05.gsi.de';
-###################################################################################
-
-
-
-# source the standard lattice environment
-$ENV{bindir}="$lattice_bin_path";
-open my $SOURCE, "bash -c '. $lattice_bin_path/diamond_env >& /dev/null; env'|" or
- die "Can't fork: $!";
-while (<$SOURCE>) {
- if (/^(.*)=(.*)/) {
- $ENV{$1} = ${2} ;
- }
-}
-close $SOURCE;
-
-
-$ENV{'PAR_DESIGN_NAME'}=$TOPNAME;
-
-#
-# set_option -technology MACHXO2
-# set_option -part LCMXO2_4000HC
-# set_option -package FTG256C
-# set_option -speed_grade -6
-# set_option -part_companion ""
-
-$ENV{'SYNPLIFY'}=$synplify_path;
-$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
-
-
-
-
-my $FAMILYNAME="MACHXO2";
-my $DEVICENAME="LCMXO2-4000HC";
-my $PACKAGE="FTBGA256";
-my $SPEEDGRADE="6";
-
-my $WORKDIR = "workdir";
-unless(-d $WORKDIR) {
- mkdir $WORKDIR or die "can't create workdir '$WORKDIR': $!";
-}
-
-system("ln -sfT $lattice_path $WORKDIR/lattice-diamond");
-
-#create full lpf file
-system("cp ../base/".$TOPNAME.".lpf $WORKDIR/$TOPNAME.lpf");
-system("cat ".$TOPNAME."_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
-
-
-#set -e
-#set -o errexit
-
-#generate timestamp
-my $t=time;
-my $fh = new FileHandle(">version.vhd");
-die "could not open file" if (! defined $fh);
-print $fh <<EOF;
-
---## attention, automatically generated. Don't change by hand.
-library ieee;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use ieee.numeric_std.all;
-
-package version is
-
- constant VERSION_NUMBER_TIME : integer := $t;
-
-end package version;
-EOF
-$fh->close;
-
-system("env| grep LM_");
-my $r = "";
-
-my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
-$r=execute($c, "do_not_exit" );
-
-
-chdir $WORKDIR;
-$fh = new FileHandle("<$TOPNAME".".srr");
-my @a = <$fh>;
-$fh -> close;
-
-
-
-foreach (@a)
-{
- if(/\@E:/)
- {
- print "\n";
- $c="cat $TOPNAME.srr | grep \"\@E\"";
- system($c);
- print "\n\n";
- exit 129;
- }
-}
-
-
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
-
-
-$c=qq| edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
-execute($c);
-
-$c=qq|edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
-execute($c);
-
-$c=qq|ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
-execute($c);
-
-my $tpmap = $TOPNAME . "_map" ;
-
-$c=qq|map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
-execute($c);
-
-system("rm $TOPNAME.ncd");
-
-#$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|;
-# $c=qq|multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
-$c=qq|par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|;
-execute($c);
-
-# IOR IO Timing Report
-$c=qq|iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-# TWR Timing Report
-$c=qq|trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-$c=qq|trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-# $c=qq|ltxt2ptxt $TOPNAME.ncd|;
-# execute($c);
-
-$c=qq|bitgen -w -g CfgMode:Disable -g RamCfg:Reset -jedec $TOPNAME.ncd $TOPNAME.jed $TOPNAME.prf|;
-# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-chdir "..";
-
-exit;
-
-sub execute {
- my ($c, $op) = @_;
- #print "option: $op \n";
- $op = "" if(!$op);
- print "\n\ncommand to execute: $c \n";
- $r=system($c);
- if($r) {
- print "$!";
- if($op ne "do_not_exit") {
- exit;
- }
- }
-
- return $r;
-
-}
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="1.3" title="padiwa_amps" device="LCMXO2-4000HC-6FTG256C" default_implementation="padiwa_amps">
- <Options/>
- <Implementation title="padiwa_amps" dir="padiwa_amps" description="padiwa_amps" default_strategy="Strategy1">
- <Options top="padiwa_amps"/>
- <Source name="padiwa_amps.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="padiwa_amps"/>
- </Source>
- <Source name="../base/trb3_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../wasa/source/spi_slave.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="version.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../wasa/cores/oddr16.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../wasa/source/pwm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../wasa/cores/efb_define_def.v" type="Verilog" type_short="Verilog">
- <Options/>
- </Source>
- <Source name="../wasa/cores/UFM_WB_top.v" type="Verilog" type_short="Verilog">
- <Options/>
- </Source>
- <Source name="../wasa/cores/pll.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../wasa/cores/flashram.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../wasa/cores/flash.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../base/padiwa_amps.lpf" type="Logic Preference" type_short="LPF">
- <Options/>
- </Source>
- </Implementation>
- <Strategy name="Strategy1" file="Strategy1.sty"/>
-</BaliProject>
+++ /dev/null
--w
--i 15
--l 5
--n 1
--y
--s 1
--t 11
--c 1
--e 2
--m nodelist.txt
-# -w
-# -i 6
-# -l 5
-# -n 1
-# -t 1
-# -s 1
-# -c 0
-# -e 0
-#
--exp parCDP=0:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
+++ /dev/null
-#-- Synopsys, Inc.
-#-- Version F-2012.03-SP1
-#-- Project file /d/jspc22/trb/cvs/trb3/wasa/panda_dirc_wasa/panda_dirc_wasa_syn.prj
-#-- Written on Mon Aug 6 18:53:10 2012
-
-
-
-#project files
-add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/machxo2.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../base/trb3_components.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib work "../wasa/source/spi_slave.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "../wasa/source/pwm.vhd"
-add_file -vhdl -lib work "../wasa/cores/pll_shifted_clocks.vhd"
-add_file -vhdl -lib work "../wasa/cores/fifo_1kx8.vhd"
-add_file -vhdl -lib work "../wasa/source/ffarray.vhd"
-
-
-add_file -vhdl -lib work "../wasa/cores/oddr16.vhd"
-add_file -vhdl -lib work "../wasa/cores/flash.vhd"
-add_file -vhdl -lib work "../wasa/cores/flashram.vhd"
-add_file -vhdl -lib work "../wasa/cores/pll.vhd"
-add_file -verilog -lib work "../wasa/cores/efb_define_def.v"
-add_file -verilog -lib work "../wasa/cores/UFM_WB.v"
-
-
-add_file -vhdl -lib work "padiwa_amps.vhd"
-
-
-#implementation: "padiwa_amps"
-impl -add workdir -type fpga
-
-#
-#implementation attributes
-
-set_option -vlog_std sysv
-set_option -project_relative_includes 1
-
-#device options
-set_option -technology MACHXO2
-set_option -part LCMXO2_4000HC
-set_option -package FTG256C
-set_option -speed_grade -6
-set_option -part_companion ""
-
-#compilation/mapping options
-
-# mapper_options
-set_option -frequency auto
-set_option -write_verilog 0
-set_option -write_vhdl 0
-
-# Lattice XP
-set_option -maxfan 1000
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 1
-set_option -forcegsr no
-set_option -fixgatedclocks 3
-set_option -fixgeneratedclocks 3
-set_option -update_models_cp 0
-
-# NFilter
-set_option -popfeed 0
-set_option -constprop 0
-set_option -createhierarchy 0
-
-# sequential_optimization_options
-set_option -symbolic_fsm_compiler 1
-
-# Compiler Options
-set_option -compiler_compatible 0
-set_option -resource_sharing 1
-set_option -multi_file_compilation_unit 1
-set_option -top_module "padiwa_amps"
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "workdir/padiwa_amps.edf"
-impl -active "workdir"
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb3_components.all;
-use work.version.all;
-
-library machxo2;
-use machxo2.all;
-
-
-entity padiwa_amps is
- generic(
- TEMP_CORRECTION: integer := c_YES
- );
- port(
- CON : out std_logic_vector(16 downto 1);
- INP : in std_logic_vector(16 downto 1);
- PWM : out std_logic_vector(16 downto 1);
- DISCHARGE : out std_logic_vector( 8 downto 1);
-
- DELAY_C_IN : in std_logic_vector( 8 downto 1);
- DELAY_R_IN : in std_logic_vector( 6 downto 1);
- DELAY_L_IN : in std_logic_vector( 5 downto 1);
- DELAY_B_IN : in std_logic_vector( 5 downto 1);
- DELAY_C_OUT : out std_logic_vector( 8 downto 1);
- DELAY_R_OUT : out std_logic_vector( 6 downto 1);
- DELAY_L_OUT : out std_logic_vector( 5 downto 1);
- DELAY_B_OUT : out std_logic_vector( 5 downto 1);
-
- SPARE_LVDS : out std_logic;
- LED : out std_logic_vector( 8 downto 1);
-
- SPI_CLK : in std_logic;
- SPI_CS : in std_logic;
- SPI_IN : in std_logic;
- SPI_OUT : out std_logic;
- TEMP_LINE : inout std_logic;
- TEST_LINE : out std_logic_vector(13 downto 0)
- );
-end entity;
-
-
-
-
-
-
-architecture padiwa_amps_arch of padiwa_amps is
-
-component OSCH
--- synthesis translate_off
- generic (NOM_FREQ: string := "133.00");
--- synthesis translate_on
- port (
- STDBY :IN std_logic;
- OSC :OUT std_logic;
- SEDSTDBY :OUT std_logic
- );
-end component;
-
-component oddr16 is
- port (
- clk: in std_logic;
- clkout: out std_logic;
- reset: in std_logic;
- sclk: out std_logic;
- dataout: in std_logic_vector(31 downto 0);
- dout: out std_logic_vector(15 downto 0));
-end component;
-
-component spi_slave
- port(
- CLK : in std_logic;
- SPI_CLK : in std_logic;
- SPI_CS : in std_logic;
- SPI_IN : in std_logic;
- SPI_OUT : out std_logic;
-
- DATA_OUT : out std_logic_vector(15 downto 0);
- REG00_IN : in std_logic_vector(15 downto 0);
- REG10_IN : in std_logic_vector(15 downto 0);
- REG20_IN : in std_logic_vector(15 downto 0);
- REG40_IN : in std_logic_vector(15 downto 0);
-
- OPERATION_OUT : out std_logic_vector(3 downto 0);
- CHANNEL_OUT : out std_logic_vector(7 downto 0);
- WRITE_OUT : out std_logic_vector(15 downto 0);
-
- DEBUG_OUT : out std_logic_vector(15 downto 0)
- );
-end component;
-
-
-component pwm_generator
- port(
- CLK : in std_logic;
- DATA_IN : in std_logic_vector(15 downto 0);
- DATA_OUT : out std_logic_vector(15 downto 0);
- COMP_IN : in signed(15 downto 0);
- WRITE_IN : in std_logic;
- ADDR_IN : in std_logic_vector(3 downto 0);
- PWM : out std_logic_vector(31 downto 0)
- );
-end component;
-
-component flashram
- port (
- DataInA: in std_logic_vector(7 downto 0);
- DataInB: in std_logic_vector(7 downto 0);
- AddressA: in std_logic_vector(3 downto 0);
- AddressB: in std_logic_vector(3 downto 0);
- ClockA: in std_logic;
- ClockB: in std_logic;
- ClockEnA: in std_logic;
- ClockEnB: in std_logic;
- WrA: in std_logic;
- WrB: in std_logic;
- ResetA: in std_logic;
- ResetB: in std_logic;
- QA: out std_logic_vector(7 downto 0);
- QB: out std_logic_vector(7 downto 0)
- );
-end component;
-
-component pll
- port (
- CLKI: in std_logic;
- CLKOP: out std_logic;
- CLKOS: out std_logic;
- LOCK: out std_logic);
-end component;
-
-
-component UFM_WB
- port(
- clk_i : in std_logic;
- rst_n : in std_logic;
- cmd : in std_logic_vector(2 downto 0);
- ufm_page : in std_logic_vector(12 downto 0);
- GO : in std_logic;
- BUSY : out std_logic;
- ERR : out std_logic;
- mem_clk : out std_logic;
- mem_we : out std_logic;
- mem_ce : out std_logic;
- mem_addr : out std_logic_vector(3 downto 0);
- mem_wr_data : out std_logic_vector(7 downto 0);
- mem_rd_data : in std_logic_vector(7 downto 0)
- );
-end component;
-
-component PUR port(PUR : in std_logic); end component;
-component GSR port(GSR : in std_logic); end component;
-
-
-
-attribute NOM_FREQ : string;
-attribute NOM_FREQ of clk_source : label is "133.00";
-signal clk_i : std_logic;
-
-signal reset_i : std_logic := '1';
-signal reset_cnt : unsigned(3 downto 0) := x"0";
-signal id_data_i : std_logic_vector(15 downto 0);
-signal id_addr_i : std_logic_vector(2 downto 0);
-signal id_write_i: std_logic;
-signal ram_write_i : std_logic;
-signal ram_data_i: std_logic_vector(7 downto 0);
-signal ram_data_o: std_logic_vector(7 downto 0);
-signal ram_addr_i: std_logic_vector(3 downto 0);
-signal temperature_i : std_logic_vector(11 downto 0);
-
-type idram_t is array(0 to 7) of std_logic_vector(15 downto 0);
-signal idram : idram_t;
-type ram_t is array(0 to 15) of std_logic_vector(15 downto 0);
-signal ram : ram_t;
-
-signal pwm_i : std_logic_vector(32 downto 1);
-signal INP_i : std_logic_vector(15 downto 0);
-signal fast_input : std_logic_vector(8 downto 1);
-signal slow_input : std_logic_vector(8 downto 1);
-signal spi_reg00_i : std_logic_vector(15 downto 0);
-signal spi_reg10_i : std_logic_vector(15 downto 0);
-signal spi_reg20_i : std_logic_vector(15 downto 0);
-signal spi_reg40_i : std_logic_vector(15 downto 0);
-signal spi_data_i : std_logic_vector(15 downto 0);
-signal spi_operation_i : std_logic_vector(3 downto 0);
-signal spi_channel_i : std_logic_vector(7 downto 0);
-signal spi_write_i : std_logic_vector(15 downto 0);
-signal buf_SPI_OUT : std_logic;
-signal spi_debug_i : std_logic_vector(15 downto 0);
-signal last_spi_channel: std_logic_vector(7 downto 0);
-
-signal pll_lock : std_logic;
-signal clk_26 : std_logic;
-signal clk_osc : std_logic;
-
-signal flashram_addr_i : std_logic_vector(3 downto 0);
-signal flashram_cen_i : std_logic;
-signal flashram_reset : std_logic;
-signal flashram_write_i: std_logic;
-signal flashram_data_i : std_logic_vector(7 downto 0);
-signal flashram_data_o : std_logic_vector(7 downto 0);
-
-signal flash_command : std_logic_vector(2 downto 0);
-signal flash_page : std_logic_vector(12 downto 0);
-signal flash_go : std_logic;
-signal flash_busy : std_logic;
-signal flash_err : std_logic;
-
-signal inp_select : integer range 0 to 31 := 0;
-signal inp_invert : std_logic_vector(15 downto 0);
-signal input_enable : std_logic_vector(15 downto 0);
-signal inp_status : std_logic_vector(15 downto 0);
-signal led_status : std_logic_vector(8 downto 0) := "100000000";
-signal discharge_disable : std_logic_vector(8 downto 1);
-signal discharge_highz : std_logic_vector(8 downto 1);
-signal discharge_override : std_logic_vector(8 downto 1);
-signal delay_invert : std_logic_vector(8 downto 1);
-
-
-signal timer : unsigned(18 downto 0) := (others => '0');
-signal last_inp : std_logic_vector(15 downto 0) := (others => '0');
-signal leds : std_logic_vector(15 downto 0) := (others => '0');
-signal last_leds: std_logic_vector(15 downto 0) := (others => '0');
-signal onewire_monitor : std_logic;
-signal onewire_reset : std_logic;
-signal inp_or : std_logic;
-signal inp_long_or : std_logic;
-signal inp_long_reg : std_logic;
-signal last_inp_long_reg : std_logic;
-
-signal inp_stretch : std_logic_vector(15 downto 0);
-signal inp_stretched : std_logic_vector(15 downto 0);
-signal inp_hold : std_logic_vector(15 downto 0);
-signal inp_gated : std_logic_vector(15 downto 0);
-signal inp_hold_reg: std_logic_vector(15 downto 0);
-signal last_inp_hold_reg: std_logic_vector(15 downto 0);
-signal flash_go_tmp : std_logic_vector(5 downto 0);
-signal flash_reset_n : std_logic;
-
-signal pwm_data_i : std_logic_vector(15 downto 0);
-signal pwm_data_o : std_logic_vector(15 downto 0);
-signal pwm_write_i : std_logic;
-signal pwm_addr_i : std_logic_vector(3 downto 0);
-type fsm_state is (IDLE, PWM_WRITE_GET_1, PWM_WRITE_GET_2, PWM_WRITE, PWM_WAIT);
-signal fsm_copydat : fsm_state;
-
-signal pwm_fsm_data_i : std_logic_vector(15 downto 0);
-signal pwm_fsm_addr : std_logic_vector(3 downto 0);
-signal pwm_fsm_write : std_logic;
-signal fsm_job : std_logic_vector(1 downto 0);
-signal ram_fsm_data_i : std_logic_vector(7 downto 0);
-signal ram_fsm_addr_i : std_logic_vector(3 downto 0);
-signal ram_fsm_write_i: std_logic;
-
-signal enable_cfg_flash : std_logic;
-signal comp_setting : std_logic_vector(15 downto 0);
-signal compensate_i : signed(15 downto 0);
-signal temp_calc_i : signed(27 downto 0);
-signal temperature_i_s : std_logic_vector(11 downto 0);
-signal comp_setting_s : std_logic_vector(15 downto 0);
-
-signal ffarr_data : std_logic_vector(15 downto 0);
-signal ffarr_read : std_logic;
-
-
-begin
-
-
-THE_PLL : pll
- port map(
- CLKI => clk_osc,
- CLKOP => clk_26, --33
- CLKOS => clk_i, --133
- LOCK => pll_lock --no lock available!
- );
-
----------------------------------------------------------------------------
--- Clock
----------------------------------------------------------------------------
-clk_source: OSCH
--- synthesis translate_off
- generic map ( NOM_FREQ => "133.00" )
--- synthesis translate_on
- port map (
- STDBY => '0',
- OSC => clk_osc,
- SEDSTDBY => open
- );
-
----------------------------------------------------------------------------
--- Input re-ordering
----------------------------------------------------------------------------
-
- INP_i <= INP;
- PWM <= pwm_i(16 downto 1);
-
-
----------------------------------------------------------------------------
--- SPI Interface
----------------------------------------------------------------------------
-THE_SPI_SLAVE : spi_slave
- port map(
- CLK => clk_i,
- SPI_CLK => SPI_CLK,
- SPI_CS => SPI_CS,
- SPI_IN => SPI_IN,
- SPI_OUT => buf_SPI_OUT,
- DATA_OUT => spi_data_i,
- REG00_IN => spi_reg00_i,
- REG10_IN => spi_reg10_i,
- REG20_IN => spi_reg20_i,
- REG40_IN => spi_reg40_i,
- OPERATION_OUT => spi_operation_i,
- CHANNEL_OUT => spi_channel_i,
- WRITE_OUT => spi_write_i,
- DEBUG_OUT => spi_debug_i
- );
-
-SPI_OUT <= buf_SPI_OUT;
-
-spi_reg00_i <= pwm_data_o;
-spi_reg10_i <= idram(to_integer(unsigned(spi_channel_i(2 downto 0))));
-spi_reg40_i <= flash_busy & flash_err & "000000" & ram_data_o;
-
----------------------------------------------------------------------------
--- RAM Interface
----------------------------------------------------------------------------
---CFG-Flash: 0 - 5758
---UFM-Flash: 7167 - 7936
-
-PROC_CTRL_FLASH : process begin
- wait until rising_edge(clk_i);
- if(spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"0") then
- flash_command <= spi_data_i(15 downto 13);
- if(enable_cfg_flash = '1') then
- flash_page <= spi_data_i(12 downto 0);
- else
- flash_page <= "111" & spi_data_i(9 downto 0);
- end if;
- flash_go_tmp(0)<= '1';
- else
- flash_go_tmp(5 downto 0) <= flash_go_tmp(4 downto 0) & '0';
- end if;
- if flash_reset_n = '0' then
- flash_go_tmp <= (others => '0');
- end if;
-end process;
-
-PROC_CTRL_FLASH_ENABLE : process begin
- wait until rising_edge(clk_i);
- if(spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"C") then
- enable_cfg_flash <= spi_data_i(0);
- end if;
-end process;
-
-flash_go <= or_all(flash_go_tmp);
-
-
-THE_FLASH_RAM : flashram
- port map(
- DataInA => ram_data_i,
- DataInB => flashram_data_i,
- AddressA => ram_addr_i,
- AddressB => flashram_addr_i,
- ClockA => clk_i,
- ClockB => clk_26,
- ClockEnA => '1',
- ClockEnB => flashram_cen_i,
- WrA => ram_write_i,
- WrB => flashram_write_i,
- ResetA => '0',
- ResetB => flashram_reset,
- QA => ram_data_o,
- QB => flashram_data_o
- );
-
----------------------------------------------------------------------------
--- Flash Controller
----------------------------------------------------------------------------
-
-THE_FLASH : UFM_WB
- port map(
- clk_i => clk_26,
- rst_n => flash_reset_n,
- cmd => flash_command,
- ufm_page => flash_page,
- GO => flash_go,
- BUSY => flash_busy,
- ERR => flash_err,
- mem_clk => open,
- mem_we => flashram_write_i,
- mem_ce => flashram_cen_i,
- mem_addr => flashram_addr_i,
- mem_wr_data => flashram_data_i,
- mem_rd_data => flashram_data_o
- );
-
-PROC_DATA_COPY : process
- variable count : integer range 0 to 31 := 0;
- variable tmp : std_logic_vector(7 downto 0);
-begin
- wait until rising_edge(clk_i);
- pwm_fsm_write <= '0';
- ram_fsm_write_i <= '0';
- case fsm_copydat is
- when IDLE =>
- count := 0;
- if spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"1" then
- fsm_copydat <= PWM_WRITE_GET_1;
- ram_fsm_addr_i <= std_logic_vector(to_unsigned(count,4));
- fsm_job <= spi_channel_i(1 downto 0);
- count := count + 1;
- end if;
- when PWM_WRITE_GET_1 =>
- ram_fsm_addr_i <= std_logic_vector(to_unsigned(count,4));
- count := count + 1;
- fsm_copydat <= PWM_WRITE_GET_2;
- when PWM_WRITE_GET_2 =>
- fsm_copydat <= PWM_WRITE;
- tmp := ram_data_o;
- when PWM_WRITE =>
- pwm_fsm_data_i <= tmp & ram_data_o;
- pwm_fsm_write <= '1';
- pwm_fsm_addr <= fsm_job(0) & std_logic_vector(to_unsigned(count/2-1,3));
-
- if(count < 15) then
- fsm_copydat <= PWM_WRITE_GET_1;
- else
- fsm_copydat <= PWM_WAIT;
- end if;
-
- ram_fsm_addr_i <= std_logic_vector(to_unsigned(count,4));
- count := count + 1;
-
- when PWM_WAIT =>
- fsm_copydat <= IDLE;
- end case;
- if onewire_reset = '1' then
- fsm_copydat <= IDLE;
- end if;
-end process;
-
----------------------------------------------------------------------------
--- PWM
----------------------------------------------------------------------------
-
-THE_PWM_GEN : pwm_generator
- port map(
- CLK => clk_i,
- DATA_IN => pwm_data_i,
- DATA_OUT => pwm_data_o,
- COMP_IN => compensate_i,
- WRITE_IN => pwm_write_i,
- ADDR_IN => pwm_addr_i,
- PWM => pwm_i
- );
-
-
-
-PROC_PWM_DATA_MUX : process(fsm_copydat, spi_data_i, spi_write_i, spi_channel_i,
- pwm_fsm_addr, pwm_fsm_data_i, pwm_fsm_write,
- ram_fsm_addr_i, ram_fsm_data_i, ram_fsm_write_i)
-begin
- if(fsm_copydat = IDLE) then
- pwm_data_i <= spi_data_i;
- pwm_write_i <= spi_write_i(0);
- pwm_addr_i <= spi_channel_i(3 downto 0);
- ram_write_i <= spi_write_i(4);
- ram_data_i <= spi_data_i(7 downto 0);
- ram_addr_i <= spi_channel_i(3 downto 0);
- else
- pwm_data_i <= pwm_fsm_data_i;
- pwm_write_i <= pwm_fsm_write;
- pwm_addr_i <= pwm_fsm_addr;
- ram_write_i <= ram_fsm_write_i;
- ram_data_i <= ram_fsm_data_i;
- ram_addr_i <= ram_fsm_addr_i;
- end if;
-end process;
-
-
----------------------------------------------------------------------------
--- Temperature Sensor
----------------------------------------------------------------------------
-
-THE_ONEWIRE : trb_net_onewire
- generic map(
- USE_TEMPERATURE_READOUT => 1,
- PARASITIC_MODE => c_NO,
- CLK_PERIOD => 33
- )
- port map(
- CLK => clk_26,
- RESET => onewire_reset,
- READOUT_ENABLE_IN => '1',
- ONEWIRE => TEMP_LINE,
- MONITOR_OUT => onewire_monitor,
- --connection to id ram, according to memory map in TrbNetRegIO
- DATA_OUT => id_data_i,
- ADDR_OUT => id_addr_i,
- WRITE_OUT=> id_write_i,
- TEMP_OUT => temperature_i,
- ID_OUT => open,
- STAT => open
- );
-
-PROC_IDMEM : process begin
- wait until rising_edge(clk_i);
- if id_write_i = '1' then
- idram(to_integer(unsigned(id_addr_i))) <= id_data_i;
- else
- idram(4) <= "0000" & temperature_i;
- end if;
-
- if spi_write_i(1) = '1' then
- onewire_reset <= spi_data_i(0);
- end if;
-end process;
-
-flash_reset_n <= not onewire_reset;
-
----------------------------------------------------------------------------
--- I/O Register 0x20
----------------------------------------------------------------------------
-THE_IO_REG_READ : process begin
- wait until rising_edge(clk_i);
- if spi_channel_i(4) = '0' then
- case spi_channel_i(3 downto 0) is
- when x"0" => spi_reg20_i <= input_enable;
- when x"1" => spi_reg20_i <= inp_status;
- when x"2" => spi_reg20_i <= x"0" & "000" & led_status(8) & leds(14) & leds(12) & leds(10) & leds(8) & leds(6) & leds(4) & leds(2) & leds(0) ;
- when x"3" => spi_reg20_i <= x"00" & "000" & std_logic_vector(to_unsigned(inp_select,5));
- when x"4" => spi_reg20_i <= inp_invert;
- when x"5" => spi_reg20_i <= inp_stretch;
- when x"6" => spi_reg20_i <= comp_setting;
- when x"7" => spi_reg20_i <= x"00" & discharge_disable;
- when x"8" => spi_reg20_i <= x"00" & discharge_override;
- when x"9" => spi_reg20_i <= x"00" & discharge_highz;
- when x"a" => spi_reg20_i <= x"00" & delay_invert;
- when x"f" => spi_reg20_i <= ffarr_data;
- when others => null;
- end case;
- else
- case spi_channel_i(3 downto 0) is
- when x"0" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16));
- when x"1" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));
- when x"2" => spi_reg20_i <= x"0000";
- when others => null;
- end case;
- end if;
-end process;
-
-THE_IO_REG_WRITE : process begin
- wait until rising_edge(clk_i);
- if spi_write_i(2) = '1' then
- case spi_channel_i(3 downto 0) is
- when x"0" => input_enable <= spi_data_i;
- when x"1" => null;
- when x"2" => led_status <= spi_data_i(8 downto 0);
- when x"3" => inp_select <= to_integer(unsigned(spi_data_i(4 downto 0)));
- when x"4" => inp_invert <= spi_data_i;
- when x"5" => inp_stretch <= spi_data_i;
- when x"6" => comp_setting <= spi_data_i;
- when x"7" => discharge_disable <= spi_data_i(7 downto 0);
- when x"8" => discharge_override <= spi_data_i(7 downto 0);
- when x"9" => discharge_highz <= spi_data_i(7 downto 0);
- when x"a" => delay_invert <= spi_data_i(7 downto 0);
- when others => null;
- end case;
- end if;
-end process;
-
-inp_status <= INP_i when rising_edge(clk_i);
-last_inp <= inp_status(15 downto 0) when rising_edge(clk_i);
-
-temperature_i_s <= temperature_i when rising_edge(clk_26);
-comp_setting_s <= comp_setting when rising_edge(clk_26);
-temp_calc_i <= signed(temperature_i_s) * signed(comp_setting_s) when rising_edge(clk_26);
-
-gen_comp: if TEMP_CORRECTION = 1 generate
- compensate_i <= temp_calc_i(27 downto 12) when rising_edge(clk_26);
-end generate;
-gen_no_comp: if TEMP_CORRECTION = 0 generate
- compensate_i <= (others => '0');
-end generate;
-
-
----------------------------------------------------------------------------
--- Delay generation
----------------------------------------------------------------------------
-
-
-gen_discharge : for i in 1 to 8 generate
-DISCHARGE(i) <= 'Z' when discharge_highz(i) = '1' else
- (DELAY_C_IN(i) and slow_input(i)) when discharge_disable(i) = '0' else
- discharge_override(i) when discharge_disable(i) = '1';
-
-DELAY_C_OUT(i) <= (fast_input(i) or slow_input(i)) xor delay_invert(i);
-end generate;
-
-fast_input <= inp_gated(14) & inp_gated(12) & inp_gated(10) & inp_gated(8) & inp_gated(6) & inp_gated(4) & inp_gated(2) & inp_gated(0);
-slow_input <= inp_gated(15) & inp_gated(13) & inp_gated(11) & inp_gated(9) & inp_gated(7) & inp_gated(5) & inp_gated(3) & inp_gated(1);
-
-
----------------------------------------------------------------------------
--- LED blinking when activity on inputs
----------------------------------------------------------------------------
-PROC_TIMER : process begin
- wait until rising_edge(clk_i);
- timer <= timer + 1;
- leds <= (last_inp xor inp_status(15 downto 0)) or leds or last_leds;
- if timer = 0 then
- leds <= not inp_status(15 downto 0);
- last_leds <= x"0000";
- end if;
-end process;
-
-
----------------------------------------------------------------------------
--- Rest of the I/O
----------------------------------------------------------------------------
-
-inp_gated <= (INP_i xor inp_invert) and not input_enable;
-CON <= inp_gated or (inp_stretched and inp_stretch);
-
-
-inp_hold <= (inp_gated or inp_hold) and not inp_hold_reg;
-inp_hold_reg <= inp_hold when rising_edge(clk_i);
-last_inp_hold_reg <= inp_hold_reg when rising_edge(clk_i);
-inp_stretched <= inp_hold_reg or last_inp_hold_reg or inp_hold;
-
-
-
-
-
-SPARE_OUTPUT : process(INP_i, inp_select, inp_or, inp_long_or, inp_long_reg, last_inp_long_reg)
- begin
- if inp_select < 16 then
- SPARE_LVDS <= INP_i(inp_select);
- elsif inp_select < 24 then
- SPARE_LVDS <= inp_or;
- else
- SPARE_LVDS <= inp_long_reg or last_inp_long_reg or inp_long_or ;
- end if;
- end process;
-
-inp_or <= or_all((INP_i xor inp_invert) and not input_enable);
-inp_long_or <= (inp_or or inp_long_or) and not inp_long_reg;
-inp_long_reg <= inp_long_or when rising_edge(clk_i);
-last_inp_long_reg <= inp_long_reg when rising_edge(clk_i);
-
-
-TEST_LINE <= (others => '0');
-
-
-gen_leds : for i in 1 to 8 generate
- LED(i) <= not leds((i-1)*2) when led_status(8) = '1' else not led_status(i-1);
-end generate;
-
-
-end architecture;
-
+++ /dev/null
-FREQUENCY NET clk_i_c 133 MHz;
-
-
-
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-
-
-library machxo2;
-use machxo2.all;
-
-
-entity panda_dirc_wasa is
- generic(
- PADIWA_FLAVOUR : integer := 3;
- TEMP_CORRECTION: integer := c_YES;
- TDCTEST : integer := c_NO
- );
- port(
- CON : out std_logic_vector(16 downto 1);
- INP : in std_logic_vector(16 downto 1);
- PWM : out std_logic_vector(16 downto 1);
- SPARE_LINE : out std_logic_vector(3 downto 0);
- SPARE_LVDS : out std_logic;
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SPI_CLK : in std_logic;
- SPI_CS : in std_logic;
- SPI_IN : in std_logic;
- SPI_OUT : out std_logic;
- TEMP_LINE : inout std_logic;
- TEST_LINE : inout std_logic_vector(15 downto 0)
- );
-end entity;
-
-architecture panda_dirc_wasa_arch of panda_dirc_wasa is
-
-component OSCH
--- synthesis translate_off
- generic (NOM_FREQ: string := "133.00");
--- synthesis translate_on
- port (
- STDBY :IN std_logic;
- OSC :OUT std_logic;
- SEDSTDBY :OUT std_logic
- );
-end component;
-
-component pll
- port (
- CLKI: in std_logic;
- CLKOP: out std_logic;
- CLKOS: out std_logic;
- LOCK: out std_logic);
-end component;
-
-
-attribute NOM_FREQ : string;
-attribute NOM_FREQ of clk_source : label is "133.00";
-signal clk_i : std_logic;
-
-signal onewire_reset : std_logic := '1';
-signal id_data_i : std_logic_vector(15 downto 0);
-signal id_addr_i : std_logic_vector(2 downto 0);
-signal id_write_i: std_logic;
-signal temperature_i : std_logic_vector(11 downto 0);
-signal timer : unsigned(31 downto 0) := (others => '0');
-
-type idram_t is array(0 to 7) of std_logic_vector(15 downto 0);
-signal idram : idram_t;
-
-signal pll_lock : std_logic;
-signal clk_26 : std_logic;
-signal clk_osc : std_logic;
-signal input_i : std_logic_vector(255 downto 0);
-
-begin
-
-
-THE_PLL : pll
- port map(
- CLKI => clk_osc,
- CLKOP => clk_26, --33
- CLKOS => clk_i, --133
- LOCK => pll_lock --no lock available!
- );
-
----------------------------------------------------------------------------
--- Clock
----------------------------------------------------------------------------
-clk_source: OSCH
--- synthesis translate_off
- generic map ( NOM_FREQ => "133.00" )
--- synthesis translate_on
- port map (
- STDBY => '0',
- OSC => clk_osc,
- SEDSTDBY => open
- );
-
-
-THE_LCD : entity work.lcd
- port map(
- CLK => clk_26,
- RESET => onewire_reset,
-
- MOSI => TEST_LINE(4),
- SCK => TEST_LINE(5),
- DC => TEST_LINE(3),
- CS => TEST_LINE(1),
- RST => TEST_LINE(2),
-
- INPUT => input_i,
- LED => open
-
- );
-
-onewire_reset <= not TEST_LINE(15);
-
-input_i( 15 downto 0) <= idram(0);
-input_i( 31 downto 16) <= idram(1);
-input_i( 47 downto 32) <= idram(2);
-input_i( 63 downto 48) <= idram(3);
-input_i( 79 downto 64) <= idram(4);
-input_i(223 downto 80) <= (others => '0');
-input_i(255 downto 224) <= std_logic_vector(timer);
-
----------------------------------------------------------------------------
--- Temperature Sensor
----------------------------------------------------------------------------
-THE_ONEWIRE : trb_net_onewire
- generic map(
- USE_TEMPERATURE_READOUT => 1,
- PARASITIC_MODE => c_NO,
- CLK_PERIOD => 33
- )
- port map(
- CLK => clk_26,
- RESET => onewire_reset,
- READOUT_ENABLE_IN => '1',
- ONEWIRE => TEMP_LINE,
- MONITOR_OUT => open,
- --connection to id ram, according to memory map in TrbNetRegIO
- DATA_OUT => id_data_i,
- ADDR_OUT => id_addr_i,
- WRITE_OUT=> id_write_i,
- TEMP_OUT => temperature_i,
- ID_OUT => open,
- STAT => open
- );
-
-PROC_IDMEM : process begin
- wait until rising_edge(clk_i);
- if id_write_i = '1' then
- idram(to_integer(unsigned(id_addr_i))) <= id_data_i;
- else
- idram(4) <= "0000" & temperature_i;
- end if;
-end process;
-
-PROC_TIMER : process begin
- wait until rising_edge(clk_26);
- timer <= timer + 1;
-end process;
-
-
-end architecture;
+++ /dev/null
-#!/usr/bin/perl
-use Data::Dumper;
-use warnings;
-use strict;
-
-
-
-
-###################################################################################
-#Settings for this project
-my $TOPNAME = "panda_dirc_wasa"; #Name of top-level entity
-my $lattice_path = '/d/jspc29/lattice/diamond/2.2_x64';
-my $synplify_path = '/d/jspc29/lattice/synplify/G-2012.09-SP1/';
-my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
-my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
-###################################################################################
-
-
-$ENV{'PAR_DESIGN_NAME'}=$TOPNAME;
-
-#
-# set_option -technology MACHXO2
-# set_option -part LCMXO2_4000HC
-# set_option -package FTG256C
-# set_option -speed_grade -6
-# set_option -part_companion ""
-
-
-
-use FileHandle;
-
-$ENV{'SYNPLIFY'}=$synplify_path;
-$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
-
-
-
-
-my $FAMILYNAME="MACHXO2";
-my $DEVICENAME="LCMXO2-4000HC";
-my $PACKAGE="FTBGA256";
-my $SPEEDGRADE="6";
-
-
-#create full lpf file
-system("cp ../base/".$TOPNAME."1.lpf workdir/$TOPNAME.lpf");
-system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
-
-
-#set -e
-#set -o errexit
-
-#generate timestamp
-my $t=time;
-my $fh = new FileHandle(">version.vhd");
-die "could not open file" if (! defined $fh);
-print $fh <<EOF;
-
---## attention, automatically generated. Don't change by hand.
-library ieee;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use ieee.numeric_std.all;
-
-package version is
-
- constant VERSION_NUMBER_TIME : integer := $t;
-
-end package version;
-EOF
-$fh->close;
-
-system("env| grep LM_");
-my $r = "";
-
-my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
-$r=execute($c, "do_not_exit" );
-
-
-chdir "workdir";
-$fh = new FileHandle("<$TOPNAME".".srr");
-my @a = <$fh>;
-$fh -> close;
-
-
-
-foreach (@a)
-{
- if(/\@E:/)
- {
- print "\n";
- $c="cat $TOPNAME.srr | grep \"\@E\"";
- system($c);
- print "\n\n";
- exit 129;
- }
-}
-
-
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
-
-
-$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
-execute($c);
-
-my $tpmap = $TOPNAME . "_map" ;
-
-$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
-execute($c);
-
-system("rm $TOPNAME.ncd");
-
-#$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|;
-# $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
-$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|;
-execute($c);
-# IOR IO Timing Report
-# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
-# execute($c);
-
-# TWR Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-# $c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
-# execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -jedec $TOPNAME.ncd $TOPNAME.jed $TOPNAME.prf|;
-# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-chdir "..";
-
-exit;
-
-sub execute {
- my ($c, $op) = @_;
- #print "option: $op \n";
- $op = "" if(!$op);
- print "\n\ncommand to execute: $c \n";
- $r=system($c);
- if($r) {
- print "$!";
- if($op ne "do_not_exit") {
- exit;
- }
- }
-
- return $r;
-
-}
+++ /dev/null
-// --------------------------------------------------------------------
-// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-// --------------------------------------------------------------------
-// Copyright (c) 2001 - 2012 by Lattice Semiconductor Corporation
-// --------------------------------------------------------------------
-//
-// Permission:
-//
-// Lattice Semiconductor grants permission to use this code for use
-// in synthesis for any Lattice programmable logic product. Other
-// use of this code, including the selling or duplication of any
-// portion is strictly prohibited.
-//
-// Disclaimer:
-//
-// This verilog source code is intended as a design reference
-// which illustrates how these types of functions can be implemented.
-// It is the user's responsibility to verify their design for
-// consistency and functionality through the use of formal
-// verification methods. Lattice Semiconductor provides no warranty
-// regarding the use or functionality of this code.
-//
-// --------------------------------------------------------------------
-//
-// Lattice Semiconductor Corporation
-// 5555 NE Moore Court
-// Hillsboro, OR 97214
-// U.S.A
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// 503-268-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// --------------------------------------------------------------------
-// Code Revision History :
-// --------------------------------------------------------------------
-// Ver: | Author |Mod. Date |Changes Made:
-// V1.0 | Vijay |3/09/12 |Initial ver
-// V1.1 | SHossner|6/08/12 |Added READ_DELAY parameter
-//
-// --------------------------------------------------------------------
-
-`timescale 1ns / 100ps
-`include "efb_define_def.v"
-//`include "/d/jspc29/lattice/diamond/2.0/ispfpga/verilog/data/machxo2/GSR.v"
-//`include "/d/jspc29/lattice/diamond/2.0/ispfpga/verilog/data/machxo2/PUR.v"
-
-module UFM_WB(
- input clk_i
- , input rst_n
- , input[2:0] cmd
- , input[12:0] ufm_page
- , input GO
- , output reg BUSY
- , output reg ERR
-
- /***************** DPRAM port B signals *************/
- , output reg mem_clk
- , output reg mem_we
- , output reg mem_ce
- , output reg[3:0] mem_addr
- , output reg[7:0] mem_wr_data
- , input [7:0] mem_rd_data
-
- );
-
- //*****************
- // For clk_i speeds less than 16.6MHz, set READ_DELAY to zero for fastest UFM read operation
- // For clk_i speeds greater than 16.6MHz, set READ_DELAY as follows:
- // Calculate minimum READ_DELAY as follows:
- // READ_DELAY(min) = 240/PERIOD - 4
- // Where PERIOD = clk_i period in ns
- // Example, for clk_i = 45MHz, PERIOD = 22.22ns and READ_DELAY = 7 (6.8 rounded up)
- //
- // Or choose from the following table:
- // READ_DELAY | Max Clk_i
- // ------------+-------------
- // 0 | 16.6 Mhz
- // 2 | 25.0 Mhz
- // 4 | 33.3 Mhz
- // 8 | 50.0 Mhz
- // 12 | 66.6 Mhz
- // 14 | 75.0 Mhz
-
- parameter READ_DELAY = 4;
- //*****************
-
- wire ufm_enable_cmd;
- wire ufm_read_cmd;
- wire ufm_write_cmd;
- wire ufm_erase_cmd;
- wire ufm_disable_cmd;
- reg ufm_enabled;
- reg n_ufm_enabled;
- wire ufm_repeated_read;
- wire ufm_repeated_write;
-
-
-
- reg [7:0] wb_dat_i ;
- reg wb_stb_i ;
- wire wb_cyc_i = wb_stb_i ;
- reg [7:0] wb_adr_i ;
- reg wb_we_i ;
- wire [7:0] wb_dat_o ;
- wire wb_ack_o ;
-
- reg [7:0] n_wb_dat_i ;
- reg n_wb_stb_i ;
- reg [7:0] n_wb_adr_i ;
- reg n_wb_we_i ;
- reg n_busy;
- reg n_error;
- reg [7:0] c_state ,n_state;
- reg efb_flag,n_efb_flag;
- reg [7:0] sm_wr_data;
- reg [3:0] sm_addr;
- reg sm_ce;
- reg sm_we;
- reg [4:0] count;
- reg sm_addr_MSB;
- reg [7:0] sm_rd_data;
-
-
- reg [7:0] n_data_frm_ufm;
- reg [3:0] n_addr_ufm;
- reg n_clk_en_ufm;
- reg n_wr_en_ufm;
- reg [4:0] n_count;
- reg n_ufm_addr_MSB;
-
- wire [7:0] cmd_read;
- wire [7:0] cmd_erase;
- wire [7:0] cmd_program;
- wire [7:0] cmd_select_sector;
- wire [12:0] real_address;
-
-
- PUR PUR_INST (.PUR(1'b1));
- GSR GSR_INST (.GSR(1'b1));
-
- flash inst1 ( .wb_clk_i(clk_i ), // EFB with UFM enabled
- .wb_rst_i(!rst_n ),
- .wb_cyc_i(wb_cyc_i ),
- .wb_stb_i(wb_stb_i ),
- .wb_we_i(wb_we_i ),
- .wb_adr_i(wb_adr_i),
- .wb_dat_i(wb_dat_i ),
- .wb_dat_o(wb_dat_o ),
- .wb_ack_o(wb_ack_o ),
- .wbc_ufm_irq( )
- );
-
- // flashram inst2 ( .DataInA(sm_wr_data ), // True dual port RAM. Port A controlled by internal SM and port B controlled by user.
- // .DataInB(mem_wr_data ),
- // .AddressA({sm_addr_MSB,sm_addr} ),
- // .AddressB({!sm_addr_MSB,mem_addr} ),
- // .ClockA(clk_i ),
- // .ClockB(mem_clk ),
- // .ClockEnA(sm_ce ),
- // .ClockEnB(mem_ce ),
- // .WrA(sm_we ),
- // .WrB(mem_we ),
- // .ResetA(!rst_n ),
- // .ResetB(!rst_n ),
- // .QA(sm_rd_data ),
- // .QB(mem_rd_data ));
-
-
- always @ (*)
- begin
- sm_rd_data <= mem_rd_data;
- mem_we <= sm_we;
- mem_ce <= sm_ce;
- mem_clk <= clk_i;
- mem_addr <= sm_addr;
- mem_wr_data <= sm_wr_data;
- end
-
- assign ufm_enable_cmd = (cmd == 3'b100) ? 1'b1 : 1'b0 ;
- assign ufm_read_cmd = ((cmd == 3'b000) || (cmd == 3'b001)) ? 1'b1 : 1'b0 ;
- assign ufm_write_cmd = ((cmd == 3'b010) || (cmd == 3'b011)) ? 1'b1 : 1'b0 ;
- assign ufm_erase_cmd = (cmd == 3'b111) ? 1'b1 : 1'b0 ;
- assign ufm_disable_cmd = (cmd == 3'b101) ? 1'b1 : 1'b0 ;
- assign ufm_repeated_read = (cmd == 3'b001) ? 1'b1 : 1'b0 ;
- assign ufm_repeated_write = (cmd == 3'b011) ? 1'b1 : 1'b0 ;
-
-
-
- assign cmd_read = (ufm_page[12:10] == 3'b111)? `CMD_UFM_READ : `CMD_CFG_READ ;
- assign cmd_erase = (ufm_page[12:10] == 3'b111)? `CMD_UFM_ERASE : `CMD_CFG_ERASE ;
- assign cmd_program = (ufm_page[12:10] == 3'b111)? `CMD_UFM_PROGRAM : `CMD_CFG_PROGRAM ;
- assign real_address= (ufm_page[12:10] == 3'b111)? {3'b000,ufm_page[9:0]} : ufm_page ;
- assign cmd_select_sector = (ufm_page[12:10] == 3'b111)? 8'h40 : 8'h00 ;
-
-
- always @ (posedge clk_i or negedge rst_n) // generate clk enable and write enable signals for port A of the DPRAM
- begin
- if(!rst_n)
- begin
- sm_ce <= 1'b0;
- sm_we <= 1'b0;
- end
- else if (((c_state == `state58) && (n_state == `state59)) || ((c_state == `state51)))
- begin
- sm_ce <= 1'b0;
- sm_we <= 1'b0;
- end
- else if ((n_state == `state58) || ((c_state == `state50) && (n_state == `state51)))
- begin
- sm_ce <= 1'b1;
- if (ufm_read_cmd)
- sm_we <= 1'b1;
- else
- sm_we <= 1'b0;
- end
- else
- begin
- sm_ce <= 1'b0;
- sm_we <= 1'b0;
- end
- end
-
-
- always @ (posedge clk_i or negedge rst_n)
- begin
- if(!rst_n)
- begin
- wb_dat_i <= 8'h00;
- wb_stb_i <= 1'b0 ;
- wb_adr_i <= 8'h00;
- wb_we_i <= 1'b0;
- end
- else
- begin
- wb_dat_i <= n_wb_dat_i;
- wb_stb_i <= #0.1 n_wb_stb_i;
- wb_adr_i <= n_wb_adr_i;
- wb_we_i <= n_wb_we_i ;
-
- end
- end
-
- always @ (posedge clk_i or negedge rst_n)
- begin
- if(!rst_n) begin
- c_state <= 10'h000;
- BUSY <= 1'b1;
- efb_flag <= 1'b0 ;
- ERR <= 1'b0;
- ufm_enabled <= 1'b0;
- sm_wr_data <= 8'h00;
- sm_addr <= 4'b0000;
- count <= 4'hF;
- sm_addr_MSB <= 1'b0;
- end
- else begin
- c_state <= n_state ;
- BUSY <= n_busy;
- efb_flag <= n_efb_flag;
- ERR <= n_error;
- ufm_enabled <= n_ufm_enabled;
- sm_wr_data <= n_data_frm_ufm;
- sm_addr <= n_addr_ufm;
- count <= n_count;
- sm_addr_MSB <= n_ufm_addr_MSB;
- end
- end
-
-
-
- always @ (*)
- begin
- n_state = c_state;
- n_efb_flag = 1'b0 ;
- n_busy = BUSY;
- n_error = ERR;
- n_ufm_enabled = ufm_enabled;
- n_data_frm_ufm = sm_wr_data;
- n_addr_ufm = sm_addr;
- n_clk_en_ufm = sm_ce;
- n_wr_en_ufm = sm_we;
- n_count = count;
- n_ufm_addr_MSB = sm_addr_MSB;
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- case (c_state)
-
- `state0 : begin
- n_busy = 1'b1;
- n_error = 1'b0;
- n_ufm_enabled = 1'b0;
- n_state = `state1; // (state1 - state8)--check if UFM is busy and deassert BUSY flag if free.
- end
-
- `state1: begin // enable WB-UFM interface
- if (wb_ack_o && efb_flag) begin
- n_state = `state2;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGCR;
- n_wb_dat_i = 8'h80;
- n_wb_stb_i = `HIGH ;
- n_efb_flag = 1'b1 ;
- end
- end
-
-
- `state2: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state3;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = `CMD_CHECK_BUSY_FLAG;
- n_wb_stb_i = `HIGH ;
- n_efb_flag = 1'b1 ;
- end
- end
-
-
- `state3: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state4;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- n_efb_flag = 1'b1 ;
- end
- end
-
-
- `state4: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state5;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state5: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state6;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_efb_flag = 1'b1 ;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- n_efb_flag = 1'b1 ;
- end
- end
-
-
- `state6: begin // Return Back to State 2
- if (wb_ack_o && efb_flag) begin
- if(wb_dat_o & (8'h80) )
- n_state = `state7;
- else
- n_state = `state8;
- end
- else begin
- n_wb_we_i = `READ_STATUS;
- n_wb_adr_i = `CFGRXDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- n_efb_flag = 1'b1 ;
- end
- end
-
- `state7: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state1;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGCR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- n_busy = 1'b1;
- end
- end
-
- `state8: begin //
- if (wb_ack_o && efb_flag) begin
- n_busy = 1'b0;
- n_state = `state9;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGCR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- n_busy = 1'b1;
- end
- end
-
- `state9: begin
- if (GO)
- begin
- n_busy = 1'b1;
- n_error = 1'b0;
- if (ufm_enabled && ufm_write_cmd)
- n_ufm_addr_MSB = !sm_addr_MSB;
- n_state = `state10;
- end
- else
- begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_busy = 1'b0;
- n_error = ERR;
- end
- end
-
-
- `state10: begin
- if(ufm_enable_cmd) // enable UFM
- n_state = `state11;
- else if (ufm_enabled)begin // decode command only if UFM is already enabled
- if (ufm_read_cmd)
- n_state = `state35;
- else if (ufm_write_cmd)
- n_state = `state35;
- else if (ufm_erase_cmd)
- n_state = `state17;
- else if (ufm_disable_cmd)
- n_state = `state23;
- end
- else begin // set ERR if a command is sent when UFM is disabled and go to previous state and wait for GO
- n_busy = 1'b0;
- n_error = 1'b1;
- n_state = `state9;
- end
- end
-
- `state11: begin // (state11 - state16) enable UFM
- if (wb_ack_o && efb_flag) begin
- n_state = `state12;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGCR;
- n_efb_flag = 1'b1 ;
- n_wb_dat_i = 8'h80;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state12: begin // enable configuration
- if (wb_ack_o && efb_flag) begin
- n_state = `state13;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = `CMD_ENABLE_INTERFACE;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state13: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state14;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h08;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state14: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state15;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_efb_flag = 1'b1 ;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state15: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state16;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state16: begin //
- if (wb_ack_o && efb_flag) begin
- n_ufm_enabled = 1'b1;
- n_state = `state1; // check for busy flag after enabling UFM
- end
- else begin
- n_efb_flag = 1'b1 ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGCR ;
- n_wb_dat_i = 8'h00;
- n_busy = 1'b1;
- n_wb_stb_i = `HIGH ;
- n_ufm_enabled = 1'b0;
- end
- end
-
-
- `state17: begin // (state17- state22) erase UFM
- if (wb_ack_o && efb_flag) begin
- n_state = `state18;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGCR;
- n_efb_flag = 1'b1 ;
- n_wb_dat_i = 8'h80;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state18: begin
- if (wb_ack_o && efb_flag) begin
- n_state = `state19;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = cmd_erase;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state19: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state20;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h04; //JM added for 0xE to erase CFG Flash
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state20: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state21;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_efb_flag = 1'b1 ;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state21: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state22;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- end
- end
-
- `state22: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state1; // check for busy flag after erasing UFM
- end
- else begin
- n_efb_flag = 1'b1 ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGCR ;
- n_wb_dat_i = 8'h00;
- n_busy = 1'b1;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state23: begin // open frame // (state23 - state 32) disable UFM
- if (wb_ack_o && efb_flag) begin
- n_state = `state24;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGCR;
- n_efb_flag = 1'b1 ;
- n_wb_dat_i = 8'h80;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state24: begin // disable configuration
- if (wb_ack_o && efb_flag) begin
- n_state = `state25;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = `CMD_DISABLE_INTERFACE;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state25: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state26;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state26: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state27;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_efb_flag = 1'b1 ;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state27: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state28;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- end
- end
- `state28: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state29;
- end
- else begin
- n_efb_flag = 1'b1 ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGCR ;
- n_wb_dat_i = 8'h00;
- n_busy = 1'b1;
- n_wb_stb_i = `HIGH ;
- end
- end
-
- `state29: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state30;
- end
- else begin
- n_efb_flag = 1'b1 ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGCR ;
- n_wb_dat_i = 8'h80;
- n_busy = 1'b1;
- n_wb_stb_i = `HIGH ;
- end
- end
- `state30: begin // bypass command
- if (wb_ack_o && efb_flag) begin
- n_state = `state31;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = `CMD_BYPASS;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state31: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state32;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = `CMD_BYPASS;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state32: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state33;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = `CMD_BYPASS;
- n_efb_flag = 1'b1 ;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state33: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state34;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = `CMD_BYPASS;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state34: begin //
- if (wb_ack_o && efb_flag) begin
- n_busy = 1'b0;
- n_ufm_enabled = 1'b0;
- n_state = `state9;
- end
- else begin
- n_efb_flag = 1'b1 ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGCR ;
- n_wb_dat_i = 8'h00;
- n_busy = 1'b1;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state35: begin // (state35 - state60 ) UFM read/write operations
- if (wb_ack_o && efb_flag) begin
- if (ufm_repeated_read)
- n_state = `state46;
- else if (ufm_repeated_write)
- n_state = `state54;
- else
- n_state = `state36;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGCR;
- n_wb_dat_i = 8'h80;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state36: begin // Set UFM Page Address
- if (wb_ack_o && efb_flag) begin
- n_state = `state37;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = `CMD_SET_ADDRESS;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state37: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state38;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state38: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state39;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state39: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state40;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state40: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state41;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = cmd_select_sector;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state41: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state42;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state42: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state43;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = {3'b000,real_address[12:8]};
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state43: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state44;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = real_address[7:0];
- n_wb_stb_i = `HIGH ;
- end
- end
-
- `state44: begin //
- if (wb_ack_o && efb_flag) begin
- if (ufm_write_cmd)
- n_state = `state53;
- else
- n_state = `state45;
- end
- else begin
- n_efb_flag = 1'b1 ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGCR ;
- n_wb_dat_i = 8'h00;
- n_busy = 1'b1;
- n_wb_stb_i = `HIGH ;
- end
- end
-
- `state45: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state46;
- end
- else begin
- n_efb_flag = 1'b1 ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGCR ;
- n_wb_dat_i = 8'h80;
- n_busy = 1'b1;
- n_wb_stb_i = `HIGH ;
- end
- end
-
- `state46: begin // Read Operation
- if (wb_ack_o && efb_flag) begin
- n_count = READ_DELAY;
- n_state = `stateRD_delay;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = cmd_read;
- n_wb_stb_i = `HIGH ;
- end
- end
-
- `stateRD_delay: begin
- if (count == 0)
- n_state = `state47;
- else begin
- n_count = count - 1;
- end
- end
-
- `state47: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state48;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h10;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state48: begin //
- if (wb_ack_o && efb_flag)
- n_state = `state49;
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state49: begin //
- if (wb_ack_o && efb_flag) begin
- n_count = 5'b10000;
- n_addr_ufm = 4'h0;
- n_clk_en_ufm = 1'b1;
- n_state = `state50;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h01;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state50: begin //
- if (wb_ack_o && efb_flag) begin
- n_count = count - 1;
- n_data_frm_ufm = wb_dat_o;
- n_state = `state51;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `READ_DATA;
- n_wb_adr_i = `CFGRXDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- end
- end
-
- `state51: begin //
- n_addr_ufm = sm_addr + 1;
- if (count == 0)
- n_state = `state52;
- else begin
- n_state = `state50;
- end
- end
-
-
- `state52: begin //
- if (wb_ack_o && efb_flag) begin
- n_ufm_addr_MSB = !sm_addr_MSB;
- n_busy = 1'b0;
- n_state = `state9;
- end
- else begin
- n_wb_we_i = `WRITE;
- n_efb_flag = 1'b1 ;
- n_wb_adr_i = `CFGCR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- n_busy = 1'b1;
- end
- end
-
- `state53: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state54;
- end
- else begin
- n_efb_flag = 1'b1 ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGCR ;
- n_wb_dat_i = 8'h80;
- n_busy = 1'b1;
- n_wb_stb_i = `HIGH ;
- end
- end
- `state54: begin // Write Operation
- if (wb_ack_o && efb_flag) begin
- n_state = `state55;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = cmd_program;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state55: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state56;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state56: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state57;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state57: begin //
- if (wb_ack_o && efb_flag) begin
- n_count = 5'b10000;
- n_addr_ufm = 4'h0;
- n_clk_en_ufm = 1'b1;
- n_wr_en_ufm = 1'b0;
- n_state = `state58;
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h01;
- n_wb_stb_i = `HIGH ;
- end
- end
-
-
- `state58: begin //
- n_count = count - 1;
- n_state = `state59;
- end
-
- `state59: begin //
- if (wb_ack_o && efb_flag) begin
- n_addr_ufm = sm_addr + 1;
- if (count == 0)
- n_state = `state60;
- else begin
- n_state = `state58;
- end
- end
- else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = sm_rd_data;
- n_wb_stb_i = `HIGH ;
- end
- end
-
- `state60: begin //
- if (wb_ack_o && efb_flag) begin
- n_state = `state1;
- end
- else begin
- n_efb_flag = 1'b1 ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `CFGCR ;
- n_wb_dat_i = 8'h00;
- n_busy = 1'b1;
- n_wb_stb_i = `HIGH ;
- end
- end
- endcase
- end
-
-
-
-endmodule
-
-
+++ /dev/null
-/****************************************************************************\r
-**\r
-** Description:\r
-** `define Define for PULI Utility\r
-**\r
-** Disclaimer:\r
-** This source code is intended as a design reference which\r
-** illustrates how these types of functions can be implemented. It\r
-** is the user's responsibility to verify their design for\r
-** consistency and functionality through the use of formal\r
-** verification methods. Lattice Semiconductor provides no warranty\r
-** regarding the use or functionality of this code.\r
-**\r
-*****************************************************************************\r
-**\r
-** Lattice Semiconductor Corporation\r
-** 5555 NE Moore Court\r
-** Hillsboro, OR 97214\r
-** U.S.A\r
-**\r
-** TEL: 1-800-Lattice (USA and Canada )\r
-** (503 268-8001 (other locations )\r
-**\r
-** web: http://www.latticesemi.com\r
-** email: techsupport@latticesemi.com\r
-**\r
-*****************************************************************************\r
-** Change History (Latest changes on top )\r
-**\r
-** Ver Date Person\r
-** --------------------------------------------------------------------------\r
-** 3.0 13/9/2011 Akhilesh LBN\r
-**\r
-*****************************************************************************/\r
-\r
-\r
-/***********************************************************************\r
- * *\r
- * EFB REGISTER SET *\r
- * *\r
- ***********************************************************************/\r
-\r
- \r
-`define MICO_EFB_I2C_CR 8'h40 //4a\r
-`define MICO_EFB_I2C_CMDR 8'h41 //4b\r
-`define MICO_EFB_I2C_BLOR 8'h42 //4c\r
-`define MICO_EFB_I2C_BHIR 8'h43 //4d\r
-`define MICO_EFB_I2C_TXDR 8'h44 //4e\r
-`define MICO_EFB_I2C_SR 8'h45 //4f\r
-`define MICO_EFB_I2C_GCDR 8'h46 //50\r
-`define MICO_EFB_I2C_RXDR 8'h47 //51\r
-`define MICO_EFB_I2C_IRQSR 8'h48 //52\r
-`define MICO_EFB_I2C_IRQENR 8'h49 //53\r
-\r
-`define MICO_EFB_SPI_CR0 8'h54 \r
-`define MICO_EFB_SPI_CR1 8'h55 \r
-`define MICO_EFB_SPI_CR2 8'h56 \r
-`define MICO_EFB_SPI_BR 8'h57 \r
-`define MICO_EFB_SPI_CSR 8'h58 \r
-`define MICO_EFB_SPI_TXDR 8'h59 \r
-`define MICO_EFB_SPI_SR 8'h5a \r
-`define MICO_EFB_SPI_RXDR 8'h5b \r
-`define MICO_EFB_SPI_IRQSR 8'h5c \r
-`define MICO_EFB_SPI_IRQENR 8'h5d \r
-\r
-\r
-`define MICO_EFB_TIMER_CR0 8'h5E \r
-`define MICO_EFB_TIMER_CR1 8'h5F \r
-`define MICO_EFB_TIMER_TOP_SET_LO 8'h60 \r
-`define MICO_EFB_TIMER_TOP_SET_HI 8'h61 \r
-`define MICO_EFB_TIMER_OCR_SET_LO 8'h62 \r
-`define MICO_EFB_TIMER_OCR_SET_HI 8'h63 \r
-`define MICO_EFB_TIMER_CR2 8'h64 \r
-`define MICO_EFB_TIMER_CNT_SR_LO 8'h65 \r
-`define MICO_EFB_TIMER_CNT_SR_HI 8'h66 \r
-`define MICO_EFB_TIMER_TOP_SR_LO 8'h67 \r
-`define MICO_EFB_TIMER_TOP_SR_HI 8'h68 \r
-`define MICO_EFB_TIMER_OCR_SR_LO 8'h69 \r
-`define MICO_EFB_TIMER_OCR_SR_HI 8'h6A \r
-`define MICO_EFB_TIMER_ICR_SR_LO 8'h6B \r
-`define MICO_EFB_TIMER_ICR_SR_HI 8'h6C \r
-`define MICO_EFB_TIMER_SR 8'h6D \r
-`define MICO_EFB_TIMER_IRQSR 8'h6E \r
-`define MICO_EFB_TIMER_IRQENR 8'h6F \r
-\r
- \r
-/***********************************************************************\r
- * *\r
- * EFB SPI CONTROLLER PHYSICAL DEVICE SPECIFIC INFORMATION *\r
- * *\r
- ***********************************************************************/\r
-\r
-\r
-\r
-\r
-// Control Register 1 Bit Masks\r
-`define MICO_EFB_SPI_CR1_SPE 8'h80 \r
-`define MICO_EFB_SPI_CR1_WKUPEN 8'h40 \r
-// Control Register 2 Bit Masks\r
-`define MICO_EFB_SPI_CR2_LSBF 8'h01 \r
-`define MICO_EFB_SPI_CR2_CPHA 8'h02 \r
-`define MICO_EFB_SPI_CR2_CPOL 8'h04 \r
-`define MICO_EFB_SPI_CR2_SFSEL_NORMAL 8'h00 \r
-`define MICO_EFB_SPI_CR2_SFSEL_LATTICE 8'h08 \r
-`define MICO_EFB_SPI_CR2_SRME 8'h20 \r
-`define MICO_EFB_SPI_CR2_MCSH 8'h40 \r
-`define MICO_EFB_SPI_CR2_MSTR 8'h80 \r
-// Status Register Bit Masks\r
-`define MICO_EFB_SPI_SR_TIP 8'h80 \r
-`define MICO_EFB_SPI_SR_TRDY 8'h10 \r
-`define MICO_EFB_SPI_SR_RRDY 8'h08 \r
-`define MICO_EFB_SPI_SR_TOE 8'h04 \r
-`define MICO_EFB_SPI_SR_ROE 8'h02 \r
-`define MICO_EFB_SPI_SR_MDF 8'h01 \r
-\r
-/***********************************************************************\r
- * *\r
- * EFB I2C CONTROLLER PHYSICAL DEVICE SPECIFIC INFORMATION *\r
- * *\r
- ***********************************************************************/\r
-\r
-\r
-\r
-// Control Register Bit Masks\r
-`define MICO_EFB_I2C_CR_I2CEN 8'h80 \r
-`define MICO_EFB_I2C_CR_GCEN 8'h40 \r
-`define MICO_EFB_I2C_CR_WKUPEN 8'h20 \r
-// Status Register Bit Masks\r
-`define MICO_EFB_I2C_SR_TIP 8'h80 \r
-`define MICO_EFB_I2C_SR_BUSY 8'h40 \r
-`define MICO_EFB_I2C_SR_RARC 8'h20 \r
-`define MICO_EFB_I2C_SR_SRW 8'h10 \r
-`define MICO_EFB_I2C_SR_ARBL 8'h08 \r
-`define MICO_EFB_I2C_SR_TRRDY 8'h04 \r
-`define MICO_EFB_I2C_SR_TROE 8'h02 \r
-`define MICO_EFB_I2C_SR_HGC 8'h01 \r
-// Command Register Bit Masks \r
-`define MICO_EFB_I2C_CMDR_STA 8'h80 \r
-`define MICO_EFB_I2C_CMDR_STO 8'h40 \r
-`define MICO_EFB_I2C_CMDR_RD 8'h20 \r
-`define MICO_EFB_I2C_CMDR_WR 8'h10 \r
-`define MICO_EFB_I2C_CMDR_NACK 8'h08 \r
-`define MICO_EFB_I2C_CMDR_CKSDIS 8'h04 \r
-\r
-/***********************************************************************\r
- * *\r
- * EFB I2C USER DEFINE *\r
- * *\r
- ***********************************************************************/\r
-`define MICO_EFB_I2C_TRANSMISSION_DONE 8'h00 \r
-`define MICO_EFB_I2C_TRANSMISSION_ONGOING 8'h80 \r
-`define MICO_EFB_I2C_FREE 8'h00 \r
-`define MICO_EFB_I2C_BUSY 8'h40 \r
-`define MICO_EFB_I2C_ACK_NOT_RCVD 8'h20 \r
-`define MICO_EFB_I2C_ACK_RCVD 8'h00 \r
-`define MICO_EFB_I2C_ARB_LOST 8'h08 \r
-`define MICO_EFB_I2C_ARB_NOT_LOST 8'h00 \r
-`define MICO_EFB_I2C_DATA_READY 8'h04 \r
-\r
-/***********************************************************************\r
- * *\r
- * EFB TIMER PHYSICAL DEVICE SPECIFIC INFORMATION *\r
- * *\r
- ***********************************************************************/\r
-\r
-\r
-\r
-// Control Register 0\r
-`define MICO_EFB_TIMER_RSTN_MASK 8'h80 \r
-`define MICO_EFB_TIMER_GSRN_MASK 8'h40 \r
-`define MICO_EFB_TIMER_GSRN_ENABLE 8'h40 \r
-`define MICO_EFB_TIMER_GSRN_DISABLE 8'h00 \r
-`define MICO_EFB_TIMER_CCLK_MASK 8'h38 \r
-`define MICO_EFB_TIMER_CCLK_DIV_0 8'h00 \r
-`define MICO_EFB_TIMER_CCLK_DIV_1 8'h08 \r
-`define MICO_EFB_TIMER_CCLK_DIV_8 8'h10 \r
-`define MICO_EFB_TIMER_CCLK_DIV_64 8'h18 \r
-`define MICO_EFB_TIMER_CCLK_DIV_256 8'h20 \r
-`define MICO_EFB_TIMER_CCLK_DIV_1024 8'h28 \r
-`define MICO_EFB_TIMER_SCLK_MASK 8'h07 \r
-`define MICO_EFB_TIMER_SCLK_CIB_RE 8'h00 \r
-`define MICO_EFB_TIMER_SCLK_OSC_RE 8'h02 \r
-`define MICO_EFB_TIMER_SCLK_CIB_FE 8'h04 \r
-`define MICO_EFB_TIMER_SCLK_OSC_FE 8'h06 \r
-// Control Register 1\r
-`define MICO_EFB_TIMER_TOP_SEL_MASK 8'h80 \r
-`define MICO_EFB_TIMER_TOP_MAX 8'h00 \r
-`define MICO_EFB_TIMER_TOP_USER_SELECT 8'h10 \r
-`define MICO_EFB_TIMER_OC_MODE_MASK 8'h0C \r
-`define MICO_EFB_TIMER_OC_MODE_STATIC_ZERO 8'h00 \r
-`define MICO_EFB_TIMER_OC_MODE_TOGGLE 8'h04 \r
-`define MICO_EFB_TIMER_OC_MODE_CLEAR 8'h08 \r
-`define MICO_EFB_TIMER_OC_MODE_SET 8'h0C \r
-`define MICO_EFB_TIMER_MODE_MASK 8'h03 \r
-`define MICO_EFB_TIMER_MODE_WATCHDOG 8'h00 \r
-`define MICO_EFB_TIMER_MODE_CTC 8'h01 \r
-`define MICO_EFB_TIMER_MODE_FAST_PWM 8'h02 \r
-`define MICO_EFB_TIMER_MODE_TRUE_PWM 8'h03 \r
-// Control Register 2\r
-`define MICO_EFB_TIMER_OC_FORCE 8'h04 \r
-`define MICO_EFB_TIMER_CNT_RESET 8'h02 \r
-`define MICO_EFB_TIMER_CNT_PAUSE 8'h01 \r
-// Status Register\r
-`define MICO_EFB_TIMER_SR_OVERFLOW 8'h01 \r
-`define MICO_EFB_TIMER_SR_COMPARE_MATCH 8'h02 \r
-`define MICO_EFB_TIMER_SR_CAPTURE 8'h04 \r
-\r
-\r
-\r
-`define CFGCR 8'h70 \r
-`define CFGTXDR 8'h71 \r
-`define CFGSR 8'h72 \r
-`define CFGRXDR 8'h73 \r
-`define CFGIRQ 8'h74 \r
-`define CFGIRQEN 8'h75 \r
-\r
-/***********************************************************************\r
- * *\r
- * PULI SPECIFIC *\r
- * *\r
- ***********************************************************************/\r
- \r
- `define ALL_ZERO 8'h00 \r
- `define READ 1'b0 \r
- `define READ 1'b0 \r
- `define HIGH 1'b1 \r
- `define WRITE 1'b1 \r
- `define LOW 1'b0 \r
- `define READ_STATUS 1'b0 \r
- `define READ_DATA 1'b0 \r
- \r
-/***********************************************************************\r
- * *\r
- * State Machine Variables *\r
- * *\r
- ***********************************************************************/ \r
- \r
-`define CMD_CHECK_BUSY_FLAG 8'hF0\r
-`define CMD_BYPASS 8'hFF\r
-`define CMD_ENABLE_INTERFACE 8'h74\r
-`define CMD_DISABLE_INTERFACE 8'h26\r
-`define CMD_SET_ADDRESS 8'hB4\r
-\r
-`define CMD_UFM_READ 8'hCA\r
-`define CMD_UFM_ERASE 8'hCB\r
-`define CMD_UFM_PROGRAM 8'hC9\r
-\r
-`define CMD_CFG_READ 8'h73\r
-`define CMD_CFG_ERASE 8'h0E\r
-`define CMD_CFG_PROGRAM 8'h70\r
- \r
- \r
- \r
-`define state0 7'd00 \r
-`define state1 7'd01 \r
-`define state2 7'd02 \r
-`define state3 7'd03 \r
-`define state4 7'd04 \r
-`define state5 7'd05 \r
-`define state6 7'd06 \r
-`define state7 7'd07 \r
-`define state8 7'd08 \r
-`define state9 7'd09 \r
-`define state10 7'd10 \r
-`define state11 7'd11 \r
-`define state12 7'd12 \r
-`define state13 7'd13 \r
-`define state14 7'd14 \r
-`define state15 7'd15 \r
-`define state16 7'd16 \r
-`define state17 7'd17 \r
-`define state18 7'd18 \r
-`define state19 7'd19 \r
-`define state20 7'd20 \r
-`define state21 7'd21 \r
-`define state22 7'd22 \r
-`define state23 7'd23 \r
-`define state24 7'd24 \r
-`define state25 7'd25 \r
-`define state26 7'd26 \r
-`define state27 7'd27 \r
-`define state28 7'd28 \r
-`define state29 7'd29 \r
-`define state30 7'd30 \r
-`define state31 7'd31 \r
-`define state32 7'd32 \r
-`define state33 7'd33 \r
-`define state34 7'd34 \r
-`define state35 7'd35 \r
-`define state36 7'd36 \r
-`define state37 7'd37 \r
-`define state38 7'd38 \r
-`define state39 7'd39 \r
-`define state40 7'd40 \r
-`define state41 7'd41 \r
-`define state42 7'd42 \r
-`define state43 7'd43 \r
-`define state44 7'd44 \r
-`define state45 7'd45 \r
-`define state46 7'd46 \r
-`define state47 7'd47 \r
-`define state48 7'd48 \r
-`define state49 7'd49 \r
-`define state50 7'd50 \r
-`define state51 7'd51 \r
-`define state52 7'd52 \r
-`define state53 7'd53 \r
-`define state54 7'd54 \r
-`define state55 7'd55 \r
-`define state56 7'd56 \r
-`define state57 7'd57 \r
-`define state58 7'd58 \r
-`define state59 7'd59 \r
-`define state60 7'd60 \r
-`define stateRD_delay 7'd61 \r
-`define state62 7'd62 \r
-`define state63 7'd63 \r
-`define state64 7'd64 \r
-`define state65 7'd65 \r
-`define state66 7'd66 \r
-`define state67 7'd67 \r
-`define state68 7'd68 \r
-`define state69 7'd69 \r
-`define state70 7'd70 \r
-`define state71 7'd71 \r
-`define state72 7'd72 \r
-`define state73 7'd73 \r
-`define state74 7'd74 \r
-`define state75 7'd75 \r
-`define state76 7'd76 \r
-`define state77 7'd77 \r
-`define state78 7'd78 \r
-`define state79 7'd79 \r
-`define state80 7'd80 \r
-`define state81 7'd81 \r
-`define state82 7'd82 \r
-`define state83 7'd83 \r
-`define state84 7'd84 \r
-`define state85 7'd85 \r
-`define state86 7'd86 \r
-`define state87 7'd87 \r
-`define state88 7'd88 \r
-`define state89 7'd89 \r
-`define state90 7'd90 \r
-`define state91 7'd91 \r
-`define state92 7'd92 \r
-`define state93 7'd93 \r
-`define state94 7'd94 \r
-`define state95 7'd95 \r
-`define state96 7'd96 \r
-`define state97 7'd97 \r
-`define state98 7'd98 \r
-`define state99 7'd99 \r
-`define state100 7'd100 \r
-`define state101 7'd101 \r
-`define state102 7'd102 \r
-`define state103 7'd103 \r
-`define state104 7'd104 \r
-`define state105 7'd105 \r
-`define state106 7'd106 \r
-`define state107 7'd107 \r
-`define state108 7'd108 \r
-`define state109 7'd109 \r
-`define state110 7'd110 \r
-`define state111 7'd111 \r
-`define state112 7'd112 \r
-`define state113 7'd113 \r
-`define state114 7'd114 \r
-`define state115 7'd115 \r
-`define state116 7'd116 \r
-`define state117 7'd117 \r
-`define state118 7'd118 \r
-`define state119 7'd119 \r
-`define state120 7'd120 \r
-`define state121 7'd121 \r
-`define state122 7'd122 \r
-`define state123 7'd123 \r
-`define state124 7'd124 \r
-`define state125 7'd125 \r
-`define state126 7'd126 \r
-`define state127 7'd127 \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
- \r
-
\ No newline at end of file
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_1kx8" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 01 14:08:56.647" version="5.4" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="fifo_1kx8.lpc" type="lpc" modified="2013 10 01 14:08:55.000"/>
- <File name="fifo_1kx8.vhd" type="top_level_vhdl" modified="2013 10 01 14:08:55.000"/>
- <File name="fifo_1kx8_tmpl.vhd" type="template_vhdl" modified="2013 10 01 14:08:55.000"/>
- <File name="tb_fifo_1kx8_tmpl.vhd" type="testbench_vhdl" modified="2013 10 01 14:08:55.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=machxo2
-PartType=LCMXO2-4000HC
-PartName=LCMXO2-4000HC-6FTG256C
-SpeedGrade=6
-Package=FTBGA256
-OperatingCondition=COM
-Status=S
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=5.4
-ModuleName=fifo_1kx8
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=10/01/2013
-Time=14:08:55
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-FIFOImp=EBR Only
-RDepth=1024
-RWidth=8
-WDepth=1024
-WWidth=8
-regout=1
-CtrlByRdEn=0
-ClockEn=0
-EmpFlg=1
-PeMode=Static - Single Threshold
-PeAssert=10
-PeDeassert=12
-FullFlg=1
-PfMode=Static - Single Threshold
-PfAssert=508
-PfDeassert=506
-Reset=Async
-Reset1=Sync
-RDataCount=0
-WDataCount=0
-EnECC=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
--- Module Version: 5.4
---/d/jspc29/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -n fifo_1kx8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 1024 -width 8 -rwidth 8 -regout -resetmode ASYNC -reset_rel SYNC -no_enable -pe 10 -pf 508 -e
-
--- Tue Oct 1 14:08:55 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library MACHXO2;
-use MACHXO2.components.all;
--- synopsys translate_on
-
-entity fifo_1kx8 is
- port (
- Data: in std_logic_vector(7 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end fifo_1kx8;
-
-architecture Structure of fifo_1kx8 is
-
- -- internal signal declarations
- signal Empty_int: std_logic;
- signal Full_int: std_logic;
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component FIFO8KB
- generic (FULLPOINTER1 : in String; FULLPOINTER : in String;
- AFPOINTER1 : in String; AFPOINTER : in String;
- AEPOINTER1 : in String; AEPOINTER : in String;
- ASYNC_RESET_RELEASE : in String; RESETMODE : in String;
- GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- CSW0: in std_logic; CSW1: in std_logic;
- CSR0: in std_logic; CSR1: in std_logic;
- FULLI: in std_logic; EMPTYI: in std_logic;
- WE: in std_logic; RE: in std_logic; ORE: in std_logic;
- CLKW: in std_logic; CLKR: in std_logic; RST: in std_logic;
- RPRST: in std_logic; DO0: out std_logic;
- DO1: out std_logic; DO2: out std_logic;
- DO3: out std_logic; DO4: out std_logic;
- DO5: out std_logic; DO6: out std_logic;
- DO7: out std_logic; DO8: out std_logic;
- DO9: out std_logic; DO10: out std_logic;
- DO11: out std_logic; DO12: out std_logic;
- DO13: out std_logic; DO14: out std_logic;
- DO15: out std_logic; DO16: out std_logic;
- DO17: out std_logic; EF: out std_logic;
- AEF: out std_logic; AFF: out std_logic; FF: out std_logic);
- end component;
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- fifo_1kx8_0_0: FIFO8KB
- generic map (FULLPOINTER1=> "0b01111111111000", FULLPOINTER=> "0b10000000000000",
- AFPOINTER1=> "0b00111111011000", AFPOINTER=> "0b00111111100000",
- AEPOINTER1=> "0b00000001011000", AEPOINTER=> "0b00000001010000",
- ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE=> "OUTREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11",
- DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 9)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>scuba_vlo, DI9=>scuba_vlo, DI10=>scuba_vlo,
- DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
- DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
- DI17=>scuba_vlo, CSW0=>scuba_vhi, CSW1=>scuba_vhi,
- CSR0=>RdEn, CSR1=>scuba_vhi, FULLI=>Full_int,
- EMPTYI=>Empty_int, WE=>WrEn, RE=>scuba_vhi, ORE=>scuba_vhi,
- CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, RPRST=>RPReset,
- DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), DO4=>Q(4),
- DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>open, DO9=>open,
- DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open,
- DO15=>open, DO16=>open, DO17=>open, EF=>Empty_int,
- AEF=>AlmostEmpty, AFF=>AlmostFull, FF=>Full_int);
-
- Empty <= Empty_int;
- Full <= Full_int;
-end Structure;
-
--- synopsys translate_off
-library MACHXO2;
-configuration Structure_CON of fifo_1kx8 is
- for Structure
- for all:VHI use entity MACHXO2.VHI(V); end for;
- for all:VLO use entity MACHXO2.VLO(V); end for;
- for all:FIFO8KB use entity MACHXO2.FIFO8KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="flash" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2012 12 10 14:50:18.087" version="1.1" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="flash.lpc" type="lpc" modified="2012 12 10 14:50:11.000"/>
- <File name="flash.vhd" type="top_level_vhdl" modified="2012 12 10 14:50:11.000"/>
- <File name="flash_tmpl.vhd" type="template_vhdl" modified="2012 12 10 14:50:11.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=machxo2
-PartType=LCMXO2-4000HC
-PartName=LCMXO2-4000HC-6FTG256C
-SpeedGrade=6
-Package=FTBGA256
-OperatingCondition=COM
-Status=S
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=EFB
-CoreRevision=1.1
-ModuleName=flash
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=12/10/2012
-Time=14:50:11
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-freq=
-i2c1=0
-i2c1_addr=7-Bit Addressing
-i2c1_ce=0
-i2c1_freq=100
-i2c1_sa=10000
-i2c1_we=0
-i2c2=0
-i2c2_addr=7-Bit Addressing
-i2c2_ce=0
-i2c2_freq=100
-i2c2_sa=10000
-i2c2_we=0
-ufm_addr=7-Bit Addressing
-ufm_sa=10000
-pll=0
-pll_cnt=1
-spi=0
-spi_clkinv=0
-spi_cs=1
-spi_en=0
-spi_freq=1
-spi_lsb=0
-spi_mode=Slave
-spi_ib=0
-spi_ph=0
-spi_hs=0
-spi_rxo=0
-spi_rxr=0
-spi_txo=0
-spi_txr=0
-spi_we=0
-static_tc=Static
-tc=0
-tc_clkinv=PCLOCK
-tc_ctr=1
-tc_div=1
-tc_ipcap=0
-tc_mode=CTCM
-tc_ocr=32767
-tc_oflow=1
-tc_o=TOGGLE
-tc_opcomp=0
-tc_osc=0
-tc_sa_oflow=0
-tc_top=65535
-ufm=1
-wb_clk_freq=33.33
-ufm_usage=SHARED_EBR_TAG
-ufm_ebr=0
-ufm_remain=
-mem_size=767
-ufm_start=
-ufm_init=0
-memfile=
-ufm_dt=hex
-wb=1
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
--- Module Version: 1.1
---/d/jspc29/lattice/diamond/2.0/ispfpga/bin/lin/scuba -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 33.33 -ufm -ufm_ebr 0 -mem_size 767 -ufm_0 -wb -dev 4000 -e
-
--- Mon Dec 10 14:50:11 2012
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library MACHXO2;
-use MACHXO2.components.all;
--- synopsys translate_on
-
-entity flash is
- port (
- wb_clk_i: in std_logic;
- wb_rst_i: in std_logic;
- wb_cyc_i: in std_logic;
- wb_stb_i: in std_logic;
- wb_we_i: in std_logic;
- wb_adr_i: in std_logic_vector(7 downto 0);
- wb_dat_i: in std_logic_vector(7 downto 0);
- wb_dat_o: out std_logic_vector(7 downto 0);
- wb_ack_o: out std_logic;
- wbc_ufm_irq: out std_logic);
-end flash;
-
-architecture Structure of flash is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component EFB
- generic (EFB_I2C1 : in String; EFB_I2C2 : in String;
- EFB_SPI : in String; EFB_TC : in String;
- EFB_TC_PORTMODE : in String; EFB_UFM : in String;
- EFB_WB_CLK_FREQ : in String; DEV_DENSITY : in String;
- UFM_INIT_PAGES : in Integer;
- UFM_INIT_START_PAGE : in Integer;
- UFM_INIT_ALL_ZEROS : in String;
- UFM_INIT_FILE_NAME : in String;
- UFM_INIT_FILE_FORMAT : in String;
- I2C1_ADDRESSING : in String; I2C2_ADDRESSING : in String;
- I2C1_SLAVE_ADDR : in String; I2C2_SLAVE_ADDR : in String;
- I2C1_BUS_PERF : in String; I2C2_BUS_PERF : in String;
- I2C1_CLK_DIVIDER : in Integer;
- I2C2_CLK_DIVIDER : in Integer; I2C1_GEN_CALL : in String;
- I2C2_GEN_CALL : in String; I2C1_WAKEUP : in String;
- I2C2_WAKEUP : in String; SPI_MODE : in String;
- SPI_CLK_DIVIDER : in Integer; SPI_LSB_FIRST : in String;
- SPI_CLK_INV : in String; SPI_PHASE_ADJ : in String;
- SPI_SLAVE_HANDSHAKE : in String;
- SPI_INTR_TXRDY : in String; SPI_INTR_RXRDY : in String;
- SPI_INTR_TXOVR : in String; SPI_INTR_RXOVR : in String;
- SPI_WAKEUP : in String; TC_MODE : in String;
- TC_SCLK_SEL : in String; TC_CCLK_SEL : in Integer;
- GSR : in String; TC_TOP_SET : in Integer;
- TC_OCR_SET : in Integer; TC_OC_MODE : in String;
- TC_RESETN : in String; TC_TOP_SEL : in String;
- TC_OV_INT : in String; TC_OCR_INT : in String;
- TC_ICR_INT : in String; TC_OVERFLOW : in String;
- TC_ICAPTURE : in String);
- port (WBCLKI: in std_logic; WBRSTI: in std_logic;
- WBCYCI: in std_logic; WBSTBI: in std_logic;
- WBWEI: in std_logic; WBADRI7: in std_logic;
- WBADRI6: in std_logic; WBADRI5: in std_logic;
- WBADRI4: in std_logic; WBADRI3: in std_logic;
- WBADRI2: in std_logic; WBADRI1: in std_logic;
- WBADRI0: in std_logic; WBDATI7: in std_logic;
- WBDATI6: in std_logic; WBDATI5: in std_logic;
- WBDATI4: in std_logic; WBDATI3: in std_logic;
- WBDATI2: in std_logic; WBDATI1: in std_logic;
- WBDATI0: in std_logic; PLL0DATI7: in std_logic;
- PLL0DATI6: in std_logic; PLL0DATI5: in std_logic;
- PLL0DATI4: in std_logic; PLL0DATI3: in std_logic;
- PLL0DATI2: in std_logic; PLL0DATI1: in std_logic;
- PLL0DATI0: in std_logic; PLL0ACKI: in std_logic;
- PLL1DATI7: in std_logic; PLL1DATI6: in std_logic;
- PLL1DATI5: in std_logic; PLL1DATI4: in std_logic;
- PLL1DATI3: in std_logic; PLL1DATI2: in std_logic;
- PLL1DATI1: in std_logic; PLL1DATI0: in std_logic;
- PLL1ACKI: in std_logic; I2C1SCLI: in std_logic;
- I2C1SDAI: in std_logic; I2C2SCLI: in std_logic;
- I2C2SDAI: in std_logic; SPISCKI: in std_logic;
- SPIMISOI: in std_logic; SPIMOSII: in std_logic;
- SPISCSN: in std_logic; TCCLKI: in std_logic;
- TCRSTN: in std_logic; TCIC: in std_logic;
- UFMSN: in std_logic; WBDATO7: out std_logic;
- WBDATO6: out std_logic; WBDATO5: out std_logic;
- WBDATO4: out std_logic; WBDATO3: out std_logic;
- WBDATO2: out std_logic; WBDATO1: out std_logic;
- WBDATO0: out std_logic; WBACKO: out std_logic;
- PLLCLKO: out std_logic; PLLRSTO: out std_logic;
- PLL0STBO: out std_logic; PLL1STBO: out std_logic;
- PLLWEO: out std_logic; PLLADRO4: out std_logic;
- PLLADRO3: out std_logic; PLLADRO2: out std_logic;
- PLLADRO1: out std_logic; PLLADRO0: out std_logic;
- PLLDATO7: out std_logic; PLLDATO6: out std_logic;
- PLLDATO5: out std_logic; PLLDATO4: out std_logic;
- PLLDATO3: out std_logic; PLLDATO2: out std_logic;
- PLLDATO1: out std_logic; PLLDATO0: out std_logic;
- I2C1SCLO: out std_logic; I2C1SCLOEN: out std_logic;
- I2C1SDAO: out std_logic; I2C1SDAOEN: out std_logic;
- I2C2SCLO: out std_logic; I2C2SCLOEN: out std_logic;
- I2C2SDAO: out std_logic; I2C2SDAOEN: out std_logic;
- I2C1IRQO: out std_logic; I2C2IRQO: out std_logic;
- SPISCKO: out std_logic; SPISCKEN: out std_logic;
- SPIMISOO: out std_logic; SPIMISOEN: out std_logic;
- SPIMOSIO: out std_logic; SPIMOSIEN: out std_logic;
- SPIMCSN7: out std_logic; SPIMCSN6: out std_logic;
- SPIMCSN5: out std_logic; SPIMCSN4: out std_logic;
- SPIMCSN3: out std_logic; SPIMCSN2: out std_logic;
- SPIMCSN1: out std_logic; SPIMCSN0: out std_logic;
- SPICSNEN: out std_logic; SPIIRQO: out std_logic;
- TCINT: out std_logic; TCOC: out std_logic;
- WBCUFMIRQ: out std_logic; CFGWAKE: out std_logic;
- CFGSTDBY: out std_logic);
- end component;
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- EFBInst_0: EFB
- generic map (UFM_INIT_FILE_FORMAT=> "HEX", UFM_INIT_FILE_NAME=> "NONE",
- UFM_INIT_ALL_ZEROS=> "DISABLED", UFM_INIT_START_PAGE=> 766,
- UFM_INIT_PAGES=> 0, DEV_DENSITY=> "4000L", EFB_UFM=> "ENABLED",
- TC_ICAPTURE=> "DISABLED", TC_OVERFLOW=> "DISABLED", TC_ICR_INT=> "OFF",
- TC_OCR_INT=> "OFF", TC_OV_INT=> "OFF", TC_TOP_SEL=> "OFF",
- TC_RESETN=> "ENABLED", TC_OC_MODE=> "TOGGLE", TC_OCR_SET=> 32767,
- TC_TOP_SET=> 65535, GSR=> "ENABLED", TC_CCLK_SEL=> 1, TC_MODE=> "CTCM",
- TC_SCLK_SEL=> "PCLOCK", EFB_TC_PORTMODE=> "WB", EFB_TC=> "DISABLED",
- SPI_WAKEUP=> "DISABLED", SPI_INTR_RXOVR=> "DISABLED",
- SPI_INTR_TXOVR=> "DISABLED", SPI_INTR_RXRDY=> "DISABLED",
- SPI_INTR_TXRDY=> "DISABLED", SPI_SLAVE_HANDSHAKE=> "DISABLED",
- SPI_PHASE_ADJ=> "DISABLED", SPI_CLK_INV=> "DISABLED",
- SPI_LSB_FIRST=> "DISABLED", SPI_CLK_DIVIDER=> 1, SPI_MODE=> "MASTER",
- EFB_SPI=> "DISABLED", I2C2_WAKEUP=> "DISABLED", I2C2_GEN_CALL=> "DISABLED",
- I2C2_CLK_DIVIDER=> 1, I2C2_BUS_PERF=> "100kHz", I2C2_SLAVE_ADDR=> "0b1000010",
- I2C2_ADDRESSING=> "7BIT", EFB_I2C2=> "DISABLED", I2C1_WAKEUP=> "DISABLED",
- I2C1_GEN_CALL=> "DISABLED", I2C1_CLK_DIVIDER=> 1, I2C1_BUS_PERF=> "100kHz",
- I2C1_SLAVE_ADDR=> "0b1000001", I2C1_ADDRESSING=> "7BIT",
- EFB_I2C1=> "DISABLED", EFB_WB_CLK_FREQ=> "33.3")
- port map (WBCLKI=>wb_clk_i, WBRSTI=>wb_rst_i, WBCYCI=>wb_cyc_i,
- WBSTBI=>wb_stb_i, WBWEI=>wb_we_i, WBADRI7=>wb_adr_i(7),
- WBADRI6=>wb_adr_i(6), WBADRI5=>wb_adr_i(5),
- WBADRI4=>wb_adr_i(4), WBADRI3=>wb_adr_i(3),
- WBADRI2=>wb_adr_i(2), WBADRI1=>wb_adr_i(1),
- WBADRI0=>wb_adr_i(0), WBDATI7=>wb_dat_i(7),
- WBDATI6=>wb_dat_i(6), WBDATI5=>wb_dat_i(5),
- WBDATI4=>wb_dat_i(4), WBDATI3=>wb_dat_i(3),
- WBDATI2=>wb_dat_i(2), WBDATI1=>wb_dat_i(1),
- WBDATI0=>wb_dat_i(0), PLL0DATI7=>scuba_vlo,
- PLL0DATI6=>scuba_vlo, PLL0DATI5=>scuba_vlo,
- PLL0DATI4=>scuba_vlo, PLL0DATI3=>scuba_vlo,
- PLL0DATI2=>scuba_vlo, PLL0DATI1=>scuba_vlo,
- PLL0DATI0=>scuba_vlo, PLL0ACKI=>scuba_vlo,
- PLL1DATI7=>scuba_vlo, PLL1DATI6=>scuba_vlo,
- PLL1DATI5=>scuba_vlo, PLL1DATI4=>scuba_vlo,
- PLL1DATI3=>scuba_vlo, PLL1DATI2=>scuba_vlo,
- PLL1DATI1=>scuba_vlo, PLL1DATI0=>scuba_vlo,
- PLL1ACKI=>scuba_vlo, I2C1SCLI=>scuba_vlo,
- I2C1SDAI=>scuba_vlo, I2C2SCLI=>scuba_vlo,
- I2C2SDAI=>scuba_vlo, SPISCKI=>scuba_vlo, SPIMISOI=>scuba_vlo,
- SPIMOSII=>scuba_vlo, SPISCSN=>scuba_vlo, TCCLKI=>scuba_vlo,
- TCRSTN=>scuba_vlo, TCIC=>scuba_vlo, UFMSN=>scuba_vhi,
- WBDATO7=>wb_dat_o(7), WBDATO6=>wb_dat_o(6),
- WBDATO5=>wb_dat_o(5), WBDATO4=>wb_dat_o(4),
- WBDATO3=>wb_dat_o(3), WBDATO2=>wb_dat_o(2),
- WBDATO1=>wb_dat_o(1), WBDATO0=>wb_dat_o(0), WBACKO=>wb_ack_o,
- PLLCLKO=>open, PLLRSTO=>open, PLL0STBO=>open, PLL1STBO=>open,
- PLLWEO=>open, PLLADRO4=>open, PLLADRO3=>open, PLLADRO2=>open,
- PLLADRO1=>open, PLLADRO0=>open, PLLDATO7=>open,
- PLLDATO6=>open, PLLDATO5=>open, PLLDATO4=>open,
- PLLDATO3=>open, PLLDATO2=>open, PLLDATO1=>open,
- PLLDATO0=>open, I2C1SCLO=>open, I2C1SCLOEN=>open,
- I2C1SDAO=>open, I2C1SDAOEN=>open, I2C2SCLO=>open,
- I2C2SCLOEN=>open, I2C2SDAO=>open, I2C2SDAOEN=>open,
- I2C1IRQO=>open, I2C2IRQO=>open, SPISCKO=>open,
- SPISCKEN=>open, SPIMISOO=>open, SPIMISOEN=>open,
- SPIMOSIO=>open, SPIMOSIEN=>open, SPIMCSN7=>open,
- SPIMCSN6=>open, SPIMCSN5=>open, SPIMCSN4=>open,
- SPIMCSN3=>open, SPIMCSN2=>open, SPIMCSN1=>open,
- SPIMCSN0=>open, SPICSNEN=>open, SPIIRQO=>open, TCINT=>open,
- TCOC=>open, WBCUFMIRQ=>wbc_ufm_irq, CFGWAKE=>open,
- CFGSTDBY=>open);
-
-end Structure;
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="flashram" module="RAM_DP_TRUE" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2012 08 09 14:41:35.856" version="7.1" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="" type="mem" modified="2012 08 09 14:41:35.000"/>
- <File name="flashram.lpc" type="lpc" modified="2012 08 09 14:41:31.000"/>
- <File name="flashram.vhd" type="top_level_vhdl" modified="2012 08 09 14:41:31.000"/>
- <File name="flashram_tmpl.vhd" type="template_vhdl" modified="2012 08 09 14:41:31.000"/>
- <File name="tb_flashram_tmpl.vhd" type="testbench_vhdl" modified="2012 08 09 14:41:32.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=machxo2
-PartType=LCMXO2-4000HC
-PartName=LCMXO2-4000HC-6FTG256C
-SpeedGrade=6
-Package=FTBGA256
-OperatingCondition=COM
-Status=S
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=RAM_DP_TRUE
-CoreRevision=7.1
-ModuleName=flashram
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=08/09/2012
-Time=14:41:31
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-RAddress=16
-RData=8
-WAddress=16
-WData=8
-ROutputEn=0
-RClockEn=0
-WOutputEn=0
-WClockEn=0
-enByte=0
-ByteSize=9
-Optimization=Area
-Reset=Sync
-Reset1=Sync
-Init=0
-MemFile=
-MemFormat=bin
-EnECC=0
-Pipeline=0
-WriteA=Normal
-WriteB=Normal
-init_data=0
-
-[FilesGenerated]
-=mem
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.4_Production (87)
--- Module Version: 7.1
---/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type bram -wp 11 -rp 1010 -data_width 8 -rdata_width 8 -num_rows 16 -cascade 11 -mem_init0 -writemodeA NORMAL -writemodeB NORMAL -e
-
--- Thu Aug 9 14:41:31 2012
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library MACHXO2;
-use MACHXO2.components.all;
--- synopsys translate_on
-
-entity flashram is
- port (
- DataInA: in std_logic_vector(7 downto 0);
- DataInB: in std_logic_vector(7 downto 0);
- AddressA: in std_logic_vector(3 downto 0);
- AddressB: in std_logic_vector(3 downto 0);
- ClockA: in std_logic;
- ClockB: in std_logic;
- ClockEnA: in std_logic;
- ClockEnB: in std_logic;
- WrA: in std_logic;
- WrB: in std_logic;
- ResetA: in std_logic;
- ResetB: in std_logic;
- QA: out std_logic_vector(7 downto 0);
- QB: out std_logic_vector(7 downto 0));
-end flashram;
-
-architecture Structure of flashram is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component DP8KC
- generic (INIT_DATA : in String; INITVAL_1F : in String;
- INITVAL_1E : in String; INITVAL_1D : in String;
- INITVAL_1C : in String; INITVAL_1B : in String;
- INITVAL_1A : in String; INITVAL_19 : in String;
- INITVAL_18 : in String; INITVAL_17 : in String;
- INITVAL_16 : in String; INITVAL_15 : in String;
- INITVAL_14 : in String; INITVAL_13 : in String;
- INITVAL_12 : in String; INITVAL_11 : in String;
- INITVAL_10 : in String; INITVAL_0F : in String;
- INITVAL_0E : in String; INITVAL_0D : in String;
- INITVAL_0C : in String; INITVAL_0B : in String;
- INITVAL_0A : in String; INITVAL_09 : in String;
- INITVAL_08 : in String; INITVAL_07 : in String;
- INITVAL_06 : in String; INITVAL_05 : in String;
- INITVAL_04 : in String; INITVAL_03 : in String;
- INITVAL_02 : in String; INITVAL_01 : in String;
- INITVAL_00 : in String; ASYNC_RESET_RELEASE : in String;
- RESETMODE : in String; GSR : in String;
- WRITEMODE_B : in String; WRITEMODE_A : in String;
- CSDECODE_B : in String; CSDECODE_A : in String;
- REGMODE_B : in String; REGMODE_A : in String;
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
- port (DIA8: in std_logic; DIA7: in std_logic;
- DIA6: in std_logic; DIA5: in std_logic;
- DIA4: in std_logic; DIA3: in std_logic;
- DIA2: in std_logic; DIA1: in std_logic;
- DIA0: in std_logic; ADA12: in std_logic;
- ADA11: in std_logic; ADA10: in std_logic;
- ADA9: in std_logic; ADA8: in std_logic;
- ADA7: in std_logic; ADA6: in std_logic;
- ADA5: in std_logic; ADA4: in std_logic;
- ADA3: in std_logic; ADA2: in std_logic;
- ADA1: in std_logic; ADA0: in std_logic; CEA: in std_logic;
- OCEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA2: in std_logic; CSA1: in std_logic;
- CSA0: in std_logic; RSTA: in std_logic;
- DIB8: in std_logic; DIB7: in std_logic;
- DIB6: in std_logic; DIB5: in std_logic;
- DIB4: in std_logic; DIB3: in std_logic;
- DIB2: in std_logic; DIB1: in std_logic;
- DIB0: in std_logic; ADB12: in std_logic;
- ADB11: in std_logic; ADB10: in std_logic;
- ADB9: in std_logic; ADB8: in std_logic;
- ADB7: in std_logic; ADB6: in std_logic;
- ADB5: in std_logic; ADB4: in std_logic;
- ADB3: in std_logic; ADB2: in std_logic;
- ADB1: in std_logic; ADB0: in std_logic; CEB: in std_logic;
- OCEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB2: in std_logic; CSB1: in std_logic;
- CSB0: in std_logic; RSTB: in std_logic;
- DOA8: out std_logic; DOA7: out std_logic;
- DOA6: out std_logic; DOA5: out std_logic;
- DOA4: out std_logic; DOA3: out std_logic;
- DOA2: out std_logic; DOA1: out std_logic;
- DOA0: out std_logic; DOB8: out std_logic;
- DOB7: out std_logic; DOB6: out std_logic;
- DOB5: out std_logic; DOB4: out std_logic;
- DOB3: out std_logic; DOB2: out std_logic;
- DOB1: out std_logic; DOB0: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute MEM_LPC_FILE of flashram_0_0_0_0 : label is "flashram.lpc";
- attribute MEM_INIT_FILE of flashram_0_0_0_0 : label is "INIT_ALL_0s";
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- flashram_0_0_0_0: DP8KC
- generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
- INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 9)
- port map (DIA8=>scuba_vlo, DIA7=>DataInA(7), DIA6=>DataInA(6),
- DIA5=>DataInA(5), DIA4=>DataInA(4), DIA3=>DataInA(3),
- DIA2=>DataInA(2), DIA1=>DataInA(1), DIA0=>DataInA(0),
- ADA12=>scuba_vlo, ADA11=>scuba_vlo, ADA10=>scuba_vlo,
- ADA9=>scuba_vlo, ADA8=>scuba_vlo, ADA7=>scuba_vlo,
- ADA6=>AddressA(3), ADA5=>AddressA(2), ADA4=>AddressA(1),
- ADA3=>AddressA(0), ADA2=>scuba_vlo, ADA1=>scuba_vlo,
- ADA0=>scuba_vhi, CEA=>ClockEnA, OCEA=>ClockEnA, CLKA=>ClockA,
- WEA=>WrA, CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo,
- RSTA=>ResetA, DIB8=>scuba_vlo, DIB7=>DataInB(7),
- DIB6=>DataInB(6), DIB5=>DataInB(5), DIB4=>DataInB(4),
- DIB3=>DataInB(3), DIB2=>DataInB(2), DIB1=>DataInB(1),
- DIB0=>DataInB(0), ADB12=>scuba_vlo, ADB11=>scuba_vlo,
- ADB10=>scuba_vlo, ADB9=>scuba_vlo, ADB8=>scuba_vlo,
- ADB7=>scuba_vlo, ADB6=>AddressB(3), ADB5=>AddressB(2),
- ADB4=>AddressB(1), ADB3=>AddressB(0), ADB2=>scuba_vlo,
- ADB1=>scuba_vlo, ADB0=>scuba_vhi, CEB=>ClockEnB,
- OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB2=>scuba_vlo,
- CSB1=>scuba_vlo, CSB0=>scuba_vlo, RSTB=>ResetB, DOA8=>open,
- DOA7=>QA(7), DOA6=>QA(6), DOA5=>QA(5), DOA4=>QA(4),
- DOA3=>QA(3), DOA2=>QA(2), DOA1=>QA(1), DOA0=>QA(0),
- DOB8=>open, DOB7=>QB(7), DOB6=>QB(6), DOB5=>QB(5),
- DOB4=>QB(4), DOB3=>QB(3), DOB2=>QB(2), DOB1=>QB(1),
- DOB0=>QB(0));
-
-end Structure;
-
--- synopsys translate_off
-library MACHXO2;
-configuration Structure_CON of flashram is
- for Structure
- for all:VHI use entity MACHXO2.VHI(V); end for;
- for all:VLO use entity MACHXO2.VLO(V); end for;
- for all:DP8KC use entity MACHXO2.DP8KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="oddr16" module="DDR_GENERIC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2012 08 03 16:02:26.912" version="5.2" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="oddr16.lpc" type="lpc" modified="2012 08 03 16:02:24.000"/>
- <File name="oddr16.vhd" type="top_level_vhdl" modified="2012 08 03 16:02:24.000"/>
- <File name="oddr16_tmpl.vhd" type="template_vhdl" modified="2012 08 03 16:02:24.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=machxo2
-PartType=LCMXO2-4000HC
-PartName=LCMXO2-4000HC-6FTG256C
-SpeedGrade=6
-Package=FTBGA256
-OperatingCondition=COM
-Status=S
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=DDR_GENERIC
-CoreRevision=5.2
-ModuleName=oddr16
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=08/03/2012
-Time=16:02:24
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-mode=Transmit
-io_type=LVTTL33
-num_int=8
-width=16
-freq_in=133
-bandwidth=4256
-aligned=Edge-to-Edge
-pre-configuration=DISABLED
-mode2=Transmit
-io_type2=LVTTL33
-freq_in2=133
-gear=1x
-aligned2=Edge-to-Edge
-num_int2=8
-width2=16
-Interface=GDDRX1_TX.SCLK.Aligned
-Delay=Bypass
-DelVal=
-UsePll=
-GenPll=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.4_Production (87)
--- Module Version: 5.2
---/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -n oddr16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type iol -mode out -io_type LVTTL33 -width 16 -freq_in 133 -gear 1 -clk sclk -aligned -del -1 -e
-
--- Fri Aug 3 16:02:24 2012
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library MACHXO2;
-use MACHXO2.components.all;
--- synopsys translate_on
-
-entity oddr16 is
- port (
- clk: in std_logic;
- clkout: out std_logic;
- reset: in std_logic;
- sclk: out std_logic;
- dataout: in std_logic_vector(31 downto 0);
- dout: out std_logic_vector(15 downto 0));
- attribute dont_touch : boolean;
- attribute dont_touch of oddr16 : entity is true;
-end oddr16;
-
-architecture Structure of oddr16 is
-
- -- internal signal declarations
- signal db15: std_logic;
- signal da15: std_logic;
- signal db14: std_logic;
- signal da14: std_logic;
- signal db13: std_logic;
- signal da13: std_logic;
- signal db12: std_logic;
- signal da12: std_logic;
- signal db11: std_logic;
- signal da11: std_logic;
- signal db10: std_logic;
- signal da10: std_logic;
- signal db9: std_logic;
- signal da9: std_logic;
- signal db8: std_logic;
- signal da8: std_logic;
- signal db7: std_logic;
- signal da7: std_logic;
- signal db6: std_logic;
- signal da6: std_logic;
- signal db5: std_logic;
- signal da5: std_logic;
- signal db4: std_logic;
- signal da4: std_logic;
- signal db3: std_logic;
- signal da3: std_logic;
- signal db2: std_logic;
- signal da2: std_logic;
- signal db1: std_logic;
- signal da1: std_logic;
- signal db0: std_logic;
- signal da0: std_logic;
- signal buf_clkout: std_logic;
- signal scuba_vlo: std_logic;
- signal scuba_vhi: std_logic;
- signal clkos: std_logic;
- signal clkop: std_logic;
- signal buf_douto15: std_logic;
- signal buf_douto14: std_logic;
- signal buf_douto13: std_logic;
- signal buf_douto12: std_logic;
- signal buf_douto11: std_logic;
- signal buf_douto10: std_logic;
- signal buf_douto9: std_logic;
- signal buf_douto8: std_logic;
- signal buf_douto7: std_logic;
- signal buf_douto6: std_logic;
- signal buf_douto5: std_logic;
- signal buf_douto4: std_logic;
- signal buf_douto3: std_logic;
- signal buf_douto2: std_logic;
- signal buf_douto1: std_logic;
- signal buf_douto0: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component OB
- port (I: in std_logic; O: out std_logic);
- end component;
- component ODDRXE
- port (D0: in std_logic; D1: in std_logic; SCLK: in std_logic;
- RST: in std_logic; Q: out std_logic);
- end component;
- attribute IO_TYPE : string;
- attribute IO_TYPE of Inst1_OB15 : label is "LVTTL33";
- attribute IO_TYPE of Inst1_OB14 : label is "LVTTL33";
- attribute IO_TYPE of Inst1_OB13 : label is "LVTTL33";
- attribute IO_TYPE of Inst1_OB12 : label is "LVTTL33";
- attribute IO_TYPE of Inst1_OB11 : label is "LVTTL33";
- attribute IO_TYPE of Inst1_OB10 : label is "LVTTL33";
- attribute IO_TYPE of Inst1_OB9 : label is "LVTTL33";
- attribute IO_TYPE of Inst1_OB8 : label is "LVTTL33";
- attribute IO_TYPE of Inst1_OB7 : label is "LVTTL33";
- attribute IO_TYPE of Inst1_OB6 : label is "LVTTL33";
- attribute IO_TYPE of Inst1_OB5 : label is "LVTTL33";
- attribute IO_TYPE of Inst1_OB4 : label is "LVTTL33";
- attribute IO_TYPE of Inst1_OB3 : label is "LVTTL33";
- attribute IO_TYPE of Inst1_OB2 : label is "LVTTL33";
- attribute IO_TYPE of Inst1_OB1 : label is "LVTTL33";
- attribute IO_TYPE of Inst1_OB0 : label is "LVTTL33";
- attribute syn_keep : boolean;
- attribute syn_noprune : boolean;
- attribute syn_noprune of Structure : architecture is true;
-
-begin
- -- component instantiation statements
- Inst3_ODDRXE15: ODDRXE
- port map (D0=>da15, D1=>db15, SCLK=>clkop, RST=>reset,
- Q=>buf_douto15);
-
- Inst3_ODDRXE14: ODDRXE
- port map (D0=>da14, D1=>db14, SCLK=>clkop, RST=>reset,
- Q=>buf_douto14);
-
- Inst3_ODDRXE13: ODDRXE
- port map (D0=>da13, D1=>db13, SCLK=>clkop, RST=>reset,
- Q=>buf_douto13);
-
- Inst3_ODDRXE12: ODDRXE
- port map (D0=>da12, D1=>db12, SCLK=>clkop, RST=>reset,
- Q=>buf_douto12);
-
- Inst3_ODDRXE11: ODDRXE
- port map (D0=>da11, D1=>db11, SCLK=>clkop, RST=>reset,
- Q=>buf_douto11);
-
- Inst3_ODDRXE10: ODDRXE
- port map (D0=>da10, D1=>db10, SCLK=>clkop, RST=>reset,
- Q=>buf_douto10);
-
- Inst3_ODDRXE9: ODDRXE
- port map (D0=>da9, D1=>db9, SCLK=>clkop, RST=>reset,
- Q=>buf_douto9);
-
- Inst3_ODDRXE8: ODDRXE
- port map (D0=>da8, D1=>db8, SCLK=>clkop, RST=>reset,
- Q=>buf_douto8);
-
- Inst3_ODDRXE7: ODDRXE
- port map (D0=>da7, D1=>db7, SCLK=>clkop, RST=>reset,
- Q=>buf_douto7);
-
- Inst3_ODDRXE6: ODDRXE
- port map (D0=>da6, D1=>db6, SCLK=>clkop, RST=>reset,
- Q=>buf_douto6);
-
- Inst3_ODDRXE5: ODDRXE
- port map (D0=>da5, D1=>db5, SCLK=>clkop, RST=>reset,
- Q=>buf_douto5);
-
- Inst3_ODDRXE4: ODDRXE
- port map (D0=>da4, D1=>db4, SCLK=>clkop, RST=>reset,
- Q=>buf_douto4);
-
- Inst3_ODDRXE3: ODDRXE
- port map (D0=>da3, D1=>db3, SCLK=>clkop, RST=>reset,
- Q=>buf_douto3);
-
- Inst3_ODDRXE2: ODDRXE
- port map (D0=>da2, D1=>db2, SCLK=>clkop, RST=>reset,
- Q=>buf_douto2);
-
- Inst3_ODDRXE1: ODDRXE
- port map (D0=>da1, D1=>db1, SCLK=>clkop, RST=>reset,
- Q=>buf_douto1);
-
- Inst3_ODDRXE0: ODDRXE
- port map (D0=>da0, D1=>db0, SCLK=>clkop, RST=>reset,
- Q=>buf_douto0);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- Inst2_ODDRXE: ODDRXE
- port map (D0=>scuba_vhi, D1=>scuba_vlo, SCLK=>clkos, RST=>reset,
- Q=>buf_clkout);
-
- Inst1_OB15: OB
- port map (I=>buf_douto15, O=>dout(15));
-
- Inst1_OB14: OB
- port map (I=>buf_douto14, O=>dout(14));
-
- Inst1_OB13: OB
- port map (I=>buf_douto13, O=>dout(13));
-
- Inst1_OB12: OB
- port map (I=>buf_douto12, O=>dout(12));
-
- Inst1_OB11: OB
- port map (I=>buf_douto11, O=>dout(11));
-
- Inst1_OB10: OB
- port map (I=>buf_douto10, O=>dout(10));
-
- Inst1_OB9: OB
- port map (I=>buf_douto9, O=>dout(9));
-
- Inst1_OB8: OB
- port map (I=>buf_douto8, O=>dout(8));
-
- Inst1_OB7: OB
- port map (I=>buf_douto7, O=>dout(7));
-
- Inst1_OB6: OB
- port map (I=>buf_douto6, O=>dout(6));
-
- Inst1_OB5: OB
- port map (I=>buf_douto5, O=>dout(5));
-
- Inst1_OB4: OB
- port map (I=>buf_douto4, O=>dout(4));
-
- Inst1_OB3: OB
- port map (I=>buf_douto3, O=>dout(3));
-
- Inst1_OB2: OB
- port map (I=>buf_douto2, O=>dout(2));
-
- Inst1_OB1: OB
- port map (I=>buf_douto1, O=>dout(1));
-
- Inst1_OB0: OB
- port map (I=>buf_douto0, O=>dout(0));
-
- sclk <= clkop;
- db15 <= dataout(31);
- db14 <= dataout(30);
- db13 <= dataout(29);
- db12 <= dataout(28);
- db11 <= dataout(27);
- db10 <= dataout(26);
- db9 <= dataout(25);
- db8 <= dataout(24);
- db7 <= dataout(23);
- db6 <= dataout(22);
- db5 <= dataout(21);
- db4 <= dataout(20);
- db3 <= dataout(19);
- db2 <= dataout(18);
- db1 <= dataout(17);
- db0 <= dataout(16);
- da15 <= dataout(15);
- da14 <= dataout(14);
- da13 <= dataout(13);
- da12 <= dataout(12);
- da11 <= dataout(11);
- da10 <= dataout(10);
- da9 <= dataout(9);
- da8 <= dataout(8);
- da7 <= dataout(7);
- da6 <= dataout(6);
- da5 <= dataout(5);
- da4 <= dataout(4);
- da3 <= dataout(3);
- da2 <= dataout(2);
- da1 <= dataout(1);
- da0 <= dataout(0);
- clkout <= buf_clkout;
- clkos <= clk;
- clkop <= clk;
-end Structure;
-
--- synopsys translate_off
-library MACHXO2;
-configuration Structure_CON of oddr16 is
- for Structure
- for all:VHI use entity MACHXO2.VHI(V); end for;
- for all:VLO use entity MACHXO2.VLO(V); end for;
- for all:OB use entity MACHXO2.OB(V); end for;
- for all:ODDRXE use entity MACHXO2.ODDRXE(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2012 09 05 14:55:16.102" version="5.2" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="pll.lpc" type="lpc" modified="2012 09 05 14:55:13.000"/>
- <File name="pll.vhd" type="top_level_vhdl" modified="2012 09 05 14:55:13.000"/>
- <File name="pll_tmpl.vhd" type="template_vhdl" modified="2012 09 05 14:55:13.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=machxo2
-PartType=LCMXO2-4000HC
-PartName=LCMXO2-4000HC-6FTG256C
-SpeedGrade=6
-Package=FTBGA256
-OperatingCondition=COM
-Status=S
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PLL
-CoreRevision=5.2
-ModuleName=pll
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/05/2012
-Time=14:55:13
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=None
-Order=None
-IO=0
-mode=Frequency
-CLKI=133
-CLKI_DIV=1
-fb_mode=INT_OP
-CLKFB_DIV=1
-FRACN_ENABLE=0
-FRACN_DIV=0
-DynamicPhase=STATIC
-ClkEnable=0
-Standby=0
-PLLRst=0
-PLLMRst=0
-ClkOS2Rst=0
-ClkOS3Rst=0
-LockSig=1
-LockStk=0
-WBProt=0
-OPBypass=1
-OPUseDiv=1
-CLKOP_DIV=5
-FREQ_PIN_CLKOP=33.33
-OP_Tol=5.0
-CLKOP_AFREQ=26.600000
-CLKOP_PHASEADJ=0
-CLKOP_TRIM_POL=Rising
-CLKOP_TRIM_DELAY=0
-EnCLKOS=1
-OSBypass=1
-OSUseDiv=0
-CLKOS_DIV=1
-FREQ_PIN_CLKOS=100
-OS_Tol=0.0
-CLKOS_AFREQ=133.000000
-CLKOS_PHASEADJ=0
-CLKOS_TRIM_POL=Rising
-CLKOS_TRIM_DELAY=0
-EnCLKOS2=0
-OS2Bypass=0
-OS2UseDiv=0
-CLKOS2_DIV=1
-FREQ_PIN_CLKOS2=100
-OS2_Tol=0.0
-CLKOS2_AFREQ=
-CLKOS2_PHASEADJ=0
-EnCLKOS3=0
-OS3Bypass=0
-OS3UseDiv=0
-CLKOS3_DIV=1
-FREQ_PIN_CLKOS3=100
-OS3_Tol=0.0
-CLKOS3_AFREQ=
-CLKOS3_PHASEADJ=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.4_Production (87)
--- Module Version: 5.2
---/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -n pll -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 133 -bypassp -bypass_divp -fclkop 26.6 -bypasss -phase_cntl STATIC -fb_mode 5 -lock -e
-
--- Wed Sep 5 14:55:13 2012
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library MACHXO2;
-use MACHXO2.components.all;
--- synopsys translate_on
-
-entity pll is
- port (
- CLKI: in std_logic;
- CLKOP: out std_logic;
- CLKOS: out std_logic;
- LOCK: out std_logic);
- attribute dont_touch : boolean;
- attribute dont_touch of pll : entity is true;
-end pll;
-
-architecture Structure of pll is
-
- -- internal signal declarations
- signal CLKOS_t: std_logic;
- signal CLKOP_t: std_logic;
- signal CLKFB_t: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VLO
- port (Z: out std_logic);
- end component;
- component EHXPLLJ
- generic (INTFB_WAKE : in String; DDRST_ENA : in String;
- DCRST_ENA : in String; MRST_ENA : in String;
- PLLRST_ENA : in String; DPHASE_SOURCE : in String;
- OUTDIVIDER_MUXD2 : in String;
- OUTDIVIDER_MUXC2 : in String;
- OUTDIVIDER_MUXB2 : in String;
- OUTDIVIDER_MUXA2 : in String;
- PREDIVIDER_MUXD1 : in Integer;
- PREDIVIDER_MUXC1 : in Integer;
- PREDIVIDER_MUXB1 : in Integer;
- PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String;
- PLL_LOCK_MODE : in Integer;
- CLKOS_TRIM_DELAY : in Integer;
- CLKOS_TRIM_POL : in String;
- CLKOP_TRIM_DELAY : in Integer;
- CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer;
- FRACN_ENABLE : in String; FEEDBK_PATH : in String;
- CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer;
- CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer;
- CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer;
- CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer;
- VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String;
- VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String;
- CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String;
- CLKOS_ENABLE : in String; CLKOP_ENABLE : in String;
- CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer;
- CLKOS_DIV : in Integer; CLKOP_DIV : in Integer;
- CLKFB_DIV : in Integer; CLKI_DIV : in Integer);
- port (CLKI: in std_logic; CLKFB: in std_logic;
- PHASESEL1: in std_logic; PHASESEL0: in std_logic;
- PHASEDIR: in std_logic; PHASESTEP: in std_logic;
- LOADREG: in std_logic; STDBY: in std_logic;
- PLLWAKESYNC: in std_logic; RST: in std_logic;
- RESETM: in std_logic; RESETC: in std_logic;
- RESETD: in std_logic; ENCLKOP: in std_logic;
- ENCLKOS: in std_logic; ENCLKOS2: in std_logic;
- ENCLKOS3: in std_logic; PLLCLK: in std_logic;
- PLLRST: in std_logic; PLLSTB: in std_logic;
- PLLWE: in std_logic; PLLADDR4: in std_logic;
- PLLADDR3: in std_logic; PLLADDR2: in std_logic;
- PLLADDR1: in std_logic; PLLADDR0: in std_logic;
- PLLDATI7: in std_logic; PLLDATI6: in std_logic;
- PLLDATI5: in std_logic; PLLDATI4: in std_logic;
- PLLDATI3: in std_logic; PLLDATI2: in std_logic;
- PLLDATI1: in std_logic; PLLDATI0: in std_logic;
- CLKOP: out std_logic; CLKOS: out std_logic;
- CLKOS2: out std_logic; CLKOS3: out std_logic;
- LOCK: out std_logic; INTLOCK: out std_logic;
- REFCLK: out std_logic; CLKINTFB: out std_logic;
- DPHSRC: out std_logic; PLLACK: out std_logic;
- PLLDATO7: out std_logic; PLLDATO6: out std_logic;
- PLLDATO5: out std_logic; PLLDATO4: out std_logic;
- PLLDATO3: out std_logic; PLLDATO2: out std_logic;
- PLLDATO1: out std_logic; PLLDATO0: out std_logic);
- end component;
- attribute STDBY_ENABLE : string;
- attribute FREQUENCY_PIN_CLKOS : string;
- attribute FREQUENCY_PIN_CLKOP : string;
- attribute FREQUENCY_PIN_CLKI : string;
- attribute ICP_CURRENT : string;
- attribute LPF_RESISTOR : string;
- attribute STDBY_ENABLE of PLLInst_0 : label is "DISABLED";
- attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "133.000000";
- attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "26.600000";
- attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "133.000000";
- attribute ICP_CURRENT of PLLInst_0 : label is "0";
- attribute LPF_RESISTOR of PLLInst_0 : label is "0";
- attribute syn_keep : boolean;
- attribute syn_noprune : boolean;
- attribute syn_noprune of Structure : architecture is true;
-
-begin
- -- component instantiation statements
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- PLLInst_0: EHXPLLJ
- generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED",
- MRST_ENA=> "DISABLED", PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
- DPHASE_SOURCE=> "DISABLED", PLL_USE_WB=> "DISABLED",
- CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0,
- CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 0,
- CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 4, PLL_LOCK_MODE=> 0,
- CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
- CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", FRACN_DIV=> 0,
- FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD",
- PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "DISABLED",
- OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=> 0, VCO_BYPASS_C0=> "DISABLED",
- CLKOS2_ENABLE=> "DISABLED", OUTDIVIDER_MUXB2=> "REFCLK",
- PREDIVIDER_MUXB1=> 0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "ENABLED",
- OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=> 0, VCO_BYPASS_A0=> "ENABLED",
- CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, CLKOS2_DIV=> 1,
- CLKOS_DIV=> 1, CLKOP_DIV=> 5, CLKFB_DIV=> 1, CLKI_DIV=> 1,
- FEEDBK_PATH=> "INT_DIVA")
- port map (CLKI=>CLKI, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo,
- PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
- PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo,
- PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, RESETM=>scuba_vlo,
- RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo,
- ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo,
- PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo,
- PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo,
- PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo,
- PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo,
- PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo,
- PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo,
- PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo,
- PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
- CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
- REFCLK=>open, CLKINTFB=>CLKFB_t, DPHSRC=>open, PLLACK=>open,
- PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open,
- PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open,
- PLLDATO1=>open, PLLDATO0=>open);
-
- CLKOS <= CLKOS_t;
- CLKOP <= CLKOP_t;
-end Structure;
-
--- synopsys translate_off
-library MACHXO2;
-configuration Structure_CON of pll is
- for Structure
- for all:VLO use entity MACHXO2.VLO(V); end for;
- for all:EHXPLLJ use entity MACHXO2.EHXPLLJ(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_shifted_clocks" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 01 20:16:48.328" version="5.4" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="pll_shifted_clocks.lpc" type="lpc" modified="2013 10 01 20:07:31.000"/>
- <File name="pll_shifted_clocks.vhd" type="top_level_vhdl" modified="2013 10 01 20:07:32.000"/>
- <File name="pll_shifted_clocks_tmpl.vhd" type="template_vhdl" modified="2013 10 01 20:07:32.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=machxo2
-PartType=LCMXO2-4000HC
-PartName=LCMXO2-4000HC-6FTG256C
-SpeedGrade=6
-Package=FTBGA256
-OperatingCondition=COM
-Status=S
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PLL
-CoreRevision=5.4
-ModuleName=pll_shifted_clocks
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=10/01/2013
-Time=20:07:31
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=None
-Order=None
-IO=0
-mode=Frequency
-CLKI=133
-CLKI_DIV=1
-BW=532.000
-VCO=10.504
-fb_mode=INT_OS3
-CLKFB_DIV=2
-FRACN_ENABLE=0
-FRACN_DIV=0
-DynamicPhase=STATIC
-ClkEnable=0
-Standby=0
-PLLRst=0
-PLLMRst=0
-ClkOS2Rst=0
-ClkOS3Rst=0
-LockSig=0
-LockStk=0
-WBProt=0
-OPBypass=0
-OPUseDiv=0
-CLKOP_DIV=2
-FREQ_PIN_CLKOP=266
-OP_Tol=10.0
-CLKOP_AFREQ=266.000000
-CLKOP_PHASEADJ=225
-CLKOP_TRIM_POL=Rising
-CLKOP_TRIM_DELAY=0
-EnCLKOS=1
-OSBypass=0
-OSUseDiv=0
-CLKOS_DIV=2
-FREQ_PIN_CLKOS=266
-OS_Tol=10.0
-CLKOS_AFREQ=266.000000
-CLKOS_PHASEADJ=270
-CLKOS_TRIM_POL=Rising
-CLKOS_TRIM_DELAY=0
-EnCLKOS2=1
-OS2Bypass=0
-OS2UseDiv=0
-CLKOS2_DIV=2
-FREQ_PIN_CLKOS2=266
-OS2_Tol=10.0
-CLKOS2_AFREQ=266.000000
-CLKOS2_PHASEADJ=315
-EnCLKOS3=1
-OS3Bypass=0
-OS3UseDiv=0
-CLKOS3_DIV=2
-FREQ_PIN_CLKOS3=266
-OS3_Tol=10.0
-CLKOS3_AFREQ=266.000000
-CLKOS3_PHASEADJ=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.2_Production (99)
--- Module Version: 5.4
---/d/jspc29/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n pll_shifted_clocks -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 133 -fclkop 266 -fclkop_tol 10.0 -fclkos 266 -fclkos_tol 10.0 -fclkos2 266 -fclkos2_tol 10.0 -fclkos3 266 -fclkos3_tol 10.0 -trimp 0 -phasep 225 -trimp_r -trims 0 -phases 270 -trims_r -phases2 315 -phases3 0 -phase_cntl STATIC -fb_mode 8 -e
-
--- Tue Oct 1 20:07:32 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library MACHXO2;
-use MACHXO2.components.all;
--- synopsys translate_on
-
-entity pll_shifted_clocks is
- port (
- CLKI: in std_logic;
- CLKOP: out std_logic;
- CLKOS: out std_logic;
- CLKOS2: out std_logic;
- CLKOS3: out std_logic);
- attribute dont_touch : boolean;
- attribute dont_touch of pll_shifted_clocks : entity is true;
-end pll_shifted_clocks;
-
-architecture Structure of pll_shifted_clocks is
-
- -- internal signal declarations
- signal LOCK: std_logic;
- signal CLKOS3_t: std_logic;
- signal CLKOS2_t: std_logic;
- signal CLKOS_t: std_logic;
- signal CLKOP_t: std_logic;
- signal CLKFB_t: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VLO
- port (Z: out std_logic);
- end component;
- component EHXPLLJ
- generic (INTFB_WAKE : in String; DDRST_ENA : in String;
- DCRST_ENA : in String; MRST_ENA : in String;
- PLLRST_ENA : in String; DPHASE_SOURCE : in String;
- STDBY_ENABLE : in String; OUTDIVIDER_MUXD2 : in String;
- OUTDIVIDER_MUXC2 : in String;
- OUTDIVIDER_MUXB2 : in String;
- OUTDIVIDER_MUXA2 : in String;
- PREDIVIDER_MUXD1 : in Integer;
- PREDIVIDER_MUXC1 : in Integer;
- PREDIVIDER_MUXB1 : in Integer;
- PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String;
- PLL_LOCK_MODE : in Integer;
- CLKOS_TRIM_DELAY : in Integer;
- CLKOS_TRIM_POL : in String;
- CLKOP_TRIM_DELAY : in Integer;
- CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer;
- FRACN_ENABLE : in String; FEEDBK_PATH : in String;
- CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer;
- CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer;
- CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer;
- CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer;
- VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String;
- VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String;
- CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String;
- CLKOS_ENABLE : in String; CLKOP_ENABLE : in String;
- CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer;
- CLKOS_DIV : in Integer; CLKOP_DIV : in Integer;
- CLKFB_DIV : in Integer; CLKI_DIV : in Integer);
- port (CLKI: in std_logic; CLKFB: in std_logic;
- PHASESEL1: in std_logic; PHASESEL0: in std_logic;
- PHASEDIR: in std_logic; PHASESTEP: in std_logic;
- LOADREG: in std_logic; STDBY: in std_logic;
- PLLWAKESYNC: in std_logic; RST: in std_logic;
- RESETM: in std_logic; RESETC: in std_logic;
- RESETD: in std_logic; ENCLKOP: in std_logic;
- ENCLKOS: in std_logic; ENCLKOS2: in std_logic;
- ENCLKOS3: in std_logic; PLLCLK: in std_logic;
- PLLRST: in std_logic; PLLSTB: in std_logic;
- PLLWE: in std_logic; PLLADDR4: in std_logic;
- PLLADDR3: in std_logic; PLLADDR2: in std_logic;
- PLLADDR1: in std_logic; PLLADDR0: in std_logic;
- PLLDATI7: in std_logic; PLLDATI6: in std_logic;
- PLLDATI5: in std_logic; PLLDATI4: in std_logic;
- PLLDATI3: in std_logic; PLLDATI2: in std_logic;
- PLLDATI1: in std_logic; PLLDATI0: in std_logic;
- CLKOP: out std_logic; CLKOS: out std_logic;
- CLKOS2: out std_logic; CLKOS3: out std_logic;
- LOCK: out std_logic; INTLOCK: out std_logic;
- REFCLK: out std_logic; CLKINTFB: out std_logic;
- DPHSRC: out std_logic; PLLACK: out std_logic;
- PLLDATO7: out std_logic; PLLDATO6: out std_logic;
- PLLDATO5: out std_logic; PLLDATO4: out std_logic;
- PLLDATO3: out std_logic; PLLDATO2: out std_logic;
- PLLDATO1: out std_logic; PLLDATO0: out std_logic);
- end component;
- attribute FREQUENCY_PIN_CLKOS3 : string;
- attribute FREQUENCY_PIN_CLKOS2 : string;
- attribute FREQUENCY_PIN_CLKOS : string;
- attribute FREQUENCY_PIN_CLKOP : string;
- attribute FREQUENCY_PIN_CLKI : string;
- attribute ICP_CURRENT : string;
- attribute LPF_RESISTOR : string;
- attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "266.000000";
- attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "266.000000";
- attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "266.000000";
- attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "266.000000";
- attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "133.000000";
- attribute ICP_CURRENT of PLLInst_0 : label is "10";
- attribute LPF_RESISTOR of PLLInst_0 : label is "24";
- attribute syn_keep : boolean;
- attribute syn_noprune : boolean;
- attribute syn_noprune of Structure : architecture is true;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- PLLInst_0: EHXPLLJ
- generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED",
- MRST_ENA=> "DISABLED", PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
- STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
- PLL_USE_WB=> "DISABLED", CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 1,
- CLKOS2_FPHASE=> 6, CLKOS2_CPHASE=> 2, CLKOS_FPHASE=> 4,
- CLKOS_CPHASE=> 2, CLKOP_FPHASE=> 2, CLKOP_CPHASE=> 2,
- PLL_LOCK_MODE=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
- CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", FRACN_DIV=> 0,
- FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD",
- PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "ENABLED",
- OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=> 0, VCO_BYPASS_C0=> "DISABLED",
- CLKOS2_ENABLE=> "ENABLED", OUTDIVIDER_MUXB2=> "DIVB",
- PREDIVIDER_MUXB1=> 0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "ENABLED",
- OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=> 0, VCO_BYPASS_A0=> "DISABLED",
- CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 2, CLKOS2_DIV=> 2,
- CLKOS_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 2, CLKI_DIV=> 1,
- FEEDBK_PATH=> "INT_DIVD")
- port map (CLKI=>CLKI, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo,
- PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
- PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo,
- PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, RESETM=>scuba_vlo,
- RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo,
- ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo,
- PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo,
- PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo,
- PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo,
- PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo,
- PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo,
- PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo,
- PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo,
- PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
- CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>LOCK,
- INTLOCK=>open, REFCLK=>open, CLKINTFB=>CLKFB_t, DPHSRC=>open,
- PLLACK=>open, PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open,
- PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open,
- PLLDATO1=>open, PLLDATO0=>open);
-
- CLKOS3 <= CLKOS3_t;
- CLKOS2 <= CLKOS2_t;
- CLKOS <= CLKOS_t;
- CLKOP <= CLKOP_t;
-end Structure;
-
--- synopsys translate_off
-library MACHXO2;
-configuration Structure_CON of pll_shifted_clocks is
- for Structure
- for all:VLO use entity MACHXO2.VLO(V); end for;
- for all:EHXPLLJ use entity MACHXO2.EHXPLLJ(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="1.3" title="panda_dirc_wasa" device="LCMXO2-4000HC-6FTG256C" default_implementation="panda_dirc_wasa">
- <Options/>
- <Implementation title="panda_dirc_wasa" dir="panda_dirc_wasa" description="panda_dirc_wasa" default_strategy="Strategy1">
- <Options top="panda_dirc_wasa"/>
- <Source name="panda_dirc_wasa.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="panda_dirc_wasa"/>
- </Source>
- <Source name="../base/trb3_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="source/spi_slave.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="version.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="cores/oddr16.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="source/pwm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="cores/efb_define_def.v" type="Verilog" type_short="Verilog">
- <Options/>
- </Source>
- <Source name="cores/UFM_WB_top.v" type="Verilog" type_short="Verilog">
- <Options/>
- </Source>
- <Source name="cores/pll.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="cores/flashram.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="cores/flash.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../base/panda_dirc_wasa1.lpf" type="Logic Preference" type_short="LPF">
- <Options/>
- </Source>
- </Implementation>
- <Strategy name="Strategy1" file="Strategy1.sty"/>
-</BaliProject>
+++ /dev/null
--w
--i 15
--l 5
--n 1
--y
--s 1
--t 11
--c 1
--e 2
--m nodelist.txt
-# -w
-# -i 6
-# -l 5
-# -n 1
-# -t 1
-# -s 1
-# -c 0
-# -e 0
-#
--exp parCDP=0:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
+++ /dev/null
-#-- Synopsys, Inc.
-#-- Version F-2012.03-SP1
-#-- Project file /d/jspc22/trb/cvs/trb3/wasa/panda_dirc_wasa/panda_dirc_wasa_syn.prj
-#-- Written on Mon Aug 6 18:53:10 2012
-
-
-
-#project files
-add_file -vhdl -lib work "/d/jspc29/lattice/diamond/2.2_x64/cae_library/synthesis/vhdl/machxo2.vhd"
-add_file -vhdl -lib work "../..//trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../base/trb3_components.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib work "source/spi_slave.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "source/pwm.vhd"
-add_file -vhdl -lib work "cores/pll_shifted_clocks.vhd"
-add_file -vhdl -lib work "cores/fifo_1kx8.vhd"
-add_file -vhdl -lib work "source/ffarray.vhd"
-
-
-add_file -vhdl -lib work "cores/oddr16.vhd"
-add_file -vhdl -lib work "cores/flash.vhd"
-add_file -vhdl -lib work "cores/flashram.vhd"
-add_file -vhdl -lib work "cores/pll.vhd"
-add_file -verilog -lib work "cores/efb_define_def.v"
-add_file -verilog -lib work "cores/UFM_WB.v"
-
-
-add_file -vhdl -lib work "panda_dirc_wasa.vhd"
-
-
-#implementation: "panda_dirc_wasa"
-impl -add workdir -type fpga
-
-#
-#implementation attributes
-
-set_option -vlog_std sysv
-set_option -project_relative_includes 1
-
-#device options
-set_option -technology MACHXO2
-set_option -part LCMXO2_4000HC
-set_option -package FTG256C
-set_option -speed_grade -6
-set_option -part_companion ""
-
-#compilation/mapping options
-
-# mapper_options
-set_option -frequency auto
-set_option -write_verilog 0
-set_option -write_vhdl 0
-
-# Lattice XP
-set_option -maxfan 1000
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 1
-set_option -forcegsr no
-set_option -fixgatedclocks 3
-set_option -fixgeneratedclocks 3
-set_option -update_models_cp 0
-
-# NFilter
-set_option -popfeed 0
-set_option -constprop 0
-set_option -createhierarchy 0
-
-# sequential_optimization_options
-set_option -symbolic_fsm_compiler 1
-
-# Compiler Options
-set_option -compiler_compatible 0
-set_option -resource_sharing 1
-set_option -multi_file_compilation_unit 1
-set_option -top_module "panda_dirc_wasa"
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "workdir/panda_dirc_wasa.edf"
-impl -active "workdir"
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb3_components.all;
-use work.version.all;
-
-library machxo2;
-use machxo2.all;
-
-
-entity panda_dirc_wasa is
- generic(
- PADIWA_FLAVOUR : integer := 3;
- TEMP_CORRECTION: integer := c_YES;
- TDCTEST : integer := c_NO
- );
- port(
- CON : out std_logic_vector(16 downto 1);
- INP : in std_logic_vector(16 downto 1);
- PWM : out std_logic_vector(16 downto 1);
- SPARE_LINE : out std_logic_vector(3 downto 0);
- SPARE_LVDS : out std_logic;
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SPI_CLK : in std_logic;
- SPI_CS : in std_logic;
- SPI_IN : in std_logic;
- SPI_OUT : out std_logic;
- TEMP_LINE : inout std_logic;
- TEST_LINE : out std_logic_vector(15 downto 0)
- );
-end entity;
-
-architecture panda_dirc_wasa_arch of panda_dirc_wasa is
-
-component OSCH
--- synthesis translate_off
- generic (NOM_FREQ: string := "133.00");
--- synthesis translate_on
- port (
- STDBY :IN std_logic;
- OSC :OUT std_logic;
- SEDSTDBY :OUT std_logic
- );
-end component;
-
-component oddr16 is
- port (
- clk: in std_logic;
- clkout: out std_logic;
- reset: in std_logic;
- sclk: out std_logic;
- dataout: in std_logic_vector(31 downto 0);
- dout: out std_logic_vector(15 downto 0));
-end component;
-
-component spi_slave
- port(
- CLK : in std_logic;
- SPI_CLK : in std_logic;
- SPI_CS : in std_logic;
- SPI_IN : in std_logic;
- SPI_OUT : out std_logic;
-
- DATA_OUT : out std_logic_vector(15 downto 0);
- REG00_IN : in std_logic_vector(15 downto 0);
- REG10_IN : in std_logic_vector(15 downto 0);
- REG20_IN : in std_logic_vector(15 downto 0);
- REG40_IN : in std_logic_vector(15 downto 0);
-
- OPERATION_OUT : out std_logic_vector(3 downto 0);
- CHANNEL_OUT : out std_logic_vector(7 downto 0);
- WRITE_OUT : out std_logic_vector(15 downto 0);
-
- DEBUG_OUT : out std_logic_vector(15 downto 0)
- );
-end component;
-
-
-component pwm_generator
- port(
- CLK : in std_logic;
- DATA_IN : in std_logic_vector(15 downto 0);
- DATA_OUT : out std_logic_vector(15 downto 0);
- COMP_IN : in signed(15 downto 0);
- WRITE_IN : in std_logic;
- ADDR_IN : in std_logic_vector(3 downto 0);
- PWM : out std_logic_vector(31 downto 0)
- );
-end component;
-
-component flashram
- port (
- DataInA: in std_logic_vector(7 downto 0);
- DataInB: in std_logic_vector(7 downto 0);
- AddressA: in std_logic_vector(3 downto 0);
- AddressB: in std_logic_vector(3 downto 0);
- ClockA: in std_logic;
- ClockB: in std_logic;
- ClockEnA: in std_logic;
- ClockEnB: in std_logic;
- WrA: in std_logic;
- WrB: in std_logic;
- ResetA: in std_logic;
- ResetB: in std_logic;
- QA: out std_logic_vector(7 downto 0);
- QB: out std_logic_vector(7 downto 0)
- );
-end component;
-
-component pll
- port (
- CLKI: in std_logic;
- CLKOP: out std_logic;
- CLKOS: out std_logic;
- LOCK: out std_logic);
-end component;
-
-
-component UFM_WB
- port(
- clk_i : in std_logic;
- rst_n : in std_logic;
- cmd : in std_logic_vector(2 downto 0);
- ufm_page : in std_logic_vector(12 downto 0);
- GO : in std_logic;
- BUSY : out std_logic;
- ERR : out std_logic;
- mem_clk : out std_logic;
- mem_we : out std_logic;
- mem_ce : out std_logic;
- mem_addr : out std_logic_vector(3 downto 0);
- mem_wr_data : out std_logic_vector(7 downto 0);
- mem_rd_data : in std_logic_vector(7 downto 0)
- );
-end component;
-
-component PUR port(PUR : in std_logic); end component;
-component GSR port(GSR : in std_logic); end component;
-
-
-
-attribute NOM_FREQ : string;
-attribute NOM_FREQ of clk_source : label is "133.00";
-signal clk_i : std_logic;
-
-signal reset_i : std_logic := '1';
-signal reset_cnt : unsigned(3 downto 0) := x"0";
-signal id_data_i : std_logic_vector(15 downto 0);
-signal id_addr_i : std_logic_vector(2 downto 0);
-signal id_write_i: std_logic;
-signal ram_write_i : std_logic;
-signal ram_data_i: std_logic_vector(7 downto 0);
-signal ram_data_o: std_logic_vector(7 downto 0);
-signal ram_addr_i: std_logic_vector(3 downto 0);
-signal temperature_i : std_logic_vector(11 downto 0);
-
-type idram_t is array(0 to 7) of std_logic_vector(15 downto 0);
-signal idram : idram_t;
-type ram_t is array(0 to 15) of std_logic_vector(15 downto 0);
-signal ram : ram_t;
-
-signal pwm_i : std_logic_vector(32 downto 1);
-signal INP_i : std_logic_vector(15 downto 0);
-signal spi_reg00_i : std_logic_vector(15 downto 0);
-signal spi_reg10_i : std_logic_vector(15 downto 0);
-signal spi_reg20_i : std_logic_vector(15 downto 0);
-signal spi_reg40_i : std_logic_vector(15 downto 0);
-signal spi_data_i : std_logic_vector(15 downto 0);
-signal spi_operation_i : std_logic_vector(3 downto 0);
-signal spi_channel_i : std_logic_vector(7 downto 0);
-signal spi_write_i : std_logic_vector(15 downto 0);
-signal buf_SPI_OUT : std_logic;
-signal spi_debug_i : std_logic_vector(15 downto 0);
-signal last_spi_channel: std_logic_vector(7 downto 0);
-
-signal pll_lock : std_logic;
-signal clk_26 : std_logic;
-signal clk_osc : std_logic;
-
-signal flashram_addr_i : std_logic_vector(3 downto 0);
-signal flashram_cen_i : std_logic;
-signal flashram_reset : std_logic;
-signal flashram_write_i: std_logic;
-signal flashram_data_i : std_logic_vector(7 downto 0);
-signal flashram_data_o : std_logic_vector(7 downto 0);
-
-signal flash_command : std_logic_vector(2 downto 0);
-signal flash_page : std_logic_vector(12 downto 0);
-signal flash_go : std_logic;
-signal flash_busy : std_logic;
-signal flash_err : std_logic;
-
-signal inp_select : integer range 0 to 31 := 0;
-signal inp_invert : std_logic_vector(15 downto 0);
-signal input_enable : std_logic_vector(15 downto 0);
-signal inp_status : std_logic_vector(15 downto 0);
-signal led_status : std_logic_vector(4 downto 0) := "10000";
-
-signal timer : unsigned(18 downto 0) := (others => '0');
-signal last_inp : std_logic_vector(3 downto 0) := (others => '0');
-signal leds : std_logic_vector(3 downto 0) := (others => '0');
-signal last_leds: std_logic_vector(3 downto 0) := (others => '0');
-signal onewire_monitor : std_logic;
-signal onewire_reset : std_logic;
-signal inp_or : std_logic;
-signal inp_long_or : std_logic;
-signal inp_long_reg : std_logic;
-signal last_inp_long_reg : std_logic;
-
-signal inp_stretch : std_logic_vector(15 downto 0);
-signal inp_stretched : std_logic_vector(15 downto 0);
-signal inp_hold : std_logic_vector(15 downto 0);
-signal inp_gated : std_logic_vector(15 downto 0);
-signal inp_hold_reg: std_logic_vector(15 downto 0);
-signal last_inp_hold_reg: std_logic_vector(15 downto 0);
-signal flash_go_tmp : std_logic_vector(5 downto 0);
-signal flash_reset_n : std_logic;
-
-signal pwm_data_i : std_logic_vector(15 downto 0);
-signal pwm_data_o : std_logic_vector(15 downto 0);
-signal pwm_write_i : std_logic;
-signal pwm_addr_i : std_logic_vector(3 downto 0);
-type fsm_state is (IDLE, PWM_WRITE_GET_1, PWM_WRITE_GET_2, PWM_WRITE, PWM_WAIT);
-signal fsm_copydat : fsm_state;
-
-signal pwm_fsm_data_i : std_logic_vector(15 downto 0);
-signal pwm_fsm_addr : std_logic_vector(3 downto 0);
-signal pwm_fsm_write : std_logic;
-signal fsm_job : std_logic_vector(1 downto 0);
-signal ram_fsm_data_i : std_logic_vector(7 downto 0);
-signal ram_fsm_addr_i : std_logic_vector(3 downto 0);
-signal ram_fsm_write_i: std_logic;
-
-signal enable_cfg_flash : std_logic;
-signal comp_setting : std_logic_vector(15 downto 0);
-signal compensate_i : signed(15 downto 0);
-signal temp_calc_i : signed(27 downto 0);
-signal temperature_i_s : std_logic_vector(11 downto 0);
-signal comp_setting_s : std_logic_vector(15 downto 0);
-
-signal ffarr_data : std_logic_vector(15 downto 0);
-signal ffarr_read : std_logic;
-
-begin
-
-
-THE_PLL : pll
- port map(
- CLKI => clk_osc,
- CLKOP => clk_26, --33
- CLKOS => clk_i, --133
- LOCK => pll_lock --no lock available!
- );
-
----------------------------------------------------------------------------
--- Clock
----------------------------------------------------------------------------
-clk_source: OSCH
--- synthesis translate_off
- generic map ( NOM_FREQ => "133.00" )
--- synthesis translate_on
- port map (
- STDBY => '0',
- OSC => clk_osc,
- SEDSTDBY => open
- );
-
----------------------------------------------------------------------------
--- Input re-ordering
----------------------------------------------------------------------------
-
-gen_outputs_1 : if PADIWA_FLAVOUR = 1 generate
- INP_i <= INP(16) & INP(8) & INP(15) & INP(7) & INP(14) & INP(6) & INP(13) & INP(5) &
- INP(12) & INP(4) & INP(11) & INP(3) & INP(10) & INP(2) & INP(9) & INP(1);
- PWM <= pwm_i(16) & pwm_i(14) & pwm_i(12) & pwm_i(10) & pwm_i(8) & pwm_i(6) & pwm_i(4) & pwm_i(2) &
- pwm_i(15) & pwm_i(13) & pwm_i(11) & pwm_i(9) & pwm_i(7) & pwm_i(5) & pwm_i(3) & pwm_i(1);
-end generate;
-
-
-gen_outputs_2 : if PADIWA_FLAVOUR = 2 generate
- INP_i <= INP;
- PWM <= pwm_i(16 downto 1);
-end generate;
-
-
-gen_outputs_3 : if PADIWA_FLAVOUR = 3 generate
- INP_i <= INP(9) & INP(1) & INP(10) & INP(2) & INP(11) & INP(3) & INP(12) & INP(4) &
- INP(13) & INP(5) & INP(14) & INP(6) & INP(15) & INP(7) & INP(16) & INP(8);
- PWM <= pwm_i(2) & pwm_i(4) & pwm_i(6) & pwm_i(8) & pwm_i(10) & pwm_i(12) & pwm_i(14) & pwm_i(16) &
- pwm_i(1) & pwm_i(3) & pwm_i(5) & pwm_i(7) & pwm_i(9) & pwm_i(11) & pwm_i(13) & pwm_i(15);
-end generate;
-
-
----------------------------------------------------------------------------
--- SPI Interface
----------------------------------------------------------------------------
-THE_SPI_SLAVE : spi_slave
- port map(
- CLK => clk_i,
- SPI_CLK => SPI_CLK,
- SPI_CS => SPI_CS,
- SPI_IN => SPI_IN,
- SPI_OUT => buf_SPI_OUT,
- DATA_OUT => spi_data_i,
- REG00_IN => spi_reg00_i,
- REG10_IN => spi_reg10_i,
- REG20_IN => spi_reg20_i,
- REG40_IN => spi_reg40_i,
- OPERATION_OUT => spi_operation_i,
- CHANNEL_OUT => spi_channel_i,
- WRITE_OUT => spi_write_i,
- DEBUG_OUT => spi_debug_i
- );
-
-SPI_OUT <= buf_SPI_OUT;
-
-spi_reg00_i <= pwm_data_o;
-spi_reg10_i <= idram(to_integer(unsigned(spi_channel_i(2 downto 0))));
-spi_reg40_i <= flash_busy & flash_err & "000000" & ram_data_o;
-
----------------------------------------------------------------------------
--- RAM Interface
----------------------------------------------------------------------------
---CFG-Flash: 0 - 5758
---UFM-Flash: 7167 - 7936
-
-PROC_CTRL_FLASH : process begin
- wait until rising_edge(clk_i);
- if(spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"0") then
- flash_command <= spi_data_i(15 downto 13);
- if(enable_cfg_flash = '1') then
- flash_page <= spi_data_i(12 downto 0);
- else
- flash_page <= "111" & spi_data_i(9 downto 0);
- end if;
- flash_go_tmp(0)<= '1';
- else
- flash_go_tmp(5 downto 0) <= flash_go_tmp(4 downto 0) & '0';
- end if;
- if flash_reset_n = '0' then
- flash_go_tmp <= (others => '0');
- end if;
-end process;
-
-PROC_CTRL_FLASH_ENABLE : process begin
- wait until rising_edge(clk_i);
- if(spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"C") then
- enable_cfg_flash <= spi_data_i(0);
- end if;
-end process;
-
-flash_go <= or_all(flash_go_tmp);
-
-
-THE_FLASH_RAM : flashram
- port map(
- DataInA => ram_data_i,
- DataInB => flashram_data_i,
- AddressA => ram_addr_i,
- AddressB => flashram_addr_i,
- ClockA => clk_i,
- ClockB => clk_26,
- ClockEnA => '1',
- ClockEnB => flashram_cen_i,
- WrA => ram_write_i,
- WrB => flashram_write_i,
- ResetA => '0',
- ResetB => flashram_reset,
- QA => ram_data_o,
- QB => flashram_data_o
- );
-
----------------------------------------------------------------------------
--- Flash Controller
----------------------------------------------------------------------------
-
-THE_FLASH : UFM_WB
- port map(
- clk_i => clk_26,
- rst_n => flash_reset_n,
- cmd => flash_command,
- ufm_page => flash_page,
- GO => flash_go,
- BUSY => flash_busy,
- ERR => flash_err,
- mem_clk => open,
- mem_we => flashram_write_i,
- mem_ce => flashram_cen_i,
- mem_addr => flashram_addr_i,
- mem_wr_data => flashram_data_i,
- mem_rd_data => flashram_data_o
- );
-
-PROC_DATA_COPY : process
- variable count : integer range 0 to 31 := 0;
- variable tmp : std_logic_vector(7 downto 0);
-begin
- wait until rising_edge(clk_i);
- pwm_fsm_write <= '0';
- ram_fsm_write_i <= '0';
- case fsm_copydat is
- when IDLE =>
- count := 0;
- if spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"1" then
- fsm_copydat <= PWM_WRITE_GET_1;
- ram_fsm_addr_i <= std_logic_vector(to_unsigned(count,4));
- fsm_job <= spi_channel_i(1 downto 0);
- count := count + 1;
- end if;
- when PWM_WRITE_GET_1 =>
- ram_fsm_addr_i <= std_logic_vector(to_unsigned(count,4));
- count := count + 1;
- fsm_copydat <= PWM_WRITE_GET_2;
- when PWM_WRITE_GET_2 =>
- fsm_copydat <= PWM_WRITE;
- tmp := ram_data_o;
- when PWM_WRITE =>
- pwm_fsm_data_i <= tmp & ram_data_o;
- pwm_fsm_write <= '1';
- pwm_fsm_addr <= fsm_job(0) & std_logic_vector(to_unsigned(count/2-1,3));
-
- if(count < 15) then
- fsm_copydat <= PWM_WRITE_GET_1;
- else
- fsm_copydat <= PWM_WAIT;
- end if;
-
- ram_fsm_addr_i <= std_logic_vector(to_unsigned(count,4));
- count := count + 1;
-
- when PWM_WAIT =>
- fsm_copydat <= IDLE;
- end case;
- if onewire_reset = '1' then
- fsm_copydat <= IDLE;
- end if;
-end process;
-
----------------------------------------------------------------------------
--- PWM
----------------------------------------------------------------------------
-
-THE_PWM_GEN : pwm_generator
- port map(
- CLK => clk_i,
- DATA_IN => pwm_data_i,
- DATA_OUT => pwm_data_o,
- COMP_IN => compensate_i,
- WRITE_IN => pwm_write_i,
- ADDR_IN => pwm_addr_i,
- PWM => pwm_i
- );
-
-
-
-PROC_PWM_DATA_MUX : process(fsm_copydat, spi_data_i, spi_write_i, spi_channel_i,
- pwm_fsm_addr, pwm_fsm_data_i, pwm_fsm_write,
- ram_fsm_addr_i, ram_fsm_data_i, ram_fsm_write_i)
-begin
- if(fsm_copydat = IDLE) then
- pwm_data_i <= spi_data_i;
- pwm_write_i <= spi_write_i(0);
- pwm_addr_i <= spi_channel_i(3 downto 0);
- ram_write_i <= spi_write_i(4);
- ram_data_i <= spi_data_i(7 downto 0);
- ram_addr_i <= spi_channel_i(3 downto 0);
- else
- pwm_data_i <= pwm_fsm_data_i;
- pwm_write_i <= pwm_fsm_write;
- pwm_addr_i <= pwm_fsm_addr;
- ram_write_i <= ram_fsm_write_i;
- ram_data_i <= ram_fsm_data_i;
- ram_addr_i <= ram_fsm_addr_i;
- end if;
-end process;
-
-
-gen_ffarr : if TDCTEST = 1 generate
- THE_FFARR : entity work.ffarray
- port map(
- CLK => clk_i,
- RESET_IN => onewire_reset,
- SIGNAL_IN => SPI_IN,
-
- DATA_OUT => ffarr_data(7 downto 0),
- READ_IN => ffarr_read,
- EMPTY_OUT => ffarr_data(12)
- );
-
- process begin
- wait until rising_edge(clk_i);
- last_spi_channel <= spi_channel_i;
- if spi_channel_i = x"0a" and last_spi_channel /= x"0a" then
- ffarr_read <= '1';
- else
- ffarr_read <= '0';
- end if;
- end process;
-
-end generate;
-
----------------------------------------------------------------------------
--- Temperature Sensor
----------------------------------------------------------------------------
-
-THE_ONEWIRE : trb_net_onewire
- generic map(
- USE_TEMPERATURE_READOUT => 1,
- PARASITIC_MODE => c_NO,
- CLK_PERIOD => 33
- )
- port map(
- CLK => clk_26,
- RESET => onewire_reset,
- READOUT_ENABLE_IN => '1',
- ONEWIRE => TEMP_LINE,
- MONITOR_OUT => onewire_monitor,
- --connection to id ram, according to memory map in TrbNetRegIO
- DATA_OUT => id_data_i,
- ADDR_OUT => id_addr_i,
- WRITE_OUT=> id_write_i,
- TEMP_OUT => temperature_i,
- ID_OUT => open,
- STAT => open
- );
-
-PROC_IDMEM : process begin
- wait until rising_edge(clk_i);
- if id_write_i = '1' then
- idram(to_integer(unsigned(id_addr_i))) <= id_data_i;
- else
- idram(4) <= "0000" & temperature_i;
- end if;
-
- if spi_write_i(1) = '1' then
- onewire_reset <= spi_data_i(0);
- end if;
-end process;
-
-flash_reset_n <= not onewire_reset;
-
----------------------------------------------------------------------------
--- I/O Register 0x20
----------------------------------------------------------------------------
-THE_IO_REG_READ : process begin
- wait until rising_edge(clk_i);
- if spi_channel_i(4) = '0' then
- case spi_channel_i(3 downto 0) is
- when x"0" => spi_reg20_i <= input_enable;
- when x"1" => spi_reg20_i <= inp_status;
- when x"2" => spi_reg20_i <= x"00" & "000" & led_status(4) & leds;
- when x"3" => spi_reg20_i <= x"00" & "000" & std_logic_vector(to_unsigned(inp_select,5));
- when x"4" => spi_reg20_i <= inp_invert;
- when x"5" => spi_reg20_i <= inp_stretch;
- when x"6" => spi_reg20_i <= comp_setting;
- when x"f" => spi_reg20_i <= ffarr_data;
- when others => null;
- end case;
- else
- case spi_channel_i(3 downto 0) is
- when x"0" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16));
- when x"1" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));
- when x"2" => spi_reg20_i <= x"000" & std_logic_vector(to_unsigned(PADIWA_FLAVOUR,4));
- when others => null;
- end case;
- end if;
-end process;
-
-THE_IO_REG_WRITE : process begin
- wait until rising_edge(clk_i);
- if spi_write_i(2) = '1' then
- case spi_channel_i(3 downto 0) is
- when x"0" => input_enable <= spi_data_i;
- when x"1" => null;
- when x"2" => led_status <= spi_data_i(4 downto 0);
- when x"3" => inp_select <= to_integer(unsigned(spi_data_i(4 downto 0)));
- when x"4" => inp_invert <= spi_data_i;
- when x"5" => inp_stretch <= spi_data_i;
- when x"6" => comp_setting <= spi_data_i;
- when others => null;
- end case;
- end if;
-end process;
-
-inp_status <= INP_i when rising_edge(clk_i);
-last_inp <= inp_status(3 downto 0) when rising_edge(clk_i);
-
-temperature_i_s <= temperature_i when rising_edge(clk_26);
-comp_setting_s <= comp_setting when rising_edge(clk_26);
-temp_calc_i <= signed(temperature_i_s) * signed(comp_setting_s) when rising_edge(clk_26);
-
-gen_comp: if TEMP_CORRECTION = 1 generate
- compensate_i <= temp_calc_i(27 downto 12) when rising_edge(clk_26);
-end generate;
-gen_no_comp: if TEMP_CORRECTION = 0 generate
- compensate_i <= (others => '0');
-end generate;
-
-
----------------------------------------------------------------------------
--- LED blinking when activity on inputs
----------------------------------------------------------------------------
-PROC_TIMER : process begin
- wait until rising_edge(clk_i);
- timer <= timer + 1;
- leds <= (last_inp xor inp_status(3 downto 0)) or leds or last_leds;
- if timer = 0 then
- leds <= not inp_status(3 downto 0);
- last_leds <= x"0";
- end if;
-end process;
-
-
----------------------------------------------------------------------------
--- Rest of the I/O
----------------------------------------------------------------------------
-
-inp_gated <= (INP_i xor inp_invert) and not input_enable;
-CON <= inp_gated or (inp_stretched and inp_stretch);
-
-
-
-SPARE_LINE(0) <= '0'; --clk_26;
-SPARE_LINE(1) <= '0'; --clk_i;
-SPARE_LINE(2) <= '0'; --timer(18);
-SPARE_LINE(3) <= '0';
-
-
-inp_hold <= (inp_gated or inp_hold) and not inp_hold_reg;
-inp_hold_reg <= inp_hold when rising_edge(clk_i);
-last_inp_hold_reg <= inp_hold_reg when rising_edge(clk_i);
-inp_stretched <= inp_hold_reg or last_inp_hold_reg or inp_hold;
-
-
-
-
-
-SPARE_OUTPUT : process(INP_i, inp_select, inp_or, inp_long_or, inp_long_reg, last_inp_long_reg)
- begin
- if inp_select < 16 then
- SPARE_LVDS <= INP_i(inp_select);
- elsif inp_select < 24 then
- SPARE_LVDS <= inp_or;
- else
- SPARE_LVDS <= inp_long_reg or last_inp_long_reg or inp_long_or ;
- end if;
- end process;
-
-inp_or <= or_all((INP_i xor inp_invert) and not input_enable);
-inp_long_or <= (inp_or or inp_long_or) and not inp_long_reg;
-inp_long_reg <= inp_long_or when rising_edge(clk_i);
-last_inp_long_reg <= inp_long_reg when rising_edge(clk_i);
-
--- ll_inp_long_reg <= last_inp_long_reg when rising_edge(clk_i);
-
-
--- TEST_LINE(0) <= '0';
--- TEST_LINE(15 downto 1) <= (others => '0');
-
--- TEST_LINE(0) <= '0';
--- TEST_LINE(1) <= spi_write_i(5);
--- TEST_LINE(2) <= pwm_write_i;
--- TEST_LINE(3) <= ram_write_i;
--- TEST_LINE(7 downto 4) <= pwm_addr_i;
--- TEST_LINE(11 downto 8) <= ram_addr_i;
--- TEST_LINE(12) <= spi_write_i(4);
--- TEST_LINE(13) <= ;
--- TEST_LINE(14) <= '1' when fsm_copydat = PWM_WRITE_GET_1 or fsm_copydat = PWM_WRITE_GET_2 else '0';
--- TEST_LINE(15) <= '1' when fsm_copydat = PWM_WRITE_GET_2 or fsm_copydat = PWM_WRITE else '0';
-
-
-TEST_LINE <= (others => '0');
-
-
-LED_GREEN <= not leds(0) when led_status(4) = '1' else not led_status(0);
-LED_ORANGE <= not leds(1) when led_status(4) = '1' else not led_status(1);
-LED_RED <= not leds(2) when led_status(4) = '1' else not led_status(2);
-LED_YELLOW <= not leds(3) when led_status(4) = '1' else not led_status(3);
-
-end architecture;
-
-
-
-
--- PWM_ODDR : oddr16
--- port map(
--- clk => clk_i,
--- clkout => open,
--- reset => '0',
--- sclk => open,
--- dataout => pwm_i,
--- dout => PWM
--- );
-
--- PROC_RESET : process begin
--- wait until rising_edge(clk_osc);
--- reset_i <= not pll_lock;
--- -- if reset_cnt /= x"F" then
--- -- reset_cnt <= reset_cnt + 1;
--- -- reset_i <= '1';
--- -- end if;
--- end process;
-
-
--- process(inp_gated,clk_i);
--- begin
--- if inp_gated(i) then
--- inp_hold(i) <= inp_gated(i);
--- elsif rising_edge(clk_i) then
--- inp_hold(i) <= inp_hold(i) and not inp_hold_reg(i);
--- end if;
--- end process;
---
+++ /dev/null
-FREQUENCY NET clk_i_c 133 MHz;
-
-
-
-UGROUP "ffarr0group"
- BLKNAME gen_ffarr_THE_FFARR/ffarr_0_0
- BLKNAME gen_ffarr_THE_FFARR/ffarr_1_0
- BLKNAME gen_ffarr_THE_FFARR/ffarr_2_0
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_1_ffarr_0_1
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_2_ffarr_0_2
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_3_ffarr_0_3
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_4_ffarr_0_4
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_5_ffarr_0_5
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_6_ffarr_0_6
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_7_ffarr_0_7;
-
-UGROUP "ffarr12group"
- BLKNAME gen_ffarr_THE_FFARR/ffarr_1_0
- BLKNAME gen_ffarr_THE_FFARR/ffarr_2_0
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_1_ffarr_1_1
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_1_ffarr_2_1
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_2_ffarr_1_2
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_2_ffarr_2_2
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_3_ffarr_1_3
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_3_ffarr_2_3
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_4_ffarr_1_4
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_4_ffarr_2_4
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_5_ffarr_1_5
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_5_ffarr_2_5
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_6_ffarr_1_6
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_6_ffarr_2_6
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_7_ffarr_1_7
- BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_7_ffarr_2_7;
-
-
-REGION "FFARR0" "R19C26" 1 2 DEVSIZE;
-REGION "FFARR12" "R20C26" 1 2 DEVSIZE;
-LOCATE UGROUP "ffarr0group" REGION "FFARR0";
-LOCATE UGROUP "ffarr12group" REGION "FFARR12";
-
-USE PRIMARY NET "gen_ffarr_THE_FFARR/CLKa*";
-USE PRIMARY NET "gen_ffarr_THE_FFARR_CLKa*";
-USE PRIMARY NET "gen_ffarr_THE_FFARR/CLKa_0";
-USE PRIMARY NET "gen_ffarr_THE_FFARR/CLKa_1";
-USE PRIMARY NET "gen_ffarr_THE_FFARR/CLKa_2";
-USE PRIMARY NET "gen_ffarr_THE_FFARR/CLKa_3";
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="2.0" title="padiwa" device="LCMXO2-4000HC-6FTG256C" synthesis="synplify" default_implementation="padiwa">
- <Options/>
- <Implementation title="padiwa" dir="padiwa" description="padiwa" default_strategy="Strategy1">
- <Options def_top="panda_dirc_wasa" top="panda_dirc_wasa"/>
- <Source name="../version.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../panda_dirc_wasa.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="panda_dirc_wasa"/>
- </Source>
- <Source name="../source/ffarray.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../source/pwm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../source/spi_slave.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../cores/efb_define_def.v" type="Verilog" type_short="Verilog">
- <Options/>
- </Source>
- <Source name="../cores/fifo_1kx8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../cores/flash.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../cores/flashram.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../cores/pll_shifted_clocks.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../cores/pll.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../cores/UFM_WB.v" type="Verilog" type_short="Verilog">
- <Options/>
- </Source>
- <Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../workdir/panda_dirc_wasa.lpf" type="Logic Preference" type_short="LPF">
- <Options/>
- </Source>
- </Implementation>
- <Strategy name="Strategy1" file="padiwa1.sty"/>
-</BaliProject>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<!DOCTYPE strategy>
-<Strategy version="1.0" predefined="0" description="" label="Strategy1">
- <Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
- <Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
- <Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
- <Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
- <Property name="PROP_BD_EdfMemPath" value="" time="0"/>
- <Property name="PROP_BD_ParSearchPath" value="" time="0"/>
- <Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
- <Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
- <Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
- <Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
- <Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
- <Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
- <Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
- <Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
- <Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
- <Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
- <Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
- <Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
- <Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
- <Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
- <Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
- <Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
- <Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
- <Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
- <Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
- <Property name="PROP_BIT_NoHeader" value="False" time="0"/>
- <Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
- <Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
- <Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
- <Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
- <Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
- <Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
- <Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
- <Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
- <Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
- <Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
- <Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
- <Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
- <Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
- <Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
- <Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
- <Property name="PROP_LST_CarryChain" value="True" time="0"/>
- <Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
- <Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
- <Property name="PROP_LST_EBRUtil" value="100" time="0"/>
- <Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
- <Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
- <Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
- <Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
- <Property name="PROP_LST_EdfMemPath" value="" time="0"/>
- <Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
- <Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
- <Property name="PROP_LST_IOInsertion" value="True" time="0"/>
- <Property name="PROP_LST_InterFileDump" value="False" time="0"/>
- <Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
- <Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
- <Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
- <Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
- <Property name="PROP_LST_PrfOutput" value="False" time="0"/>
- <Property name="PROP_LST_PropagatConst" value="True" time="0"/>
- <Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
- <Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
- <Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
- <Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
- <Property name="PROP_LST_ResourceShare" value="True" time="0"/>
- <Property name="PROP_LST_UseIOReg" value="True" time="0"/>
- <Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
- <Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
- <Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
- <Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
- <Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
- <Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
- <Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
- <Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
- <Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
- <Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
- <Property name="PROP_MAP_GuideFileMapDes" value="" time="0"/>
- <Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
- <Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
- <Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
- <Property name="PROP_MAP_MapModArgs" value="" time="0"/>
- <Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
- <Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
- <Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
- <Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
- <Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
- <Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
- <Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
- <Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
- <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
- <Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
- <Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
- <Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
- <Property name="PROP_PARSTA_FullName" value="False" time="0"/>
- <Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
- <Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
- <Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
- <Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
- <Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
- <Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
- <Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
- <Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
- <Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
- <Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
- <Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
- <Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
- <Property name="PROP_PAR_PARModArgs" value="" time="0"/>
- <Property name="PROP_PAR_ParGuideRepMatch" value="False" time="0"/>
- <Property name="PROP_PAR_ParMatchFact" value="" time="0"/>
- <Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
- <Property name="PROP_PAR_ParNCDGuideFile" value="" time="0"/>
- <Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
- <Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
- <Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
- <Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
- <Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
- <Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
- <Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
- <Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
- <Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
- <Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
- <Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
- <Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
- <Property name="PROP_PAR_StopZero" value="False" time="0"/>
- <Property name="PROP_PAR_parHold" value="On" time="0"/>
- <Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
- <Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
- <Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
- <Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
- <Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
- <Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
- <Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
- <Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
- <Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
- <Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
- <Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
- <Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
- <Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
- <Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
- <Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
- <Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
- <Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
- <Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
- <Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
- <Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
- <Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
- <Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
- <Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
- <Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
- <Property name="PROP_PRE_VSynOutPref" value="False" time="0"/>
- <Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
- <Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
- <Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
- <Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
- <Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
- <Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
- <Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
- <Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
- <Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
- <Property name="PROP_SYN_EdfArea" value="True" time="0"/>
- <Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
- <Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
- <Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
- <Property name="PROP_SYN_EdfFrequency" value="" time="0"/>
- <Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
- <Property name="PROP_SYN_EdfInPrfWrite" value="True" time="0"/>
- <Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
- <Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
- <Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
- <Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
- <Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
- <Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
- <Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
- <Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
- <Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
- <Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
- <Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
- <Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
- <Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
- <Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
- <Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
- <Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
- <Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
- <Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
- <Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
- <Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
- <Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
- <Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
- <Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
-</Strategy>
+++ /dev/null
-; Copyright 1991-2011 Mentor Graphics Corporation
-;
-; All Rights Reserved.
-;
-; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
-; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
-;
-
-[Library]
-std = $MODEL_TECH/../std
-ieee = $MODEL_TECH/../ieee
-vital2000 = $MODEL_TECH/../vital2000
-;
-; VITAL concerns:
-;
-; The library ieee contains (among other packages) the packages of the
-; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use
-; the physical library ieee (recommended), or use the physical library
-; vital2000, but not both. The design can use logical library ieee and/or
-; vital2000 as long as each of these maps to the same physical library, either
-; ieee or vital2000.
-;
-; A design using the 1995 version of the VITAL packages, whether or not
-; it also uses the 2000 version of the VITAL packages, must have logical library
-; name ieee mapped to physical library vital1995. (A design cannot use library
-; vital1995 directly because some packages in this library use logical name ieee
-; when referring to the other packages in the library.) The design source
-; should use logical name ieee when referring to any packages there except the
-; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical
-; name vital2000 (mapped to physical library vital2000) to refer to those
-; packages.
-; ieee = $MODEL_TECH/../vital1995
-;
-; For compatiblity with previous releases, logical library name vital2000 maps
-; to library vital2000 (a different library than library ieee, containing the
-; same packages).
-; A design should not reference VITAL from both the ieee library and the
-; vital2000 library because the vital packages are effectively different.
-; A design that references both the ieee and vital2000 libraries must have
-; both logical names ieee and vital2000 mapped to the same library, either of
-; these:
-; $MODEL_TECH/../ieee
-; $MODEL_TECH/../vital2000
-;
-verilog = $MODEL_TECH/../verilog
-std_developerskit = $MODEL_TECH/../std_developerskit
-synopsys = $MODEL_TECH/../synopsys
-modelsim_lib = $MODEL_TECH/../modelsim_lib
-sv_std = $MODEL_TECH/../sv_std
-mtiAvm = $MODEL_TECH/../avm
-mtiOvm = $MODEL_TECH/../ovm-2.1.2
-mtiUvm = $MODEL_TECH/../uvm-1.1
-mtiUPF = $MODEL_TECH/../upf_lib
-mtiPA = $MODEL_TECH/../pa_lib
-floatfixlib = $MODEL_TECH/../floatfixlib
-mc2_lib = $MODEL_TECH/../mc2_lib
-;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
-;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
-;mvc_lib = $MODEL_TECH/../mvc_lib
-
-machxo2 = /d/jspc29/lattice/diamond/1.4.2.105/ispfpga/vhdl/data/machxo2/mti/machxo2
-work = work
-ecp3 = /d/jspc29/lattice/diamond/2.01/ispfpga/vhdl/data/ecp3/mti/work
-[vcom]
-; VHDL93 variable selects language version as the default.
-; Default is VHDL-2002.
-; Value of 0 or 1987 for VHDL-1987.
-; Value of 1 or 1993 for VHDL-1993.
-; Default or value of 2 or 2002 for VHDL-2002.
-; Value of 3 or 2008 for VHDL-2008
-VHDL93 = 2002
-
-; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off.
-; ignoreStandardRealVector = 1
-
-; Show source line containing error. Default is off.
-; Show_source = 1
-
-; Turn off unbound-component warnings. Default is on.
-; Show_Warning1 = 0
-
-; Turn off process-without-a-wait-statement warnings. Default is on.
-; Show_Warning2 = 0
-
-; Turn off null-range warnings. Default is on.
-; Show_Warning3 = 0
-
-; Turn off no-space-in-time-literal warnings. Default is on.
-; Show_Warning4 = 0
-
-; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
-; Show_Warning5 = 0
-
-; Turn off optimization for IEEE std_logic_1164 package. Default is on.
-; Optimize_1164 = 0
-
-; Turn on resolving of ambiguous function overloading in favor of the
-; "explicit" function declaration (not the one automatically created by
-; the compiler for each type declaration). Default is off.
-; The .ini file has Explicit enabled so that std_logic_signed/unsigned
-; will match the behavior of synthesis tools.
-Explicit = 1
-
-; Turn off acceleration of the VITAL packages. Default is to accelerate.
-; NoVital = 1
-
-; Turn off VITAL compliance checking. Default is checking on.
-; NoVitalCheck = 1
-
-; Ignore VITAL compliance checking errors. Default is to not ignore.
-; IgnoreVitalErrors = 1
-
-; Turn off VITAL compliance checking warnings. Default is to show warnings.
-; Show_VitalChecksWarnings = 0
-
-; Turn off PSL assertion warning messages. Default is to show warnings.
-; Show_PslChecksWarnings = 0
-
-; Enable parsing of embedded PSL assertions. Default is enabled.
-; EmbeddedPsl = 0
-
-; Keep silent about case statement static warnings.
-; Default is to give a warning.
-; NoCaseStaticError = 1
-
-; Keep silent about warnings caused by aggregates that are not locally static.
-; Default is to give a warning.
-; NoOthersStaticError = 1
-
-; Treat as errors:
-; case statement static warnings
-; warnings caused by aggregates that are not locally static
-; Overrides NoCaseStaticError, NoOthersStaticError settings.
-; PedanticErrors = 1
-
-; Turn off inclusion of debugging info within design units.
-; Default is to include debugging info.
-; NoDebug = 1
-
-; Turn off "Loading..." messages. Default is messages on.
-; Quiet = 1
-
-; Turn on some limited synthesis rule compliance checking. Checks only:
-; -- signals used (read) by a process must be in the sensitivity list
-; CheckSynthesis = 1
-
-; Activate optimizations on expressions that do not involve signals,
-; waits, or function/procedure/task invocations. Default is off.
-; ScalarOpts = 1
-
-; Turns on lint-style checking.
-; Show_Lint = 1
-
-; Require the user to specify a configuration for all bindings,
-; and do not generate a compile time default binding for the
-; component. This will result in an elaboration error of
-; 'component not bound' if the user fails to do so. Avoids the rare
-; issue of a false dependency upon the unused default binding.
-; RequireConfigForAllDefaultBinding = 1
-
-; Perform default binding at compile time.
-; Default is to do default binding at load time.
-; BindAtCompile = 1;
-
-; Inhibit range checking on subscripts of arrays. Range checking on
-; scalars defined with subtypes is inhibited by default.
-; NoIndexCheck = 1
-
-; Inhibit range checks on all (implicit and explicit) assignments to
-; scalar objects defined with subtypes.
-; NoRangeCheck = 1
-
-; Run the 0-in compiler on the VHDL source files
-; Default is off.
-; ZeroIn = 1
-
-; Set the options to be passed to the 0-in compiler.
-; Default is "".
-; ZeroInOptions = ""
-
-; Set the synthesis prefix to be honored for synthesis pragma recognition.
-; Default is "".
-; SynthPrefix = ""
-
-; Turn on code coverage in VHDL design units. Default is off.
-; Coverage = sbceft
-
-; Turn off code coverage in VHDL subprograms. Default is on.
-; CoverageSub = 0
-
-; Automatically exclude VHDL case statement OTHERS choice branches.
-; This includes OTHERS choices in selected signal assigment statements.
-; Default is to not exclude.
-; CoverExcludeDefault = 1
-
-; Control compiler and VOPT optimizations that are allowed when
-; code coverage is on. Refer to the comment for this in the [vlog] area.
-; CoverOpt = 3
-
-; Turn on or off clkOpt optimization for code coverage. Default is on.
-; CoverClkOpt = 1
-
-; Turn on or off clkOpt optimization builtins for code coverage. Default is on.
-; CoverClkOptBuiltins = 0
-
-; Inform code coverage optimizations to respect VHDL 'H' and 'L'
-; values on signals in conditions and expressions, and to not automatically
-; convert them to '1' and '0'. Default is to not convert.
-; CoverRespectHandL = 0
-
-; Increase or decrease the maximum number of rows allowed in a UDP table
-; implementing a VHDL condition coverage or expression coverage expression.
-; More rows leads to a longer compile time, but more expressions covered.
-; CoverMaxUDPRows = 192
-
-; Increase or decrease the maximum number of input patterns that are present
-; in FEC table. This leads to a longer compile time with more expressions
-; covered with FEC metric.
-; CoverMaxFECRows = 192
-
-; Enable or disable Focused Expression Coverage analysis for conditions and
-; expressions. Focused Expression Coverage data is provided by default when
-; expression and/or condition coverage is active.
-; CoverFEC = 0
-
-; Enable or disable UDP Coverage analysis for conditions and expressions.
-; UDP Coverage data is provided by default when expression and/or condition
-; coverage is active.
-; CoverUDP = 0
-
-; Enable or disable short circuit evaluation of conditions and expressions when
-; condition or expression coverage is active. Short circuit evaluation is enabled
-; by default.
-; CoverShortCircuit = 0
-
-; Enable code coverage reporting of code that has been optimized away.
-; The default is not to report.
-; CoverReportCancelled = 1
-
-; Use this directory for compiler temporary files instead of "work/_temp"
-; CompilerTempDir = /tmp
-
-; Set this to cause the compilers to force data to be committed to disk
-; when the files are closed.
-; SyncCompilerFiles = 1
-
-; Add VHDL-AMS declarations to package STANDARD
-; Default is not to add
-; AmsStandard = 1
-
-; Range and length checking will be performed on array indices and discrete
-; ranges, and when violations are found within subprograms, errors will be
-; reported. Default is to issue warnings for violations, because subprograms
-; may not be invoked.
-; NoDeferSubpgmCheck = 0
-
-; Turn ON detection of FSMs having single bit current state variable.
-; FsmSingle = 1
-
-; Turn off reset state transitions in FSM.
-; FsmResetTrans = 0
-
-; Turn ON detection of FSM Implicit Transitions.
-; FsmImplicitTrans = 1
-
-; Controls whether or not to show immediate assertions with constant expressions
-; in GUI/report/UCDB etc. By default, immediate assertions with constant
-; expressions are shown in GUI/report/UCDB etc. This does not affect
-; evaluation of immediate assertions.
-; ShowConstantImmediateAsserts = 0
-
-; Controls how VHDL basic identifiers are stored with the design unit.
-; Does not make the language case-sensitive, effects only how declarations
-; declared with basic identifiers have their names stored and printed
-; (examine, etc.).
-; Default is to preserve the case as originally depicted in the VHDL source.
-; Value of 0 indicates to change basic identifiers to lower case.
-; PreserveCase = 0
-
-; For Configuration Declarations, controls the effect that USE clauses have
-; on visibility inside the configuration items being configured. If 1
-; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance
-; extend the visibility of objects made visible through USE clauses into nested
-; component configurations.
-; OldVHDLConfigurationVisibility = 0
-
-; Allows VHDL configuration declarations to be in a different library from
-; the corresponding configured entity. Default is to not allow this for
-; stricter LRM-compliance
-; SeparateConfigLibrary = 1;
-
-; Change how subprogram out parameter of type array and record are treated.
-; If 1, always initial the out parameter to its default value.
-; If 2, do not initialize the out parameter.
-; The value 0 indicates use the default for the langauge version being compiled.
-; Prior to 10.1 all langauge version did not initialize out composite parameters.
-; 10.1 and later files compile with -2008 initialize by default
-; InitOutCompositeParam = 0
-
-[vlog]
-; Turn off inclusion of debugging info within design units.
-; Default is to include debugging info.
-; NoDebug = 1
-
-; Turn on `protect compiler directive processing.
-; Default is to ignore `protect directives.
-; Protect = 1
-
-; Turn off "Loading..." messages. Default is messages on.
-; Quiet = 1
-
-; Turn on Verilog hazard checking (order-dependent accessing of global vars).
-; Default is off.
-; Hazard = 1
-
-; Turn on converting regular Verilog identifiers to uppercase. Allows case
-; insensitivity for module names. Default is no conversion.
-; UpCase = 1
-
-; Activate optimizations on expressions that do not involve signals,
-; waits, or function/procedure/task invocations. Default is off.
-; ScalarOpts = 1
-
-; Turns on lint-style checking.
-; Show_Lint = 1
-
-; Show source line containing error. Default is off.
-; Show_source = 1
-
-; Turn on bad option warning. Default is off.
-; Show_BadOptionWarning = 1
-
-; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
-; vlog95compat = 1
-
-; Turn off PSL warning messages. Default is to show warnings.
-; Show_PslChecksWarnings = 0
-
-; Enable parsing of embedded PSL assertions. Default is enabled.
-; EmbeddedPsl = 0
-
-; Set the threshold for automatically identifying sparse Verilog memories.
-; A memory with depth equal to or more than the sparse memory threshold gets
-; marked as sparse automatically, unless specified otherwise in source code
-; or by +nosparse commandline option of vlog or vopt.
-; The default is 1M. (i.e. memories with depth equal
-; to or greater than 1M are marked as sparse)
-; SparseMemThreshold = 1048576
-
-; Run the 0-in compiler on the Verilog source files
-; Default is off.
-; ZeroIn = 1
-
-; Set the options to be passed to the 0-in compiler.
-; Default is "".
-; ZeroInOptions = ""
-
-; Set the synthesis prefix to be honored for synthesis pragma recognition.
-; Default is "".
-; SynthPrefix = ""
-
-; Set the option to treat all files specified in a vlog invocation as a
-; single compilation unit. The default value is set to 0 which will treat
-; each file as a separate compilation unit as specified in the P1800 draft standard.
-; MultiFileCompilationUnit = 1
-
-; Turn on code coverage in Verilog design units. Default is off.
-; Coverage = sbceft
-
-; Automatically exclude Verilog case statement default branches.
-; Default is to not automatically exclude defaults.
-; CoverExcludeDefault = 1
-
-; Increase or decrease the maximum number of rows allowed in a UDP table
-; implementing a Verilog condition coverage or expression coverage expression.
-; More rows leads to a longer compile time, but more expressions covered.
-; CoverMaxUDPRows = 192
-
-; Increase or decrease the maximum number of input patterns that are present
-; in FEC table. This leads to a longer compile time with more expressions
-; covered with FEC metric.
-; CoverMaxFECRows = 192
-
-; Enable or disable Focused Expression Coverage analysis for conditions and
-; expressions. Focused Expression Coverage data is provided by default when
-; expression and/or condition coverage is active.
-; CoverFEC = 0
-
-; Enable or disable UDP Coverage analysis for conditions and expressions.
-; UDP Coverage data is provided by default when expression and/or condition
-; coverage is active.
-; CoverUDP = 0
-
-; Enable or disable short circuit evaluation of conditions and expressions when
-; condition or expression coverage is active. Short circuit evaluation is enabled
-; by default.
-; CoverShortCircuit = 0
-
-
-; Turn on code coverage in VLOG `celldefine modules and modules included
-; using vlog -v and -y. Default is off.
-; CoverCells = 1
-
-; Enable code coverage reporting of code that has been optimized away.
-; The default is not to report.
-; CoverReportCancelled = 1
-
-; Control compiler and VOPT optimizations that are allowed when
-; code coverage is on. This is a number from 1 to 4, with the following
-; meanings (the default is 3):
-; 1 -- Turn off all optimizations that affect coverage reports.
-; 2 -- Allow optimizations that allow large performance improvements
-; by invoking sequential processes only when the data changes.
-; This may make major reductions in coverage counts.
-; 3 -- In addition, allow optimizations that may change expressions or
-; remove some statements. Allow constant propagation. Allow VHDL
-; subprogram inlining and VHDL FF recognition.
-; 4 -- In addition, allow optimizations that may remove major regions of
-; code by changing assignments to built-ins or removing unused
-; signals. Change Verilog gates to continuous assignments.
-; CoverOpt = 3
-
-; Specify the override for the default value of "cross_num_print_missing"
-; option for the Cross in Covergroups. If not specified then LRM default
-; value of 0 (zero) is used. This is a compile time option.
-; SVCrossNumPrintMissingDefault = 0
-
-; Setting following to 1 would cause creation of variables which
-; would represent the value of Coverpoint expressions. This is used
-; in conjunction with "SVCoverpointExprVariablePrefix" option
-; in the modelsim.ini
-; EnableSVCoverpointExprVariable = 0
-
-; Specify the override for the prefix used in forming the variable names
-; which represent the Coverpoint expressions. This is used in conjunction with
-; "EnableSVCoverpointExprVariable" option of the modelsim.ini
-; The default prefix is "expr".
-; The variable name is
-; variable name => <prefix>_<coverpoint name>
-; SVCoverpointExprVariablePrefix = expr
-
-; Override for the default value of the SystemVerilog covergroup,
-; coverpoint, and cross option.goal (defined to be 100 in the LRM).
-; NOTE: It does not override specific assignments in SystemVerilog
-; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
-; in the [vsim] section can override this value.
-; SVCovergroupGoalDefault = 100
-
-; Override for the default value of the SystemVerilog covergroup,
-; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
-; NOTE: It does not override specific assignments in SystemVerilog
-; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
-; in the [vsim] section can override this value.
-; SVCovergroupTypeGoalDefault = 100
-
-; Specify the override for the default value of "strobe" option for the
-; Covergroup Type. This is a compile time option which forces "strobe" to
-; a user specified default value and supersedes SystemVerilog specified
-; default value of '0'(zero). NOTE: This can be overriden by a runtime
-; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
-; SVCovergroupStrobeDefault = 0
-
-; Specify the override for the default value of "merge_instances" option for
-; the Covergroup Type. This is a compile time option which forces
-; "merge_instances" to a user specified default value and supersedes
-; SystemVerilog specified default value of '0'(zero).
-; SVCovergroupMergeInstancesDefault = 0
-
-; Specify the override for the default value of "per_instance" option for the
-; Covergroup variables. This is a compile time option which forces "per_instance"
-; to a user specified default value and supersedes SystemVerilog specified
-; default value of '0'(zero).
-; SVCovergroupPerInstanceDefault = 0
-
-; Specify the override for the default value of "get_inst_coverage" option for the
-; Covergroup variables. This is a compile time option which forces
-; "get_inst_coverage" to a user specified default value and supersedes
-; SystemVerilog specified default value of '0'(zero).
-; SVCovergroupGetInstCoverageDefault = 0
-
-;
-; A space separated list of resource libraries that contain precompiled
-; packages. The behavior is identical to using the "-L" switch.
-;
-; LibrarySearchPath = <path/lib> [<path/lib> ...]
-LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF
-
-; The behavior is identical to the "-mixedansiports" switch. Default is off.
-; MixedAnsiPorts = 1
-
-; Enable SystemVerilog 3.1a $typeof() function. Default is off.
-; EnableTypeOf = 1
-
-; Only allow lower case pragmas. Default is disabled.
-; AcceptLowerCasePragmaOnly = 1
-
-; Set the maximum depth permitted for a recursive include file nesting.
-; IncludeRecursionDepthMax = 5
-
-; Turn ON detection of FSMs having single bit current state variable.
-; FsmSingle = 1
-
-; Turn off reset state transitions in FSM.
-; FsmResetTrans = 0
-
-; Turn off detections of FSMs having x-assignment.
-; FsmXAssign = 0
-
-; Turn ON detection of FSM Implicit Transitions.
-; FsmImplicitTrans = 1
-
-; List of file suffixes which will be read as SystemVerilog. White space
-; in extensions can be specified with a back-slash: "\ ". Back-slashes
-; can be specified with two consecutive back-slashes: "\\";
-; SVFileExtensions = sv svp svh
-
-; This setting is the same as the vlog -sv command line switch.
-; Enables SystemVerilog features and keywords when true (1).
-; When false (0), the rules of IEEE Std 1364-2001 are followed and
-; SystemVerilog keywords are ignored.
-; Svlog = 0
-
-; Prints attribute placed upon SV packages during package import
-; when true (1). The attribute will be ignored when this
-; entry is false (0). The attribute name is "package_load_message".
-; The value of this attribute is a string literal.
-; Default is true (1).
-; PrintSVPackageLoadingAttribute = 1
-
-; Do not show immediate assertions with constant expressions in
-; GUI/reports/UCDB etc. By default immediate assertions with constant
-; expressions are shown in GUI/reports/UCDB etc. This does not affect
-; evaluation of immediate assertions.
-; ShowConstantImmediateAsserts = 0
-
-; Controls if untyped parameters that are initialized with values greater
-; than 2147483647 are mapped to generics of type INTEGER or ignored.
-; If mapped to VHDL Integers, values greater than 2147483647
-; are mapped to negative values.
-; Default is to map these parameter to generic of type INTEGER
-; ForceUnsignedToVHDLInteger = 1
-
-; Enable AMS wreal (wired real) extensions. Default is 0.
-; WrealType = 1
-
-[sccom]
-; Enable use of SCV include files and library. Default is off.
-; UseScv = 1
-
-; Add C++ compiler options to the sccom command line by using this variable.
-; CppOptions = -g
-
-; Use custom C++ compiler located at this path rather than the default path.
-; The path should point directly at a compiler executable.
-; CppPath = /usr/bin/g++
-
-; Enable verbose messages from sccom. Default is off.
-; SccomVerbose = 1
-
-; sccom logfile. Default is no logfile.
-; SccomLogfile = sccom.log
-
-; Enable use of SC_MS include files and library. Default is off.
-; UseScMs = 1
-
-[vopt]
-; Turn on code coverage in vopt. Default is off.
-; Coverage = sbceft
-
-; Control compiler optimizations that are allowed when
-; code coverage is on. Refer to the comment for this in the [vlog] area.
-; CoverOpt = 3
-
-; Increase or decrease the maximum number of rows allowed in a UDP table
-; implementing a vopt condition coverage or expression coverage expression.
-; More rows leads to a longer compile time, but more expressions covered.
-; CoverMaxUDPRows = 192
-
-; Increase or decrease the maximum number of input patterns that are present
-; in FEC table. This leads to a longer compile time with more expressions
-; covered with FEC metric.
-; CoverMaxFECRows = 192
-
-; Enable code coverage reporting of code that has been optimized away.
-; The default is not to report.
-; CoverReportCancelled = 1
-
-; Do not show immediate assertions with constant expressions in
-; GUI/reports/UCDB etc. By default immediate assertions with constant
-; expressions are shown in GUI/reports/UCDB etc. This does not affect
-; evaluation of immediate assertions.
-; ShowConstantImmediateAsserts = 0
-
-; Set the maximum number of iterations permitted for a generate loop.
-; Restricting this permits the implementation to recognize infinite
-; generate loops.
-; GenerateLoopIterationMax = 100000
-
-; Set the maximum depth permitted for a recursive generate instantiation.
-; Restricting this permits the implementation to recognize infinite
-; recursions.
-; GenerateRecursionDepthMax = 200
-
-
-[vsim]
-; vopt flow
-; Set to turn on automatic optimization of a design.
-; Default is on
-VoptFlow = 1
-
-; Simulator resolution
-; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
-Resolution = ns
-
-; Disable certain code coverage exclusions automatically.
-; Assertions and FSM are exluded from the code coverage by default
-; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
-; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
-; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
-; Or specify comma or space separated list
-;AutoExclusionsDisable = fsm,assertions
-
-; User time unit for run commands
-; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
-; unit specified for Resolution. For example, if Resolution is 100ps,
-; then UserTimeUnit defaults to ps.
-; Should generally be set to default.
-UserTimeUnit = default
-
-; Default run length
-RunLength = 200 us
-
-; Maximum iterations that can be run without advancing simulation time
-IterationLimit = 5000
-
-; Control PSL and Verilog Assume directives during simulation
-; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
-; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
-; SimulateAssumeDirectives = 1
-
-; Control the simulation of PSL and SVA
-; These switches can be overridden by the vsim command line switches:
-; -psl, -nopsl, -sva, -nosva.
-; Set SimulatePSL = 0 to disable PSL simulation
-; Set SimulatePSL = 1 to enable PSL simulation (default)
-; SimulatePSL = 1
-; Set SimulateSVA = 0 to disable SVA simulation
-; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
-; SimulateSVA = 1
-
-; Directives to license manager can be set either as single value or as
-; space separated multi-values:
-; vhdl Immediately reserve a VHDL license
-; vlog Immediately reserve a Verilog license
-; plus Immediately reserve a VHDL and Verilog license
-; noqueue Do not wait in the license queue when a license is not available
-; viewsim Try for viewer license but accept simulator license(s) instead
-; of queuing for viewer license (PE ONLY)
-; noviewer Disable checkout of msimviewer and vsim-viewer license
-; features (PE ONLY)
-; noslvhdl Disable checkout of qhsimvh and vsim license features
-; noslvlog Disable checkout of qhsimvl and vsimvlog license features
-; nomix Disable checkout of msimhdlmix and hdlmix license features
-; nolnl Disable checkout of msimhdlsim and hdlsim license features
-; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
-; features
-; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
-; hdlmix license features
-; Single value:
-; License = plus
-; Multi-value:
-; License = noqueue plus
-
-; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion
-; which will cause a running simulation to stop.
-; VHDL assertions and SystemVerilog immediate assertions that occur with the
-; given severity or higher will cause a running simulation to stop.
-; This value is ignored during elaboration.
-; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
-BreakOnAssertion = 3
-
-; Message Format conversion specifications:
-; %S - Severity Level of message/assertion
-; %R - Text of message
-; %T - Time of message
-; %D - Delta value (iteration number) of Time
-; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected
-; %i - Instance/Region/Signal pathname with Process name (if available)
-; %I - shorthand for one of these:
-; " %K: %i"
-; " %K: %i File: %F" (when path is not Process or Signal)
-; except that the %i in this case does not report the Process name
-; %O - Process name
-; %P - Instance/Region path without leaf process
-; %F - File name
-; %L - Line number; if assertion message, then line number of assertion or, if
-; assertion is in a subprogram, line from which the call is made
-; %u - Design unit name in form library.primary
-; %U - Design unit name in form library.primary(secondary)
-; %% - The '%' character itself
-;
-; If specific format for Severity Level is defined, use that format.
-; Else, for a message that occurs during elaboration:
-; -- Failure/Fatal message in VHDL region that is not a Process, and in
-; certain non-VHDL regions, uses MessageFormatBreakLine;
-; -- Failure/Fatal message otherwise uses MessageFormatBreak;
-; -- Note/Warning/Error message uses MessageFormat.
-; Else, for a message that occurs during runtime and triggers a breakpoint because
-; of the BreakOnAssertion setting:
-; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine;
-; -- otherwise uses MessageFormatBreak.
-; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat.
-;
-; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
-; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
-; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
-; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
-; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
-; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
-; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
-; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
-
-; Error File - alternate file for storing error messages
-; ErrorFile = error.log
-
-; Simulation Breakpoint messages
-; This flag controls the display of function names when reporting the location
-; where the simulator stops because of a breakpoint or fatal error.
-; Example with function name: # Break in Process ctr at counter.vhd line 44
-; Example without function name: # Break at counter.vhd line 44
-; Default value is 1.
-ShowFunctions = 1
-
-; Default radix for all windows and commands.
-; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
-DefaultRadix = symbolic
-
-; VSIM Startup command
-; Startup = do startup.do
-
-; VSIM Shutdown file
-; Filename to save u/i formats and configurations.
-; ShutdownFile = restart.do
-; To explicitly disable auto save:
-; ShutdownFile = --disable-auto-save
-
-; File for saving command transcript
-TranscriptFile = transcript
-
-; File for saving command history
-; CommandHistory = cmdhist.log
-
-; Specify whether paths in simulator commands should be described
-; in VHDL or Verilog format.
-; For VHDL, PathSeparator = /
-; For Verilog, PathSeparator = .
-; Must not be the same character as DatasetSeparator.
-PathSeparator = /
-
-; Specify the dataset separator for fully rooted contexts.
-; The default is ':'. For example: sim:/top
-; Must not be the same character as PathSeparator.
-DatasetSeparator = :
-
-; Specify a unique path separator for the Signal Spy set of functions.
-; The default will be to use the PathSeparator variable.
-; Must not be the same character as DatasetSeparator.
-; SignalSpyPathSeparator = /
-
-; Used to control parsing of HDL identifiers input to the tool.
-; This includes CLI commands, vsim/vopt/vlog/vcom options,
-; string arguments to FLI/VPI/DPI calls, etc.
-; If set to 1, accept either Verilog escaped Id syntax or
-; VHDL extended id syntax, regardless of source language.
-; If set to 0, the syntax of the source language must be used.
-; Each identifier in a hierarchical name may need different syntax,
-; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
-; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
-; GenerousIdentifierParsing = 1
-
-; Disable VHDL assertion messages
-; IgnoreNote = 1
-; IgnoreWarning = 1
-; IgnoreError = 1
-; IgnoreFailure = 1
-
-; Disable SystemVerilog assertion messages
-; IgnoreSVAInfo = 1
-; IgnoreSVAWarning = 1
-; IgnoreSVAError = 1
-; IgnoreSVAFatal = 1
-
-; Do not print any additional information from Severity System tasks.
-; Only the message provided by the user is printed along with severity
-; information.
-; SVAPrintOnlyUserMessage = 1;
-
-; Default force kind. May be freeze, drive, deposit, or default
-; or in other terms, fixed, wired, or charged.
-; A value of "default" will use the signal kind to determine the
-; force kind, drive for resolved signals, freeze for unresolved signals
-; DefaultForceKind = freeze
-
-; Control the iteration of events when a VHDL signal is forced to a value
-; This flag can be set to honour the signal update event in next iteration,
-; the default is to update and propagate in the same iteration.
-; ForceSigNextIter = 1
-
-
-; If zero, open files when elaborated; otherwise, open files on
-; first read or write. Default is 0.
-; DelayFileOpen = 1
-
-; Control VHDL files opened for write.
-; 0 = Buffered, 1 = Unbuffered
-UnbufferedOutput = 0
-
-; Control the number of VHDL files open concurrently.
-; This number should always be less than the current ulimit
-; setting for max file descriptors.
-; 0 = unlimited
-ConcurrentFileLimit = 40
-
-; Control the number of hierarchical regions displayed as
-; part of a signal name shown in the Wave window.
-; A value of zero tells VSIM to display the full name.
-; The default is 0.
-; WaveSignalNameWidth = 0
-
-; Turn off warnings when changing VHDL constants and generics
-; Default is 1 to generate warning messages
-; WarnConstantChange = 0
-
-; Turn off warnings from accelerated versions of the std_logic_arith,
-; std_logic_unsigned, and std_logic_signed packages.
-; StdArithNoWarnings = 1
-
-; Turn off warnings from accelerated versions of the IEEE numeric_std
-; and numeric_bit packages.
-; NumericStdNoWarnings = 1
-
-; Use old-style (pre-6.6) VHDL FOR generate statement iteration names
-; in the design hierarchy.
-; This style is controlled by the value of the GenerateFormat
-; value described next. Default is to use new-style names, which
-; comprise the generate statement label, '(', the value of the generate
-; parameter, and a closing ')'.
-; Uncomment this to use old-style names.
-; OldVhdlForGenNames = 1
-
-; Enable changes in VHDL elaboration to allow for Variable Logging
-; This trades off simulation performance for the ability to log variables
-; efficiently. By default this is disable for maximum simulation performance
-; VhdlVariableLogging = 1
-
-; Control the format of the old-style VHDL FOR generate statement region
-; name for each iteration. Do not quote it.
-; The format string here must contain the conversion codes %s and %d,
-; in that order, and no other conversion codes. The %s represents
-; the generate statement label; the %d represents the generate parameter value
-; at a particular iteration (this is the position number if the generate parameter
-; is of an enumeration type). Embedded whitespace is allowed (but discouraged);
-; leading and trailing whitespace is ignored.
-; Application of the format must result in a unique region name over all
-; loop iterations for a particular immediately enclosing scope so that name
-; lookup can function properly. The default is %s__%d.
-; GenerateFormat = %s__%d
-
-; Specify whether checkpoint files should be compressed.
-; The default is 1 (compressed).
-; CheckpointCompressMode = 0
-
-; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.
-; Use custom gcc compiler located at this path rather than the default path.
-; The path should point directly at a compiler executable.
-; DpiCppPath = <your-gcc-installation>/bin/gcc
-
-; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
-; The term "out-of-the-blue" refers to SystemVerilog export function calls
-; made from C functions that don't have the proper context setup
-; (as is the case when running under "DPI-C" import functions).
-; When this is enabled, one can call a DPI export function
-; (but not task) from any C code.
-; the setting of this variable can be one of the following values:
-; 0 : dpioutoftheblue call is disabled (default)
-; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
-; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
-; DpiOutOfTheBlue = 1
-
-; Specify whether continuous assignments are run before other normal priority
-; processes scheduled in the same iteration. This event ordering minimizes race
-; differences between optimized and non-optimized designs, and is the default
-; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
-; ImmediateContinuousAssign to 0.
-; The default is 1 (enabled).
-; ImmediateContinuousAssign = 0
-
-; List of dynamically loaded objects for Verilog PLI applications
-; Veriuser = veriuser.sl
-
-; Which default VPI object model should the tool conform to?
-; The 1364 modes are Verilog-only, for backwards compatibility with older
-; libraries, and SystemVerilog objects are not available in these modes.
-;
-; In the absence of a user-specified default, the tool default is the
-; latest available LRM behavior.
-; Options for PliCompatDefault are:
-; VPI_COMPATIBILITY_VERSION_1364v1995
-; VPI_COMPATIBILITY_VERSION_1364v2001
-; VPI_COMPATIBILITY_VERSION_1364v2005
-; VPI_COMPATIBILITY_VERSION_1800v2005
-; VPI_COMPATIBILITY_VERSION_1800v2008
-;
-; Synonyms for each string are also recognized:
-; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
-; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
-; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
-; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
-; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
-
-
-; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
-
-; Specify default options for the restart command. Options can be one
-; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
-; DefaultRestartOptions = -force
-
-; Turn on (1) or off (0) WLF file compression.
-; The default is 1 (compress WLF file).
-; WLFCompress = 0
-
-; Specify whether to save all design hierarchy (1) in the WLF file
-; or only regions containing logged signals (0).
-; The default is 0 (save only regions with logged signals).
-; WLFSaveAllRegions = 1
-
-; WLF file time limit. Limit WLF file by time, as closely as possible,
-; to the specified amount of simulation time. When the limit is exceeded
-; the earliest times get truncated from the file.
-; If both time and size limits are specified the most restrictive is used.
-; UserTimeUnits are used if time units are not specified.
-; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
-; WLFTimeLimit = 0
-
-; WLF file size limit. Limit WLF file size, as closely as possible,
-; to the specified number of megabytes. If both time and size limits
-; are specified then the most restrictive is used.
-; The default is 0 (no limit).
-; WLFSizeLimit = 1000
-
-; Specify whether or not a WLF file should be deleted when the
-; simulation ends. A value of 1 will cause the WLF file to be deleted.
-; The default is 0 (do not delete WLF file when simulation ends).
-; WLFDeleteOnQuit = 1
-
-; Specify whether or not a WLF file should be optimized during
-; simulation. If set to 0, the WLF file will not be optimized.
-; The default is 1, optimize the WLF file.
-; WLFOptimize = 0
-
-; Specify the name of the WLF file.
-; The default is vsim.wlf
-; WLFFilename = vsim.wlf
-
-; Specify whether to lock the WLF file.
-; Locking the file prevents other invocations of ModelSim/Questa tools from
-; inadvertently overwriting the WLF file.
-; The default is 1, lock the WLF file.
-; WLFFileLock = 0
-
-; Specify the WLF reader cache size limit for each open WLF file.
-; The size is giving in megabytes. A value of 0 turns off the
-; WLF cache.
-; WLFSimCacheSize allows a different cache size to be set for
-; simulation WLF file independent of post-simulation WLF file
-; viewing. If WLFSimCacheSize is not set it defaults to the
-; WLFCacheSize setting.
-; The default WLFCacheSize setting is enabled to 256M per open WLF file.
-; WLFCacheSize = 2000
-; WLFSimCacheSize = 500
-
-; Specify the WLF file event collapse mode.
-; 0 = Preserve all events and event order. (same as -wlfnocollapse)
-; 1 = Only record values of logged objects at the end of a simulator iteration.
-; (same as -wlfcollapsedelta)
-; 2 = Only record values of logged objects at the end of a simulator time step.
-; (same as -wlfcollapsetime)
-; The default is 1.
-; WLFCollapseMode = 0
-
-; Specify whether WLF file logging can use threads on multi-processor machines
-; if 0, no threads will be used, if 1, threads will be used if the system has
-; more than one processor
-; WLFUseThreads = 1
-
-; Turn on/off undebuggable SystemC type warnings. Default is on.
-; ShowUndebuggableScTypeWarning = 0
-
-; Turn on/off unassociated SystemC name warnings. Default is off.
-; ShowUnassociatedScNameWarning = 1
-
-; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
-; ScShowIeeeDeprecationWarnings = 1
-
-; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
-; ScEnableScSignalWriteCheck = 1
-
-; Set SystemC default time unit.
-; Set to fs, ps, ns, us, ms, or sec with optional
-; prefix of 1, 10, or 100. The default is 1 ns.
-; The ScTimeUnit value is honored if it is coarser than Resolution.
-; If ScTimeUnit is finer than Resolution, it is set to the value
-; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
-; then the default time unit will be 1 ns. However if Resolution
-; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
-ScTimeUnit = ns
-
-; Set SystemC sc_main stack size. The stack size is set as an integer
-; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
-; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
-; on the amount of data on the sc_main() stack and the memory required
-; to succesfully execute the longest function call chain of sc_main().
-ScMainStackSize = 10 Mb
-
-; Turn on/off execution of remainder of sc_main upon quitting the current
-; simulation session. If the cumulative length of sc_main() in terms of
-; simulation time units is less than the length of the current simulation
-; run upon quit or restart, sc_main() will be in the middle of execution.
-; This switch gives the option to execute the remainder of sc_main upon
-; quitting simulation. The drawback of not running sc_main till the end
-; is memory leaks for objects created by sc_main. If on, the remainder of
-; sc_main will be executed ignoring all delays. This may cause the simulator
-; to crash if the code in sc_main is dependent on some simulation state.
-; Default is on.
-ScMainFinishOnQuit = 1
-
-; Set the SCV relationship name that will be used to identify phase
-; relations. If the name given to a transactor relation matches this
-; name, the transactions involved will be treated as phase transactions
-ScvPhaseRelationName = mti_phase
-
-; Customize the vsim kernel shutdown behavior at the end of the simulation.
-; Some common causes of the end of simulation are $finish (implicit or explicit),
-; sc_stop(), tf_dofinish(), and assertion failures.
-; This should be set to "ask", "exit", or "stop". The default is "ask".
-; "ask" -- In batch mode, the vsim kernel will abruptly exit.
-; In GUI mode, a dialog box will pop up and ask for user confirmation
-; whether or not to quit the simulation.
-; "stop" -- Cause the simulation to stay loaded in memory. This can make some
-; post-simulation tasks easier.
-; "exit" -- The simulation will abruptly exit without asking for any confirmation.
-; "final" -- Run SystemVerilog final blocks then behave as "stop".
-; Note: This variable can be overridden with the vsim "-onfinish" command line switch.
-OnFinish = ask
-
-; Print pending deferred assertion messages.
-; Deferred assertion messages may be scheduled after the $finish in the same
-; time step. Deferred assertions scheduled to print after the $finish are
-; printed before exiting with severity level NOTE since it's not known whether
-; the assertion is still valid due to being printed in the active region
-; instead of the reactive region where they are normally printed.
-; OnFinishPendingAssert = 1;
-
-; Print "simstats" result
-; 0 == do not print simstats
-; 1 == print at end of simulation
-; 2 == print at end of run
-; 3 == print at end of run and end of simulation
-; default == 0
-; PrintSimStats = 1
-
-
-; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
-; AssertFile = assert.log
-
-; Enable assertion counts. Default is off.
-; AssertionCover = 1
-
-; Run simulator in assertion debug mode. Default is off.
-; AssertionDebug = 1
-
-; Turn on/off PSL/SVA/VHDL assertion enable. Default is on.
-; AssertionEnable = 0
-
-; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1.
-; Any positive integer, -1 for infinity.
-; AssertionLimit = 1
-
-; Turn on/off concurrent assertion pass log. Default is off.
-; Assertion pass logging is only enabled when assertion is browseable
-; and assertion debug is enabled.
-; AssertionPassLog = 1
-
-; Turn on/off PSL concurrent assertion fail log. Default is on.
-; The flag does not affect SVA
-; AssertionFailLog = 0
-
-; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
-; AssertionFailLocalVarLog = 0
-
-; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
-; 0 = Continue 1 = Break 2 = Exit
-; AssertionFailAction = 1
-
-; Enable the active thread monitor in the waveform display when assertion debug is enabled.
-; AssertionActiveThreadMonitor = 1
-
-; Control how many waveform rows will be used for displaying the active threads. Default is 5.
-; AssertionActiveThreadMonitorLimit = 5
-
-; Assertion thread limit after which assertion would be killed/switched off.
-; The default is -1 (unlimited). If the number of threads for an assertion go
-; beyond this limit, the assertion would be either switched off or killed. This
-; limit applies to only assert directives.
-;AssertionThreadLimit = -1
-
-; Action to be taken once the assertion thread limit is reached. Default
-; is kill. It can have a value of off or kill. In case of kill, all the existing
-; threads are terminated and no new attempts are started. In case of off, the
-; existing attempts keep on evaluating but no new attempts are started. This
-; variable applies to only assert directives.
-;AssertionThreadLimitAction = kill
-
-; Cover thread limit after which cover would be killed/switched off.
-; The default is -1 (unlimited). If the number of threads for a cover go
-; beyond this limit, the cover would be either switched off or killed. This
-; limit applies to only cover directives.
-;CoverThreadLimit = -1
-
-; Action to be taken once the cover thread limit is reached. Default
-; is kill. It can have a value of off or kill. In case of kill, all the existing
-; threads are terminated and no new attempts are started. In case of off, the
-; existing attempts keep on evaluating but no new attempts are started. This
-; variable applies to only cover directives.
-;CoverThreadLimitAction = kill
-
-
-; By default immediate assertions do not participate in Assertion Coverage calculations
-; unless they are executed. This switch causes all immediate assertions in the design
-; to participate in Assertion Coverage calculations, whether attempted or not.
-; UnattemptedImmediateAssertions = 0
-
-; By default immediate covers participate in Coverage calculations
-; whether they are attempted or not. This switch causes all unattempted
-; immediate covers in the design to stop participating in Coverage
-; calculations.
-; UnattemptedImmediateCovers = 0
-
-; By default pass action block is not executed for assertions on vacuous
-; success. The following variable is provided to enable execution of
-; pass action block on vacuous success. The following variable is only effective
-; if the user does not disable pass action block execution by using either
-; system tasks or CLI. Also there is a performance penalty for enabling
-; the following variable.
-;AssertionEnableVacuousPassActionBlock = 1
-
-; As per strict 1850-2005 PSL LRM, an always property can either pass
-; or fail. However, by default, Questa reports multiple passes and
-; multiple fails on top always/never property (always/never operator
-; is the top operator under Verification Directive). The reason
-; being that Questa reports passes and fails on per attempt of the
-; top always/never property. Use the following flag to instruct
-; Questa to strictly follow LRM. With this flag, all assert/never
-; directives will start an attempt once at start of simulation.
-; The attempt can either fail, match or match vacuously.
-; For e.g. if always is the top operator under assert, the always will
-; keep on checking the property at every clock. If the property under
-; always fails, the directive will be considered failed and no more
-; checking will be done for that directive. A top always property,
-; if it does not fail, will show a pass at end of simulation.
-; The default value is '0' (i.e. zero is off). For example:
-; PslOneAttempt = 1
-
-; Specify the number of clock ticks to represent infinite clock ticks.
-; This affects eventually!, until! and until_!. If at End of Simulation
-; (EOS) an active strong-property has not clocked this number of
-; clock ticks then neither pass or fail (vacuous match) is returned
-; else respective fail/pass is returned. The default value is '0' (zero)
-; which effectively does not check for clock tick condition. For example:
-; PslInfinityThreshold = 5000
-
-; Control how many thread start times will be preserved for ATV viewing for a given assertion
-; instance. Default is -1 (ALL).
-; ATVStartTimeKeepCount = -1
-
-; Turn on/off code coverage
-; CodeCoverage = 0
-
-; Count all code coverage condition and expression truth table rows that match.
-; CoverCountAll = 1
-
-; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
-; is to include them.
-; ToggleNoIntegers = 1
-
-; Set the maximum number of values that are collected for toggle coverage of
-; VHDL integers. Default is 100;
-; ToggleMaxIntValues = 100
-
-; Set the maximum number of values that are collected for toggle coverage of
-; Verilog real. Default is 100;
-; ToggleMaxRealValues = 100
-
-; Turn on automatic inclusion of Verilog integers in toggle coverage, except
-; for enumeration types. Default is to include them.
-; ToggleVlogIntegers = 0
-
-; Turn on automatic inclusion of Verilog real type in toggle coverage, except
-; for shortreal types. Default is to not include them.
-; ToggleVlogReal = 1
-
-; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays
-; and VHDL arrays-of-arrays in toggle coverage.
-; Default is to not include them.
-; ToggleFixedSizeArray = 1
-
-; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays,
-; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage.
-; This leads to a longer simulation time with bigger arrays covered with toggle coverage.
-; Default is 1024.
-; ToggleMaxFixedSizeArray = 1024
-
-; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized
-; one-dimensional packed vectors for toggle coverage. Default is 0.
-; TogglePackedAsVec = 0
-
-; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for
-; toggle coverage. Default is 0.
-; ToggleVlogEnumBits = 0
-
-; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
-; For unlimited width, set to 0.
-; ToggleWidthLimit = 128
-
-; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
-; reached this count, further activity on the bit is ignored. Default is 1.
-; For unlimited counts, set to 0.
-; ToggleCountLimit = 1
-
-; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3.
-; Following is the toggle coverage calculation criteria based on extended toggle mode:
-; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
-; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
-; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions.
-; ExtendedToggleMode = 3
-
-; Enable toggle statistics collection only for ports. Default is 0.
-; TogglePortsOnly = 1
-
-; Turn on/off all PSL/SVA cover directive enables. Default is on.
-; CoverEnable = 0
-
-; Turn on/off PSL/SVA cover log. Default is off "0".
-; CoverLog = 1
-
-; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
-; CoverAtLeast = 2
-
-; Set "limit" value for all PSL/SVA cover directives. Default is -1.
-; Any positive integer, -1 for infinity.
-; CoverLimit = 1
-
-; Specify the coverage database filename.
-; Default is "" (i.e. database is NOT automatically saved on close).
-; UCDBFilename = vsim.ucdb
-
-; Specify the maximum limit for the number of Cross (bin) products reported
-; in XML and UCDB report against a Cross. A warning is issued if the limit
-; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this
-; setting.
-; MaxReportRhsSVCrossProducts = 1000
-
-; Specify the override for the "auto_bin_max" option for the Covergroups.
-; If not specified then value from Covergroup "option" is used.
-; SVCoverpointAutoBinMax = 64
-
-; Specify the override for the value of "cross_num_print_missing"
-; option for the Cross in Covergroups. If not specified then value
-; specified in the "option.cross_num_print_missing" is used. This
-; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
-; value specified by user in source file and any SVCrossNumPrintMissingDefault
-; specified in modelsim.ini.
-; SVCrossNumPrintMissing = 0
-
-; Specify whether to use the value of "cross_num_print_missing"
-; option in report and GUI for the Cross in Covergroups. If not specified then
-; cross_num_print_missing is ignored for creating reports and displaying
-; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
-; UseSVCrossNumPrintMissing = 0
-
-; Specify the threshold of Coverpoint wildcard bin value range size, above which
-; a warning will be triggered. The default is 4K -- 12 wildcard bits.
-; SVCoverpointWildCardBinValueSizeWarn = 4096
-
-; Specify the override for the value of "strobe" option for the
-; Covergroup Type. If not specified then value in "type_option.strobe"
-; will be used. This is runtime option which forces "strobe" to
-; user specified value and supersedes user specified values in the
-; SystemVerilog Code. NOTE: This also overrides the compile time
-; default value override specified using "SVCovergroupStrobeDefault"
-; SVCovergroupStrobe = 0
-
-; Override for explicit assignments in source code to "option.goal" of
-; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
-; default value of "option.goal" (defined to be 100 in the SystemVerilog
-; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
-; SVCovergroupGoal = 100
-
-; Override for explicit assignments in source code to "type_option.goal" of
-; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
-; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
-; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
-; SVCovergroupTypeGoal = 100
-
-; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
-; builtin functions, and report. This setting changes the default values of
-; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
-; behavior if explicit assignments are not made on option.get_inst_coverage and
-; type_option.merge_instances by the user. There are two vsim command line
-; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
-; The default value of this variable from release 6.6 onwards is 0. This default
-; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
-; SVCovergroup63Compatibility = 0
-
-; Enforce the 6.5 default behavior of covergroup get_coverage() builtin
-; functions, GUI, and report. This setting changes the default values of
-; type_option.merge_instances to ensure the 6.5 default behavior if explicit
-; assignments are not made on type_option.merge_instances by the user.
-; There are two vsim command line options, -cvgmergeinstances and
-; -nocvgmergeinstances to override this setting from vsim command line.
-; The default value of this variable from release 6.6 onwards is 0. This default
-; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
-; SvCovergroupMergeInstancesDefault = 1
-
-; Enable or disable generation of more detailed information about the sampling
-; of covergroup, cross, and coverpoints. It provides the details of the number
-; of times the covergroup instance and type were sampled, as well as details
-; about why covergroup, cross and coverpoint were not covered. A non-zero value
-; is to enable this feature. 0 is to disable this feature. Default is 0
-; SVCovergroupSampleInfo = 0
-
-; Specify the maximum number of Coverpoint bins in whole design for
-; all Covergroups.
-; MaxSVCoverpointBinsDesign = 2147483648
-
-; Specify maximum number of Coverpoint bins in any instance of a Covergroup
-; MaxSVCoverpointBinsInst = 2147483648
-
-; Specify the maximum number of Cross bins in whole design for
-; all Covergroups.
-; MaxSVCrossBinsDesign = 2147483648
-
-; Specify maximum number of Cross bins in any instance of a Covergroup
-; MaxSVCrossBinsInst = 2147483648
-
-; Specify a space delimited list of double quoted TCL style
-; regular expressions which will be matched against the text of all messages.
-; If any regular expression is found to be contained within any message, the
-; status for that message will not be propagated to the UCDB TESTSTATUS.
-; If no match is detected, then the status will be propagated to the
-; UCDB TESTSTATUS. More than one such regular expression text is allowed,
-; and each message text is compared for each regular expression in the list.
-; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message"
-
-; Set weight for all PSL/SVA cover directives. Default is 1.
-; CoverWeight = 2
-
-; Check vsim plusargs. Default is 0 (off).
-; 0 = Don't check plusargs
-; 1 = Warning on unrecognized plusarg
-; 2 = Error and exit on unrecognized plusarg
-; CheckPlusargs = 1
-
-; Load the specified shared objects with the RTLD_GLOBAL flag.
-; This gives global visibility to all symbols in the shared objects,
-; meaning that subsequently loaded shared objects can bind to symbols
-; in the global shared objects. The list of shared objects should
-; be whitespace delimited. This option is not supported on the
-; Windows or AIX platforms.
-; GlobalSharedObjectList = example1.so example2.so example3.so
-
-; Run the 0in tools from within the simulator.
-; Default is off.
-; ZeroIn = 1
-
-; Set the options to be passed to the 0in runtime tool.
-; Default value set to "".
-; ZeroInOptions = ""
-
-; Initial seed for the random number generator of the root thread (SystemVerilog).
-; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch.
-; The default value is 0.
-; Sv_Seed = 0
-
-; Specify the solver "engine" that vsim will select for constrained random
-; generation.
-; Valid values are:
-; "auto" - automatically select the best engine for the current
-; constraint scenario
-; "bdd" - evaluate all constraint scenarios using the BDD solver engine
-; "act" - evaluate all constraint scenarios using the ACT solver engine
-; While the BDD solver engine is generally efficient with constraint scenarios
-; involving bitwise logical relationships, the ACT solver engine can exhibit
-; superior performance with constraint scenarios involving large numbers of
-; random variables related via arithmetic operators (+, *, etc).
-; NOTE: This variable can be overridden with the vsim "-solveengine" command
-; line switch.
-; The default value is "auto".
-; SolveEngine = auto
-
-; Specify if the solver should attempt to ignore overflow/underflow semantics
-; for arithmetic constraints (multiply, addition, subtraction) in order to
-; improve performance. The "solveignoreoverflow" attribute can be specified on
-; a per-call basis to randomize() to override this setting.
-; The default value is 0 (overflow/underflow is not ignored). Set to 1 to
-; ignore overflow/underflow.
-; SolveIgnoreOverflow = 0
-
-; Specifies the maximum size that a dynamic array may be resized to by the
-; solver. If the solver attempts to resize a dynamic array to a size greater
-; than the specified limit, the solver will abort with an error.
-; The default value is 2000. A value of 0 indicates no limit.
-; SolveArrayResizeMax = 2000
-
-; Error message severity when randomize() failure is detected (SystemVerilog).
-; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
-; The default is 0 (no error).
-; SolveFailSeverity = 0
-
-; Enable/disable debug information for randomize() failures.
-; NOTE: This variable can be overridden with the vsim "-solvefaildbug" command
-; line switch.
-; The default is 0 (disabled). Set to 1 to enable.
-; SolveFailDebug = 0
-
-; Specify the maximum size of the solution graph generated by the BDD solver.
-; This value can be used to force the BDD solver to abort the evaluation of a
-; complex constraint scenario that cannot be evaluated with finite memory.
-; This value is specified in 1000s of nodes.
-; The default value is 10000. A value of 0 indicates no limit.
-; SolveGraphMaxSize = 10000
-
-; Specify the maximum number of evaluations that may be performed on the
-; solution graph by the BDD solver. This value can be used to force the BDD
-; solver to abort the evaluation of a complex constraint scenario that cannot
-; be evaluated in finite time. This value is specified in 10000s of evaluations.
-; The default value is 10000. A value of 0 indicates no limit.
-; SolveGraphMaxEval = 10000
-
-; Specify the maximum number of tests that the ACT solver may evaluate before
-; abandoning an attempt to solve a particular constraint scenario.
-; The default value is 20000000. A value of 0 indicates no limit.
-; SolveACTMaxTests = 20000000
-
-; Specify the maximum number of operations that the ACT solver may perform
-; before abandoning an attempt to solve a particular constraint scenario. The
-; value is specified in 1000000s of operations. The default value is 1000. A
-; value of 0 indicates no limit.
-; SolveACTMaxOps = 1000
-
-; Specify the number of times the ACT solver will retry to evaluate a constraint
-; scenario that fails due to the SolveACTMaxTests threshold.
-; The default value is 0 (no retry).
-; SolveACTRetryCount = 0
-
-; SolveSpeculateLevel controls whether or not the solver performs speculation
-; during the evaluation of a constraint scenario.
-; Speculation is an attempt to partition complex constraint scenarios by
-; choosing a 'speculation' subset of the variables and constraints. This
-; 'speculation' set is solved independently of the remaining constraints.
-; The solver then attempts to solve the remaining variables and constraints
-; (the 'dependent' set). If this attempt fails, the solver backs up and
-; re-solves the 'speculation' set, then retries the 'dependent' set.
-; Valid values are:
-; 0 - no speculation
-; 1 - enable speculation that maintains LRM specified distribution
-; 2 - enable other speculation - may yield non-LRM distribution
-; Currently, distribution constraints and solve-before constraints are
-; used in selecting the 'speculation' sets for speculation level 1. Non-LRM
-; compliant speculation includes random variables in condition expressions.
-; The default value is 0.
-; SolveSpeculateLevel = 0
-
-; By default, when speculation is enabled, the solver first tries to solve a
-; constraint scenario *without* speculation. If the solver fails to evaluate
-; the constraint scenario (due to time/memory limits) then the solver will
-; re-evaluate the constraint scenario with speculation. If SolveSpeculateFirst
-; is set to 1, the solver will skip the initial non-speculative attempt to
-; evaluate the constraint scenario. (Only applies when SolveSpeculateLevel is
-; non-zero)
-; The default value is 0.
-; SolveSpeculateFirst = 0
-
-; Specify the maximum bit width of a variable in a conditional expression that
-; may be considered as the basis for "conditional" speculation. (Only applies
-; when SolveSpeculateLevel=2)
-; The default value is 6.
-; SolveSpeculateMaxCondWidth = 6
-
-; Specify the maximum number of attempts to solve a speculative set of random
-; variables and constraints. Exceeding this limit will cause the solver to
-; abandon the current speculative set. (Only applies when SolveSpeculateLevel
-; is non-zero)
-; The default value is 100.
-; SolveSpeculateMaxIterations = 100
-
-; Specifies whether to attempt speculation on solve-before constraints or
-; distribution constraints first. A value of 0 specifies that solve-before
-; constraints are attempted first as the basis for speculative randomization.
-; A value of 1 specifies that distribution constraints are attempted first
-; as the basis for speculative randomization.
-; The default value is 0.
-; SolveSpeculateDistFirst = 0
-
-; If the non-speculative BDD solver fails to evaluate a constraint scenario
-; (due to time/memory limits) then the solver can be instructed to automatically
-; re-evaluate the constraint scenario with the ACT solver engine. Set
-; SolveACTbeforeSpeculate to 1 to enable this feature.
-; The default value is 0 (do not re-evaluate with the ACT solver).
-; SolveACTbeforeSpeculate = 0
-
-; Use SolveFlags to specify options that will guide the behavior of the
-; constraint solver. These options may improve the performance of the
-; constraint solver for some testcases, and decrease the performance of the
-; constraint solver for others.
-; Valid flags are:
-; i = disable bit interleaving for >, >=, <, <= constraints (BDD engine)
-; n = disable bit interleaving for all constraints (BDD engine)
-; r = reverse bit interleaving (BDD engine)
-; The default value is "" (no options).
-; SolveFlags =
-
-; Specify random sequence compatiblity with a prior letter release. This
-; option is used to get the same random sequences during simulation as
-; as a prior letter release. Only prior letter releases (of the current
-; number release) are allowed.
-; NOTE: Only those random sequence changes due to solver optimizations are
-; reverted by this variable. Random sequence changes due to solver bugfixes
-; cannot be un-done.
-; NOTE: This variable can be overridden with the vsim "-solverev" command
-; line switch.
-; Default value set to "" (no compatibility).
-; SolveRev =
-
-; Environment variable expansion of command line arguments has been depricated
-; in favor shell level expansion. Universal environment variable expansion
-; inside -f files is support and continued support for MGC Location Maps provide
-; alternative methods for handling flexible pathnames.
-; The following line may be uncommented and the value set to 1 to re-enable this
-; deprecated behavior. The default value is 0.
-; DeprecatedEnvironmentVariableExpansion = 0
-
-; Turn on/off collapsing of bus ports in VCD dumpports output
-DumpportsCollapse = 1
-
-; Location of Multi-Level Verification Component (MVC) installation.
-; The default location is the product installation directory.
-; MvcHome = $MODEL_TECH/...
-
-; Initialize SystemVerilog enums using the base type's default value
-; instead of the leftmost value.
-; EnumBaseInit = 1
-
-[lmc]
-; The simulator's interface to Logic Modeling's SmartModel SWIFT software
-libsm = $MODEL_TECH/libsm.sl
-; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
-; libsm = $MODEL_TECH/libsm.dll
-; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
-; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
-; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
-; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
-; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
-; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
-; Logic Modeling's SmartModel SWIFT software (Windows NT)
-; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
-; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
-; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
-; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
-; libswift = $LMC_HOME/lib/linux.lib/libswift.so
-
-; The simulator's interface to Logic Modeling's hardware modeler SFI software
-libhm = $MODEL_TECH/libhm.sl
-; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
-; libhm = $MODEL_TECH/libhm.dll
-; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
-; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
-; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
-; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
-; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
-; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
-; Logic Modeling's hardware modeler SFI software (Windows NT)
-; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
-; Logic Modeling's hardware modeler SFI software (Linux)
-; libsfi = <sfi_dir>/lib/linux/libsfi.so
-
-[msg_system]
-; Change a message severity or suppress a message.
-; The format is: <msg directive> = <msg number>[,<msg number>...]
-; suppress can be used to achieve +nowarn<CODE> functionality
-; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
-; Examples:
-suppress = 8780
-; note = 3009
-; warning = 3033
-; error = 3010,3016
-; fatal = 3016,3033
-; suppress = 3009,3016,3043
-; suppress = 3009,CNNODP,3043,TFMPC
-; suppress = 8683,8684
-; The command verror <msg number> can be used to get the complete
-; description of a message.
-
-; Control transcripting of Verilog display system task messages and
-; PLI/FLI print function call messages. The system tasks include
-; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They
-; also include the analogous file I/O tasks that write to STDOUT
-; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
-; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
-; is to have messages appear only in the transcript. The other
-; settings are to send messages to the wlf file only (messages that
-; are recorded in the wlf file can be viewed in the MsgViewer) or
-; to both the transcript and the wlf file. The valid values are
-; tran {transcript only (default)}
-; wlf {wlf file only}
-; both {transcript and wlf file}
-; displaymsgmode = tran
-
-; Control transcripting of elaboration/runtime messages not
-; addressed by the displaymsgmode setting. The default is to
-; have messages appear in the transcript and recorded in the wlf
-; file (messages that are recorded in the wlf file can be viewed
-; in the MsgViewer). The other settings are to send messages
-; only to the transcript or only to the wlf file. The valid
-; values are
-; both {default}
-; tran {transcript only}
-; wlf {wlf file only}
-; msgmode = both
-[Project]
-; Warning -- Do not edit the project properties directly.
-; Property names are dynamic in nature and property
-; values have special syntax. Changing property data directly
-; can result in a corrupt MPF file. All project properties
-; can be modified through project window dialogs.
-Project_Version = 6
-Project_DefaultLib = work
-Project_SortMethod = unused
-Project_Files_Count = 20
-Project_File_0 = /d/jspc22/trb/cvs/trb3/wasa/cores/efb_define_def.v
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1344528395 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_1 = /d/jspc22/trb/cvs/trbnet/trb_net_components.vhd
-Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346851369 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_2 = /d/jspc22/trb/cvs/trb3/wasa/source/pwm.vhd
-Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355218918 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_3 = /d/jspc22/trb/cvs/trb3/tdc_test/modelsim/sim_pulsestretch.vhd
-Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355306195 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_4 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/full_tb.vhd
-Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355226184 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_5 = /d/jspc22/trb/cvs/trb3/wasa/source/spi_slave.vhd
-Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346854393 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_6 = /d/jspc22/trb/cvs/trb3/wasa/version.vhd
-Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355493687 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_7 = /d/jspc22/trb/cvs/trb3/base/trb3_components.vhd
-Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355506570 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_8 = /d/jspc22/trb/cvs/trb3/wasa/panda_dirc_wasa.vhd
-Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355487288 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_9 = /d/jspc22/trb/cvs/trbnet/trb_net_std.vhd
-Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346849814 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_10 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/pwm_tb.vhd
-Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344272681 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_11 = /d/jspc22/trb/cvs/trb3/wasa/cores/UFM_WB.v
-Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1355162337 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+/d/jspc22/trb/cvs/trb3/wasa/cores\7f compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_12 = /d/jspc22/trb/cvs/trbnet/trb_net_onewire.vhd
-Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350049 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_13 = /d/jspc22/trb/cvs/trbnet/special/spi_ltc2600.vhd
-Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1350664433 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_14 = /d/jspc22/trb/fifotest/tb_fifo_36x8k_oreg_tmpl.vhd
-Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355754626 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 19 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_15 = /d/jspc22/trb/cvs/trb3/wasa/cores/flashram.vhd
-Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344516091 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_16 = /d/jspc22/trb/cvs/trb3/wasa/cores/flash.vhd
-Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355147411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_17 = /d/jspc22/trb/fifotest/fifo_36x4k_oreg.vhd
-Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355754876 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 18 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_18 = /d/jspc22/trb/cvs/trb3/wasa/cores/pll.vhd
-Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346849713 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_19 = /d/jspc22/trb/cvs/trb3/wasa/cores/oddr16.vhd
-Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344002544 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_Sim_Count = 0
-Project_Folder_Count = 0
-Echo_Compile_Output = 0
-Save_Compile_Report = 1
-Project_Opt_Count = 0
-ForceSoftPaths = 0
-ProjectStatusDelay = 5000
-VERILOG_DoubleClick = Edit
-VERILOG_CustomDoubleClick =
-SYSTEMVERILOG_DoubleClick = Edit
-SYSTEMVERILOG_CustomDoubleClick =
-VHDL_DoubleClick = Edit
-VHDL_CustomDoubleClick =
-PSL_DoubleClick = Edit
-PSL_CustomDoubleClick =
-TEXT_DoubleClick = Edit
-TEXT_CustomDoubleClick =
-SYSTEMC_DoubleClick = Edit
-SYSTEMC_CustomDoubleClick =
-TCL_DoubleClick = Edit
-TCL_CustomDoubleClick =
-MACRO_DoubleClick = Edit
-MACRO_CustomDoubleClick =
-VCD_DoubleClick = Edit
-VCD_CustomDoubleClick =
-SDF_DoubleClick = Edit
-SDF_CustomDoubleClick =
-XML_DoubleClick = Edit
-XML_CustomDoubleClick =
-LOGFILE_DoubleClick = Edit
-LOGFILE_CustomDoubleClick =
-UCDB_DoubleClick = Edit
-UCDB_CustomDoubleClick =
-UPF_DoubleClick = Edit
-UPF_CustomDoubleClick =
-PCF_DoubleClick = Edit
-PCF_CustomDoubleClick =
-PROJECT_DoubleClick = Edit
-PROJECT_CustomDoubleClick =
-Project_Major_Version = 10
-Project_Minor_Version = 0
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-
-
-entity ffarray is
- port(
- CLK : in std_logic;
- RESET_IN : in std_logic;
- SIGNAL_IN : in std_logic;
-
- DATA_OUT : out std_logic_vector(7 downto 0);
- READ_IN : in std_logic := '0';
- EMPTY_OUT : out std_logic := '0'
- );
-end entity;
-
-architecture ffarray_arch of ffarray is
-
-signal CLKt : std_logic_vector(3 downto 0);
-signal CLKa : std_logic_vector(7 downto 0);
-
-signal final, final1, final2 : std_logic_vector(7 downto 0);
-signal final_t : std_logic_vector(7 downto 0);
-
-type ffarr_t is array(0 to 3) of std_logic_vector(7 downto 0);
-signal ffarr : ffarr_t;
-
-type ram_t is array(0 to 1023) of std_logic_vector(7 downto 0);
-signal ram : ram_t;
-
-signal fifo_write : std_logic;
-
-
- attribute syn_preserve : boolean;
- attribute syn_keep : boolean;
-
- attribute syn_preserve of CLKa : signal is true;
- attribute syn_keep of CLKa : signal is true;
- attribute syn_preserve of CLKt : signal is true;
- attribute syn_keep of CLKt : signal is true;
-
-
-begin
-
-THE_PLL : entity work.pll_shifted_clocks
- port map(
- CLKI => CLK,
- CLKOP => CLKt(0),
- CLKOS => CLKt(1),
- CLKOS2 => CLKt(2),
- CLKOS3 => CLKt(3)
- );
-
-CLKa(3 downto 0) <= CLKt(3 downto 0) xor x"0";
-CLKa(7 downto 4) <= not CLKt(3 downto 0);
-
-gen_ffarr_first : for i in 0 to 7 generate
- ffarr(0)(i) <= SIGNAL_IN when rising_edge(CLKa(i));
- ffarr(1)(i) <= ffarr(0)(i) when rising_edge(CLKa((i/4)*4));
- ffarr(2)(i) <= ffarr(1)(i) when rising_edge(CLKa(0));
-end generate;
-
-process begin
- wait until falling_edge(CLK);
- final_t <= ffarr(2);
-end process;
-
-
-process begin
- wait until rising_edge(CLK);
- final1 <= final_t;
- final2 <= ffarr(2);
- if (final1(7) xor final1(0)) = '1' then
- fifo_write <= '1';
- final <= final1;
- elsif (final2(7) xor final2(0)) = '1' then
- fifo_write <= '1';
- final <= final2;
- else
- fifo_write <= '0';
- end if;
-end process;
-
-
-THE_FIFO : entity work.fifo_1kx8
- port map(
- Data => final,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => fifo_write,
- RdEn => READ_IN,
- Reset => RESET_IN,
- RPReset => RESET_IN,
- Q => DATA_OUT,
- Empty => EMPTY_OUT,
- Full => open,
- AlmostEmpty => open,
- AlmostFull => open
- );
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-\r
-\r
-entity lcd is\r
- port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- \r
- MOSI : out std_logic;\r
- SCK : out std_logic;\r
- DC : out std_logic;\r
- CS : out std_logic;\r
- RST : out std_logic;\r
- \r
- INPUT: in std_logic_vector(255 downto 0);\r
- LED : out std_logic_vector(3 downto 0)\r
- \r
- );\r
-end entity;\r
-\r
-\r
-\r
-architecture base of lcd is\r
--- Font size in bytes : 2002\r
--- Font width : 10\r
--- Font height : 16\r
--- Font first char : 0x20\r
--- Font last char : 0x7E\r
-type fontram_t is array (0 to 2047) of std_logic_vector(7 downto 0);\r
-constant fontram : fontram_t := ( \r
- x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", \r
- x"00", x"00", x"00", x"00",\r
- x"00", x"00", x"00", x"00", x"00", x"00", x"FF", x"33", x"FF", x"33", x"FF", x"33", x"00", x"00", x"00", x"00", \r
- x"00", x"00", x"00", x"00", x"00", x"00", x"1F", x"00", x"1F", x"00", x"1F", x"00", x"00", x"00", x"00", x"00", \r
- x"1F", x"00", x"1F", x"00", x"1F", x"00", x"00", x"00", x"00", x"32", x"20", x"3F", x"F8", x"0F", x"FE", x"02", \r
- x"26", x"32", x"A0", x"3F", x"F8", x"0F", x"7E", x"02", x"26", x"02", x"20", x"00", x"38", x"30", x"7C", x"70", \r
- x"FE", x"60", x"C6", x"60", x"FF", x"FF", x"FF", x"FF", x"06", x"63", x"06", x"3F", x"04", x"1C", x"00", x"00", \r
- x"3C", x"60", x"7E", x"38", x"42", x"1C", x"7E", x"0E", x"FE", x"3F", x"FC", x"7F", x"70", x"7E", x"38", x"42", \r
- x"1C", x"7E", x"06", x"3C", x"00", x"1E", x"00", x"3F", x"BC", x"7F", x"FE", x"71", x"FE", x"63", x"E6", x"67", \r
- x"3E", x"7F", x"1C", x"7C", x"00", x"7F", x"00", x"47", x"00", x"00", x"00", x"00", x"00", x"00", x"1F", x"00", \r
- x"1F", x"00", x"1F", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"C0", x"03", \r
- x"F0", x"0F", x"FC", x"3F", x"3E", x"7C", x"0E", x"70", x"07", x"E0", x"03", x"C0", x"03", x"C0", x"00", x"00", \r
- x"00", x"00", x"03", x"C0", x"03", x"C0", x"07", x"E0", x"0E", x"70", x"3E", x"7C", x"FC", x"3F", x"F0", x"0F", \r
- x"C0", x"03", x"00", x"00", x"18", x"00", x"98", x"00", x"D8", x"01", x"DE", x"01", x"4E", x"00", x"DE", x"01", \r
- x"D8", x"01", x"98", x"00", x"18", x"00", x"00", x"00", x"00", x"00", x"00", x"03", x"00", x"03", x"00", x"03", \r
- x"F0", x"3F", x"F0", x"3F", x"F0", x"3F", x"00", x"03", x"00", x"03", x"00", x"03", x"00", x"00", x"00", x"4E", \r
- x"00", x"7E", x"00", x"7E", x"00", x"1E", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", \r
- x"00", x"00", x"80", x"01", x"80", x"01", x"80", x"01", x"80", x"01", x"80", x"01", x"80", x"01", x"80", x"01", \r
- x"80", x"01", x"00", x"00", x"00", x"00", x"00", x"38", x"00", x"38", x"00", x"38", x"00", x"38", x"00", x"00", \r
- x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"60", x"00", x"78", x"00", x"7F", \r
- x"E0", x"1F", x"F8", x"07", x"FE", x"00", x"1E", x"00", x"06", x"00", x"00", x"00", x"F0", x"0F", x"F8", x"1F", \r
- x"FC", x"3F", x"1E", x"78", x"06", x"60", x"06", x"60", x"1E", x"78", x"FC", x"3F", x"FC", x"1F", x"F0", x"0F", \r
- x"00", x"60", x"18", x"60", x"1C", x"60", x"0C", x"60", x"FE", x"7F", x"FE", x"7F", x"FE", x"7F", x"00", x"60", \r
- x"00", x"60", x"00", x"60", x"0C", x"70", x"0E", x"78", x"06", x"7C", x"06", x"6E", x"06", x"67", x"8E", x"63", \r
- x"FE", x"61", x"FC", x"60", x"78", x"60", x"00", x"60", x"00", x"00", x"0C", x"60", x"CE", x"60", x"C6", x"60", \r
- x"C6", x"60", x"E6", x"71", x"FE", x"7F", x"BE", x"3F", x"1C", x"1E", x"00", x"00", x"00", x"06", x"80", x"07", \r
- x"C0", x"07", x"E0", x"06", x"78", x"06", x"1C", x"06", x"FE", x"7F", x"FE", x"7F", x"FE", x"7F", x"00", x"06", \r
- x"00", x"00", x"FE", x"60", x"FE", x"60", x"FE", x"60", x"C6", x"60", x"C6", x"71", x"C6", x"7F", x"86", x"3F", \r
- x"06", x"1F", x"06", x"0E", x"E0", x"0F", x"F8", x"3F", x"FC", x"3F", x"9E", x"71", x"CE", x"60", x"C6", x"60", \r
- x"C6", x"71", x"C6", x"7F", x"84", x"3F", x"00", x"1F", x"06", x"00", x"06", x"60", x"06", x"7C", x"06", x"7F", \r
- x"C6", x"1F", x"F6", x"03", x"FE", x"00", x"3E", x"00", x"0E", x"00", x"06", x"00", x"00", x"1E", x"3C", x"3F", \r
- x"7C", x"7F", x"FE", x"71", x"E6", x"61", x"C6", x"61", x"FE", x"73", x"7E", x"7F", x"3C", x"3F", x"00", x"1E", \r
- x"F8", x"00", x"FC", x"21", x"FE", x"63", x"8E", x"63", x"06", x"63", x"06", x"73", x"8E", x"79", x"FC", x"3F", \r
- x"FC", x"1F", x"F0", x"07", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"1C", x"38", x"1C", x"38", x"1C", \r
- x"38", x"1C", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"9C", x"38", x"FC", x"38", x"FC", \r
- x"38", x"3C", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"80", x"01", x"80", x"01", \r
- x"C0", x"03", x"E0", x"07", x"60", x"06", x"70", x"0E", x"30", x"0C", x"38", x"1C", x"18", x"18", x"18", x"18", \r
- x"30", x"03", x"30", x"03", x"30", x"03", x"30", x"03", x"30", x"03", x"30", x"03", x"30", x"03", x"30", x"03", \r
- x"30", x"03", x"30", x"03", x"18", x"18", x"18", x"18", x"38", x"1C", x"30", x"0C", x"70", x"0E", x"60", x"06", \r
- x"E0", x"07", x"C0", x"03", x"80", x"01", x"80", x"01", x"0E", x"00", x"0E", x"00", x"06", x"00", x"06", x"66", \r
- x"06", x"67", x"86", x"67", x"CE", x"01", x"FE", x"00", x"7C", x"00", x"3C", x"00", x"F0", x"0F", x"FC", x"3F", \r
- x"1C", x"38", x"C6", x"67", x"E2", x"4F", x"32", x"4C", x"36", x"4C", x"3E", x"6C", x"FC", x"6F", x"F8", x"0F", \r
- x"00", x"38", x"80", x"3F", x"E0", x"1F", x"FC", x"07", x"3C", x"06", x"3C", x"06", x"FC", x"07", x"E0", x"1F", \r
- x"80", x"3F", x"00", x"38", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"8C", x"31", x"8C", x"31", x"8C", x"31", \r
- x"CC", x"33", x"FC", x"3F", x"78", x"1F", x"78", x"1E", x"E0", x"07", x"F0", x"0F", x"F8", x"1F", x"38", x"1C", \r
- x"1C", x"38", x"0C", x"30", x"0C", x"30", x"0C", x"30", x"1C", x"30", x"18", x"10", x"FC", x"3F", x"FC", x"3F", \r
- x"FC", x"3F", x"0C", x"30", x"0C", x"30", x"1C", x"38", x"3C", x"3C", x"F8", x"1F", x"F8", x"0F", x"E0", x"07", \r
- x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"8C", x"31", x"8C", x"31", x"8C", x"31", x"8C", x"31", x"8C", x"31", \r
- x"0C", x"30", x"0C", x"30", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"8C", x"01", x"8C", x"01", x"8C", x"01", \r
- x"8C", x"01", x"8C", x"01", x"0C", x"00", x"0C", x"00", x"E0", x"07", x"F0", x"0F", x"F8", x"1F", x"38", x"1C", \r
- x"1C", x"38", x"0C", x"30", x"8C", x"31", x"8C", x"31", x"9C", x"3F", x"98", x"1F", x"FC", x"3F", x"FC", x"3F", \r
- x"FC", x"3F", x"80", x"01", x"80", x"01", x"80", x"01", x"80", x"01", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", \r
- x"0C", x"30", x"0C", x"30", x"0C", x"30", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"0C", x"30", x"0C", x"30", \r
- x"0C", x"30", x"00", x"00", x"00", x"00", x"00", x"30", x"0C", x"30", x"0C", x"30", x"0C", x"30", x"0C", x"38", \r
- x"FC", x"3F", x"FC", x"1F", x"FC", x"0F", x"00", x"00", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"C0", x"03", \r
- x"E0", x"07", x"78", x"0F", x"3C", x"1E", x"1C", x"3C", x"0C", x"38", x"04", x"30", x"FC", x"3F", x"FC", x"3F", \r
- x"FC", x"3F", x"00", x"30", x"00", x"30", x"00", x"30", x"00", x"30", x"00", x"30", x"00", x"30", x"00", x"00", \r
- x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"F8", x"00", x"F0", x"07", x"C0", x"07", x"E0", x"07", x"F8", x"00", \r
- x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"F8", x"00", x"F0", x"03", x"C0", x"0F", \r
- x"00", x"1F", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"E0", x"07", x"F8", x"1F", x"F8", x"1F", x"1C", x"38", \r
- x"0C", x"30", x"0C", x"30", x"1C", x"38", x"F8", x"1F", x"F8", x"1F", x"E0", x"07", x"FC", x"3F", x"FC", x"3F", \r
- x"FC", x"3F", x"8C", x"01", x"8C", x"01", x"8C", x"01", x"CC", x"01", x"FC", x"01", x"F8", x"00", x"78", x"00", \r
- x"E0", x"07", x"F8", x"0F", x"F8", x"1F", x"1C", x"38", x"0C", x"30", x"0C", x"70", x"1C", x"F8", x"F8", x"DF", \r
- x"F8", x"CF", x"E0", x"87", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"8C", x"01", x"8C", x"03", x"CC", x"07", \r
- x"FC", x"1F", x"FC", x"3E", x"78", x"38", x"00", x"30", x"78", x"18", x"F8", x"38", x"FC", x"38", x"CC", x"30", \r
- x"8C", x"31", x"8C", x"31", x"8C", x"33", x"1C", x"3F", x"18", x"1F", x"00", x"0E", x"00", x"00", x"0C", x"00", \r
- x"0C", x"00", x"0C", x"00", x"FC", x"3F", x"FC", x"3F", x"FC", x"3F", x"0C", x"00", x"0C", x"00", x"0C", x"00", \r
- x"FC", x"0F", x"FC", x"1F", x"FC", x"3F", x"00", x"38", x"00", x"30", x"00", x"30", x"00", x"38", x"FC", x"3F", \r
- x"FC", x"1F", x"FC", x"0F", x"0C", x"00", x"FC", x"00", x"F8", x"03", x"E0", x"1F", x"80", x"3F", x"00", x"3C", \r
- x"80", x"3F", x"E0", x"1F", x"FC", x"03", x"3C", x"00", x"00", x"00", x"FC", x"07", x"FC", x"1F", x"00", x"3F", \r
- x"C0", x"1F", x"E0", x"07", x"C0", x"1F", x"00", x"3F", x"FC", x"1F", x"FC", x"07", x"00", x"00", x"0C", x"30", \r
- x"1C", x"38", x"78", x"1E", x"E0", x"07", x"C0", x"03", x"E0", x"07", x"78", x"1E", x"1C", x"38", x"0C", x"30", \r
- x"00", x"00", x"1C", x"00", x"7C", x"00", x"F0", x"00", x"E0", x"3F", x"80", x"3F", x"E0", x"3F", x"F0", x"00", \r
- x"7C", x"00", x"1C", x"00", x"0C", x"38", x"0C", x"3C", x"0C", x"3E", x"0C", x"3F", x"8C", x"37", x"CC", x"33", \r
- x"EC", x"31", x"FC", x"30", x"7C", x"30", x"1C", x"30", x"00", x"00", x"00", x"00", x"FF", x"FF", x"FF", x"FF", \r
- x"FF", x"FF", x"03", x"C0", x"03", x"C0", x"03", x"C0", x"03", x"C0", x"00", x"00", x"00", x"00", x"07", x"00", \r
- x"1F", x"00", x"FF", x"00", x"F8", x"07", x"E0", x"1F", x"00", x"FF", x"00", x"F8", x"00", x"E0", x"00", x"00", \r
- x"00", x"00", x"03", x"C0", x"03", x"C0", x"03", x"C0", x"03", x"C0", x"FF", x"FF", x"FF", x"FF", x"FF", x"FF", \r
- x"00", x"00", x"00", x"00", x"00", x"00", x"80", x"01", x"E0", x"01", x"FC", x"00", x"1E", x"00", x"1E", x"00", \r
- x"FC", x"00", x"E0", x"01", x"80", x"01", x"00", x"00", x"00", x"C0", x"00", x"C0", x"00", x"C0", x"00", x"C0", \r
- x"00", x"C0", x"00", x"C0", x"00", x"C0", x"00", x"C0", x"00", x"C0", x"00", x"C0", x"00", x"00", x"00", x"00", \r
- x"00", x"00", x"02", x"00", x"06", x"00", x"06", x"00", x"04", x"00", x"00", x"00", x"00", x"00", x"00", x"00", \r
- x"00", x"1C", x"60", x"3E", x"70", x"3F", x"30", x"33", x"30", x"31", x"30", x"39", x"F0", x"1F", x"F0", x"3F", \r
- x"E0", x"3F", x"00", x"30", x"FE", x"3F", x"FE", x"3F", x"FE", x"3F", x"60", x"38", x"30", x"30", x"30", x"30", \r
- x"70", x"38", x"F0", x"3F", x"E0", x"1F", x"C0", x"07", x"80", x"07", x"E0", x"1F", x"E0", x"1F", x"70", x"38", \r
- x"30", x"38", x"30", x"30", x"30", x"30", x"30", x"30", x"30", x"30", x"20", x"10", x"80", x"0F", x"E0", x"1F", \r
- x"F0", x"3F", x"70", x"38", x"30", x"30", x"30", x"30", x"70", x"38", x"FE", x"3F", x"FE", x"3F", x"FE", x"3F", \r
- x"80", x"0F", x"E0", x"1F", x"E0", x"1F", x"70", x"3B", x"30", x"33", x"30", x"33", x"70", x"33", x"F0", x"33", \r
- x"E0", x"3B", x"C0", x"1B", x"60", x"00", x"60", x"00", x"60", x"00", x"FC", x"3F", x"FE", x"3F", x"FF", x"3F", \r
- x"63", x"00", x"63", x"00", x"63", x"00", x"63", x"00", x"80", x"0F", x"E0", x"4F", x"F0", x"DF", x"70", x"DC", \r
- x"30", x"D8", x"30", x"D8", x"70", x"D8", x"F0", x"FF", x"F0", x"FF", x"F0", x"7F", x"FE", x"3F", x"FE", x"3F", \r
- x"FE", x"3F", x"60", x"00", x"70", x"00", x"30", x"00", x"30", x"00", x"F0", x"3F", x"F0", x"3F", x"E0", x"3F", \r
- x"00", x"00", x"30", x"00", x"30", x"00", x"30", x"00", x"30", x"00", x"F3", x"3F", x"F3", x"3F", x"F3", x"3F", \r
- x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"60", x"30", x"E0", x"30", x"C0", x"30", x"C0", x"30", x"C0", \r
- x"F3", x"FF", x"F3", x"7F", x"F3", x"3F", x"00", x"00", x"FE", x"3F", x"FE", x"3F", x"FE", x"3F", x"80", x"07", \r
- x"E0", x"0F", x"F0", x"1F", x"70", x"3C", x"30", x"38", x"10", x"30", x"00", x"20", x"00", x"00", x"06", x"00", \r
- x"06", x"00", x"06", x"00", x"06", x"00", x"FE", x"3F", x"FE", x"3F", x"FE", x"3F", x"00", x"00", x"00", x"00", \r
- x"F0", x"3F", x"F0", x"3F", x"F0", x"3F", x"70", x"00", x"F0", x"3F", x"E0", x"3F", x"70", x"00", x"F0", x"3F", \r
- x"F0", x"3F", x"E0", x"3F", x"F0", x"3F", x"F0", x"3F", x"F0", x"3F", x"60", x"00", x"70", x"00", x"30", x"00", \r
- x"30", x"00", x"F0", x"3F", x"F0", x"3F", x"E0", x"3F", x"80", x"07", x"E0", x"1F", x"E0", x"1F", x"70", x"38", \r
- x"30", x"30", x"30", x"30", x"70", x"38", x"E0", x"1F", x"E0", x"1F", x"80", x"07", x"F0", x"FF", x"F0", x"FF", \r
- x"F0", x"FF", x"70", x"1C", x"30", x"18", x"30", x"18", x"70", x"1C", x"F0", x"1F", x"E0", x"0F", x"C0", x"07", \r
- x"80", x"07", x"E0", x"0F", x"F0", x"1F", x"70", x"1C", x"30", x"18", x"30", x"18", x"70", x"1C", x"F0", x"FF", \r
- x"F0", x"FF", x"F0", x"FF", x"00", x"00", x"F0", x"3F", x"F0", x"3F", x"F0", x"3F", x"70", x"00", x"30", x"00", \r
- x"30", x"00", x"70", x"00", x"70", x"00", x"00", x"00", x"E0", x"18", x"F0", x"39", x"F0", x"31", x"B0", x"33", \r
- x"30", x"33", x"30", x"33", x"30", x"3F", x"30", x"1E", x"00", x"1C", x"00", x"00", x"30", x"00", x"30", x"00", \r
- x"30", x"00", x"FC", x"1F", x"FC", x"3F", x"FC", x"3F", x"30", x"30", x"30", x"30", x"30", x"30", x"30", x"30", \r
- x"F0", x"1F", x"F0", x"3F", x"F0", x"3F", x"00", x"30", x"00", x"30", x"00", x"38", x"00", x"18", x"F0", x"3F", \r
- x"F0", x"3F", x"F0", x"3F", x"10", x"00", x"F0", x"00", x"F0", x"03", x"E0", x"1F", x"00", x"3F", x"00", x"3C", \r
- x"C0", x"3F", x"F0", x"0F", x"F0", x"01", x"30", x"00", x"30", x"00", x"F0", x"0F", x"E0", x"3F", x"00", x"1E", \r
- x"C0", x"03", x"C0", x"03", x"00", x"1E", x"E0", x"3F", x"F0", x"0F", x"30", x"00", x"10", x"20", x"30", x"30", \r
- x"F0", x"3C", x"F0", x"1F", x"C0", x"07", x"C0", x"0F", x"E0", x"3F", x"F0", x"3C", x"30", x"30", x"10", x"20", \r
- x"10", x"00", x"F0", x"00", x"F0", x"C3", x"E0", x"CF", x"00", x"FF", x"00", x"7F", x"C0", x"0F", x"F0", x"01", \r
- x"F0", x"00", x"10", x"00", x"30", x"30", x"30", x"38", x"30", x"3C", x"30", x"3E", x"30", x"37", x"B0", x"33", \r
- x"F0", x"31", x"F0", x"30", x"70", x"30", x"30", x"30", x"00", x"00", x"80", x"01", x"80", x"01", x"FE", x"7F", \r
- x"FF", x"FF", x"7F", x"FE", x"03", x"C0", x"03", x"C0", x"03", x"C0", x"00", x"00", x"00", x"00", x"00", x"00", \r
- x"00", x"00", x"FF", x"FF", x"FF", x"FF", x"FF", x"FF", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", \r
- x"00", x"00", x"03", x"C0", x"03", x"C0", x"03", x"C0", x"7F", x"FE", x"FF", x"FF", x"FE", x"7F", x"80", x"01", \r
- x"80", x"01", x"00", x"00", x"00", x"03", x"80", x"03", x"80", x"01", x"80", x"01", x"80", x"03", x"80", x"03", \r
- x"00", x"03", x"00", x"03", x"80", x"03", x"80", x"01", others => x"00");\r
-\r
- type initdc_t is array (0 to 15) of std_logic;\r
- constant initdc : initdc_t := ('0','1','0','1','0','0','1','1','1','1','0','1','1','1','1','0');\r
-\r
- type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);\r
- constant dataram : data_t := (\r
- x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00",\r
- x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C",\r
- x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",\r
- x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",\r
-\r
- \r
- x"50", x"61", x"64", x"69", x"77", x"61", x"20", x"53", x"74", x"61", x"74", x"75", x"73", x"0a", \r
- x"0a", \r
- x"54", x"65", x"6d", x"70", x"65", x"72", x"61", x"74", x"75", x"72", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"84", x"0a", \r
- x"55", x"49", x"44", x"20", x"20", x"83", x"82", x"81", x"80", x"0a",\r
- x"45", x"6e", x"61", x"62", x"6c", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"85", x"0a", \r
- x"49", x"6e", x"76", x"65", x"72", x"74", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"86", x"0a",\r
- x"49", x"6e", x"70", x"75", x"74", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20",x"20", x"87", x"0a", \r
- x"0a",\r
- x"54", x"69", x"6d", x"65", x"72", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"8F", x"8E", x"0a",\r
- others => x"00");\r
- \r
- \r
- signal timer : unsigned(27 downto 0) := (others => '0');\r
- --2**16: 2.5ms\r
- --2**20: 40ms\r
- \r
- type state_t is (RSTIDLE, RSTRESET, RSTWAIT, RSTSELECT, \r
- RSTCONFIG1, RSTCONFIG2, RSTCONFIG3, RSTCONFIG4, \r
- RSTCONFIG5, RSTCLEAR, RSTCLEAR2, RSTFINISH, WAITSTART,\r
- TSTART, WAITFONT, WRITEFONT, SETWINDOW,\r
- WRITEWAIT, WRITESECONDBYTE, GETNIBBLE, \r
- GETHEX, NEXTCHAR);\r
- type spistate_t is (SPIIDLE, SPISEND1, SPISEND2, SPISEND3, SPISEND4);\r
-\r
- signal state : state_t;\r
- signal spistate : spistate_t; \r
-\r
- signal cnt : integer range 0 to 200000 := 0; --general purpose counter\r
- signal datapos : integer range 0 to 1023; --pointer in data ROM\r
- signal fontpos : integer range 0 to 2047; --pointer in font ROM\r
- \r
- signal spi_data : std_logic_vector(7 downto 0);\r
- signal spi_dc : std_logic;\r
- signal spi_send : std_logic;\r
- signal spi_idle : std_logic;\r
- signal spi_busy : std_logic;\r
- signal spi_cnt : integer range 0 to 7 := 0;\r
- signal spi_buf : std_logic_vector(7 downto 0);\r
- \r
- signal poscol : integer range 0 to 239 := 0; --horizontal position\r
- signal posrow : integer range 0 to 19 := 0; --vertical position in 16px steps\r
- \r
- signal curdata : std_logic_vector(7 downto 0); --current byte in data ROM\r
- signal curfont : std_logic_vector(7 downto 0); --curent font byte\r
- signal nibble : unsigned (7 downto 0); --var. nibble to show\r
- signal varcnt : integer range 0 to 4 := 0; --position within variable\r
- \r
- signal pixcnt : integer range 0 to 15 := 0; --Pixel count when plotting fonts\r
- signal bytecnt : integer range 0 to 1 := 0; --high or low byte when plotting fonts\r
- signal colcnt : integer range 0 to 15 := 0; --number of cols in current char\r
- \r
-begin\r
-\r
-spi_idle <= not spi_busy and not spi_send;\r
-\r
-\r
-spi_fsm : process begin\r
- wait until rising_edge(CLK);\r
- case spistate is\r
- when SPIIDLE =>\r
- MOSI <= '0';\r
- SCK <= '0';\r
- spi_busy <= '0';\r
- if spi_send = '1' then\r
- spistate <= SPISEND1;\r
- spi_buf <= spi_data;\r
- spi_busy <= '1';\r
- spi_cnt <= 7;\r
- DC <= spi_dc;\r
- end if;\r
- when SPISEND1 => \r
- spistate <= SPISEND2;\r
- SCK <= '0';\r
- MOSI <= spi_buf(spi_cnt);\r
- when SPISEND2 => \r
- spistate <= SPISEND3;\r
- SCK <= '0';\r
- MOSI <= spi_buf(spi_cnt);\r
- when SPISEND3 => \r
- spistate <= SPISEND4;\r
- SCK <= '1';\r
- MOSI <= spi_buf(spi_cnt);\r
- when SPISEND4 => \r
- SCK <= '1';\r
- MOSI <= spi_buf(spi_cnt);\r
- if spi_cnt = 0 then\r
- spistate <= SPIIDLE;\r
- else\r
- spistate <= SPISEND1;\r
- spi_cnt <= spi_cnt - 1;\r
- end if;\r
- end case;\r
- if RESET = '1' then\r
- spistate <= SPIIDLE;\r
- end if;\r
-end process;\r
-\r
-\r
-fsm : process begin\r
- wait until rising_edge(CLK);\r
- timer <= timer + 1;\r
- RST <= '1';\r
- CS <= '0';\r
- spi_send <= '0';\r
- LED(0) <= '1';\r
- case state is\r
--------------------------------------------------------------- \r
--- Reset sequence\r
--------------------------------------------------------------- \r
- when RSTIDLE =>\r
- RST <= '1';\r
- CS <= '1';\r
- if timer = x"4000000" then --2500ms\r
- state <= RSTRESET;\r
- timer <= (others => '0');\r
- end if; \r
- when RSTRESET =>\r
- RST <= '0';\r
- CS <= '1';\r
- if timer = x"0300000" then --120ms\r
- state <= RSTWAIT;\r
- timer <= (others => '0');\r
- end if; \r
- when RSTWAIT =>\r
- RST <= '1';\r
- CS <= '1';\r
- if timer = x"0300000" then --120ms\r
- state <= RSTSELECT;\r
- timer <= (others => '0');\r
- end if; \r
- when RSTSELECT =>\r
- if timer = x"000000F" then --short...\r
- state <= RSTCONFIG1;\r
- spi_data <= x"11";\r
- spi_dc <= '0';\r
- spi_send <= '1';\r
- timer <= (others => '0');\r
- end if;\r
- when RSTCONFIG1 =>\r
- if timer = x"0200000" then --80ms\r
- state <= RSTCONFIG2;\r
- timer <= (others => '0');\r
- datapos <= 0;\r
- end if;\r
--------------------------------------------------------------- \r
--- Load config & clear display\r
--------------------------------------------------------------- \r
- when RSTCONFIG2 =>\r
- if spi_idle = '1' then\r
- if datapos = 15 then\r
- state <= RSTCLEAR;\r
- datapos <= 0;\r
- else\r
- datapos <= datapos + 1;\r
- end if;\r
- spi_data <= curdata;\r
- spi_dc <= initdc(datapos);\r
- spi_send <= '1';\r
- end if;\r
- when RSTCLEAR =>\r
- if spi_idle = '1' then\r
- cnt <= cnt + 1;\r
- spi_data <= x"20";\r
- spi_dc <= '1';\r
- spi_send <= '1';\r
- state <= RSTCLEAR2;\r
- if cnt = 320*240*2-1 then\r
- state <= RSTFINISH;\r
- end if;\r
- end if;\r
- when RSTCLEAR2 =>\r
- if spi_idle = '1' then\r
- cnt <= cnt + 1;\r
- spi_data <= x"8B";\r
- spi_dc <= '1';\r
- spi_send <= '1';\r
- state <= RSTCLEAR;\r
- if cnt = 320*240*2-1 then\r
- state <= RSTFINISH;\r
- end if;\r
- end if;\r
- when RSTFINISH =>\r
- LED(0) <= '0';\r
- poscol <= 0;\r
- posrow <= 0;\r
- datapos <= 32; --start of text section\r
- varcnt <= 4; --no nibble active\r
- state <= WAITSTART;\r
- \r
--------------------------------------------------------------- \r
--- Write text from memory\r
--------------------------------------------------------------- \r
- when NEXTCHAR =>\r
- state <= WAITSTART;\r
- if varcnt = 0 or varcnt = 4 then\r
- datapos <= datapos + 1;\r
- varcnt <= 4;\r
- end if;\r
- \r
- when WAITSTART =>\r
- state <= TSTART;\r
- when TSTART =>\r
- if curdata >= x"20" and curdata <= x"7E" then --plain text\r
- state <= SETWINDOW;\r
- cnt <= 0;\r
- colcnt <= 0;\r
- bytecnt <= 0;\r
- varcnt <= 4; \r
- fontpos <= (to_integer(unsigned(curdata)) - 32)*20;\r
- elsif curdata(7 downto 4) = x"8" then --show a variable\r
- state <= GETNIBBLE;\r
- varcnt <= varcnt - 1; --here: range 4..1\r
- nibble <= x"0" & unsigned(INPUT(to_integer(unsigned(curdata(3 downto 0)))*16+varcnt*4-1 downto \r
- to_integer(unsigned(curdata(3 downto 0)))*16+varcnt*4-4));\r
- elsif curdata = x"0a" then --line break\r
- poscol <= 0;\r
- posrow <= posrow + 1;\r
- datapos <= datapos + 1;\r
- state <= WAITSTART;\r
- elsif curdata = x"00" then --end of string\r
- state <= RSTFINISH;\r
- else --error, skip\r
- datapos <= datapos + 1;\r
- end if;\r
- \r
- when GETNIBBLE =>\r
- state <= GETHEX;\r
- if nibble < x"0a" then\r
- nibble <= nibble + x"30";\r
- else\r
- nibble <= nibble + x"57";\r
- end if;\r
- \r
- when GETHEX =>\r
- state <= SETWINDOW;\r
- cnt <= 0;\r
- colcnt <= 0;\r
- bytecnt <= 0;\r
- fontpos <= (to_integer(nibble) - 32)*20;\r
- \r
- when SETWINDOW =>\r
- if cnt < 11 then\r
- if spi_idle = '1' then\r
- cnt <= cnt + 1;\r
- spi_send <= '1';\r
- case cnt is\r
- when 0 => spi_dc <= '0'; spi_data <= x"2A";\r
- when 1 => spi_dc <= '1'; spi_data <= x"00";\r
- when 2 => spi_dc <= '1'; spi_data <= std_logic_vector(to_unsigned(poscol,8));\r
- when 3 => spi_dc <= '1'; spi_data <= x"00";\r
- when 4 => spi_dc <= '1'; spi_data <= std_logic_vector(to_unsigned(poscol,8));\r
- when 5 => spi_dc <= '0'; spi_data <= x"2B";\r
- when 6 => spi_dc <= '1'; spi_data <= std_logic_vector(to_unsigned(posrow/16,8));\r
- when 7 => spi_dc <= '1'; spi_data <= std_logic_vector(to_unsigned(posrow*16,8));\r
- when 8 => spi_dc <= '1'; spi_data <= std_logic_vector(to_unsigned((posrow*16+15)/256,8));\r
- when 9 => spi_dc <= '1'; spi_data <= std_logic_vector(to_unsigned(posrow*16+15,8));\r
- when 10=> spi_dc <= '0'; spi_data <= x"2C";\r
- end case;\r
- end if;\r
- else\r
- state <= WRITEFONT;\r
- spi_dc <= '1';\r
- bytecnt<= 0;\r
- pixcnt <= 0;\r
- end if;\r
-\r
- when WRITEWAIT =>\r
- state <= WRITEFONT;\r
- when WRITEFONT =>\r
- if pixcnt = 8 and bytecnt = 1 and colcnt < 10 then --end of column\r
- state <= SETWINDOW;\r
- cnt <= 0;\r
- poscol <= poscol + 1;\r
- colcnt <= colcnt + 1;\r
- fontpos <= fontpos + 1;\r
- elsif pixcnt = 8 and bytecnt = 1 and colcnt = 10 then --end of character\r
- state <= NEXTCHAR;\r
- poscol <= poscol + 1;\r
- elsif spi_idle = '1' then\r
- if pixcnt < 8 then\r
- state <= WRITESECONDBYTE;\r
- if colcnt < 10 and curfont(pixcnt) = '1' then\r
- if varcnt = 4 then\r
- spi_data <= x"FD";\r
- else\r
- spi_data <= x"FF";\r
- end if;\r
- else\r
- spi_data <= x"20";\r
- end if;\r
- spi_send <= '1';\r
- else\r
- state <= WRITEWAIT;\r
- fontpos <= fontpos + 1;\r
- pixcnt <= 0;\r
- bytecnt <= 1; \r
- end if;\r
- end if;\r
- when WRITESECONDBYTE =>\r
- if spi_idle = '1' then\r
- spi_send <= '1';\r
- if colcnt < 10 and curfont(pixcnt) = '1' then\r
- if varcnt = 4 then\r
- spi_data <= x"40";\r
- else\r
- spi_data <= x"FF";\r
- end if;\r
- else\r
- spi_data <= x"8B";\r
- end if;\r
- state <= WRITEFONT;\r
- pixcnt <= pixcnt + 1;\r
- end if;\r
- \r
- \r
- end case;\r
- if RESET = '1' then\r
- state <= RSTIDLE;\r
- datapos <= 0;\r
- end if;\r
-end process;\r
-\r
-ram : process begin\r
- wait until rising_edge(CLK);\r
- curdata <= dataram(datapos);\r
- curfont <= fontram(fontpos);\r
-end process;\r
-\r
-LED(1) <= spi_idle;\r
-LED(2) <= not spi_dc;\r
-LED(3) <= not spi_send;\r
-\r
- \r
-end architecture;\r
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-
-entity pwm_generator is
- port(
- CLK : in std_logic;
-
- DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');
- DATA_OUT : out std_logic_vector(15 downto 0);
- WRITE_IN : in std_logic := '0';
- COMP_IN : in signed(15 downto 0);
- ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0');
-
-
- PWM : out std_logic_vector(31 downto 0)
-
- );
-end entity;
-
-
-
-architecture pwm_arch of pwm_generator is
-
-type ram_t is array(0 to 15) of unsigned(15 downto 0);
-signal set : ram_t := (others => x"87C1");
-signal set_tmp : ram_t;
-
-type cnt_t is array(0 to 15) of unsigned(16 downto 0);
-signal cnt : cnt_t := (others => (others => '0'));
-
-signal last_flag : std_logic_vector(15 downto 0) := (others => '0');
-signal flag : std_logic_vector(15 downto 0) := (others => '0');
-signal pwm_i : std_logic_vector(15 downto 0) := (others => '0');
-
-signal i : integer range 0 to 15 := 0;
-
-begin
-
-PROC_MEM : process begin
- wait until rising_edge(CLK);
- if WRITE_IN = '1' then
- set(to_integer(unsigned(ADDR_IN))) <= unsigned(DATA_IN);
- end if;
- DATA_OUT <= std_logic_vector(set(to_integer(unsigned(ADDR_IN))));
-end process;
-
-
-GEN_REAL_VALUES : process begin
- wait until rising_edge(CLK);
- set_tmp(i) <= unsigned(signed(set(i)) + COMP_IN);
- i <= i + 1;
-end process;
-
-
-
-gen_channels : for i in 0 to 15 generate
- flag(i) <= cnt(i)(16);
- last_flag(i) <= flag(i) when rising_edge(CLK);
- pwm_i(i) <= (last_flag(i) xor flag(i)) when rising_edge(CLK);
- cnt(i) <= cnt(i) + resize(set_tmp(i),17) when rising_edge(CLK);
-end generate;
-
-
-PWM(31 downto 16) <= pwm_i(15 downto 0); --no high-res yet
-PWM(15 downto 0 ) <= pwm_i(15 downto 0);
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-
-library machxo2;
-use machxo2.all;
-
-
-entity spi_slave is
- port(
- CLK : in std_logic;
-
- SPI_CLK : in std_logic;
- SPI_CS : in std_logic;
- SPI_IN : in std_logic;
- SPI_OUT : out std_logic;
-
- DATA_OUT : out std_logic_vector(15 downto 0);
- REG00_IN : in std_logic_vector(15 downto 0);
- REG10_IN : in std_logic_vector(15 downto 0);
- REG20_IN : in std_logic_vector(15 downto 0);
- REG40_IN : in std_logic_vector(15 downto 0);
-
- OPERATION_OUT : out std_logic_vector(3 downto 0);
- CHANNEL_OUT : out std_logic_vector(7 downto 0);
- WRITE_OUT : out std_logic_vector(15 downto 0);
-
- DEBUG_OUT : out std_logic_vector(15 downto 0)
- );
-end entity;
-
-
-
-architecture spi_slave_arch of spi_slave is
-signal spi_clk_last : std_logic;
-signal spi_clk_reg : std_logic;
-signal spi_cs_reg : std_logic;
-signal spi_in_reg : std_logic;
-signal buf_SPI_OUT : std_logic;
-
-signal input : std_logic_vector(31 downto 0);
-signal output_data : std_logic_vector(31 downto 0);
-signal data_write : std_logic_vector(15 downto 0);
-signal write_i : std_logic_vector(15 downto 0) := x"0000";
-signal last_input : std_logic;
-signal bitcnt : integer range 0 to 31 := 31;
-
-signal next_output : std_logic;
-signal operation_i : std_logic_vector(3 downto 0) := x"0";
-signal channel_i : std_logic_vector(7 downto 0) := x"00";
-
-type state_t is (IDLE, WAIT_FOR_CMD, GET_DATA, PREPARE_OUTPUT, WRITE_DATA, WAIT_FINISH);
-signal state : state_t;
-
-begin
-
-spi_clk_last <= spi_clk_reg when rising_edge(CLK);
-spi_clk_reg <= SPI_CLK when rising_edge(CLK);
-spi_cs_reg <= SPI_CS when rising_edge(CLK);
-spi_in_reg <= SPI_IN when rising_edge(CLK);
-
-OPERATION_OUT <= operation_i;
-CHANNEL_OUT <= channel_i;
-DATA_OUT <= data_write;
-WRITE_OUT <= write_i;
-
-PROC_OUTPUT : process begin
- wait until rising_edge(CLK);
- next_output <= output_data(bitcnt);
- if spi_clk_reg = '0' and spi_clk_last = '1' then
- SPI_OUT <= last_input;
- if operation_i = x"0" and bitcnt <= 15 then
- SPI_OUT <= next_output;
- end if;
- end if;
-end process;
-
-
-PROC_INPUT_SHIFT : process begin
- wait until rising_edge(CLK);
- if spi_cs_reg = '1' then
- bitcnt <= 31;
- else
- if spi_clk_reg = '1' and spi_clk_last = '0' then
- if bitcnt /= 0 then
- bitcnt <= bitcnt - 1;
- else
- bitcnt <= 31;
- end if;
- last_input <= spi_in_reg;
- input(bitcnt) <= spi_in_reg;
- end if;
- end if;
-end process;
-
-
-PROC_GEN_SIGNALS : process begin
- wait until rising_edge(CLK);
- write_i <= (others => '0');
- case state is
- when IDLE =>
- channel_i <= x"ff";
- operation_i <= x"7";
- if spi_cs_reg = '0' then
- state <= WAIT_FOR_CMD;
- end if;
- when WAIT_FOR_CMD =>
- if bitcnt = 15 then
- operation_i <= input(23 downto 20);
- channel_i <= input(27 downto 24) & input(19 downto 16);
- state <= GET_DATA;
- end if;
- when GET_DATA =>
- state <= PREPARE_OUTPUT;
- when PREPARE_OUTPUT =>
- if input(31 downto 28) = x"0" then
- output_data(15 downto 0) <= REG00_IN;
- elsif input(31 downto 28) = x"1" then
- output_data(15 downto 0) <= REG10_IN;
- elsif input(31 downto 28) = x"2" then
- output_data(15 downto 0) <= REG20_IN;
- else
- output_data(15 downto 0) <= REG40_IN;
- end if;
- state <= WRITE_DATA;
- when WRITE_DATA =>
- if bitcnt = 31 then
- if operation_i(3) = '1' then
- data_write <= input(15 downto 0);
- write_i(to_integer(unsigned(input(31 downto 28)))) <= '1';
- end if;
- state <= WAIT_FINISH;
- end if;
- when WAIT_FINISH =>
- if spi_cs_reg = '1' then
- state <= IDLE;
- end if;
- end case;
-
- if spi_cs_reg = '1' then
- state <= IDLE;
- operation_i <= x"7";
- end if;
-end process;
-
-DEBUG_OUT(0) <= spi_clk_reg;
-DEBUG_OUT(1) <= spi_cs_reg;
-DEBUG_OUT(2) <= spi_in_reg;
-DEBUG_OUT(3) <= buf_SPI_OUT;
-DEBUG_OUT(7 downto 4) <= std_logic_vector(to_unsigned(bitcnt,4));
-DEBUG_OUT(14 downto 8) <= input(30 downto 24);
-DEBUG_OUT(15) <= write_i(4);
-
-
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-
-
-entity tb is
-end entity;
-
-
-
-architecture full_tb of tb is
-
-signal clk, reset : std_logic := '1';
-
-signal spi_clk, spi_in, spi_out : std_logic;
-
-signal spi_cs : std_logic_vector(15 downto 0) := x"ffff";
-signal bus_addr : std_logic_vector( 4 downto 0) := "00000";
-signal bus_data : std_logic_vector(31 downto 0) := (others => '0');
-signal bus_write: std_logic := '0';
-
-component spi_ltc2600 is
- port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- -- Slave bus
- BUS_READ_IN : in std_logic;
- BUS_WRITE_IN : in std_logic;
- BUS_BUSY_OUT : out std_logic;
- BUS_ACK_OUT : out std_logic;
- BUS_ADDR_IN : in std_logic_vector(4 downto 0);
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0);
- -- SPI connections
- SPI_CS_OUT : out std_logic_vector(15 downto 0);
- SPI_SDI_IN : in std_logic;
- SPI_SDO_OUT : out std_logic;
- SPI_SCK_OUT : out std_logic
- );
-end component;
-
-
-component panda_dirc_wasa is
- port(
- CON : out std_logic_vector(16 downto 1);
- INP : in std_logic_vector(16 downto 1);
- PWM : out std_logic_vector(16 downto 1);
- SPARE_LINE : out std_logic_vector(3 downto 0);
- SPARE_LVDS : out std_logic;
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SPI_CLK : in std_logic;
- SPI_CS : in std_logic;
- SPI_IN : in std_logic;
- SPI_OUT : out std_logic;
- TEMP_LINE : inout std_logic;
- TEST_LINE : out std_logic_vector(15 downto 0)
- );
-end component;
-
-begin
-
-clk <= not clk after 5 ns;
-reset <= '0' after 30 ns;
-
-process begin
- wait for 101 ns;
- bus_addr <= "00000";
- bus_data <= x"51800000";
- bus_write <= '1';
- wait for 10 ns;
- bus_write <= '0';
-
- wait for 101 ns;
- bus_addr <= "10000";
- bus_data <= x"00000001";
- bus_write <= '1';
- wait for 10 ns;
- bus_write <= '0';
-
- wait for 101 ns;
- bus_addr <= "10001";
- bus_data <= x"00000001";
- bus_write <= '1';
- wait for 10 ns;
- bus_write <= '0';
-
- wait for 10010 ns;
- bus_addr <= "00000";
- bus_data <= x"51810000";
- bus_write <= '1';
- wait for 10 ns;
- bus_write <= '0';
-
- wait for 101 ns;
- bus_addr <= "10000";
- bus_data <= x"00000001";
- bus_write <= '1';
- wait for 10 ns;
- bus_write <= '0';
-
- wait for 101 ns;
- bus_addr <= "10001";
- bus_data <= x"00000001";
- bus_write <= '1';
- wait for 10 ns;
- bus_write <= '0';
-
- wait for 10010 ns;
- bus_addr <= "00000";
- bus_data <= x"0080ffff";
- bus_write <= '1';
- wait for 10 ns;
- bus_write <= '0';
-
- wait for 101 ns;
- bus_addr <= "10000";
- bus_data <= x"00000001";
- bus_write <= '1';
- wait for 10 ns;
- bus_write <= '0';
-
- wait for 101 ns;
- bus_addr <= "10001";
- bus_data <= x"00000001";
- bus_write <= '1';
- wait for 10 ns;
- bus_write <= '0';
- wait;
-end process;
-
-PWM : panda_dirc_wasa
- port map(
- CON => open,
- INP => (others => '0'),
- PWM => open,
- SPARE_LINE => open,
- LED_GREEN => open,
- LED_ORANGE => open,
- LED_RED => open,
- LED_YELLOW => open,
- SPI_CLK => spi_clk,
- SPI_CS => spi_cs(0),
- SPI_IN => spi_in,
- SPI_OUT => spi_out,
- TEMP_LINE => open,
- TEST_LINE => open
- );
-
-
-THE_SPI : spi_ltc2600
- port map(
- CLK_IN => clk,
- RESET_IN => reset,
- -- Slave bus
- BUS_READ_IN => '0',
- BUS_WRITE_IN => bus_write,
- BUS_BUSY_OUT => open,
- BUS_ACK_OUT => open,
- BUS_ADDR_IN => bus_addr,
- BUS_DATA_IN => bus_data,
- BUS_DATA_OUT => open,
- -- SPI connections
- SPI_CS_OUT => spi_cs,
- SPI_SDI_IN => spi_out,
- SPI_SDO_OUT => spi_in,
- SPI_SCK_OUT => spi_clk
- );
-
-
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-
-
-entity tb is
-end entity;
-
-
-
-architecture arch of tb is
-
-signal clk : std_logic := '1';
-
-signal data : std_logic_vector(15 downto 0) := (others => '0');
-signal write : std_logic := '0';
-signal addr : std_logic_vector(3 downto 0) := (others => '0');
-
-
-
-component pwm_generator is
- port(
- CLK : in std_logic;
-
- DATA_IN : in std_logic_vector(15 downto 0);
- DATA_OUT : out std_logic_vector(15 downto 0);
- WRITE_IN : in std_logic;
- ADDR_IN : in std_logic_vector(3 downto 0);
-
- PWM : out std_logic_vector(31 downto 0)
-
- );
-end component;
-
-begin
-
-clk<= not clk after 5 ns;
-
-
-
-
-process begin
- wait for 101 ns;
- data <= x"6234";
- write <= '1';
- addr <= x"0";
- wait for 10 ns;
- write <= '0';
- wait;
-end process;
-
-PWM : pwm_generator
- port map(
- CLK => clk,
- DATA_IN => data,
- DATA_OUT => open,
- WRITE_IN => write,
- ADDR_IN => addr,
- PWM => open
- );
-
-
-end architecture;
\ No newline at end of file
jspc29 / trb3.git / commitdiff