--- /dev/null
+\documentclass[11pt,a4paper,twoside]{scrartcl} %twoside
+
+%Einstellungen der Seitenr?nder
+\usepackage[left=3.5cm,right=3cm,top=2.5cm,bottom=2.5cm,includeheadfoot]{geometry}
+\usepackage[utf8]{inputenc}
+\usepackage{amsfonts}
+\usepackage[american]{babel}
+\usepackage[T1]{fontenc}
+\usepackage[pdftex]{graphicx}
+\usepackage{pslatex}
+\usepackage{array}
+\usepackage{rotating}
+\usepackage{multirow}
+\usepackage{tabularx}
+\usepackage{url}
+\linespread{1.15}
+\usepackage{booktabs}
+\usepackage{longtable}
+\usepackage{ltxtable}
+\usepackage{upgreek}
+\usepackage{listings}
+\usepackage{scrtime}
+\usepackage{lscape}
+\usepackage{enumerate}
+\usepackage{textcomp}
+\usepackage{wrapfig}
+\usepackage[caption=false]{subfig}
+\usepackage{amsmath}
+\usepackage{setspace}
+\usepackage[update,prepend]{epstopdf}
+\usepackage[table]{xcolor}
+\definecolor{light-gray}{gray}{0.90}
+
+
+
+\definecolor{darkblue}{rgb}{.1,.1,.6}
+\definecolor{darkgray}{rgb}{.5,.5,.5}
+\usepackage[linkbordercolor={0 0 0},
+ pdfborder={0 0 0},
+ bookmarks,
+ citecolor=blue,
+ linkcolor=darkblue,
+ colorlinks=true,
+ urlcolor=darkblue]{hyperref}
+\usepackage{cite}
+
+\newcolumntype{W}[1]{>{\centering\let\newline\\\arraybackslash\hspace{0pt}}m{#1}}
+\newcolumntype{L}{>{\arraybackslash}X}
+\newcolumntype{C}{>{\centering\arraybackslash}X}
+
+%%\usepackage{fancyhdr}
+%%\pagestyle{headings}%{fancy}
+%%\fancyhf{}
+%%\fancyhead[R]{\nouppercase{\leftmark}}
+%%\renewcommand{\headrulewidth}{0.5pt}
+%%\fancyfoot[C]{\thepage}
+%\renewcommand{\footrulewidth}{0}
+%\usepackage[sort,square]{natbib}
+%\usepackage{mathptmx}
+%\usepackage{pslatex}
+\usepackage{scrpage2}
+\usepackage[toc,title]{appendix}
+
+\newenvironment{itemize*}%
+ {\begin{itemize}%
+ \setlength{\itemsep}{0pt}%
+ \setlength{\parskip}{0pt}%
+ \setlength{\topsep}{1pt}%
+ \setlength{\partopsep}{1pt}}%
+ {\end{itemize}}
+
+\newenvironment{description*}%
+ {\begin{description}%
+ \setlength{\itemsep}{0pt}%
+ \setlength{\parskip}{0pt}%
+ \setlength{\topsep}{1pt}%
+ \setlength{\partopsep}{1pt}}%
+ {\end{description}}
+
+\title{Documentation UFM\_control.vhd}
+\date{\today ~-~\thistime}
+\author{Abdul-Karim Bennett}
+
+
+\newcommand{\files}[1]{\texttt{#1}}
+\newcommand{\signal}[1]{\textsc{#1}}
+\newcommand{\genericname}[1]{\textsc{#1}}
+\newcommand{\constname}[1]{\textsc{#1}}
+\newcommand{\netname}[1]{\textsc{#1}}
+\newcommand{\cmdname}[1]{\texttt{#1}}
+\newcommand{\addr}[1]{\texttt{#1}}
+\bibliographystyle{alpha}
+
+\usepackage{remreset}
+\makeatletter\@removefromreset{footnote}{chapter}\makeatother
+
+\lstset { language = bash, numbers = none, breaklines=true, stringstyle=\color{black}\ttfamily }
+
+
+
+\usepackage{listings}
+\lstdefinelanguage{VHDL}{
+ morekeywords={
+ library,use,all,entity,is,port,in,out,end,architecture,of,
+ begin,and
+ },
+ morecomment=[l]--
+}
+
+%\usepackage{xcolor}
+\colorlet{keyword}{blue!100!black!80}
+\colorlet{comment}{green!90!black!90}
+\lstdefinestyle{vhdl}{
+ language = VHDL,
+ basicstyle = \ttfamily,
+ keywordstyle = \color{keyword}\bfseries,
+ commentstyle = \color{comment}
+}
+
+\begin{document}
+\lstset{language=VHDL}
+
+\newcounter{line}
+\newcounter{ct}
+
+\maketitle
+
+\vspace*{\fill}
+\vspace*{\fill}
+\clearpage
+\tableofcontents
+\cleardoublepage
+
+
+
+\section{Overview}
+With the entity UFM\_control.vhd data can be saved/fetched bytewise to/from the Userflashmemory (UFM). The implementation is intended for Lattice MachXO3 FPGAs but should also run on MachXO2 FPGAs.
+\newline
+The entity is built in order that data can be handled bytewise, but internally the data will always be written or read pagewise. One UFM-page consists of 16 bytes. Prior to writing to the UFM all data contained in it will be erased. Therefore data that is to be kept has to be stored elsewhere prior to writing. A read/write event always reads/writes all specified data.
+\newline
+\newline
+\textbf{The dependencies of UFM\_control. vhd are as follows:}
+
+UFM\_control. vhd $\rightarrow$ flashram.vhd
+
+UFM\_control. vhd $\rightarrow$ UFM\_WB.v $\rightarrow$ flash.vhd
+
+
+
+
+
+
+\section{Port Description and Parameters}
+Table \ref{tabportdescription} shows the portdescription. The number of of datapages that are to be read (NO\_DATAPAGES; one page = 16 byte) has to be specifies as well as the startpage (UFM\_STARTPAGE) which specifies where the written data will be located/start inside the UFM.
+\newline
+Depending on the clockfrequency that is used for CLK the parameter READ\_DELAY in the module UFM\_WB.v has to be adjusted. When using another device one can make corresponding adjustments in the file flash.vhd. For further information see inside according files.
+\newline
+\begin{table}[h]
+\begin{tabular}{ l| l| l| l }
+ \textbf{Port} & \textbf{Type} & \textbf{Width(Bits)} & \textbf{Descrition}\\
+ \hline
+ NO\_DATAPAGES & generic & integer & no datapages to read/write\\
+ UFM\_STARTPAGE & generic & 10 &startpage of data in UFM\\ \hline
+ CLK & in & 1 & clock input\\
+ CMD & in & 1 & '0' - Read; '1' - Write\\
+ GO & in & 1 & starts read/write process\\
+ BUSY & out & 1 & operation in progress\\
+ RESET & in & 1 & active high reset\\ \hline
+ DATA\_IN & in & 8 & datainput\\
+ DATA\_OUT & out & 8 &dataoutput\\
+ DATABYTE\_COUNTER & out & 15 & no of databyte to read/write\\
+ BUS\_READY\_IN & in &1 & interface signal\\
+ BUS\_READY\_OUT & out &1 & interface signal\\ \hline
+ FLASH\_ERROR & out & 1 &error of flashmodule\\
+\end{tabular}
+ \caption{Portdescription}
+ \label{tabportdescription}
+\end{table}
+
+\section{Interface}
+The data will be clocked out bytewise until all bytes/pages specified with NO\_DATAPAGES are processed. CMD determines wether to read or write to the UFM. GO triggers a read or write procedure. DATA\_IN accepts new data while writing and DATA\_OUT outputs the data while reading. DATABYTE\_COUNTER tells which byte currently has to be written or read. It starts with zero and always goes up to 16 * NO\_DATAPAGES.
+\newline
+FLASH\_ERROR is connected to the flash-interface inside UFM\_control. If an error occurs (only) the internal statemachine will be reset automatically. With RESET the statemachine and also the other components of UFM\_control will be reset.
+
+
+\subsection{Writing to UFM}
+A write process is initiated by setting CMD to '1' and asserting GO. Consequently BUSY will be set high until the process is complete. When BUS\_READY\_OUT is asserted UFM\_control is ready to accept the new byte at the port DATA\_IN. DATABYTE\_COUNTER specifies which byte to use. When the databyte is ready BUS\_READY\_IN has to be asserted and kept high until BUS\_READY\_OUT is low again (at which point the data is taken over). When BUS\_READY\_IN gets low again the internal statmachine of UFM\_control prepares the next byte. This goes on until all bytes are processed. Figure \ref{fig_datatoregister} shows the related timing diagram.
+
+\begin{figure}[h]
+ \centering
+ \includegraphics[width=1\textwidth]{UFM_DATA_TO_UFM.png}
+ \caption{Timing diagramm: Copy data from register to UFM}
+ \label{fig_datatoregister}
+\end{figure}
+
+
+\subsection{Reading from UFM}
+A read process is initiated by setting CMD to '0' and asserting GO. Consequently BUSY will be set high until the process is complete.
+When BUS\_READY\_OUT is asserted UFM\_control signals that a new byte specified by DATABYTE\_COUNTER is ready to be read out from UFM\_DATA\_OUT. Asserting BUS\_READY\_IN signals that the data has been taken over. When the data is copied BUS\_READY\_IN is to be set low again. Only then the statemachine of UFM\_control will prepare the next byte.
+Figure \ref{fig_datatoUFM} shows the related timing diagram.
+
+\begin{figure}[h]
+ \centering
+ \includegraphics[width=1\textwidth]{UFM_DATA_OUT.png}
+ \caption{Timing diagramm: Copy data from UFM to register}
+ \label{fig_datatoUFM}
+\end{figure}
+%\clearpage
+
+
+
+
+\section{Code Example}
+In the following a code example is provided for the usage of UFM\_control.vhd.
+
+\begin{lstlisting}[style=vhdl]
+
+ --SIGNALS
+-------------------------------------
+ signal ufm_cmd : std_logic := '0'; --CMD=0 => Read; CMD=1 => Write
+ signal ufm_go : std_logic := '1'; --load default values to registers from UFM at startup
+ signal ufm_data_in : std_logic_vector(7 downto 0); --directly connected to flashram DataInA
+ signal ufm_data_out : std_logic_vector(7 downto 0); --directly connected to flashram QB
+ signal ufm_databyte_counter : unsigned(14 downto 0);
+ signal ufm_bus_ready_out : std_logic;
+ signal ufm_bus_ready_in : std_logic;
+ signal ufm_busy : std_logic;
+
+-- UFM (FLASH) CONTROLLER
+-------------------------------------
+THE_UFM : entity UFM_control
+ generic map(
+ NO_DATAPAGES => 1,
+ UFM_STARTPAGE => "00"&x"00"
+ )
+ port map(
+ CLK => clk_33,
+ CMD => ufm_cmd, --CMD=0 => Read; CMD=1 => Write
+ GO => ufm_go,
+ BUSY => ufm_busy,
+ RESET => '0',
+
+ DATA_IN => ufm_data_in,
+ DATA_OUT => ufm_data_out,
+ DATABYTE_COUNTER => ufm_databyte_counter,
+ BUS_READY_IN => ufm_bus_ready_in,
+ BUS_READY_OUT => ufm_bus_ready_out,
+ FLASH_ERROR => open--ufmflasherror
+ );
+
+-- REGISTERS <=> UFM DATATRANSFER
+-------------------------------------------------
+PROC_REGS : process begin
+ wait until rising_edge(clk_33);
+
+ ufm_bus_ready_in <= '0';
+
+ if ufm_cmd = '0' and ufm_bus_ready_out = '1' then
+ --copy data from UFM to registers
+ ufm_bus_ready_in <= '1';
+ case to_integer(ufm_databyte_counter) is
+ when 0 => reg(7 downto 0) <= ufm_data_out;
+ when 1 => reg(15 downto 8) <= ufm_data_out;
+ when 2 => reg(23 downto 16) <= ufm_data_out;
+ when 3 => reg(31 downto 24) <= ufm_data_out;
+ when others =>null;
+ end case;
+
+ elsif ufm_cmd = '1' and ufm_bus_ready_out = '1' then
+ --save data from registers to UFM
+ ufm_bus_ready_in <= '1';
+ case to_integer(ufm_databyte_counter) is
+ when 0 => ufm_data_in <= reg(7 downto 0);
+ when 1 => ufm_data_in <= reg(15 downto 8);
+ when 2 => ufm_data_in <= reg(23 downto 16);
+ when 3 => ufm_data_in <= reg(31 downto 24);
+ when others =>null;
+ end case;
+
+ end if;
+end process;
+\end{lstlisting}
+
+
+
+
+
+
+% \cleardoublepage
+% \begin{appendices}
+% \end{appendices}
+% \cleardoublepage
+% \bibliography{biblio}
+\end{document}
+
+%%% Local Variables:
+%%% mode: latex
+%%% TeX-master: t
+%%% End:
--- /dev/null
+--##############################################################################
+-- With the entity UFM_control.vhd data can be saved/fetched bytewise to/from the
+-- Userflashmemory (UFM). The implementation is intended for Lattice MachXO3 FPGAs
+-- but should also run on MachXO2 FPGAs.
+--##############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library machxo3lf;
+use machxo3lf.all;
+
+library work;
+use work.all;--.trb_net_std.all;
+
+entity UFM_control is
+ generic(
+ NO_DATAPAGES : integer := 1;
+ UFM_STARTPAGE : std_logic_vector := "00"&x"00"
+ );
+ port(
+ CLK : in std_logic;
+
+ CMD : in std_logic; --CMD=0 => Read; CMD=1 => Write
+ GO : in std_logic; --initiate read/write process
+ BUSY : out std_logic; --operation in progress
+ RESET : in std_logic; --reset active high
+
+ DATA_IN : in std_logic_vector(7 downto 0);
+ DATA_OUT : out std_logic_vector(7 downto 0); --directly connected to QB of THE_FLASH_RAM
+ DATABYTE_COUNTER : out unsigned(14 downto 0); --specifies current databyte
+ BUS_READY_IN : in std_logic;
+ BUS_READY_OUT : out std_logic;
+
+ FLASH_ERROR : out std_logic --error signal from flash module, also resets statemachine
+ );
+end entity;
+
+
+architecture arch of UFM_control is
+
+ --FOR THE STATEMACHINE IN PROC_UFM_CONTROL
+ -----------------------------------
+ type UFM_control_state_t is (IDLE, DELAY, ERASEUFM, ENABLEUFMACCESS, READ1PAGE, READNEXTPAGE, WRITE1PAGE, WRITENEXTPAGE, SETRAMADDRESS, COPYDATAOUT, COPYDATAOUT2, COPYDATATORAM, COPYDATATORAM2, DisableUFMaccess);
+ signal control_state, control_nextstate : UFM_control_state_t;
+ signal cmd_buffer : std_logic;
+ constant no_databytes : unsigned(14 downto 0) := to_unsigned(NO_DATAPAGES * 16, 15); --calculate number of databytes in NO_DATAPAGES pages of UFM
+
+ --FOR THE_FLASH_RAM
+ -----------------------------------
+ signal ram_write_i : std_logic;
+ signal ram_addr_i : std_logic_vector(3 downto 0);
+ signal ram_data_in_buffer : std_logic_vector(7 downto 0);
+
+ --FOR CONNECTING THE_FLASH AND THE_FLASH_RAM
+ -----------------------------------
+ signal flashram_addr_i : std_logic_vector(3 downto 0);
+ signal flashram_cen_i : std_logic;
+ signal flashram_write_i: std_logic;
+ signal flashram_data_i : std_logic_vector(7 downto 0);
+ signal flashram_data_o : std_logic_vector(7 downto 0);
+
+ --FOR THE_FLASH
+ -----------------------------------
+ signal flash_command : std_logic_vector(2 downto 0):= (others => '0');
+ signal flash_go : std_logic:= '0';
+ signal flash_busy : std_logic;
+
+
+ component UFM_WB
+ port(
+ clk_i : in std_logic;
+ rst_n : in std_logic;
+ cmd : in std_logic_vector(2 downto 0);
+ ufm_page : in std_logic_vector(12 downto 0);
+ GO : in std_logic;
+ BUSY : out std_logic;
+ ERR : out std_logic;
+ mem_clk : out std_logic;
+ mem_we : out std_logic;
+ mem_ce : out std_logic;
+ mem_addr : out std_logic_vector(3 downto 0);
+ mem_wr_data : out std_logic_vector(7 downto 0);
+ mem_rd_data : in std_logic_vector(7 downto 0)
+ );
+ end component;
+
+
+begin
+--------------------------------------------------------------------------
+-- FLASH CONTROLLER WITH RAM
+---------------------------------------------------------------------------
+THE_FLASH_RAM : entity flashram
+ port map(
+ DataInA => ram_data_in_buffer,
+ AddressA => ram_addr_i,
+ ClockA => CLK,
+ ClockEnA => '1',
+ WrA => ram_write_i,
+ ResetA => RESET,
+ QA => DATA_OUT,
+
+ DataInB => flashram_data_i,
+ AddressB => flashram_addr_i,
+ ClockB => CLK,
+ ClockEnB => flashram_cen_i,
+ WrB => flashram_write_i,
+ ResetB => RESET,
+ QB => flashram_data_o
+ );
+
+THE_FLASH : UFM_WB
+ port map(
+ clk_i => CLK,
+ rst_n => not RESET, --active low
+ cmd => flash_command,
+ ufm_page => "111" & UFM_STARTPAGE,
+ GO => flash_go,
+ BUSY => flash_busy,
+ ERR => FLASH_ERROR,
+ mem_clk => open,
+ mem_we => flashram_write_i,
+ mem_ce => flashram_cen_i,
+ mem_addr => flashram_addr_i,
+ mem_wr_data => flashram_data_i,
+ mem_rd_data => flashram_data_o
+ );
+
+---------------------------------------------------------------------------
+-- STATEMACHINE FOR READING AND WRITING TO UFM
+---------------------------------------------------------------------------
+PROC_UFM_CONTROL : process
+
+begin
+ wait until rising_edge(CLK);
+ --base values for some signals in statemachine,
+ --meaning resetting them after respective state
+ flash_go <= '0';
+ ram_write_i <= '0';
+
+ case control_state is
+
+ when IDLE =>
+ DATABYTE_COUNTER<= (others => '0');
+ BUSY <= '0';
+ if GO = '1' then
+ BUSY <= '1';
+ cmd_buffer <= CMD; --buffer CMD
+ control_state <= ENABLEUFMACCESS;
+ end if;
+
+ when DELAY =>
+ control_state <= control_nextstate;
+
+ when ENABLEUFMACCESS =>
+ --prepare flash for access/further operations
+ if flash_busy = '0' then
+ flash_command<="100";--flash enable command
+ flash_go <= '1';
+
+ control_state <= DELAY;
+ if cmd_buffer = '0' then
+ control_nextstate <= READ1PAGE;
+ elsif cmd_buffer ='1' then
+ control_nextstate <= ERASEUFM;
+ end if;
+ end if;
+
+ when ERASEUFM =>
+ --erase complete UFM to prepare for new data
+ if flash_busy = '0' then
+ flash_command<="111";--erase UFM command
+ flash_go <= '1';
+ control_state <= DELAY;
+ control_nextstate <= SETRAMADDRESS;
+ end if;
+
+ when READ1PAGE =>
+ --read one flashpage specified by input UFM_STARTPAGE
+ if flash_busy = '0' then
+ flash_command<="000";--command read one page
+ flash_go <='1';
+ control_state <= DELAY;
+ control_nextstate <= SETRAMADDRESS;
+ end if;
+
+ when READNEXTPAGE =>
+ --read next UFM page
+ if flash_busy = '0' then
+ flash_command<="001";--command read one page
+ flash_go <='1';
+ control_state <= DELAY;
+ control_nextstate <= SETRAMADDRESS;
+ end if;
+
+ when SETRAMADDRESS =>
+ --set address of byte in ram to be accessed in next state
+ if flash_busy = '0' then
+ ram_addr_i <= std_logic_vector(DATABYTE_COUNTER(3 downto 0));
+ control_state <= DELAY;
+ if cmd_buffer = '0' then
+ control_nextstate <= COPYDATAOUT;
+ elsif cmd_buffer = '1' then
+ control_nextstate <= COPYDATATORAM;
+ end if;
+ end if;
+
+ when COPYDATAOUT =>
+ --data interface to UFM_control -
+ --copy out current byte, meaning making a proper handover since
+ --the ram output is directly connected to the output of UFM_control
+ BUS_READY_OUT <= '1';
+ if BUS_READY_IN = '1' then
+ BUS_READY_OUT <= '0';
+ control_state <= COPYDATAOUT2;
+ end if;
+
+ when COPYDATAOUT2 =>
+ if BUS_READY_IN = '0' then
+ DATABYTE_COUNTER <= DATABYTE_COUNTER + 1;
+
+ if DATABYTE_COUNTER = no_databytes - 1 then
+ --data read out complete, go for IDLE (->DisableUFMaccess->IDLE)
+ control_state<=DisableUFMaccess;
+ elsif DATABYTE_COUNTER(3 downto 0) = "1111" then
+ --one UFM page complete -> read next one
+ control_state <= READNEXTPAGE;
+ else
+ --read out next byte from ram (respectively current flash page in ram)
+ control_state<=SETRAMADDRESS;
+ end if;
+ end if;
+
+ when COPYDATATORAM =>
+ --data interface to UFM_control - copy the current byte at input DATA_IN to ram
+ BUS_READY_OUT <= '1'; --tell outside that ready for new data
+ if BUS_READY_IN = '1' then
+ --when new data available
+ ram_data_in_buffer <= DATA_IN; --take data inside (input to buffer/ram)
+ BUS_READY_OUT <= '0'; --tell data has been taken
+
+ control_state <= COPYDATATORAM2;
+ end if;
+
+ when COPYDATATORAM2 =>
+ if BUS_READY_IN = '0' then
+ --wait until outside understood that datatransfer complete
+ ram_write_i <= '1'; --tell THE_FLASH_RAM to take over byte
+ DATABYTE_COUNTER<= DATABYTE_COUNTER + 1;
+
+ control_state <= DELAY;
+ if DATABYTE_COUNTER = to_unsigned(15,DATABYTE_COUNTER'length) then
+ --ram for first flashpage full -> copy data to first flashpage (specified by UFM_STARTPAGE)
+ control_nextstate <= WRITE1PAGE;
+ elsif DATABYTE_COUNTER(3 downto 0) = "1111" then
+ --ram filled for next flashpage -> copy data to next flashpage
+ control_nextstate <= WRITENEXTPAGE;
+ else
+ --go on filling ram with data
+ control_nextstate <= SETRAMADDRESS;
+ end if;
+ end if;
+
+ when WRITE1PAGE =>
+ --write one flash page specified by input UFM_STARTPAGE
+ if flash_busy = '0' then
+ flash_command<="010"; --command write one page
+ flash_go <='1';
+
+ control_state <= DELAY;
+ if DATABYTE_COUNTER = no_databytes then
+ control_nextstate <= DisableUFMaccess;
+ else
+ control_nextstate <= SETRAMADDRESS;
+ end if;
+ end if;
+
+ when WRITENEXTPAGE =>
+ --write next flash page
+ if flash_busy = '0' then
+ flash_command<="011";--command write next page
+ flash_go <='1';
+
+ control_state <= DELAY;
+ if DATABYTE_COUNTER = no_databytes then
+ control_nextstate <= DisableUFMaccess;
+ else
+ control_nextstate <= SETRAMADDRESS;
+ end if;
+ end if;
+
+ when DisableUFMaccess =>
+ --disable flash access
+ if flash_busy = '0' then
+ flash_command<="101";
+ flash_go <='1';
+
+ control_state <= DELAY;
+ control_nextstate <= IDLE;
+ end if;
+ end case;
+
+ if RESET = '1' or FLASH_ERROR = '1' then
+ --if RESET is asserted or flash reports error stop running statemachine and go to IDLE
+ control_nextstate <= IDLE;
+ end if;
+
+end process;
+
+end architecture;
--- /dev/null
+--##############################################################################
+-- With the entity UFM_control.vhd data can be saved/fetched bytewise to/from the
+-- Userflashmemory (UFM). The implementation is intended for Lattice MachXO3 FPGAs
+-- but should also run on MachXO2 FPGAs.
+--##############################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library machxo3lf;
+use machxo3lf.all;
+
+library work;
+use work.all;--.trb_net_std.all;
+
+entity UFM_control is
+ generic(
+ NO_DATAPAGES : integer := 1;
+ UFM_STARTPAGE : std_logic_vector := "00"&x"00"
+ );
+ port(
+ CLK : in std_logic;
+
+ CMD : in std_logic; --CMD=0 => Read; CMD=1 => Write
+ GO : in std_logic; --initiate read/write process
+ BUSY : out std_logic; --operation in progress
+ RESET : in std_logic; --reset active high
+
+ DATA_IN : in std_logic_vector(7 downto 0);
+ DATA_OUT : out std_logic_vector(7 downto 0); --directly connected to QB of THE_FLASH_RAM
+ DATABYTE_COUNTER : out unsigned(14 downto 0); --specifies current databyte
+ BUS_READY_IN : in std_logic;
+ BUS_READY_OUT : out std_logic;
+
+ FLASH_ERROR : out std_logic --error signal from flash module, also resets statemachine
+ );
+end entity;
+
+
+architecture arch of UFM_control is
+
+ --FOR THE STATEMACHINE IN PROC_UFM_CONTROL
+ -----------------------------------
+ type UFM_control_state_t is (IDLE, DELAY, ERASEUFM, ENABLEUFMACCESS, READ1PAGE, READNEXTPAGE, WRITE1PAGE, WRITENEXTPAGE, SETRAMADDRESS, COPYDATAOUT, COPYDATAOUT2, COPYDATATORAM, COPYDATATORAM2, DisableUFMaccess);
+ signal control_state, control_nextstate : UFM_control_state_t;
+ signal cmd_buffer : std_logic;
+ constant no_databytes : unsigned(14 downto 0) := to_unsigned(NO_DATAPAGES * 16, 15); --calculate number of databytes in NO_DATAPAGES pages of UFM
+
+ --FOR THE_FLASH_RAM
+ -----------------------------------
+ signal ram_write_i : std_logic;
+ signal ram_addr_i : std_logic_vector(3 downto 0);
+ signal ram_data_in_buffer : std_logic_vector(7 downto 0);
+
+ --FOR CONNECTING THE_FLASH AND THE_FLASH_RAM
+ -----------------------------------
+ signal flashram_addr_i : std_logic_vector(3 downto 0);
+ signal flashram_cen_i : std_logic;
+ signal flashram_write_i: std_logic;
+ signal flashram_data_i : std_logic_vector(7 downto 0);
+ signal flashram_data_o : std_logic_vector(7 downto 0);
+
+ --FOR THE_FLASH
+ -----------------------------------
+ signal flash_command : std_logic_vector(2 downto 0):= (others => '0');
+ signal flash_go : std_logic:= '0';
+ signal flash_busy : std_logic;
+
+
+ component UFM_WB
+ port(
+ clk_i : in std_logic;
+ rst_n : in std_logic;
+ cmd : in std_logic_vector(2 downto 0);
+ ufm_page : in std_logic_vector(12 downto 0);
+ GO : in std_logic;
+ BUSY : out std_logic;
+ ERR : out std_logic;
+ mem_clk : out std_logic;
+ mem_we : out std_logic;
+ mem_ce : out std_logic;
+ mem_addr : out std_logic_vector(3 downto 0);
+ mem_wr_data : out std_logic_vector(7 downto 0);
+ mem_rd_data : in std_logic_vector(7 downto 0)
+ );
+ end component;
+
+
+begin
+--------------------------------------------------------------------------
+-- FLASH CONTROLLER WITH RAM
+---------------------------------------------------------------------------
+THE_FLASH_RAM : entity flashram
+ port map(
+ DataInA => ram_data_in_buffer,
+ AddressA => ram_addr_i,
+ ClockA => CLK,
+ ClockEnA => '1',
+ WrA => ram_write_i,
+ ResetA => RESET,
+ QA => DATA_OUT,
+
+ DataInB => flashram_data_i,
+ AddressB => flashram_addr_i,
+ ClockB => CLK,
+ ClockEnB => flashram_cen_i,
+ WrB => flashram_write_i,
+ ResetB => RESET,
+ QB => flashram_data_o
+ );
+
+THE_FLASH : UFM_WB
+ port map(
+ clk_i => CLK,
+ rst_n => not RESET, --active low
+ cmd => flash_command,
+ ufm_page => "111" & UFM_STARTPAGE,
+ GO => flash_go,
+ BUSY => flash_busy,
+ ERR => FLASH_ERROR,
+ mem_clk => open,
+ mem_we => flashram_write_i,
+ mem_ce => flashram_cen_i,
+ mem_addr => flashram_addr_i,
+ mem_wr_data => flashram_data_i,
+ mem_rd_data => flashram_data_o
+ );
+
+---------------------------------------------------------------------------
+-- STATEMACHINE FOR READING AND WRITING TO UFM
+---------------------------------------------------------------------------
+PROC_UFM_CONTROL : process
+
+begin
+ wait until rising_edge(CLK);
+ --base values for some signals in statemachine,
+ --meaning resetting them after respective state
+ flash_go <= '0';
+ ram_write_i <= '0';
+
+ case control_state is
+
+ when IDLE =>
+ DATABYTE_COUNTER<= (others => '0');
+ BUSY <= '0';
+ if GO = '1' then
+ BUSY <= '1';
+ cmd_buffer <= CMD; --buffer CMD
+ control_state <= ENABLEUFMACCESS;
+ end if;
+
+ when DELAY =>
+ control_state <= control_nextstate;
+
+ when ENABLEUFMACCESS =>
+ --prepare flash for access/further operations
+ if flash_busy = '0' then
+ flash_command<="100";--flash enable command
+ flash_go <= '1';
+
+ control_state <= DELAY;
+ if cmd_buffer = '0' then
+ control_nextstate <= READ1PAGE;
+ elsif cmd_buffer ='1' then
+ control_nextstate <= ERASEUFM;
+ end if;
+ end if;
+
+ when ERASEUFM =>
+ --erase complete UFM to prepare for new data
+ if flash_busy = '0' then
+ flash_command<="111";--erase UFM command
+ flash_go <= '1';
+ control_state <= DELAY;
+ control_nextstate <= SETRAMADDRESS;
+ end if;
+
+ when READ1PAGE =>
+ --read one flashpage specified by input UFM_STARTPAGE
+ if flash_busy = '0' then
+ flash_command<="000";--command read one page
+ flash_go <='1';
+ control_state <= DELAY;
+ control_nextstate <= SETRAMADDRESS;
+ end if;
+
+ when READNEXTPAGE =>
+ --read next UFM page
+ if flash_busy = '0' then
+ flash_command<="001";--command read one page
+ flash_go <='1';
+ control_state <= DELAY;
+ control_nextstate <= SETRAMADDRESS;
+ end if;
+
+ when SETRAMADDRESS =>
+ --set address of byte in ram to be accessed in next state
+ if flash_busy = '0' then
+ ram_addr_i <= std_logic_vector(DATABYTE_COUNTER(3 downto 0));
+ control_state <= DELAY;
+ if cmd_buffer = '0' then
+ control_nextstate <= COPYDATAOUT;
+ elsif cmd_buffer = '1' then
+ control_nextstate <= COPYDATATORAM;
+ end if;
+ end if;
+
+ when COPYDATAOUT =>
+ --data interface to UFM_control -
+ --copy out current byte, meaning making a proper handover since
+ --the ram output is directly connected to the output of UFM_control
+ BUS_READY_OUT <= '1';
+ if BUS_READY_IN = '1' then
+ BUS_READY_OUT <= '0';
+ control_state <= COPYDATAOUT2;
+ end if;
+
+ when COPYDATAOUT2 =>
+ if BUS_READY_IN = '0' then
+ DATABYTE_COUNTER <= DATABYTE_COUNTER + 1;
+
+ if DATABYTE_COUNTER = no_databytes - 1 then
+ --data read out complete, go for IDLE (->DisableUFMaccess->IDLE)
+ control_state<=DisableUFMaccess;
+ elsif DATABYTE_COUNTER(3 downto 0) = "1111" then
+ --one UFM page complete -> read next one
+ control_state <= READNEXTPAGE;
+ else
+ --read out next byte from ram (respectively current flash page in ram)
+ control_state<=SETRAMADDRESS;
+ end if;
+ end if;
+
+ when COPYDATATORAM =>
+ --data interface to UFM_control - copy the current byte at input DATA_IN to ram
+ BUS_READY_OUT <= '1'; --tell outside that ready for new data
+ if BUS_READY_IN = '1' then
+ --when new data available
+ ram_data_in_buffer <= DATA_IN; --take data inside (input to buffer/ram)
+ BUS_READY_OUT <= '0'; --tell data has been taken
+
+ control_state <= COPYDATATORAM2;
+ end if;
+
+ when COPYDATATORAM2 =>
+ if BUS_READY_IN = '0' then
+ --wait until outside understood that datatransfer complete
+ ram_write_i <= '1'; --tell THE_FLASH_RAM to take over byte
+ DATABYTE_COUNTER<= DATABYTE_COUNTER + 1;
+
+ control_state <= DELAY;
+ if DATABYTE_COUNTER = to_unsigned(15,DATABYTE_COUNTER'length) then
+ --ram for first flashpage full -> copy data to first flashpage (specified by UFM_STARTPAGE)
+ control_nextstate <= WRITE1PAGE;
+ elsif DATABYTE_COUNTER(3 downto 0) = "1111" then
+ --ram filled for next flashpage -> copy data to next flashpage
+ control_nextstate <= WRITENEXTPAGE;
+ else
+ --go on filling ram with data
+ control_nextstate <= SETRAMADDRESS;
+ end if;
+ end if;
+
+ when WRITE1PAGE =>
+ --write one flash page specified by input UFM_STARTPAGE
+ if flash_busy = '0' then
+ flash_command<="010"; --command write one page
+ flash_go <='1';
+
+ control_state <= DELAY;
+ if DATABYTE_COUNTER = no_databytes then
+ control_nextstate <= DisableUFMaccess;
+ else
+ control_nextstate <= SETRAMADDRESS;
+ end if;
+ end if;
+
+ when WRITENEXTPAGE =>
+ --write next flash page
+ if flash_busy = '0' then
+ flash_command<="011";--command write next page
+ flash_go <='1';
+
+ control_state <= DELAY;
+ if DATABYTE_COUNTER = no_databytes then
+ control_nextstate <= DisableUFMaccess;
+ else
+ control_nextstate <= SETRAMADDRESS;
+ end if;
+ end if;
+
+ when DisableUFMaccess =>
+ --disable flash access
+ if flash_busy = '0' then
+ flash_command<="101";
+ flash_go <='1';
+
+ control_state <= DELAY;
+ control_nextstate <= IDLE;
+ end if;
+ end case;
+
+ if RESET = '1' or FLASH_ERROR = '1' then
+ --if RESET is asserted or flash reports error stop running statemachine and go to IDLE
+ control_nextstate <= IDLE;
+ end if;
+
+end process;
+
+end architecture;
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="flash" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2016 09 29 10:00:22.906" version="1.2" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="flash.lpc" type="lpc" modified="2016 09 29 10:00:20.000"/>
+ <File name="flash.vhd" type="top_level_vhdl" modified="2016 09 29 10:00:20.000"/>
+ <File name="flash_tmpl.vhd" type="template_vhdl" modified="2016 09 29 10:00:20.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=machxo3lf
+PartType=LCMXO3LF-2100E
+PartName=LCMXO3LF-2100E-5UWG49CTR
+SpeedGrade=5
+Package=WLCSP49
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=EFB
+CoreRevision=1.2
+ModuleName=flash
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=09/29/2016
+Time=10:00:20
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+freq=
+i2c1=0
+i2c1config=0
+i2c1_addr=7-Bit Addressing
+i2c1_ce=0
+i2c1_freq=100
+i2c1_sa=10000
+i2c1_we=0
+i2c2=0
+i2c2_addr=7-Bit Addressing
+i2c2_ce=0
+i2c2_freq=100
+i2c2_sa=10000
+i2c2_we=0
+ufm_addr=7-Bit Addressing
+ufm_sa=10000
+pll=0
+pll_cnt=1
+spi=0
+spi_clkinv=0
+spi_cs=1
+spi_en=0
+spi_freq=1
+spi_lsb=0
+spi_mode=Slave
+spi_ib=0
+spi_ph=0
+spi_hs=0
+spi_rxo=0
+spi_rxr=0
+spi_txo=0
+spi_txr=0
+spi_we=0
+static_tc=Static
+tc=0
+tc_clkinv=Positive
+tc_ctr=1
+tc_div=1
+tc_ipcap=0
+tc_mode=CTCM
+tc_ocr=32767
+tc_oflow=1
+tc_o=TOGGLE
+tc_opcomp=0
+tc_osc=0
+tc_sa_oflow=0
+tc_top=65535
+ufm=1
+wb_clk_freq=33.33
+ufm_usage=SHARED_EBR_TAG
+ufm_ebr=629
+ufm_remain=
+mem_size=10
+ufm_start=
+ufm_init=0
+memfile=
+ufm_dt=hex
+wb=1
+
+[Command]
+cmd_line= -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.33 -ufm -ufm_ebr 629 -mem_size 10 -ufm_0 -wb -dev 2100
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4
+-- Module Version: 1.2
+--/opt/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.33 -ufm -ufm_ebr 629 -mem_size 10 -ufm_0 -wb -dev 2100
+
+-- Thu Sep 29 10:00:20 2016
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library MACHXO3L;
+use MACHXO3L.components.all;
+-- synopsys translate_on
+
+entity flash is
+ port (
+ wb_clk_i: in std_logic;
+ wb_rst_i: in std_logic;
+ wb_cyc_i: in std_logic;
+ wb_stb_i: in std_logic;
+ wb_we_i: in std_logic;
+ wb_adr_i: in std_logic_vector(7 downto 0);
+ wb_dat_i: in std_logic_vector(7 downto 0);
+ wb_dat_o: out std_logic_vector(7 downto 0);
+ wb_ack_o: out std_logic;
+ wbc_ufm_irq: out std_logic);
+end flash;
+
+architecture Structure of flash is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component EFB
+ generic (EFB_I2C1 : in String; EFB_I2C2 : in String;
+ EFB_SPI : in String; EFB_TC : in String;
+ EFB_TC_PORTMODE : in String; EFB_UFM : in String;
+ EFB_WB_CLK_FREQ : in String; DEV_DENSITY : in String;
+ UFM_INIT_PAGES : in Integer;
+ UFM_INIT_START_PAGE : in Integer;
+ UFM_INIT_ALL_ZEROS : in String;
+ UFM_INIT_FILE_NAME : in String;
+ UFM_INIT_FILE_FORMAT : in String;
+ I2C1_ADDRESSING : in String; I2C2_ADDRESSING : in String;
+ I2C1_SLAVE_ADDR : in String; I2C2_SLAVE_ADDR : in String;
+ I2C1_BUS_PERF : in String; I2C2_BUS_PERF : in String;
+ I2C1_CLK_DIVIDER : in Integer;
+ I2C2_CLK_DIVIDER : in Integer; I2C1_GEN_CALL : in String;
+ I2C2_GEN_CALL : in String; I2C1_WAKEUP : in String;
+ I2C2_WAKEUP : in String; SPI_MODE : in String;
+ SPI_CLK_DIVIDER : in Integer; SPI_LSB_FIRST : in String;
+ SPI_CLK_INV : in String; SPI_PHASE_ADJ : in String;
+ SPI_SLAVE_HANDSHAKE : in String;
+ SPI_INTR_TXRDY : in String; SPI_INTR_RXRDY : in String;
+ SPI_INTR_TXOVR : in String; SPI_INTR_RXOVR : in String;
+ SPI_WAKEUP : in String; TC_MODE : in String;
+ TC_SCLK_SEL : in String; TC_CCLK_SEL : in Integer;
+ GSR : in String; TC_TOP_SET : in Integer;
+ TC_OCR_SET : in Integer; TC_OC_MODE : in String;
+ TC_RESETN : in String; TC_TOP_SEL : in String;
+ TC_OV_INT : in String; TC_OCR_INT : in String;
+ TC_ICR_INT : in String; TC_OVERFLOW : in String;
+ TC_ICAPTURE : in String);
+ port (WBCLKI: in std_logic; WBRSTI: in std_logic;
+ WBCYCI: in std_logic; WBSTBI: in std_logic;
+ WBWEI: in std_logic; WBADRI7: in std_logic;
+ WBADRI6: in std_logic; WBADRI5: in std_logic;
+ WBADRI4: in std_logic; WBADRI3: in std_logic;
+ WBADRI2: in std_logic; WBADRI1: in std_logic;
+ WBADRI0: in std_logic; WBDATI7: in std_logic;
+ WBDATI6: in std_logic; WBDATI5: in std_logic;
+ WBDATI4: in std_logic; WBDATI3: in std_logic;
+ WBDATI2: in std_logic; WBDATI1: in std_logic;
+ WBDATI0: in std_logic; PLL0DATI7: in std_logic;
+ PLL0DATI6: in std_logic; PLL0DATI5: in std_logic;
+ PLL0DATI4: in std_logic; PLL0DATI3: in std_logic;
+ PLL0DATI2: in std_logic; PLL0DATI1: in std_logic;
+ PLL0DATI0: in std_logic; PLL0ACKI: in std_logic;
+ PLL1DATI7: in std_logic; PLL1DATI6: in std_logic;
+ PLL1DATI5: in std_logic; PLL1DATI4: in std_logic;
+ PLL1DATI3: in std_logic; PLL1DATI2: in std_logic;
+ PLL1DATI1: in std_logic; PLL1DATI0: in std_logic;
+ PLL1ACKI: in std_logic; I2C1SCLI: in std_logic;
+ I2C1SDAI: in std_logic; I2C2SCLI: in std_logic;
+ I2C2SDAI: in std_logic; SPISCKI: in std_logic;
+ SPIMISOI: in std_logic; SPIMOSII: in std_logic;
+ SPISCSN: in std_logic; TCCLKI: in std_logic;
+ TCRSTN: in std_logic; TCIC: in std_logic;
+ UFMSN: in std_logic; WBDATO7: out std_logic;
+ WBDATO6: out std_logic; WBDATO5: out std_logic;
+ WBDATO4: out std_logic; WBDATO3: out std_logic;
+ WBDATO2: out std_logic; WBDATO1: out std_logic;
+ WBDATO0: out std_logic; WBACKO: out std_logic;
+ PLLCLKO: out std_logic; PLLRSTO: out std_logic;
+ PLL0STBO: out std_logic; PLL1STBO: out std_logic;
+ PLLWEO: out std_logic; PLLADRO4: out std_logic;
+ PLLADRO3: out std_logic; PLLADRO2: out std_logic;
+ PLLADRO1: out std_logic; PLLADRO0: out std_logic;
+ PLLDATO7: out std_logic; PLLDATO6: out std_logic;
+ PLLDATO5: out std_logic; PLLDATO4: out std_logic;
+ PLLDATO3: out std_logic; PLLDATO2: out std_logic;
+ PLLDATO1: out std_logic; PLLDATO0: out std_logic;
+ I2C1SCLO: out std_logic; I2C1SCLOEN: out std_logic;
+ I2C1SDAO: out std_logic; I2C1SDAOEN: out std_logic;
+ I2C2SCLO: out std_logic; I2C2SCLOEN: out std_logic;
+ I2C2SDAO: out std_logic; I2C2SDAOEN: out std_logic;
+ I2C1IRQO: out std_logic; I2C2IRQO: out std_logic;
+ SPISCKO: out std_logic; SPISCKEN: out std_logic;
+ SPIMISOO: out std_logic; SPIMISOEN: out std_logic;
+ SPIMOSIO: out std_logic; SPIMOSIEN: out std_logic;
+ SPIMCSN7: out std_logic; SPIMCSN6: out std_logic;
+ SPIMCSN5: out std_logic; SPIMCSN4: out std_logic;
+ SPIMCSN3: out std_logic; SPIMCSN2: out std_logic;
+ SPIMCSN1: out std_logic; SPIMCSN0: out std_logic;
+ SPICSNEN: out std_logic; SPIIRQO: out std_logic;
+ TCINT: out std_logic; TCOC: out std_logic;
+ WBCUFMIRQ: out std_logic; CFGWAKE: out std_logic;
+ CFGSTDBY: out std_logic);
+ end component;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ EFBInst_0: EFB
+ generic map (UFM_INIT_FILE_FORMAT=> "HEX", UFM_INIT_FILE_NAME=> "NONE",
+ UFM_INIT_ALL_ZEROS=> "ENABLED", UFM_INIT_START_PAGE=> 0,
+ UFM_INIT_PAGES=> 0, DEV_DENSITY=> "2100L", EFB_UFM=> "ENABLED",
+ TC_ICAPTURE=> "DISABLED", TC_OVERFLOW=> "DISABLED", TC_ICR_INT=> "OFF",
+ TC_OCR_INT=> "OFF", TC_OV_INT=> "OFF", TC_TOP_SEL=> "OFF",
+ TC_RESETN=> "ENABLED", TC_OC_MODE=> "TOGGLE", TC_OCR_SET=> 32767,
+ TC_TOP_SET=> 65535, GSR=> "ENABLED", TC_CCLK_SEL=> 1, TC_MODE=> "CTCM",
+ TC_SCLK_SEL=> "PCLOCK", EFB_TC_PORTMODE=> "WB", EFB_TC=> "DISABLED",
+ SPI_WAKEUP=> "DISABLED", SPI_INTR_RXOVR=> "DISABLED",
+ SPI_INTR_TXOVR=> "DISABLED", SPI_INTR_RXRDY=> "DISABLED",
+ SPI_INTR_TXRDY=> "DISABLED", SPI_SLAVE_HANDSHAKE=> "DISABLED",
+ SPI_PHASE_ADJ=> "DISABLED", SPI_CLK_INV=> "DISABLED",
+ SPI_LSB_FIRST=> "DISABLED", SPI_CLK_DIVIDER=> 1, SPI_MODE=> "MASTER",
+ EFB_SPI=> "DISABLED", I2C2_WAKEUP=> "DISABLED", I2C2_GEN_CALL=> "DISABLED",
+ I2C2_CLK_DIVIDER=> 1, I2C2_BUS_PERF=> "100kHz", I2C2_SLAVE_ADDR=> "0b1000010",
+ I2C2_ADDRESSING=> "7BIT", EFB_I2C2=> "DISABLED", I2C1_WAKEUP=> "DISABLED",
+ I2C1_GEN_CALL=> "DISABLED", I2C1_CLK_DIVIDER=> 1, I2C1_BUS_PERF=> "100kHz",
+ I2C1_SLAVE_ADDR=> "0b1000001", I2C1_ADDRESSING=> "7BIT",
+ EFB_I2C1=> "DISABLED", EFB_WB_CLK_FREQ=> "33.3")
+ port map (WBCLKI=>wb_clk_i, WBRSTI=>wb_rst_i, WBCYCI=>wb_cyc_i,
+ WBSTBI=>wb_stb_i, WBWEI=>wb_we_i, WBADRI7=>wb_adr_i(7),
+ WBADRI6=>wb_adr_i(6), WBADRI5=>wb_adr_i(5),
+ WBADRI4=>wb_adr_i(4), WBADRI3=>wb_adr_i(3),
+ WBADRI2=>wb_adr_i(2), WBADRI1=>wb_adr_i(1),
+ WBADRI0=>wb_adr_i(0), WBDATI7=>wb_dat_i(7),
+ WBDATI6=>wb_dat_i(6), WBDATI5=>wb_dat_i(5),
+ WBDATI4=>wb_dat_i(4), WBDATI3=>wb_dat_i(3),
+ WBDATI2=>wb_dat_i(2), WBDATI1=>wb_dat_i(1),
+ WBDATI0=>wb_dat_i(0), PLL0DATI7=>scuba_vlo,
+ PLL0DATI6=>scuba_vlo, PLL0DATI5=>scuba_vlo,
+ PLL0DATI4=>scuba_vlo, PLL0DATI3=>scuba_vlo,
+ PLL0DATI2=>scuba_vlo, PLL0DATI1=>scuba_vlo,
+ PLL0DATI0=>scuba_vlo, PLL0ACKI=>scuba_vlo,
+ PLL1DATI7=>scuba_vlo, PLL1DATI6=>scuba_vlo,
+ PLL1DATI5=>scuba_vlo, PLL1DATI4=>scuba_vlo,
+ PLL1DATI3=>scuba_vlo, PLL1DATI2=>scuba_vlo,
+ PLL1DATI1=>scuba_vlo, PLL1DATI0=>scuba_vlo,
+ PLL1ACKI=>scuba_vlo, I2C1SCLI=>scuba_vlo,
+ I2C1SDAI=>scuba_vlo, I2C2SCLI=>scuba_vlo,
+ I2C2SDAI=>scuba_vlo, SPISCKI=>scuba_vlo, SPIMISOI=>scuba_vlo,
+ SPIMOSII=>scuba_vlo, SPISCSN=>scuba_vlo, TCCLKI=>scuba_vlo,
+ TCRSTN=>scuba_vlo, TCIC=>scuba_vlo, UFMSN=>scuba_vhi,
+ WBDATO7=>wb_dat_o(7), WBDATO6=>wb_dat_o(6),
+ WBDATO5=>wb_dat_o(5), WBDATO4=>wb_dat_o(4),
+ WBDATO3=>wb_dat_o(3), WBDATO2=>wb_dat_o(2),
+ WBDATO1=>wb_dat_o(1), WBDATO0=>wb_dat_o(0), WBACKO=>wb_ack_o,
+ PLLCLKO=>open, PLLRSTO=>open, PLL0STBO=>open, PLL1STBO=>open,
+ PLLWEO=>open, PLLADRO4=>open, PLLADRO3=>open, PLLADRO2=>open,
+ PLLADRO1=>open, PLLADRO0=>open, PLLDATO7=>open,
+ PLLDATO6=>open, PLLDATO5=>open, PLLDATO4=>open,
+ PLLDATO3=>open, PLLDATO2=>open, PLLDATO1=>open,
+ PLLDATO0=>open, I2C1SCLO=>open, I2C1SCLOEN=>open,
+ I2C1SDAO=>open, I2C1SDAOEN=>open, I2C2SCLO=>open,
+ I2C2SCLOEN=>open, I2C2SDAO=>open, I2C2SDAOEN=>open,
+ I2C1IRQO=>open, I2C2IRQO=>open, SPISCKO=>open,
+ SPISCKEN=>open, SPIMISOO=>open, SPIMISOEN=>open,
+ SPIMOSIO=>open, SPIMOSIEN=>open, SPIMCSN7=>open,
+ SPIMCSN6=>open, SPIMCSN5=>open, SPIMCSN4=>open,
+ SPIMCSN3=>open, SPIMCSN2=>open, SPIMCSN1=>open,
+ SPIMCSN0=>open, SPICSNEN=>open, SPIIRQO=>open, TCINT=>open,
+ TCOC=>open, WBCUFMIRQ=>wbc_ufm_irq, CFGWAKE=>open,
+ CFGSTDBY=>open);
+
+end Structure;
<BaliProject version="3.2" title="L" device="LCMXO3LF-2100E-5UWG49CTR" default_implementation="L">
<Options/>
<Implementation title="L" dir="L" description="L" synthesis="synplify" default_strategy="Strategy1">
- <Options def_top="uart_sctrl" top="logicbox"/>
+ <Options def_top="flashram" top="logicbox"/>
<Source name="../logicbox.vhd" type="VHDL" type_short="VHDL">
<Options top_module="logicbox"/>
</Source>
<Source name="../../../trbnet/special/uart_trans.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../../padiwa/amps/version.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../../code/uart_sctrl.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="../../cores/flashram.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../cores/pll_in133_out33_133_266.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../code/UFM_control.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../cores/UFM_WB.v" type="Verilog" type_short="Verilog">
+ <Options/>
+ </Source>
+ <Source name="../../cores/flash.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="L/L.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
use machxo3lf.all;\r
\r
library work;\r
-use work.trb_net_std.all;\r
+use work.all;--trb_net_std.all;\r
\r
entity logicbox is\r
port(\r
end entity;\r
\r
architecture arch of logicbox is\r
- signal clk_i, clk_osc, clk_33 : std_logic;\r
+ signal clk_i, clk_osc, clk_33,clk_266 : std_logic;\r
signal led_i : std_logic_vector(3 downto 0);\r
signal timer_i : unsigned(31 downto 0) := (others => '0');\r
signal config : std_logic_vector(3 downto 0);\r
signal led_timer : led_timer_t;\r
signal led_state : std_logic_vector(3 downto 0);\r
\r
+ --UART\r
+ -------------------------------------\r
signal uart_rx_data : std_logic_vector(31 downto 0);\r
signal uart_tx_data : std_logic_vector(31 downto 0);\r
signal uart_addr : std_logic_vector(7 downto 0);\r
signal input_reg_0, input_reg_1, input_reg_2 : std_logic_vector(3 downto 0);\r
\r
signal edge_rising, edge_falling : std_logic_vector(3 downto 0);\r
- signal pulser : std_logic;\r
signal reg : std_logic_vector(31 downto 0);\r
signal last_config : std_logic_vector(3 downto 0);\r
- \r
+ \r
signal sed_error : std_logic;\r
signal sed_debug : std_logic_vector(31 downto 0);\r
signal controlsed_i : std_logic_vector(3 downto 0);\r
\r
+ --PULSER\r
+ ------------------------------------- \r
+ signal pulser : std_logic;\r
+ signal pulser_counter : unsigned(27 downto 0) := (others => '0');\r
+ signal pulser_periodlength : unsigned(27 downto 0) := x"0000002";\r
+ signal pulser_pulslength : unsigned(27 downto 0) := x"0000001";\r
+ signal pulser_periodlength_buffer : unsigned(27 downto 0);\r
+ signal pulser_pulslength_buffer : unsigned(27 downto 0);\r
\r
- signal ram_write_i : std_logic;\r
- signal ram_data_i: std_logic_vector(7 downto 0);\r
- signal ram_data_o: std_logic_vector(7 downto 0);\r
- signal ram_addr_i: std_logic_vector(3 downto 0);\r
-\r
- signal flashram_addr_i : std_logic_vector(3 downto 0);\r
- signal flashram_cen_i : std_logic;\r
- signal flashram_reset : std_logic;\r
- signal flashram_write_i: std_logic;\r
- signal flashram_data_i : std_logic_vector(7 downto 0);\r
- signal flashram_data_o : std_logic_vector(7 downto 0);\r
-\r
- signal flash_command : std_logic_vector(2 downto 0);\r
- signal flash_page : std_logic_vector(12 downto 0);\r
- signal flash_go : std_logic;\r
- signal flash_busy : std_logic;\r
- signal flash_err : std_logic;\r
- \r
+ --UFM\r
+ -------------------------------------\r
+ signal ufm_cmd : std_logic := '0'; --CMD=0 => Read; CMD=1 => Write\r
+ signal ufm_go : std_logic := '1'; --load default values to registers from UFM at startup \r
+ signal ufm_data_in : std_logic_vector(7 downto 0); --directly connected to flashram DataInA\r
+ signal ufm_data_out : std_logic_vector(7 downto 0); --directly connected to flashram QB\r
+ signal ufm_databyte_counter : unsigned(14 downto 0);\r
+ signal ufm_bus_ready_out : std_logic;\r
+ signal ufm_bus_ready_in : std_logic;\r
+ signal ufm_busy : std_logic;\r
\r
component OSCH\r
generic (NOM_FREQ: string := "133.00");\r
);\r
end component; \r
\r
- component UFM_WB\r
- port(\r
- clk_i : in std_logic;\r
- rst_n : in std_logic;\r
- cmd : in std_logic_vector(2 downto 0);\r
- ufm_page : in std_logic_vector(12 downto 0);\r
- GO : in std_logic;\r
- BUSY : out std_logic;\r
- ERR : out std_logic;\r
- mem_clk : out std_logic;\r
- mem_we : out std_logic;\r
- mem_ce : out std_logic;\r
- mem_addr : out std_logic_vector(3 downto 0);\r
- mem_wr_data : out std_logic_vector(7 downto 0);\r
- mem_rd_data : in std_logic_vector(7 downto 0)\r
- );\r
- end component;\r
- \r
+ \r
begin\r
\r
-\r
-\r
-\r
---------------------------------------------------------------------------\r
-- I/O Logic\r
---------------------------------------------------------------------------\r
---------------------------------------------------------------------------\r
PROC_PULSER : process begin\r
wait until rising_edge(clk_i);\r
- if timer_i(13 downto 0) = "00"&x"000" then\r
+ pulser_counter <= pulser_counter + 1;\r
+ \r
+ if pulser_counter = x"0000000" then\r
pulser <= '1';\r
- elsif timer_i(13 downto 0) = "00"&x"008" then\r
+ pulser_pulslength_buffer <= pulser_pulslength;\r
+ pulser_periodlength_buffer <= pulser_periodlength;\r
+ end if;\r
+ \r
+ if pulser_counter = pulser_pulslength_buffer then\r
pulser <= '0';\r
- end if; \r
+ end if;\r
+ \r
+ if pulser_counter = pulser_periodlength_buffer then\r
+ pulser_counter <= (others => '0');\r
+ end if;\r
end process; \r
\r
---------------------------------------------------------------------------\r
end loop;\r
end process; \r
\r
- \r
---------------------------------------------------------------------------\r
-- Clock\r
---------------------------------------------------------------------------\r
CLKI => clk_osc,\r
CLKOP => clk_i, --133\r
CLKOS => clk_33, --33 \r
- CLKOS2=> open --266\r
+ CLKOS2=> clk_266 --266\r
);\r
\r
-\r
timer_i <= timer_i + 1 when rising_edge(clk_i);\r
\r
-\r
---------------------------------------------------------------------------\r
-- Read configuration switch\r
---------------------------------------------------------------------------\r
process begin\r
wait until rising_edge(clk_i);\r
- \r
-\r
if timer_i(27 downto 10) = 0 then\r
led_highz <= '1';\r
last_config <= config;\r
---------------------------------------------------------------------------\r
THE_UART : entity work.uart_sctrl\r
generic map(\r
- CLOCK_SPEED => 133000000\r
+ CLOCK_SPEED => 33250000\r
)\r
port map(\r
- CLK => clk_i,\r
+ CLK => clk_33,\r
RESET => '0',\r
UART_RX => TX_IN,\r
UART_TX => RX_OUT,\r
DEBUG => open\r
);\r
\r
+---------------------------------------------------------------------------\r
+-- UFM (FLASH) CONTROLLER\r
+--------------------------------------------------------------------------- \r
+THE_UFM : entity UFM_control\r
+ generic map(\r
+ NO_DATAPAGES => 1,\r
+ UFM_STARTPAGE => "00"&x"00"\r
+ )\r
+ port map(\r
+ CLK => clk_33,\r
\r
+ CMD => ufm_cmd, --CMD=0 => Read; CMD=1 => Write\r
+ GO => ufm_go,\r
+ BUSY => ufm_busy,\r
+ RESET => '0',\r
+ \r
+ DATA_IN => ufm_data_in, \r
+ DATA_OUT => ufm_data_out,\r
+ DATABYTE_COUNTER => ufm_databyte_counter,\r
+ BUS_READY_IN => ufm_bus_ready_in,\r
+ BUS_READY_OUT => ufm_bus_ready_out,\r
+\r
+ FLASH_ERROR => open--ufmflasherror\r
+ );\r
+ \r
+---------------------------------------------------------------------------\r
+-- READ/WRITE REGISTERS VIA UART/FLASH\r
+---------------------------------------------------------------------------\r
PROC_REGS : process begin\r
- wait until rising_edge(clk_i);\r
+ wait until rising_edge(clk_33);\r
+ \r
+ --register <=> UART datatransfer\r
+ -------------------------------------------------------------------\r
bus_ready <= '0';\r
+ ufm_go <= '0'; --for operating UFM_control\r
+ \r
if bus_read = '1' then\r
+ --send out data from registers over RS232\r
bus_ready <= '1';\r
case uart_addr is\r
when x"00" => uart_tx_data <= x"0000000" & config;\r
when x"10" => uart_tx_data <= reg;\r
when x"ee" => uart_tx_data <= sed_debug;\r
+ \r
+ when x"20" => uart_tx_data <= x"0" & std_logic_vector(pulser_periodlength);\r
+ when x"21" => uart_tx_data <= x"0" & std_logic_vector(pulser_pulslength);\r
+ \r
+ when others =>null;\r
end case;\r
+ \r
elsif bus_write = '1' then\r
+ --write registers with data from received from RS232\r
case uart_addr is\r
+ when x"02" => if uart_rx_data = x"00000000" and ufm_busy = '0' then \r
+ --initiate load from UFM\r
+ ufm_cmd <= '0';\r
+ ufm_go <= '1';\r
+ elsif uart_rx_data = x"FFFFFFFF" and ufm_busy = '0' then\r
+ --initiate write to UFM\r
+ ufm_cmd <= '1';\r
+ ufm_go <= '1';\r
+ end if; \r
+ \r
when x"10" => reg <= uart_rx_data;\r
- when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);\r
+\r
+ when x"20" => if uart_rx_data = x"00000000" or uart_rx_data = x"00000001" then\r
+ pulser_periodlength <= x"0000001";\r
+ else\r
+ pulser_periodlength <= unsigned(uart_rx_data(27 downto 0)) - 1;\r
+ end if;\r
+ \r
+ when x"21" => pulser_pulslength <= uart_rx_data(27 downto 0);\r
+ \r
+ when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);\r
+ \r
+ when others => null;\r
end case;\r
end if;\r
+ \r
+ --register <=> UFM datatransfer\r
+ -------------------------------------------------------------------\r
+ ufm_bus_ready_in <= '0'; \r
+\r
+ if ufm_cmd = '0' and ufm_bus_ready_out = '1' then\r
+ --copy data from UFM to registers\r
+ ufm_bus_ready_in <= '1';\r
+ case to_integer(ufm_databyte_counter) is\r
+ when 0 => reg(7 downto 0) <= ufm_data_out;\r
+ when 1 => reg(15 downto 8) <= ufm_data_out;\r
+ when 2 => reg(23 downto 16) <= ufm_data_out;\r
+ when 3 => reg(31 downto 24) <= ufm_data_out;\r
+ \r
+ when 4 => pulser_periodlength(7 downto 0) <= ufm_data_out;\r
+ when 5 => pulser_periodlength(15 downto 8) <= ufm_data_out;\r
+ when 6 => pulser_periodlength(23 downto 16) <= ufm_data_out;\r
+ when 7 => pulser_periodlength(27 downto 24) <= ufm_data_out(3 downto 0);\r
+ \r
+ when 8 => pulser_pulslength(7 downto 0) <= ufm_data_out;\r
+ when 9 => pulser_pulslength(15 downto 8) <= ufm_data_out;\r
+ when 10 => pulser_pulslength(23 downto 16) <= ufm_data_out;\r
+ when 11 => pulser_pulslength(27 downto 24) <= ufm_data_out(3 downto 0);\r
+ \r
+ when others =>null;\r
+ end case;\r
+ \r
+ elsif ufm_cmd = '1' and ufm_bus_ready_out = '1' then\r
+ --save data from registers to UFM\r
+ ufm_bus_ready_in <= '1';\r
+ case to_integer(ufm_databyte_counter) is\r
+ when 0 => ufm_data_in <= reg(7 downto 0);\r
+ when 1 => ufm_data_in <= reg(15 downto 8);\r
+ when 2 => ufm_data_in <= reg(23 downto 16);\r
+ when 3 => ufm_data_in <= reg(31 downto 24);\r
+\r
+ when 4 => ufm_data_in <= pulser_periodlength(7 downto 0);\r
+ when 5 => ufm_data_in <= pulser_periodlength(15 downto 8);\r
+ when 6 => ufm_data_in <= pulser_periodlength(23 downto 16);\r
+ when 7 => ufm_data_in <= x"0" & std_logic_vector(pulser_periodlength(27 downto 24));\r
+ \r
+ when 8 => ufm_data_in <= pulser_pulslength(7 downto 0);\r
+ when 9 => ufm_data_in <= pulser_pulslength(15 downto 8);\r
+ when 10 => ufm_data_in <= pulser_pulslength(23 downto 16);\r
+ when 11 => ufm_data_in <= x"0" & std_logic_vector(pulser_pulslength(27 downto 24));\r
+ \r
+ when others =>null;\r
+ end case;\r
+ \r
+ end if;\r
end process;\r
\r
\r
-THE_SED : entity work.sedcheck\r
- port map(\r
- CLK => clk_i,\r
- ERROR_OUT => sed_error,\r
- \r
- CONTROL_IN => controlsed_i,\r
- DEBUG => sed_debug\r
- );\r
-\r
- \r
- \r
- \r
----------------------------------------------------------------------------\r
--- Flash Controller\r
---------------------------------------------------------------------------- \r
-\r
-THE_FLASH_RAM : entity work.flashram\r
- port map(\r
- DataInA => ram_data_i,\r
- AddressA => ram_addr_i,\r
- ClockA => clk_i, \r
- ClockEnA => '1',\r
- WrA => ram_write_i, \r
- ResetA => '0',\r
- QA => ram_data_o,\r
-\r
- DataInB => flashram_data_i,\r
- AddressB => flashram_addr_i,\r
- ClockB => clk_33,\r
- ClockEnB => flashram_cen_i,\r
- WrB => flashram_write_i, \r
- ResetB => flashram_reset,\r
- QB => flashram_data_o\r
- );\r
-\r
-\r
-\r
-THE_FLASH : UFM_WB\r
- port map(\r
- clk_i => clk_33,\r
- rst_n => '1',\r
- cmd => flash_command,\r
- ufm_page => flash_page,\r
- GO => flash_go,\r
- BUSY => flash_busy,\r
- ERR => flash_err,\r
- mem_clk => open,\r
- mem_we => flashram_write_i,\r
- mem_ce => flashram_cen_i,\r
- mem_addr => flashram_addr_i,\r
- mem_wr_data => flashram_data_i,\r
- mem_rd_data => flashram_data_o\r
- ); \r
- \r
+-- THE_SED : entity work.sedcheck\r
+-- port map(\r
+-- CLK => clk_i,\r
+-- ERROR_OUT => sed_error,\r
+-- \r
+-- CONTROL_IN => controlsed_i,\r
+-- DEBUG => sed_debug\r
+-- );\r
\r
end architecture;\r
\r
\r
-
\ No newline at end of file
+ \r
\item[B] not used
\item[C] not used
\item[D] not used
-\item[E] Basic pulser, 8.1 kHz, 60 ns long signals
+\item[E] Basic pulser, 0,5 Hz - 66,5 MHz, pulslength in 7,5 nSec steps
\item[F] like E, but inverted
\end{description*}
\begin{itemize*}
\item[Bit 31] valid data
\end{description*}
+
+
+\section{Operation}
+The FPGA based versions of the Logic Box can be controlled over a RS232 interface. Settings can be loaded from and stored to flashmemory.
+
+\subsection{Control over RS232}
+The Logic Box can be controlled over a terminal program. Settings may be changed and also saved or loaded. The generell structure of RS232 commands is shown in Table \ref{tabRS232Writecommand} and \ref{tabRS232ReadCommand}. If a Read-Command is send the reply is formed as follows: RDDDDDDDD (wherein D..D is the 32-bit data consisting of 8 Hexnumbers). Table \ref{tabRS232LoadSaveCommands} shows the commands for saving and loading settings.
+
+\begin{table}[h]
+\begin{tabular}{ l| l}
+ \multicolumn{2}{l}{\textbf{W-XX-DDDD-DDDD} (actual commands without hyphens)} \\ \hline
+Designator & Command/Data\\ \hline
+XX & Registeradress consisting of 2 Hexnumbers\\
+D..D & 32-bit data consisting of 8 Hexnumbers\\
+\end{tabular}
+ \caption{RS232 Write Command}
+ \label{tabRS232Writecommand}
+\end{table}
+
+\begin{table}[h]
+\begin{tabular}{ l| l}
+ \multicolumn{2}{l}{\textbf{R-XX} (actual commands without hyphens)} \\ \hline
+Designator & Command/Data\\ \hline
+XX & Registeradress consisting of 2 Hexnumbers\\
+\end{tabular}
+ \caption{RS232 Read Command}
+ \label{tabRS232ReadCommand}
+\end{table}
+
+\begin{table}[h]
+\begin{tabular}{ l| l}
+
+Description & Command\\ \hline
+Load & W0200000000\\
+Save & W02FFFFFFFF\\
+\end{tabular}
+ \caption{RS232 Load/Save Commands}
+ \label{tabRS232LoadSaveCommands}
+\end{table}
+
+
+
+
+
+\subsection{Level Converter}
+
+\subsection{Logic Box}
+As already mentioned different modes can be selected by using the on-board switch. Furthermore the pulswidth and frequency of the basic pulser can be adjusted over RS232. Table \ref{tabRS232BasicPulserCommands} shows the associated commands. Here D..D is the 28-bit or 7-digit Hexnumber that defines the pulslength/periodlength. -I- can be an arbitrary number since it will be ignored. The puls- and periodlength are adjusted as multiples of approximately 7,5 nSec.
+
+\begin{table}[h]
+\begin{tabular}{ l| l}
+
+Description & Command (actual commands without hyphens)\\ \hline
+Adjust periodlength & W20-I-DDD-DDDD\\
+Read periodlength & R20\\
+Adjust pulslength & W21-I-DDD-DDDD\\
+Read pulslength & R21\\
+\end{tabular}
+ \caption{RS232 Basic Pulser Commands}
+ \label{tabRS232BasicPulserCommands}
+\end{table}
+
+
+\subsection{Pulse Generator}
+
+\subsection{TDC}
+
% \cleardoublepage
% \begin{appendices}
% \end{appendices}
IOBUF PORT "CBUS" IO_TYPE=LVTTL33 ;
IOBUF PORT "CLK" IO_TYPE=LVDS25 ;
IOBUF PORT "STATUSO" IO_TYPE=LVTTL33 ;
-IOBUF PORT "STATUSI" IO_TYPE=LVTTL33 PULLMODE=DOWN;
+IOBUF PORT "STATUSI" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
BANK 0 VCCIO 3.3 V;
BANK 5 VCCIO 3.3 V;
BANK 2 VCCIO 3.3 V;
-
-
-FREQUENCY PORT CLK 100 MHz;
-FREQUENCY NET clk_osc 133 MHz;
\ No newline at end of file
+FREQUENCY PORT "CLK" 100.000000 MHz ;
+FREQUENCY NET "clk_osc" 133.000000 MHz ;
jspc29 / logicbox.git / commitdiff
