bugfix for padding correction

diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd
index 18563066094a1159248f7045499ba917a6e07459..40128eae9b21e718a1cb3b995dbd57e300ca5497 100644 (file)
--- a/trb_net16_api_base.vhd
+++ b/trb_net16_api_base.vhd
@@ -106,6 +106,7 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is
   signal fifo_to_int_read  : std_logic;
   signal fifo_to_int_full  : std_logic;
   signal fifo_to_int_empty : std_logic;
+  signal last_fifo_to_int_empty : std_logic;
 
   -- signals for the INT to APL:
   signal fifo_to_apl_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
@@ -772,7 +773,7 @@ INT_MASTER_DATAREADY_OUT  <= buf_INT_MASTER_DATAREADY_OUT;
             next_INT_MASTER_DATAREADY_OUT <= sbuf_free and
                                 ((fifo_to_int_read_before or master_counter(2)) or   --write data from fifo
                                 (fifo_to_int_empty and not master_counter(2))); --fill with padding words
-            if fifo_to_int_empty = '1' then
+            if last_fifo_to_int_empty = '1' then
               out_select <= PAD;
             end if;
             if master_counter = c_F3 and fifo_to_int_empty = '1' and sbuf_free = '1' then
@@ -809,6 +810,7 @@ INT_MASTER_DATAREADY_OUT  <= buf_INT_MASTER_DATAREADY_OUT;
           state_to_int <= next_state_to_int;
           send_trm_wrong_addr <= next_send_trm_wrong_addr;
           fifo_was_not_empty <= next_fifo_was_not_empty;
+          last_fifo_to_int_empty  <= fifo_to_int_empty;
         end if;
       end if;
     end process;