*** empty log message ***

diff --git a/trb_net16_regio_bus_handler.vhd b/trb_net16_regio_bus_handler.vhd
index 65d2f71521fdff36fa819e8a5391fdf877551317..923e208a6f06e45478129b7ec1c34c433ca4ac6e 100644 (file)
--- a/trb_net16_regio_bus_handler.vhd
+++ b/trb_net16_regio_bus_handler.vhd
@@ -50,8 +50,8 @@ architecture regio_bus_handler_arch of trb_net16_regio_bus_handler is
   signal port_select_int      : integer range 0 to c_BUS_HANDLER_MAX_PORTS;
   signal next_port_select_int : integer range 0 to c_BUS_HANDLER_MAX_PORTS;
 
-  signal buf_BUS_READ_OUT         : std_logic_vector(PORT_NUMBER-1 downto 0);
-  signal buf_BUS_WRITE_OUT        : std_logic_vector(PORT_NUMBER-1 downto 0);
+  signal buf_BUS_READ_OUT         : std_logic_vector(PORT_NUMBER downto 0);
+  signal buf_BUS_WRITE_OUT        : std_logic_vector(PORT_NUMBER downto 0);
   signal buf_BUS_DATA_OUT         : std_logic_vector(31 downto 0);
   signal buf_BUS_ADDR_OUT         : std_logic_vector(15 downto 0);
 
@@ -69,26 +69,14 @@ begin
 
   proc_port_select : process(DAT_ADDR_IN)
     begin
+      next_port_select_int <= PORT_NUMBER;
       gen_port_select : for i in 0 to PORT_NUMBER-1 loop
-        next_port_select_int <= PORT_NUMBER;
         if DAT_ADDR_IN(15 downto PORT_ADDR_MASK(i)) = PORT_ADDRESSES(i)(15 downto PORT_ADDR_MASK(i)) then
           next_port_select_int <= i;
         end if;
       end loop;
     end process;
 
-  proc_reg_port_sel : process(CLK)
-    begin
-      if rising_edge(CLK) then
-        if RESET = '1' then
-          port_select_int <= 0;
-        elsif DAT_WRITE_ENABLE_IN = '1' or DAT_READ_ENABLE_IN = '1' then
-          port_select_int <= next_port_select_int;
-        end if;
-      end if;
-    end process;
-
-
 ---------------------------------------------------------------------
 --Generate R/W strobes
 ---------------------------------------------------------------------
@@ -99,11 +87,15 @@ begin
         if RESET = '1' then
           buf_BUS_READ_OUT  <= (others => '0');
           buf_BUS_WRITE_OUT <= (others => '0');
+          port_select_int <= PORT_NUMBER;
         else
           buf_BUS_READ_OUT  <= (others => '0');
           buf_BUS_WRITE_OUT <= (others => '0');
-          buf_BUS_DATA_OUT  <= DAT_DATA_IN;
-          buf_BUS_ADDR_OUT  <= DAT_ADDR_IN;
+          if DAT_WRITE_ENABLE_IN = '1' or DAT_READ_ENABLE_IN = '1' then
+            buf_BUS_DATA_OUT  <= DAT_DATA_IN;
+            buf_BUS_ADDR_OUT  <= DAT_ADDR_IN;
+            port_select_int   <= next_port_select_int;
+          end if;
           if DAT_READ_ENABLE_IN = '1' then
             buf_BUS_READ_OUT(next_port_select_int) <= '1';
           end if;
@@ -118,8 +110,8 @@ begin
 --Map Data Outputs
 ---------------------------------------------------------------------
 
-  BUS_READ_ENABLE_OUT <= buf_BUS_READ_OUT;
-  BUS_WRITE_ENABLE_OUT<= buf_BUS_WRITE_OUT;
+  BUS_READ_ENABLE_OUT <= buf_BUS_READ_OUT(PORT_NUMBER-1 downto 0);
+  BUS_WRITE_ENABLE_OUT<= buf_BUS_WRITE_OUT(PORT_NUMBER-1 downto 0);
   gen_bus_outputs : for i in 0 to PORT_NUMBER-1 generate
     BUS_DATA_OUT(i*32+31 downto i*32)  <= buf_BUS_DATA_OUT;
     BUS_ADDR_OUT(i*16+15 downto i*16)  <= buf_BUS_ADDR_OUT;
@@ -140,19 +132,23 @@ begin
   buf_BUS_DATAREADY_IN(PORT_NUMBER) <= '0';
   buf_BUS_WRITE_ACK_IN(PORT_NUMBER) <= '0';
   buf_BUS_NO_MORE_DATA_IN(PORT_NUMBER) <= '0';
-  buf_BUS_UNKNOWN_ADDR_IN(PORT_NUMBER) <= '1';
+  buf_BUS_UNKNOWN_ADDR_IN(PORT_NUMBER) <= buf_BUS_READ_OUT(PORT_NUMBER) or buf_BUS_WRITE_OUT(PORT_NUMBER);
 
 
 ---------------------------------------------------------------------
 --Multiplex Data Output
 ---------------------------------------------------------------------
 
-  DAT_DATA_OUT          <= buf_BUS_DATA_IN(port_select_int*32+31 downto port_select_int*32);
-  DAT_DATAREADY_OUT     <= buf_BUS_DATAREADY_IN(port_select_int);
-  DAT_WRITE_ACK_OUT     <= buf_BUS_WRITE_ACK_IN(port_select_int);
-  DAT_NO_MORE_DATA_OUT  <= buf_BUS_NO_MORE_DATA_IN(port_select_int);
-  DAT_UNKNOWN_ADDR_OUT  <= buf_BUS_UNKNOWN_ADDR_IN(port_select_int);
-
+  proc_reg_output_signals : process(CLK)
+    begin
+      if rising_edge(CLK) then
+        DAT_DATA_OUT          <= buf_BUS_DATA_IN(port_select_int*32+31 downto port_select_int*32);
+        DAT_DATAREADY_OUT     <= buf_BUS_DATAREADY_IN(port_select_int);
+        DAT_WRITE_ACK_OUT     <= buf_BUS_WRITE_ACK_IN(port_select_int);
+        DAT_NO_MORE_DATA_OUT  <= buf_BUS_NO_MORE_DATA_IN(port_select_int);
+        DAT_UNKNOWN_ADDR_OUT  <= buf_BUS_UNKNOWN_ADDR_IN(port_select_int);
+      end if;
+    end process;
 
 ---------------------------------------------------------------------
 --Debugging