Full : out std_logic);
end component;
+ component FIFO_DC_36x128_DynThr_OutReg is
+ port (
+ Data : in std_logic_vector(35 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ AmFullThresh : in std_logic_vector(6 downto 0);
+ Q : out std_logic_vector(35 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostFull : out std_logic);
+ end component FIFO_DC_36x128_DynThr_OutReg;
+
component FIFO_DC_36x128_OutReg is
port (
Data : in std_logic_vector(35 downto 0);