new fifo core with dynamic threshold

diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd
index 73ca4c924d3d88bda3450625054d5ab0076b7c37..8b66550f5fceeb7a4d0dbbfbc08120f65f5e5e00 100644 (file)
--- a/base/trb3_components.vhd
+++ b/base/trb3_components.vhd
@@ -110,6 +110,22 @@ package trb3_components is
       Full        : out std_logic);
   end component;  
 
+  component FIFO_DC_36x128_DynThr_OutReg is
+    port (
+      Data         : in  std_logic_vector(35 downto 0);
+      WrClock      : in  std_logic;
+      RdClock      : in  std_logic;
+      WrEn         : in  std_logic;
+      RdEn         : in  std_logic;
+      Reset        : in  std_logic;
+      RPReset      : in  std_logic;
+      AmFullThresh : in  std_logic_vector(6 downto 0);
+      Q            : out std_logic_vector(35 downto 0);
+      Empty        : out std_logic;
+      Full         : out std_logic;
+      AlmostFull   : out std_logic);
+  end component FIFO_DC_36x128_DynThr_OutReg;
+  
   component FIFO_DC_36x128_OutReg is
     port (
       Data       : in  std_logic_vector(35 downto 0);