-\subsection{SPI Interface}
- \input{DacProgramming}
-\subsection{Forward inputs for trigger}
- \input{TriggerModule}
-\subsection{Interfaces}
+\section{Communication Interfaces}
\begin{description}
- \item[SPI] The module used for DAC programming is a generic SPI interface that can be used for any purpose. (resources: 300 slices in FPGA)
- \item[UART] A generic UART master implemented in FPGA (resources: 300 slices in FPGA)
- \item[LCD] Any numeric values can be shown on a graphic LCD (resources: 800 slices in FPGA)
- \item[Debug] For debugging, a UART can be used to access the internal data bus (resources: 300 slices in FPGA)
+ \item[SPI] SPI module, e.g. for communication with Padiwa, threshold FPGAs (DiRich) or any other SPI device.
+ \item[I2C] A I2C controller for accesses up to 3 byte.
+ \item[UART] A generic UART master implemented in FPGA
+ \item[Debug] For debugging, a UART that can be used to access the internal data bus
\end{description}
+
-The generic SPI interface which is used for many modules has the following structure:
-
-\begin{tabularx}{\textwidth}{c|c|X}
- \textbf{Bit} & \textbf{Name} & \textbf{Content} \\
- \hline
- 31 -- 24 & 8-Bit-Register & \\
- 23 -- 20 & Command & Command, 0: read, 8: write, other: no operation \\
- 19 -- 16 & Subregister & Additional 4 bits (only used for padiwa amps and v123) \\
- 15 -- 0 & Data & 16 Bit data payload for write commands\\
-\end{tabularx}
-
-The generic UART interface has the following structure:
-
-\begin{tabularx}{\textwidth}{c|c|X}
- \textbf{Bit} & \textbf{Name} & \textbf{Content} \\
- \hline
- 39 -- 32 & 8-Bit-Register & \\
- 31 -- 0 & Data & 16 Bit data payload for write commands\\
-\end{tabularx}
-
-
-\subsection{Flash programming}
+\subsection{SPI Interface}
+ \input{DacProgramming}
+
+\subsection{Flash programming (MachXO3)}
Flash programming of the MACHX03 FPGAs (like the DiRich threshold FPGAs or the Logicbox, but also Padiwa-Amps2) is done via a generic
flash controller which sits in the middle between the serial interface (SPI or UART) and
+
+
Programming the DAC for threshold generation is simple: A standard SPI interface takes 32 Bit of data, the device is chainable. A Perl software module cares about the data content, a simple VHDL core outputs the data and controls the CS signal.
-\paragraph*{Slow Control Interface}
+\subsubsection{Slow Control Interface}
\begin{itemize*}
\item 32 Bit Data Memory: 0xd400 - 0xd40f, Chain select mask 0xd410, Length register 0xd411
\item Transfer is started when the length register (counting 32 Bit words) is written.
\item While busy, the writing to the length register will be ignored and gives back a no-more-data flag.
\item Doing a memory write with 18 words will do the job, should be faster than two individual accesses for data and length.
- \item All data is sent MSB first (Bit 31), Bits 31-24 are the don't-care-Bits of the DAC.
+ \item All data is sent MSB first (Bit 31)
\item Interface speed: e.g. 6.25 MHz -> max. 80us for 16 chips
\item If a chain contains only one device, up to 16 commands can be sent to this device with one access. Bit 7 in length register 0xd411 has to be set to select this multi-write to single device mode.
\item Register 0xd412 contains the read-back of data from SPI. Content depends on slave chip.
\end{itemize*}
-\paragraph*{VHDL Configuration}
-The number of bits per word can be set with a generic in the VHDL component instantiation. If a value below 32 is chosen, the upper bits in all registers are ignored.
-The number of wait-cycles between two edges on SCK can be selected as well. The default for LTC2600 and Padiwa is 7 wait cycles, I.e. 6.25 MHz.
+\paragraph*{Registers}~\\
+
+\begin{tabularx}{\textwidth}{c|c|X}
+ 0xd40N & Data & 16 places for SPI commands \\
+ 0xd410 & Chip Select & CS output, one bit for each of the 15 outputs, positive logic\\
+ 0xd411 & Control & Control register. See next paragraph\\
+ 0xd412 & Readback & Data received on SPI\\
+ 0xd413 & Master & Block SPI for other use. See next paragraph\\
+ 0xd414 & Clear & Additional output to connect to a CLR-input on SPI devices \newline(not available in most designs)\\
+ 0xd415 & SDO Ctrl & Bit 15..0: Disable SDO outputs, Bit 31..16: Invert SDO outputs\newline(added 2019-01-30)\\
+ 0xd416 & SCK Ctrl & Bit 15..0: Disable SCK outputs, Bit 31..16: Invert SCK outputs\newline(added 2019-01-30)\\
+ 0xd417 & CS Ctrl & Bit 15..0: Disable CS outputs, Bit 31..16: Invert CS outputs\newline(added 2019-01-30)\\
+ 0xd418 & Invert & Set lowest bit to invert all outputs (removed 2019-01-30)\\
+ 0xd419 & Word Length & Number of bits of a SPI word, default: 32\\
+ 0xd41a & Period & Half period of a SPI clock cycle, in system clocks. default: 7\\
+
+\end{tabularx}
-\paragraph*{Configuration File for LTC2600 DAC}
+\subsubsection{Use with LTC2600 DAC}
+\paragraph*{Configuration File}
The software takes a text file as input and generates the correct SPI sequence to load and activate the DAC.
The ASCII format is shown below, the commands can be found in table~\ref{ltc2600cmd}.
\begin{verbatim}
\item Example Configuration: daqtools/config/DAC\_config.db
\end{itemize*}
-\paragraph*{Registers}~\\
-\begin{tabularx}{\textwidth}{c|c|X}
- 0xd40N & Data & 16 places for SPI commands \\
- 0xd410 & Chip Select & CS output, one bit for each of the 15 outputs, positive logic\\
- 0xd411 & Control & Control register. See next paragraph\\
- 0xd412 & Readback & Data received on SPI\\
- 0xd413 & Master & Block SPI for other use. See next paragraph\\
- 0xd414 & Clear & Additional output to connect to a CLR-input on SPI devices \newline(not available in most designs)\\
- 0xd415 & SDO Ctrl & Bit 15..0: Disable SDO outputs, Bit 31..16: Invert SDO outputs\newline(added 2019-01-30)\\
- 0xd416 & SCK Ctrl & Bit 15..0: Disable SCK outputs, Bit 31..16: Invert SCK outputs\newline(added 2019-01-30)\\
- 0xd417 & CS Ctrl & Bit 15..0: Disable CS outputs, Bit 31..16: Invert CS outputs\newline(added 2019-01-30)\\
- 0xd418 & Invert & Set lowest bit to invert all outputs (removed 2019-01-30)\\
- 0xd419 & Word Length & Number of bits of a SPI word, default: 32\\
- 0xd41a & Period & Half period of a SPI clock cycle, in system clocks. default: 7\\
-
-\end{tabularx}
-\paragraph*{Collisions during reading}
+\subsubsection{Collisions during reading}
Writing to all registers is blocked while a transfer is in progress, i.e. writing can not be broken.
Reading back a value can break, if to processes access the SPI port in a interleaved manner, because reading the read-back register is non-atomic.
+\section{Trigger Generation}
\label{triggermodule}
The trigger module can be used to forward any input of a peripheral FPGA via the central FPGA to
-the CTS. E.g. any input to any TDC can be used to generate the trigger in the CTS. (resources: 400 slices in FPGA for 32 inputs, 2 outputs)
+the CTS. E.g. any input to any TDC can be used to generate the trigger in the CTS.
-The VHDL code is available in \files{trb3/base/code/input\_to\_trigger\_logic\_record.vhd}
-
-\paragraph*{Setup}
The trigger module can feature up to 96 input signals and up to 8 independent outputs.
For each output, any of the connected inputs can be enabled or disabled as well as been inverted
\verb!(chanA and chanB) or (chanC and chanD) or ...!
\end{itemize*}
-All modules have their own configuration registers and can be used in combination of individually.
-
-The central FPGA contains the same trigger logic to combine the four signals from each of the
-peripheral FPGAs to one common signal forwarded on the trigger output on the RJ-45 connector
-(middle pair). Additional signals can be forward to the AddOn connector of the central FPGA, e.g.
-to one of the RJ-45 sockets on the CTS-AddOn.
+All modules have their own configuration registers and can be used in combination or individually.
-\paragraph*{SlowControl}
-Configuration of the module can be done in registers 0xcf00 to 0xcf3f. Each output has two
-configuration registers. The first one contains a bit mask to enable individual inputs, the second is unused.
-Additionally, inputs can be inverted and short signals can be stretched to at least 10 ns length.
+On a TRB3, the central FPGA contains the same trigger logic to combine the four signals from each of the
+peripheral FPGAs to one common signal forwarded on the trigger output on the RJ-45 connector.
-\paragraph*{Input Scalers}
-An additional module is used to have counters for each of up to 32 input channels. These values can
-be stored in a Fifo at an adjustable rate. The Fifos for all channels are controlled by a common
-logic and store their data synchronously. Filling of the Fifos has to be triggered and stops after
-1024 samples have been acquired.
-To save resources, it is also possible to use only one monitoring Fifo combined
-with a multiplexer to select one of the inputs as source. (resources: 1300 slices in FPGA for 32 inputs)
-\subsubsection{Inputs}
+\subsection{Inputs}
The number, order and selection of inputs varies depending on the hardware and design used in the FPGAs. This list shows the most common design options:
+The inputs labeled as "trigger logic output" are only used for the monitoring scalers, not on the trigger logic itself.
\begin{itemize}
\item Trb3sc CTS: Backplane master
\end{itemize}
\end{itemize}
+
+\subsection{Outputs}
+\begin{itemize}
+\item Trb3: peripheral
+\begin{itemize}
+\item 4 outputs to central FPGA
+\end{itemize}
+
+\item Trb3: central (hub)
+\begin{itemize}
+\item Output 0: TRG\_RJ(3)
+\item Output 1: TRG\_RJ(4)
+\item Output 2: CLK\_RJ(3)
+\item Output 3: CLK\_RJ(4)
+\end{itemize}
+
+\item Trb3sc
+\begin{itemize}
+\item Output 0: RJ\_IO(3)
+\item Output 1: RJ\_IO(4)
+\item Output 2: RJ\_IO(1) and Backplane(0)
+\item Output 3: RJ\_IO(2) and Backplane(1)
+\end{itemize}
+
+\item Trb5sc
+\begin{itemize}
+\item Output 0: RJ\_IO(3)
+\item Output 1: RJ\_IO(4)
+\item Output 2: Backplane(0)
+\item Output 3: Backplane(1)
+\end{itemize}
+
+
+\end{itemize}
+
+
+
+\section{Input Scalers}
+An additional module is used to have counters for each of the input channels. These values can
+be stored in a Fifo at an adjustable rate.
+To save resources, it is also possible there is one monitoring Fifo combined with a multiplexer to select one of the inputs as source.
+This Fifo can store up to 1024 samples of the counter of the selected channel at configurable intervals.
+
+Examples of the input connections are listed in the Trigger Generation section right above.
+
\subsection{FPGA based TDC calibration}
\input{Trb3scFpgaBasedTdcCalibration}
\clearpage
- \section{Additional Modules}
- \input{AdditionalModules}
+ \input{AdditionalModules}
+ \clearpage
+ \input{TriggerModule}
\clearpage
\section{GbE Data Read-out}
jspc29 / daqdocu.git / commitdiff