--- /dev/null
+*~
+*.log
+*.rpt
+netlists
+version.vhd
+*.jhd
+*.naf
+*.sort
+*.srp
+*.sym
+*tmpl.vhd
+*.log
+workdir
+workdir_*
+*.bit
+*.kate-swp*
+*.kate-swap*
+.run_manager.ini
+reportview.xml
+.kateproject.d
+cts/project*
+cbmnet/project*
+cbmnet/sim*
+
--- /dev/null
+######################################################################\r
+# ADCMv3 pinouts\r
+######################################################################\r
+\r
+COMMERCIAL;\r
+BLOCK RESETPATHS;\r
+BLOCK ASYNCPATHS;\r
+\r
+######################################################################\r
+# I/O bank 8 - 3.30V\r
+# JTAG and SPI boot interface\r
+######################################################################\r
+#\r
+# These signals are not user definable! Hands off!\r
+\r
+######################################################################\r
+# I/O bank 7 - 2.50V\r
+# APV1 control signals, ADC1 inputs\r
+######################################################################\r
+LOCATE COMP "APV1A_CLK" SITE "J8" ;\r
+IOBUF PORT "APV1A_CLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV1B_CLK" SITE "G5" ;\r
+IOBUF PORT "APV1B_CLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV1A_TRG" SITE "L5" ;\r
+IOBUF PORT "APV1A_TRG" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV1B_TRG" SITE "G6" ;\r
+IOBUF PORT "APV1B_TRG" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV1_SDA" SITE "K7" ;\r
+IOBUF PORT "APV1_SDA" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "APV1_SCL" SITE "K6" ;\r
+IOBUF PORT "APV1_SCL" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "APV1_RST" SITE "K5" ;\r
+IOBUF PORT "APV1_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "ADC1_LCLK" SITE "L3" ;\r
+IOBUF PORT "ADC1_LCLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_ADCLK" SITE "D2" ;\r
+IOBUF PORT "ADC1_ADCLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_7" SITE "E2" ;\r
+IOBUF PORT "ADC1_OUT_7" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_6" SITE "G2" ;\r
+IOBUF PORT "ADC1_OUT_6" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_5" SITE "J5" ;\r
+IOBUF PORT "ADC1_OUT_5" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_4" SITE "J3" ;\r
+IOBUF PORT "ADC1_OUT_4" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_3" SITE "K2" ;\r
+IOBUF PORT "ADC1_OUT_3" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_2" SITE "N5" ;\r
+IOBUF PORT "ADC1_OUT_2" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_1" SITE "M4" ;\r
+IOBUF PORT "ADC1_OUT_1" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_0" SITE "P3" ;\r
+IOBUF PORT "ADC1_OUT_0" IO_TYPE=LVDS25 ;\r
+\r
+LOCATE COMP "ADC1_CLK" SITE "H2" ;\r
+IOBUF PORT "ADC1_CLK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "ADC1_RST" SITE "G3" ;\r
+IOBUF PORT "ADC1_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC1_CS" SITE "E1" ;\r
+IOBUF PORT "ADC1_CS" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC1_PD" SITE "H1" ;\r
+IOBUF PORT "ADC1_PD" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC1_SDI" SITE "F2" ;\r
+IOBUF PORT "ADC1_SDI" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "ADC1_SCK" SITE "F1" ;\r
+IOBUF PORT "ADC1_SCK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "FPGA_LED_ADC_1" SITE "H3" ;\r
+IOBUF PORT "FPGA_LED_ADC_1" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+\r
+# LOCATE COMP "ADC1_DEBUG" SITE "H4" ;\r
+# IOBUF PORT "ADC1_DEBUG" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+\r
+# short cut pins for FPGA placement control by JTAG\r
+# LOCATE COMP "PIN_CHECK_7_IN" SITE "E3" ;\r
+# LOCATE COMP "PIN_CHECK_7_OUT" SITE "E4" ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 6 - 2.50V\r
+# APV0 control signals, ADC0 inputs, 12 test outputs to pads\r
+######################################################################\r
+LOCATE COMP "APV0A_CLK" SITE "AC7" ;\r
+IOBUF PORT "APV0A_CLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV0B_CLK" SITE "W3" ;\r
+IOBUF PORT "APV0B_CLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV0A_TRG" SITE "Y9" ;\r
+IOBUF PORT "APV0A_TRG" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV0B_TRG" SITE "AB4" ;\r
+IOBUF PORT "APV0B_TRG" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV0_SDA" SITE "Y6" ;\r
+IOBUF PORT "APV0_SDA" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "APV0_SCL" SITE "AA6" ;\r
+IOBUF PORT "APV0_SCL" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "APV0_RST" SITE "AA5" ;\r
+IOBUF PORT "APV0_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "ADC0_LCLK" SITE "T3" ;\r
+IOBUF PORT "ADC0_LCLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_ADCLK" SITE "R3" ;\r
+IOBUF PORT "ADC0_ADCLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_7" SITE "T5" ;\r
+IOBUF PORT "ADC0_OUT_7" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_6" SITE "U3" ;\r
+IOBUF PORT "ADC0_OUT_6" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_5" SITE "U5" ;\r
+IOBUF PORT "ADC0_OUT_5" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_4" SITE "Y1" ;\r
+IOBUF PORT "ADC0_OUT_4" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_3" SITE "AA1" ;\r
+IOBUF PORT "ADC0_OUT_3" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_2" SITE "AB2" ;\r
+IOBUF PORT "ADC0_OUT_2" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_1" SITE "AC1" ;\r
+IOBUF PORT "ADC0_OUT_1" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_0" SITE "AD2" ;\r
+IOBUF PORT "ADC0_OUT_0" IO_TYPE=LVDS25 ;\r
+\r
+LOCATE COMP "ADC0_CLK" SITE "W1" ;\r
+IOBUF PORT "ADC0_CLK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4;\r
+LOCATE COMP "ADC0_RST" SITE "AD3" ;\r
+IOBUF PORT "ADC0_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC0_CS" SITE "AC3" ;\r
+IOBUF PORT "ADC0_CS" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC0_PD" SITE "V1" ;\r
+IOBUF PORT "ADC0_PD" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC0_SDI" SITE "AB1" ;\r
+IOBUF PORT "ADC0_SDI" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "ADC0_SCK" SITE "W2" ;\r
+IOBUF PORT "ADC0_SCK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "FPGA_LED_ADC_0" SITE "V2" ;\r
+IOBUF PORT "FPGA_LED_ADC_0" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+\r
+# LOCATE COMP "ADC0_DEBUG" SITE "AC5" ;\r
+# IOBUF PORT "ADC0_DEBUG" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 5 - 3.30V\r
+# LVDS driver control, backplane sense pins\r
+######################################################################\r
+LOCATE COMP "ENA_LVDS_7" SITE "AG2" ;\r
+LOCATE COMP "ENA_LVDS_6" SITE "AG3" ;\r
+LOCATE COMP "ENA_LVDS_5" SITE "AG4" ;\r
+LOCATE COMP "ENA_LVDS_4" SITE "AG5" ;\r
+LOCATE COMP "ENA_LVDS_3" SITE "AG11" ;\r
+LOCATE COMP "ENA_LVDS_2" SITE "AG12" ;\r
+LOCATE COMP "ENA_LVDS_1" SITE "AG13" ;\r
+LOCATE COMP "ENA_LVDS_0" SITE "AG15" ;\r
+# LOCATE COMP "FPGA_SECTOR_5" SITE "AF16" ;\r
+# IOBUF PORT "FPGA_SECTOR_5" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SECTOR_4" SITE "AE16" ;\r
+# IOBUF PORT "FPGA_SECTOR_4" IO_TYPE=LVTTL33 ;\r
+# Backplane sense wires: sector number\r
+# small assembly bug: switch is 180degree rotated, so number are mirrored\r
+LOCATE COMP "BP_SECTOR_3" SITE "AF11" ; # was "AF15"\r
+IOBUF PORT "BP_SECTOR_3" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_SECTOR_2" SITE "AF12" ; # was "AF13"\r
+IOBUF PORT "BP_SECTOR_2" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_SECTOR_1" SITE "AF13" ; # was "AF12"\r
+IOBUF PORT "BP_SECTOR_1" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_SECTOR_0" SITE "AF15" ; # was "AF11"\r
+IOBUF PORT "BP_MODULE_0 IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+\r
+LOCATE COMP "BP_LED" SITE "AE8" ;\r
+IOBUF PORT "BP_LED" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 ;\r
+\r
+# LOCATE COMP "FPGA_SPARE_4" SITE "AF10" ;\r
+# IOBUF PORT "FPGA_SPARE_4" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_3" SITE "AG8" ;\r
+# IOBUF PORT "FPGA_SPARE_3" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_2" SITE "AF8" ;\r
+# IOBUF PORT "FPGA_SPARE_2" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_1" SITE "AG10" ;\r
+# IOBUF PORT "FPGA_SPARE_1" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_0" SITE "AG9" ;\r
+# IOBUF PORT "FPGA_SPARE_0" IO_TYPE=LVTTL33 ;\r
+\r
+# short cut pins for FPGA placement control by JTAG\r
+# LOCATE COMP "PIN_CHECK_5_IN" SITE "AF4" ;\r
+# LOCATE COMP "PIN_CHECK_5_OUT" SITE "AF3" ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 4 - 3.30V\r
+# 100MHZ clock in, SPI user pins, APV0 OneWire\r
+######################################################################\r
+LOCATE COMP "CLK100M" SITE "AJ14" ;\r
+IOBUF PORT "CLK100M" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV0_1W_7" SITE "AJ16" ;\r
+IOBUF PORT "APV0_1W_7" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_6" SITE "AK16" ;\r
+IOBUF PORT "APV0_1W_6" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_5" SITE "AJ17" ;\r
+IOBUF PORT "APV0_1W_5" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_4" SITE "AK17" ;\r
+IOBUF PORT "APV0_1W_4" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_3" SITE "AG18" ;\r
+IOBUF PORT "APV0_1W_3" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_2" SITE "AG19" ;\r
+IOBUF PORT "APV0_1W_2" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_1" SITE "AG20" ;\r
+IOBUF PORT "APV0_1W_1" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_0" SITE "AG21" ;\r
+IOBUF PORT "APV0_1W_0" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+# LOCATE COMP "EXP_2" SITE "AF21" ;\r
+# IOBUF PORT "EXP_2" IO_TYPE=LVTTL33;\r
+# LOCATE COMP "EXP_1" SITE "AE20" ;\r
+# IOBUF PORT "EXP_1" IO_TYPE=LVTTL33;\r
+# LOCATE COMP "EXP_0" SITE "AE21" ;\r
+# IOBUF PORT "EXP_0" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "U_SPI_SDO" SITE "AE24" ;\r
+IOBUF PORT "U_SPI_SDO" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "U_SPI_SDI" SITE "AE25" ;\r
+IOBUF PORT "U_SPI_SDI" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "U_SPI_CS" SITE "AD24" ;\r
+IOBUF PORT "U_SPI_CS" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "U_SPI_SCK" SITE "AF26" ;\r
+IOBUF PORT "U_SPI_SCK" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ;\r
+\r
+LOCATE COMP "FPGA_LED_PLL" SITE "AG22" ;\r
+IOBUF PORT "FPGA_LED_PLL" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+\r
+# short cut pins for FPGA placement control by JTAG\r
+# LOCATE COMP "PIN_CHECK_4_IN" SITE "AD23" ;\r
+# LOCATE COMP "PIN_CHECK_4_OUT" SITE "AC23" ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 3 - 3.30V\r
+# uC connection, external inputs, debug pins (SMC50)\r
+######################################################################\r
+LOCATE COMP "EXT_IN_3" SITE "AA30" ;\r
+IOBUF PORT "EXT_IN_3" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "EXT_IN_2" SITE "AB30" ;\r
+IOBUF PORT "EXT_IN_2" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "EXT_IN_1" SITE "AB29" ;\r
+IOBUF PORT "EXT_IN_1" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "EXT_IN_0" SITE "AB28" ;\r
+# alternative, if needed\r
+# LOCATE COMP "EXT_IN_0" SITE "P28" ;\r
+IOBUF PORT "EXT_IN_0" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "DBG_EXP_41" SITE "T27" ;\r
+# LOCATE COMP "DBG_EXP_39" SITE "T26" ;\r
+# LOCATE COMP "DBG_EXP_37" SITE "U26" ;\r
+# LOCATE COMP "DBG_EXP_35" SITE "V25" ;\r
+# LOCATE COMP "DBG_EXP_33" SITE "W25" ;\r
+# LOCATE COMP "DBG_EXP_31" SITE "W26" ;\r
+# LOCATE COMP "DBG_EXP_29" SITE "Y26" ;\r
+# LOCATE COMP "DBG_EXP_27" SITE "Y27" ;\r
+# LOCATE COMP "DBG_EXP_25" SITE "AB26" ;\r
+# LOCATE COMP "DBG_EXP_23" SITE "AC27" ;\r
+# LOCATE COMP "DBG_EXP_21" SITE "U25" ;\r
+# LOCATE COMP "DBG_EXP_19" SITE "U28" ;\r
+# LOCATE COMP "DBG_EXP_17" SITE "U27" ;\r
+# LOCATE COMP "DBG_EXP_5" SITE "R28" ;\r
+# LOCATE COMP "DBG_EXP_3" SITE "R27" ;\r
+# LOCATE COMP "DBG_EXP_1" SITE "T28" ;\r
+LOCATE COMP "UC_REBOOT" SITE "Y28" ; # was UC_FPGA3\r
+IOBUF PORT "UC_REBOOT" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_FPGA_2" SITE "W27" ;\r
+# IOBUF PORT "UC_FPGA_2" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_FPGA_1" SITE "W28" ;\r
+# IOBUF PORT "UC_FPGA_1" IO_TYPE=LVTTL33 ;\r
+# UC_FPGA_0 pin is GSR\r
+LOCATE COMP "UC_RESET" SITE "V26" ;\r
+IOBUF PORT "UC_RESET" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_WR" SITE "P29" ;\r
+# IOBUF PORT "UC_WR" IO_TYPE=LVTTL33;\r
+# LOCATE COMP "UC_RD" SITE "P30" ;\r
+# IOBUF PORT "UC_RD" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_ALE" SITE "W29" ;\r
+# IOBUF PORT "UC_ALE" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_SCL" SITE "N30" ;\r
+# IOBUF PORT "UC_SCL" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_SDA" SITE "N29" ;\r
+# IOBUF PORT "UC_SDA" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_7" SITE "W30" ;\r
+# IOBUF PORT "UC_AD_7" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_6" SITE "Y29" ;\r
+# IOBUF PORT "UC_AD_6" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_5" SITE "Y30" ;\r
+# IOBUF PORT "UC_AD_5" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_4" SITE "AA29" ;\r
+# IOBUF PORT "UC_AD_4" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_3" SITE "AB27" ;\r
+# IOBUF PORT "UC_AD_3" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_2" SITE "AC29" ;\r
+# IOBUF PORT "UC_AD_2" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_1" SITE "AC30" ;\r
+# IOBUF PORT "UC_AD_1" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_0" SITE "AC28" ;\r
+# IOBUF PORT "UC_AD_0" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_15" SITE "V30" ;\r
+# IOBUF PORT "UC_A_15" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_14" SITE "V29" ;\r
+# IOBUF PORT "UC_A_14" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_13" SITE "U30" ;\r
+# IOBUF PORT "UC_A_13" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_12" SITE "U29" ;\r
+# IOBUF PORT "UC_A_12" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_11" SITE "T30" ;\r
+# IOBUF PORT "UC_A_11" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_10" SITE "T29" ;\r
+# IOBUF PORT "UC_A_10" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_9" SITE "R30" ;\r
+# IOBUF PORT "UC_A_9" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_8" SITE "R29" ;\r
+# IOBUF PORT "UC_A_8" IO_TYPE=LVTTL33 ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 2 - 3.30V\r
+# SFP control, LEDs, 1Wire ID, debug pins (SMC50)\r
+######################################################################\r
+# LOCATE COMP "DBG_EXP_43" SITE "R26" ;\r
+# LOCATE COMP "DBG_EXP_42" SITE "P25" ;\r
+# LOCATE COMP "DBG_EXP_40" SITE "P26" ;\r
+# LOCATE COMP "DBG_EXP_38" SITE "N25" ;\r
+# LOCATE COMP "DBG_EXP_36" SITE "M25" ;\r
+# LOCATE COMP "DBG_EXP_34" SITE "M26" ;\r
+# LOCATE COMP "DBG_EXP_32" SITE "L25" ;\r
+# LOCATE COMP "DBG_EXP_30" SITE "L26" ;\r
+# LOCATE COMP "DBG_EXP_28" SITE "K25" ;\r
+# LOCATE COMP "DBG_EXP_26" SITE "J26" ;\r
+# LOCATE COMP "DBG_EXP_24" SITE "H25" ;\r
+# LOCATE COMP "DBG_EXP_22" SITE "H26" ;\r
+# LOCATE COMP "DBG_EXP_20" SITE "H24" ;\r
+# LOCATE COMP "DBG_EXP_18" SITE "G26" ;\r
+# LOCATE COMP "DBG_EXP_16" SITE "G25" ;\r
+# LOCATE COMP "DBG_EXP_15" SITE "L27" ;\r
+# LOCATE COMP "DBG_EXP_14" SITE "L28" ;\r
+# LOCATE COMP "DBG_EXP_13" SITE "M28" ;\r
+# LOCATE COMP "DBG_EXP_12" SITE "K24" ;\r
+# LOCATE COMP "DBG_EXP_11" SITE "M27" ;\r
+# LOCATE COMP "DBG_EXP_10" SITE "M30" ;\r
+# LOCATE COMP "DBG_EXP_9" SITE "N26" ;\r
+# LOCATE COMP "DBG_EXP_8" SITE "M29" ;\r
+# LOCATE COMP "DBG_EXP_7" SITE "P27" ;\r
+# LOCATE COMP "DBG_EXP_6" SITE "L30" ;\r
+# LOCATE COMP "DBG_EXP_4" SITE "L29" ;\r
+# LOCATE COMP "DBG_EXP_2" SITE "K30" ;\r
+# LOCATE COMP "DBG_EXP_0" SITE "K29" ;\r
+LOCATE COMP "FPGA_LED_6" SITE "G28" ;\r
+IOBUF PORT "FPGA_LED_6" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_5" SITE "G27" ;\r
+IOBUF PORT "FPGA_LED_5" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_4" SITE "H28" ;\r
+IOBUF PORT "FPGA_LED_4" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_3" SITE "H27" ;\r
+IOBUF PORT "FPGA_LED_3" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_RXD" SITE "J28" ;\r
+IOBUF PORT "FPGA_LED_RXD" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_TXD" SITE "J27" ;\r
+IOBUF PORT "FPGA_LED_TXD" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_LINK" SITE "K26" ;\r
+IOBUF PORT "FPGA_LED_LINK" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "SD_LOS" SITE "F30" ;\r
+IOBUF PORT "SD_LOS" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "SD_PRESENT" SITE "G30" ; # alias MD[0]\r
+IOBUF PORT "SD_PRESENT" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "SD_TXDIS" SITE "J29" ;\r
+IOBUF PORT "SD_TXDIS" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ;\r
+# LOCATE COMP "SD_TXFAULT" SITE "J30" ;\r
+# IOBUF PORT "SD_TXFAULT" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "SD_SDA" SITE "H30" ; # alias MD[2]\r
+# IOBUF PORT "SD_SDA" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "SD_SCL" SITE "H29" ; # alias MD[1]\r
+# IOBUF PORT "SD_SCL" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "SD_RATE" SITE "G29" ;\r
+# IOBUF PORT "SD_RATE" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "ADCM_ONEWIRE" SITE "F29" ;\r
+IOBUF PORT "ADCM_ONEWIRE" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8 ;\r
+\r
+# short cut pins for FPGA placement control by JTAG\r
+# LOCATE COMP "PIN_CHECK_2_IN" SITE "D29" ;\r
+# LOCATE COMP "PIN_CHECK_2_OUT" SITE "D30" ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 1 - 3.30V\r
+# APV1 OneWire\r
+######################################################################\r
+LOCATE COMP "APV1_1W_7" SITE "B15" ;\r
+IOBUF PORT "APV1_1W_7" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_6" SITE "A16" ;\r
+IOBUF PORT "APV1_1W_6" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_5" SITE "B16" ;\r
+IOBUF PORT "APV1_1W_5" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_4" SITE "A17" ;\r
+IOBUF PORT "APV1_1W_4" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_3" SITE "B17" ;\r
+IOBUF PORT "APV1_1W_3" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_2" SITE "C16" ;\r
+IOBUF PORT "APV1_1W_2" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_1" SITE "C17" ;\r
+IOBUF PORT "APV1_1W_1" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_0" SITE "D16" ;\r
+IOBUF PORT "APV1_1W_0" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+\r
+#### HERE WE ARE ######################\r
+\r
+\r
+######################################################################\r
+# I/O bank 0 - 3.30V\r
+# ADC1 control, LVDS driver control, backplane sense pins\r
+######################################################################\r
+LOCATE COMP "ENB_LVDS_7" SITE "F6" ;\r
+LOCATE COMP "ENB_LVDS_6" SITE "D5" ;\r
+LOCATE COMP "ENB_LVDS_5" SITE "D4" ;\r
+LOCATE COMP "ENB_LVDS_4" SITE "E5" ;\r
+LOCATE COMP "ENB_LVDS_3" SITE "D15" ;\r
+LOCATE COMP "ENB_LVDS_2" SITE "E13" ;\r
+LOCATE COMP "ENB_LVDS_1" SITE "D13" ;\r
+LOCATE COMP "ENB_LVDS_0" SITE "D12" ;\r
+# LOCATE COMP "FPGA_BP_13" SITE "C15" ;\r
+# IOBUF PORT "FPGA_BP_13" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_BP_12" SITE "C14" ;\r
+# IOBUF PORT "FPGA_BP_12" IO_TYPE=LVTTL33 ;\r
+# Backplane sense wires: backplane number\r
+LOCATE COMP "BP_MODULE_3" SITE "A14" ;\r
+IOBUF PORT "BP_MODULE_3" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_MODULE_2" SITE "F13" ;\r
+IOBUF PORT "BP_MODULE_2" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_MODULE_1" SITE "E12" ;\r
+IOBUF PORT "BP_MODULE_1" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_MODULE_0" SITE "G11" ;\r
+IOBUF PORT "BP_MODULE_0" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+\r
+# LOCATE COMP "FPGA_SPARE_12" SITE "D8" ;\r
+# IOBUF PORT "FPGA_SPARE_12" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_11" SITE "E8" ;\r
+# IOBUF PORT "FPGA_SPARE_11" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_10" SITE "D9" ;\r
+# IOBUF PORT "FPGA_SPARE_10" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_9" SITE "D11" ;\r
+# IOBUF PORT "FPGA_SPARE_9" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_8" SITE "F11" ;\r
+# IOBUF PORT "FPGA_SPARE_8" IO_TYPE=LVTTL33 ;\r
+\r
+LOCATE COMP "BP_ONEWIRE" SITE "F7" ;\r
+IOBUF PORT "BP_ONEWIRE" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 ;\r
+\r
+\r
+######################################################################\r
+# simplify IO definitions\r
+######################################################################\r
+# Debug header (50pin SMC connector)\r
+# DEFINE PORT GROUP "debug_header_group" "DBG_EXP_{0:43}" ;\r
+# IOBUF GROUP "debug_header_group" IO_TYPE=LVCMOS33 PULLMODE=DOWN DRIVE=4 SLEWRATE=FAST ;\r
+\r
+# LED drivers\r
+# DEFINE PORT GROUP "led_output_group" "FPGA_LED*" ;\r
+# IOBUF GROUP "led_output_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+\r
+# LVDS driver control\r
+DEFINE PORT GROUP "enable_lvds_group" "EN?_LVDS_{0:7}" ;\r
+IOBUF GROUP "enable_lvds_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW ;\r
+\r
+######################################################################\r
+# FPGA boot et. al.\r
+######################################################################\r
+SYSCONFIG PERSISTENT=OFF ;\r
+SYSCONFIG CONFIG_MODE=SPI ;\r
+SYSCONFIG DONE_OD=OFF ;\r
+SYSCONFIG DONE_EX=OFF ;\r
+SYSCONFIG MCCLK_FREQ=34 ;\r
+SYSCONFIG CONFIG_SECURE=OFF ;\r
+SYSCONFIG WAKE_UP=21 ;\r
+#SYSCONFIG WAKE_ON_LOCK=OFF ;\r
+SYSCONFIG COMPRESS_CONFIG=OFF ;\r
+SYSCONFIG INBUF=OFF ;\r
+SYSCONFIG ENABLE_NDR=OFF ;\r
+USERCODE HEX "DEADAFFE" ;\r
+######################################################################\r
+# PLL 100MHz -> 40MHz\r
+######################################################################\r
+FREQUENCY PORT "clk100m" 100.000000 MHz ;\r
+LOCATE COMP "THE_40M_PLL/PLLDINST_0" SITE "PLL_R103C3" ;\r
+FREQUENCY NET "clk_adc" 40.000000 MHz ;\r
+FREQUENCY NET "clk_apv" 40.000000 MHz ;\r
+\r
+######################################################################\r
+# DLL 100MHz -> 100MHz\r
+######################################################################\r
+LOCATE COMP "THE_100M_DLL/dll_100m_0_0" SITE "DLL_R103C1" ;\r
+FREQUENCY NET "sysclk" 100.000000 MHz ;\r
+\r
+######################################################################\r
+# TRBnet SerDes clock constraints\r
+######################################################################\r
+FREQUENCY NET "THE_RICH_TRB/THE_MEDIA_INTERFACE/ff_txfullclk" 200.000000 MHz ;\r
+FREQUENCY NET "THE_RICH_TRB/THE_MEDIA_INTERFACE/ff_txhalfclk" 100.000000 MHz ;\r
+\r
+REGION "MEDIA_INTERFACE_REGION" "R9C100" 10 28 ;\r
+LOCATE UGROUP "THE_RICH_TRB/THE_MEDIA_INTERFACE/MEDIA_INTERFACE_group" REGION "MEDIA_INTERFACE_REGION" ;\r
+\r
+######################################################################\r
+# PLL ADC0: 40MHz\r
+######################################################################\r
+LOCATE COMP "THE_ADC0_HANDLER/THE_ADC_PLL/PLLDINST_0" SITE "SPLL_R67C1" ;\r
+\r
+PERIOD PORT "ADC0_LCLK" 4.1666 ns ;\r
+USE PRIMARY PURE NET "ADC0_LCLK_c" ;\r
+USE EDGE NET "ADC0_LCLK_c" ;\r
+\r
+# Input setup\r
+DEFINE PORT GROUP "ADC0_INPUT" "ADC0_OUT*" "ADC0_ADCLK*" ;\r
+INPUT_SETUP GROUP "ADC0_INPUT" 0.600000 ns HOLD 0.600000 ns CLKPORT "ADC0_LCLK" ;\r
+\r
+# Reconstructed clock\r
+FREQUENCY NET "THE_ADC0_HANDLER/clk40m" 40.000000 MHz ;\r
+USE PRIMARY DCS NET "THE_ADC0_HANDLER/clk40m" ;\r
+\r
+# 240MHz ADC0 regions (namely ser2par for DDR data stream)\r
+REGION "ADC0_REGION" "R59C2" 46 4 ;\r
+LOCATE UGROUP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;\r
+LOCATE UGROUP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;\r
+LOCATE UGROUP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;\r
+LOCATE UGROUP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;\r
+\r
+######################################################################\r
+# PLL ADC1: 40MHz\r
+######################################################################\r
+LOCATE COMP "THE_ADC1_HANDLER/THE_ADC_PLL/PLLDINST_0" SITE "SPLL_R49C1" ;\r
+\r
+PERIOD PORT "ADC1_LCLK" 4.1666 ns ;\r
+USE PRIMARY PURE NET "ADC1_LCLK_c" ;\r
+USE EDGE NET "ADC1_LCLK_c" ;\r
+\r
+# Input setup\r
+DEFINE PORT GROUP "ADC1_INPUT" "ADC1_OUT*" "ADC1_ADCLK*" ;\r
+INPUT_SETUP GROUP "ADC1_INPUT" 0.600000 ns HOLD 0.600000 ns CLKPORT "ADC1_LCLK" ;\r
+\r
+# Reconstructed clock\r
+FREQUENCY NET "THE_ADC1_HANDLER/clk40m" 40.000000 MHz ;\r
+USE PRIMARY DCS NET "THE_ADC1_HANDLER/clk40m" ;\r
+\r
+# 240MHz ADC1 regions (namely ser2par for DDR data stream)\r
+REGION "ADC1_REGION" "R9C2" 49 4 ;\r
+LOCATE UGROUP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;\r
+LOCATE UGROUP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;\r
+LOCATE UGROUP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;\r
+LOCATE UGROUP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;\r
+\r
+######################################################################\r
+# SerDes URC\r
+# SerDes\r
+######################################################################\r
+LOCATE COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/PCSC_INST" SITE "URPCS" ;\r
+\r
+\r
+\r
--- /dev/null
+ Lattice Mapping Report File for Design 'adcmv3'
+
+Design Information
+------------------
+
+Command line: /usr/local/opt/synplify/8/isptools/ispfpga/bin/lin/map
+ -noinferGSR -a LATTICEECP2M -p LFE2M100E -t FPBGA900 -s 6 adcmv3.ngd -o
+ adcmv3_map.ncd -mp adcmv3.mrp adcmv3.lpf -tdm -td_pack
+Target Vendor: LATTICE
+Target Device: LFE2M100EFPBGA900
+Target Speed: 6
+Mapper: ep5m00, version: ispLever_v8.0_PROD_Build (41)
+Mapped on: 06/14/10 22:12:44
+
+Design Summary
+--------------
+
+ Number of registers: 14733
+ PFU registers: 14702
+ PIO registers: 31
+ Number of SLICEs: 13874 out of 47376 (29%)
+ SLICEs(logic/ROM): 13499 out of 38412 (35%)
+ SLICEs(logic/ROM/RAM): 375 out of 8964 (4%)
+ As RAM: 375 out of 8964 (4%)
+ As Logic/ROM: 0 out of 8964 (0%)
+ Number of logic LUT4s: 11205
+ Number of distributed RAM: 375 (750 LUT4s)
+ Number of ripple logic: 3979 (7958 LUT4s)
+ Number of shift registers: 0
+ Total number of LUT4s: 19913
+ Number of PIO sites used: 140 out of 416 (34%)
+ Number of PIO sites used for single ended IOs: 82
+ Number of PIO sites used for differential IOs: 58 (represented by 29 PIO
+ comps in NCD)
+ Number of IDDR/ODDR/TDDR cells used: 28
+ Number of IDDR cells: 18
+ Number of ODDR cells: 10
+ Number of TDDR cells: 0
+ Number of PIO using at least one IDDR/ODDR/TDDR: 28 (26 differential)
+ Number of PIO using IDDR only: 18 (18 differential)
+ Number of PIO using ODDR only: 10 (8 differential)
+ Number of PIO using TDDR only: 0 (0 differential)
+ Number of PIO using IDDR/ODDR: 0 (0 differential)
+ Number of PIO using IDDR/TDDR: 0 (0 differential)
+ Number of PIO using ODDR/TDDR: 0 (0 differential)
+ Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential)
+ Number of PIO FIXEDDELAY: 0
+ Number of PCS (SerDes): 1 out of 4 (25%) with bonded PIO sites
+ Number of DQSDLLs: 0 out of 2 (0%)
+ Number of PLLs: 2 out of 8 (25%)
+ Number of DLLs: 1 out of 2 (50%)
+ Number of block RAMs: 143 out of 288 (50%)
+ Number of CLKDIVs: 0 out of 2 (0%)
+ Number of GSRs: 0 out of 1 (0%)
+ JTAG used : No
+ Readback used : No
+ Oscillator used : No
+ Startup used : No
+ Notes:-
+ 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+
+ Page 1
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ distributed RAMs) + 2*(Number of ripple logic)
+ 2. Number of logic LUT4s does not include count of distributed RAM and
+ ripple logic.
+
+ Number Of Mapped DSP Components:
+ --------------------------------
+ MULT36X36B 0
+ MULT18X18B 0
+ MULT18X18MACB 0
+ MULT18X18ADDSUBB 0
+ MULT18X18ADDSUBSUMB 0
+ MULT9X9B 0
+ MULT9X9ADDSUBB 0
+ MULT9X9ADDSUBSUMB 0
+ --------------------------------
+ Number of Used DSP Sites: 0 out of 336 (0 %)
+ Number of clocks: 11
+ Net GND: 9 loads, 9 rising, 0 falling (Driver: GND )
+ Net clk_adc: 2 loads, 2 rising, 0 falling (Driver: THE_40M_PLL/PLLDInst_0 )
+ Net CLK100M_c: 20 loads, 20 rising, 0 falling (Driver: PIO CLK100M )
+ Net clk_apv_c: 2009 loads, 2009 rising, 0 falling (Driver:
+ THE_40M_PLL/PLLDInst_0 )
+ Net cts_clk40m: 1 loads, 1 rising, 0 falling (Driver:
+ THE_SYNC_PLL/PLLDInst_0 )
+ Net sysclk_c: 6899 loads, 6899 rising, 0 falling (Driver:
+ THE_100M_DLL/dll_100m_0_0 )
+ Net adc1_iodelay_0: 9 loads, 9 rising, 0 falling (Driver:
+ THE_SLAVE_BUS/THE_SPI_ADC1_MASTER/adc_ctrl_data_4 )
+ Net adc0_iodelay_0: 9 loads, 9 rising, 0 falling (Driver:
+ THE_SLAVE_BUS/THE_SPI_ADC0_MASTER/adc_ctrl_data_4 )
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/ff_txfullclk:
+ 1 loads, 1 rising, 0 falling (Driver:
+ THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/PCSC_INST )
+ Net ADC0_LCLK_c: 280 loads, 280 rising, 0 falling (Driver: PIO ADC0_LCLK )
+ Net ADC1_LCLK_c: 280 loads, 280 rising, 0 falling (Driver: PIO ADC1_LCLK )
+ Number of Clock Enables: 430
+ Net div_done_Q_0: 6 loads, 5 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/N_21: 1 loads, 1
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/STATE_10: 1 loads,
+ 1 LSLICEs
+ Net THE_RESET_HANDLER_final_reset_fast_1: 49 loads, 49 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/N_27: 1 loads, 1
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/N_5_i_2: 46 loads,
+ 46 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/N_5_i_1: 47 loads,
+ 47 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/N_5_i: 46 loads, 46
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/timecounter_16: 1
+ loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/N_46: 1 loads, 1
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/N_817: 1 loads, 1
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/N_20: 9 loads, 9
+
+ Page 2
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ LSLICEs
+ Net
+ THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/ram_addr_2_sqmuxa_i: 2
+ loads, 2 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/N_39: 1 loads, 1
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_GOOD_TEST_REG/store_rd: 16 loads, 16 LSLICEs
+ Net THE_SLAVE_BUS/THE_GOOD_TEST_REG/store_wr: 16 loads, 16 LSLICEs
+ Net THE_SLAVE_BUS/THE_ADC1_SNOOPER/N_86_i: 6 loads, 6 LSLICEs
+ Net THE_SLAVE_BUS/THE_ADC1_SNOOPER/store_rd: 13 loads, 13 LSLICEs
+ Net THE_SLAVE_BUS/THE_ADC1_SNOOPER/store_wr: 3 loads, 3 LSLICEs
+ Net THE_SLAVE_BUS/THE_ADC0_SNOOPER/N_86_i: 6 loads, 6 LSLICEs
+ Net THE_SLAVE_BUS/THE_ADC0_SNOOPER/store_rd: 13 loads, 13 LSLICEs
+ Net THE_SLAVE_BUS/THE_ADC0_SNOOPER/store_wr: 3 loads, 3 LSLICEs
+ Net THE_SLAVE_BUS/THE_PLL_CTRL_REG/store_rd: 15 loads, 15 LSLICEs
+ Net THE_SLAVE_BUS/THE_PLL_CTRL_REG/store_wr: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_TRG_CTRL_REG/store_rd: 16 loads, 16 LSLICEs
+ Net THE_SLAVE_BUS/THE_TRG_CTRL_REG/store_wr: 16 loads, 16 LSLICEs
+ Net THE_SLAVE_BUS/THE_ADC_LVL_REG/store_rd: 16 loads, 16 LSLICEs
+ Net THE_SLAVE_BUS/THE_ADC_LVL_REG/store_wr: 16 loads, 16 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_0: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_1: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_2: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_3: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_4: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_5: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_6: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_7: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_8: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_9: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_10: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_11: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_12: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_13: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_14: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_wr_15: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS_THE_SPI_ADC1_MASTER_THE_SPI_REAL_SLIM_N_103_i: 8 loads, 7
+ LSLICEs
+ Net div_done_Q_1: 6 loads, 5 LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_ADC1_MASTER/un1_start_in: 4 loads, 4 LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_ADC1_MASTER/THE_SPI_REAL_SLIM/N_1860_i: 1 loads,
+ 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_ADC1_MASTER/store_rd: 9 loads, 9 LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_ADC1_MASTER/store_wr: 9 loads, 9 LSLICEs
+ Net THE_SLAVE_BUS_THE_SPI_ADC0_MASTER_THE_SPI_REAL_SLIM_N_103_i: 8 loads, 7
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_ADC0_MASTER/un1_start_in: 4 loads, 4 LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_ADC0_MASTER/THE_SPI_REAL_SLIM/N_1927_i: 1 loads,
+ 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_ADC0_MASTER/store_rd: 9 loads, 9 LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_ADC0_MASTER/store_wr: 9 loads, 9 LSLICEs
+ Net tx_ena_RNI4FDH: 9 loads, 8 LSLICEs
+ Net div_done_Q: 16 loads, 15 LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_MASTER/un1_start_in: 20 loads, 20 LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/N_1159_i: 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS_THE_SPI_MASTER_THE_SPI_SLIM_THE_RX_SHIFT_AND_BITCOUNT_un1
+
+ Page 3
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ 7_clk_en: 5 loads, 4 LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/N_2673_i: 4 loads, 4 LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/un19_clk_en_i: 2 loads, 2
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/N_1157_i: 4 loads, 4 LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_MASTER/store_rd: 16 loads, 16 LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_MASTER/spi_startc: 16 loads, 16 LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_MASTER/un13_store_wr: 4 loads, 4 LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/THE_I2C_SENDB/shift_i: 5
+ loads, 5 LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/r_scl_Q: 4 loads, 4 LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/THE_I2C_SENDB/N_2401_i: 6
+ loads, 6 LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/N_386_i: 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/N_310_i: 4 loads, 4 LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/un1_CURRENT_STATE_11_i_a2_i:
+ 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/un1_CURRENT_STATE_8_i_a2_i: 1
+ loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/un1_CURRENT_STATE_9_i_a2_i: 1
+ loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/N_11: 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/N_9: 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/un1_CURRENT_STATE_7_i_a2_i: 1
+ loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/SDA_OUT_RNO_0: 1 loads, 1
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/SCL_OUT_RNO_0: 1 loads, 1
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/store_rd: 13 loads, 13 LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/store_wr: 15 loads, 15 LSLICEs
+ Net THE_SLAVE_BUS/THE_BUS_HANDLER/N_1554_i: 5 loads, 5 LSLICEs
+ Net THE_SLAVE_BUS/THE_BUS_HANDLER/N_4_i: 23 loads, 23 LSLICEs
+ Net regio_write_ack: 16 loads, 16 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/mov
+ e_b2_buffer: 13 loads, 13 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/N_3
+ 60_i: 10 loads, 10 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/ARBITER/N_4_i: 7 loads, 7
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/next_demux_dr_0_sqmuxa: 2
+ loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/N_69:
+ 4 loads, 4 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/N_18_
+ 0_i: 1 loads, 1 LSLICEs
+ Net
+ THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/N_8_0: 4
+ loads, 4 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i: 9 loads, 9 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1
+ wire_onewire_interface/next_state65: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1
+ wire_onewire_interface/N_284_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1
+ wire_onewire_interface/un8_recv_bit_ready: 9 loads, 9 LSLICEs
+
+ Page 4
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1
+ wire_onewire_interface/un1_next_send_rom_0_sqmuxa_i_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1
+ wire_onewire_interface/N_281_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1
+ wire_onewire_interface/N_280_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1
+ wire_onewire_interface/N_267_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1
+ wire_onewire_interface/N_279_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1
+ wire_onewire_interface/buf_TEMP_OUT_0_sqmuxa: 6 loads, 6 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /the_addresses/sending_state_0_sqmuxa: 8 loads, 8 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /the_addresses/sending_state_2_sqmuxa_1_i: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /ADR_READ_IN: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /the_addresses/un1_recv_set_address_0_sqmuxa: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /the_addresses/N_365_i: 4 loads, 4 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /N_5: 8 loads, 8 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /N_8: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /N_1572_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /N_1037_i: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /N_27: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /un1_next_nomoredata_0_sqmuxa_2_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /N_936_li: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /N_1575_i: 8 loads, 8 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /N_46: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /N_1555_i: 17 loads, 17 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /REGISTERS_OUT_write_enable_0: 16 loads, 16 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /COMMON_REGISTERS_OUT_write_enable_2: 17 loads, 17 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /COMMON_REGISTERS_OUT_write_enable_1: 16 loads, 16 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /N_851_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /N_1556_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the
+ _ipudata_apl/N_1614_i: 16 loads, 16 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the
+ _ipudata_apl/state_1: 1 loads, 1 LSLICEs
+
+ Page 5
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the
+ _ipudata_apl/N_1624_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the
+ _ipudata_apl/state_1_sqmuxa_2: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the
+ _ipudata_apl/state_s0_0_a2_0_a2: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the
+ _ipudata_apl/buf_INFORMATION_1_sqmuxa: 4 loads, 4 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the
+ _ipudata_apl/buf_NUMBER_1_sqmuxa: 8 loads, 8 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the
+ _ipudata_apl/state_RNI9V981_1: 9 loads, 9 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the
+ _ipudata_apl/N_1623_i: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the
+ _ipudata_apl/N_1618_i: 8 loads, 8 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_t
+ rigger_apl/N_11: 3 loads, 3 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_t
+ rigger_apl/buf_INT_DATAREADY_OUT_RNILIED: 5 loads, 5 LSLICEs
+ Net lvl1_trg_release: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_t
+ rigger_apl/seqnrce_0: 4 loads, 4 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_t
+ rigger_apl/int_packet_num_in: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_t
+ rigger_apl/N_1435_i: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_t
+ rigger_apl/next_TRG_RECEIVED_OUT_0_sqmuxa_i_s: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_t
+ rigger_apl/next_TRG_NUMBER_OUT_1_sqmuxa: 8 loads, 8 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_t
+ rigger_apl/next_TRG_INFORMATION_OUT_1_sqmuxa: 6 loads, 6 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_t
+ rigger_apl/reg_TRG_INFORMATION_OUTce_8: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/wren_i: 6 loads, 5 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/rden_i: 6 loads, 5 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/wren_i: 6 loads, 5 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/rden_i: 6 loads, 5 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/SBUF_TO_APL2/move_b2_buffer: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/SBUF_TO_APL2/N_152_i: 3 loads, 3 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/SBUF_TO_APL/gen_version_0_sbuf/move_b2_buffer: 10 loads, 10
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/SBUF_TO_APL/gen_version_0_sbuf/N_317_i: 10 loads, 10 LSLICEs
+
+ Page 6
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/SBUF/gen_version_0_sbuf/move_b2_buffer: 9 loads, 9 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/SBUF/gen_version_0_sbuf/N_317_i: 11 loads, 11 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/apl_to_buf_REPLY_READ_i_2_i_3: 1
+ loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/update_registered_header_1_sqmuxa: 22 loads, 22 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/un1_fifo_to_apl_long_packet_num_out: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/last_fifo_to_apl_read: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/un6_send_trm_wrong_addr_i: 17 loads, 17 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/next_last_fifo_to_apl_read: 9 loads, 9 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/N_884_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/N_864_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PAS
+ SIVE_API/un10_current_fifo_to_apl_packet_type: 8 loads, 8 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/wren_i: 7 loads, 6 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/rden_i: 6 loads, 5 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/wren_i: 6 loads, 5 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/rden_i: 6 loads, 5 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/SBUF_TO_APL2/move_b2_buffer: 3 loads, 3 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/SBUF_TO_APL2/N_109_i: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/SBUF_TO_APL/gen_version_0_sbuf/move_b2_buffer: 10 loads, 10
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/SBUF_TO_APL/gen_version_0_sbuf/N_317_i: 10 loads, 10 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/SBUF/gen_version_0_sbuf/move_b2_buffer: 9 loads, 9 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/SBUF/gen_version_0_sbuf/N_317_i: 11 loads, 11 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/apl_to_buf_REPLY_READ_i_2_i_1: 1
+ loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/N_778_i: 9 loads, 9 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/last_fifo_to_apl_read: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/N_1655_i: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+
+ Page 7
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ SIVE_API/N_451_li_0: 30 loads, 30 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/next_last_fifo_to_apl_read: 9 loads, 9 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/N_770_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/fifo_to_apl_read_before_RNO: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/un10_current_fifo_to_apl_packet_type: 8 loads, 8 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/move_b2_buffer: 10 loads, 10
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/N_360_i: 11 loads, 11 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/TRANSMITTED_BUFFERS_2_sqmuxa_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/transfer_counter_0_sqmuxa: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/un4_buf_int_read_out: 9 loads, 9 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/move_b2_buffer: 10
+ loads, 10 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/N_359_i: 10 loads, 10
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/THE_FIFO/fifo/wren_i: 6 loads, 5 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/THE_FIFO/fifo/rden_i: 6 loads, 5 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/THE_FIFO/fifo/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/un24_fifo_long_packet_num_out: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/fifo_valid_read: 10 loads, 10 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/next_rec_buffer_size_out_0_sqmuxa: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/move_b2_buffer: 11 loads, 11
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/N_360_i: 11 loads, 11 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/TRANSMITTED_BUFFERS_2_sqmuxa_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/transfer_counter_0_sqmuxa: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/un4_buf_int_read_out: 9 loads, 9 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/move_b2_buffer: 10
+ loads, 10 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/N_317_i: 10 loads, 10
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_
+
+ Page 8
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ THE_IBUF/THE_FIFO/fifo/wren_i: 6 loads, 5 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/THE_FIFO/fifo/rden_i: 7 loads, 6 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/THE_FIFO/fifo/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/un24_fifo_long_packet_num_out: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/fifo_valid_read: 10 loads, 10 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/next_rec_buffer_size_out_0_sqmuxa: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/move_b2_buffer: 10 loads, 10
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/N_317_i: 11 loads, 11 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/N_36: 8 loads, 8 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/un1_current_EOB_word_2_sqmuxa_4_i_a2_1_RNII0EK_0: 2 loads, 2
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/un1_reg_int_read_out_RNI7E9K: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/un4_buf_int_read_out: 5 loads, 5 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/N_535_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/N_17: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/TRANSMITTED_BUFFERS_2_sqmuxa_i_o2_RNI1VV81: 4 loads, 4
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/current_buffer_state_1:
+ 10 loads, 10 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/move_b2_buffer: 10
+ loads, 10 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/THE_FIFO/fifo/wren_i: 6 loads, 5 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/THE_FIFO/fifo/rden_i: 6 loads, 5 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/THE_FIFO/fifo/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/N_417_i: 8 loads, 8 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/un24_fifo_long_packet_num_out: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/fifo_valid_read: 10 loads, 10 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/N_24: 2 loads, 2 LSLICEs
+ Net
+ THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/wren_i:
+ 19 loads, 18 LSLICEs
+ Net
+
+ Page 9
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/rden_i:
+ 19 loads, 18 LSLICEs
+ Net
+ THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/wren_i:
+ 19 loads, 18 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/fifo_rx_empty: 19 loads, 18 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/reset_i: 10 loads, 10 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/N_491_i: 15 loads, 15
+ LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/N_517_i: 1 loads, 1
+ LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/N_9: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/reset_word_cnt_1_sqmuxa_i: 3 loads, 3
+ LSLICEs
+ Net THE_APV_TRGCTRL/atc_eds_we: 20 loads, 20 LSLICEs
+ Net THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/un1_accept: 6 loads, 6 LSLICEs
+ Net THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/N_267_i: 1 loads, 1 LSLICEs
+ Net THE_ADC0_CROSSOVER/THE_CROSSOVER/wren_i: 9 loads, 9 LSLICEs
+ Net THE_ADC0_CROSSOVER/THE_CROSSOVER/rden_i: 57 loads, 57 LSLICEs
+ Net THE_ADC0_HANDLER/un1_THE_ADC_6_7_CH_1_13: 24 loads, 24 LSLICEs
+ Net THE_ADC0_HANDLER/un1_THE_ADC_0_1_CH_1_12: 24 loads, 24 LSLICEs
+ Net THE_ADC0_HANDLER/realstore_1: 48 loads, 48 LSLICEs
+ Net THE_ADC1_CROSSOVER/THE_CROSSOVER/rden_i: 57 loads, 57 LSLICEs
+ Net THE_ADC1_CROSSOVER/THE_CROSSOVER/wren_i: 9 loads, 9 LSLICEs
+ Net THE_ADC1_HANDLER/store_b_Q: 24 loads, 24 LSLICEs
+ Net THE_ADC1_HANDLER/store_a_Q: 24 loads, 24 LSLICEs
+ Net THE_ADC1_HANDLER/realstore_1: 48 loads, 48 LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_11: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_9: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_8: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_15: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_14: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_12: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_13: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_10: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/N_1954_i: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/N_1951_i: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/N_1948_i: 1 loads, 1
+
+ Page 10
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/N_1945_i: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/N_1942_i: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/N_1939_i: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/N_1936_i: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/N_1933_i: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_0: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_6: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_7: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_2: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_5: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_1: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_3: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/apv_analog_4: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/N_1930_i: 1 loads, 1
+
+ Page 11
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/N_1927_i: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/N_1924_i: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/N_1921_i: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/N_1918_i: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/N_1915_i: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/frame_analog_RNO_0: 1
+ loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/inc_tc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/inc_lc_sm: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/N_1909_i: 1 loads, 1
+
+ Page 12
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/delay_store_7: 5 loads, 5
+ LSLICEs
+ Net THE_PED_CORR_STAGE/buf_addr_done: 1 loads, 1 LSLICEs
+ Net THE_IPU_STAGE/ld_todo_4: 9 loads, 9 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/wren_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/rden_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/wren_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/rden_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/wren_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/rden_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/wren_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/rden_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/wren_i: 7 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/rden_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/wren_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/rden_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/wren_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/rden_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/wren_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/rden_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/wren_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/rden_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/wren_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/rden_i: 7 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/fcnt_en: 7 loads, 7 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/wren_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/rden_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/wren_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/rden_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/wren_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/rden_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/wren_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/rden_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/wren_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/rden_i: 6 loads, 5 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/wren_i: 7 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/rden_i: 7 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/rden_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+
+ Page 13
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/rden_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/rden_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/rden_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/rden_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/rden_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/rden_i: 10 loads, 7 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/rden_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/rden_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/rden_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/rden_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/rden_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/rden_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/rden_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/rden_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/wren_i: 9 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/rden_i: 10 loads, 7 LSLICEs
+ Net THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/fcnt_en: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_65_0_i: 16 loads, 16 LSLICEs
+ Net THE_IPU_STAGE/N_2676_i: 16 loads, 16 LSLICEs
+ Net THE_REBOOT_HANDLER/N_9_i: 9 loads, 9 LSLICEs
+ Number of LSRs: 569
+ Net GND: 12 loads, 0 LSLICEs
+ Net THE_RAW_BUF_STAGE_reset_all: 960 loads, 960 LSLICEs
+ Net THE_RESET_HANDLER_final_reset_iso_1: 1679 loads, 1668 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_16_2: 1
+ loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_15_2: 1
+ loads, 1 LSLICEs
+
+ Page 14
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_14_2: 1
+ loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_13_2: 1
+ loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_12_2: 1
+ loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_11_2: 1
+ loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_10_2: 1
+ loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_9_2: 1 loads,
+ 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_8_2: 1 loads,
+ 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_7_2: 1 loads,
+ 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_6_2: 1 loads,
+ 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_5_2: 1 loads,
+ 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_4_2: 1 loads,
+ 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_3_2: 1 loads,
+ 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_2_2: 1 loads,
+ 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_1_2: 1 loads,
+ 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/input_0_2: 1 loads,
+ 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/wait_pulse: 9
+ loads, 9 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/presence_reset: 9
+ loads, 9 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/mux_wrs_i: 1 loads,
+ 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/reset_bitcounter_0_
+ 0_i_0: 4 loads, 4 LSLICEs
+ Net THE_RESET_HANDLER_final_reset_1: 74 loads, 0 LSLICEs
+ Net THE_SLAVE_BUS/slv_data_wr_3: 2 loads, 2 LSLICEs
+ Net THE_SLAVE_BUS/THE_GOOD_TEST_REG/CURRENT_STATE_nss_2_i_4: 1 loads, 1
+ LSLICEs
+ Net THE_APV_TRGCTRL_apv_clk_rst_r14: 4 loads, 4 LSLICEs
+ Net THE_APV_TRGCTRL_apv_clk_rst_r1: 7 loads, 7 LSLICEs
+ Net THE_SLAVE_BUS/THE_ADC1_SNOOPER/CURRENT_STATE_nss_1_i_4: 1 loads, 1
+ LSLICEs
+ Net THE_APV_TRGCTRL_apv_clk_rst_r13: 4 loads, 4 LSLICEs
+ Net THE_SLAVE_BUS/THE_ADC0_SNOOPER/CURRENT_STATE_nss_1_i_4: 1 loads, 1
+ LSLICEs
+ Net BP_LED_c: 1 loads, 1 LSLICEs
+ Net adc0_valid: 1 loads, 1 LSLICEs
+ Net adc1_valid: 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_PLL_CTRL_REG/CURRENT_STATE_nss_2_i_2: 1 loads, 1
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_TRG_CTRL_REG/CURRENT_STATE_nss_2_i_4: 1 loads, 1
+ LSLICEs
+
+ Page 15
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_SLAVE_BUS/THE_ADC_LVL_REG/CURRENT_STATE_nss_2_i_4: 1 loads, 1
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_IPU_HANDLER_STATUS/CURRENT_STATE_nss_1_i_4: 1 loads,
+ 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_LVL1_RELEASE_STATUS/CURRENT_STATE_nss_1_i_4: 1 loads,
+ 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_FIFO_STATUS_BANK/CURRENT_STATE_nss_1_i_4: 1 loads, 1
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/adc_addr_3: 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/adc_addr_2: 3 loads, 3 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/adc_addr_1: 3 loads, 3 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/adc_addr_0: 6 loads, 6 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/reg_selc_11_i: 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/store_wr: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/CURRENT_STATE_nss_1_i_4: 1 loads, 1
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/inc_addr_txc_i_i: 1 loads, 1
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/phase: 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/un1_reset_in_0_i: 4 loads, 4
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/N_2298: 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_THR_MEM/un1_THE_THR_MEM_0_19: 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_THR_MEM/mem_0_2: 3 loads, 3 LSLICEs
+ Net THE_SLAVE_BUS/THE_THR_MEM/mem_0_1: 3 loads, 3 LSLICEs
+ Net THE_SLAVE_BUS/THE_THR_MEM/mem_0_0: 6 loads, 6 LSLICEs
+ Net THE_SLAVE_BUS/THE_THR_MEM/mem_selc_11_i: 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_THR_MEM/store_wr: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_THR_MEM/CURRENT_STATE_nss_1_i_4: 1 loads, 1 LSLICEs
+ Net buf_addr_0: 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_PED_MEM/un1_THE_PED_MEM_0_19: 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_PED_MEM/mem_0_2_0: 3 loads, 3 LSLICEs
+ Net THE_SLAVE_BUS/THE_PED_MEM/mem_0_1_0: 3 loads, 3 LSLICEs
+ Net THE_SLAVE_BUS/THE_PED_MEM/mem_0_0_0: 6 loads, 6 LSLICEs
+ Net THE_SLAVE_BUS/THE_PED_MEM/mem_selc_11_i: 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_PED_MEM/store_wr: 8 loads, 8 LSLICEs
+ Net THE_SLAVE_BUS/THE_PED_MEM/CURRENT_STATE_nss_1_i_4: 1 loads, 1 LSLICEs
+ Net THE_SLAVE_BUS/THE_BUS_HANDLER/DAT_WRITE_ACK_OUT_1_18_0_o4: 1 loads, 1
+ LSLICEs
+ Net THE_SLAVE_BUS/THE_BUS_HANDLER/N_118_i: 14 loads, 14 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r4: 6 loads, 6
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r0: 7 loads, 7
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r11: 8 loads, 8
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r3: 5 loads, 5
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r2: 3 loads, 3
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r1: 5 loads, 5
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/N_72:
+ 1 loads, 1 LSLICEs
+ Net
+ THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/N_30_i: 4
+
+ Page 16
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ loads, 4 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r20: 6 loads, 6
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r18: 8 loads, 8
+ LSLICEs
+ Net
+ THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/N_24_i: 2
+ loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r17: 4 loads, 4
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1
+ wire_onewire_interface/N_274_i: 4 loads, 4 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /rom_read_addr_2: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /rom_read_addr_1: 3 loads, 3 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/buf_APL_SEND_IN_3: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /un2_local_time_i: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /next_COMMON_CTRL_REG_STROBEc_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /N_6: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO
+ /COMMON_REGISTERS_OUT_write_enable_0: 17 loads, 17 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the
+ _ipudata_apl/N_7: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the
+ _ipudata_apl/state_3_sqmuxa: 1 loads, 1 LSLICEs
+ Net ipu_start_readout: 3 loads, 3 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/buf_APL_SEND_IN_1: 2 loads, 2 LSLICEs
+ Net lvl1_trg_received: 1 loads, 1 LSLICEs
+ Net THE_RESET_HANDLER_final_reset_1_1: 53 loads, 47 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/N_782_i: 10 loads, 10 LSLICEs
+ Net THE_RESET_HANDLER_final_reset_2_1: 48 loads, 46 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/endpoint_reached_1_iv_0_a2_0: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PAS
+ SIVE_API/next_last_fifo_to_apl_readc_i_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/N_48_i_i: 4 loads, 4 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r24: 8 loads, 8
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r25: 5 loads, 5
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r23: 9 loads, 9
+ LSLICEs
+ Net THE_RICH_TRB/med_stat_op_r1_14: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r21: 6 loads, 6
+ LSLICEs
+ Net THE_RICH_TRB/med_stat_op_r14_14: 5 loads, 5 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/N_356: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_2: 30 loads, 26
+ LSLICEs
+ Net THE_RICH_TRB/med_stat_op_r2_14: 1 loads, 1 LSLICEs
+
+ Page 17
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/N_20_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r22: 9 loads, 9
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r19: 4 loads, 4
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/buf_STAT_REPLY_OBUF_DEBUG_112: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/med_stat_op_r12_14: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYO
+ BUF1_REPLYOBUF/N_48_i_i: 4 loads, 4 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r16: 5 loads, 5
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r12: 5 loads, 5
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r15: 9 loads, 9
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r7: 8 loads, 8
+ LSLICEs
+ Net THE_RICH_TRB/med_stat_op_r13_14: 5 loads, 5 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/N_314: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_1: 31 loads, 29
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/N_419_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r14: 4 loads, 4
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r13: 9 loads, 9
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r10: 4 loads, 4
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/buf_STAT_INIT_BUFFER_37: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r9: 6 loads, 6
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r6: 5 loads, 5
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/N_357: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r8: 6 loads, 6
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r5: 4 loads, 4
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_
+ THE_IBUF/buf_STAT_INIT_BUFFER_5: 2 loads, 2 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/reset_no_link_i_i_r26: 9 loads, 9
+ LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/N_1260_i: 3 loads, 3 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/fb: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_UNIFIED_ENDPOINT/last_LVL1_TRG_RECEIVED_OUT: 1 loads,
+ 1 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/N_1995_i: 62 loads, 60 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/N_1939_1_i: 62 loads, 60 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/lane_rst: 2 loads, 0 LSLICEs
+ Net SD_TXDIS_c: 1 loads, 0 LSLICEs
+
+ Page 18
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/N_429_1: 17 loads, 17
+ LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/ce_cctrc_i: 1 loads, 1
+ LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_2: 2 loads,
+ 2 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/next_lane_rst_tz: 1 loads,
+ 1 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/N_390: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/NEXT_STATE_1_sqmuxa: 1
+ loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/N_382: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/reset_i: 31 loads, 31 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/N_364: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/rx_allows_i: 1 loads, 1
+ LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/rst_cctr: 1 loads, 1
+ LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/med_stat_op_1: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/fb: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/fb_i: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/last_fifo_tx_empty: 1 loads, 1 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/N_7_i: 1 loads, 1 LSLICEs
+ Net reset_by_trb: 4 loads, 4 LSLICEs
+ Net THE_RICH_TRB/THE_MEDIA_INTERFACE/N_3_0_i: 1 loads, 1 LSLICEs
+ Net THE_APV_TRGCTRL/apv_clk_rst_r2: 10 loads, 10 LSLICEs
+ Net THE_APV_TRGCTRL/apv_clk_rst_r0: 5 loads, 5 LSLICEs
+ Net THE_APV_TRGCTRL/apv_clk_rst_r4: 6 loads, 6 LSLICEs
+ Net THE_APV_TRGCTRL/apv_clk_rst_r6: 4 loads, 4 LSLICEs
+ Net THE_APV_TRGCTRL/apv_clk_rst_r3: 5 loads, 5 LSLICEs
+ Net THE_APV_TRGCTRL/apv_clk_rst_r8: 6 loads, 6 LSLICEs
+ Net THE_APV_TRGCTRL/apv_clk_rst_r9: 4 loads, 4 LSLICEs
+ Net THE_APV_TRGCTRL/apv_clk_rst_r5: 5 loads, 5 LSLICEs
+ Net THE_APV_TRGCTRL/apv_clk_rst_r12: 4 loads, 4 LSLICEs
+ Net THE_APV_TRGCTRL/apv_clk_rst_r7: 5 loads, 5 LSLICEs
+ Net THE_APV_TRGCTRL/apv_clk_rst_r11: 7 loads, 7 LSLICEs
+ Net THE_APV_TRGCTRL/apv_clk_rst_r10: 5 loads, 5 LSLICEs
+ Net THE_APV_TRGCTRL/atc_eds_we: 10 loads, 10 LSLICEs
+ Net eds_data_2: 17 loads, 17 LSLICEs
+ Net THE_APV_TRGCTRL/THE_EDS_BUF/eds_buf_level_3: 1 loads, 1 LSLICEs
+ Net THE_APV_TRGCTRL/THE_EDS_BUF/eds_availables_i: 1 loads, 1 LSLICEs
+ Net THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/N_296_i: 6 loads, 6 LSLICEs
+ Net THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/N_295_i: 6 loads, 6 LSLICEs
+ Net THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/N_294_i: 1 loads, 1 LSLICEs
+ Net THE_ADC_0_SELECT_reset: 32 loads, 32 LSLICEs
+ Net THE_ADC0_CROSSOVER/THE_CROSSOVER/wren_i: 24 loads, 24 LSLICEs
+ Net THE_ADC0_CROSSOVER/reset: 81 loads, 81 LSLICEs
+ Net THE_ADC0_HANDLER/un1_THE_ADC_6_7_CH_1_13: 1 loads, 1 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r17: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r16: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r15: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r14: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r13: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r12: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r11: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r10: 3 loads, 3 LSLICEs
+
+ Page 19
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_ADC0_HANDLER/reset_r9: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r8: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r7: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r6: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r5: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r4: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r3: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r2: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r1: 3 loads, 3 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r0: 4 loads, 4 LSLICEs
+ Net THE_ADC0_HANDLER/reset_r18: 4 loads, 4 LSLICEs
+ Net THE_ADC0_HANDLER/synccounter_0: 1 loads, 1 LSLICEs
+ Net THE_ADC0_HANDLER/sync_highc_i: 1 loads, 1 LSLICEs
+ Net THE_ADC0_HANDLER/swapcounter_Q_0: 1 loads, 1 LSLICEs
+ Net THE_ADC0_HANDLER/swap_highc_i: 1 loads, 1 LSLICEs
+ Net THE_ADC0_HANDLER/recstore_0: 2 loads, 2 LSLICEs
+ Net THE_ADC0_HANDLER/adc0_ce: 1 loads, 1 LSLICEs
+ Net THE_ADC0_HANDLER/bitcounter_Q_0: 3 loads, 3 LSLICEs
+ Net THE_ADC1_CROSSOVER/THE_CROSSOVER/wren_i: 24 loads, 24 LSLICEs
+ Net THE_ADC1_CROSSOVER/reset: 81 loads, 81 LSLICEs
+ Net THE_ADC1_HANDLER/store_b_Q: 1 loads, 1 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r17: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r16: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r15: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r14: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r13: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r12: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r11: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r10: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r9: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r8: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r7: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r6: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r5: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r4: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r3: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r2: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r1: 3 loads, 3 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r0: 4 loads, 4 LSLICEs
+ Net THE_ADC1_HANDLER/reset_r18: 4 loads, 4 LSLICEs
+ Net THE_ADC1_HANDLER/synccounter_0: 1 loads, 1 LSLICEs
+ Net THE_ADC1_HANDLER/sync_highc_i: 1 loads, 1 LSLICEs
+ Net THE_ADC1_HANDLER/swapcounter_Q_0_0: 1 loads, 1 LSLICEs
+ Net THE_ADC1_HANDLER/swap_highc_i: 1 loads, 1 LSLICEs
+ Net THE_ADC1_HANDLER/recstore_0: 2 loads, 2 LSLICEs
+ Net THE_ADC1_HANDLER/adc1_ce: 1 loads, 1 LSLICEs
+ Net THE_ADC1_HANDLER/bitcounter_Q_0_0: 3 loads, 3 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/reset_all_3: 56 loads, 30 LSLICEs
+ Net buf_data_11_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/reset_all_4: 56 loads, 30 LSLICEs
+ Net THE_RAW_BUF_STAGE/reset: 240 loads, 240 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+
+ Page 20
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ LSLICEs
+ Net buf_data_9_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+ LSLICEs
+ Net buf_data_8_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+ LSLICEs
+ Net buf_data_15_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+ LSLICEs
+ Net buf_data_14_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+ LSLICEs
+ Net buf_data_12_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+ LSLICEs
+ Net buf_data_13_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+ LSLICEs
+ Net buf_data_10_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r24: 8 loads, 8 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r23: 8 loads, 8 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r22: 8 loads, 8 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r21: 8 loads, 8 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r20: 8 loads, 8 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r19: 8 loads, 8 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r18: 5 loads, 5 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r17: 8 loads, 8 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r16: 4 loads, 4 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r15: 2 loads, 2 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r14: 2 loads, 2 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r13: 2 loads, 2 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r12: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r11: 2 loads, 2 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r10: 2 loads, 2 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r9: 2 loads, 2 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r8: 2 loads, 2 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r7: 3 loads, 3 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r6: 2 loads, 2 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r5: 2 loads, 2 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r4: 2 loads, 2 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r3: 2 loads, 2 LSLICEs
+
+ Page 21
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_RAW_BUF_STAGE/N_65_r2: 2 loads, 2 LSLICEs
+ Net THE_RAW_BUF_STAGE/N_65_r1: 2 loads, 2 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_LOCK_SM/N_65_r0: 1
+ loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/N_1964_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/N_1965_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/reset_all_2: 32 loads, 20 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/N_1966_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/bit_low: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/bit_low: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/N_4: 4 loads, 4 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un20_reset_in_i: 4 loads,
+ 4 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/N_1971_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/N_1974_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/N_1975_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/bit_low: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/N_1976_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/N_1979_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/N_1980_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/N_1981_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/bit_low: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/N_1984_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/N_1985_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/N_1986_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/bit_low: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/N_1989_i: 4 loads, 4
+ LSLICEs
+
+ Page 22
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/N_1990_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/N_1991_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/bit_low: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/N_1994_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/N_1995_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/N_1996_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/bit_low: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/N_1999_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/N_2000_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/bit_low: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/N_2001_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+ LSLICEs
+ Net buf_data_0_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+ LSLICEs
+ Net buf_data_6_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+ LSLICEs
+ Net buf_data_7_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+ LSLICEs
+ Net buf_data_2_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+ LSLICEs
+ Net buf_data_5_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+ LSLICEs
+ Net buf_data_1_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+
+ Page 23
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+ LSLICEs
+ Net buf_data_3_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/adc_last_x: 3 loads, 3
+ LSLICEs
+ Net buf_data_4_26: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/apv_on: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/N_2012_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/N_2014_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/bit_low: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un17_reset_in_i_2: 4 loads,
+ 4 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/N_2017_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/N_2018_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/N_2019_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/bit_low: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/N_2022_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/N_2024_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/bit_low: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/N_5: 4 loads, 4 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/N_2027_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/N_2028_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/N_2029_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/bit_low: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/N_2032_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/N_2033_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/N_2034_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/bit_low: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/N_2037_i: 4 loads, 4
+ LSLICEs
+
+ Page 24
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/N_2039_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/bit_low: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un17_reset_in_i_1: 4 loads,
+ 4 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/N_2042_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/N_2044_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/bit_low: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un17_reset_in_i_0: 4 loads,
+ 4 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/N_2047_i: 4 loads, 4
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/N_2049_i: 2 loads, 2
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/bit_low: 1 loads, 1 LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/bit_high: 1 loads, 1
+ LSLICEs
+ Net THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un17_reset_in_i: 4 loads, 4
+ LSLICEs
+ Net THE_PED_CORR_STAGE/N_4295_i_r15: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4295_i_r14: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4295_i_r13: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4295_i_r12: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4295_i_r11: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4295_i_r10: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4295_i_r9: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4295_i_r8: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4295_i_r7: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4295_i_r6: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4295_i_r5: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4295_i_r4: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4295_i_r3: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4295_i_r2: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/N_4295_i_r1: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4295_i_r0: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4294_i_r15: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4294_i_r14: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4294_i_r13: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4294_i_r12: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4294_i_r11: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4294_i_r10: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4294_i_r9: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4294_i_r8: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4294_i_r7: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4294_i_r6: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4294_i_r5: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4294_i_r4: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4294_i_r3: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4294_i_r2: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/N_4294_i_r1: 7 loads, 7 LSLICEs
+
+ Page 25
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_PED_CORR_STAGE/N_4294_i_r0: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/N_4293_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_1887: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r2: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/un10_next_clip_min_i_a2_0_a2: 32 loads, 32 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r0: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/frame_ctr_error: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/frame_row_error: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/buffers_valid: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/buf_gooddata_1: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/N_4300_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r10: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r9: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/buf_gooddata_8: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/N_4305_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r3: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/buf_gooddata_2: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/N_4310_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r15: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/buf_gooddata_13: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/N_4315_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r7: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/buf_gooddata_6: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/N_4320_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r18: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r20: 4 loads, 4 LSLICEs
+ Net THE_PED_CORR_STAGE/buf_gooddata_15: 7 loads, 7 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/N_4325_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r1: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/buf_gooddata_0: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/N_4330_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r11: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/buf_gooddata_9: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/N_4335_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r14: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/buf_gooddata_12: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/N_4340_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r8: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/buf_gooddata_7: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/N_4345_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r6: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/buf_gooddata_5: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/N_4350_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r4: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+
+ Page 26
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_PED_CORR_STAGE/buf_gooddata_3: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/N_4355_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r13: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/buf_gooddata_11: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/N_4360_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r5: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/buf_gooddata_4: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/N_4365_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r12: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/buf_gooddata_10: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/N_4370_i: 8 loads, 8 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r17: 6 loads, 6 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r16: 4 loads, 4 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/bad_corrs_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/buf_gooddata_14: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_11_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_11_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_4_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_4_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_5_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_5_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_13_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_13_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_1_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_1_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_10_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_10_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_7_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_7_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_3_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_3_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_8_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_8_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_9_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_9_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_14_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_14_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_12_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_12_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_15_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_15_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_6_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_6_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_2_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_2_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_0_THE_BUF_TOC/N_178_i: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/GEN_TOC_0_THE_BUF_TOC/N_177_i: 2 loads, 2 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r21: 9 loads, 9 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4286_i_r19: 3 loads, 3 LSLICEs
+ Net THE_PED_CORR_STAGE/next_max_num_words_5_i_0_0_o2_0_10: 1 loads, 1
+ LSLICEs
+ Net THE_PED_CORR_STAGE/N_1234_i: 1 loads, 1 LSLICEs
+ Net THE_PED_CORR_STAGE/N_4287_i: 4 loads, 4 LSLICEs
+
+ Page 27
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Summary (cont)
+---------------------
+ Net THE_IPU_STAGE/un1_THE_IPU_STAGE_1_sn_63: 11 loads, 11 LSLICEs
+ Net THE_IPU_STAGE/reset_all_li_i_iso: 42 loads, 42 LSLICEs
+ Net THE_IPU_STAGE/reset_all_li_i_6: 58 loads, 44 LSLICEs
+ Net THE_IPU_STAGE/reset_all_li_i_8: 55 loads, 45 LSLICEs
+ Net THE_IPU_STAGE/reset_all_li_i_7: 55 loads, 47 LSLICEs
+ Net THE_IPU_STAGE/reset_all_li_i_9: 54 loads, 46 LSLICEs
+ Net THE_IPU_STAGE/reset_all_li_i_11: 56 loads, 48 LSLICEs
+ Net THE_IPU_STAGE/reset_all_li_i_5: 55 loads, 47 LSLICEs
+ Net THE_IPU_STAGE/reset_all_li_i: 55 loads, 47 LSLICEs
+ Net THE_IPU_STAGE/reset_all_li_i_10: 57 loads, 43 LSLICEs
+ Net THE_IPU_STAGE/reset_all_li_i_12: 56 loads, 46 LSLICEs
+ Net THE_IPU_STAGE/reset_all_li_i_4: 56 loads, 46 LSLICEs
+ Net THE_IPU_STAGE/reset_all_li_i_2: 59 loads, 45 LSLICEs
+ Net THE_IPU_STAGE/reset_all_li_i_1: 55 loads, 47 LSLICEs
+ Net THE_IPU_STAGE/reset_all_li_i_3: 56 loads, 48 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r15: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r14: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r13: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r12: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r11: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r10: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r9: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r8: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r7: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r6: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r5: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r4: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r3: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r2: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r1: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/N_2035_i_r0: 6 loads, 6 LSLICEs
+ Net THE_IPU_STAGE/un11_todo_list_sn: 1 loads, 1 LSLICEs
+ Net THE_RESET_HANDLER/async_sampler_5: 1 loads, 1 LSLICEs
+ Number of nets driven by tri-state buffers: 0
+ Top 10 highest fanout non-clock nets:
+ Net VCC: 3409 loads
+ Net THE_RESET_HANDLER_final_reset_iso_1: 1679 loads
+ Net THE_RAW_BUF_STAGE_reset_all: 961 loads
+ Net THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/adc_addr_3: 241 loads
+ Net THE_RAW_BUF_STAGE/reset: 240 loads
+ Net THE_RESET_HANDLER_final_reset_fast_1: 237 loads
+ Net THE_SLAVE_BUS/THE_PED_MEM/un1_THE_PED_MEM_0_19: 160 loads
+ Net THE_SLAVE_BUS/THE_THR_MEM/un1_THE_THR_MEM_0_19: 160 loads
+ Net apv_sync_1: 137 loads
+ Net THE_SLAVE_BUS/onewire_debug_1_29: 137 loads
+
+
+
+
+ Number of warnings: 3
+ Number of errors: 0
+
+Design Errors/Warnings
+----------------------
+
+WARNING: IO buffer missing for top level port BP_MODULE[3:0](3)...logic will be
+
+ Page 28
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Design Errors/Warnings (cont)
+-----------------------------
+ discarded.
+WARNING: IO buffer missing for top level port BP_SECTOR[3:0](3)...logic will be
+ discarded.
+WARNING: comp
+ THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/PCSC_INST site
+ assignment is not supported in pgroup. Moved out of the pgroup
+
+IO (PIO) Attributes
+-------------------
+
++---------------------+-----------+-----------+------------+------------+
+| IO Name | Direction | Levelmode | IO | FIXEDDELAY |
+| | | IO_TYPE | Register | |
++---------------------+-----------+-----------+------------+------------+
+| APV0_SDA | BIDIR | LVCMOS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| APV0A_CLK | OUTPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| CLK100M | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC0_OUT_7 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC0_OUT_6 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC0_OUT_5 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC0_OUT_4 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC0_OUT_3 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC0_OUT_2 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC0_OUT_1 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC0_OUT_0 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC0_ADCLK | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_OUT_7 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_OUT_6 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_OUT_5 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_OUT_4 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_OUT_3 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_OUT_2 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_OUT_1 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_OUT_0 | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_ADCLK | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+
+ Page 29
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+IO (PIO) Attributes (cont)
+--------------------------
+| U_SPI_SDO | INPUT | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| U_SPI_SDI | OUTPUT | LVTTL33 | OUT | |
++---------------------+-----------+-----------+------------+------------+
+| U_SPI_SCK | OUTPUT | LVTTL33 | OUT | |
++---------------------+-----------+-----------+------------+------------+
+| U_SPI_CS | OUTPUT | LVTTL33 | OUT | |
++---------------------+-----------+-----------+------------+------------+
+| APV1_1W_7 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| APV1_1W_6 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| APV1_1W_5 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| APV1_1W_4 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| APV1_1W_3 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| APV1_1W_2 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| APV1_1W_1 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| APV1_1W_0 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| APV0_1W_7 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| APV0_1W_6 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| APV0_1W_5 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| APV0_1W_4 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| APV0_1W_3 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| APV0_1W_2 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| APV0_1W_1 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| APV0_1W_0 | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| FPGA_LED_ADC_1 | OUTPUT | LVCMOS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| FPGA_LED_ADC_0 | OUTPUT | LVCMOS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| FPGA_LED_PLL | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| FPGA_LED_LINK | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| FPGA_LED_TXD | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| FPGA_LED_RXD | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| FPGA_LED_6 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| FPGA_LED_5 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+
+ Page 30
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+IO (PIO) Attributes (cont)
+--------------------------
+| FPGA_LED_4 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| FPGA_LED_3 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| BP_LED | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| BP_ONEWIRE | BIDIR | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| BP_SECTOR_2 | INPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| BP_SECTOR_1 | INPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| BP_SECTOR_0 | INPUT | LVCMOS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| BP_MODULE_2 | INPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| BP_MODULE_1 | INPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| BP_MODULE_0 | INPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADCM_ONEWIRE | BIDIR | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| SD_TXDIS | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| SD_LOS | INPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| SD_PRESENT | INPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| UC_REBOOT | OUTPUT | LVTTL33 | OUT | |
++---------------------+-----------+-----------+------------+------------+
+| UC_RESET | INPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_LCLK | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_SCK | OUTPUT | LVCMOS25 | OUT | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_SDI | OUTPUT | LVCMOS25 | OUT | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_CS | OUTPUT | LVCMOS25 | OUT | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_PD | OUTPUT | LVCMOS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_RST | OUTPUT | LVCMOS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC1_CLK | OUTPUT | LVCMOS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC0_LCLK | INPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC0_SCK | OUTPUT | LVCMOS25 | OUT | |
++---------------------+-----------+-----------+------------+------------+
+| ADC0_SDI | OUTPUT | LVCMOS25 | OUT | |
++---------------------+-----------+-----------+------------+------------+
+| ADC0_CS | OUTPUT | LVCMOS25 | OUT | |
++---------------------+-----------+-----------+------------+------------+
+| ADC0_PD | OUTPUT | LVCMOS25 | | |
++---------------------+-----------+-----------+------------+------------+
+
+ Page 31
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+IO (PIO) Attributes (cont)
+--------------------------
+| ADC0_RST | OUTPUT | LVCMOS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ADC0_CLK | OUTPUT | LVCMOS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENB_LVDS_7 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENB_LVDS_6 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENB_LVDS_5 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENB_LVDS_4 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENB_LVDS_3 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENB_LVDS_2 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENB_LVDS_1 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENB_LVDS_0 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| APV1_SCL | BIDIR | LVCMOS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| APV1_SDA | BIDIR | LVCMOS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| APV1_RST | OUTPUT | LVCMOS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| APV1B_TRG | OUTPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| APV1A_TRG | OUTPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| APV1B_CLK | OUTPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| APV1A_CLK | OUTPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENA_LVDS_7 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENA_LVDS_6 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENA_LVDS_5 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENA_LVDS_4 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENA_LVDS_3 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENA_LVDS_2 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENA_LVDS_1 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| ENA_LVDS_0 | OUTPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| APV0_SCL | BIDIR | LVCMOS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| APV0_RST | OUTPUT | LVCMOS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| APV0B_TRG | OUTPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+
+ Page 32
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+IO (PIO) Attributes (cont)
+--------------------------
+| APV0A_TRG | OUTPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| APV0B_CLK | OUTPUT | LVDS25 | | |
++---------------------+-----------+-----------+------------+------------+
+| EXT_IN_3 | INPUT | LVTTL33 | | |
++---------------------+-----------+-----------+------------+------------+
+| EXT_IN_2 | INPUT | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| EXT_IN_1 | INPUT | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+| EXT_IN_0 | INPUT | LVTTL33 | IN | |
++---------------------+-----------+-----------+------------+------------+
+
+Removed logic
+-------------
+
+Block THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/INV_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/frame_udf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/frame_ovf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un5_next_ce_underflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/delay_store_RNIAEO4_1 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+
+ Page 33
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/frame_ovf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/frame_udf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_udf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_udf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_udf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_udf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_udf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_udf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_udf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_udf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+
+ Page 34
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/frame_udf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/frame_ovf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un5_next_ce_underflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/delay_store_RNI4EO4_1 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/frame_ovf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/frame_udf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_udf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_udf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_udf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_udf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_udf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_udf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_udf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_udf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+
+ Page 35
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/frame_udf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/frame_ovf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un5_next_ce_underflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/delay_store_RNI3PE5_1 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/frame_ovf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/frame_udf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_0 undriven or does not
+ drive anything - clipped.
+
+ Page 36
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_udf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_udf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_udf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_udf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_udf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_udf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_udf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_udf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/frame_udf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/frame_ovf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un5_next_ce_underflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/delay_store_RNI9EO4_1 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/frame_ovf undriven or does not
+ drive anything - clipped.
+
+ Page 37
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/frame_udf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_udf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_udf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_udf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_udf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_udf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_udf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_udf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_udf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+
+ Page 38
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/frame_udf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/frame_ovf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un5_next_ce_underflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/delay_store_RNI5EO4_1 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/frame_ovf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/frame_udf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_udf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_udf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_udf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_udf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_udf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_udf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_udf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_udf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+
+ Page 39
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/frame_udf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/frame_ovf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un5_next_ce_underflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/delay_store_RNI2EO4_1 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/frame_ovf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/frame_udf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_udf_7 undriven or does not
+ drive anything - clipped.
+
+ Page 40
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_udf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_udf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_udf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_udf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_udf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_udf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_udf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un3_next_ce_overflow_0_a2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/frame_ovf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/frame_udf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un5_next_ce_underflow_0_a2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/delay_store_RNI1EO4_1 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/frame_ovf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/frame_udf undriven or does not
+ drive anything - clipped.
+
+ Page 41
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_udf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_udf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_udf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_udf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_udf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_udf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_udf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_udf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/frame_udf_RNO undriven or does
+ not drive anything - clipped.
+
+ Page 42
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/frame_ovf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un5_next_ce_underflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/delay_store_RNI8EO4_1 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/frame_ovf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/frame_udf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_udf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_udf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_udf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_udf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_udf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_udf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_udf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_udf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+
+ Page 43
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/frame_udf_RNO undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/frame_ovf_RNO undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/delay_store_RNIEGL6_1
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/frame_ovf undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/frame_udf undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_udf_7 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+
+ Page 44
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/frame_udf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/frame_ovf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un5_next_ce_underflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/delay_store_RNI6PE5_1 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/frame_ovf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/frame_udf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_7 undriven or does not
+ drive anything - clipped.
+
+ Page 45
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_udf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_udf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_udf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_udf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_udf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_udf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_udf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_udf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un3_next_ce_overflow_0_a2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/frame_ovf_RNO undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/frame_udf_RNO undriven or does
+ not drive anything - clipped.
+
+ Page 46
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un5_next_ce_underflow_0_a2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/delay_store_RNI5PE5_1 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/frame_ovf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/frame_udf undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_udf_7 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_udf_6 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_udf_5 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_udf_4 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_udf_3 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_udf_2 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_udf_1 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_udf_0 undriven or does not
+ drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+
+ Page 47
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/frame_udf_RNO undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/frame_ovf_RNO undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/delay_store_RNIPNO5_1
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/frame_ovf undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/frame_udf undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_udf_7 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+
+ Page 48
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/frame_udf_RNO undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/frame_ovf_RNO undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/delay_store_RNII1E8_1
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/frame_ovf undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/frame_udf undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+
+ Page 49
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_udf_7 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/frame_udf_RNO undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/frame_ovf_RNO undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+
+ Page 50
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/delay_store_RNI4VRC_1
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/frame_ovf undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/frame_udf undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_udf_7 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+
+ Page 51
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/frame_udf_RNO undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/frame_ovf_RNO undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/delay_store_RNIT8H7_1
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/frame_ovf undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/frame_udf undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_udf_7 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+
+ Page 52
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/frame_udf_RNO undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/frame_ovf_RNO undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/delay_store_RNI7QA9_1
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/frame_ovf undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/frame_udf undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+
+ Page 53
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_udf_7 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Block THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/frame_int_CR0_ram/RAM2 undriven or
+ does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0
+ _0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0
+ _0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0
+ _0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0
+ _0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0
+ _0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0
+
+ Page 54
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0
+ _0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0
+ _0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/delay_store_CR0_ram/RAM2
+ undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_
+ 0_0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_
+ 0_0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_
+ 0_0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_
+ 0_0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_
+ 0_0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0
+ _0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0
+ _0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_
+ 0_0/RAM2 undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un26_wait_for_ack_counter_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un26_wait_for_ack_counter_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un26_wait_for_ack_counter_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un26_wait_for_ack_counter_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un26_wait_for_ack_counter_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_4_1 undriven
+ or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+
+ Page 55
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_7 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_6 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_3 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_2 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_1 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_0 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_5 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/un1_wait_for_ack_counter_8 undriven or does not drive anything
+ - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_u undriven
+ or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_4 undriven
+ or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_5/GATE
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_5_bm
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_5_am
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/un1_wait_for_ack_counter_7 undriven or does not drive anything
+ - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_4 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_8 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_7 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_6 undriven or
+ does not drive anything - clipped.
+
+ Page 56
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_5 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_4 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_3 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_2 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_1 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_0 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_timeout undriven or does
+ not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_reg_setting_timer_tick undriven or does not drive anything
+ - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_reg_setting_wait_for_ack_max_bit_2 undriven or does not
+ drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_reg_setting_wait_for_ack_max_bit_1 undriven or does not
+ drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_reg_setting_wait_for_ack_max_bit_0 undriven or does not
+ drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_timeout_RNO undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un26_wait_for_ack_counter_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un26_wait_for_ack_counter_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un26_wait_for_ack_counter_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un26_wait_for_ack_counter_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un26_wait_for_ack_counter_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_4_1 undriven
+ or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_7 undriven or
+
+ Page 57
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_6 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_5 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_4 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_1 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_0 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_3 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/un1_wait_for_ack_counter_5 undriven or does not drive anything
+ - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_u undriven
+ or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_5/GATE
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_5_bm
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_5_am
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_4 undriven
+ or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/un1_wait_for_ack_counter_4 undriven or does not drive anything
+ - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_2 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_8 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_7 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_6 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+
+ Page 58
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_5 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_4 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_3 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_2 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_1 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_0 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_timeout undriven or does
+ not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_reg_setting_timer_tick undriven or does not drive anything
+ - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_reg_setting_wait_for_ack_max_bit_2 undriven or does not
+ drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_reg_setting_wait_for_ack_max_bit_1 undriven or does not
+ drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_reg_setting_wait_for_ack_max_bit_0 undriven or does not
+ drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_timeout_RNO undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un26_wait_for_ack_counter_cry_0_0
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un26_wait_for_ack_counter_cry_1_0
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un26_wait_for_ack_counter_cry_3_0
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un26_wait_for_ack_counter_cry_5_0
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un26_wait_for_ack_counter_s_7_0
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_4_1 undriven
+ or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_7 undriven or
+ does not drive anything - clipped.
+
+ Page 59
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_6 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_5 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_4 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_1 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_0 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_3 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/un1_wait_for_ack_counter_5 undriven or does not drive anything
+ - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_u undriven
+ or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_4 undriven
+ or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_5/GATE
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_5_bm
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_un9_wait_for_ack_counter_5_am
+ undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/un1_wait_for_ack_counter_4 undriven or does not drive anything
+ - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counterc_2 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_8 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_7 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_6 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_5 undriven or
+
+ Page 60
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_4 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_3 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_2 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_1 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_counter_0 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_timeout undriven or does
+ not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_reg_setting_timer_tick undriven or does not drive anything
+ - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_reg_setting_wait_for_ack_max_bit_2 undriven or does not
+ drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_reg_setting_wait_for_ack_max_bit_1 undriven or does not
+ drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_reg_setting_wait_for_ack_max_bit_0 undriven or does not
+ drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF
+ 1_REPLYOBUF/proc_ack_timeout_counters_wait_for_ack_timeout_RNO undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIV
+ E_API/SBUF_TO_APL2/current_SYN_DATAREADY_OUT_RNO undriven or does not drive
+ anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIV
+ E_API/SBUF_TO_APL2/current_next_READ_OUT_RNO undriven or does not drive
+ anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIV
+ E_API/SBUF_TO_APL2/un1_next_buffer_state_2_sqmuxa_1_0_o3 undriven or does
+ not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIV
+ E_API/SBUF_TO_APL2/current_SYN_DATAREADY_OUT undriven or does not drive
+ anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIV
+ E_API/SBUF_TO_APL2/current_next_READ_OUT undriven or does not drive
+ anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIV
+ E_API/SBUF_TO_APL2/current_SYN_DATAREADY_OUT_RNO undriven or does not drive
+ anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIV
+ E_API/SBUF_TO_APL2/current_next_READ_OUT_RNO undriven or does not drive
+ anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIV
+
+ Page 61
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ E_API/SBUF_TO_APL2/un1_next_buffer_state_2_sqmuxa_1_0_o3 undriven or does
+ not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIV
+ E_API/SBUF_TO_APL2/current_SYN_DATAREADY_OUT undriven or does not drive
+ anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIV
+ E_API/SBUF_TO_APL2/current_next_READ_OUT undriven or does not drive
+ anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/TI
+ MER_MS_TICK_0_sqmuxa undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/TI
+ MER_MS_TICK_0_sqmuxa_8 undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/TI
+ MER_MS_TICK_0_sqmuxa_7 undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/TI
+ MER_MS_TICK_0_sqmuxa_6 undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/TI
+ MER_MS_TICK undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/buf_INT_DATA_OUT_47 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/buf_INT_DATA_OUT_46 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/buf_INT_DATA_OUT_45 undriven or
+ does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/buf_INT_DATA_OUT_44 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/comb_next_init_read was merged into signal THE_RICH_TRB/THE_UNIFIED_
+ ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/N_357
+Signal BP_LED_c_i was merged into signal BP_LED_c
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_10_16
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_10_18
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_12_16
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_12_18
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_13_16
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_13_18
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/wren_i
+
+ Page 62
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_9_16
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_9_18
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_14_16
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_14_18
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_4_16
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_4_18
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_6_16
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_6_18
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_7_16
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_7_18
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_1_16
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_1_18
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_15_16
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_15_18
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/wren_i
+
+ Page 63
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_3_16
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_3_18
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_0_16
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_0_18
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_8_16
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_8_18
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_11_16
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_11_18
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_2_16
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_2_18
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/invout_0 was merged into signal
+ fifo_status_5_16
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/invout_1 was merged into signal
+ fifo_status_5_18
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/fcnt_en_inv_inv was merged into
+ signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/rden_i
+
+ Page 64
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_12_24
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_12_26
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/fcnt_en_inv_inv was merged into
+ signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_13_24
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_13_26
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/fcnt_en_inv_inv was merged into
+ signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_10_24
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_10_26
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/fcnt_en_inv_inv was merged into
+ signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_11_24
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_11_26
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/fcnt_en_inv_inv was merged into
+ signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/rden_i
+
+ Page 65
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_14_24
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_14_26
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/fcnt_en_inv_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_9_24
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_9_26
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/fcnt_en_inv_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_8_24
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_8_26
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/fcnt_en_inv_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_6_24
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_6_26
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/fcnt_en_inv_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/rden_i
+
+ Page 66
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_0_24
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_0_26
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/fcnt_en_inv_inv was merged into
+ signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_15_24
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_15_26
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/fcnt_en_inv_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_7_24
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_7_26
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/fcnt_en_inv_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_2_24
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_2_26
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/fcnt_en_inv_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/rden_i
+
+ Page 67
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_5_24
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_5_26
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/fcnt_en_inv_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_3_24
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_3_26
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/fcnt_en_inv_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_4_24
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_4_26
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/fcnt_en_inv_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/cnt_con_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/cnt_con
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/fcnt_en_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/fcnt_en
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/wren_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/wren_i
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/rden_i_inv was merged into signal
+ THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/rden_i
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/invout_1 was merged into signal
+ fifo_status_1_24
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/invout_2 was merged into signal
+ fifo_status_1_26
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_0 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_0
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_2 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_2
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_6 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_6
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_15 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_15
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_12 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_12
+
+ Page 68
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_14 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_14
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_9 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_9
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_8 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_8
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_3 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_3
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_7 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_7
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_10 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_10
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_1 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_1
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_13 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_13
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_5 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_5
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_4 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_4
+Signal THE_PED_CORR_STAGE/buf_gooddata_i_11 was merged into signal
+ THE_PED_CORR_STAGE/buf_gooddata_11
+Signal buf_data_4_i_26 was merged into signal buf_data_4_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec0
+ _wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/adc_last_x
+Signal buf_data_3_i_26 was merged into signal buf_data_3_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec0
+ _wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/adc_last_x
+Signal buf_data_1_i_26 was merged into signal buf_data_1_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec0
+ _wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/adc_last_x
+Signal buf_data_5_i_26 was merged into signal buf_data_5_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec0
+ _wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/adc_last_x
+Signal buf_data_2_i_26 was merged into signal buf_data_2_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec0
+ _wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/adc_last_x
+Signal buf_data_7_i_26 was merged into signal buf_data_7_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec0
+ _wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/adc_last_x
+Signal buf_data_6_i_26 was merged into signal buf_data_6_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec0
+ _wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/adc_last_x
+Signal buf_data_0_i_26 was merged into signal buf_data_0_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec0
+ _wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/adc_last_x
+Signal buf_data_10_i_26 was merged into signal buf_data_10_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec
+
+ Page 69
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ 0_wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/adc_last_x
+Signal buf_data_13_i_26 was merged into signal buf_data_13_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec
+ 0_wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/adc_last_x
+Signal buf_data_12_i_26 was merged into signal buf_data_12_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec
+ 0_wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/adc_last_x
+Signal buf_data_14_i_26 was merged into signal buf_data_14_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec
+ 0_wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/adc_last_x
+Signal buf_data_15_i_26 was merged into signal buf_data_15_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec
+ 0_wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/adc_last_x
+Signal buf_data_8_i_26 was merged into signal buf_data_8_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec0
+ _wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/adc_last_x
+Signal buf_data_9_i_26 was merged into signal buf_data_9_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec0
+ _wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/adc_last_x
+Signal buf_data_11_i_26 was merged into signal buf_data_11_26
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dec
+ 0_wre3 was merged into signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/adc_last_x
+Signal adc1_ce_i was merged into signal THE_ADC1_HANDLER/adc1_ce
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/invout_0 was merged into signal
+ THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_1_Q
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/invout_1 was merged into signal
+ THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_0_Q
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/rRst was merged into signal
+ THE_ADC1_CROSSOVER/reset
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/dec0_wre3 was merged into signal
+ THE_ADC1_CROSSOVER/THE_CROSSOVER/wren_i
+Signal adc0_ce_i was merged into signal THE_ADC0_HANDLER/adc0_ce
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/rRst was merged into signal
+ THE_ADC0_CROSSOVER/reset
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/invout_0 was merged into signal
+ THE_ADC0_CROSSOVER/THE_CROSSOVER/un1_THE_CROSSOVER_2
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/invout_1 was merged into signal
+ THE_ADC0_CROSSOVER/THE_CROSSOVER/un1_THE_CROSSOVER_1
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/dec0_wre3 was merged into signal
+ THE_ADC0_CROSSOVER/THE_CROSSOVER/wren_i
+Signal THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/dec_wre3 was merged into
+ signal THE_APV_TRGCTRL/atc_eds_we
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/reset_i_i was merged into signal
+ THE_RICH_TRB/THE_MEDIA_INTERFACE/reset_i
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/tx_ks_i was merged into signal
+ THE_RICH_TRB/THE_MEDIA_INTERFACE/med_stat_op_1
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/rRst
+ was merged into signal THE_RICH_TRB/THE_MEDIA_INTERFACE/N_1939_1_i
+
+ Page 70
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/rden_i
+ was merged into signal THE_RICH_TRB/THE_MEDIA_INTERFACE/fifo_rx_empty
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/invout
+ _1 was merged into signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_
+ FPGA/FIFO_DP_BRAM/fifo_rx_full
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/fifo_r
+ x_empty_i was merged into signal
+ THE_RICH_TRB/THE_MEDIA_INTERFACE/fifo_rx_empty
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/rRst
+ was merged into signal THE_RICH_TRB/THE_MEDIA_INTERFACE/N_1995_i
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/invout
+ _0 was merged into signal THE_RICH_TRB/THE_MEDIA_INTERFACE/fifo_tx_empty
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/invout
+ _1 was merged into signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO
+ _SFP/FIFO_DP_BRAM/fifo_tx_full
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/wren_i_inv was merged into signal THE_RICH_TRB/THE_UNI
+ FIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/w
+ ren_i
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/rden_i_inv was merged into signal THE_RICH_TRB/THE_UNI
+ FIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/r
+ den_i
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/invout_1 was merged into signal THE_RICH_TRB/THE_UNIFI
+ ED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/fifo_empty
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/invout_2 was merged into signal THE_RICH_TRB/THE_UNIFI
+ ED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/fifo_full
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/N_360_i was merged into
+ signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IB
+ UF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/current_buffer_state
+ _1
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/wren_i_inv was merged into signal THE_RICH_TRB/THE_UNI
+ FIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/w
+ ren_i
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/rden_i_inv was merged into signal THE_RICH_TRB/THE_UNI
+ FIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/r
+ den_i
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/invout_1 was merged into signal THE_RICH_TRB/THE_UNIFI
+ ED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/fifo_empty
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/invout_2 was merged into signal THE_RICH_TRB/THE_UNIFI
+ ED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/fifo_full
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/wren_i_inv was merged into signal THE_RICH_TRB/THE_UNI
+ FIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/w
+ ren_i
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/rden_i_inv was merged into signal THE_RICH_TRB/THE_UNI
+ FIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/r
+ den_i
+
+ Page 71
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/invout_1 was merged into signal THE_RICH_TRB/THE_UNIFI
+ ED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/fifo_empty
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/invout_2 was merged into signal THE_RICH_TRB/THE_UNIFI
+ ED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/fifo_full
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/wren_i_inv was merged into signal T
+ HE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_
+ API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/wren_i
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/rden_i_inv was merged into signal T
+ HE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_
+ API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/rden_i
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/invout_1 was merged into signal THE
+ _RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_AP
+ I/next_fifo_to_apl_empty
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/invout_2 was merged into signal THE
+ _RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_AP
+ I/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/buf_api_stat_fifo_to_apl_46
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/wren_i_inv was merged into signal T
+ HE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_
+ API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/wren_i
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/rden_i_inv was merged into signal T
+ HE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_
+ API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/rden_i
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/invout_1 was merged into signal THE
+ _RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_AP
+ I/buf_api_stat_fifo_to_int_47
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/invout_2 was merged into signal
+ THE_RICH_TRB_THE_UNIFIED_ENDPOINT_buf_api_stat_fifo_to_int_46
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/wren_i_inv was merged into signal T
+ HE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_
+ API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/wren_i
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/rden_i_inv was merged into signal T
+ HE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_
+ API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/rden_i
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/invout_1 was merged into signal THE
+ _RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_AP
+ I/next_fifo_to_apl_empty
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/invout_2 was merged into signal THE
+ _RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_AP
+ I/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/buf_api_stat_fifo_to_apl_110
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/wren_i_inv was merged into signal T
+ HE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_
+
+ Page 72
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/wren_i
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/rden_i_inv was merged into signal T
+ HE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_
+ API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/rden_i
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/invout_1 was merged into signal THE
+ _RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_AP
+ I/buf_api_stat_fifo_to_int_111
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/invout_2 was merged into signal
+ THE_RICH_TRB/THE_UNIFIED_ENDPOINT/buf_api_stat_fifo_to_int_110
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/ipu_start_readout_i was merged into signal ipu_start_readout
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/C
+ OMMON_REGISTERS_OUT_write_enable_i_0 was merged into signal THE_RICH_TRB/TH
+ E_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/COMMON_REGISTERS_O
+ UT_write_enable_0
+Signal THE_SLAVE_BUS/slv_data_wr_i_3 was merged into signal
+ THE_SLAVE_BUS/slv_data_wr_3
+Signal THE_SLAVE_BUS/THE_PED_MEM/store_wr_i was merged into signal
+ THE_SLAVE_BUS/THE_PED_MEM/store_wr
+Signal THE_SLAVE_BUS/THE_THR_MEM/store_wr_i was merged into signal
+ THE_SLAVE_BUS/THE_THR_MEM/store_wr
+Signal THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/store_wr_i was merged into signal
+ THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/store_wr
+Signal THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/wait_pulse_i was
+ merged into signal
+ THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/wait_pulse
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/invout
+ _0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/send_reset_in_i undriven or does not
+ drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un5_next_ce_underflow
+
+ Page 73
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_frame_udf_i undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_udf_3 undriven or does
+
+ Page 74
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/N_2050_i undriven or does not
+ drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_frame_udf_i undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_7
+
+ Page 75
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/N_2045_i undriven or does not
+ drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_1
+
+ Page 76
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_frame_udf_i undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_3
+
+ Page 77
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/N_2040_i undriven or does not
+ drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+
+ Page 78
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_frame_udf_i undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_udf_5 undriven or does
+
+ Page 79
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/N_2035_i undriven or does not
+ drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_frame_udf_i undriven
+
+ Page 80
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_udf_1 undriven or does
+
+ Page 81
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/N_2030_i undriven or does not
+ drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_frame_udf_i undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_5
+
+ Page 82
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/N_2025_i undriven or does not
+ drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+
+ Page 83
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_frame_udf_i undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_1
+
+ Page 84
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/N_2020_i undriven or does not
+ drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un5_next_ce_underflow
+
+ Page 85
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_frame_udf_i undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_udf_3 undriven or does
+
+ Page 86
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/N_2015_i undriven or does not
+ drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_4_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_3_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_1_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_5_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_2_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_7_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_6_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_0_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un3_next_ce_overflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_frame_udf_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un5_next_ce_underflow
+
+ Page 87
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_frame_udf_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_frame_udf_i
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_udf_3 undriven or does
+
+ Page 88
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/N_2002_i undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_frame_udf_i undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_7
+
+ Page 89
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/N_1997_i undriven or does not
+ drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_1
+
+ Page 90
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un3_next_ce_overflow undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_frame_udf_4 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_frame_udf_3 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_frame_udf_i undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_3
+
+ Page 91
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/N_1992_i undriven or does not
+ drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+
+ Page 92
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un3_next_ce_overflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_frame_udf_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_frame_udf_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_frame_udf_i
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_udf_5 undriven or does
+
+ Page 93
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/N_1987_i undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un3_next_ce_overflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_frame_udf_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_frame_udf_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_frame_udf_i
+
+ Page 94
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_udf_1 undriven or does
+
+ Page 95
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/N_1982_i undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un3_next_ce_overflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_frame_udf_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_frame_udf_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_frame_udf_i
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_5
+
+ Page 96
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/N_1977_i undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+
+ Page 97
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un3_next_ce_overflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_frame_udf_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un5_next_ce_underflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_frame_udf_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_frame_udf_i
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_1
+
+ Page 98
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_udf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/N_1972_i undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_cry_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_cry_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_cry_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_cry_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un3_next_ce_overflow
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_frame_udf_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/next_frame_ovf_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un5_next_ce_underflow
+
+ Page 99
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_frame_udf_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/next_frame_ovf_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/next_frame_ovf_i undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_frame_udf_i
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_7 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_3 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_ovf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_udf_6 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_udf_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_udf_4 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_udf_3 undriven or does
+
+ Page 100
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_udf_2 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_udf_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/sum_udf_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/N_1967_i undriven or does
+ not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_10_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_13_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_12_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_14_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_15_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_8_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_9_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RAW_BUF_STAGE/apv_frame_11_11 undriven or does not drive anything -
+ clipped.
+Signal THE_RESET_HANDLER/reset_cnt_s_0_S1_15 undriven or does not drive anything
+ - clipped.
+Signal THE_RESET_HANDLER/reset_cnt_s_0_COUT_15 undriven or does not drive
+ anything - clipped.
+Signal THE_RESET_HANDLER/reset_cnt_cry_0_S0_0 undriven or does not drive
+ anything - clipped.
+Signal THE_REBOOT_HANDLER/reboot_counter_cry_0_S0_0 undriven or does not drive
+ anything - clipped.
+Signal THE_REBOOT_HANDLER/reboot_counter_s_0_S1_15 undriven or does not drive
+ anything - clipped.
+Signal THE_REBOOT_HANDLER/reboot_counter_s_0_COUT_15 undriven or does not drive
+ anything - clipped.
+Signal THE_40M_PLL/CLKINTFB undriven or does not drive anything - clipped.
+Signal THE_40M_PLL/CLKOK undriven or does not drive anything - clipped.
+Signal THE_100M_DLL/SMIRDATA undriven or does not drive anything - clipped.
+Signal THE_100M_DLL/CLKOS_0 undriven or does not drive anything - clipped.
+Signal THE_SYNC_PLL/CLKOK_0 undriven or does not drive anything - clipped.
+Signal THE_SYNC_PLL/CLKOS undriven or does not drive anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_3_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_3_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_3_3_s_9_0_S1 undriven or does not drive anything
+
+ Page 101
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_3_3_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_15_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_15_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_15_3_s_9_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_15_3_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_13_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_13_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_13_3_s_9_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_13_3_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_7_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_7_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_7_3_s_9_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_7_3_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_2_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_2_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_2_3_s_9_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_2_3_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_14_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_14_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_14_3_s_9_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_14_3_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_9_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_9_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_9_3_s_9_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_9_3_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_11_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_11_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_11_3_s_9_0_S1 undriven or does not drive anything
+
+ Page 102
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_11_3_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_0_4_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_0_4_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_0_4_s_9_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_0_4_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_10_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_10_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_10_3_s_9_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_10_3_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_5_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_5_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_5_3_s_9_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_5_3_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_12_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_12_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_12_3_s_9_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_12_3_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_4_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_4_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_4_3_s_9_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_4_3_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_6_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_6_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_6_3_s_9_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_6_3_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_1_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_1_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_1_3_s_9_0_S1 undriven or does not drive anything
+
+ Page 103
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_1_3_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_8_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_8_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_todo_8_3_s_9_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_IPU_STAGE/fifo_todo_8_3_s_9_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un1_finished_cry_0_0_S0 undriven or does not drive anything
+ - clipped.
+Signal THE_IPU_STAGE/un1_finished_s_15_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_IPU_STAGE/un1_finished_s_15_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_0_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_0_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_0_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_0_s_11_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_2_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_2_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_2_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_2_s_11_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_1_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_1_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_1_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_1_s_11_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_3_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_3_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_3_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_3_s_11_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_4_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_4_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_4_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_4_s_11_0_COUT undriven or does not drive
+
+ Page 104
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_5_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_5_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_5_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_5_s_11_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_6_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_6_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_6_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_6_s_11_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_7_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_7_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_7_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_7_s_11_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_9_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_9_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_9_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_9_s_11_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_8_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_8_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_8_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_8_s_11_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_10_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_10_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_10_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_10_s_11_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_11_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_11_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_11_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_11_s_11_0_COUT undriven or does not drive
+
+ Page 105
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_12_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_12_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_12_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_12_s_11_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_13_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_13_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_13_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_13_s_11_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_14_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_14_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_14_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_14_s_11_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_15_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_15_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_15_s_11_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/fifo_data_free_x_15_s_11_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un63_dfifo_available_x_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un63_dfifo_available_x_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un63_dfifo_available_x_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un63_dfifo_available_x_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un63_dfifo_available_x_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un63_dfifo_available_x_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un63_dfifo_available_x_cry_5_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un63_dfifo_available_x_cry_5_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un63_dfifo_available_x_cry_7_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un63_dfifo_available_x_cry_7_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un63_dfifo_available_x_cry_9_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un63_dfifo_available_x_cry_9_0_S0 undriven or does not
+
+ Page 106
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un63_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un63_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un55_dfifo_available_x_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un55_dfifo_available_x_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un55_dfifo_available_x_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un55_dfifo_available_x_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un55_dfifo_available_x_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un55_dfifo_available_x_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un55_dfifo_available_x_cry_5_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un55_dfifo_available_x_cry_5_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un55_dfifo_available_x_cry_7_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un55_dfifo_available_x_cry_7_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un55_dfifo_available_x_cry_9_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un55_dfifo_available_x_cry_9_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un55_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un55_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un47_dfifo_available_x_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un47_dfifo_available_x_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un47_dfifo_available_x_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un47_dfifo_available_x_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un47_dfifo_available_x_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un47_dfifo_available_x_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un47_dfifo_available_x_cry_5_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un47_dfifo_available_x_cry_5_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un47_dfifo_available_x_cry_7_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un47_dfifo_available_x_cry_7_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un47_dfifo_available_x_cry_9_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un47_dfifo_available_x_cry_9_0_S0 undriven or does not
+
+ Page 107
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un47_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un47_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un39_dfifo_available_x_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un39_dfifo_available_x_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un39_dfifo_available_x_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un39_dfifo_available_x_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un39_dfifo_available_x_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un39_dfifo_available_x_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un39_dfifo_available_x_cry_5_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un39_dfifo_available_x_cry_5_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un39_dfifo_available_x_cry_7_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un39_dfifo_available_x_cry_7_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un39_dfifo_available_x_cry_9_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un39_dfifo_available_x_cry_9_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un39_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un39_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un31_dfifo_available_x_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un31_dfifo_available_x_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un31_dfifo_available_x_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un31_dfifo_available_x_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un31_dfifo_available_x_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un31_dfifo_available_x_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un31_dfifo_available_x_cry_5_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un31_dfifo_available_x_cry_5_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un31_dfifo_available_x_cry_7_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un31_dfifo_available_x_cry_7_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un31_dfifo_available_x_cry_9_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un31_dfifo_available_x_cry_9_0_S0 undriven or does not
+
+ Page 108
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un31_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un31_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un23_dfifo_available_x_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un23_dfifo_available_x_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un23_dfifo_available_x_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un23_dfifo_available_x_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un23_dfifo_available_x_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un23_dfifo_available_x_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un23_dfifo_available_x_cry_5_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un23_dfifo_available_x_cry_5_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un23_dfifo_available_x_cry_7_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un23_dfifo_available_x_cry_7_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un23_dfifo_available_x_cry_9_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un23_dfifo_available_x_cry_9_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un23_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un23_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un15_dfifo_available_x_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un15_dfifo_available_x_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un15_dfifo_available_x_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un15_dfifo_available_x_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un15_dfifo_available_x_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un15_dfifo_available_x_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un15_dfifo_available_x_cry_5_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un15_dfifo_available_x_cry_5_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un15_dfifo_available_x_cry_7_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un15_dfifo_available_x_cry_7_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un15_dfifo_available_x_cry_9_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un15_dfifo_available_x_cry_9_0_S0 undriven or does not
+
+ Page 109
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un15_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un15_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un4_dfifo_available_x_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un4_dfifo_available_x_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un4_dfifo_available_x_cry_1_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un4_dfifo_available_x_cry_1_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un4_dfifo_available_x_cry_3_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un4_dfifo_available_x_cry_3_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un4_dfifo_available_x_cry_5_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un4_dfifo_available_x_cry_5_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un4_dfifo_available_x_cry_7_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un4_dfifo_available_x_cry_7_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un4_dfifo_available_x_cry_9_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un4_dfifo_available_x_cry_9_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un4_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un4_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un127_dfifo_available_x_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un127_dfifo_available_x_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un127_dfifo_available_x_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un127_dfifo_available_x_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un127_dfifo_available_x_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un127_dfifo_available_x_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un127_dfifo_available_x_cry_5_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un127_dfifo_available_x_cry_5_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un127_dfifo_available_x_cry_7_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un127_dfifo_available_x_cry_7_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un127_dfifo_available_x_cry_9_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un127_dfifo_available_x_cry_9_0_S0 undriven or does not
+
+ Page 110
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un127_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un127_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un119_dfifo_available_x_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un119_dfifo_available_x_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un119_dfifo_available_x_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un119_dfifo_available_x_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un119_dfifo_available_x_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un119_dfifo_available_x_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un119_dfifo_available_x_cry_5_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un119_dfifo_available_x_cry_5_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un119_dfifo_available_x_cry_7_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un119_dfifo_available_x_cry_7_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un119_dfifo_available_x_cry_9_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un119_dfifo_available_x_cry_9_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un119_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un119_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un111_dfifo_available_x_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un111_dfifo_available_x_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un111_dfifo_available_x_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un111_dfifo_available_x_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un111_dfifo_available_x_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un111_dfifo_available_x_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un111_dfifo_available_x_cry_5_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un111_dfifo_available_x_cry_5_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un111_dfifo_available_x_cry_7_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un111_dfifo_available_x_cry_7_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un111_dfifo_available_x_cry_9_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un111_dfifo_available_x_cry_9_0_S0 undriven or does not
+
+ Page 111
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un111_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un111_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un103_dfifo_available_x_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un103_dfifo_available_x_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un103_dfifo_available_x_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un103_dfifo_available_x_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un103_dfifo_available_x_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un103_dfifo_available_x_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un103_dfifo_available_x_cry_5_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un103_dfifo_available_x_cry_5_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un103_dfifo_available_x_cry_7_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un103_dfifo_available_x_cry_7_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un103_dfifo_available_x_cry_9_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un103_dfifo_available_x_cry_9_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un103_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un103_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un95_dfifo_available_x_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un95_dfifo_available_x_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un95_dfifo_available_x_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un95_dfifo_available_x_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un95_dfifo_available_x_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un95_dfifo_available_x_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un95_dfifo_available_x_cry_5_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un95_dfifo_available_x_cry_5_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un95_dfifo_available_x_cry_7_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un95_dfifo_available_x_cry_7_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un95_dfifo_available_x_cry_9_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un95_dfifo_available_x_cry_9_0_S0 undriven or does not
+
+ Page 112
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un95_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un95_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un87_dfifo_available_x_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un87_dfifo_available_x_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un87_dfifo_available_x_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un87_dfifo_available_x_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un87_dfifo_available_x_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un87_dfifo_available_x_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un87_dfifo_available_x_cry_5_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un87_dfifo_available_x_cry_5_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un87_dfifo_available_x_cry_7_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un87_dfifo_available_x_cry_7_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un87_dfifo_available_x_cry_9_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un87_dfifo_available_x_cry_9_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un87_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un87_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un79_dfifo_available_x_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un79_dfifo_available_x_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un79_dfifo_available_x_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un79_dfifo_available_x_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un79_dfifo_available_x_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un79_dfifo_available_x_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un79_dfifo_available_x_cry_5_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un79_dfifo_available_x_cry_5_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un79_dfifo_available_x_cry_7_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un79_dfifo_available_x_cry_7_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un79_dfifo_available_x_cry_9_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un79_dfifo_available_x_cry_9_0_S0 undriven or does not
+
+ Page 113
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un79_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un79_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un71_dfifo_available_x_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un71_dfifo_available_x_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un71_dfifo_available_x_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un71_dfifo_available_x_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un71_dfifo_available_x_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un71_dfifo_available_x_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un71_dfifo_available_x_cry_5_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un71_dfifo_available_x_cry_5_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un71_dfifo_available_x_cry_7_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un71_dfifo_available_x_cry_7_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un71_dfifo_available_x_cry_9_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un71_dfifo_available_x_cry_9_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un71_dfifo_available_x_cry_11_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un71_dfifo_available_x_cry_11_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un1_next_trgnum_match_0_I_1_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un1_next_trgnum_match_0_I_1_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/un1_next_trgnum_match_0_I_10_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un1_next_trgnum_match_0_I_10_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un1_next_trgnum_match_0_I_37_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un1_next_trgnum_match_0_I_37_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un1_next_trgnum_match_0_I_46_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un1_next_trgnum_match_0_I_46_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un1_next_trgnum_match_0_I_28_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/un1_next_trgnum_match_0_I_28_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/w_ctr_cia_S1 undriven or does not
+
+ Page 114
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/w_ctr_cia_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/a1_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/a1_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/g_cmp_ci_a_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/g_cmp_ci_a_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/a0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/a0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/e_cmp_ci_a_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/e_cmp_ci_a_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/bdcnt_bctr_cia_S1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/bdcnt_bctr_cia_S0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOB17 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOB16 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOB15 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOB14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOB13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOB12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOB11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOB10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOB9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA17 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA16 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA15 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA10 undriven or does
+
+ Page 115
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1_DOA0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOB17 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOB16 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOB15 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOB14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOB13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOB12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOB11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOB10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOB9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA17 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA16 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA15 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA9 undriven or does
+
+ Page 116
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2_DOA0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/r_ctr_cia_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/r_ctr_cia_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/co5_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOB17 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOB16 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOB15 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOB14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOB13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOB12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOB11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOB10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOB9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/fifo_out_data_10_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/fifo_out_data_10_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/fifo_out_data_10_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/fifo_out_data_10_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/fifo_out_data_10_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA17 undriven or does
+
+ Page 117
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA16 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA15 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0_DOA0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/co5_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/r_ctr_cia_S1_0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/r_ctr_cia_S0_0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/w_ctr_cia_S1_0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/w_ctr_cia_S0_0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/a1_S1_0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/a1_COUT_0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/g_cmp_ci_a_S1_0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/g_cmp_ci_a_S0_0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/a0_S1_0 undriven or does not drive
+
+ Page 118
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/a0_COUT_0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/e_cmp_ci_a_S1_0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/e_cmp_ci_a_S0_0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/bdcnt_bctr_cia_S1_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/bdcnt_bctr_cia_S0_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOB17_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOB16_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOB15_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOB14_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOB13_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOB12_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOB11_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOB10_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOB9_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/fifo_out_data_12_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/fifo_out_data_12_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/fifo_out_data_12_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/fifo_out_data_12_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/fifo_out_data_12_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA17_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA16_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA15_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA14_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA13_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA12_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA11_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA10_0 undriven or
+
+ Page 119
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA9_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA8_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA7_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA6_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA5_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA4_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA3_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA2_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA1_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0_DOA0_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOB17_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOB16_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOB15_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOB14_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOB13_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOB12_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOB11_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOB10_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOB9_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA17_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA16_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA15_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA14_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA13_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA12_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA11_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA10_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA9_0 undriven or does
+
+ Page 120
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA8_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA7_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA6_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA5_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA4_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA3_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA2_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA1_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1_DOA0_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOB17_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOB16_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOB15_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOB14_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOB13_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOB12_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOB11_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOB10_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOB9_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA17_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA16_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA15_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA14_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA13_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA12_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA11_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA10_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA9_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA8_0 undriven or does
+
+ Page 121
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA7_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA6_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA5_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA4_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA3_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA2_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA1_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2_DOA0_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/co5_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/r_ctr_cia_S1_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/r_ctr_cia_S0_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/w_ctr_cia_S1_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/w_ctr_cia_S0_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/a1_S1_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/a1_COUT_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/g_cmp_ci_a_S1_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/g_cmp_ci_a_S0_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/a0_S1_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/a0_COUT_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/e_cmp_ci_a_S1_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/e_cmp_ci_a_S0_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/bdcnt_bctr_cia_S1_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/bdcnt_bctr_cia_S0_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOB17_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOB16_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOB15_1 undriven or
+
+ Page 122
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOB14_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOB13_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOB12_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOB11_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOB10_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOB9_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/fifo_out_data_13_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/fifo_out_data_13_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/fifo_out_data_13_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/fifo_out_data_13_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/fifo_out_data_13_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA17_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA16_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA15_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA14_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA13_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA12_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA11_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA10_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA9_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA8_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA7_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA6_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA5_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA4_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA3_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA2_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA1_1 undriven or does
+
+ Page 123
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0_DOA0_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOB17_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOB16_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOB15_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOB14_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOB13_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOB12_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOB11_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOB10_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOB9_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA17_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA16_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA15_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA14_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA13_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA12_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA11_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA10_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA9_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA8_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA7_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA6_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA5_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA4_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA3_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA2_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA1_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1_DOA0_1 undriven or does
+
+ Page 124
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOB17_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOB16_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOB15_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOB14_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOB13_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOB12_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOB11_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOB10_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOB9_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA17_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA16_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA15_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA14_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA13_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA12_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA11_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA10_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA9_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA8_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA7_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA6_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA5_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA4_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA3_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA2_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA1_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2_DOA0_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/co5_2 undriven or does not drive
+
+ Page 125
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/r_ctr_cia_S1_2 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/r_ctr_cia_S0_2 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/w_ctr_cia_S1_2 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/w_ctr_cia_S0_2 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/a1_S1_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/a1_COUT_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/g_cmp_ci_a_S1_2 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/g_cmp_ci_a_S0_2 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/a0_S1_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/a0_COUT_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/e_cmp_ci_a_S1_2 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/e_cmp_ci_a_S0_2 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/bdcnt_bctr_cia_S1_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/bdcnt_bctr_cia_S0_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOB17_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOB16_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOB15_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOB14_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOB13_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOB12_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOB11_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOB10_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOB9_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/fifo_out_data_9_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/fifo_out_data_9_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/fifo_out_data_9_24 undriven or does
+
+ Page 126
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/fifo_out_data_9_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/fifo_out_data_9_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA17_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA16_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA15_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA14_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA13_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA12_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA11_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA10_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA9_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA8_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA7_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA6_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA5_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA4_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA3_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA2_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA1_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0_DOA0_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOB17_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOB16_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOB15_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOB14_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOB13_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOB12_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOB11_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOB10_2 undriven or does
+
+ Page 127
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOB9_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA17_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA16_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA15_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA14_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA13_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA12_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA11_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA10_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA9_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA8_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA7_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA6_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA5_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA4_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA3_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA2_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA1_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1_DOA0_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOB17_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOB16_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOB15_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOB14_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOB13_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOB12_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOB11_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOB10_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOB9_2 undriven or does
+
+ Page 128
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA17_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA16_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA15_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA14_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA13_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA12_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA11_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA10_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA9_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA8_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA7_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA6_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA5_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA4_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA3_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA2_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA1_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2_DOA0_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/co5_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/r_ctr_cia_S1_3 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/r_ctr_cia_S0_3 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/w_ctr_cia_S1_3 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/w_ctr_cia_S0_3 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/a1_S1_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/a1_COUT_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/g_cmp_ci_a_S1_3 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/g_cmp_ci_a_S0_3 undriven or does not
+
+ Page 129
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/a0_S1_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/a0_COUT_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/e_cmp_ci_a_S1_3 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/e_cmp_ci_a_S0_3 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/bdcnt_bctr_cia_S1_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/bdcnt_bctr_cia_S0_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOB17_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOB16_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOB15_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOB14_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOB13_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOB12_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOB11_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOB10_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOB9_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/fifo_out_data_14_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/fifo_out_data_14_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/fifo_out_data_14_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/fifo_out_data_14_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/fifo_out_data_14_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA17_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA16_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA15_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA14_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA13_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA12_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA11_3 undriven or
+
+ Page 130
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA10_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA9_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA8_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA7_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA6_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA5_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA4_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA3_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA2_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA1_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0_DOA0_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOB17_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOB16_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOB15_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOB14_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOB13_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOB12_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOB11_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOB10_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOB9_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA17_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA16_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA15_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA14_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA13_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA12_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA11_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA10_3 undriven or
+
+ Page 131
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA9_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA8_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA7_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA6_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA5_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA4_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA3_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA2_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA1_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1_DOA0_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOB17_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOB16_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOB15_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOB14_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOB13_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOB12_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOB11_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOB10_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOB9_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA17_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA16_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA15_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA14_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA13_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA12_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA11_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA10_3 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA9_3 undriven or does
+
+ Page 132
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA8_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA7_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA6_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA5_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA4_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA3_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA2_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA1_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2_DOA0_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/co5_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/r_ctr_cia_S1_4 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/r_ctr_cia_S0_4 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/w_ctr_cia_S1_4 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/w_ctr_cia_S0_4 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/a1_S1_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/a1_COUT_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/g_cmp_ci_a_S1_4 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/g_cmp_ci_a_S0_4 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/a0_S1_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/a0_COUT_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/e_cmp_ci_a_S1_4 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/e_cmp_ci_a_S0_4 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/bdcnt_bctr_cia_S1_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/bdcnt_bctr_cia_S0_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOB17_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOB16_4 undriven or does
+
+ Page 133
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOB15_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOB14_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOB13_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOB12_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOB11_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOB10_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOB9_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/fifo_out_data_4_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/fifo_out_data_4_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/fifo_out_data_4_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/fifo_out_data_4_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/fifo_out_data_4_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA17_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA16_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA15_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA14_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA13_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA12_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA11_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA10_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA9_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA8_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA7_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA6_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA5_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA4_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA3_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA2_4 undriven or does
+
+ Page 134
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA1_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0_DOA0_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOB17_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOB16_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOB15_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOB14_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOB13_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOB12_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOB11_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOB10_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOB9_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA17_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA16_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA15_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA14_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA13_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA12_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA11_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA10_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA9_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA8_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA7_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA6_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA5_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA4_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA3_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA2_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA1_4 undriven or does
+
+ Page 135
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1_DOA0_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOB17_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOB16_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOB15_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOB14_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOB13_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOB12_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOB11_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOB10_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOB9_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA17_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA16_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA15_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA14_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA13_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA12_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA11_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA10_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA9_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA8_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA7_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA6_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA5_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA4_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA3_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA2_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA1_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2_DOA0_4 undriven or does
+
+ Page 136
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/co5_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/r_ctr_cia_S1_5 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/r_ctr_cia_S0_5 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/w_ctr_cia_S1_5 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/w_ctr_cia_S0_5 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/a1_S1_5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/a1_COUT_5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/g_cmp_ci_a_S1_5 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/g_cmp_ci_a_S0_5 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/a0_S1_5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/a0_COUT_5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/e_cmp_ci_a_S1_5 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/e_cmp_ci_a_S0_5 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/bdcnt_bctr_cia_S1_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/bdcnt_bctr_cia_S0_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOB17_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOB16_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOB15_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOB14_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOB13_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOB12_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOB11_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOB10_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOB9_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/fifo_out_data_6_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/fifo_out_data_6_25 undriven or does
+
+ Page 137
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/fifo_out_data_6_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/fifo_out_data_6_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/fifo_out_data_6_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA17_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA16_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA15_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA14_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA13_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA12_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA11_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA10_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA9_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA8_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA7_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA6_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA5_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA4_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA3_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA2_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA1_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0_DOA0_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOB17_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOB16_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOB15_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOB14_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOB13_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOB12_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOB11_5 undriven or does
+
+ Page 138
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOB10_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOB9_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA17_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA16_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA15_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA14_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA13_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA12_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA11_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA10_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA9_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA8_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA7_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA6_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA5_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA4_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA3_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA2_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA1_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1_DOA0_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOB17_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOB16_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOB15_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOB14_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOB13_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOB12_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOB11_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOB10_5 undriven or does
+
+ Page 139
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOB9_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA17_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA16_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA15_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA14_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA13_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA12_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA11_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA10_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA9_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA8_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA7_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA6_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA5_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA4_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA3_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA2_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA1_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2_DOA0_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/co5_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/r_ctr_cia_S1_6 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/r_ctr_cia_S0_6 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/w_ctr_cia_S1_6 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/w_ctr_cia_S0_6 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/a1_S1_6 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/a1_COUT_6 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/g_cmp_ci_a_S1_6 undriven or does not
+
+ Page 140
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/g_cmp_ci_a_S0_6 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/a0_S1_6 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/a0_COUT_6 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/e_cmp_ci_a_S1_6 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/e_cmp_ci_a_S0_6 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/bdcnt_bctr_cia_S1_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/bdcnt_bctr_cia_S0_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOB17_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOB16_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOB15_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOB14_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOB13_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOB12_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOB11_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOB10_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOB9_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/fifo_out_data_7_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/fifo_out_data_7_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/fifo_out_data_7_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/fifo_out_data_7_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/fifo_out_data_7_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA17_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA16_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA15_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA14_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA13_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA12_6 undriven or does
+
+ Page 141
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA11_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA10_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA9_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA8_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA7_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA6_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA5_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA4_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA3_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA2_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA1_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0_DOA0_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOB17_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOB16_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOB15_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOB14_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOB13_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOB12_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOB11_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOB10_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOB9_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA17_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA16_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA15_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA14_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA13_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA12_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA11_6 undriven or does
+
+ Page 142
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA10_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA9_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA8_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA7_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA6_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA5_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA4_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA3_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA2_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA1_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1_DOA0_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOB17_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOB16_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOB15_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOB14_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOB13_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOB12_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOB11_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOB10_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOB9_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA17_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA16_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA15_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA14_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA13_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA12_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA11_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA10_6 undriven or does
+
+ Page 143
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA9_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA8_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA7_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA6_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA5_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA4_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA3_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA2_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA1_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2_DOA0_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/co5_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/r_ctr_cia_S1_7 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/r_ctr_cia_S0_7 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/w_ctr_cia_S1_7 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/w_ctr_cia_S0_7 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/a1_S1_7 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/a1_COUT_7 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/g_cmp_ci_a_S1_7 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/g_cmp_ci_a_S0_7 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/a0_S1_7 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/a0_COUT_7 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/e_cmp_ci_a_S1_7 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/e_cmp_ci_a_S0_7 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/bdcnt_bctr_cia_S1_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/bdcnt_bctr_cia_S0_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOB17_7 undriven or does
+
+ Page 144
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOB16_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOB15_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOB14_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOB13_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOB12_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOB11_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOB10_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOB9_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/fifo_out_data_1_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/fifo_out_data_1_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/fifo_out_data_1_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/fifo_out_data_1_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/fifo_out_data_1_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA17_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA16_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA15_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA14_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA13_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA12_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA11_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA10_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA9_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA8_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA7_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA6_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA5_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA4_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA3_7 undriven or does
+
+ Page 145
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA2_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA1_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0_DOA0_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOB17_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOB16_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOB15_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOB14_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOB13_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOB12_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOB11_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOB10_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOB9_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA17_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA16_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA15_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA14_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA13_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA12_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA11_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA10_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA9_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA8_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA7_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA6_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA5_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA4_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA3_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA2_7 undriven or does
+
+ Page 146
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA1_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1_DOA0_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOB17_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOB16_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOB15_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOB14_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOB13_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOB12_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOB11_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOB10_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOB9_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA17_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA16_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA15_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA14_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA13_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA12_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA11_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA10_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA9_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA8_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA7_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA6_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA5_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA4_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA3_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA2_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA1_7 undriven or does
+
+ Page 147
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2_DOA0_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/co5_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/r_ctr_cia_S1_8 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/r_ctr_cia_S0_8 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/w_ctr_cia_S1_8 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/w_ctr_cia_S0_8 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/a1_S1_8 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/a1_COUT_8 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/g_cmp_ci_a_S1_8 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/g_cmp_ci_a_S0_8 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/a0_S1_8 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/a0_COUT_8 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/e_cmp_ci_a_S1_8 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/e_cmp_ci_a_S0_8 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/bdcnt_bctr_cia_S1_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/bdcnt_bctr_cia_S0_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOB17_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOB16_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOB15_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOB14_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOB13_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOB12_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOB11_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOB10_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOB9_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/fifo_out_data_15_26 undriven or does
+
+ Page 148
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/fifo_out_data_15_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/fifo_out_data_15_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/fifo_out_data_15_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/fifo_out_data_15_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA17_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA16_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA15_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA14_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA13_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA12_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA11_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA10_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA9_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA8_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA7_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA6_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA5_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA4_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA3_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA2_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA1_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0_DOA0_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOB17_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOB16_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOB15_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOB14_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOB13_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOB12_8 undriven or
+
+ Page 149
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOB11_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOB10_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOB9_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA17_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA16_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA15_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA14_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA13_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA12_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA11_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA10_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA9_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA8_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA7_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA6_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA5_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA4_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA3_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA2_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA1_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1_DOA0_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOB17_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOB16_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOB15_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOB14_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOB13_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOB12_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOB11_8 undriven or
+
+ Page 150
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOB10_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOB9_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA17_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA16_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA15_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA14_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA13_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA12_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA11_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA10_8 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA9_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA8_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA7_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA6_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA5_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA4_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA3_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA2_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA1_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2_DOA0_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/co5_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/r_ctr_cia_S1_9 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/r_ctr_cia_S0_9 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/w_ctr_cia_S1_9 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/w_ctr_cia_S0_9 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/a1_S1_9 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/a1_COUT_9 undriven or does not drive
+
+ Page 151
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/g_cmp_ci_a_S1_9 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/g_cmp_ci_a_S0_9 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/a0_S1_9 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/a0_COUT_9 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/e_cmp_ci_a_S1_9 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/e_cmp_ci_a_S0_9 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/bdcnt_bctr_cia_S1_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/bdcnt_bctr_cia_S0_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOB17_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOB16_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOB15_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOB14_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOB13_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOB12_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOB11_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOB10_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOB9_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/fifo_out_data_3_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/fifo_out_data_3_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/fifo_out_data_3_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/fifo_out_data_3_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/fifo_out_data_3_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA17_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA16_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA15_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA14_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA13_9 undriven or does
+
+ Page 152
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA12_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA11_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA10_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA9_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA8_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA7_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA6_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA5_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA4_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA3_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA2_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA1_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0_DOA0_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOB17_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOB16_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOB15_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOB14_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOB13_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOB12_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOB11_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOB10_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOB9_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA17_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA16_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA15_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA14_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA13_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA12_9 undriven or does
+
+ Page 153
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA11_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA10_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA9_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA8_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA7_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA6_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA5_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA4_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA3_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA2_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA1_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1_DOA0_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOB17_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOB16_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOB15_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOB14_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOB13_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOB12_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOB11_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOB10_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOB9_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA17_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA16_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA15_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA14_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA13_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA12_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA11_9 undriven or does
+
+ Page 154
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA10_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA9_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA8_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA7_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA6_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA5_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA4_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA3_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA2_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA1_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2_DOA0_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/co5_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/r_ctr_cia_S1_10 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/r_ctr_cia_S0_10 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/w_ctr_cia_S1_10 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/w_ctr_cia_S0_10 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/a1_S1_10 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/a1_COUT_10 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/g_cmp_ci_a_S1_10 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/g_cmp_ci_a_S0_10 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/a0_S1_10 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/a0_COUT_10 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/e_cmp_ci_a_S1_10 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/e_cmp_ci_a_S0_10 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/bdcnt_bctr_cia_S1_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/bdcnt_bctr_cia_S0_10 undriven or does
+
+ Page 155
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOB17_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOB16_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOB15_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOB14_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOB13_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOB12_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOB11_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOB10_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOB9_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/fifo_out_data_0_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/fifo_out_data_0_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/fifo_out_data_0_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/fifo_out_data_0_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/fifo_out_data_0_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA17_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA16_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA15_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA14_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA13_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA12_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA11_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA10_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA9_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA8_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA7_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA6_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA5_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA4_10 undriven or does
+
+ Page 156
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA3_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA2_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA1_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0_DOA0_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOB17_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOB16_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOB15_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOB14_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOB13_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOB12_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOB11_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOB10_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOB9_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA17_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA16_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA15_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA14_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA13_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA12_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA11_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA10_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA9_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA8_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA7_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA6_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA5_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA4_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA3_10 undriven or does
+
+ Page 157
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA2_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA1_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1_DOA0_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOB17_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOB16_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOB15_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOB14_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOB13_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOB12_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOB11_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOB10_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOB9_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA17_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA16_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA15_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA14_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA13_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA12_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA11_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA10_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA9_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA8_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA7_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA6_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA5_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA4_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA3_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA2_10 undriven or does
+
+ Page 158
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA1_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2_DOA0_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/co5_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/r_ctr_cia_S1_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/r_ctr_cia_S0_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/w_ctr_cia_S1_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/w_ctr_cia_S0_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/a1_S1_11 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/a1_COUT_11 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/g_cmp_ci_a_S1_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/g_cmp_ci_a_S0_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/a0_S1_11 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/a0_COUT_11 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/e_cmp_ci_a_S1_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/e_cmp_ci_a_S0_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/bdcnt_bctr_cia_S1_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/bdcnt_bctr_cia_S0_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOB17_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOB16_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOB15_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOB14_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOB13_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOB12_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOB11_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOB10_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOB9_11 undriven or does
+
+ Page 159
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/fifo_out_data_8_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/fifo_out_data_8_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/fifo_out_data_8_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/fifo_out_data_8_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/fifo_out_data_8_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA17_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA16_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA15_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA14_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA13_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA12_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA11_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA10_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA9_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA8_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA7_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA6_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA5_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA4_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA3_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA2_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA1_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0_DOA0_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOB17_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOB16_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOB15_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOB14_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOB13_11 undriven or
+
+ Page 160
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOB12_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOB11_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOB10_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOB9_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA17_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA16_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA15_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA14_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA13_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA12_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA11_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA10_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA9_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA8_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA7_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA6_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA5_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA4_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA3_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA2_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA1_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1_DOA0_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOB17_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOB16_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOB15_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOB14_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOB13_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOB12_11 undriven or
+
+ Page 161
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOB11_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOB10_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOB9_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA17_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA16_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA15_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA14_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA13_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA12_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA11_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA10_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA9_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA8_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA7_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA6_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA5_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA4_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA3_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA2_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA1_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2_DOA0_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/co5_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/r_ctr_cia_S1_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/r_ctr_cia_S0_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/w_ctr_cia_S1_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/w_ctr_cia_S0_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/a1_S1_12 undriven or does not drive
+
+ Page 162
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/a1_COUT_12 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/g_cmp_ci_a_S1_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/g_cmp_ci_a_S0_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/a0_S1_12 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/a0_COUT_12 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/e_cmp_ci_a_S1_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/e_cmp_ci_a_S0_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/bdcnt_bctr_cia_S1_12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/bdcnt_bctr_cia_S0_12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOB17_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOB16_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOB15_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOB14_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOB13_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOB12_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOB11_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOB10_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOB9_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/fifo_out_data_11_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/fifo_out_data_11_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/fifo_out_data_11_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/fifo_out_data_11_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/fifo_out_data_11_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA17_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA16_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA15_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA14_12 undriven or
+
+ Page 163
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA13_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA12_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA11_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA10_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA9_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA8_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA7_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA6_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA5_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA4_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA3_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA2_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA1_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0_DOA0_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOB17_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOB16_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOB15_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOB14_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOB13_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOB12_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOB11_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOB10_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOB9_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA17_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA16_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA15_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA14_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA13_12 undriven or
+
+ Page 164
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA12_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA11_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA10_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA9_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA8_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA7_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA6_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA5_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA4_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA3_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA2_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA1_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1_DOA0_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOB17_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOB16_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOB15_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOB14_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOB13_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOB12_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOB11_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOB10_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOB9_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA17_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA16_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA15_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA14_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA13_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA12_12 undriven or
+
+ Page 165
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA11_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA10_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA9_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA8_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA7_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA6_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA5_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA4_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA3_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA2_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA1_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2_DOA0_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/co5_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/r_ctr_cia_S1_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/r_ctr_cia_S0_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/w_ctr_cia_S1_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/w_ctr_cia_S0_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/a1_S1_13 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/a1_COUT_13 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/g_cmp_ci_a_S1_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/g_cmp_ci_a_S0_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/a0_S1_13 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/a0_COUT_13 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/e_cmp_ci_a_S1_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/e_cmp_ci_a_S0_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/bdcnt_bctr_cia_S1_13 undriven or does
+
+ Page 166
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/bdcnt_bctr_cia_S0_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOB17_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOB16_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOB15_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOB14_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOB13_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOB12_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOB11_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOB10_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOB9_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/fifo_out_data_2_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/fifo_out_data_2_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/fifo_out_data_2_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/fifo_out_data_2_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/fifo_out_data_2_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA17_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA16_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA15_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA14_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA13_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA12_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA11_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA10_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA9_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA8_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA7_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA6_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA5_13 undriven or does
+
+ Page 167
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA4_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA3_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA2_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA1_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0_DOA0_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOB17_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOB16_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOB15_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOB14_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOB13_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOB12_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOB11_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOB10_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOB9_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA17_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA16_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA15_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA14_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA13_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA12_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA11_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA10_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA9_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA8_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA7_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA6_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA5_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA4_13 undriven or does
+
+ Page 168
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA3_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA2_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA1_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1_DOA0_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOB17_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOB16_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOB15_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOB14_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOB13_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOB12_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOB11_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOB10_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOB9_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA17_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA16_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA15_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA14_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA13_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA12_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA11_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA10_13 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA9_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA8_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA7_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA6_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA5_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA4_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA3_13 undriven or does
+
+ Page 169
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA2_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA1_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2_DOA0_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/co5_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/r_ctr_cia_S1_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/r_ctr_cia_S0_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/co5_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/w_ctr_cia_S1_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/w_ctr_cia_S0_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/a1_S1_14 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/a1_COUT_14 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/g_cmp_ci_a_S1_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/g_cmp_ci_a_S0_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/a0_S1_14 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/a0_COUT_14 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/e_cmp_ci_a_S1_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/e_cmp_ci_a_S0_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/bdcnt_bctr_cia_S1_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/bdcnt_bctr_cia_S0_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOB17_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOB16_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOB15_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOB14_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOB13_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOB12_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOB11_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOB10_14 undriven or
+
+ Page 170
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOB9_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/fifo_out_data_5_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/fifo_out_data_5_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/fifo_out_data_5_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/fifo_out_data_5_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/fifo_out_data_5_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA17_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA16_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA15_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA14_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA13_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA12_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA11_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA10_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA9_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA8_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA7_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA6_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA5_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA4_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA3_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA2_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA1_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0_DOA0_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOB17_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOB16_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOB15_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOB14_14 undriven or
+
+ Page 171
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOB13_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOB12_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOB11_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOB10_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOB9_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA17_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA16_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA15_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA14_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA13_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA12_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA11_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA10_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA9_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA8_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA7_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA6_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA5_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA4_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA3_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA2_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA1_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1_DOA0_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOB17_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOB16_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOB15_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOB14_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOB13_14 undriven or
+
+ Page 172
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOB12_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOB11_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOB10_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOB9_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA17_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA16_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA15_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA14_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA13_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA12_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA11_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA10_14 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA9_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA8_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA7_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA6_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA5_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA4_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA3_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA2_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA1_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2_DOA0_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/a2_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/a2_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/af_cmp_ci_a_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/af_cmp_ci_a_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/r_ctr_cia_S1_15 undriven or does not
+
+ Page 173
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/r_ctr_cia_S0_15 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/w_ctr_cia_S1_15 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/w_ctr_cia_S0_15 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/a1_S1_15 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/a1_COUT_15 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/g_cmp_ci_a_S1_15 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/g_cmp_ci_a_S0_15 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/a0_S1_15 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/a0_COUT_15 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/e_cmp_ci_a_S1_15 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/e_cmp_ci_a_S0_15 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/bdcnt_bctr_5_NC1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/bdcnt_bctr_cia_S1_15 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/bdcnt_bctr_cia_S0_15 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA17 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA16 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA15 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA10 undriven or does
+
+ Page 174
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0_DOA0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/a2_S1_0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/a2_COUT_0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/af_cmp_ci_a_S1_0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/af_cmp_ci_a_S0_0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/r_ctr_cia_S1_16 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/r_ctr_cia_S0_16 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/w_ctr_cia_S1_16 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/w_ctr_cia_S0_16 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/a1_S1_16 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/a1_COUT_16 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/g_cmp_ci_a_S1_16 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/g_cmp_ci_a_S0_16 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/a0_S1_16 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/a0_COUT_16 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/e_cmp_ci_a_S1_16 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/e_cmp_ci_a_S0_16 undriven or does not
+
+ Page 175
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/bdcnt_bctr_5_NC1_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/bdcnt_bctr_cia_S1_16 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/bdcnt_bctr_cia_S0_16 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA17_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA16_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA15_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA14_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA13_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA12_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA11_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA10_0 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA9_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA8_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA7_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA6_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA5_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA4_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA3_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA2_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA1_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0_DOA0_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_a2_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_a2 undriven or does not drive
+
+ Page 176
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_af_cmp_ci_a_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_af_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_r_ctr_cia_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_r_ctr_cia undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_w_ctr_cia_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_w_ctr_cia undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_a1_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_a1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_g_cmp_ci_a_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_g_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_a0_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_a0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_e_cmp_ci_a_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_e_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_bdcnt_bctr_5 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_bdcnt_bctr_cia_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_bdcnt_bctr_cia undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_11 undriven or does
+
+ Page 177
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_17 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_16 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_15 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/un1_pdp_ram_0_0_0_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/a2_S1_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/a2_COUT_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/af_cmp_ci_a_S1_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/af_cmp_ci_a_S0_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/r_ctr_cia_S1_17 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/r_ctr_cia_S0_17 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/w_ctr_cia_S1_17 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/w_ctr_cia_S0_17 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/a1_S1_17 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/a1_COUT_17 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/g_cmp_ci_a_S1_17 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/g_cmp_ci_a_S0_17 undriven or does not
+
+ Page 178
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/a0_S1_17 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/a0_COUT_17 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/e_cmp_ci_a_S1_17 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/e_cmp_ci_a_S0_17 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/bdcnt_bctr_5_NC1_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/bdcnt_bctr_cia_S1_17 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/bdcnt_bctr_cia_S0_17 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA17_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA16_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA15_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA14_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA13_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA12_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA11_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA10_1 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA9_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA8_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA7_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA6_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA5_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA4_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA3_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA2_1 undriven or does
+
+ Page 179
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA1_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0_DOA0_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/a2_S1_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/a2_COUT_2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/af_cmp_ci_a_S1_2 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/af_cmp_ci_a_S0_2 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/r_ctr_cia_S1_18 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/r_ctr_cia_S0_18 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/w_ctr_cia_S1_18 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/w_ctr_cia_S0_18 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/a1_S1_18 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/a1_COUT_18 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/g_cmp_ci_a_S1_18 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/g_cmp_ci_a_S0_18 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/a0_S1_18 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/a0_COUT_18 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/e_cmp_ci_a_S1_18 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/e_cmp_ci_a_S0_18 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/bdcnt_bctr_5_NC1_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/bdcnt_bctr_cia_S1_18 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/bdcnt_bctr_cia_S0_18 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+
+ Page 180
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA17_2 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA16_2 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA15_2 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA14_2 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA13_2 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA12_2 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA11_2 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA10_2 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA9_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA8_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA7_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA6_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA5_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA4_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA3_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA2_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA1_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0_DOA0_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_a2_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_a2 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_af_cmp_ci_a_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_af_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_r_ctr_cia_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_r_ctr_cia undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_w_ctr_cia_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_w_ctr_cia undriven or does not
+
+ Page 181
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_a1_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_a1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_g_cmp_ci_a_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_g_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_a0_1 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_a0 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_e_cmp_ci_a_1 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_e_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_bdcnt_bctr_5 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_bdcnt_bctr_cia_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_bdcnt_bctr_cia undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_1 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_17 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_16 undriven or does
+
+ Page 182
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_15 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_14 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_2 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/un1_pdp_ram_0_0_0_13 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/a2_S1_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/a2_COUT_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/af_cmp_ci_a_S1_3 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/af_cmp_ci_a_S0_3 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/r_ctr_cia_S1_19 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/r_ctr_cia_S0_19 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/w_ctr_cia_S1_19 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/w_ctr_cia_S0_19 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/a1_S1_19 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/a1_COUT_19 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/g_cmp_ci_a_S1_19 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/g_cmp_ci_a_S0_19 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/a0_S1_19 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/a0_COUT_19 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/e_cmp_ci_a_S1_19 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/e_cmp_ci_a_S0_19 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/bdcnt_bctr_5_NC1_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/bdcnt_bctr_cia_S1_19 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/bdcnt_bctr_cia_S0_19 undriven or does
+
+ Page 183
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA17_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA16_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA15_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA14_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA13_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA12_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA11_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA10_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA9_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA8_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA7_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA6_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA5_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA4_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA3_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA2_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA1_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0_DOA0_3 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/a2_S1_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/a2_COUT_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/af_cmp_ci_a_S1_4 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/af_cmp_ci_a_S0_4 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/r_ctr_cia_S1_20 undriven or does not
+
+ Page 184
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/r_ctr_cia_S0_20 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/w_ctr_cia_S1_20 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/w_ctr_cia_S0_20 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/a1_S1_20 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/a1_COUT_20 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/g_cmp_ci_a_S1_20 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/g_cmp_ci_a_S0_20 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/a0_S1_20 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/a0_COUT_20 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/e_cmp_ci_a_S1_20 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/e_cmp_ci_a_S0_20 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/bdcnt_bctr_5_NC1_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/bdcnt_bctr_cia_S1_20 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/bdcnt_bctr_cia_S0_20 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA17_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA16_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA15_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA14_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA13_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA12_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA11_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA10_4 undriven or does
+
+ Page 185
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA9_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA8_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA7_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA6_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA5_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA4_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA3_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA2_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA1_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0_DOA0_4 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/a2_S1_5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/a2_COUT_5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/af_cmp_ci_a_S1_5 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/af_cmp_ci_a_S0_5 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/r_ctr_cia_S1_21 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/r_ctr_cia_S0_21 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/w_ctr_cia_S1_21 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/w_ctr_cia_S0_21 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/a1_S1_21 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/a1_COUT_21 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/g_cmp_ci_a_S1_21 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/g_cmp_ci_a_S0_21 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/a0_S1_21 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/a0_COUT_21 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/e_cmp_ci_a_S1_21 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/e_cmp_ci_a_S0_21 undriven or does not
+
+ Page 186
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/bdcnt_bctr_5_NC1_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/bdcnt_bctr_cia_S1_21 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/bdcnt_bctr_cia_S0_21 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA17_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA16_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA15_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA14_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA13_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA12_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA11_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA10_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA9_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA8_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA7_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA6_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA5_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA4_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA3_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA2_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA1_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0_DOA0_5 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/a2_S1_6 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/a2_COUT_6 undriven or does not drive
+
+ Page 187
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/af_cmp_ci_a_S1_6 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/af_cmp_ci_a_S0_6 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/r_ctr_cia_S1_22 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/r_ctr_cia_S0_22 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/w_ctr_cia_S1_22 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/w_ctr_cia_S0_22 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/a1_S1_22 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/a1_COUT_22 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/g_cmp_ci_a_S1_22 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/g_cmp_ci_a_S0_22 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/a0_S1_22 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/a0_COUT_22 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/e_cmp_ci_a_S1_22 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/e_cmp_ci_a_S0_22 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/bdcnt_bctr_5_NC1_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/bdcnt_bctr_cia_S1_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/bdcnt_bctr_cia_S0_22 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA17_6 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA16_6 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA15_6 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA14_6 undriven or
+
+ Page 188
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA13_6 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA12_6 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA11_6 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA10_6 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA9_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA8_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA7_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA6_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA5_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA4_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA3_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA2_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA1_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0_DOA0_6 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/a2_S1_7 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/a2_COUT_7 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/af_cmp_ci_a_S1_7 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/af_cmp_ci_a_S0_7 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/r_ctr_cia_S1_23 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/r_ctr_cia_S0_23 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/w_ctr_cia_S1_23 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/w_ctr_cia_S0_23 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/a1_S1_23 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/a1_COUT_23 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/g_cmp_ci_a_S1_23 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/g_cmp_ci_a_S0_23 undriven or does not
+
+ Page 189
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/a0_S1_23 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/a0_COUT_23 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/e_cmp_ci_a_S1_23 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/e_cmp_ci_a_S0_23 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/bdcnt_bctr_5_NC1_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/bdcnt_bctr_cia_S1_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/bdcnt_bctr_cia_S0_23 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA17_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA16_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA15_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA14_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA13_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA12_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA11_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA10_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA9_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA8_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA7_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA6_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA5_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA4_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA3_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA2_7 undriven or does
+
+ Page 190
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA1_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0_DOA0_7 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/a2_S1_8 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/a2_COUT_8 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/af_cmp_ci_a_S1_8 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/af_cmp_ci_a_S0_8 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/r_ctr_cia_S1_24 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/r_ctr_cia_S0_24 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/w_ctr_cia_S1_24 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/w_ctr_cia_S0_24 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/a1_S1_24 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/a1_COUT_24 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/g_cmp_ci_a_S1_24 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/g_cmp_ci_a_S0_24 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/a0_S1_24 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/a0_COUT_24 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/e_cmp_ci_a_S1_24 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/e_cmp_ci_a_S0_24 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/bdcnt_bctr_5_NC1_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/bdcnt_bctr_cia_S1_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/bdcnt_bctr_cia_S0_24 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+
+ Page 191
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA17_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA16_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA15_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA14_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA13_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA12_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA11_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA10_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA9_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA8_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA7_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA6_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA5_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA4_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA3_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA2_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA1_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0_DOA0_8 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/a2_S1_9 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/a2_COUT_9 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/af_cmp_ci_a_S1_9 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/af_cmp_ci_a_S0_9 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/r_ctr_cia_S1_25 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/r_ctr_cia_S0_25 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/w_ctr_cia_S1_25 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/w_ctr_cia_S0_25 undriven or does not
+
+ Page 192
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/a1_S1_25 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/a1_COUT_25 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/g_cmp_ci_a_S1_25 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/g_cmp_ci_a_S0_25 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/a0_S1_25 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/a0_COUT_25 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/e_cmp_ci_a_S1_25 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/e_cmp_ci_a_S0_25 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/bdcnt_bctr_5_NC1_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/bdcnt_bctr_cia_S1_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/bdcnt_bctr_cia_S0_25 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA17_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA16_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA15_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA14_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA13_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA12_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA11_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA10_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA9_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA8_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA7_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA6_9 undriven or does
+
+ Page 193
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA5_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA4_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA3_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA2_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA1_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0_DOA0_9 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/a2_S1_10 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/a2_COUT_10 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/af_cmp_ci_a_S1_10 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/af_cmp_ci_a_S0_10 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/r_ctr_cia_S1_26 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/r_ctr_cia_S0_26 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/w_ctr_cia_S1_26 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/w_ctr_cia_S0_26 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/a1_S1_26 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/a1_COUT_26 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/g_cmp_ci_a_S1_26 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/g_cmp_ci_a_S0_26 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/a0_S1_26 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/a0_COUT_26 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/e_cmp_ci_a_S1_26 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/e_cmp_ci_a_S0_26 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/bdcnt_bctr_5_NC1_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/bdcnt_bctr_cia_S1_26 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/bdcnt_bctr_cia_S0_26 undriven or does
+
+ Page 194
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA17_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA16_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA15_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA14_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA13_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA12_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA11_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA10_10 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA9_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA8_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA7_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA6_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA5_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA4_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA3_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA2_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA1_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0_DOA0_10 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/a2_S1_11 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/a2_COUT_11 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/af_cmp_ci_a_S1_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/af_cmp_ci_a_S0_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/r_ctr_cia_S1_27 undriven or does not
+
+ Page 195
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/r_ctr_cia_S0_27 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/w_ctr_cia_S1_27 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/w_ctr_cia_S0_27 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/a1_S1_27 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/a1_COUT_27 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/g_cmp_ci_a_S1_27 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/g_cmp_ci_a_S0_27 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/a0_S1_27 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/a0_COUT_27 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/e_cmp_ci_a_S1_27 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/e_cmp_ci_a_S0_27 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/bdcnt_bctr_5_NC1_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/bdcnt_bctr_cia_S1_27 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/bdcnt_bctr_cia_S0_27 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA17_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA16_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA15_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA14_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA13_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA12_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA11_11 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA10_11 undriven or
+
+ Page 196
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA9_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA8_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA7_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA6_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA5_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA4_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA3_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA2_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA1_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0_DOA0_11 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/a2_S1_12 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/a2_COUT_12 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/af_cmp_ci_a_S1_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/af_cmp_ci_a_S0_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/r_ctr_cia_S1_28 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/r_ctr_cia_S0_28 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/w_ctr_cia_S1_28 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/w_ctr_cia_S0_28 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/a1_S1_28 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/a1_COUT_28 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/g_cmp_ci_a_S1_28 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/g_cmp_ci_a_S0_28 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/a0_S1_28 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/a0_COUT_28 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/e_cmp_ci_a_S1_28 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/e_cmp_ci_a_S0_28 undriven or does not
+
+ Page 197
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/bdcnt_bctr_5_NC1_12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/bdcnt_bctr_cia_S1_28 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/bdcnt_bctr_cia_S0_28 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/un1_THE_LFIFO_14 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/un1_THE_LFIFO_13 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/un1_THE_LFIFO_12 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/un1_THE_LFIFO_11 undriven or does not
+ drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA17_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA16_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA15_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA14_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA13_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA12_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA11_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA10_12 undriven or
+ does not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA9_12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA8_12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA7_12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA6_12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA5_12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA4_12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA3_12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA2_12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA1_12 undriven or does
+ not drive anything - clipped.
+Signal THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0_DOA0_12 undriven or does
+ not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/un1_ce_frm_ctr_2_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_PED_CORR_STAGE/un1_ce_frm_ctr_2_cry_0_0_S0 undriven or does not drive
+
+ Page 198
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ anything - clipped.
+Signal THE_PED_CORR_STAGE/un1_ce_frm_ctr_2_s_3_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_PED_CORR_STAGE/un1_ce_frm_ctr_2_s_3_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_PED_CORR_STAGE/un1_total_sum_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_PED_CORR_STAGE/un1_total_sum_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_PED_CORR_STAGE/un1_total_sum_s_15_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_PED_CORR_STAGE/un1_total_sum_s_15_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_PED_CORR_STAGE/un2_small_sum_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_PED_CORR_STAGE/un2_small_sum_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_PED_CORR_STAGE/un2_small_sum_cry_3_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_PED_CORR_STAGE/un1_buf_addr_ce_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_PED_CORR_STAGE/un1_buf_addr_ce_s_5_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_PED_CORR_STAGE/un1_buf_addr_ce_s_5_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_PED_CORR_STAGE/thr_addr_CR6_ram_0_DO3 undriven or does not drive
+ anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un293_next_row_match_0_I_1_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un293_next_row_match_0_I_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un293_next_row_match_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un293_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un293_next_row_match_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un293_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un269_next_row_match_0_I_1_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un269_next_row_match_0_I_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un269_next_row_match_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un269_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un269_next_row_match_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un269_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un245_next_row_match_0_I_1_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un245_next_row_match_0_I_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un245_next_row_match_0_I_10_0_S1
+
+ Page 199
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un245_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un245_next_row_match_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un245_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un221_next_row_match_0_I_1_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un221_next_row_match_0_I_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un221_next_row_match_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un221_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un221_next_row_match_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un221_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un197_next_row_match_0_I_1_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un197_next_row_match_0_I_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un197_next_row_match_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un197_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un197_next_row_match_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un197_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un173_next_row_match_0_I_1_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un173_next_row_match_0_I_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un173_next_row_match_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un173_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un173_next_row_match_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un173_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un149_next_row_match_0_I_1_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un149_next_row_match_0_I_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un149_next_row_match_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un149_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un149_next_row_match_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un149_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un125_next_row_match_0_I_1_0_S1
+
+ Page 200
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un125_next_row_match_0_I_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un125_next_row_match_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un125_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un125_next_row_match_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un125_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un101_next_row_match_0_I_1_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un101_next_row_match_0_I_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un101_next_row_match_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un101_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un101_next_row_match_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un101_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un77_next_row_match_0_I_1_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un77_next_row_match_0_I_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un77_next_row_match_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un77_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un77_next_row_match_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un77_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un53_next_row_match_0_I_1_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un53_next_row_match_0_I_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un53_next_row_match_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un53_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un53_next_row_match_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un53_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un29_next_row_match_0_I_1_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un29_next_row_match_0_I_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un29_next_row_match_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un29_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un29_next_row_match_0_I_28_0_S0
+
+ Page 201
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un29_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un5_next_row_match_0_I_1_0_S1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un5_next_row_match_0_I_1_0_S0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un5_next_row_match_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un5_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un5_next_row_match_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un5_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un365_next_row_match_0_I_1_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un365_next_row_match_0_I_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un365_next_row_match_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un365_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un365_next_row_match_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un365_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un341_next_row_match_0_I_1_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un341_next_row_match_0_I_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un341_next_row_match_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un341_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un341_next_row_match_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un341_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un317_next_row_match_0_I_1_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un317_next_row_match_0_I_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un317_next_row_match_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un317_next_row_match_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un317_next_row_match_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/THE_REF_ROW_SEL/un317_next_row_match_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_0_THE_BUF_TOC/next_frames_avail_cry_0_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_0_THE_BUF_TOC/next_frames_avail_cry_0_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_0_THE_BUF_TOC/next_frames_avail_cry_1_0_S1
+
+ Page 202
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_0_THE_BUF_TOC/next_frames_avail_cry_1_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_0_THE_BUF_TOC/next_frames_avail_cry_3_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_0_THE_BUF_TOC/next_frames_avail_cry_3_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_0_THE_BUF_TOC/next_frames_avail_cry_4_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_0_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_2_THE_BUF_TOC/next_frames_avail_cry_0_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_2_THE_BUF_TOC/next_frames_avail_cry_0_0_S0_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_2_THE_BUF_TOC/next_frames_avail_cry_1_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_2_THE_BUF_TOC/next_frames_avail_cry_1_0_S0_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_2_THE_BUF_TOC/next_frames_avail_cry_3_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_2_THE_BUF_TOC/next_frames_avail_cry_3_0_S0_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_2_THE_BUF_TOC/next_frames_avail_cry_4_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_2_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_6_THE_BUF_TOC/next_frames_avail_cry_0_0_S1_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_6_THE_BUF_TOC/next_frames_avail_cry_0_0_S0_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_6_THE_BUF_TOC/next_frames_avail_cry_1_0_S1_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_6_THE_BUF_TOC/next_frames_avail_cry_1_0_S0_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_6_THE_BUF_TOC/next_frames_avail_cry_3_0_S1_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_6_THE_BUF_TOC/next_frames_avail_cry_3_0_S0_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_6_THE_BUF_TOC/next_frames_avail_cry_4_0_S1_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_6_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_15_THE_BUF_TOC/next_frames_avail_cry_0_0_S1_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_15_THE_BUF_TOC/next_frames_avail_cry_0_0_S0_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_15_THE_BUF_TOC/next_frames_avail_cry_1_0_S1_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_15_THE_BUF_TOC/next_frames_avail_cry_1_0_S0_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_15_THE_BUF_TOC/next_frames_avail_cry_3_0_S1_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_15_THE_BUF_TOC/next_frames_avail_cry_3_0_S0_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_15_THE_BUF_TOC/next_frames_avail_cry_4_0_S1_2
+
+ Page 203
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal
+ THE_PED_CORR_STAGE/GEN_TOC_15_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_12_THE_BUF_TOC/next_frames_avail_cry_0_0_S1_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_12_THE_BUF_TOC/next_frames_avail_cry_0_0_S0_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_12_THE_BUF_TOC/next_frames_avail_cry_1_0_S1_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_12_THE_BUF_TOC/next_frames_avail_cry_1_0_S0_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_12_THE_BUF_TOC/next_frames_avail_cry_3_0_S1_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_12_THE_BUF_TOC/next_frames_avail_cry_3_0_S0_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_12_THE_BUF_TOC/next_frames_avail_cry_4_0_S1_3
+ undriven or does not drive anything - clipped.
+Signal
+ THE_PED_CORR_STAGE/GEN_TOC_12_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_14_THE_BUF_TOC/next_frames_avail_cry_0_0_S1_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_14_THE_BUF_TOC/next_frames_avail_cry_0_0_S0_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_14_THE_BUF_TOC/next_frames_avail_cry_1_0_S1_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_14_THE_BUF_TOC/next_frames_avail_cry_1_0_S0_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_14_THE_BUF_TOC/next_frames_avail_cry_3_0_S1_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_14_THE_BUF_TOC/next_frames_avail_cry_3_0_S0_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_14_THE_BUF_TOC/next_frames_avail_cry_4_0_S1_4
+ undriven or does not drive anything - clipped.
+Signal
+ THE_PED_CORR_STAGE/GEN_TOC_14_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_9_THE_BUF_TOC/next_frames_avail_cry_0_0_S1_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_9_THE_BUF_TOC/next_frames_avail_cry_0_0_S0_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_9_THE_BUF_TOC/next_frames_avail_cry_1_0_S1_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_9_THE_BUF_TOC/next_frames_avail_cry_1_0_S0_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_9_THE_BUF_TOC/next_frames_avail_cry_3_0_S1_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_9_THE_BUF_TOC/next_frames_avail_cry_3_0_S0_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_9_THE_BUF_TOC/next_frames_avail_cry_4_0_S1_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_9_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_8_THE_BUF_TOC/next_frames_avail_cry_0_0_S1_6
+ undriven or does not drive anything - clipped.
+
+ Page 204
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_TOC_8_THE_BUF_TOC/next_frames_avail_cry_0_0_S0_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_8_THE_BUF_TOC/next_frames_avail_cry_1_0_S1_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_8_THE_BUF_TOC/next_frames_avail_cry_1_0_S0_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_8_THE_BUF_TOC/next_frames_avail_cry_3_0_S1_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_8_THE_BUF_TOC/next_frames_avail_cry_3_0_S0_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_8_THE_BUF_TOC/next_frames_avail_cry_4_0_S1_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_8_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_3_THE_BUF_TOC/next_frames_avail_cry_0_0_S1_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_3_THE_BUF_TOC/next_frames_avail_cry_0_0_S0_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_3_THE_BUF_TOC/next_frames_avail_cry_1_0_S1_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_3_THE_BUF_TOC/next_frames_avail_cry_1_0_S0_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_3_THE_BUF_TOC/next_frames_avail_cry_3_0_S1_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_3_THE_BUF_TOC/next_frames_avail_cry_3_0_S0_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_3_THE_BUF_TOC/next_frames_avail_cry_4_0_S1_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_3_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_7_THE_BUF_TOC/next_frames_avail_cry_0_0_S1_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_7_THE_BUF_TOC/next_frames_avail_cry_0_0_S0_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_7_THE_BUF_TOC/next_frames_avail_cry_1_0_S1_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_7_THE_BUF_TOC/next_frames_avail_cry_1_0_S0_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_7_THE_BUF_TOC/next_frames_avail_cry_3_0_S1_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_7_THE_BUF_TOC/next_frames_avail_cry_3_0_S0_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_7_THE_BUF_TOC/next_frames_avail_cry_4_0_S1_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_7_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_10_THE_BUF_TOC/next_frames_avail_cry_0_0_S1_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_10_THE_BUF_TOC/next_frames_avail_cry_0_0_S0_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_10_THE_BUF_TOC/next_frames_avail_cry_1_0_S1_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_10_THE_BUF_TOC/next_frames_avail_cry_1_0_S0_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_10_THE_BUF_TOC/next_frames_avail_cry_3_0_S1_9
+ undriven or does not drive anything - clipped.
+
+ Page 205
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_TOC_10_THE_BUF_TOC/next_frames_avail_cry_3_0_S0_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_10_THE_BUF_TOC/next_frames_avail_cry_4_0_S1_9
+ undriven or does not drive anything - clipped.
+Signal
+ THE_PED_CORR_STAGE/GEN_TOC_10_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_1_THE_BUF_TOC/next_frames_avail_cry_0_0_S1_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_1_THE_BUF_TOC/next_frames_avail_cry_0_0_S0_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_1_THE_BUF_TOC/next_frames_avail_cry_1_0_S1_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_1_THE_BUF_TOC/next_frames_avail_cry_1_0_S0_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_1_THE_BUF_TOC/next_frames_avail_cry_3_0_S1_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_1_THE_BUF_TOC/next_frames_avail_cry_3_0_S0_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_1_THE_BUF_TOC/next_frames_avail_cry_4_0_S1_10
+ undriven or does not drive anything - clipped.
+Signal
+ THE_PED_CORR_STAGE/GEN_TOC_1_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_13_THE_BUF_TOC/next_frames_avail_cry_0_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_13_THE_BUF_TOC/next_frames_avail_cry_0_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_13_THE_BUF_TOC/next_frames_avail_cry_1_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_13_THE_BUF_TOC/next_frames_avail_cry_1_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_13_THE_BUF_TOC/next_frames_avail_cry_3_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_13_THE_BUF_TOC/next_frames_avail_cry_3_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_13_THE_BUF_TOC/next_frames_avail_cry_4_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_13_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT_
+ 11 undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_5_THE_BUF_TOC/next_frames_avail_cry_0_0_S1_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_5_THE_BUF_TOC/next_frames_avail_cry_0_0_S0_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_5_THE_BUF_TOC/next_frames_avail_cry_1_0_S1_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_5_THE_BUF_TOC/next_frames_avail_cry_1_0_S0_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_5_THE_BUF_TOC/next_frames_avail_cry_3_0_S1_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_5_THE_BUF_TOC/next_frames_avail_cry_3_0_S0_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_5_THE_BUF_TOC/next_frames_avail_cry_4_0_S1_12
+ undriven or does not drive anything - clipped.
+Signal
+ THE_PED_CORR_STAGE/GEN_TOC_5_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT_12
+
+ Page 206
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_4_THE_BUF_TOC/next_frames_avail_cry_0_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_4_THE_BUF_TOC/next_frames_avail_cry_0_0_S0_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_4_THE_BUF_TOC/next_frames_avail_cry_1_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_4_THE_BUF_TOC/next_frames_avail_cry_1_0_S0_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_4_THE_BUF_TOC/next_frames_avail_cry_3_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_4_THE_BUF_TOC/next_frames_avail_cry_3_0_S0_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_4_THE_BUF_TOC/next_frames_avail_cry_4_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal
+ THE_PED_CORR_STAGE/GEN_TOC_4_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_11_THE_BUF_TOC/next_frames_avail_cry_0_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_11_THE_BUF_TOC/next_frames_avail_cry_0_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_11_THE_BUF_TOC/next_frames_avail_cry_1_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_11_THE_BUF_TOC/next_frames_avail_cry_1_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_11_THE_BUF_TOC/next_frames_avail_cry_3_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_11_THE_BUF_TOC/next_frames_avail_cry_3_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_11_THE_BUF_TOC/next_frames_avail_cry_4_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_TOC_11_THE_BUF_TOC/next_frames_avail_cry_4_0_COUT_
+ 14 undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/nc_corr_data_q_0_cry_0_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/nc_corr_data_q_0_s_13_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/nc_corr_data_q_0_s_13_0_COUT_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/un3_loc_baseline_q_cry_0_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/un3_loc_baseline_q_cry_0_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/un3_loc_baseline_q_cry_12_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/un1_data_we_cry_0_0_S0_14 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/un1_data_we_s_9_0_S1_14 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/un1_data_we_s_9_0_COUT_14 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/un1_frame_int_cry_0_0_S0 undriven
+ or does not drive anything - clipped.
+
+ Page 207
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/un1_frame_int_cry_5_0_COUT undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/nc_corr_data_qq_1_s_13_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/ped_corr_data_q_1_cry_0_0_S1_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/ped_corr_data_q_1_cry_0_0_S0_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_0_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_0_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_1_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_1_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_3_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_3_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_5_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_5_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_7_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_7_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_9_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_9_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_11_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_11_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_13_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/thr_pass_comb_cry_13_0_COUT_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/frame_int_CR0_ram_DO2 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/frame_int_CR0_ram_DO3 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/frame_int_CR0_ram_DO1 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/nc_corr_data_q_0_cry_0_0_S0_13
+ undriven or does not drive anything - clipped.
+
+ Page 208
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/nc_corr_data_q_0_s_13_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/nc_corr_data_q_0_s_13_0_COUT_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/un3_loc_baseline_q_cry_0_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/un3_loc_baseline_q_cry_0_0_S0_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/un3_loc_baseline_q_cry_12_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/un1_data_we_cry_0_0_S0_13 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/un1_data_we_s_9_0_S1_13 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/un1_data_we_s_9_0_COUT_13 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/nc_corr_data_qq_1_s_13_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/ped_corr_data_q_1_cry_0_0_S1_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/ped_corr_data_q_1_cry_0_0_S0_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_0_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_0_0_S0_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_1_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_1_0_S0_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_3_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_3_0_S0_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_5_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_5_0_S0_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_7_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_7_0_S0_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_9_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_9_0_S0_13
+ undriven or does not drive anything - clipped.
+
+ Page 209
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_11_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_11_0_S0_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_13_0_S0_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_10_THE_ALU/thr_pass_comb_cry_13_0_COUT_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/nc_corr_data_q_0_cry_0_0_S0_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/nc_corr_data_q_0_s_13_0_S1_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/nc_corr_data_q_0_s_13_0_COUT_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/un3_loc_baseline_q_cry_0_0_S1_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/un3_loc_baseline_q_cry_0_0_S0_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/un3_loc_baseline_q_cry_12_0_S1_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/un1_data_we_cry_0_0_S0_12 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/un1_data_we_s_9_0_S1_12 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/un1_data_we_s_9_0_COUT_12 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/nc_corr_data_qq_1_s_13_0_S1_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/ped_corr_data_q_1_cry_0_0_S1_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/ped_corr_data_q_1_cry_0_0_S0_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_0_0_S1_12 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_0_0_S0_12 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_1_0_S1_12 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_1_0_S0_12 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_3_0_S1_12 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_3_0_S0_12 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_5_0_S1_12 undriven
+ or does not drive anything - clipped.
+
+ Page 210
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_5_0_S0_12 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_7_0_S1_12 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_7_0_S0_12 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_9_0_S1_12 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_9_0_S0_12 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_11_0_S1_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_11_0_S0_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_13_0_S0_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_4_THE_ALU/thr_pass_comb_cry_13_0_COUT_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/nc_corr_data_q_0_cry_0_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/nc_corr_data_q_0_s_13_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/nc_corr_data_q_0_s_13_0_COUT_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/un3_loc_baseline_q_cry_0_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/un3_loc_baseline_q_cry_0_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/un3_loc_baseline_q_cry_12_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/un1_data_we_cry_0_0_S0_11 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/un1_data_we_s_9_0_S1_11 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/un1_data_we_s_9_0_COUT_11 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/nc_corr_data_qq_1_s_13_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/ped_corr_data_q_1_cry_0_0_S1_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/ped_corr_data_q_1_cry_0_0_S0_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_0_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_0_0_S0_11
+ undriven or does not drive anything - clipped.
+
+ Page 211
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_1_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_1_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_3_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_3_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_5_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_5_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_7_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_7_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_9_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_9_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_11_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_11_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_13_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_11_THE_ALU/thr_pass_comb_cry_13_0_COUT_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/nc_corr_data_q_0_cry_0_0_S0_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/nc_corr_data_q_0_s_13_0_S1_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/nc_corr_data_q_0_s_13_0_COUT_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/un3_loc_baseline_q_cry_0_0_S1_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/un3_loc_baseline_q_cry_0_0_S0_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/un3_loc_baseline_q_cry_12_0_S1_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/un1_data_we_cry_0_0_S0_10 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/un1_data_we_s_9_0_S1_10 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/un1_data_we_s_9_0_COUT_10 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/nc_corr_data_qq_1_s_13_0_S1_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT_10
+ undriven or does not drive anything - clipped.
+
+ Page 212
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/ped_corr_data_q_1_cry_0_0_S1_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/ped_corr_data_q_1_cry_0_0_S0_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_0_0_S1_10 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_0_0_S0_10 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_1_0_S1_10 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_1_0_S0_10 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_3_0_S1_10 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_3_0_S0_10 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_5_0_S1_10 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_5_0_S0_10 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_7_0_S1_10 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_7_0_S0_10 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_9_0_S1_10 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_9_0_S0_10 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_11_0_S1_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_11_0_S0_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_13_0_S0_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_3_THE_ALU/thr_pass_comb_cry_13_0_COUT_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/nc_corr_data_q_0_cry_0_0_S0_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/nc_corr_data_q_0_s_13_0_S1_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/nc_corr_data_q_0_s_13_0_COUT_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/un3_loc_baseline_q_cry_0_0_S1_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/un3_loc_baseline_q_cry_0_0_S0_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/un3_loc_baseline_q_cry_12_0_S1_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/un1_data_we_cry_0_0_S0_9 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/un1_data_we_s_9_0_S1_9 undriven or
+ does not drive anything - clipped.
+
+ Page 213
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/un1_data_we_s_9_0_COUT_9 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/nc_corr_data_qq_1_s_13_0_S1_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/ped_corr_data_q_1_cry_0_0_S1_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/ped_corr_data_q_1_cry_0_0_S0_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_0_0_S1_9 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_0_0_S0_9 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_1_0_S1_9 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_1_0_S0_9 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_3_0_S1_9 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_3_0_S0_9 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_5_0_S1_9 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_5_0_S0_9 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_7_0_S1_9 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_7_0_S0_9 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_9_0_S1_9 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_9_0_S0_9 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_11_0_S1_9 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_11_0_S0_9 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_13_0_S0_9 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_5_THE_ALU/thr_pass_comb_cry_13_0_COUT_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/nc_corr_data_q_0_cry_0_0_S0_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/nc_corr_data_q_0_s_13_0_S1_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/nc_corr_data_q_0_s_13_0_COUT_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1_8
+ undriven or does not drive anything - clipped.
+
+ Page 214
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/nc_corr_data_qq_1_s_13_0_S1_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/un3_loc_baseline_q_cry_0_0_S1_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/un3_loc_baseline_q_cry_0_0_S0_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/un3_loc_baseline_q_cry_12_0_S1_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/un1_data_we_cry_0_0_S0_8 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/un1_data_we_s_9_0_S1_8 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/un1_data_we_s_9_0_COUT_8 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/ped_corr_data_q_1_cry_0_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/ped_corr_data_q_1_cry_0_0_S0_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_0_0_S1_8 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_0_0_S0_8 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_1_0_S1_8 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_1_0_S0_8 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_3_0_S1_8 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_3_0_S0_8 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_5_0_S1_8 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_5_0_S0_8 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_7_0_S1_8 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_7_0_S0_8 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_9_0_S1_8 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_9_0_S0_8 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_11_0_S1_8 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_11_0_S0_8 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_13_0_S0_8 undriven
+ or does not drive anything - clipped.
+
+ Page 215
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_7_THE_ALU/thr_pass_comb_cry_13_0_COUT_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/nc_corr_data_q_0_cry_0_0_S0_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/nc_corr_data_q_0_s_13_0_S1_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/nc_corr_data_q_0_s_13_0_COUT_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/un3_loc_baseline_q_cry_0_0_S1_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/un3_loc_baseline_q_cry_0_0_S0_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/un3_loc_baseline_q_cry_12_0_S1_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/un1_data_we_cry_0_0_S0_7 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/un1_data_we_s_9_0_S1_7 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/un1_data_we_s_9_0_COUT_7 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/nc_corr_data_qq_1_s_13_0_S1_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/ped_corr_data_q_1_cry_0_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/ped_corr_data_q_1_cry_0_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_0_0_S1_7 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_0_0_S0_7 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_1_0_S1_7 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_1_0_S0_7 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_3_0_S1_7 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_3_0_S0_7 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_5_0_S1_7 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_5_0_S0_7 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_7_0_S1_7 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_7_0_S0_7 undriven
+ or does not drive anything - clipped.
+
+ Page 216
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_9_0_S1_7 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_9_0_S0_7 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_11_0_S1_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_11_0_S0_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_13_0_S0_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_12_THE_ALU/thr_pass_comb_cry_13_0_COUT_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/nc_corr_data_q_0_cry_0_0_S0_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/nc_corr_data_q_0_s_13_0_S1_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/nc_corr_data_q_0_s_13_0_COUT_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/un3_loc_baseline_q_cry_0_0_S1_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/un3_loc_baseline_q_cry_0_0_S0_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/un3_loc_baseline_q_cry_12_0_S1_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/un1_data_we_cry_0_0_S0_6 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/un1_data_we_s_9_0_S1_6 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/un1_data_we_s_9_0_COUT_6 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/nc_corr_data_qq_1_s_13_0_S1_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/ped_corr_data_q_1_cry_0_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/ped_corr_data_q_1_cry_0_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT_14
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_0_0_S1_6 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_0_0_S0_6 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_1_0_S1_6 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_1_0_S0_6 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_3_0_S1_6 undriven
+ or does not drive anything - clipped.
+
+ Page 217
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_3_0_S0_6 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_5_0_S1_6 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_5_0_S0_6 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_7_0_S1_6 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_7_0_S0_6 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_9_0_S1_6 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_9_0_S0_6 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_11_0_S1_6 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_11_0_S0_6 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_13_0_S0_6 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_9_THE_ALU/thr_pass_comb_cry_13_0_COUT_6
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/nc_corr_data_q_0_cry_0_0_S0_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/nc_corr_data_q_0_s_13_0_S1_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/nc_corr_data_q_0_s_13_0_COUT_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/un3_loc_baseline_q_cry_0_0_S1_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/un3_loc_baseline_q_cry_0_0_S0_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/un3_loc_baseline_q_cry_12_0_S1_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/un1_data_we_cry_0_0_S0_5 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/un1_data_we_s_9_0_S1_5 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/un1_data_we_s_9_0_COUT_5 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/nc_corr_data_qq_1_s_13_0_S1_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/ped_corr_data_q_1_cry_0_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/ped_corr_data_q_1_cry_0_0_S0_13
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT_13
+ undriven or does not drive anything - clipped.
+
+ Page 218
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_0_0_S1_5 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_0_0_S0_5 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_1_0_S1_5 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_1_0_S0_5 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_3_0_S1_5 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_3_0_S0_5 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_5_0_S1_5 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_5_0_S0_5 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_7_0_S1_5 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_7_0_S0_5 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_9_0_S1_5 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_9_0_S0_5 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_11_0_S1_5 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_11_0_S0_5 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_13_0_S0_5 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_0_THE_ALU/thr_pass_comb_cry_13_0_COUT_5
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/nc_corr_data_q_0_cry_0_0_S0_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/nc_corr_data_q_0_s_13_0_S1_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/nc_corr_data_q_0_s_13_0_COUT_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/un3_loc_baseline_q_cry_0_0_S1_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/un3_loc_baseline_q_cry_0_0_S0_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/un3_loc_baseline_q_cry_12_0_S1_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/un1_data_we_cry_0_0_S0_4 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/un1_data_we_s_9_0_S1_4 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/un1_data_we_s_9_0_COUT_4 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0_4
+ undriven or does not drive anything - clipped.
+
+ Page 219
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/nc_corr_data_qq_1_s_13_0_S1_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/ped_corr_data_q_1_cry_0_0_S1_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/ped_corr_data_q_1_cry_0_0_S0_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT_12
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_0_0_S1_4 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_0_0_S0_4 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_1_0_S1_4 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_1_0_S0_4 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_3_0_S1_4 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_3_0_S0_4 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_5_0_S1_4 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_5_0_S0_4 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_7_0_S1_4 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_7_0_S0_4 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_9_0_S1_4 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_9_0_S0_4 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_11_0_S1_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_11_0_S0_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_13_0_S0_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_15_THE_ALU/thr_pass_comb_cry_13_0_COUT_4
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/nc_corr_data_q_0_cry_0_0_S0_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/nc_corr_data_q_0_s_13_0_S1_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/nc_corr_data_q_0_s_13_0_COUT_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/un3_loc_baseline_q_cry_0_0_S1_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/un3_loc_baseline_q_cry_0_0_S0_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/un3_loc_baseline_q_cry_12_0_S1_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT_3
+ undriven or does not drive anything - clipped.
+
+ Page 220
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/un1_data_we_cry_0_0_S0_3 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/un1_data_we_s_9_0_S1_3 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/un1_data_we_s_9_0_COUT_3 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/nc_corr_data_qq_1_s_13_0_S1_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/ped_corr_data_q_1_cry_0_0_S1_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/ped_corr_data_q_1_cry_0_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT_11
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_0_0_S1_3 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_0_0_S0_3 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_1_0_S1_3 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_1_0_S0_3 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_3_0_S1_3 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_3_0_S0_3 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_5_0_S1_3 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_5_0_S0_3 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_7_0_S1_3 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_7_0_S0_3 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_9_0_S1_3 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_9_0_S0_3 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_11_0_S1_3 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_11_0_S0_3 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_13_0_S0_3 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_6_THE_ALU/thr_pass_comb_cry_13_0_COUT_3
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/nc_corr_data_q_0_cry_0_0_S0_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/nc_corr_data_q_0_s_13_0_S1_2
+ undriven or does not drive anything - clipped.
+
+ Page 221
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/nc_corr_data_q_0_s_13_0_COUT_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/un3_loc_baseline_q_cry_0_0_S1_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/un3_loc_baseline_q_cry_0_0_S0_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/un3_loc_baseline_q_cry_12_0_S1_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/un1_data_we_cry_0_0_S0_2 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/un1_data_we_s_9_0_S1_2 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/un1_data_we_s_9_0_COUT_2 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/nc_corr_data_qq_1_s_13_0_S1_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/ped_corr_data_q_1_cry_0_0_S1_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/ped_corr_data_q_1_cry_0_0_S0_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT_10
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_0_0_S1_2 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_0_0_S0_2 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_1_0_S1_2 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_1_0_S0_2 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_3_0_S1_2 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_3_0_S0_2 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_5_0_S1_2 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_5_0_S0_2 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_7_0_S1_2 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_7_0_S0_2 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_9_0_S1_2 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_9_0_S0_2 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_11_0_S1_2
+ undriven or does not drive anything - clipped.
+
+ Page 222
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_11_0_S0_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_13_0_S0_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_13_THE_ALU/thr_pass_comb_cry_13_0_COUT_2
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/nc_corr_data_q_0_cry_0_0_S0_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/nc_corr_data_q_0_s_13_0_S1_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/nc_corr_data_q_0_s_13_0_COUT_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/un1_data_we_cry_0_0_S0_1 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/un1_data_we_s_9_0_S1_1 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/un1_data_we_s_9_0_COUT_1 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/nc_corr_data_qq_1_s_13_0_S1_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/un3_loc_baseline_q_cry_0_0_S1_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/un3_loc_baseline_q_cry_0_0_S0_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/un3_loc_baseline_q_cry_12_0_S1_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/ped_corr_data_q_1_cry_0_0_S1_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/ped_corr_data_q_1_cry_0_0_S0_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT_9
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_0_0_S1_1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_0_0_S0_1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_1_0_S1_1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_1_0_S0_1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_3_0_S1_1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_3_0_S0_1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_5_0_S1_1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_5_0_S0_1 undriven
+ or does not drive anything - clipped.
+
+ Page 223
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_7_0_S1_1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_7_0_S0_1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_9_0_S1_1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_9_0_S0_1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_11_0_S1_1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_11_0_S0_1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_13_0_S0_1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_2_THE_ALU/thr_pass_comb_cry_13_0_COUT_1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/nc_corr_data_q_0_cry_0_0_S0_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/nc_corr_data_q_0_s_13_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/nc_corr_data_q_0_s_13_0_COUT_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/un3_loc_baseline_q_cry_0_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/un3_loc_baseline_q_cry_0_0_S0_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/un3_loc_baseline_q_cry_12_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/un1_data_we_cry_0_0_S0_0 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/un1_data_we_s_9_0_S1_0 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/un1_data_we_s_9_0_COUT_0 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/nc_corr_data_qq_1_s_13_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/ped_corr_data_q_1_cry_0_0_S1_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/ped_corr_data_q_1_cry_0_0_S0_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT_8
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_0_0_S1_0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_0_0_S0_0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_1_0_S1_0 undriven
+ or does not drive anything - clipped.
+
+ Page 224
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_1_0_S0_0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_3_0_S1_0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_3_0_S0_0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_5_0_S1_0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_5_0_S0_0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_7_0_S1_0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_7_0_S0_0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_9_0_S1_0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_9_0_S0_0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_11_0_S1_0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_11_0_S0_0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_13_0_S0_0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_8_THE_ALU/thr_pass_comb_cry_13_0_COUT_0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/nc_corr_data_q_0_cry_0_0_S0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/nc_corr_data_q_0_s_13_0_S1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/nc_corr_data_q_0_s_13_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/un3_loc_baseline_q_cry_0_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/un3_loc_baseline_q_cry_0_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/un3_loc_baseline_q_cry_12_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/un3_loc_baseline_q_cry_12_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/un1_data_we_cry_0_0_S0 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/un1_data_we_s_9_0_S1 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/un1_data_we_s_9_0_COUT undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/nc_corr_data_qq_1_cry_0_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/nc_corr_data_qq_1_cry_0_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/nc_corr_data_qq_1_s_13_0_S1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/nc_corr_data_qq_1_s_13_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/ped_corr_data_q_1_cry_0_0_S1_7
+ undriven or does not drive anything - clipped.
+
+ Page 225
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/ped_corr_data_q_1_cry_0_0_S0_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/ped_corr_data_q_1_cry_11_0_COUT_7
+ undriven or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_0_0_S1 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_0_0_S0 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_1_0_S1 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_1_0_S0 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_3_0_S1 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_3_0_S0 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_5_0_S1 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_5_0_S0 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_7_0_S1 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_7_0_S0 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_9_0_S1 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_9_0_S0 undriven or
+ does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_11_0_S1 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_11_0_S0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_13_0_S0 undriven
+ or does not drive anything - clipped.
+Signal THE_PED_CORR_STAGE/GEN_ALU_1_THE_ALU/thr_pass_comb_cry_13_0_COUT undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/pc_ctr_cry_0_S0_14_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/pc_ctr_s_0_S1_14_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/pc_ctr_s_0_COUT_14_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0_
+ S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S1
+ _14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_CO
+ UT_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ _S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_S
+ 1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_C
+ OUT_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0_14
+ undriven or does not drive anything - clipped.
+
+ Page 226
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT_
+ 14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/delay_store_CR0_ram_DO2_14
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/delay_store_CR0_ram_DO3_14
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/delay_store_CR0_ram_DO1_14
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_COUT_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_COUT_14 undriven or does not drive anything - clipped.
+
+ Page 227
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_COUT_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_COUT_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/pc_ctr_cry_0_S0_13_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/pc_ctr_s_0_S1_13_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/pc_ctr_s_0_COUT_13_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0_
+ S0_13 undriven or does not drive anything - clipped.
+
+ Page 228
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S1
+ _13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_CO
+ UT_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ _S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_S
+ 1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_C
+ OUT_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0_13
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT_
+ 13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/delay_store_CR0_ram_DO2_13
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/delay_store_CR0_ram_DO3_13
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/delay_store_CR0_ram_DO1_13
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_COUT_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S0_13 undriven or does not drive anything - clipped.
+
+ Page 229
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_COUT_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_COUT_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S0_13 undriven or does not drive anything - clipped.
+
+ Page 230
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_COUT_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/pc_ctr_cry_0_S0_12_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/pc_ctr_s_0_S1_12_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/pc_ctr_s_0_COUT_12_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0_12
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT_
+ 12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0_
+ S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S1
+ _12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_CO
+ UT_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ _S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_S
+ 1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_C
+ OUT_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/delay_store_CR0_ram_DO2_12
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/delay_store_CR0_ram_DO3_12
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/delay_store_CR0_ram_DO1_12
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S0_12 undriven or does not drive anything - clipped.
+
+ Page 231
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_COUT_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_COUT_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_COUT_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S0_12 undriven or does not drive anything - clipped.
+
+ Page 232
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_COUT_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/pc_ctr_cry_0_S0_11_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/pc_ctr_s_0_S1_11_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/pc_ctr_s_0_COUT_11_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0_
+ S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S1
+ _11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_CO
+ UT_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ _S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_S
+ 1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_C
+ OUT_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT_
+ 11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/delay_store_CR0_ram_DO2_11
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/delay_store_CR0_ram_DO3_11
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/delay_store_CR0_ram_DO1_11
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S0_11 undriven or does not drive anything - clipped.
+
+ Page 233
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_COUT_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_COUT_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S0_11 undriven or does not drive anything - clipped.
+
+ Page 234
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_COUT_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_COUT_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/pc_ctr_cry_0_S0_10_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/pc_ctr_s_0_S1_10_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/pc_ctr_s_0_COUT_10_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0_
+ S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S1
+ _10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_CO
+ UT_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ _S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_S
+ 1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_C
+ OUT_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0_10
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT_
+ 10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/delay_store_CR0_ram_DO2_10
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/delay_store_CR0_ram_DO3_10
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/delay_store_CR0_ram_DO1_10
+ undriven or does not drive anything - clipped.
+
+ Page 235
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_COUT_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_COUT_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S0_10 undriven or does not drive anything - clipped.
+
+ Page 236
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_COUT_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_COUT_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/pc_ctr_cry_0_S0_9_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/pc_ctr_s_0_S1_9_5 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/pc_ctr_s_0_COUT_9_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0_
+ S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S1
+ _9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_CO
+ UT_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ _S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_S
+ 1_9 undriven or does not drive anything - clipped.
+
+ Page 237
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_C
+ OUT_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0_9
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT_9
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/delay_store_CR0_ram_DO2_9
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/delay_store_CR0_ram_DO3_9
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/delay_store_CR0_ram_DO1_9
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_COUT_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+
+ Page 238
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ cry_9_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_COUT_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_COUT_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_COUT_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/pc_ctr_cry_0_S0_8_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/pc_ctr_s_0_S1_8_5 undriven or
+
+ Page 239
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/pc_ctr_s_0_COUT_8_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0_
+ S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S1
+ _8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_CO
+ UT_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ _S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_S
+ 1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_C
+ OUT_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0_8
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/delay_store_CR0_ram_DO2_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/delay_store_CR0_ram_DO3_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/delay_store_CR0_ram_DO1_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_COUT_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S1_8 undriven or does not drive anything - clipped.
+
+ Page 240
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_COUT_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_COUT_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S1_8 undriven or does not drive anything - clipped.
+
+ Page 241
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_COUT_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/pc_ctr_cry_0_S0_7_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/pc_ctr_s_0_S1_7_5 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/pc_ctr_s_0_COUT_7_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0_
+ S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S1
+ _7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_CO
+ UT_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ _S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_S
+ 1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_C
+ OUT_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0_7
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/delay_store_CR0_ram_DO2_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/delay_store_CR0_ram_DO3_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/delay_store_CR0_ram_DO1_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+
+ Page 242
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ n_cry_11_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_COUT_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_COUT_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+
+ Page 243
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ 2_cry_11_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_COUT_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_COUT_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S1
+ _14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S0
+ _14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_CO
+ UT_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S1
+ _14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S0
+ _14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_CO
+ UT_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1_14
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0_14
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT_
+ 14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1_
+ 14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0_
+ 14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1_
+ 14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_COU
+ T_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+
+ Page 244
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _S0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _COUT_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB17 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB16 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB15 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA17 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA16 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA15 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+
+ Page 245
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0_1_0_DOA3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB17 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB16 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB15 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA17 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA16 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA15 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+
+ Page 246
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0_0_1_DOA2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out11_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out9_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S1
+ _13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S0
+ _13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_CO
+ UT_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S1
+ _13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S0
+ _13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_CO
+ UT_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1_13
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0_13
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT_
+ 13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1_
+ 13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0_
+ 13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1_
+ 13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_COU
+ T_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _S0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _COUT_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB17_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+
+ Page 247
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0_1_0_DOB16_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB15_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB14_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB13_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB12_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB11_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB10_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB9_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA17_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA16_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA15_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA14_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA13_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA12_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA11_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA10_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA9_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA8_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA7_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA6_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA5_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA4_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA3_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA2_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB17_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB16_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+
+ Page 248
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0_0_1_DOB15_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB14_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB13_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB12_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB11_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB10_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB9_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA17_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA16_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA15_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA14_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA13_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA12_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA11_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA10_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA9_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA8_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA7_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA6_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA5_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA4_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA3_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA2_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out11_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out9_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S1
+
+ Page 249
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S0
+ _12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_CO
+ UT_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S1
+ _12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S0
+ _12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_CO
+ UT_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1_12
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0_12
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT_
+ 12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1_
+ 12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0_
+ 12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1_
+ 12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_COU
+ T_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _S0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _COUT_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB17_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB16_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB15_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB14_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB13_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB12_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB11_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+
+ Page 250
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0_1_0_DOB10_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB9_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA17_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA16_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA15_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA14_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA13_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA12_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA11_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA10_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA9_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA8_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA7_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA6_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA5_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA4_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA3_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA2_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB17_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB16_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB15_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB14_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB13_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB12_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB11_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB10_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+
+ Page 251
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0_0_1_DOB9_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA17_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA16_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA15_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA14_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA13_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA12_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA11_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA10_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA9_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA8_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA7_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA6_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA5_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA4_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA3_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA2_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out11_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out9_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S1
+ _11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S0
+ _11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_CO
+ UT_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S1
+ _11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S0
+ _11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_CO
+ UT_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1_11
+
+ Page 252
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0_11
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT_
+ 11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1_
+ 11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0_
+ 11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1_
+ 11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_COU
+ T_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _S0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _COUT_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB17_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB16_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB15_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB14_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB13_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB12_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB11_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB10_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB9_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA17_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA16_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA15_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA14_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+
+ Page 253
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0_1_0_DOA13_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA12_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA11_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA10_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA9_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA8_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA7_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA6_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA5_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA4_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA3_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA2_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB17_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB16_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB15_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB14_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB13_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB12_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB11_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB10_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB9_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA17_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA16_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA15_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA14_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA13_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+
+ Page 254
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0_0_1_DOA12_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA11_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA10_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA9_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA8_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA7_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA6_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA5_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA4_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA3_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA2_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out11_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out9_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S1
+ _10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S0
+ _10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_CO
+ UT_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S1
+ _10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S0
+ _10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_CO
+ UT_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1_10
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0_10
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT_
+ 10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1_
+ 10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0_
+ 10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1_
+ 10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_COU
+
+ Page 255
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ T_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _S0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _COUT_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB17_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB16_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB15_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB14_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB13_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB12_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB11_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB10_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB9_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA17_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA16_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA15_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA14_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA13_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA12_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA11_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA10_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA9_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA8_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+
+ Page 256
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0_1_0_DOA7_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA6_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA5_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA4_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA3_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA2_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB17_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB16_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB15_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB14_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB13_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB12_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB11_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB10_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB9_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA17_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA16_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA15_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA14_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA13_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA12_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA11_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA10_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA9_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA8_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA7_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+
+ Page 257
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0_0_1_DOA6_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA5_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA4_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA3_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA2_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out11_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out9_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S1
+ _9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S0
+ _9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_CO
+ UT_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S1
+ _9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S0
+ _9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_CO
+ UT_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1_9
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0_9
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT_9
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1_9
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0_9
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1_9
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_COU
+ T_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+
+ Page 258
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _S0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _COUT_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB17_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB16_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB15_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB14_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB13_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB12_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB11_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB10_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB9_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA17_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA16_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA15_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA14_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA13_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA12_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA11_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA10_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA9_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA8_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA7_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA6_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA5_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA4_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+
+ Page 259
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0_1_0_DOA3_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA2_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB17_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB16_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB15_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB14_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB13_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB12_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB11_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB10_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB9_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA17_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA16_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA15_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA14_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA13_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA12_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA11_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA10_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA9_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA8_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA7_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA6_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA5_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA4_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA3_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+
+ Page 260
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0_0_1_DOA2_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out11_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out9_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S1
+ _8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S0
+ _8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_CO
+ UT_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S1
+ _8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S0
+ _8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_CO
+ UT_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0_8
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT_8
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1_8
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0_8
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1_8
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_COU
+ T_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _S0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+
+ Page 261
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _COUT_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB17_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB16_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB15_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB14_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB13_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB12_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB11_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB10_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB9_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA17_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA16_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA15_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA14_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA13_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA12_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA11_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA10_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA9_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA8_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA7_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA6_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA5_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA4_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA3_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA2_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+
+ Page 262
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0_0_1_DOB17_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB16_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB15_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB14_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB13_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB12_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB11_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB10_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB9_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA17_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA16_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA15_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA14_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA13_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA12_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA11_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA10_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA9_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA8_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA7_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA6_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA5_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA4_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA3_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA2_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+
+ Page 263
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ out11_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out9_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S1
+ _7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S0
+ _7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_CO
+ UT_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S1
+ _7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S0
+ _7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_CO
+ UT_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0_7
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT_7
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1_7
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0_7
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1_7
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_COU
+ T_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _S0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _COUT_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB17_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB16_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB15_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+
+ Page 264
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0_1_0_DOB14_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB13_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB12_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB11_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB10_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB9_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA17_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA16_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA15_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA14_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA13_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA12_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA11_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA10_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA9_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA8_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA7_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA6_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA5_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA4_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA3_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA2_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB17_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB16_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB15_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB14_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+
+ Page 265
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _0_0_1_DOB13_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB12_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB11_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB10_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB9_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA17_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA16_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA15_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA14_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA13_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA12_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA11_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA10_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA9_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA8_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA7_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA6_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA5_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA4_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA3_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA2_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out11_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out9_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/pc_ctr_cry_0_S0_6_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/pc_ctr_s_0_S1_6_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/pc_ctr_s_0_COUT_6_5 undriven
+
+ Page 266
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT
+ _6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ _S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S
+ 1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_C
+ OUT_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_
+ 0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_
+ S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_
+ COUT_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/delay_store_CR0_ram_DO2_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/delay_store_CR0_ram_DO3_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/delay_store_CR0_ram_DO1_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_4_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_4_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_5_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_5_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_7_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_7_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_9_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_9_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_11_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_11_0_COUT_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_0_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_0_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_1_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_1_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_3_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_3_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+
+ Page 267
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _cry_5_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_5_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_7_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_7_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_9_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_9_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_11_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_11_0_COUT_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_0_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_0_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_1_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_1_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_3_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_3_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_5_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_5_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_7_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_7_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_9_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_9_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_11_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_11_0_COUT_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_4_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_4_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_5_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_5_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_7_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_7_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+
+ Page 268
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ ry_9_0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_9_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_11_0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_11_0_COUT_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/pc_ctr_cry_0_S0_5_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/pc_ctr_s_0_S1_5_5 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/pc_ctr_s_0_COUT_5_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0_
+ S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S1
+ _5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_CO
+ UT_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ _S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_S
+ 1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_C
+ OUT_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0_5
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/delay_store_CR0_ram_DO2_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/delay_store_CR0_ram_DO3_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/delay_store_CR0_ram_DO1_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_COUT_5 undriven or does not drive anything - clipped.
+
+ Page 269
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_COUT_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_COUT_5 undriven or does not drive anything - clipped.
+
+ Page 270
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_COUT_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/pc_ctr_cry_0_S0_4_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/pc_ctr_s_0_S1_4_5 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/pc_ctr_s_0_COUT_4_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0_
+ S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S1
+ _4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_CO
+ UT_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_0
+ _S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_S
+ 1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_C
+ OUT_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0_4
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/delay_store_CR0_ram_DO2_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/delay_store_CR0_ram_DO3_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/delay_store_CR0_ram_DO1_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_4_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_5_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+
+ Page 271
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ n_cry_5_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_7_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_9_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_i
+ n_cry_11_0_COUT_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_0_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_1_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_3_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_5_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_7_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_9_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_
+ cry_11_0_COUT_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_0_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_1_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_3_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_5_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+
+ Page 272
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ 2_cry_5_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_7_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_9_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high
+ 2_cry_11_0_COUT_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_4_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_5_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_7_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_9_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cr
+ y_11_0_COUT_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/pc_ctr_cry_0_S0_3_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/pc_ctr_s_0_S1_3_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/pc_ctr_s_0_COUT_3_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ _S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S
+ 1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_C
+ OUT_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_
+ 0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_
+ S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_
+ COUT_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT
+ _3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/delay_store_CR0_ram_DO2_3
+
+ Page 273
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/delay_store_CR0_ram_DO3_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/delay_store_CR0_ram_DO1_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_4_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_4_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_5_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_5_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_7_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_7_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_9_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_9_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_11_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_11_0_COUT_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_0_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_0_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_1_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_1_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_3_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_3_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_5_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_5_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_7_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_7_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_9_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_9_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_11_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_11_0_COUT_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_0_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+
+ Page 274
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ h2_cry_0_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_1_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_1_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_3_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_3_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_5_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_5_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_7_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_7_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_9_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_9_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_11_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_11_0_COUT_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_4_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_4_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_5_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_5_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_7_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_7_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_9_0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_9_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_11_0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_11_0_COUT_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/pc_ctr_cry_0_S0_2_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/pc_ctr_s_0_S1_2_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/pc_ctr_s_0_COUT_2_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_
+ 0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_
+ S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_
+
+ Page 275
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ COUT_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT
+ _2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ _S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S
+ 1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_C
+ OUT_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/delay_store_CR0_ram_DO2_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/delay_store_CR0_ram_DO3_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/delay_store_CR0_ram_DO1_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_4_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_4_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_5_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_5_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_7_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_7_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_9_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_9_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_11_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_11_0_COUT_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_4_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_4_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_5_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_5_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_7_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_7_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_9_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_9_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_11_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+
+ Page 276
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ in_cry_11_0_COUT_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_0_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_0_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_1_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_1_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_3_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_3_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_5_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_5_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_7_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_7_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_9_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_9_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_11_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_11_0_COUT_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_0_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_0_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_1_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_1_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_3_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_3_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_5_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_5_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_7_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_7_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_9_0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_9_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_11_0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+
+ Page 277
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ h2_cry_11_0_COUT_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/pc_ctr_cry_0_S0_1_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/pc_ctr_s_0_S1_1_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/pc_ctr_s_0_COUT_1_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ _S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S
+ 1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_C
+ OUT_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_
+ 0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_
+ S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_
+ COUT_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT
+ _1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/delay_store_CR0_ram_DO2_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/delay_store_CR0_ram_DO3_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/delay_store_CR0_ram_DO1_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_0_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_0_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_1_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_1_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_3_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_3_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_5_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_5_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_7_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_7_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_9_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_9_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_11_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+
+ Page 278
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ _cry_11_0_COUT_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_0_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_0_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_1_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_1_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_3_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_3_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_5_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_5_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_7_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_7_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_9_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_9_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_11_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_11_0_COUT_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_4_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_4_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_5_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_5_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_7_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_7_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_9_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_9_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_11_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_11_0_COUT_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_4_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_4_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_5_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+
+ Page 279
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ in_cry_5_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_7_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_7_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_9_0_S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_9_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_11_0_S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_11_0_COUT_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/pc_ctr_cry_0_S0_0_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/pc_ctr_s_0_S1_0_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/pc_ctr_s_0_COUT_0_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ _S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S
+ 1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_C
+ OUT_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_
+ 0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_
+ S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_
+ COUT_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT
+ _0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/delay_store_CR0_ram_DO2_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/delay_store_CR0_ram_DO3_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/delay_store_CR0_ram_DO1_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_4_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_4_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_5_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_5_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_7_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_7_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_9_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+
+ Page 280
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ in_cry_9_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_11_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_11_0_COUT_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_0_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_0_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_1_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_1_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_3_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_3_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_5_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_5_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_7_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_7_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_9_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_9_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_11_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_11_0_COUT_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_0_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_0_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_1_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_1_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_3_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_3_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_5_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_5_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_7_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_7_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_9_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+
+ Page 281
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ h2_cry_9_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_11_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_11_0_COUT_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_4_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_4_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_5_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_5_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_7_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_7_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_9_0_S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_9_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_11_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_11_0_COUT_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/pc_ctr_cry_0_S0_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/pc_ctr_s_0_S1_5 undriven or
+ does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/pc_ctr_s_0_COUT_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_cry_0_0
+ _S0 undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_overflow_s_7_0_C
+ OUT undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_cry_0_
+ 0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_
+ S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_next_ce_underflow_s_7_0_
+ COUT undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_0_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/un1_ce_chnl_ctr_cry_5_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/delay_store_CR0_ram_DO2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/delay_store_CR0_ram_DO3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/delay_store_CR0_ram_DO1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_4_0_S1 undriven or does not drive anything - clipped.
+
+ Page 282
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_4_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_5_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_5_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_7_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_7_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_9_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_9_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_11_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_
+ in_cry_11_0_COUT undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_0_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_0_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_1_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_1_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_3_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_3_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_5_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_5_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_7_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_7_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_9_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_9_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_11_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2
+ _cry_11_0_COUT undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_0_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_0_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_1_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_1_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_3_0_S1 undriven or does not drive anything - clipped.
+
+ Page 283
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_3_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_5_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_5_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_7_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_7_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_9_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_9_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_11_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_hig
+ h2_cry_11_0_COUT undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_4_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_4_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_5_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_5_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_7_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_7_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_9_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_9_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_11_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_c
+ ry_11_0_COUT undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S
+ 1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S
+ 0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_C
+ OUT_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S
+ 1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S
+ 0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_C
+ OUT_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0_6
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT
+ _6 undriven or does not drive anything - clipped.
+
+ Page 284
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1
+ _6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0
+ _6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1
+ _6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_CO
+ UT_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_
+ 0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_
+ 0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_
+ 0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_
+ 0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_
+ 0_S1_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_
+ 0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_
+ 0_S0_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_
+ 0_COUT_6 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB17_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB16_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB15_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB14_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB13_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB12_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB11_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB10_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB9_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA17_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA16_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA15_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA14_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA13_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA12_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA11_7 undriven or does not drive anything - clipped.
+
+ Page 285
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA10_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA9_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA8_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA7_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA6_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA5_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA4_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA3_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA2_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB17_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB16_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB15_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB14_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB13_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB12_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB11_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB10_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB9_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA17_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA16_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA15_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA14_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA13_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA12_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA11_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA10_7 undriven or does not drive anything - clipped.
+
+ Page 286
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA9_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA8_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA7_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA6_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA5_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA4_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA3_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA2_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA1_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA0_7 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout11_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout9_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S
+ 1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S
+ 0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_C
+ OUT_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S
+ 1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S
+ 0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_C
+ OUT_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0_5
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT
+ _5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1
+ _5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0
+ _5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1
+ _5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_CO
+ UT_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_
+ 0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_
+ 0_S0_5 undriven or does not drive anything - clipped.
+
+ Page 287
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_
+ 0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_
+ 0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_
+ 0_S1_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_
+ 0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_
+ 0_S0_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_
+ 0_COUT_5 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB17_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB16_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB15_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB14_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB13_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB12_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB11_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB10_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB9_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA17_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA16_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA15_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA14_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA13_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA12_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA11_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA10_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA9_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA8_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA7_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA6_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA5_8 undriven or does not drive anything - clipped.
+
+ Page 288
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA4_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA3_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA2_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB17_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB16_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB15_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB14_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB13_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB12_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB11_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB10_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB9_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA17_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA16_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA15_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA14_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA13_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA12_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA11_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA10_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA9_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA8_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA7_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA6_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA5_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA4_8 undriven or does not drive anything - clipped.
+
+ Page 289
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA3_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA2_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA1_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA0_8 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout11_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout9_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S
+ 1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S
+ 0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_C
+ OUT_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S
+ 1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S
+ 0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_C
+ OUT_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0_4
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT
+ _4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1
+ _4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0
+ _4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1
+ _4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_CO
+ UT_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_
+ 0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_
+ 0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_
+ 0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_
+ 0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_
+ 0_S1_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_
+ 0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_
+ 0_S0_4 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_
+ 0_COUT_4 undriven or does not drive anything - clipped.
+
+ Page 290
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB17_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB16_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB15_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB14_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB13_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB12_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB11_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB10_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB9_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA17_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA16_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA15_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA14_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA13_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA12_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA11_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA10_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA9_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA8_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA7_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA6_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA5_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA4_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA3_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA2_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB17_9 undriven or does not drive anything - clipped.
+
+ Page 291
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB16_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB15_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB14_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB13_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB12_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB11_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB10_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB9_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA17_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA16_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA15_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA14_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA13_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA12_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA11_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA10_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA9_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA8_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA7_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA6_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA5_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA4_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA3_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA2_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA1_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA0_9 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout11_ffin undriven or does not drive anything - clipped.
+
+ Page 292
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout9_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S
+ 1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S
+ 0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_C
+ OUT_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S
+ 1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S
+ 0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_C
+ OUT_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0_3
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT
+ _3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1
+ _3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0
+ _3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1
+ _3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_CO
+ UT_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_
+ 0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_
+ 0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_
+ 0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_
+ 0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_
+ 0_S1_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_
+ 0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_
+ 0_S0_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_
+ 0_COUT_3 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB17_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB16_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB15_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB14_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB13_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB12_10 undriven or does not drive anything - clipped.
+
+ Page 293
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB11_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB10_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB9_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA17_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA16_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA15_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA14_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA13_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA12_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA11_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA10_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA9_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA8_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA7_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA6_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA5_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA4_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA3_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA2_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB17_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB16_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB15_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB14_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB13_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB12_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB11_10 undriven or does not drive anything - clipped.
+
+ Page 294
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB10_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB9_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA17_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA16_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA15_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA14_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA13_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA12_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA11_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA10_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA9_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA8_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA7_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA6_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA5_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA4_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA3_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA2_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA1_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA0_10 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout11_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout9_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S
+ 1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S
+ 0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_C
+ OUT_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S
+ 1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S
+ 0_2 undriven or does not drive anything - clipped.
+
+ Page 295
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_C
+ OUT_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0_2
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT
+ _2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1
+ _2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0
+ _2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1
+ _2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_CO
+ UT_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_
+ 0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_
+ 0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_
+ 0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_
+ 0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_
+ 0_S1_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_
+ 0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_
+ 0_S0_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_
+ 0_COUT_2 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB17_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB16_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB15_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB14_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB13_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB12_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB11_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB10_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB9_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA17_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA16_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA15_11 undriven or does not drive anything - clipped.
+
+ Page 296
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA14_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA13_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA12_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA11_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA10_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA9_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA8_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA7_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA6_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA5_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA4_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA3_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA2_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB17_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB16_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB15_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB14_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB13_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB12_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB11_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB10_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB9_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA17_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA16_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA15_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA14_11 undriven or does not drive anything - clipped.
+
+ Page 297
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA13_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA12_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA11_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA10_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA9_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA8_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA7_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA6_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA5_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA4_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA3_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA2_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA1_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA0_11 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout11_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout9_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S1
+ _1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S0
+ _1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_CO
+ UT_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S1
+ _1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S0
+ _1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_CO
+ UT_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0_1
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT_1
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1_1
+ undriven or does not drive anything - clipped.
+
+ Page 298
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0_1
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1_1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_COU
+ T_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S1_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _S0_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _COUT_1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB17_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB16_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB15_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB14_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB13_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB12_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB11_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB10_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB9_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA17_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA16_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA15_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA14_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA13_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA12_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA11_12 undriven or does not drive anything - clipped.
+
+ Page 299
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA10_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA9_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA8_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA7_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA6_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA5_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA4_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA3_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA2_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB17_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB16_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB15_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB14_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB13_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB12_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB11_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB10_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB9_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA17_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA16_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA15_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA14_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA13_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA12_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA11_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA10_12 undriven or does not drive anything - clipped.
+
+ Page 300
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA9_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA8_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA7_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA6_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA5_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA4_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA3_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA2_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA1_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA0_12 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out11_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out9_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S1
+ _0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S0
+ _0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_CO
+ UT_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S1
+ _0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S0
+ _0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_CO
+ UT_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0_0
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT_0
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0_0
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_COU
+ T_0 undriven or does not drive anything - clipped.
+
+ Page 301
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_0
+ _S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_0
+ _S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S1_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_0
+ _S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _S0_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_0
+ _COUT_0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB17_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB16_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB15_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB14_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB13_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB12_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB11_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB10_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOB9_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA17_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA16_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA15_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA14_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA13_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA12_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA11_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA10_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA9_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA8_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA7_13 undriven or does not drive anything - clipped.
+
+ Page 302
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA6_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA5_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA4_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA3_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA2_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_1_0_DOA0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB17_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB16_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB15_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB14_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB13_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB12_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB11_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB10_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOB9_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA17_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA16_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA15_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA14_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA13_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA12_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA11_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA10_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA9_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA8_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA7_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA6_13 undriven or does not drive anything - clipped.
+
+ Page 303
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA5_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA4_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA3_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA2_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA1_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram
+ _0_0_1_DOA0_13 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out11_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/data
+ out9_ffin undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S1
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_0_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/apv_free_ctr_4_cry_3_0_C
+ OUT undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S1
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_0_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/buf_free_ctr_3_cry_3_0_C
+ OUT undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/buf_level_4_cry_0_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/buf_level_4_cry_3_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_0_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/sum_apv_buf_1_cry_4_0_CO
+ UT undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_
+ 0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_0_
+ 0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_
+ 0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_1_
+ 0_S0 undriven or does not drive anything - clipped.
+
+ Page 304
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_
+ 0_S1 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_3_
+ 0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_
+ 0_S0 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/apv_or_buf_full_x_cry_5_
+ 0_COUT undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB17_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB16_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB15_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB14_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB13_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB12_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB11_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB10_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOB9_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA17_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA16_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA15_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA14_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA13_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA12_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA11_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA10_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA9_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA8_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA7_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA6_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA5_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA4_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA3_14 undriven or does not drive anything - clipped.
+
+ Page 305
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA2_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_1_0_DOA0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB17_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB16_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB15_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB14_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB13_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB12_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB11_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB10_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOB9_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA17_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA16_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA15_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA14_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA13_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA12_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA11_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA10_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA9_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA8_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA7_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA6_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA5_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA4_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA3_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA2_14 undriven or does not drive anything - clipped.
+
+ Page 306
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA1_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bra
+ m_0_0_1_DOA0_14 undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout10_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout11_ffin undriven or does not drive anything - clipped.
+Signal THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/dat
+ aout9_ffin undriven or does not drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/un1_next_fifo_rd_ena_cry_0_0_S1_0 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/un1_next_fifo_rd_ena_cry_0_0_S0_0 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/un1_next_fifo_rd_ena_cry_1_0_S1_0 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/un1_next_fifo_rd_ena_cry_1_0_S0_0 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/un1_next_fifo_rd_ena_cry_3_0_S1_0 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/un1_next_fifo_rd_ena_cry_3_0_S0_0 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/un1_next_fifo_rd_ena_cry_4_0_S1_0 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/un1_next_fifo_rd_ena_cry_4_0_COUT_0 undriven or does
+ not drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/un1_a1_1 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/un1_a1 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/un1_full_cmp_ci_a_1 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/un1_full_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/un1_a0_1 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/un1_a0 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/un1_empty_cmp_ci_a_1 undriven or does
+ not drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/un1_empty_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/un1_rfill_0 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/un1_r_gctr_2 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/co2_1 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/un1_r_gctr_cia_1 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/un1_r_gctr_cia undriven or does not
+ drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/un1_w_gctr_2 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/co2 undriven or does not drive anything
+ - clipped.
+
+ Page 307
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/un1_w_gctr_cia_1 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/un1_w_gctr_cia undriven or does not
+ drive anything - clipped.
+Signal THE_ADC1_CROSSOVER/THE_CROSSOVER/co2_3 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC0_CROSSOVER/un1_next_fifo_rd_ena_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC0_CROSSOVER/un1_next_fifo_rd_ena_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC0_CROSSOVER/un1_next_fifo_rd_ena_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC0_CROSSOVER/un1_next_fifo_rd_ena_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC0_CROSSOVER/un1_next_fifo_rd_ena_cry_3_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC0_CROSSOVER/un1_next_fifo_rd_ena_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC0_CROSSOVER/un1_next_fifo_rd_ena_cry_4_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC0_CROSSOVER/un1_next_fifo_rd_ena_cry_4_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/a1_S1_29 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/a1_COUT_29 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/full_cmp_ci_a_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/full_cmp_ci_a_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/a0_S1_29 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/a0_COUT_29 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/empty_cmp_ci_a_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/empty_cmp_ci_a_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/co2_3 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/rfill_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gctr_2_NC1 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/co2_1 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gctr_cia_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gctr_cia_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/w_gctr_2_NC1 undriven or does not drive
+ anything - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/co2 undriven or does not drive anything
+ - clipped.
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/w_gctr_cia_S1 undriven or does not drive
+ anything - clipped.
+
+ Page 308
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_ADC0_CROSSOVER/THE_CROSSOVER/w_gctr_cia_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/evtctr_4_cry_0_0_S1 undriven or does
+ not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/evtctr_4_cry_0_0_S0 undriven or does
+ not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/evtctr_4_s_15_0_S1 undriven or does
+ not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/evtctr_4_s_15_0_COUT undriven or
+ does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/un1_ce_frmctr_1_cry_0_0_S1 undriven
+ or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/un1_ce_frmctr_1_cry_0_0_S0 undriven
+ or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/un1_ce_frmctr_1_s_3_0_S1 undriven or
+ does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/un1_ce_frmctr_1_s_3_0_COUT undriven
+ or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/un1_trg_qqqq_cry_0_0_S0 undriven or
+ does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/un1_trg_qqqq_cry_7_0_COUT undriven
+ or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_final_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_final_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_final_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_final_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_final_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_final_cry_3_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_1_gt_0_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_1_gt_0_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_1_gt_0_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_1_gt_0_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_1_gt_0_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_1_gt_0_cry_3_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_32_gt_21_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_32_gt_21_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_32_gt_21_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_32_gt_21_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_32_gt_21_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+
+ Page 309
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_32_gt_21_cry_3_0_COUT undriven or does
+ not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_21_gt_10_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_21_gt_10_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_21_gt_10_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_21_gt_10_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_21_gt_10_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_21_gt_10_cry_3_0_COUT undriven or does
+ not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_3_gt_2_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_3_gt_2_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_3_gt_2_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_3_gt_2_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_3_gt_2_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_3_gt_2_cry_3_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_2_gt_1_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_2_gt_1_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_2_gt_1_cry_1_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_2_gt_1_cry_1_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_2_gt_1_cry_3_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_MAX_TRG/comb_2_gt_1_cry_3_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_EDS_BUF/eds_free_ctr_4_cry_0_0_S1 undriven or does
+ not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_EDS_BUF/eds_free_ctr_4_cry_0_0_S0 undriven or does
+ not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_EDS_BUF/eds_free_ctr_4_cry_3_0_COUT undriven or does
+ not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/un1_delay_ctr_ce_cry_0_0_S1_2
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/un1_delay_ctr_ce_cry_0_0_S0_2
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/un1_delay_ctr_ce_s_3_0_S1_2
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/un1_delay_ctr_ce_s_3_0_COUT_2
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/un1_apv_trgcnt_cry_0_0_S1_2
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/un1_apv_trgcnt_cry_0_0_S0_2
+ undriven or does not drive anything - clipped.
+
+ Page 310
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/un1_apv_trgcnt_s_3_0_S1_2 undriven
+ or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/un1_apv_trgcnt_s_3_0_COUT_2
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/un1_delay_ctr_ce_cry_0_0_S1_1
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/un1_delay_ctr_ce_cry_0_0_S0_1
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/un1_delay_ctr_ce_s_3_0_S1_1
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/un1_delay_ctr_ce_s_3_0_COUT_1
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/un1_apv_trgcnt_cry_0_0_S1_1
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/un1_apv_trgcnt_cry_0_0_S0_1
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/un1_apv_trgcnt_s_3_0_S1_1 undriven
+ or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/un1_apv_trgcnt_s_3_0_COUT_1
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/un1_delay_ctr_ce_cry_0_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/un1_delay_ctr_ce_cry_0_0_S0_0
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/un1_delay_ctr_ce_s_3_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/un1_delay_ctr_ce_s_3_0_COUT_0
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/un1_apv_trgcnt_cry_0_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/un1_apv_trgcnt_cry_0_0_S0_0
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/un1_apv_trgcnt_s_3_0_S1_0 undriven
+ or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/un1_apv_trgcnt_s_3_0_COUT_0
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/un1_delay_ctr_ce_cry_0_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/un1_delay_ctr_ce_cry_0_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/un1_delay_ctr_ce_s_3_0_S1 undriven
+ or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/un1_delay_ctr_ce_s_3_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/un1_apv_trgcnt_cry_0_0_S1 undriven
+ or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/un1_apv_trgcnt_cry_0_0_S0 undriven
+ or does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/un1_apv_trgcnt_s_3_0_S1 undriven or
+ does not drive anything - clipped.
+Signal THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/un1_apv_trgcnt_s_3_0_COUT undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/reset_word_cnt_cry_0_S0_0 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/reset_word_cnt_cry_0_COUT_3 undriven or
+ does not drive anything - clipped.
+
+ Page 311
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/un1_led_counter_1_cry_0_0_S1 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/un1_led_counter_1_cry_0_0_S0 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/un1_led_counter_1_cry_15_0_COUT undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_cry_0_S0_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_cry_0_COUT_27
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_TXFBFIFO_ERR
+ OR_3 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/link_error_2
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_TXFBFIFO_ERR
+ OR_1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_TXFBFIFO_ERR
+ OR_0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_RXFBFIFO_ERR
+ OR_3 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/link_error_3
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_RXFBFIFO_ERR
+ OR_1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_RXFBFIFO_ERR
+ OR_0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_RLOL_3
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_RLOL_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_RLOL_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/SCIRDATA7
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/SCIRDATA6
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/SCIRDATA5
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/SCIRDATA4
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/SCIRDATA3
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/SCIRDATA2
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/SCIRDATA1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/SCIRDATA0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/SCIINT undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/REFCK2CORE
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/OOB_OUT_3
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/un1_THE_SERDES_4
+ undriven or does not drive anything - clipped.
+
+ Page 312
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/OOB_OUT_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/OOB_OUT_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_RLOS_LO_3
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/link_error_8
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_RLOS_LO_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_RLOS_LO_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_PCIE_DONE_3
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_PCIE_DONE_2
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_PCIE_DONE_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_PCIE_DONE_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_PCIE_CON_3
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_PCIE_CON_2
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_PCIE_CON_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_PCIE_CON_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_LS_SYNC_STAT
+ US_3 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_LS_SYNC_STAT
+ US_1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_LS_SYNC_STAT
+ US_0 undriven or does not drive anything - clipped.
+Signal
+ THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_CC_UNDERRUN_3
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/link_error_0
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_CC_UNDERRUN_1
+ undriven or does not drive anything - clipped.
+Signal
+ THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_CC_UNDERRUN_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_CC_OVERRUN_3
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/link_error_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_CC_OVERRUN_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FFS_CC_OVERRUN_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_TX_Q_CLK
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/ff_txhalfclk
+
+ Page 313
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_Q_CLK_3
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_Q_CLK_2
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_Q_CLK_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_Q_CLK_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_H_CLK_3
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/un1_THE_SERDES_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_H_CLK_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_H_CLK_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_F_CLK_3
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/un1_THE_SERDES
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_F_CLK_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_F_CLK_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_23
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_22
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_21
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_20
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_19
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_18
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_17
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_16
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_15
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_14
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_13
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_12
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_11
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_10
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_9
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_8
+
+ Page 314
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_7
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_6
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_5
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_4
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_3
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_2
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_3_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/un1_THE_SERDES_2
+ _1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/un1_THE_SERDES_3
+ _1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/un1_THE_SERDES_2
+ _0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/un1_THE_SERDES_3
+ _0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_23
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_22
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_21
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_20
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_19
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_18
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_17
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_16
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_15
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_14
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_13
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_12
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_11
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_10
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_9
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_8
+
+ Page 315
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_7
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_6
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_5
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_4
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_3
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_2
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_1_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_23
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_22
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_21
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_20
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_19
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_18
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_17
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_16
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_15
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_14
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_13
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_12
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_11
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_10
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_9
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_8
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_7
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_6
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_5
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_4
+
+ Page 316
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_3
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_2
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/FF_RX_D_0_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_19 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_18 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_17 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_16 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_15 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_14 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_13 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_12 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_11 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_10 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_9 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_8 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_7 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_6 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_5 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_4 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_3 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_2 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_1 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/cout_0 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_a1
+ _1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_a1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_fu
+ ll_cmp_ci_a_1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_fu
+
+ Page 317
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ ll_cmp_ci_a undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_a0
+ _1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_a0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_em
+ pty_cmp_ci_a_1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_em
+ pty_cmp_ci_a undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_r_
+ gctr_5 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/co5_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_r_
+ gctr_cia_1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_r_
+ gctr_cia undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_w_
+ gctr_5 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/co5
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_w_
+ gctr_cia_1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_w_
+ gctr_cia undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_11 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_10 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_13 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_3 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_2 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_9 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_8 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_7 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_6 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_5 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_14 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_12 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_15 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+
+ Page 318
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ p_ram_0_0_0_17 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_16 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_4 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_a1
+ _1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_a1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_fu
+ ll_cmp_ci_a_1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_fu
+ ll_cmp_ci_a undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_a0
+ _1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_a0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_em
+ pty_cmp_ci_a_1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_em
+ pty_cmp_ci_a undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_r_
+ gctr_5 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/co5_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_r_
+ gctr_cia_1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_r_
+ gctr_cia undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_w_
+ gctr_5 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/co5
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_w_
+ gctr_cia_1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_w_
+ gctr_cia undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/fifo_t
+ x_dout_17 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/fifo_t
+ x_dout_16 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_11 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_10 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_13 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_3 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_2 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_9 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+
+ Page 319
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ p_ram_0_0_0_8 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_7 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_6 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_5 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_14 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_12 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_15 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_17 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_16 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/un1_pd
+ p_ram_0_0_0_4 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/int_trigger_num_4_cry_0_0_S1 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/int_trigger_num_4_cry_0_0_S0 undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/int_trigger_num_4_s_15_0_S1 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/int_trigger_num_4_s_15_0_COUT undriven
+ or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/un4_lvl1_trg_received_out_rising_0_I_1_
+ 0_S1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/un4_lvl1_trg_received_out_rising_0_I_1_
+ 0_S0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/un4_lvl1_trg_received_out_rising_0_I_10
+ _0_S1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/un4_lvl1_trg_received_out_rising_0_I_10
+ _0_S0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/un4_lvl1_trg_received_out_rising_0_I_37
+ _0_S1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/un4_lvl1_trg_received_out_rising_0_I_37
+ _0_S0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/un4_lvl1_trg_received_out_rising_0_I_46
+ _0_S1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/un4_lvl1_trg_received_out_rising_0_I_46
+ _0_S0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/un4_lvl1_trg_received_out_rising_0_I_28
+ _0_S0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/un4_lvl1_trg_received_out_rising_0_I_28
+ _0_COUT undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/reply_buffer_number_cry_0_S0_0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/reply_buffer_number_s_0_S1_15 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+
+ Page 320
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ E_IBUF/reply_buffer_number_s_0_COUT_15 undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/co4_4 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_r_ctr_cia_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_r_ctr_cia undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/co4_3 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_w_ctr_cia_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_w_ctr_cia undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_a1_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_a1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_g_cmp_ci_a_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_g_cmp_ci_a undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_a0_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_a0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_e_cmp_ci_a_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_e_cmp_ci_a undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_bdcnt_bctr_5 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/co5 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_bdcnt_bctr_cia_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_bdcnt_bctr_cia undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_6 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_5 undriven or does not drive
+
+ Page 321
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_12 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_11 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_10 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_9 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_8 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_7 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0 undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_17 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_16 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_15 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_14 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_4 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_3 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_2 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_13 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/CURRENT_DATA_COUNT_cry_0_S0_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/CURRENT_DATA_COUNT_cry_0_COUT_5 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+
+ Page 322
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ F1_REPLYOBUF/buffer_number_cry_0_S0_0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/buffer_number_s_0_S1_15 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/buffer_number_s_0_COUT_15 undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_0_0_S1_1 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_0_0_S0_1 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_2 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_4 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_s_7_0_S1_1 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_s_7_0_COUT_1 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_6 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_2 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_7 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_6 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_5 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_4 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_3 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/N_528 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+
+ Page 323
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ F1_REPLYOBUF/un9_wait_for_ack_counter undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un9_wait_for_ack_counter_4_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un9_wait_for_ack_counter_5_bm undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un9_wait_for_ack_counter_5_am undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_8 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_4 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_7 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_3 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_6 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_2 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_5 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_4 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_3 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_2 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_7 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_1 undriven or does not drive anything -
+ clipped.
+
+ Page 324
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_6 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_5 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_timeout undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un1_wait_for_ack_counter_7 undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/timer_tick undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_max_bit_2 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_max_bit_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_timeoutc undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/N_346 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/N_347 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_max_bit_0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/un1_reply_buffer_number_0_sqmuxa_cry_0_0_S0_0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/un1_reply_buffer_number_0_sqmuxa_s_15_0_S1_0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/un1_reply_buffer_number_0_sqmuxa_s_15_0_COUT_0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/co4_4 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_r_ctr_cia_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_r_ctr_cia undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/co4_3 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_w_ctr_cia_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+
+ Page 325
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ E_IBUF/THE_FIFO/fifo/un1_w_ctr_cia undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_a1_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_a1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_g_cmp_ci_a_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_g_cmp_ci_a undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_a0_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_a0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_e_cmp_ci_a_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_e_cmp_ci_a undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_bdcnt_bctr_5 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/co5 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_bdcnt_bctr_cia_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_bdcnt_bctr_cia undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_6 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_5 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_12 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_11 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_10 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_9 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_8 undriven or does not drive
+ anything - clipped.
+
+ Page 326
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_7 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0 undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_17 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_16 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_15 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_14 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_4 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_3 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_2 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_13 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un1_buffer_number_0_sqmuxa_cry_0_0_S0_0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un1_buffer_number_0_sqmuxa_s_15_0_S1_0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un1_buffer_number_0_sqmuxa_s_15_0_COUT_0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_0_0_S1_0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_0_0_S0_0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_2 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_4 undriven or does not drive
+
+ Page 327
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_s_7_0_S1_0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_s_7_0_COUT_0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_6 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un3_clk_en_cry_0_0_S0_0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un3_clk_en_cry_5_0_COUT_0 undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_4 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_3 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_2 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_7 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_6 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_5 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/N_578 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un9_wait_for_ack_counter undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un9_wait_for_ack_counter_5_bm_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un9_wait_for_ack_counter_5_am_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un9_wait_for_ack_counter_4_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_8 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_2 undriven or does not drive anything -
+
+ Page 328
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_7 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_6 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_5 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_4 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_7 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_3 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_6 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_2 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_5 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_4 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_3 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_timeout undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un1_wait_for_ack_counter_4 undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+
+ Page 329
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ F1_REPLYOBUF/timer_tick undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_max_bit_2 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_max_bit_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_timeoutc undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/N_508 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/N_509 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_max_bit_0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/un1_reply_buffer_number_0_sqmuxa_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/un1_reply_buffer_number_0_sqmuxa_s_15_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/un1_reply_buffer_number_0_sqmuxa_s_15_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/co4_4 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_r_ctr_cia_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_r_ctr_cia undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/co4_3 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_w_ctr_cia_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_w_ctr_cia undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_a1_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_a1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_g_cmp_ci_a_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_g_cmp_ci_a undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_a0_1 undriven or does not drive anything -
+ clipped.
+
+ Page 330
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_a0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_e_cmp_ci_a_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_e_cmp_ci_a undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_bdcnt_bctr_5 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/co5 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_bdcnt_bctr_cia_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_bdcnt_bctr_cia undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_6 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_5 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_12 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_11 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_10 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_9 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_8 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_7 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0 undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_17 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_16 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+
+ Page 331
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_15 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_14 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_4 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_3 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_2 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_TH
+ E_IBUF/THE_FIFO/fifo/un1_pdp_ram_0_0_0_13 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un1_buffer_number_0_sqmuxa_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un1_buffer_number_0_sqmuxa_s_15_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un1_buffer_number_0_sqmuxa_s_15_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_0_0_S1 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_0_0_S0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_2 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_4 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_s_7_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_s_7_0_COUT undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_cry_6 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un3_clk_en_cry_0_0_S0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un3_clk_en_cry_5_0_COUT undriven or does not drive anything -
+ clipped.
+
+ Page 332
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_4 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_3 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_2 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_7 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_6 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un26_wait_for_ack_counter_5 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/N_578 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un9_wait_for_ack_counter undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un9_wait_for_ack_counter_4_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un9_wait_for_ack_counter_5_bm_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un9_wait_for_ack_counter_5_am_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_8 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_2 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_7 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_6 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_5 undriven or does not drive anything -
+ clipped.
+
+ Page 333
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_4 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_7 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_3 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_6 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_2 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_5 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_4 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counter_0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_counterc_3 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_timeout undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/un1_wait_for_ack_counter_4 undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/timer_tick undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_max_bit_2 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_max_bit_1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_timeoutc undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/N_508 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/N_509 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBU
+ F1_REPLYOBUF/wait_for_ack_max_bit_0 undriven or does not drive anything -
+
+ Page 334
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/un1_master_end_0_sqmuxa_cry_0_0_S0_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/un1_master_end_0_sqmuxa_s_7_0_S1_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/un1_master_end_0_sqmuxa_s_7_0_COUT_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_1_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_1_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_10_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_10_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_37_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_37_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_46_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_46_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_28_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_28_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/SBUF_TO_APL2/N_44_li undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/SBUF_TO_APL2/current_SYN_DATAREADY_OUT_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/SBUF_TO_APL2/N_104_i undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/SBUF_TO_APL2/current_next_READ_OUT_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/SBUF_TO_APL2/N_105_i undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+
+ Page 335
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_r_ctr_cia_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_r_ctr_cia undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_w_ctr_cia_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_w_ctr_cia undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_a1_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_a1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_g_cmp_ci_a_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_g_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_a0_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_a0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_e_cmp_ci_a_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_e_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_bdcnt_bctr_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_bdcnt_bctr_cia_1 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_bdcnt_bctr_cia undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_6 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_5 undriven or
+ does not drive anything - clipped.
+
+ Page 336
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_12 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_11 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_10 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_9 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_8 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_7 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_1 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_17 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_16 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_15 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_14 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_2 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_13 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_r_ctr_cia_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_r_ctr_cia undriven or does not
+
+ Page 337
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_w_ctr_cia_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_w_ctr_cia undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_a1_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_a1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_g_cmp_ci_a_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_g_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_a0_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_a0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_e_cmp_ci_a_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_e_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_bdcnt_bctr_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_bdcnt_bctr_cia_1 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_bdcnt_bctr_cia undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/fifo_to_int_packet_num_out_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/fifo_to_int_packet_num_out_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_6 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+
+ Page 338
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_5 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_12 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_11 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_10 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_9 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_8 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_7 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_1 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_17 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_16 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_15 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_14 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_2 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_13 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/un1_master_end_0_sqmuxa_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/un1_master_end_0_sqmuxa_s_7_0_S1 undriven or does not drive anything
+ - clipped.
+
+ Page 339
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/un1_master_end_0_sqmuxa_s_7_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_1_0_S1_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_1_0_S0_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_10_0_S1_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_10_0_S0_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_37_0_S1_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_37_0_S0_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_46_0_S1_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_46_0_S0_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_28_0_S0_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/un9_int_slave_dataready_in_0_I_28_0_COUT_0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/SBUF_TO_APL2/N_87_li undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/SBUF_TO_APL2/current_SYN_DATAREADY_OUT_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/SBUF_TO_APL2/N_147_i undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/SBUF_TO_APL2/current_next_READ_OUT_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/SBUF_TO_APL2/N_148_i undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_r_ctr_cia_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_r_ctr_cia undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/co4_3 undriven or does not drive
+
+ Page 340
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_w_ctr_cia_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_w_ctr_cia undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_a1_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_a1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_g_cmp_ci_a_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_g_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_a0_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_a0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_e_cmp_ci_a_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_e_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_bdcnt_bctr_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_bdcnt_bctr_cia_1 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_bdcnt_bctr_cia undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_6 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_5 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_12 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_11 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+
+ Page 341
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_10 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_9 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_8 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_7 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_1 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_17 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_16 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_15 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_14 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_2 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/un1_pdp_ram_0_0_0_13 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/co4_4 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_r_ctr_cia_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_r_ctr_cia undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/co4_3 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_w_ctr_cia_1 undriven or does
+ not drive anything - clipped.
+
+ Page 342
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_w_ctr_cia undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_a1_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_a1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_g_cmp_ci_a_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_g_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_a0_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_a0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_e_cmp_ci_a_1 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_e_cmp_ci_a undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_bdcnt_bctr_5 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/co5 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_bdcnt_bctr_cia_1 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_bdcnt_bctr_cia undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/fifo_to_int_packet_num_out_1
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/fifo_to_int_packet_num_out_0
+ undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_6 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_5 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_12 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_11 undriven or
+
+ Page 343
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_10 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_9 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_8 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_7 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_1 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0 undriven or does
+ not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_17 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_16 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_15 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_14 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_4 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_3 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_2 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSI
+ VE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/un1_pdp_ram_0_0_0_13 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/buf_IPU_LENGTH_IN_cry_0_S0_0 undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/buf_IPU_LENGTH_IN_s_0_S1_15 undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/buf_IPU_LENGTH_IN_s_0_COUT_15 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un1_api_length_out_1_cry_0_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+
+ Page 344
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ pudata_apl/un1_api_length_out_1_cry_0_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un1_api_length_out_1_cry_13_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un15_make_compare_0_I_1_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un15_make_compare_0_I_1_0_S0 undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un15_make_compare_0_I_10_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un15_make_compare_0_I_10_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un15_make_compare_0_I_37_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un15_make_compare_0_I_37_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un15_make_compare_0_I_46_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un15_make_compare_0_I_46_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un15_make_compare_0_I_28_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un15_make_compare_0_I_28_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un20_make_compare_0_I_1_0_S1 undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un20_make_compare_0_I_1_0_S0 undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un20_make_compare_0_I_10_0_S1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un20_make_compare_0_I_10_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un20_make_compare_0_I_28_0_S0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_i
+ pudata_apl/un20_make_compare_0_I_28_0_COUT undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/n
+ ext_dat_data_counter_cry_0_0_S1 undriven or does not drive anything -
+ clipped.
+
+ Page 345
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/n
+ ext_dat_data_counter_cry_0_0_S0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/n
+ ext_dat_data_counter_s_15_0_S1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/n
+ ext_dat_data_counter_s_15_0_COUT undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/n
+ ext_address_cry_0_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/n
+ ext_address_cry_0_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/n
+ ext_address_s_15_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/n
+ ext_address_s_15_0_COUT undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/l
+ ength_3_cry_0_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/l
+ ength_3_cry_0_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/l
+ ength_3_s_15_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/l
+ ength_3_s_15_0_COUT undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/g
+ lobal_time_i_cry_0_S0_0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/g
+ lobal_time_i_s_0_S1_31 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/g
+ lobal_time_i_s_0_COUT_31 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ ime_since_last_trg_i_cry_0_S0_0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ ime_since_last_trg_i_s_0_S1_31 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ ime_since_last_trg_i_s_0_COUT_31 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/u
+ n4_local_time_i_cry_0_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/u
+ n4_local_time_i_cry_0_0_S0 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/u
+ n4_local_time_i_s_7_0_S1 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/u
+ n4_local_time_i_s_7_0_COUT undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/T
+ IMER_MS_TICK_0_sqmuxa_8 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/T
+ IMER_MS_TICK_0_sqmuxa_7 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/T
+ IMER_MS_TICK_0_sqmuxa_6 undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/TIMER_MS_TICK_Q undriven or does not
+ drive anything - clipped.
+
+ Page 346
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/T
+ IMER_MS_TICK_0_sqmuxa undriven or does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/un29_clk_en_0_I_1_0_S1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/un29_clk_en_0_I_1_0_S0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/un29_clk_en_0_I_10_0_S1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/un29_clk_en_0_I_10_0_S0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/un29_clk_en_0_I_37_0_S1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/un29_clk_en_0_I_37_0_S0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/un29_clk_en_0_I_46_0_S1 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/un29_clk_en_0_I_46_0_S0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/un29_clk_en_0_I_28_0_S0 undriven or does not drive anything -
+ clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/un29_clk_en_0_I_28_0_COUT undriven or does not drive anything
+ - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/ram_1_ram_1_0_0_DOB17 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/ram_1_ram_1_0_0_DOB16 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_15 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_14 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_13 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_12 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_11 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_10 undriven or does not drive
+ anything - clipped.
+
+ Page 347
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_9 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_8 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_7 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_6 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_5 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_4 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_3 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_2 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_1 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/buf_IDRAM_DATA_OUT_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/ram_1_ram_1_0_0_DOA17 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/t
+ he_addresses/THE_STAT_RAM/ram_1_ram_1_0_0_DOA16 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wi
+ re_onewire_interface/timecounter_cry_0_S0_0 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wi
+ re_onewire_interface/timecounter_s_0_S1_27 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wi
+ re_onewire_interface/timecounter_s_0_COUT_27 undriven or does not drive
+ anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wi
+ re_onewire_interface/un1_inc_bitcounter_cry_0_0_S0_0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wi
+ re_onewire_interface/un1_inc_bitcounter_cry_5_0_COUT_0 undriven or does not
+ drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/buf_INT_DATA_OUT_1_47 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/buf_INT_DATA_OUT_1_46 undriven or
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/buf_INT_DATA_OUT_1_45 undriven or
+
+ Page 348
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ does not drive anything - clipped.
+Signal THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/buf_INT_DATA_OUT_1_44 undriven or
+ does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_3_THE_PED_MEM/ped_data_3_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_3_THE_PED_MEM/ped_data_3_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_3_THE_PED_MEM/ped_data_3_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_3_THE_PED_MEM/ped_data_3_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_3_THE_PED_MEM/ped_data_3_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_2_THE_PED_MEM/ped_data_2_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_2_THE_PED_MEM/ped_data_2_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_2_THE_PED_MEM/ped_data_2_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_2_THE_PED_MEM/ped_data_2_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_2_THE_PED_MEM/ped_data_2_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_0_THE_PED_MEM/ped_data_0_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_0_THE_PED_MEM/ped_data_0_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_0_THE_PED_MEM/ped_data_0_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_0_THE_PED_MEM/ped_data_0_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_0_THE_PED_MEM/ped_data_0_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_1_THE_PED_MEM/ped_data_1_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_1_THE_PED_MEM/ped_data_1_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_1_THE_PED_MEM/ped_data_1_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_1_THE_PED_MEM/ped_data_1_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_1_THE_PED_MEM/ped_data_1_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_10_THE_PED_MEM/ped_data_10_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_10_THE_PED_MEM/ped_data_10_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_10_THE_PED_MEM/ped_data_10_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_10_THE_PED_MEM/ped_data_10_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_10_THE_PED_MEM/ped_data_10_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_6_THE_PED_MEM/ped_data_6_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_6_THE_PED_MEM/ped_data_6_15
+
+ Page 349
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_6_THE_PED_MEM/ped_data_6_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_6_THE_PED_MEM/ped_data_6_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_6_THE_PED_MEM/ped_data_6_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_5_THE_PED_MEM/ped_data_5_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_5_THE_PED_MEM/ped_data_5_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_5_THE_PED_MEM/ped_data_5_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_5_THE_PED_MEM/ped_data_5_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_5_THE_PED_MEM/ped_data_5_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_11_THE_PED_MEM/ped_data_11_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_11_THE_PED_MEM/ped_data_11_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_11_THE_PED_MEM/ped_data_11_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_11_THE_PED_MEM/ped_data_11_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_11_THE_PED_MEM/ped_data_11_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_7_THE_PED_MEM/ped_data_7_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_7_THE_PED_MEM/ped_data_7_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_7_THE_PED_MEM/ped_data_7_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_7_THE_PED_MEM/ped_data_7_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_7_THE_PED_MEM/ped_data_7_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_12_THE_PED_MEM/ped_data_12_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_12_THE_PED_MEM/ped_data_12_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_12_THE_PED_MEM/ped_data_12_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_12_THE_PED_MEM/ped_data_12_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_12_THE_PED_MEM/ped_data_12_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_8_THE_PED_MEM/ped_data_8_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_8_THE_PED_MEM/ped_data_8_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_8_THE_PED_MEM/ped_data_8_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_8_THE_PED_MEM/ped_data_8_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_8_THE_PED_MEM/ped_data_8_12
+
+ Page 350
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_4_THE_PED_MEM/ped_data_4_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_4_THE_PED_MEM/ped_data_4_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_4_THE_PED_MEM/ped_data_4_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_4_THE_PED_MEM/ped_data_4_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_4_THE_PED_MEM/ped_data_4_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_14_THE_PED_MEM/ped_data_14_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_14_THE_PED_MEM/ped_data_14_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_14_THE_PED_MEM/ped_data_14_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_14_THE_PED_MEM/ped_data_14_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_14_THE_PED_MEM/ped_data_14_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_15_THE_PED_MEM/ped_data_15_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_15_THE_PED_MEM/ped_data_15_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_15_THE_PED_MEM/ped_data_15_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_15_THE_PED_MEM/ped_data_15_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_15_THE_PED_MEM/ped_data_15_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_9_THE_PED_MEM/ped_data_9_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_9_THE_PED_MEM/ped_data_9_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_9_THE_PED_MEM/ped_data_9_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_9_THE_PED_MEM/ped_data_9_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_9_THE_PED_MEM/ped_data_9_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_13_THE_PED_MEM/ped_data_13_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_13_THE_PED_MEM/ped_data_13_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_13_THE_PED_MEM/ped_data_13_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_13_THE_PED_MEM/ped_data_13_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_13_THE_PED_MEM/ped_data_13_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_3_THE_PED_MEM/thr_data_3_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_3_THE_PED_MEM/thr_data_3_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_3_THE_PED_MEM/thr_data_3_15
+
+ Page 351
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_3_THE_PED_MEM/thr_data_3_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_3_THE_PED_MEM/thr_data_3_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_3_THE_PED_MEM/thr_data_3_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_2_THE_PED_MEM/thr_data_2_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_2_THE_PED_MEM/thr_data_2_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_2_THE_PED_MEM/thr_data_2_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_2_THE_PED_MEM/thr_data_2_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_2_THE_PED_MEM/thr_data_2_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_2_THE_PED_MEM/thr_data_2_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_0_THE_PED_MEM/thr_data_0_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_0_THE_PED_MEM/thr_data_0_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_0_THE_PED_MEM/thr_data_0_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_0_THE_PED_MEM/thr_data_0_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_0_THE_PED_MEM/thr_data_0_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_0_THE_PED_MEM/thr_data_0_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_1_THE_PED_MEM/thr_data_1_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_1_THE_PED_MEM/thr_data_1_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_1_THE_PED_MEM/thr_data_1_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_1_THE_PED_MEM/thr_data_1_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_1_THE_PED_MEM/thr_data_1_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_1_THE_PED_MEM/thr_data_1_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_10_THE_PED_MEM/thr_data_10_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_10_THE_PED_MEM/thr_data_10_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_10_THE_PED_MEM/thr_data_10_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_10_THE_PED_MEM/thr_data_10_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_10_THE_PED_MEM/thr_data_10_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_10_THE_PED_MEM/thr_data_10_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_6_THE_PED_MEM/thr_data_6_17
+
+ Page 352
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_6_THE_PED_MEM/thr_data_6_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_6_THE_PED_MEM/thr_data_6_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_6_THE_PED_MEM/thr_data_6_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_6_THE_PED_MEM/thr_data_6_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_6_THE_PED_MEM/thr_data_6_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_5_THE_PED_MEM/thr_data_5_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_5_THE_PED_MEM/thr_data_5_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_5_THE_PED_MEM/thr_data_5_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_5_THE_PED_MEM/thr_data_5_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_5_THE_PED_MEM/thr_data_5_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_5_THE_PED_MEM/thr_data_5_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_11_THE_PED_MEM/thr_data_11_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_11_THE_PED_MEM/thr_data_11_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_11_THE_PED_MEM/thr_data_11_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_11_THE_PED_MEM/thr_data_11_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_11_THE_PED_MEM/thr_data_11_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_11_THE_PED_MEM/thr_data_11_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_7_THE_PED_MEM/thr_data_7_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_7_THE_PED_MEM/thr_data_7_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_7_THE_PED_MEM/thr_data_7_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_7_THE_PED_MEM/thr_data_7_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_7_THE_PED_MEM/thr_data_7_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_7_THE_PED_MEM/thr_data_7_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_12_THE_PED_MEM/thr_data_12_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_12_THE_PED_MEM/thr_data_12_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_12_THE_PED_MEM/thr_data_12_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_12_THE_PED_MEM/thr_data_12_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_12_THE_PED_MEM/thr_data_12_13
+
+ Page 353
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_12_THE_PED_MEM/thr_data_12_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_8_THE_PED_MEM/thr_data_8_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_8_THE_PED_MEM/thr_data_8_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_8_THE_PED_MEM/thr_data_8_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_8_THE_PED_MEM/thr_data_8_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_8_THE_PED_MEM/thr_data_8_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_8_THE_PED_MEM/thr_data_8_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_4_THE_PED_MEM/thr_data_4_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_4_THE_PED_MEM/thr_data_4_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_4_THE_PED_MEM/thr_data_4_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_4_THE_PED_MEM/thr_data_4_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_4_THE_PED_MEM/thr_data_4_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_4_THE_PED_MEM/thr_data_4_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_14_THE_PED_MEM/thr_data_14_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_14_THE_PED_MEM/thr_data_14_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_14_THE_PED_MEM/thr_data_14_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_14_THE_PED_MEM/thr_data_14_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_14_THE_PED_MEM/thr_data_14_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_14_THE_PED_MEM/thr_data_14_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_15_THE_PED_MEM/thr_data_15_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_15_THE_PED_MEM/thr_data_15_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_15_THE_PED_MEM/thr_data_15_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_15_THE_PED_MEM/thr_data_15_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_15_THE_PED_MEM/thr_data_15_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_15_THE_PED_MEM/thr_data_15_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_9_THE_PED_MEM/thr_data_9_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_9_THE_PED_MEM/thr_data_9_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_9_THE_PED_MEM/thr_data_9_15
+
+ Page 354
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_9_THE_PED_MEM/thr_data_9_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_9_THE_PED_MEM/thr_data_9_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_9_THE_PED_MEM/thr_data_9_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_13_THE_PED_MEM/thr_data_13_17
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_13_THE_PED_MEM/thr_data_13_16
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_13_THE_PED_MEM/thr_data_13_15
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_13_THE_PED_MEM/thr_data_13_14
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_13_THE_PED_MEM/thr_data_13_13
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_13_THE_PED_MEM/thr_data_13_12
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/THE_I2C_SENDB/cctr_4_cry_0_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/THE_I2C_SENDB/cctr_4_cry_0_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/THE_I2C_SENDB/cctr_4_s_7_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/THE_I2C_SENDB/cctr_4_s_7_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/THE_I2C_GSTART/cctr_4_cry_0_0_S
+ 1_0 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/THE_I2C_GSTART/cctr_4_cry_0_0_S
+ 0_0 undriven or does not drive anything - clipped.
+Signal
+ THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/THE_I2C_GSTART/cctr_4_s_7_0_S1_0
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/THE_I2C_GSTART/cctr_4_s_7_0_COU
+ T_0 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/addr_ctr_cry_0_S0_0 undriven or
+ does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/addr_ctr_s_0_S1_7 undriven or
+ does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/addr_ctr_s_0_COUT_7 undriven or
+ does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/data_done_x_0_I_1_0_S1 undriven
+ or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/data_done_x_0_I_1_0_S0 undriven
+ or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/data_done_x_0_I_10_0_S1
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/data_done_x_0_I_10_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/data_done_x_0_I_28_0_S0
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/data_done_x_0_I_28_0_COUT
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ B17 undriven or does not drive anything - clipped.
+
+ Page 355
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ B16 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ B15 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ B14 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ B13 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ B12 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ B11 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ B10 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ B9 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ B8 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ B7 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ B6 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ B5 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ B4 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ A17 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0_DO
+ A8 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ B17 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ B16 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ B15 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ B14 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ B13 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ B12 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ B11 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ B10 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ B9 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ B8 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ B7 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ B6 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ B5 undriven or does not drive anything - clipped.
+
+ Page 356
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ B4 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ A17 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1_DO
+ A8 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/wr_ctr_cry_0_S0_0 undriven or does not
+ drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/wr_ctr_s_0_S1_9 undriven or does not drive
+ anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/wr_ctr_s_0_COUT_9 undriven or does not
+ drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _15 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _14 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _10 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _9 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _3 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _2 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _1 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _8 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _7 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _19 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _18 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _13 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _12 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _11 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _5 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _17 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _16 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _6 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _4 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/wr_ctr_cry_0_S0_0_0 undriven or does not
+ drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/wr_ctr_s_0_S1_0_9 undriven or does not
+ drive anything - clipped.
+
+ Page 357
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/wr_ctr_s_0_COUT_0_9 undriven or does not
+ drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _15 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _14 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _10 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _9 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _3 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _2 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _1 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _8 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _7 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _19 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _18 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _13 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _12 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _11 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _5 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _17 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _16 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _6 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/un1_adc_snoop_mem_0_0_0
+ _4 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_SLV_ONEWIRE_DPRAM/slv_onewire_dpram_
+ 0_0_0_DOB17 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_SLV_ONEWIRE_DPRAM/slv_onewire_dpram_
+ 0_0_0_DOB16 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_SLV_ONEWIRE_DPRAM/slv_onewire_dpram_
+ 0_0_0_DOA17 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_SLV_ONEWIRE_DPRAM/slv_onewire_dpram_
+ 0_0_0_DOA16 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/timecounter_cry_0_S0_
+ 0_0 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/timecounter_s_0_S1_0_
+ 27 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/timecounter_s_0_COUT_
+ 0_27 undriven or does not drive anything - clipped.
+
+ Page 358
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Signal THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/un1_inc_bitcounter_cr
+ y_0_0_S0 undriven or does not drive anything - clipped.
+Signal THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/un1_inc_bitcounter_cr
+ y_5_0_COUT undriven or does not drive anything - clipped.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE
+ _IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/COMB_next_READ_OUT_f0 was
+ optimized away.
+Block THE_SYNC_PLL/PLLDInst_0_RNIJ36 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/INV_3 was optimized away.
+
+ Page 359
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/INV_1 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/INV_6 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/INV_8 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/INV_6 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/INV_8 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/INV_6 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/INV_8 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/INV_6 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/INV_8 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/INV_6 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/INV_8 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/INV_6 was optimized away.
+
+ Page 360
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/INV_8 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/INV_6 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/INV_8 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/INV_6 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/INV_8 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/INV_6 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/INV_8 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/INV_6 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/INV_8 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/INV_6 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/INV_8 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/INV_6 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/INV_8 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/INV_6 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/INV_8 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/INV_6 was optimized away.
+
+ Page 361
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/INV_8 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/INV_6 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/INV_8 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/INV_0 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/INV_2 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/INV_3 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/INV_5 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/INV_6 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/INV_7 was optimized away.
+Block THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/INV_8 was optimized away.
+Block THE_PED_CORR_STAGE/GEN_TOC_0_THE_BUF_TOC/stat_good_RNIO1R2 was optimized
+ away.
+Block THE_PED_CORR_STAGE/GEN_TOC_2_THE_BUF_TOC/stat_good_RNIQ1R2 was optimized
+ away.
+Block THE_PED_CORR_STAGE/GEN_TOC_6_THE_BUF_TOC/stat_good_RNIU1R2 was optimized
+ away.
+Block THE_PED_CORR_STAGE/GEN_TOC_15_THE_BUF_TOC/stat_good_RNISO8 was optimized
+ away.
+Block THE_PED_CORR_STAGE/GEN_TOC_12_THE_BUF_TOC/stat_good_RNIBT22 was optimized
+ away.
+Block THE_PED_CORR_STAGE/GEN_TOC_14_THE_BUF_TOC/stat_good_RNI15S was optimized
+ away.
+Block THE_PED_CORR_STAGE/GEN_TOC_9_THE_BUF_TOC/stat_good_RNI12R2 was optimized
+ away.
+Block THE_PED_CORR_STAGE/GEN_TOC_8_THE_BUF_TOC/stat_good_RNI02R2 was optimized
+ away.
+Block THE_PED_CORR_STAGE/GEN_TOC_3_THE_BUF_TOC/stat_good_RNIR1R2 was optimized
+ away.
+Block THE_PED_CORR_STAGE/GEN_TOC_7_THE_BUF_TOC/stat_good_RNIV1R2 was optimized
+ away.
+Block THE_PED_CORR_STAGE/GEN_TOC_10_THE_BUF_TOC/stat_good_RNILL93 was optimized
+ away.
+Block THE_PED_CORR_STAGE/GEN_TOC_1_THE_BUF_TOC/stat_good_RNIP1R2 was optimized
+ away.
+Block THE_PED_CORR_STAGE/GEN_TOC_13_THE_BUF_TOC/stat_good_RNI6HF1 was optimized
+ away.
+Block THE_PED_CORR_STAGE/GEN_TOC_5_THE_BUF_TOC/stat_good_RNIT1R2 was optimized
+ away.
+Block THE_PED_CORR_STAGE/GEN_TOC_4_THE_BUF_TOC/stat_good_RNIS1R2 was optimized
+ away.
+Block THE_PED_CORR_STAGE/GEN_TOC_11_THE_BUF_TOC/stat_good_RNIG9M2 was optimized
+ away.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8_
+ RNIOJD1 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4_
+ 0 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8_
+ RNINJD1 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4_
+ 0 was optimized away.
+
+ Page 362
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8_
+ RNILJD1 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4_
+ 0 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8_
+ RNIPJD1 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4_
+ 0 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8_
+ RNIMJD1 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4_
+ 0 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8_
+ RNIRJD1 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4_
+ 0 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8_
+ RNIQJD1 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4_
+ 0 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8_
+ RNIKJD1 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4_
+ 0 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8
+ _RNI8FB7 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4
+ _0 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8
+ _RNIJDJ1 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4
+ _0 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8
+ _RNIQOG3 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4
+ _0 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8
+ _RNIC2M7 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4
+ _0 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8
+ _RNI5NO5 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4
+ _0 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8_
+ RNITJD1 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4_
+ 0 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8_
+ RNIUJD1 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4_
+ 0 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/FF_8
+ _RNI14E5 was optimized away.
+Block THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/LUT4
+ _0 was optimized away.
+
+ Page 363
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_ADC1_HANDLER/recstore_RNIQV01_3 was optimized away.
+Block THE_ADC1_CROSSOVER/THE_CROSSOVER/INV_0 was optimized away.
+Block THE_ADC1_CROSSOVER/THE_CROSSOVER/INV_1 was optimized away.
+Block THE_ADC1_CROSSOVER/THE_CROSSOVER/OR2_t10 was optimized away.
+Block THE_ADC1_CROSSOVER/THE_CROSSOVER/LUT4_12 was optimized away.
+Block THE_ADC0_HANDLER/recstore_RNIPV01_3 was optimized away.
+Block THE_ADC0_CROSSOVER/THE_CROSSOVER/OR2_t10 was optimized away.
+Block THE_ADC0_CROSSOVER/THE_CROSSOVER/INV_0 was optimized away.
+Block THE_ADC0_CROSSOVER/THE_CROSSOVER/INV_1 was optimized away.
+Block THE_ADC0_CROSSOVER/THE_CROSSOVER/LUT4_12 was optimized away.
+Block THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/LUT4_0 was optimized away.
+Block THE_RICH_TRB/THE_MEDIA_INTERFACE/reset_i_RNIOH17 was optimized away.
+Block THE_RICH_TRB/THE_MEDIA_INTERFACE/tx_k_RNO_0 was optimized away.
+Block THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/OR2_t20
+ was optimized away.
+Block THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/AND2_t2
+ 1 was optimized away.
+Block THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/INV_1
+ was optimized away.
+Block THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/AND2_t2
+ 1_RNO was optimized away.
+Block THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/OR2_t20
+ was optimized away.
+Block THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/INV_0
+ was optimized away.
+Block THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/INV_1
+ was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE
+ _IBUF/THE_FIFO/fifo/INV_5 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE
+ _IBUF/THE_FIFO/fifo/INV_6 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE
+ _IBUF/THE_FIFO/fifo/INV_7 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE
+ _IBUF/THE_FIFO/fifo/INV_8 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE
+ _IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/combined_COMB_DATAREADY_IN
+ _RNILRLC was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE
+ _IBUF/THE_FIFO/fifo/INV_5 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE
+ _IBUF/THE_FIFO/fifo/INV_6 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE
+ _IBUF/THE_FIFO/fifo/INV_7 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE
+ _IBUF/THE_FIFO/fifo/INV_8 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE
+ _IBUF/THE_FIFO/fifo/INV_5 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE
+ _IBUF/THE_FIFO/fifo/INV_6 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE
+ _IBUF/THE_FIFO/fifo/INV_7 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE
+ _IBUF/THE_FIFO/fifo/INV_8 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/INV_5 was optimized away.
+
+ Page 364
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Removed logic (cont)
+--------------------
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/INV_6 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/INV_7 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/INV_8 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/INV_5 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/INV_6 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/INV_7 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/INV_8 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/INV_5 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/INV_6 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/INV_7 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/INV_8 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/INV_5 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/INV_6 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/INV_7 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIV
+ E_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/INV_8 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ip
+ udata_apl/buf_START_READOUT_RNI0885 was optimized away.
+Block THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/CO
+ MMON_REGISTERS_OUT_write_enable_RNIM924_0 was optimized away.
+Block THE_SLAVE_BUS/THE_BUS_HANDLER/buf_BUS_DATA_OUT_RNIOL3_3 was optimized
+ away.
+Block THE_SLAVE_BUS/THE_PED_MEM/CURRENT_STATE_RNIP373_5 was optimized away.
+Block THE_SLAVE_BUS/THE_THR_MEM/CURRENT_STATE_RNI65P5_5 was optimized away.
+Block THE_SLAVE_BUS/THE_SLV_REGISTER_BANK/CURRENT_STATE_RNIIDO2_5 was optimized
+ away.
+Block THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/wait_pulse_RNIGAD2 was
+ optimized away.
+Block THE_RICH_TRB/THE_MEDIA_INTERFACE/tx_correct_RNO_1 was optimized away.
+
+Memory Usage
+------------
+
+ INFO: Design contains EBR with ASYNC Reset Mode that has a limitation:
+ The use of the EBR block asynchronous reset requires that certain timing
+ be met between the clock and the reset within the memory block.
+ See the device specific data sheet for additional details.
+
+
+
+
+
+ Page 365
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+
+
+
+/THE_ADC0_CROSSOVER/THE_CROSSOVER:
+ EBRs: 0
+ RAM SLICEs: 48
+ Logic SLICEs: 47
+ PFU Registers: 153
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_10:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_11:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_12:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_13:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_14:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_15:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_16:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_17:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+
+ Page 366
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_18:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_19:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_20:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_21:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_22:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_23:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_3:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_5:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_6:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_7:
+
+ Page 367
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_8:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_9:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER:
+ EBRs: 0
+ RAM SLICEs: 48
+ Logic SLICEs: 47
+ PFU Registers: 153
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_10:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_11:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_12:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_13:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_14:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_15:
+ EBRs: 0
+
+ Page 368
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_16:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_17:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_18:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_19:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_20:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_21:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_22:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_23:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_3:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4:
+ EBRs: 0
+ RAM SLICEs: 1
+
+ Page 369
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_5:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_6:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_7:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_8:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_ADC1_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_9:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER:
+ EBRs: 0
+ RAM SLICEs: 20
+ Logic SLICEs: 1
+ PFU Registers: 40
+/THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_3:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_4:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+
+ Page 370
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ PFU Registers: 0
+/THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_5:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_6:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_7:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_8:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_9:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO:
+ EBRs: 3
+ RAM SLICEs: 0
+ Logic SLICEs: 42
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 47
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO:
+ EBRs: 3
+ RAM SLICEs: 0
+ Logic SLICEs: 42
+
+ Page 371
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 47
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO:
+ EBRs: 3
+ RAM SLICEs: 0
+ Logic SLICEs: 42
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 47
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO:
+ EBRs: 3
+ RAM SLICEs: 0
+ Logic SLICEs: 41
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+
+ Page 372
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 49
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO:
+ EBRs: 3
+ RAM SLICEs: 0
+ Logic SLICEs: 41
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 47
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO:
+ EBRs: 3
+ RAM SLICEs: 0
+ Logic SLICEs: 41
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+
+ Page 373
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 47
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO:
+ EBRs: 3
+ RAM SLICEs: 0
+ Logic SLICEs: 43
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 47
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO:
+ EBRs: 3
+ RAM SLICEs: 0
+ Logic SLICEs: 42
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+
+ Page 374
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 47
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO:
+ EBRs: 3
+ RAM SLICEs: 0
+ Logic SLICEs: 42
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 48
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO:
+ EBRs: 3
+ RAM SLICEs: 0
+ Logic SLICEs: 42
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+
+ Page 375
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ Logic SLICEs: 47
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO:
+ EBRs: 3
+ RAM SLICEs: 0
+ Logic SLICEs: 41
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 47
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO:
+ EBRs: 3
+ RAM SLICEs: 0
+ Logic SLICEs: 42
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 47
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+
+ Page 376
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO:
+ EBRs: 3
+ RAM SLICEs: 0
+ Logic SLICEs: 42
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 47
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO:
+ EBRs: 3
+ RAM SLICEs: 0
+ Logic SLICEs: 41
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 47
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO:
+ EBRs: 3
+
+ Page 377
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ RAM SLICEs: 0
+ Logic SLICEs: 42
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 49
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO:
+ EBRs: 3
+ RAM SLICEs: 0
+ Logic SLICEs: 41
+ PFU Registers: 38
+ -Contains EBR pdp_ram_0_0_2: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_1_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+ -Contains EBR pdp_ram_0_2_0: TYPE= DP16KB, Width_B= 4, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_2kx27.lpc
+/THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 47
+ PFU Registers: 34
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 14, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= fifo_1kx18.lpc
+/THE_PED_CORR_STAGE:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 194
+ PFU Registers: 254
+/THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/frame_int_CR0_ram:
+
+ Page 378
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_PED_CORR_STAGE/GEN_ALU_14_THE_ALU/frame_int_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_PED_CORR_STAGE/thr_addr_CR6_ram:
+ EBRs: 0
+ RAM SLICEs: 3
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_PED_CORR_STAGE/thr_addr_CR6_ram_0:
+ EBRs: 0
+ RAM SLICEs: 3
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 48
+ PFU Registers: 74
+/THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/RA
+ MW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+
+ Page 379
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 50
+ PFU Registers: 75
+/THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/RA
+ MW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+
+ Page 380
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 50
+ PFU Registers: 75
+/THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/RA
+ MW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+
+ Page 381
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+/THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 49
+ PFU Registers: 75
+/THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/RA
+ MW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+
+ Page 382
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 50
+ PFU Registers: 75
+/THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/RA
+ MW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+
+ Page 383
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 49
+ PFU Registers: 75
+/THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/RA
+ MW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+
+ Page 384
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 50
+ PFU Registers: 75
+/THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/RA
+ MW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+
+ Page 385
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 50
+ PFU Registers: 75
+/THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/RA
+ MW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+
+ Page 386
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 49
+ PFU Registers: 75
+/THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/R
+ AMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+
+ Page 387
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 49
+ PFU Registers: 75
+/THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/R
+ AMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER:
+
+ Page 388
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 51
+ PFU Registers: 76
+/THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/R
+ AMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER:
+ EBRs: 0
+ RAM SLICEs: 1
+
+ Page 389
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ Logic SLICEs: 50
+ PFU Registers: 76
+/THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/R
+ AMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 49
+ PFU Registers: 75
+
+ Page 390
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+/THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/R
+ AMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 50
+ PFU Registers: 76
+/THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+
+ Page 391
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/R
+ AMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 48
+ PFU Registers: 74
+/THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+
+ Page 392
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/RA
+ MW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 49
+ PFU Registers: 75
+/THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/delay_store_CR0_ram:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_LOCKER/delay_store_CR0_ram/RAMW:
+
+ Page 393
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM:
+ EBRs: 0
+ RAM SLICEs: 5
+ Logic SLICEs: 0
+ PFU Registers: 9
+/THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/RA
+ MW:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2:
+ EBRs: 0
+ RAM SLICEs: 1
+ Logic SLICEs: 0
+ PFU Registers: 0
+/THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR input_bram_0_0_1: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+ -Contains EBR input_bram_0_1_0: TYPE= DP16KB, Width_B= 9, Depth_A= 2048,
+ Depth_B= 2048, REGMODE_A= OUTREG, REGMODE_B= OUTREG, RESETMODE=
+ SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= input_bram.lpc
+/THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 89
+ PFU Registers: 112
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 16, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= lattice_ecp2m_fifo_16bit_dualport.lpc
+/THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 88
+
+ Page 394
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ PFU Registers: 112
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 18, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= lattice_ecp2m_fifo_16bit_dualport.lpc
+/THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF
+ /THE_FIFO/fifo:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 39
+ PFU Registers: 33
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 18, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= lattice_ecp2m_fifo_18x1k.lpc
+/THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF
+ /THE_FIFO/fifo:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 40
+ PFU Registers: 33
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 18, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= lattice_ecp2m_fifo_18x1k.lpc
+/THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API
+ /GEN_FIFO_TO_APL_FIFO_TO_APL/fifo:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 40
+ PFU Registers: 32
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 18, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= lattice_ecp2m_fifo_18x1k.lpc
+/THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API
+ /GEN_FIFO_TO_INT_FIFO_TO_INT/fifo:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 40
+ PFU Registers: 33
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 16, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= lattice_ecp2m_fifo_18x1k.lpc
+/THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF
+ /THE_FIFO/fifo:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 39
+ PFU Registers: 33
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 18, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= lattice_ecp2m_fifo_18x1k.lpc
+/THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API
+
+ Page 395
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ /GEN_FIFO_TO_APL_FIFO_TO_APL/fifo:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 40
+ PFU Registers: 33
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 18, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= lattice_ecp2m_fifo_18x1k.lpc
+/THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API
+ /GEN_FIFO_TO_INT_FIFO_TO_INT/fifo:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 38
+ PFU Registers: 32
+ -Contains EBR pdp_ram_0_0_0: TYPE= DP16KB, Width_B= 16, Depth_A= 1024,
+ Depth_B= 1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
+ WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= DISABLED,
+ MEM_LPC_FILE= lattice_ecp2m_fifo_18x1k.lpc
+/THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_add
+ resses/THE_STAT_RAM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 18
+ PFU Registers: 0
+ -Contains EBR ram_1_ram_1_0_0: TYPE= DP16KB, Width_A= 16, Depth_A= 16,
+ Depth_B= 4, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= SYNC,
+ WRITEMODE_A= WRITETHROUGH, WRITEMODE_B= WRITETHROUGH, GSR= DISABLED
+/THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR adc_snoop_mem_0_0_0: TYPE= DP16KB, Width_B= 16, Depth_A=
+ 1024, Depth_B= 1024, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= adc_snoop_mem.lpc
+/THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR adc_snoop_mem_0_0_0: TYPE= DP16KB, Width_B= 16, Depth_A=
+ 1024, Depth_B= 1024, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= adc_snoop_mem.lpc
+/THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_SLV_ONEWIRE_DPRAM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR slv_onewire_dpram_0_0_0: TYPE= DP16KB, Width_A= 16,
+ Width_B= 16, Depth_A= 128, Depth_B= 64, REGMODE_A= NOREG,
+ REGMODE_B= NOREG, RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B=
+ NORMAL, GSR= DISABLED, MEM_LPC_FILE= slv_onewire_dpram.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_0_THE_PED_MEM:
+
+ Page 396
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_10_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_11_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_12_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_13_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_14_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_15_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+
+ Page 397
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_1_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_2_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_3_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_4_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_5_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_6_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+
+ Page 398
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_7_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_8_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_9_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 13,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM:
+ EBRs: 2
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR spi_dpram_32_to_8_0_0_1: TYPE= DP16KB, Width_A= 16,
+ Width_B= 4, Depth_A= 64, Depth_B= 256, REGMODE_A= NOREG, REGMODE_B=
+ NOREG, RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL,
+ GSR= DISABLED, MEM_LPC_FILE= spi_dpram_32_to_8.lpc
+ -Contains EBR spi_dpram_32_to_8_0_1_0: TYPE= DP16KB, Width_A= 16,
+ Width_B= 4, Depth_A= 64, Depth_B= 256, REGMODE_A= NOREG, REGMODE_B=
+ NOREG, RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL,
+ GSR= DISABLED, MEM_LPC_FILE= spi_dpram_32_to_8.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_0_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_10_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+
+ Page 399
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_11_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_12_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_13_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_14_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_15_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_1_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+
+ Page 400
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_2_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_3_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_4_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_5_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_6_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_7_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+
+ Page 401
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ (cont)
+-------
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_8_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+/THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_9_THE_PED_MEM:
+ EBRs: 1
+ RAM SLICEs: 0
+ Logic SLICEs: 0
+ PFU Registers: 0
+ -Contains EBR ped_thr_true_0_0_0: TYPE= DP16KB, Width_A= 18, Width_B= 12,
+ Depth_A= 128, Depth_B= 128, REGMODE_A= OUTREG, REGMODE_B= OUTREG,
+ RESETMODE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR=
+ DISABLED, MEM_LPC_FILE= ped_thr_true.lpc
+
+PLL/DLL Summary
+---------------
+
+PLL 1: Pin/Node Value
+ PLL Instance Name: THE_SYNC_PLL/PLLDInst_0
+ PLL Type: EPLLD
+ Input Clock: PIN EXT_IN_c_3
+ Output Clock(P): NODE cts_clk40m
+ Output Clock(S): NONE
+ Output Clock(K): NONE
+ PLL Feedback Signal: NODE THE_SYNC_PLL/CLKFB_t
+ PLL Reset Signal: NODE ctrl_pll_4
+ PLL K Divider Reset Signal: NODE GND
+ PLL LOCK Signal: PIN,NODE BP_LED_c
+ Dynamic Phase Adjust Mode Signal: NONE
+ Dynamic Phase Adjust Input 0: NONE
+ Dynamic Phase Adjust Input 1: NONE
+ Dynamic Phase Adjust Input 2: NONE
+ Dynamic Phase Adjust Input 3: NONE
+ Dynamic Duty Adjust Input 0: NONE
+ Dynamic Duty Adjust Input 1: NONE
+ Dynamic Duty Adjust Input 2: NONE
+ Dynamic Duty Adjust Input 3: NONE
+ Input Clock Frequency (MHz): 40.0000
+ Output Clock(P) Frequency (MHz): 40.0000
+ Output Clock(K) Frequency (MHz): NA
+ Output Clock(P) Actual Frequency: 40.0000
+ CLKOP BYPASS: DISABLED
+ CLKOS BYPASS: DISABLED
+ CLKOK BYPASS: DISABLED
+ CLKI Divider: 1
+ CLKFB Divider: 1
+ CLKOP Divider: 32
+ CLKOK Divider: 2
+ PLL Delay Factor (*130ps): NONE
+
+ Page 402
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+PLL/DLL Summary (cont)
+----------------------
+ CLKOS Phase Shift (degree): 0.0
+ CLKOS Duty Cycle (*1/16): 8
+ Phase Control: STATIC
+ FB_MODE: NONE
+PLL 2: Pin/Node Value
+ PLL Instance Name: THE_40M_PLL/PLLDInst_0
+ PLL Type: EPLLD
+ Input Clock: PIN CLK100M_c
+ Output Clock(P): NODE clk_apv_c
+ Output Clock(S): NODE clk_adc
+ Output Clock(K): NONE
+ PLL Feedback Signal: NODE clk_apv_c
+ PLL Reset Signal: NODE ctrl_pll_7
+ PLL K Divider Reset Signal: NODE GND
+ PLL LOCK Signal: NODE clk40m_locked
+ Dynamic Phase Adjust Mode Signal: NODE VCC
+ Dynamic Phase Adjust Input 0: NODE ctrl_pll_0
+ Dynamic Phase Adjust Input 1: NODE ctrl_pll_1
+ Dynamic Phase Adjust Input 2: NODE ctrl_pll_2
+ Dynamic Phase Adjust Input 3: NODE ctrl_pll_3
+ Dynamic Duty Adjust Input 0: NODE ctrl_pll_0
+ Dynamic Duty Adjust Input 1: NODE ctrl_pll_1
+ Dynamic Duty Adjust Input 2: NODE ctrl_pll_2
+ Dynamic Duty Adjust Input 3: NODE THE_40M_PLL/DPHASE3_inv
+ Input Clock Frequency (MHz): 100.0000
+ Output Clock(P) Frequency (MHz): 40.0000
+ Output Clock(K) Frequency (MHz): NA
+ Output Clock(P) Actual Frequency: 40.0000
+ CLKOP BYPASS: DISABLED
+ CLKOS BYPASS: DISABLED
+ CLKOK BYPASS: DISABLED
+ CLKI Divider: 5
+ CLKFB Divider: 2
+ CLKOP Divider: 32
+ CLKOK Divider: 2
+ PLL Delay Factor (*130ps): NONE
+ CLKOS Phase Shift (degree): 0.0
+ CLKOS Duty Cycle (*1/16): 8
+ Phase Control: DYNAMIC
+ FB_MODE: NONE
+DLL 1: Pin/Node Value
+ DLL Instance Name: THE_100M_DLL/dll_100m_0_0
+ DLL Type: CIDDLLA
+ Input Clock: PIN CLK100M_c
+ Output Clock(P): NODE sysclk_c
+ Output Clock(S): NONE
+ DLL Feedback Input Signal: NODE sysclk_c
+ DLL Reset Signal: NONE
+ DLL_LOCK Signal: NODE clk100m_locked
+ ALUHOLD: NONE
+ Input Clock Frequency (MHz): 100.0000
+ Output Clock(P) Frequency (MHz): 100.0000
+ Output Clock(S) Frequency (MHz): NA
+ CLKOP Duty50: DISABLED
+ CLKOS Duty50: DISABLED
+ CLKOP Phase: 270
+
+ Page 403
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+PLL/DLL Summary (cont)
+----------------------
+ CLKOS Phase: 270
+ CLKOS Fine Phase: 0
+ CLKI Divider: 1
+ CLKOS Divider: 1
+ GSR: DISABLED
+ CLKOS Fine Delay Adjustment: DISABLED
+ CLKOS Fine Delay Adjustment Value: 0
+ CLKOS Fine Phase Adjustment Value: NONE
+ ALU Lock Count: 3
+ ALU Unlock Count: 3
+ ALU Initial Count: 0
+ Adjust Delay Control: NONE
+ Glitch Tolerance: 2
+ SMI_OFFSET: 0x410
+
+ASIC Components
+---------------
+
+Instance Name: THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_SLV_ONEWIRE_DPRAM/slv_onewir
+ e_dpram_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_ADC1_SNOOPER/THE_ADC0_SNOOP_MEM/adc_snoop_mem_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_ADC0_SNOOPER/THE_ADC0_SNOOP_MEM/adc_snoop_mem_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_13_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_9_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_15_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_14_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_4_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_8_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_12_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_7_THE_PED_MEM/ped_thr_true_0_0_0
+
+ Page 404
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ASIC Components (cont)
+----------------------
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_11_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_5_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_6_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_10_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_1_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_0_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_2_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_THR_MEM/GEN_PED_MEM_3_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_13_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_9_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_15_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_14_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_4_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_8_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_12_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_7_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_11_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_5_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+
+ Page 405
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ASIC Components (cont)
+----------------------
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_6_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_10_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_1_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_0_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_2_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_SLAVE_BUS/THE_PED_MEM/GEN_PED_MEM_3_THE_PED_MEM/ped_thr_true_0_0_0
+ Type: DP16KB
+Instance Name: THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio
+ _regIO/the_addresses/THE_STAT_RAM/ram_1_ram_1_0_0
+ Type: DP16KB
+Instance Name: THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_D
+ AT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_D
+ AT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_D
+ AT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_D
+ AT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN
+ _IBUF_THE_IBUF/THE_FIFO/fifo/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN
+ _IBUF_THE_IBUF/THE_FIFO/fifo/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN
+ _IBUF_THE_IBUF/THE_FIFO/fifo/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRA
+ M/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRA
+ M/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name:
+ THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/PCSC_INST
+ Type: PCSC
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/i
+ nput_bram_0_0_1
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/i
+ nput_bram_0_1_0
+ Type: DP16KB
+
+ Page 406
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ASIC Components (cont)
+----------------------
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_0_1
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_1_0
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_0_1
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_1_0
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/i
+ nput_bram_0_0_1
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/i
+ nput_bram_0_1_0
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/i
+ nput_bram_0_0_1
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/i
+ nput_bram_0_1_0
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/i
+ nput_bram_0_0_1
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/i
+ nput_bram_0_1_0
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/i
+ nput_bram_0_0_1
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/i
+ nput_bram_0_1_0
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/i
+ nput_bram_0_0_1
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/i
+ nput_bram_0_1_0
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_0_1
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_1_0
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_0_1
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_1_0
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_0_1
+
+ Page 407
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ASIC Components (cont)
+----------------------
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_1_0
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_0_1
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_1_0
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_0_1
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_1_0
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_0_1
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_1_0
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_0_1
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_1_0
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_0_1
+ Type: DP16KB
+Instance Name: THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/in
+ put_bram_0_1_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+
+ Page 408
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ASIC Components (cont)
+----------------------
+Instance Name: THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+
+ Page 409
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+ASIC Components (cont)
+----------------------
+Instance Name: THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2
+ Type: DP16KB
+Instance Name: THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1
+ Type: DP16KB
+Instance Name: THE_SYNC_PLL/PLLDInst_0
+ Type: EPLLD
+Instance Name: THE_100M_DLL/dll_100m_0_0
+ Type: CIDDLLA
+Instance Name: THE_40M_PLL/PLLDInst_0
+ Type: EPLLD
+
+ Page 410
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+
+PGROUP Utilization
+------------------
+
+PGROUP "THE_SLAVE_BUS/THE_SPI_MASTER/SPI_group":
+ Logic contained: 198 SLICEs, 50 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/RICH_TRB_group":
+ Logic contained: 335 SLICEs, 84 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/
+ the_addresses/HUBLOGIC_group":
+ Logic contained: 71 SLICEs, 18 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/
+ RegIO_group":
+ Logic contained: 463 SLICEs, 116 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASS
+ IVE_API/API_group":
+ Logic contained: 271 SLICEs, 68 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASS
+ IVE_API/API_group":
+ Logic contained: 271 SLICEs, 68 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOB
+ UF1_REPLYOBUF/OBUF_group":
+ Logic contained: 131 SLICEs, 33 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_T
+ HE_IBUF/IBUF_group":
+ Logic contained: 140 SLICEs, 35 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOB
+ UF1_REPLYOBUF/OBUF_group":
+ Logic contained: 135 SLICEs, 34 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_T
+ HE_IBUF/IBUF_group":
+ Logic contained: 142 SLICEs, 36 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOB
+ UF1_REPLYOBUF/OBUF_group":
+ Logic contained: 110 SLICEs, 28 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_T
+ HE_IBUF/IBUF_group":
+ Logic contained: 124 SLICEs, 31 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_MEDIA_INTERFACE/media_interface_group":
+ Logic contained: 349 SLICEs, 88 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_APV_TRGCTRL/APV_TRG_CTRL_group":
+ Logic contained: 326 SLICEs, 82 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 58 SLICEs, 15 PFUs
+
+ Page 411
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+PGROUP Utilization (cont)
+-------------------------
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 58 SLICEs, 15 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 58 SLICEs, 15 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 59 SLICEs, 15 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 58 SLICEs, 15 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 59 SLICEs, 15 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 59 SLICEs, 15 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 58 SLICEs, 15 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 58 SLICEs, 15 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 59 SLICEs, 15 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 59 SLICEs, 15 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 58 SLICEs, 15 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 59 SLICEs, 15 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 58 SLICEs, 15 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 58 SLICEs, 15 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/APV_RAW_BUF_group":
+ Logic contained: 59 SLICEs, 15 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_IPU_STAGE/IPU_FIFO_STAGE_group":
+ Logic contained: 2374 SLICEs, 594 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group":
+ Logic contained: 45 SLICEs, 12 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group":
+ Logic contained: 38 SLICEs, 10 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group":
+
+ Page 412
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+PGROUP Utilization (cont)
+-------------------------
+ Logic contained: 36 SLICEs, 9 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group":
+ Logic contained: 37 SLICEs, 10 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_ADC0_HANDLER/ADC_DATA_HANDLER_group":
+ Logic contained: 77 SLICEs, 20 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group":
+ Logic contained: 45 SLICEs, 12 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group":
+ Logic contained: 38 SLICEs, 10 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group":
+ Logic contained: 36 SLICEs, 9 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group":
+ Logic contained: 37 SLICEs, 10 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_ADC1_HANDLER/ADC_DATA_HANDLER_group":
+ Logic contained: 77 SLICEs, 20 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_group":
+ Logic contained: 146 SLICEs, 37 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBU
+ F2_gen_INITOBUF3_INITOBUF/OBUF_group":
+ Logic contained: 20 SLICEs, 5 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBU
+ F2_gen_INITOBUF3_INITOBUF/OBUF_group":
+ Logic contained: 21 SLICEs, 6 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/TRMBUF
+ _group":
+ Logic contained: 31 SLICEs, 8 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBU
+ F2_gen_INITOBUF3_INITOBUF/OBUF_group":
+ Logic contained: 20 SLICEs, 5 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_SLAVE_BUS/THE_BUS_HANDLER/Bus_handler_group":
+ Logic contained: 301 SLICEs, 76 PFUs
+ Bounded Area: (Unbounded)
+PGROUP "THE_SLAVE_BUS/THE_SPI_MEMORY/SPI_group":
+ Logic contained: 8 SLICEs, 2 PFUs
+ Bounded Area: (Unbounded)
+
+Recommendations for Optimization
+--------------------------------
+
+ We recommend the Datasheet and several Technical Notes to help you best
+ optimize your design performance and speed the design process to completion:
+ http://www.latticesemi.com/designresourcesforecp2m
+
+
+ Page 413
+
+
+
+
+Design: adcmv3 Date: 06/14/10 22:12:44
+
+Run Time and Memory Usage
+-------------------------
+
+ Total CPU Time: 17 mins 34 secs
+ Total REAL Time: 17 mins 37 secs
+ Peak Memory Usage: 401 MB
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+ Page 414
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995
+ AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent
+ Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems
+ All rights reserved.
+Copyright (c) 2002-2009 Lattice Semiconductor
+ Corporation, All rights reserved.
--- /dev/null
+SCHEMATIC START ;
+# map: version ispLever_v8.0_PROD_Build (41) -- WARNING: Map write only section -- Mon Jun 14 22:30:13 2010
+
+SYSCONFIG PERSISTENT=OFF CONFIG_MODE=SPI DONE_OD=OFF DONE_EX=OFF MCCLK_FREQ=34 CONFIG_SECURE=OFF WAKE_UP=21 COMPRESS_CONFIG=OFF INBUF=OFF ENABLE_NDR=OFF ;
+PGROUP "THE_SLAVE_BUS/THE_SPI_MASTER/SPI_group"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_31"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_32"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_33"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_34"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_35"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_36"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_37"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_38"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10062"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10063"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10064"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10065"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10066"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10067"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10068"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10069"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10070"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10071"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10072"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10073"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10074"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10075"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10076"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10077"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10078"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10079"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10080"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10081"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10082"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10083"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10084"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10085"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10086"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10087"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10088"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10089"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10090"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10091"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10092"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10093"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10094"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10095"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10096"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10097"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10098"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10099"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10100"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10101"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10102"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10103"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10104"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10105"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10106"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10107"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10108"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10109"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10110"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10111"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10112"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10113"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10114"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10115"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10116"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10117"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10118"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10119"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10120"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10121"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10122"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10123"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10124"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10125"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10126"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10127"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10128"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10129"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10130"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10131"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10132"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10133"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10134"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10135"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10136"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10137"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10138"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10139"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10140"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10141"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10142"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10143"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10144"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10145"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10194"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10204"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10255"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10256"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10257"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10258"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10259"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10260"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10261"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10262"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10263"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10264"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10265"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10266"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10267"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10268"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10269"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10270"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10465"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10466"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10467"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10468"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10469"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10470"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10471"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10472"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10473"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10785"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/STATE_ns_i_i_a2_32_15_m6_i_3/SLICE_11417"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11872"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11873"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11874"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11875"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11876"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11877"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11878"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11879"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11880"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11881"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12004"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12005"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12006"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12007"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12008"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12009"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12010"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12011"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12012"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12013"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_12014"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12330"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12394"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12525"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12532"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12533"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12546"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12547"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12566"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12567"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12568"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12569"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12570"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12571"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12572"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12573"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12574"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12625"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12626"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12627"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12628"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12629"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_12630"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_12631"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12766"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12803"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12804"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12839"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12840"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12841"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12881"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12882"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12906"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_12946"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13001"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13002"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13003"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13004"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13005"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13006"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13007"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13008"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13009"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13010"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13011"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13012"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13013"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13014"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13015"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13016"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13017"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13018"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13019"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13020"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_13021"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_13022"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_13023";
+PGROUP "THE_RICH_TRB/RICH_TRB_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_49"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_50"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_51"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_52"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_53"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_54"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_55"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_56"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_57"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_58"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_59"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_60"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_61"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_62"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_63"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_64"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_65"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_66"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_67"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_139"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_140"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_141"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_142"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_143"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_144"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_145"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_146"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_147"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_148"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_149"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_150"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_151"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_152"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_153"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_154"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_155"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_156"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_157"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_158"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_159"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_160"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_161"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_162"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_163"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_495"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_496"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_497"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_498"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_499"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_500"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_501"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_502"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_503"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_504"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_505"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_506"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_507"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_508"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_8227"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_8228"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8358"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8359"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8360"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8361"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8362"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8363"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8364"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8365"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8366"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8367"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8368"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8369"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8370"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8371"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8372"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8373"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8391"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8392"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8393"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8394"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8395"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8396"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8397"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8398"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8417"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8418"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8422"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8423"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8428"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8429"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8443"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8444"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8601"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8602"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8603"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_8604"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8605"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8606"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8607"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8608"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8609"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8610"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8611"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8612"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8613"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8838"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8839"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8840"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8841"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8842"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8843"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8844"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8845"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8846"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8847"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8848"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8849"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8850"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8851"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8852"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8853"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8854"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8855"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8856"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8857"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8858"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8859"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8860"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8861"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8862"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8863"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8864"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8865"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8866"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8867"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8868"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8869"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8870"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8871"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8872"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8873"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8874"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8875"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8876"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9108"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9109"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9110"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9111"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9112"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9113"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9114"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9115"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9116"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9117"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9118"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9119"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_9262"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_9263"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_9267"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_9268"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9273"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9274"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9275"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9276"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9277"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9278"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_9279"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_9280"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_9314"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11059"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11060"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11061"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11062"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11063"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11064"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11065"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11066"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11068"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11078"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11079"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11080"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11081"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11082"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11083"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11084"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11086"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11087"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11088"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11089"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11090"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11091"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11092"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11093"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11094"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11096"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11097"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_11230"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/next_state_3_0__m48/SLICE_11622"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/next_state_3_0__m56/SLICE_11623"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/next_state_3_0__m37/SLICE_11624"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/next_state_3_0__m21/SLICE_11625"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/reset_timecounter_2/SLICE_11626"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12034"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12035"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12036"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12037"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12038"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12039"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12040"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12077"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12078"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12079"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12080"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12081"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12082"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12083"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12084"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12085"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12086"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12087"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12088"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12089"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12090"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12091"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12092"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12093"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12094"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12095"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12096"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_12097"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_12370"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12534"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12558"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12586"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12590"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12637"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12638"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12639"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12640"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12641"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12662"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12663"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_12664"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12777"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12785"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12786"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12811"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12816"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12817"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12848"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12849"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12899"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12902"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12913"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12916"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12917"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12920"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12943"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12947"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_12948"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_12949"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13116"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13117"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13118"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13119"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13120"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13121"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13122"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13123"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13124"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13125"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13126"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13207"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13208"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13209"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13210"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13211"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13212"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13213"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13214"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13215"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13216"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13217"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13218"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13219"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13220"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13221"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13222"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13223"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13224"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13225"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13226"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13227"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13228"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13229"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13230"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13231"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13232"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13233"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13234"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13235"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13236"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_13237"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_13238"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_13239"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13331"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13332"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13333"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13334"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13335"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13336"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13337"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13338"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13339"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13340"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13341"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13342"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13343"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13344"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13345"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13346"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13347"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13348"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13349"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13350"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13351"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13352"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13353"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13354"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13355"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13356"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13357"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13358"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13359"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13360";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/HUBLOGIC_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_68"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_69"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_70"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_71"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_72"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8226"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8350"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8351"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8352"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8353"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8354"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8355"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8356"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8357"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9120"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9121"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9124"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9211"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9239"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9240"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9241"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9242"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9243"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9244"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9245"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9246"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9247"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9248"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9249"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9250"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9251"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9252"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9253"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9254"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12041"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12042"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12043"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_12044"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12365"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12642"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12643"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12644"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12645"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12778"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12812"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12844"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12903"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13127"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13128"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13129"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13130"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13131"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13132"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13133"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13134"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13135"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13136"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13137"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13138"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13139"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13140"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13141"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13142"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13143"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_13144"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_13145"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_13146"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_13147"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_13148"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_13149"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/ram_1_ram_1_0_0";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/RegIO_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_73"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_74"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_75"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_76"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_77"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_78"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_79"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_80"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_81"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_82"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_83"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_84"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_85"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_86"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_87"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_88"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_89"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_90"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_91"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_92"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_93"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_94"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_95"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_96"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_97"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_98"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_99"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_100"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_101"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_102"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_103"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_104"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_105"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_106"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_107"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_108"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_109"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_110"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_111"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_112"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_113"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_114"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_115"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_116"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_117"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_118"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_119"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_120"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_121"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_122"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_123"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_124"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_125"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_126"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_127"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_128"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_129"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_130"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_131"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_132"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_133"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_134"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_135"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_136"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_137"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_138"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8388"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8415"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8416"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8419"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8420"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8421"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8430"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8481"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9122"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9123"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9125"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9126"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9127"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9128"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9129"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9130"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9131"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9132"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9133"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9134"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9135"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9136"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9137"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9138"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9139"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9140"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9141"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9142"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9143"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9144"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9145"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9146"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9147"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9148"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9149"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9150"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9151"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9152"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9153"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9154"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9155"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9156"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9157"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9158"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9159"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9160"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9161"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9162"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9163"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9164"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9165"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9166"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9167"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9168"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9169"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9170"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9171"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9172"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9173"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9174"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9175"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9176"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9177"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9178"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9179"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9180"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9181"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9182"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9183"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9184"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9185"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9186"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9187"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9188"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9189"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9190"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9191"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9192"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9193"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9194"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9195"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9196"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9197"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9198"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9199"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9200"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9201"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9202"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9203"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9204"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9205"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9206"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9207"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9208"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9209"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9210"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9212"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9213"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9214"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9215"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/board_rom/SLICE_9216"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/board_rom/SLICE_9217"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/board_rom/SLICE_9218"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/board_rom/SLICE_9219"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/board_rom/SLICE_9220"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9221"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9222"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9223"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9224"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9225"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9226"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9227"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9228"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9229"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9230"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9231"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9232"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9233"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9234"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9235"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9236"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9237"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9238"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9255"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9256"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9257"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9258"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9259"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9260"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9261"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9272"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9315"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10730"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10731"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10732"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10733"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10734"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10735"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10736"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10737"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10738"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10739"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10740"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10741"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10742"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10743"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11151"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11153"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11185"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11186"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11187"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11188"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11189"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11190"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11191"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11192"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11193"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11194"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11195"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11196"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11197"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11198"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11199"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11200"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11202"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11205"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_10/SLICE_11627"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_8/SLICE_11628"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_5/SLICE_11629"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_12/SLICE_11630"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_9/SLICE_11631"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_1/SLICE_11632"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_14/SLICE_11633"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_15/SLICE_11634"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_13/SLICE_11635"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_2/SLICE_11636"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_11/SLICE_11637"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_6/SLICE_11638"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_7/SLICE_11639"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_3/SLICE_11640"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_0/SLICE_11641"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_4/SLICE_11642"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_10/SLICE_11643"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_10/SLICE_11644"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_5/SLICE_11645"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_8/SLICE_11646"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_8/SLICE_11647"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_9/SLICE_11648"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_12/SLICE_11649"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_12/SLICE_11650"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_15/SLICE_11651"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_14/SLICE_11652"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_4/SLICE_11653"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_15/SLICE_11654"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_13/SLICE_11655"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_14/SLICE_11656"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_13/SLICE_11657"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_11/SLICE_11658"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_11/SLICE_11659"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_6/SLICE_11660"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_7/SLICE_11661"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_10/SLICE_11662"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_10/SLICE_11663"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_5/SLICE_11664"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_1/SLICE_11665"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_5/SLICE_11666"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_5/SLICE_11667"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_8/SLICE_11668"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_9/SLICE_11669"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_9/SLICE_11670"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_11/SLICE_11671"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_7/SLICE_11672"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_7/SLICE_11673"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_0/SLICE_11674"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_4/SLICE_11675"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_13/SLICE_11676"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_15/SLICE_11677"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_14/SLICE_11678"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_13/SLICE_11679"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_12/SLICE_11680"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_4/SLICE_11681"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_2/SLICE_11682"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_2/SLICE_11683"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_11/SLICE_11684"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_6/SLICE_11685"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_7/SLICE_11686"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_4/SLICE_11687"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_6/SLICE_11688"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_6/SLICE_11689"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_3/SLICE_11690"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_9/SLICE_11691"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_0/SLICE_11692"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_15_3/SLICE_11693"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_1/SLICE_11694"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_15_2/SLICE_11695"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_3/SLICE_11696"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_15_1/SLICE_11697"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_15_0/SLICE_11698"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_12/SLICE_11699"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_8/SLICE_11700"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_3/SLICE_11701"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_1/SLICE_11702"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_0/SLICE_11703"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_14/SLICE_11704"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_15/SLICE_11705"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_2/SLICE_11706"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_10/SLICE_11707"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_5/SLICE_11708"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_9/SLICE_11709"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_11/SLICE_11710"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_13/SLICE_11711"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_7/SLICE_11712"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_12/SLICE_11713"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_8/SLICE_11714"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_14/SLICE_11715"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_4/SLICE_11716"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_15/SLICE_11717"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_6/SLICE_11718"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11846"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11898"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11899"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11900"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11901"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11902"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11903"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12045"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12046"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12047"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12048"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12049"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/pattern_gen_inst/SLICE_12050"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12051"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12052"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12053"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12054"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12055"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12056"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12057"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12058"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12059"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12060"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12061"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12062"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12063"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12064"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12065"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12066"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12067"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12068"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12069"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12070"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12071"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12072"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12073"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12074"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12075"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12076"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12366"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12367"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12368"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12369"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12559"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12587"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12588"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12589"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12646"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12647"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12648"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12649"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12650"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12651"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12652"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12653"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12654"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12655"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12656"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12657"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12658"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12659"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12660"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12661"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12768"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12769"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12779"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12780"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12781"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12782"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12783"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12784"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12813"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12814"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12815"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12845"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12846"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12847"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12904"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12907"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12912"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12918"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12919"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13150"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13151"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13152"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13153"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13154"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13155"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13156"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13157"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13158"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13159"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13160"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13161"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13162"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13163"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13164"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13165"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13166"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13167"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13168"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13169"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13170"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13171"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13172"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13173"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13174"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13175"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13176"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13177"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13178"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13179"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13180"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13181"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13182"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13183"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13184"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13185"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13186"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13187"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13188"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13189"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13190"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13191"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13192"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13193"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13194"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13195"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13196"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13197"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13198"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13199"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13200"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13201"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13202"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13203"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13204"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13205"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13206";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/API_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_164"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_165"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_166"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_167"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_168"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_169"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_170"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_171"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_172"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_173"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_174"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_175"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_176"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_177"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_178"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_179"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_180"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_181"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_182"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_183"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_184"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_185"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_186"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_187"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_188"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_189"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_190"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_191"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_192"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_193"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_194"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_195"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_196"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_197"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_198"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_199"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_200"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_201"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_202"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_203"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_204"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_205"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_206"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_207"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_208"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_209"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_210"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_211"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_212"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_213"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_214"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_215"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_216"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_217"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_218"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_219"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_220"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_221"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_222"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_223"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_224"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_225"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_226"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_227"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_228"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_229"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_230"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_231"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_232"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_233"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_234"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_235"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_236"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_237"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_238"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_239"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_240"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_241"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_242"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_243"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8382"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8383"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8384"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8385"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8386"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8387"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8390"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8407"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8408"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8409"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8410"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8411"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8412"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8413"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8414"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8426"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8427"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_8434"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8435"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_8448"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8482"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8483"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8484"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8485"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_8996"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8997"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8998"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8999"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9000"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9001"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9002"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9003"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9004"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9005"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9006"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9007"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_9008"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_9009"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_9010"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_9011"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_9012"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_9013"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_9014"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_9015"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_9016"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_9017"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_9018"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9019"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_9020"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_9021"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9022"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9023"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9024"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_9025"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9026"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9027"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9028"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9029"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9030"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9031"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9032"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9033"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9034"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9035"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9036"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9037"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9038"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9039"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9040"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9041"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9042"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9043"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9044"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9045"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9046"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9047"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9048"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9049"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9050"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9051"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9052"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_9054"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9055"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9056"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9057"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9058"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9059"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9060"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9061"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9062"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9063"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9064"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9065"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9066"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9067"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9068"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9069"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9070"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9071"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9072"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9073"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9074"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9075"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9076"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9077"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9078"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9079"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9080"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9081"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9082"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9083"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9084"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9085"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9086"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9087"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9088"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9089"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9090"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9091"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9092"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9093"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9094"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9095"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9096"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9097"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9098"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9099"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9100"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9101"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9102"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9103"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9104"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9105"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9106"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9107"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_0/SLICE_11719"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_6/SLICE_11720"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_9/SLICE_11721"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_10/SLICE_11722"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_12/SLICE_11723"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_15/SLICE_11724"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_14/SLICE_11725"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_13/SLICE_11726"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_8/SLICE_11727"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_7/SLICE_11728"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_5/SLICE_11729"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_3/SLICE_11730"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_11/SLICE_11731"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/state_to_apl_ns_1_0__m16/SLICE_11732"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_11904"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_11905"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_11991"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12098"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12099"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12100"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12101"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12102"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12103"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12529"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12535"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12536"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12537"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12545"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12560"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12591"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12592"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12593"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12594"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12665"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12666"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12764"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_12787"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12788"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_12884"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_12921"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12950"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_13240"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_13241"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_13242"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13243"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13244"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13245"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13246"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13247"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13248"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13249"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13250"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13251"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_14072"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/pdp_ram_0_0_0"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/pdp_ram_0_0_0";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/API_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_244"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_245"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_246"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_247"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_248"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_249"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_250"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_251"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_252"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_253"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_254"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_255"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_256"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_257"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_258"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_259"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_260"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_261"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_262"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_263"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_264"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_265"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_266"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_267"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_268"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_269"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_270"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_271"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_272"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_273"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_274"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_275"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_276"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_277"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_278"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_279"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_280"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_281"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_282"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_283"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_284"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_285"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_286"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_287"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_288"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_289"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_290"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_291"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_292"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_293"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_294"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_295"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_296"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_297"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_298"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_299"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_300"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_301"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_302"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_303"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_304"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_305"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_306"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_307"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_308"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_309"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_310"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_311"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_312"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_313"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_314"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_315"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_316"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_317"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_318"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_319"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_320"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_321"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_322"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_323"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8374"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8375"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8376"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8377"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8378"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8379"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8380"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8381"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8389"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8399"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8400"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8401"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8402"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8403"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8404"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8405"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8406"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8424"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8425"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_8431"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_8432"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_8433"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8446"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8447"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_8727"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_8728"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8729"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8730"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8731"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8732"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8733"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8734"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8735"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8736"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8737"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8738"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8739"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8740"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8741"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8742"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8743"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8744"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8745"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8746"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8747"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8748"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8749"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8750"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8751"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8752"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8753"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8754"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8755"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_8756"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8757"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8758"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8759"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8760"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_8761"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8762"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8763"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8764"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8765"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8766"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8767"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8768"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8769"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8770"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8771"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8772"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8773"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8774"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8775"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8776"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8777"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8778"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8779"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8780"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8781"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8782"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8783"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8784"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8785"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8787"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8788"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8789"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8790"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8791"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8792"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8793"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8794"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8795"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8796"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8797"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8798"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8799"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8800"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8801"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8802"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8803"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8804"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8805"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8806"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8807"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8808"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8809"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8810"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8811"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8812"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8813"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8814"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8815"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8816"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8817"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8818"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8819"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8820"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8821"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8822"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8823"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8824"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8825"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8826"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8828"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8829"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8830"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8831"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8832"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8833"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8834"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8835"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8836"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8837"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_9313"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_7/SLICE_11733"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_9/SLICE_11734"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_10/SLICE_11735"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_11/SLICE_11736"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_14/SLICE_11737"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_15/SLICE_11738"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_5/SLICE_11739"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_0/SLICE_11740"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_6/SLICE_11741"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_13/SLICE_11742"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_3/SLICE_11743"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_8/SLICE_11744"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_12/SLICE_11745"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_11906"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_11992"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12104"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12105"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12106"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12107"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12108"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12109"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12110"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12371"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12538"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12539"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12540"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12595"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12596"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12667"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12668"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12669"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_12765"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12789"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_12790"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12818"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12819"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12820"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12944"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12951"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12952"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_13252"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_13253"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_13254"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_13255"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_13256"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13257"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13258"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13259"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13260"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13261"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13262"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13263"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13264"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13265"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_14073"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/pdp_ram_0_0_0"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/pdp_ram_0_0_0";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_324"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_325"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_326"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_327"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_328"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_329"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_330"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_331"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_332"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_333"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_334"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_335"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_336"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8239"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8303"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8304"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8305"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8306"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8307"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8308"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8321"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8322"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8486"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8487"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8950"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8951"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8952"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8953"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8954"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8955"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8956"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8957"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8958"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8959"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8960"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8961"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8962"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8963"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8964"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8965"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8966"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8967"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8968"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8969"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8970"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8971"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8972"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8973"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8974"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8975"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8976"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8977"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8978"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8979"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8980"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8981"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8982"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8983"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8984"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8985"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8986"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8987"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8988"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8989"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8991"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8992"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8993"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_9266"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_9271"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/un1_current_EOB_word_1_sqmuxa_1_0/SLICE_11746"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_6/SLICE_11747"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_14/SLICE_11748"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_15/SLICE_11749"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_3/SLICE_11750"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_7/SLICE_11751"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_13/SLICE_11752"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_12/SLICE_11753"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_11/SLICE_11754"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_10/SLICE_11755"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_9/SLICE_11756"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_8/SLICE_11757"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_5/SLICE_11758"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_4/SLICE_11759"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11907"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11908"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11909"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11910"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12111"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12112"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12113"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12114"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12115"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12116"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12117"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12118"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12119"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12120"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12121"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_12372"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_12373"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12526"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12597"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12598"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12670"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12671"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12672"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12673"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12850"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12851"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12852"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12853"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12894"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12914"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12922"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12953"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12954"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_13266"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_13267"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13268"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13269"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13270"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13271"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13272"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13273"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13274"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13275"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13276"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13277"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13278"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13279"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_14075";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_337"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_338"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_339"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_340"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_341"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_342"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_343"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_344"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_345"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_346"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_347"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_348"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_349"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_350"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_351"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_352"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_353"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_354"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_355"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_356"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_357"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_358"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_359"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_360"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_361"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_362"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_363"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_364"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_365"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_366"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_367"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_368"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_369"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_370"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_371"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_372"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_373"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_374"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_375"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_376"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_377"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_378"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_379"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_380"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8450"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8467"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8468"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8469"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8470"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8471"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8472"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8473"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8474"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8479"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8480"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8885"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8886"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8887"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8888"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8889"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8890"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8891"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8892"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8893"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8894"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8895"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8896"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8897"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8898"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8899"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8900"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8901"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8902"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8903"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8904"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8905"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8906"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8907"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8908"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8909"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8910"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8911"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8912"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8913"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_8915"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_8916"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8918"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8919"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8920"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8921"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8922"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8923"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8924"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8925"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8926"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8927"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8928"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8929"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8930"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8931"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8932"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8933"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8934"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8935"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8936"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8937"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8938"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8939"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8940"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8941"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8942"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8994"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8995"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_11911"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12124"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12125"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12126"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_12127"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12128"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12129"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12541"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12551"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12674"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12675"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12676"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12770"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_12791"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12792"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12821"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12822"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12854"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12871"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12885"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_13283"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_13284"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_13285"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_13286"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_13287"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_13288"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/pdp_ram_0_0_0";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_381"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_382"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_383"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_384"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_385"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_386"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_387"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_388"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_389"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_390"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_391"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_392"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_393"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8235"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8284"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8285"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8286"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8287"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8288"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8289"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8290"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8291"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8292"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8313"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8314"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8683"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8684"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8685"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8686"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8687"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8688"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8689"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8690"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8691"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8692"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8693"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8694"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8695"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8696"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8697"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8698"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8699"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8700"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8701"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8702"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8703"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8704"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8705"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8706"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8707"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8708"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8709"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8710"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8711"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8712"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8713"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8714"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8715"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8716"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8717"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8718"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8719"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8720"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8721"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8722"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8723"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8724"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8725"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8726"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_9265"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_9270"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/un1_current_EOB_word_1_sqmuxa_1_0/SLICE_11760"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_3/SLICE_11761"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_4/SLICE_11762"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_5/SLICE_11763"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_7/SLICE_11764"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_8/SLICE_11765"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_15/SLICE_11766"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_9/SLICE_11767"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_10/SLICE_11768"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_11/SLICE_11769"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_12/SLICE_11770"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_13/SLICE_11771"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_14/SLICE_11772"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_0/SLICE_11773"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_6/SLICE_11774"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11912"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11913"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11914"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11915"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11916"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12130"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12131"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12132"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12133"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12134"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12135"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12136"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12137"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12138"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12139"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12140"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_12374"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_12375"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12552"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12561"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12599"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12600"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12677"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12678"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12679"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12680"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12681"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12771"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12855"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12895"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12900"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12915"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12945"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12955"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_13289"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13290"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13291"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13292"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13293"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13294"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13295"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13296"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13297"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13298"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13299"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13300"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13301"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13302"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_14076";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_394"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_395"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_396"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_397"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_398"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_399"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_400"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_401"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_402"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_403"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_404"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_405"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_406"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_407"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_408"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_409"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_410"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_411"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_412"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_413"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_414"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_415"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_416"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_417"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_418"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_419"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_420"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_421"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_422"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_423"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_424"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_425"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_426"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_427"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_428"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_429"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_430"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_431"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_432"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_433"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_434"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_435"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_436"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_437"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8445"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8459"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8460"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8461"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8462"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8463"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8464"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8465"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8466"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8477"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8478"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8614"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_8615"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8616"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8617"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8618"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8619"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8620"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8621"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8622"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8623"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8624"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8625"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8626"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8627"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8628"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8629"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8630"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8631"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8632"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8633"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8634"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8635"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8636"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8637"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8638"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8639"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8640"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8641"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8642"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8643"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_8645"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_8646"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8648"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8649"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8650"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8651"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8652"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8653"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8654"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8655"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8656"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8657"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8658"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8659"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8660"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8661"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8662"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8663"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8664"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8665"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8666"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8667"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8668"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8669"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8670"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8671"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8672"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8673"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8674"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_11917"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12144"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12145"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12146"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_12147"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12148"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12149"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12542"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12553"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12682"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12683"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12684"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12772"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_12793"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12794"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12823"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12824"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12856"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12872"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12886"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_13306"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_13307"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_13308"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_13309"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_13310"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_13311"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_13312"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/pdp_ram_0_0_0";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_438"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_439"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_440"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_441"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_442"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_443"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_444"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_445"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_446"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_447"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_448"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_449"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_450"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8233"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8273"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8274"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8275"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8276"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8277"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8278"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8279"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8280"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8311"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8312"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8550"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8551"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8552"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8553"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8554"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8555"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8556"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8557"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8558"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8559"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8560"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8561"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8562"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8563"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8564"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8565"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8566"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8567"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8568"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8569"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8570"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8571"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8572"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8573"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8574"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8575"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8576"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8577"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8578"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8579"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8580"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8581"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8582"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8583"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8584"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8585"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8586"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8587"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8588"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8589"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8590"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8591"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8592"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_9264"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_9269"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_3_9/SLICE_11775"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_3_11/SLICE_11776"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_3_10/SLICE_11777"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_3_8/SLICE_11778"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_3_7/SLICE_11779"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_3_6/SLICE_11780"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_3_5/SLICE_11781"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_3_0/SLICE_11782"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11918"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11919"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11920"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12150"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12151"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12152"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12153"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12154"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12155"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12527"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12530"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12685"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12686"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12687"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12767"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12795"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12857"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12887"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12908"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_13313"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13314"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13315"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13316"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13317"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13318"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13319"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13320"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13321"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13322"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13323"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13324"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13325"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_14077";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_451"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_452"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_453"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_454"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_455"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_456"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_457"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_458"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_459"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_460"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_461"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_462"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_463"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_464"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_465"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_466"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_467"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_468"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_469"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_470"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_471"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_472"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_473"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_474"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_475"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_476"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_477"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_478"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_479"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_480"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_481"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_482"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_483"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_484"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_485"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_486"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_487"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_488"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_489"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_490"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_491"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_492"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_493"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_494"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8449"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8451"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8452"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8453"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8454"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8455"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8456"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8457"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8458"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8475"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8476"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8488"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8489"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8490"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8491"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8492"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8493"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8494"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8495"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8496"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8497"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8498"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8499"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8500"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8501"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8502"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8503"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8504"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8505"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8506"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8507"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_8509"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_8510"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8512"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8513"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8514"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8515"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8516"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8517"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8518"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8519"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8520"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8521"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8522"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8523"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8524"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8525"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8526"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8527"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8528"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8529"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8530"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8531"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8532"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8533"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8534"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8535"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8536"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8537"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8538"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8539"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8593"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8594"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8595"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8596"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8597"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8598"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8599"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8600"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_12159"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12160"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12554"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12796"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12825"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12873"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_12888"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12889"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_13329"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_13330"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/pdp_ram_0_0_0";
+PGROUP "THE_RICH_TRB/THE_MEDIA_INTERFACE/media_interface_group"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_509"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_510"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_511"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_512"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_513"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_514"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_515"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_516"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_517"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_518"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_519"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_520"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_521"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_522"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_523"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_524"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_525"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_526"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_527"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_528"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_529"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_530"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_531"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_532"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_533"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_534"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_535"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_536"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_537"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_538"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_539"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_540"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_541"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_542"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_543"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_544"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_545"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_546"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_547"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_548"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_549"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_550"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_551"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_552"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_553"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_554"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_555"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_556"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_557"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_558"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_559"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_560"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_561"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_562"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_563"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_564"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_565"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_566"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_567"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_568"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_569"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_570"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_571"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_572"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_573"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_574"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_575"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_576"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_577"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_578"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_579"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_580"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_581"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_582"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_583"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_584"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_585"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_586"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_587"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_588"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_589"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_590"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_591"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_592"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_593"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_594"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_595"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_4356"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_4486"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8050"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8051"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8052"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8053"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8054"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8055"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8056"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8057"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8058"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8059"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8060"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8061"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8062"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8063"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8064"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8065"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8066"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8067"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8068"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8069"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8070"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8071"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8072"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8073"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8074"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8075"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8076"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8077"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8078"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8079"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8080"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8081"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8082"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8083"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8084"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8085"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8086"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8087"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8088"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8089"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8090"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8091"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8092"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8093"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8094"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8095"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8096"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8097"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8098"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8099"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8100"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8101"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8102"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8103"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8104"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8105"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8106"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8107"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8108"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8109"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8110"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8111"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8112"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8113"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8114"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8115"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8116"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8117"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8118"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8119"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8120"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8121"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8122"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8123"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8124"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8125"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8126"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8127"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8128"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8129"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8130"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8131"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8132"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8133"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8134"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8135"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8136"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8137"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8138"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8139"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8140"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8141"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8142"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8143"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8144"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8145"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8146"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8147"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8148"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8149"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8150"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8151"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8152"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8154"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8155"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8156"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8157"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8158"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8159"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8160"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8161"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8162"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_K_DELAY/SLICE_8163"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8164"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8165"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8166"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8167"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8168"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8169"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8170"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8171"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8172"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_STATUS_SYNC/SLICE_8173"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_STATUS_SYNC/SLICE_8174"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8175"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8176"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8177"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8178"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8179"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8180"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8181"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8182"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8183"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8184"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8185"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8186"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8187"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8188"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8189"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8190"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8191"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8192"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8193"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8194"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8195"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8196"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8197"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8198"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8199"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8200"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8201"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8202"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_K_DELAY/SLICE_8203"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8204"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8205"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8206"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_ALLOW_SYNC/SLICE_8207"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8208"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8209"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8210"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8211"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8212"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8213"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8214"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8215"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8216"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8217"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8218"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8219"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8220"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8221"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8222"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8223"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8224"
+ COMP "SLICE_8225"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9295"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9296"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9297"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9298"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9299"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9300"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9301"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9302"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9303"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9304"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9305"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9306"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9307"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9308"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9309"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9310"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9311"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_9312"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_11206"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/link_status_led_4/SLICE_11783"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/link_status_led_u/SLICE_11784"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12161"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12162"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12163"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12164"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12165"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12166"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12167"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12168"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12169"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12170"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12171"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12172"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12173"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12174"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12175"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12176"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12177"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12178"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12179"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12180"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12181"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_12182"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12376"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_12531"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12562"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_12688"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_12689"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_12690"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12797"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12798"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12799"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12800"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12801"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12802"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12826"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12827"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12828"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12829"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12858"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12859"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12890"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12891"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12892"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12893"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12905"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12923"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12924"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_13361"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13362"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13363"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13364"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13365"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13366"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13367"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13368"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13369"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13370"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_13371"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_13372"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_13373"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_13374"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_13375"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/pdp_ram_0_0_0"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/pdp_ram_0_0_0";
+PGROUP "THE_APV_TRGCTRL/APV_TRG_CTRL_group"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_596"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_597"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_598"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_599"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_600"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_601"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_602"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_603"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_604"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_605"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_606"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_607"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_608"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_609"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_610"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_611"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_612"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_613"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_614"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_615"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_616"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_617"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_618"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_619"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_620"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_621"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_622"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_623"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_624"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_625"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_626"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_627"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_628"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_629"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_630"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_631"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_632"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_633"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_634"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_635"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_636"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_637"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_638"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_639"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_640"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_641"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_642"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_643"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_644"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_645"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_646"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_647"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_648"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_649"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_650"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_651"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_652"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_653"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_654"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_655"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_656"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_657"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_0/SLICE_3979"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3980"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3981"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_1/SLICE_3982"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3983"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3984"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_2/SLICE_3985"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3986"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3987"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_3/SLICE_3988"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3989"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3990"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_4/SLICE_3991"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3992"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3993"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_5/SLICE_3994"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3995"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3996"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_6/SLICE_3997"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3998"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3999"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_7/SLICE_4000"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_4001"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_4002"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_8/SLICE_4003"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_4004"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_4005"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_9/SLICE_4006"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_4007"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_4008"
+ COMP "THE_APV_TRGCTRL/SC_TRG0_STRECH/SLICE_4918"
+ COMP "THE_APV_TRGCTRL/SC_TRG0_STRECH/SLICE_4919"
+ COMP "THE_APV_TRGCTRL/SC_TRG0_STRECH/SLICE_4920"
+ COMP "THE_APV_TRGCTRL/SC_TRG1_STRECH/SLICE_4921"
+ COMP "THE_APV_TRGCTRL/SC_TRG1_STRECH/SLICE_4922"
+ COMP "THE_APV_TRGCTRL/SC_TRG1_STRECH/SLICE_4923"
+ COMP "THE_APV_TRGCTRL/SC_TRG2_STRECH/SLICE_4924"
+ COMP "THE_APV_TRGCTRL/SC_TRG2_STRECH/SLICE_4925"
+ COMP "THE_APV_TRGCTRL/SC_TRG2_STRECH/SLICE_4926"
+ COMP "THE_APV_TRGCTRL/SC_TRG3_STRECH/SLICE_4927"
+ COMP "THE_APV_TRGCTRL/SC_TRG3_STRECH/SLICE_4928"
+ COMP "THE_APV_TRGCTRL/SC_TRG3_STRECH/SLICE_4929"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_4930"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_4931"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_4932"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_4933"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_4934"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_4935"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/THE_APVTRGSTART_SYNC/SLICE_4937"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/THE_APVTRGSTART_SYNC/SLICE_4938"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/THE_APVTRGSTART_SYNC/SLICE_4939"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/THE_APVTRGSTART_SYNC/SLICE_4940"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4941"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4942"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4943"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGDONE_SYNC/SLICE_4945"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGDONE_SYNC/SLICE_4946"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGDONE_SYNC/SLICE_4947"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGSENT_SYNC/SLICE_4949"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGSENT_SYNC/SLICE_4950"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGSENT_SYNC/SLICE_4951"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGSTART_SYNC/SLICE_4953"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGSTART_SYNC/SLICE_4954"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGSTART_SYNC/SLICE_4955"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4956"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4957"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4958"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGSTART_SYNC/SLICE_4959"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4960"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4961"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4962"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4963"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4964"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4965"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4966"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGDONE_SYNC/SLICE_4968"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGDONE_SYNC/SLICE_4969"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGDONE_SYNC/SLICE_4970"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGSENT_SYNC/SLICE_4972"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGSENT_SYNC/SLICE_4973"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGSENT_SYNC/SLICE_4974"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGSTART_SYNC/SLICE_4976"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGSTART_SYNC/SLICE_4977"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGSTART_SYNC/SLICE_4978"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4979"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4980"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4981"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGSTART_SYNC/SLICE_4982"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4983"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4984"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4985"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4986"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_4987"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_4988"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_4989"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGDONE_SYNC/SLICE_4991"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGDONE_SYNC/SLICE_4992"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGDONE_SYNC/SLICE_4993"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGSENT_SYNC/SLICE_4995"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGSENT_SYNC/SLICE_4996"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGSENT_SYNC/SLICE_4997"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGSTART_SYNC/SLICE_4999"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGSTART_SYNC/SLICE_5000"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGSTART_SYNC/SLICE_5001"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_5002"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_5003"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_5004"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGSTART_SYNC/SLICE_5005"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_5006"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_5007"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_5008"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_5009"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5010"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5011"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5012"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGDONE_SYNC/SLICE_5014"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGDONE_SYNC/SLICE_5015"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGDONE_SYNC/SLICE_5016"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGSENT_SYNC/SLICE_5018"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGSENT_SYNC/SLICE_5019"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGSENT_SYNC/SLICE_5020"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGSTART_SYNC/SLICE_5022"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGSTART_SYNC/SLICE_5023"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGSTART_SYNC/SLICE_5024"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5025"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5026"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5027"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGSTART_SYNC/SLICE_5028"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5029"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5030"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5031"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5032"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5033"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5034"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5035"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5036"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5037"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5038"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5039"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5040"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5041"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5042"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5043"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5044"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5045"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5046"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5047"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5048"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5049"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5050"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5051"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5052"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5053"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5054"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5055"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5056"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5057"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/THE_TIME_TRG_3_SYNC/SLICE_5058"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5059"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5060"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5061"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5062"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5063"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5064"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5065"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5066"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5067"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5068"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5069"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5070"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5071"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5072"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5073"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5074"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5075"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5076"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5077"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5078"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5079"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5080"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5081"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5082"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5083"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5084"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5085"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5086"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5087"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5088"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5089"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5090"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5091"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5092"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_5093"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_5094"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_5095"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_5096"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5097"
+ COMP "THE_APV_TRGCTRL/SLICE_5098"
+ COMP "THE_APV_TRGCTRL/SLICE_5099"
+ COMP "THE_APV_TRGCTRL/SLICE_5100"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5101"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5102"
+ COMP "THE_APV_TRGCTRL/SLICE_5103"
+ COMP "THE_APV_TRGCTRL/SLICE_5104"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5105"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5106"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5107"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5108"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5109"
+ COMP "THE_APV_TRGCTRL/SLICE_5110"
+ COMP "THE_APV_TRGCTRL/SLICE_5111"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5112"
+ COMP "THE_APV_TRGCTRL/SLICE_5113"
+ COMP "THE_APV_TRGCTRL/SLICE_5114"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5116"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5117"
+ COMP "THE_APV_TRGCTRL/SLICE_10625"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_10628"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_10629"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_10630"
+ COMP "THE_APV_TRGCTRL/SLICE_10631"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_10787"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_11069"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_11085"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_11095"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_11098"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_11099"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_11208"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_11209"
+ COMP "THE_APV_TRGCTRL/SLICE_11210"
+ COMP "THE_APV_TRGCTRL/SLICE_11211"
+ COMP "THE_APV_TRGCTRL/SLICE_11212"
+ COMP "THE_APV_TRGCTRL/SLICE_11213"
+ COMP "THE_APV_TRGCTRL/SLICE_11214"
+ COMP "THE_APV_TRGCTRL/SLICE_11215"
+ COMP "THE_APV_TRGCTRL/SLICE_11216"
+ COMP "THE_APV_TRGCTRL/SLICE_11217"
+ COMP "THE_APV_TRGCTRL/SLICE_11218"
+ COMP "THE_APV_TRGCTRL/SLICE_11219"
+ COMP "THE_APV_TRGCTRL/SLICE_11220"
+ COMP "THE_APV_TRGCTRL/SLICE_11221"
+ COMP "THE_APV_TRGCTRL/SLICE_11222"
+ COMP "THE_APV_TRGCTRL/SLICE_11223"
+ COMP "THE_APV_TRGCTRL/SLICE_11224"
+ COMP "THE_APV_TRGCTRL/SLICE_11225"
+ COMP "THE_APV_TRGCTRL/SLICE_11226"
+ COMP "THE_APV_TRGCTRL/SLICE_11227"
+ COMP "THE_APV_TRGCTRL/SLICE_11228"
+ COMP "THE_APV_TRGCTRL/SLICE_11229"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/THE_TRG_PRIORITY_PROC_todo_start_6_m2_0/SLICE_11785"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/THE_TRG_PRIORITY_PROC_todo_start_6_m2_1/SLICE_11786"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/THE_TRG_PRIORITY_PROC_todo_start_6_m2_2/SLICE_11787"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/THE_TRG_PRIORITY_PROC_todo_start_6_m2_3/SLICE_11788"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_12183"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_12184"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_12185"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_12186"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_12563"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_13376"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_13377"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_13378"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_13379"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_13380"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_13381";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_708"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_709"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_710"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_711"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_712"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_713"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_714"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_715"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_716"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_717"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_718"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_719"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_720"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_721"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_722"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_723"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_724"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4153"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4154"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4155"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4156"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4157"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4158"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4159"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4160"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7202"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7203"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7204"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7206"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7207"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7208"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7210"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7213"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7214"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7215"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_7216"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7218"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7219"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7220"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7221"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7222"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7223"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7224"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7225"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7226"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7227"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7228"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_10647"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_10648"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_10649"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_10709"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10725"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_13390"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_13391"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_13392"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_13393"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_725"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_726"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_727"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_728"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_729"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_730"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_731"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_732"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_733"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_734"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_735"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_736"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_737"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_738"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_739"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_740"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_741"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4161"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4162"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4163"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4164"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4165"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4166"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4167"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4168"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7718"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7719"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7720"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7722"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7723"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7724"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7726"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7729"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7730"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7731"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_7732"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7734"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7735"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7736"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7737"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7738"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7739"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7740"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7741"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7742"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7743"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7744"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_10686"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_10687"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_10688"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_10707"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10723"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_13394"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_13395"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_13396"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_13397"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_742"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_743"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_744"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_745"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_746"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_747"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_748"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_749"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_750"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_751"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_752"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_753"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_754"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_755"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_756"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_757"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_758"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4169"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4170"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4171"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4172"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4173"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4174"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4175"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4176"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7632"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7633"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7634"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7636"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7637"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7638"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7640"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7643"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7644"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7645"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_7646"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7648"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7649"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7650"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7651"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7652"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7653"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7654"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7655"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7656"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7657"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7658"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_10683"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_10684"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_10685"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_10706"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10722"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_13398"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_13399"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_13400"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_13401"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_759"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_760"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_761"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_762"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_763"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_764"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_765"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_766"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_767"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_768"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_769"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_770"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_771"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_772"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_773"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_774"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_775"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4177"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4178"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4179"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4180"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4181"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4182"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4183"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4184"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7546"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7547"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7548"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7550"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7551"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7552"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7554"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7557"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7558"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7559"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_7560"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7562"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7563"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7564"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7565"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7566"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7567"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7568"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7569"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7570"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7571"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7572"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_10659"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_10660"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_10661"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_10713"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10729"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_13402"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_13403"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_13404"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_13405"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_13406"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_776"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_777"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_778"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_779"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_780"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_781"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_782"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_783"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_784"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_785"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_786"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_787"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_788"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_789"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_790"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_791"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_792"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4185"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4186"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4187"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4188"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4189"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4190"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4191"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4192"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7460"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7461"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7462"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7464"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7465"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7466"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7468"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7471"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7472"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7473"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7474"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7476"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7477"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7478"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7479"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7480"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7481"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7482"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7483"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7484"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7485"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7486"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_10656"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_10657"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_10658"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_10712"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10728"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_13407"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_13408"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_13409"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_13410"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_793"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_794"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_795"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_796"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_797"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_798"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_799"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_800"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_801"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_802"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_803"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_804"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_805"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_806"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_807"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_808"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_809"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4193"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4194"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4195"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4196"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4197"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4198"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4199"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4200"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7288"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7289"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7290"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7292"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7293"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7294"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7296"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7299"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7300"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7301"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_7302"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7304"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7305"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7306"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7307"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7308"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7309"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7310"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7311"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7312"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7313"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7314"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_10650"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_10651"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_10652"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_10710"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10726"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_13411"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_13412"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_13413"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_13414"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_13415"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_810"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_811"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_812"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_813"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_814"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_815"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_816"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_817"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_818"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_819"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_820"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_821"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_822"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_823"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_824"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_825"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_826"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4201"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4202"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4203"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4204"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4205"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4206"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4207"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4208"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7374"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7375"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7376"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7378"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7379"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7380"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7382"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7385"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7386"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7387"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7388"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7390"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7391"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7392"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7393"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7394"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7395"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7396"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7397"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7398"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7399"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7400"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_10653"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_10654"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_10655"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_10711"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10727"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_13416"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_13417"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_13418"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_13419"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_13420"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_827"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_828"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_829"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_830"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_831"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_832"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_833"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_834"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_835"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_836"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_837"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_838"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_839"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_840"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_841"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_842"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_843"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4209"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4210"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4211"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4212"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4213"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4214"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4215"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4216"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7116"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7117"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7118"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7120"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7121"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7122"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7124"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7127"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7128"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7129"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7130"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7132"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7133"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7134"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7135"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7136"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7137"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7138"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7139"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7140"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7141"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7142"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_10644"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_10645"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_10646"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_10708"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10724"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_13421"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_13422"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_13423"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_13424"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1100"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1101"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1102"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1103"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1104"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1105"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1106"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1107"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1108"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1109"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1110"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1111"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1112"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1113"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1114"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1115"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1116"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4233"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4234"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4235"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4236"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4237"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4238"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4239"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4240"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6428"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6429"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6430"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6432"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6433"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6434"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_6436"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6439"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6440"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6441"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_6442"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6444"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6445"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6446"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6447"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6448"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6449"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6450"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6451"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6452"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6453"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6454"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_10641"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_10642"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_10643"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_10698"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10714"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_13502"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_13503"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_13504"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_13505"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1117"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1118"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1119"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1120"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1121"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1122"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1123"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1124"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1125"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1126"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1127"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1128"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1129"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1130"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1131"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1132"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1133"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4241"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4242"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4243"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4244"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4245"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4246"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4247"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4248"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6944"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6945"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6946"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6948"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6949"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6950"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_6952"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6955"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6956"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6957"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_6958"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6960"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6961"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6962"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6963"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6964"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6965"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6966"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6967"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6968"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6969"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6970"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_10677"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_10678"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_10679"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_10704"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10720"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_13506"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_13507"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_13508"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_13509"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_13510"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1134"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1135"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1136"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1137"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1138"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1139"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1140"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1141"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1142"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1143"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1144"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1145"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1146"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1147"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1148"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1149"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1150"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4249"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4250"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4251"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4252"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4253"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4254"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4255"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4256"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7030"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7031"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7032"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7034"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7035"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7036"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7038"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7041"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7042"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7043"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_7044"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7046"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7047"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7048"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7049"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7050"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7051"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7052"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7053"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7054"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7055"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7056"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_10680"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_10681"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_10682"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_10705"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10721"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_13511"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_13512"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_13513"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_13514"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_13515"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1151"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1152"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1153"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1154"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1155"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1156"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1157"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1158"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1159"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1160"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1161"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1162"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1163"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1164"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1165"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1166"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1167"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4257"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4258"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4259"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4260"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4261"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4262"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4263"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4264"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6600"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6601"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6602"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6604"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6605"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6606"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_6608"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6611"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6612"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6613"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_6614"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6616"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6617"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6618"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6619"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6620"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6621"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6622"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6623"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6624"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6625"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6626"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_10665"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_10666"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_10667"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_10700"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10716"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_13516"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_13517"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_13518"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_13519"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1168"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1169"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1170"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1171"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1172"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1173"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1174"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1175"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1176"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1177"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1178"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1179"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1180"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1181"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1182"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1183"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1184"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4265"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4266"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4267"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4268"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4269"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4270"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4271"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4272"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6858"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6859"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6860"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6862"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6863"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6864"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_6866"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6869"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6870"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6871"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_6872"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6874"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6875"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6876"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6877"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6878"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6879"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6880"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6881"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6882"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6883"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6884"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_10674"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_10675"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_10676"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_10703"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10719"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_13520"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_13521"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_13522"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_13523"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_13524"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1185"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1186"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1187"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1188"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1189"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1190"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1191"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1192"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1193"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1194"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1195"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1196"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1197"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1198"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1199"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1200"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1201"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4273"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4274"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4275"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4276"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4277"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4278"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4279"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4280"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6514"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6515"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6516"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6518"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6519"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6520"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_6522"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6525"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6526"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6527"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_6528"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6530"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6531"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6532"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6533"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6534"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6535"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6536"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6537"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6538"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6539"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6540"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_10662"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_10663"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_10664"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_10699"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10715"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_13525"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_13526"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_13527"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_13528"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1202"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1203"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1204"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1205"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1206"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1207"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1208"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1209"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1210"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1211"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1212"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1213"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1214"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1215"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1216"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1217"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1218"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4281"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4282"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4283"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4284"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4285"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4286"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4287"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4288"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6686"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6687"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6688"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6690"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6691"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6692"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_6694"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6697"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6698"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6699"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_6700"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6702"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6703"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6704"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6705"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6706"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6707"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6708"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6709"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6710"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6711"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6712"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_10668"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_10669"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_10670"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_10701"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10717"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_13529"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_13530"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_13531"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_13532"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1219"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1220"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1221"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1222"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1223"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1224"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1225"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1226"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1227"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1228"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1229"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1230"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1231"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1232"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1233"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1234"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1235"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4289"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4290"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4291"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4292"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4293"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4294"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4295"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4296"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6772"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6773"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6774"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6776"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6777"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6778"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_6780"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6783"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6784"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6785"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_6786"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6788"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6789"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6790"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6791"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6792"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6793"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6794"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6795"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6796"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6797"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6798"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_10671"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_10672"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_10673"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_10702"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10718"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_13533"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_13534"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_13535"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_13536"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_13537"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_IPU_STAGE/IPU_FIFO_STAGE_group"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2347"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2348"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2349"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2350"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2351"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2352"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2353"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2354"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2355"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2356"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2357"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2358"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2359"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2360"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2361"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2362"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2363"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2364"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2365"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2366"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2367"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2368"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2369"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2370"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2371"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2372"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2373"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2374"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2375"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2376"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2377"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2378"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2379"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2380"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2381"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2382"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2383"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2384"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2385"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2386"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2387"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2388"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2389"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2390"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2391"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2392"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2393"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2394"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2395"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2396"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2397"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2398"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2399"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2400"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2401"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2402"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2403"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2404"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2405"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2406"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2407"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2408"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2409"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2410"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2411"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2412"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2413"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2414"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2415"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2416"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2417"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2418"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2419"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2420"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2421"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2422"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2423"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2424"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2425"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2426"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2427"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2428"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2429"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2430"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2431"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2432"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2433"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2434"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2435"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2436"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2437"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2438"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2439"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2440"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2441"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2442"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2443"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2444"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2445"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2446"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2447"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2448"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2449"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2450"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2451"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2452"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2453"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2454"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2455"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2456"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2457"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2458"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2459"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2460"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2461"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2462"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2463"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2464"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2465"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2466"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2467"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2468"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2469"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2470"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2471"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2472"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2473"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2474"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2475"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2476"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2477"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2478"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2479"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2480"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2481"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2482"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2483"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2484"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2485"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2486"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2487"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2488"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2489"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2490"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2491"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2492"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2493"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2494"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2495"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2496"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2497"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2498"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2499"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2500"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2501"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2502"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2503"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2504"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2505"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2506"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2507"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2508"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2509"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2510"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2511"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2512"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2513"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2514"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2515"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2516"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2517"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2518"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2519"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2520"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2521"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2522"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2523"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2524"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2525"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2526"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2527"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2528"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2529"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2530"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2531"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2532"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2533"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2534"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2535"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2536"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2537"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2538"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2539"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2540"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2541"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2542"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2543"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2544"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2545"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2546"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2547"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2548"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2549"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2550"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2551"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2552"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2553"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2554"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2555"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2556"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2557"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2558"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2559"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2560"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2561"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2562"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2563"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2564"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2565"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2566"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2567"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2568"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2569"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2570"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2571"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2572"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2573"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2574"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2575"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2576"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2577"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2578"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2579"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2580"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2581"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2582"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2583"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2584"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2585"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2586"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2587"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2588"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2589"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2590"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2591"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2592"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2593"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2594"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2595"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2596"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2597"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2598"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2599"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2600"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2601"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2602"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2603"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2604"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2605"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2606"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2607"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2608"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2609"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2610"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2611"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2612"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2613"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2614"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2615"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2616"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2617"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2618"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2619"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2620"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2621"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2622"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2623"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2624"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2625"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2626"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2627"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2628"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2629"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2630"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2631"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2632"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2633"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2634"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2635"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2636"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2637"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2638"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2639"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2640"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2641"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2642"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2643"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2644"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2645"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2646"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2647"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2648"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2649"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2650"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2651"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2652"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2653"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2654"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2655"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2656"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2657"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2658"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2659"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2660"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2661"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2662"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2663"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2664"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2665"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2666"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2667"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2668"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2669"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2670"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2671"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2672"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2673"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2674"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2675"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2676"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2677"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2678"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2679"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2680"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2681"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2682"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2683"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2684"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2685"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2686"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2687"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2688"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2689"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2690"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2691"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2692"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2693"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2694"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2695"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2696"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2697"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2698"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2699"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2700"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2701"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2702"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2703"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2704"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2705"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2706"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2707"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2708"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2709"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2710"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2711"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2712"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2713"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2714"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2715"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2716"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2717"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2718"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2719"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2720"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2721"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2722"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2723"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2724"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2725"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2726"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2727"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2728"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2729"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2730"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2731"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2732"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2733"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2734"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2735"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2736"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2737"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2738"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2739"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2740"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2741"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2742"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2743"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2744"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2745"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2746"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2747"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2748"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2749"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2750"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2751"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2752"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2753"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2754"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2755"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2756"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2757"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2758"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2759"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2760"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2761"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2762"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2763"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2764"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2765"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2766"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2767"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2768"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2769"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2770"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2771"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2772"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2773"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2774"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2775"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2776"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2777"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2778"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2779"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2780"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2781"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2782"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2783"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2784"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2785"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2786"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2787"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2788"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2789"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2790"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2791"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2792"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2793"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2794"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2795"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2796"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2797"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2798"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2799"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2800"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2801"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2802"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2803"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2804"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2805"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2806"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2807"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2808"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2809"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2810"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2811"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2812"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2813"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2814"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2815"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2816"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2817"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2818"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2819"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2820"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2821"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2822"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2823"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2824"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2825"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2826"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2827"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2828"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2829"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2830"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2831"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2832"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2833"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2834"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2835"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2836"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2837"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2838"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2839"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2840"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2841"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2842"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2843"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2844"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2845"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2846"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2847"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2848"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2849"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2850"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2851"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2852"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2853"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2854"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2855"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2856"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2857"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2858"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2859"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2860"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2861"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2862"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2863"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2864"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2865"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2866"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2867"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2868"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2869"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2870"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2871"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2872"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2873"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2874"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2875"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2876"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2877"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2878"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2879"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2880"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2881"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2882"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2883"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2884"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2885"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2886"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2887"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2888"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2889"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2890"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2891"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2892"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2893"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2894"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2895"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2896"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2897"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2898"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2899"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2900"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2901"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2902"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2903"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2904"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2905"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2906"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2907"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2908"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2909"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2910"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2911"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2912"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2913"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2914"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2915"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2916"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2917"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2918"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2919"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2920"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2921"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2922"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2923"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2924"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2925"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2926"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2927"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2928"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2929"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2930"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2931"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2932"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2933"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2934"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2935"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2936"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2937"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2938"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2939"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2940"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2941"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2942"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2943"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2944"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2945"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2946"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2947"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2948"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2949"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2950"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2951"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2952"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2953"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2954"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2955"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2956"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2957"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2958"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2959"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2960"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2961"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2962"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2963"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2964"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2965"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2966"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2967"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2968"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2969"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2970"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2971"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2972"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2973"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2974"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2975"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2976"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2977"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2978"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2979"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2980"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2981"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2982"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2983"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2984"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2985"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2986"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2987"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2988"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2989"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2990"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2991"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2992"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2993"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2994"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2995"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2996"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2997"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2998"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2999"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3000"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3001"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3002"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3003"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3004"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3005"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3006"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3007"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3008"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3009"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3010"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3011"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3012"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3013"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3014"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3015"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3016"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3017"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3018"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3019"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3020"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3021"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3022"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3023"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3024"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3025"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3026"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3027"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3028"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3029"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3030"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3031"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3032"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3033"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3034"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3035"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3036"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3037"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3038"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3039"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3040"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3041"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3042"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3043"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3044"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3045"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3046"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3047"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3048"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3049"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3050"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3051"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3052"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3053"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3054"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3055"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3056"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3057"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3058"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3059"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3060"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3061"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3062"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3063"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3064"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3065"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3066"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3067"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3068"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3069"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3070"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3071"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3072"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3073"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3074"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3075"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3076"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3077"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3078"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3079"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3080"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3081"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3082"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3083"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3084"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3085"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3086"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3087"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3088"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3089"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3090"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3091"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3092"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3093"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3094"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3095"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3096"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3097"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3098"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3099"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3100"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3101"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3102"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3103"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3104"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3105"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3106"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3107"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3108"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3109"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3110"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3111"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3112"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3113"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3114"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3115"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3116"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3117"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3118"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3119"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3120"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3121"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3122"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3123"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3124"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3125"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3126"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3127"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3128"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3129"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3130"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3131"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3132"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3133"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3134"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3135"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3136"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3137"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3138"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3139"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3140"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3141"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3142"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3143"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3144"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3145"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3146"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3147"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3148"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3149"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3150"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3151"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3152"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3153"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3154"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3155"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3156"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3157"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3158"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3159"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3160"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3161"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3162"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3163"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3164"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3165"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3166"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3167"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3168"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3169"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3170"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3171"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3172"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3173"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3174"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3175"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3176"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3177"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3178"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3179"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3180"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3181"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3182"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3183"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3184"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3185"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3186"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3187"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3188"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3189"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3190"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3191"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3192"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3193"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3194"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3195"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3196"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3197"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3198"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3199"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3200"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3201"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3202"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3203"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3204"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3205"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3206"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3207"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3208"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3209"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3210"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3211"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3212"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3213"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3214"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3215"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3216"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3217"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3218"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3219"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3220"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3221"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3222"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3223"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3224"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3225"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3226"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3227"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3228"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3229"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3230"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3231"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3232"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3233"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3234"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3235"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3236"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3237"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3238"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3239"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3240"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3241"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3242"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3243"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3244"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3245"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3246"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3247"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3248"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3249"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3250"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3251"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3252"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3253"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3254"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3255"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3256"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3257"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3258"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3259"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3260"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3261"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3262"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3263"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3264"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3265"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3266"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3267"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3268"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3269"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3270"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3271"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3272"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3273"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3274"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3275"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3276"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3277"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3278"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3279"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3280"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3281"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3282"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3283"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3284"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3285"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3286"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3287"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3288"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3289"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3290"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3291"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3292"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3293"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3294"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3295"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3296"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3297"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3298"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3299"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3300"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3301"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3302"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3303"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3304"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3305"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3306"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3307"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3308"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3309"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3310"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3311"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3312"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3313"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3314"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3315"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3316"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3317"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3318"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3319"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3320"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3321"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3322"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3323"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3324"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3325"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3326"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3327"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3328"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3329"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3330"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3331"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3332"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3333"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3334"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3335"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3336"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3337"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3338"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3339"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3340"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3341"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3342"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3343"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3344"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3345"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3346"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3347"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3348"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3349"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3350"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3351"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3352"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3353"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3354"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3355"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3356"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3357"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3358"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3359"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3360"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3361"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3362"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3363"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3364"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3365"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3366"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3367"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3368"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3369"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3370"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3371"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3372"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3373"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3374"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3375"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3376"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3377"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3378"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3379"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3380"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3381"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3382"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3383"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3384"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3385"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3386"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3387"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3388"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3389"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3390"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3391"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3392"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3393"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3394"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3395"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3396"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3397"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3398"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3399"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3400"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3401"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3402"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3403"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3404"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3405"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3406"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3407"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3408"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3409"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3410"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3411"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3412"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3413"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3414"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3415"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3416"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3417"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3418"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3419"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3420"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3421"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3422"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3423"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3424"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3425"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3426"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3427"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3428"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3429"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3430"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3431"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3432"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3433"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3434"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3435"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3436"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3437"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3438"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3439"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3440"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3441"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3442"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3443"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3444"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3445"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3446"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3447"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3448"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3449"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3450"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3451"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3452"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3453"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3454"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3455"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3456"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3457"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3458"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3459"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3460"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3461"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3462"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3463"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3464"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3465"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3466"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3467"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3468"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3469"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3470"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3471"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3472"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3473"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3474"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3475"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3476"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3477"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3478"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3479"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3480"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3481"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3482"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3483"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3484"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3485"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3486"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3487"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3488"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3489"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3490"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3491"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3492"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3493"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3494"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3495"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3496"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3497"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3498"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3499"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3500"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3501"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3502"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3503"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3504"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3505"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3506"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3507"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3508"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3509"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3510"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3511"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3512"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3513"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3514"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3515"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3516"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3517"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3518"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3519"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3520"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3521"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3522"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3523"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3524"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3525"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3526"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3527"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3528"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3529"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3530"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3531"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3532"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3533"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3534"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3535"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3536"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3537"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3538"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3539"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3540"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3541"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3542"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3543"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3544"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3545"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3546"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3547"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3548"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3549"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3550"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3551"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3552"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3553"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3554"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3555"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3556"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3557"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3558"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3559"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3560"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3561"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3562"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3563"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3564"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3565"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3566"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3567"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3568"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3569"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3570"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3571"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3572"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3573"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3574"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3575"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3576"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3577"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3578"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3579"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3580"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3581"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3582"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3583"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3584"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3585"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3586"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3587"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3588"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3589"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3590"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3591"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3592"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3593"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3594"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3595"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3596"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3597"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3598"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3599"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3600"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3601"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3602"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3603"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3604"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3605"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3606"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3607"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3608"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3609"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3610"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3611"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3612"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3613"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3614"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3615"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3616"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3617"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3618"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3619"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3620"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3621"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3622"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3623"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3624"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3625"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3626"
+ COMP "THE_IPU_STAGE/SLICE_3627"
+ COMP "THE_IPU_STAGE/SLICE_3628"
+ COMP "THE_IPU_STAGE/SLICE_3629"
+ COMP "THE_IPU_STAGE/SLICE_3630"
+ COMP "THE_IPU_STAGE/SLICE_3631"
+ COMP "THE_IPU_STAGE/SLICE_3632"
+ COMP "THE_IPU_STAGE/SLICE_3633"
+ COMP "THE_IPU_STAGE/SLICE_3634"
+ COMP "THE_IPU_STAGE/SLICE_3635"
+ COMP "THE_IPU_STAGE/SLICE_3636"
+ COMP "THE_IPU_STAGE/SLICE_3637"
+ COMP "THE_IPU_STAGE/SLICE_3638"
+ COMP "THE_IPU_STAGE/SLICE_3639"
+ COMP "THE_IPU_STAGE/SLICE_3640"
+ COMP "THE_IPU_STAGE/SLICE_3641"
+ COMP "THE_IPU_STAGE/SLICE_3642"
+ COMP "THE_IPU_STAGE/SLICE_3643"
+ COMP "THE_IPU_STAGE/SLICE_3644"
+ COMP "THE_IPU_STAGE/SLICE_3645"
+ COMP "THE_IPU_STAGE/SLICE_3646"
+ COMP "THE_IPU_STAGE/SLICE_3647"
+ COMP "THE_IPU_STAGE/SLICE_3648"
+ COMP "THE_IPU_STAGE/SLICE_3649"
+ COMP "THE_IPU_STAGE/SLICE_3650"
+ COMP "THE_IPU_STAGE/SLICE_3651"
+ COMP "THE_IPU_STAGE/SLICE_3652"
+ COMP "THE_IPU_STAGE/SLICE_3653"
+ COMP "THE_IPU_STAGE/SLICE_3654"
+ COMP "THE_IPU_STAGE/SLICE_3655"
+ COMP "THE_IPU_STAGE/SLICE_3656"
+ COMP "THE_IPU_STAGE/SLICE_3657"
+ COMP "THE_IPU_STAGE/SLICE_3658"
+ COMP "THE_IPU_STAGE/SLICE_3659"
+ COMP "THE_IPU_STAGE/SLICE_3660"
+ COMP "THE_IPU_STAGE/SLICE_3661"
+ COMP "THE_IPU_STAGE/SLICE_3662"
+ COMP "THE_IPU_STAGE/SLICE_3663"
+ COMP "THE_IPU_STAGE/SLICE_3664"
+ COMP "THE_IPU_STAGE/SLICE_3665"
+ COMP "THE_IPU_STAGE/SLICE_3666"
+ COMP "THE_IPU_STAGE/SLICE_3667"
+ COMP "THE_IPU_STAGE/SLICE_3668"
+ COMP "THE_IPU_STAGE/SLICE_3669"
+ COMP "THE_IPU_STAGE/SLICE_3670"
+ COMP "THE_IPU_STAGE/SLICE_3671"
+ COMP "THE_IPU_STAGE/SLICE_3672"
+ COMP "THE_IPU_STAGE/SLICE_3673"
+ COMP "THE_IPU_STAGE/SLICE_3674"
+ COMP "THE_IPU_STAGE/SLICE_3675"
+ COMP "THE_IPU_STAGE/SLICE_3676"
+ COMP "THE_IPU_STAGE/SLICE_3677"
+ COMP "THE_IPU_STAGE/SLICE_3678"
+ COMP "THE_IPU_STAGE/SLICE_3679"
+ COMP "THE_IPU_STAGE/SLICE_3680"
+ COMP "THE_IPU_STAGE/SLICE_3681"
+ COMP "THE_IPU_STAGE/SLICE_3682"
+ COMP "THE_IPU_STAGE/SLICE_3683"
+ COMP "THE_IPU_STAGE/SLICE_3684"
+ COMP "THE_IPU_STAGE/SLICE_3685"
+ COMP "THE_IPU_STAGE/SLICE_3686"
+ COMP "THE_IPU_STAGE/SLICE_3687"
+ COMP "THE_IPU_STAGE/SLICE_3688"
+ COMP "THE_IPU_STAGE/SLICE_3689"
+ COMP "THE_IPU_STAGE/SLICE_3690"
+ COMP "THE_IPU_STAGE/SLICE_3691"
+ COMP "THE_IPU_STAGE/SLICE_3692"
+ COMP "THE_IPU_STAGE/SLICE_3693"
+ COMP "THE_IPU_STAGE/SLICE_3694"
+ COMP "THE_IPU_STAGE/SLICE_3695"
+ COMP "THE_IPU_STAGE/SLICE_3696"
+ COMP "THE_IPU_STAGE/SLICE_3697"
+ COMP "THE_IPU_STAGE/SLICE_3698"
+ COMP "THE_IPU_STAGE/SLICE_3699"
+ COMP "THE_IPU_STAGE/SLICE_3700"
+ COMP "THE_IPU_STAGE/SLICE_3701"
+ COMP "THE_IPU_STAGE/SLICE_3702"
+ COMP "THE_IPU_STAGE/SLICE_3703"
+ COMP "THE_IPU_STAGE/SLICE_3704"
+ COMP "THE_IPU_STAGE/SLICE_3705"
+ COMP "THE_IPU_STAGE/SLICE_3706"
+ COMP "THE_IPU_STAGE/SLICE_3707"
+ COMP "THE_IPU_STAGE/SLICE_3708"
+ COMP "THE_IPU_STAGE/SLICE_3709"
+ COMP "THE_IPU_STAGE/SLICE_3710"
+ COMP "THE_IPU_STAGE/SLICE_3711"
+ COMP "THE_IPU_STAGE/SLICE_3712"
+ COMP "THE_IPU_STAGE/SLICE_3713"
+ COMP "THE_IPU_STAGE/SLICE_3714"
+ COMP "THE_IPU_STAGE/SLICE_3715"
+ COMP "THE_IPU_STAGE/SLICE_3716"
+ COMP "THE_IPU_STAGE/SLICE_3717"
+ COMP "THE_IPU_STAGE/SLICE_3718"
+ COMP "THE_IPU_STAGE/SLICE_3719"
+ COMP "THE_IPU_STAGE/SLICE_3720"
+ COMP "THE_IPU_STAGE/SLICE_3721"
+ COMP "THE_IPU_STAGE/SLICE_3722"
+ COMP "THE_IPU_STAGE/SLICE_3723"
+ COMP "THE_IPU_STAGE/SLICE_3724"
+ COMP "THE_IPU_STAGE/SLICE_3725"
+ COMP "THE_IPU_STAGE/SLICE_3726"
+ COMP "THE_IPU_STAGE/SLICE_3727"
+ COMP "THE_IPU_STAGE/SLICE_3728"
+ COMP "THE_IPU_STAGE/SLICE_3729"
+ COMP "THE_IPU_STAGE/SLICE_3730"
+ COMP "THE_IPU_STAGE/SLICE_3731"
+ COMP "THE_IPU_STAGE/SLICE_3732"
+ COMP "THE_IPU_STAGE/SLICE_3733"
+ COMP "THE_IPU_STAGE/SLICE_3734"
+ COMP "THE_IPU_STAGE/SLICE_3735"
+ COMP "THE_IPU_STAGE/SLICE_3736"
+ COMP "THE_IPU_STAGE/SLICE_3737"
+ COMP "THE_IPU_STAGE/SLICE_3738"
+ COMP "THE_IPU_STAGE/SLICE_3739"
+ COMP "THE_IPU_STAGE/SLICE_3740"
+ COMP "THE_IPU_STAGE/SLICE_3741"
+ COMP "THE_IPU_STAGE/SLICE_3742"
+ COMP "THE_IPU_STAGE/SLICE_3743"
+ COMP "THE_IPU_STAGE/SLICE_3744"
+ COMP "THE_IPU_STAGE/SLICE_3745"
+ COMP "THE_IPU_STAGE/SLICE_3746"
+ COMP "THE_IPU_STAGE/SLICE_3747"
+ COMP "THE_IPU_STAGE/SLICE_3748"
+ COMP "THE_IPU_STAGE/SLICE_3749"
+ COMP "THE_IPU_STAGE/SLICE_3750"
+ COMP "THE_IPU_STAGE/SLICE_3751"
+ COMP "THE_IPU_STAGE/SLICE_3752"
+ COMP "THE_IPU_STAGE/SLICE_3753"
+ COMP "THE_IPU_STAGE/SLICE_3754"
+ COMP "THE_IPU_STAGE/SLICE_3755"
+ COMP "THE_IPU_STAGE/SLICE_3756"
+ COMP "THE_IPU_STAGE/SLICE_3757"
+ COMP "THE_IPU_STAGE/SLICE_3758"
+ COMP "THE_IPU_STAGE/SLICE_3759"
+ COMP "THE_IPU_STAGE/SLICE_3760"
+ COMP "THE_IPU_STAGE/SLICE_3761"
+ COMP "THE_IPU_STAGE/SLICE_3762"
+ COMP "THE_IPU_STAGE/SLICE_3763"
+ COMP "THE_IPU_STAGE/SLICE_3764"
+ COMP "THE_IPU_STAGE/SLICE_3765"
+ COMP "THE_IPU_STAGE/SLICE_3766"
+ COMP "THE_IPU_STAGE/SLICE_3767"
+ COMP "THE_IPU_STAGE/SLICE_3768"
+ COMP "THE_IPU_STAGE/SLICE_3769"
+ COMP "THE_IPU_STAGE/SLICE_3770"
+ COMP "THE_IPU_STAGE/SLICE_3771"
+ COMP "THE_IPU_STAGE/SLICE_3772"
+ COMP "THE_IPU_STAGE/SLICE_3773"
+ COMP "THE_IPU_STAGE/SLICE_3774"
+ COMP "THE_IPU_STAGE/SLICE_3775"
+ COMP "THE_IPU_STAGE/SLICE_3776"
+ COMP "THE_IPU_STAGE/SLICE_3777"
+ COMP "THE_IPU_STAGE/SLICE_3778"
+ COMP "THE_IPU_STAGE/SLICE_3779"
+ COMP "THE_IPU_STAGE/SLICE_3780"
+ COMP "THE_IPU_STAGE/SLICE_3781"
+ COMP "THE_IPU_STAGE/SLICE_3782"
+ COMP "THE_IPU_STAGE/SLICE_3783"
+ COMP "THE_IPU_STAGE/SLICE_3784"
+ COMP "THE_IPU_STAGE/SLICE_3785"
+ COMP "THE_IPU_STAGE/SLICE_3786"
+ COMP "THE_IPU_STAGE/SLICE_3787"
+ COMP "THE_IPU_STAGE/SLICE_3788"
+ COMP "THE_IPU_STAGE/SLICE_3789"
+ COMP "THE_IPU_STAGE/SLICE_3790"
+ COMP "THE_IPU_STAGE/SLICE_3791"
+ COMP "THE_IPU_STAGE/SLICE_3792"
+ COMP "THE_IPU_STAGE/SLICE_3793"
+ COMP "THE_IPU_STAGE/SLICE_3794"
+ COMP "THE_IPU_STAGE/SLICE_3795"
+ COMP "THE_IPU_STAGE/SLICE_3796"
+ COMP "THE_IPU_STAGE/SLICE_3797"
+ COMP "THE_IPU_STAGE/SLICE_3798"
+ COMP "THE_IPU_STAGE/SLICE_3799"
+ COMP "THE_IPU_STAGE/SLICE_3800"
+ COMP "THE_IPU_STAGE/SLICE_3801"
+ COMP "THE_IPU_STAGE/SLICE_3802"
+ COMP "THE_IPU_STAGE/SLICE_3803"
+ COMP "THE_IPU_STAGE/SLICE_3804"
+ COMP "THE_IPU_STAGE/SLICE_3805"
+ COMP "THE_IPU_STAGE/SLICE_3806"
+ COMP "THE_IPU_STAGE/SLICE_3807"
+ COMP "THE_IPU_STAGE/SLICE_3808"
+ COMP "THE_IPU_STAGE/SLICE_3809"
+ COMP "THE_IPU_STAGE/SLICE_3810"
+ COMP "THE_IPU_STAGE/SLICE_3811"
+ COMP "THE_IPU_STAGE/SLICE_3812"
+ COMP "THE_IPU_STAGE/SLICE_3813"
+ COMP "THE_IPU_STAGE/SLICE_3814"
+ COMP "THE_IPU_STAGE/SLICE_3815"
+ COMP "THE_IPU_STAGE/SLICE_3816"
+ COMP "THE_IPU_STAGE/SLICE_3817"
+ COMP "THE_IPU_STAGE/SLICE_3818"
+ COMP "THE_IPU_STAGE/SLICE_3819"
+ COMP "THE_IPU_STAGE/SLICE_3820"
+ COMP "THE_IPU_STAGE/SLICE_3821"
+ COMP "THE_IPU_STAGE/SLICE_3822"
+ COMP "THE_IPU_STAGE/SLICE_3823"
+ COMP "THE_IPU_STAGE/SLICE_3824"
+ COMP "THE_IPU_STAGE/SLICE_3825"
+ COMP "THE_IPU_STAGE/SLICE_3826"
+ COMP "THE_IPU_STAGE/SLICE_3827"
+ COMP "THE_IPU_STAGE/SLICE_3828"
+ COMP "THE_IPU_STAGE/SLICE_3829"
+ COMP "THE_IPU_STAGE/SLICE_3830"
+ COMP "THE_IPU_STAGE/SLICE_3831"
+ COMP "THE_IPU_STAGE/SLICE_3832"
+ COMP "THE_IPU_STAGE/SLICE_3833"
+ COMP "THE_IPU_STAGE/SLICE_3834"
+ COMP "THE_IPU_STAGE/SLICE_3835"
+ COMP "THE_IPU_STAGE/SLICE_3836"
+ COMP "THE_IPU_STAGE/SLICE_3837"
+ COMP "THE_IPU_STAGE/SLICE_3838"
+ COMP "THE_IPU_STAGE/SLICE_3839"
+ COMP "THE_IPU_STAGE/SLICE_3840"
+ COMP "THE_IPU_STAGE/SLICE_3841"
+ COMP "THE_IPU_STAGE/SLICE_3842"
+ COMP "THE_IPU_STAGE/SLICE_3843"
+ COMP "THE_IPU_STAGE/SLICE_3844"
+ COMP "THE_IPU_STAGE/SLICE_3845"
+ COMP "THE_IPU_STAGE/SLICE_3846"
+ COMP "THE_IPU_STAGE/SLICE_3847"
+ COMP "THE_IPU_STAGE/SLICE_3848"
+ COMP "THE_IPU_STAGE/SLICE_3849"
+ COMP "THE_IPU_STAGE/SLICE_3850"
+ COMP "THE_IPU_STAGE/SLICE_3851"
+ COMP "THE_IPU_STAGE/SLICE_3852"
+ COMP "THE_IPU_STAGE/SLICE_3853"
+ COMP "THE_IPU_STAGE/SLICE_3854"
+ COMP "THE_IPU_STAGE/SLICE_3855"
+ COMP "THE_IPU_STAGE/SLICE_3856"
+ COMP "THE_IPU_STAGE/SLICE_3857"
+ COMP "THE_IPU_STAGE/SLICE_3858"
+ COMP "THE_IPU_STAGE/SLICE_3859"
+ COMP "THE_IPU_STAGE/SLICE_3860"
+ COMP "THE_IPU_STAGE/SLICE_3861"
+ COMP "THE_IPU_STAGE/SLICE_3862"
+ COMP "THE_IPU_STAGE/SLICE_3863"
+ COMP "THE_IPU_STAGE/SLICE_3864"
+ COMP "THE_IPU_STAGE/SLICE_3865"
+ COMP "THE_IPU_STAGE/SLICE_3866"
+ COMP "THE_IPU_STAGE/SLICE_3867"
+ COMP "THE_IPU_STAGE/SLICE_3868"
+ COMP "THE_IPU_STAGE/SLICE_3869"
+ COMP "THE_IPU_STAGE/SLICE_3870"
+ COMP "THE_IPU_STAGE/SLICE_3871"
+ COMP "THE_IPU_STAGE/SLICE_3872"
+ COMP "THE_IPU_STAGE/SLICE_3873"
+ COMP "THE_IPU_STAGE/SLICE_3874"
+ COMP "THE_IPU_STAGE/SLICE_3875"
+ COMP "THE_IPU_STAGE/SLICE_3876"
+ COMP "THE_IPU_STAGE/SLICE_3877"
+ COMP "THE_IPU_STAGE/SLICE_3878"
+ COMP "THE_IPU_STAGE/SLICE_3879"
+ COMP "THE_IPU_STAGE/SLICE_3880"
+ COMP "THE_IPU_STAGE/SLICE_3881"
+ COMP "THE_IPU_STAGE/SLICE_3882"
+ COMP "THE_IPU_STAGE/SLICE_3883"
+ COMP "THE_IPU_STAGE/SLICE_3884"
+ COMP "THE_IPU_STAGE/SLICE_3885"
+ COMP "THE_IPU_STAGE/SLICE_3886"
+ COMP "THE_IPU_STAGE/SLICE_3887"
+ COMP "THE_IPU_STAGE/SLICE_3888"
+ COMP "THE_IPU_STAGE/SLICE_3889"
+ COMP "THE_IPU_STAGE/SLICE_3890"
+ COMP "THE_IPU_STAGE/SLICE_3891"
+ COMP "THE_IPU_STAGE/SLICE_3892"
+ COMP "THE_IPU_STAGE/SLICE_3893"
+ COMP "THE_IPU_STAGE/SLICE_3894"
+ COMP "THE_IPU_STAGE/SLICE_3895"
+ COMP "THE_IPU_STAGE/SLICE_3896"
+ COMP "THE_IPU_STAGE/SLICE_3897"
+ COMP "THE_IPU_STAGE/SLICE_3898"
+ COMP "THE_IPU_STAGE/SLICE_3899"
+ COMP "THE_IPU_STAGE/SLICE_3900"
+ COMP "THE_IPU_STAGE/SLICE_3901"
+ COMP "THE_IPU_STAGE/SLICE_3902"
+ COMP "THE_IPU_STAGE/SLICE_3903"
+ COMP "THE_IPU_STAGE/SLICE_3904"
+ COMP "THE_IPU_STAGE/SLICE_3905"
+ COMP "THE_IPU_STAGE/SLICE_3906"
+ COMP "THE_IPU_STAGE/SLICE_3907"
+ COMP "THE_IPU_STAGE/SLICE_3908"
+ COMP "THE_IPU_STAGE/SLICE_3909"
+ COMP "THE_IPU_STAGE/SLICE_3910"
+ COMP "THE_IPU_STAGE/SLICE_3911"
+ COMP "THE_IPU_STAGE/SLICE_3912"
+ COMP "THE_IPU_STAGE/SLICE_3913"
+ COMP "THE_IPU_STAGE/SLICE_3914"
+ COMP "THE_IPU_STAGE/SLICE_3915"
+ COMP "THE_IPU_STAGE/SLICE_3916"
+ COMP "THE_IPU_STAGE/SLICE_3917"
+ COMP "THE_IPU_STAGE/SLICE_3918"
+ COMP "THE_IPU_STAGE/SLICE_3919"
+ COMP "THE_IPU_STAGE/SLICE_3920"
+ COMP "THE_IPU_STAGE/SLICE_3921"
+ COMP "THE_IPU_STAGE/SLICE_3922"
+ COMP "THE_IPU_STAGE/SLICE_3923"
+ COMP "THE_IPU_STAGE/SLICE_3924"
+ COMP "THE_IPU_STAGE/SLICE_3925"
+ COMP "THE_IPU_STAGE/SLICE_3926"
+ COMP "THE_IPU_STAGE/SLICE_3927"
+ COMP "THE_IPU_STAGE/SLICE_3928"
+ COMP "THE_IPU_STAGE/SLICE_3929"
+ COMP "THE_IPU_STAGE/SLICE_3930"
+ COMP "THE_IPU_STAGE/SLICE_3931"
+ COMP "THE_IPU_STAGE/SLICE_3932"
+ COMP "THE_IPU_STAGE/SLICE_3933"
+ COMP "THE_IPU_STAGE/SLICE_3934"
+ COMP "THE_IPU_STAGE/SLICE_3935"
+ COMP "THE_IPU_STAGE/SLICE_3936"
+ COMP "THE_IPU_STAGE/SLICE_3937"
+ COMP "THE_IPU_STAGE/SLICE_3938"
+ COMP "THE_IPU_STAGE/SLICE_3939"
+ COMP "THE_IPU_STAGE/SLICE_3940"
+ COMP "THE_IPU_STAGE/SLICE_3941"
+ COMP "THE_IPU_STAGE/SLICE_3942"
+ COMP "THE_IPU_STAGE/SLICE_3943"
+ COMP "THE_IPU_STAGE/SLICE_3944"
+ COMP "THE_IPU_STAGE/SLICE_3945"
+ COMP "THE_IPU_STAGE/SLICE_3946"
+ COMP "THE_IPU_STAGE/SLICE_3947"
+ COMP "THE_IPU_STAGE/SLICE_3948"
+ COMP "THE_IPU_STAGE/SLICE_3949"
+ COMP "THE_IPU_STAGE/SLICE_3950"
+ COMP "THE_IPU_STAGE/SLICE_3951"
+ COMP "THE_IPU_STAGE/SLICE_3952"
+ COMP "THE_IPU_STAGE/SLICE_3953"
+ COMP "THE_IPU_STAGE/SLICE_3954"
+ COMP "THE_IPU_STAGE/SLICE_3955"
+ COMP "THE_IPU_STAGE/SLICE_3956"
+ COMP "THE_IPU_STAGE/SLICE_3957"
+ COMP "THE_IPU_STAGE/SLICE_3958"
+ COMP "THE_IPU_STAGE/SLICE_3959"
+ COMP "THE_IPU_STAGE/SLICE_3960"
+ COMP "THE_IPU_STAGE/SLICE_5118"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_5119"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_5120"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_5121"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_5122"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_5123"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_5124"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_5125"
+ COMP "THE_IPU_STAGE/SLICE_5126"
+ COMP "THE_IPU_STAGE/SLICE_5127"
+ COMP "THE_IPU_STAGE/SLICE_5128"
+ COMP "THE_IPU_STAGE/SLICE_5129"
+ COMP "THE_IPU_STAGE/SLICE_5130"
+ COMP "THE_IPU_STAGE/SLICE_5131"
+ COMP "THE_IPU_STAGE/SLICE_5132"
+ COMP "THE_IPU_STAGE/SLICE_5133"
+ COMP "THE_IPU_STAGE/SLICE_5134"
+ COMP "THE_IPU_STAGE/SLICE_5135"
+ COMP "THE_IPU_STAGE/SLICE_5136"
+ COMP "THE_IPU_STAGE/SLICE_5137"
+ COMP "THE_IPU_STAGE/SLICE_5138"
+ COMP "THE_IPU_STAGE/SLICE_5139"
+ COMP "THE_IPU_STAGE/SLICE_5140"
+ COMP "THE_IPU_STAGE/SLICE_5141"
+ COMP "THE_IPU_STAGE/SLICE_5142"
+ COMP "THE_IPU_STAGE/SLICE_5143"
+ COMP "THE_IPU_STAGE/SLICE_5144"
+ COMP "THE_IPU_STAGE/SLICE_5145"
+ COMP "THE_IPU_STAGE/SLICE_5146"
+ COMP "THE_IPU_STAGE/SLICE_5147"
+ COMP "THE_IPU_STAGE/SLICE_5148"
+ COMP "THE_IPU_STAGE/SLICE_5149"
+ COMP "THE_IPU_STAGE/SLICE_5150"
+ COMP "THE_IPU_STAGE/SLICE_5151"
+ COMP "THE_IPU_STAGE/SLICE_5152"
+ COMP "THE_IPU_STAGE/SLICE_5153"
+ COMP "THE_IPU_STAGE/SLICE_5154"
+ COMP "THE_IPU_STAGE/SLICE_5155"
+ COMP "THE_IPU_STAGE/SLICE_5156"
+ COMP "THE_IPU_STAGE/SLICE_5157"
+ COMP "THE_IPU_STAGE/SLICE_5158"
+ COMP "THE_IPU_STAGE/SLICE_5159"
+ COMP "THE_IPU_STAGE/SLICE_5160"
+ COMP "THE_IPU_STAGE/SLICE_5161"
+ COMP "THE_IPU_STAGE/SLICE_5162"
+ COMP "THE_IPU_STAGE/SLICE_5163"
+ COMP "THE_IPU_STAGE/SLICE_5164"
+ COMP "THE_IPU_STAGE/SLICE_5165"
+ COMP "THE_IPU_STAGE/SLICE_5166"
+ COMP "THE_IPU_STAGE/SLICE_5167"
+ COMP "THE_IPU_STAGE/SLICE_5168"
+ COMP "THE_IPU_STAGE/SLICE_5169"
+ COMP "THE_IPU_STAGE/SLICE_5170"
+ COMP "THE_IPU_STAGE/SLICE_5171"
+ COMP "THE_IPU_STAGE/SLICE_5172"
+ COMP "THE_IPU_STAGE/SLICE_5173"
+ COMP "THE_IPU_STAGE/SLICE_5174"
+ COMP "THE_IPU_STAGE/SLICE_5175"
+ COMP "THE_IPU_STAGE/SLICE_5176"
+ COMP "THE_IPU_STAGE/SLICE_5177"
+ COMP "THE_IPU_STAGE/SLICE_5178"
+ COMP "THE_IPU_STAGE/SLICE_5179"
+ COMP "THE_IPU_STAGE/SLICE_5180"
+ COMP "THE_IPU_STAGE/SLICE_5181"
+ COMP "THE_IPU_STAGE/SLICE_5182"
+ COMP "THE_IPU_STAGE/SLICE_5183"
+ COMP "THE_IPU_STAGE/SLICE_5184"
+ COMP "THE_IPU_STAGE/SLICE_5185"
+ COMP "THE_IPU_STAGE/SLICE_5186"
+ COMP "THE_IPU_STAGE/SLICE_5187"
+ COMP "THE_IPU_STAGE/SLICE_5188"
+ COMP "THE_IPU_STAGE/SLICE_5189"
+ COMP "THE_IPU_STAGE/SLICE_5190"
+ COMP "THE_IPU_STAGE/SLICE_5191"
+ COMP "THE_IPU_STAGE/SLICE_5192"
+ COMP "THE_IPU_STAGE/SLICE_5193"
+ COMP "THE_IPU_STAGE/SLICE_5194"
+ COMP "THE_IPU_STAGE/SLICE_5195"
+ COMP "THE_IPU_STAGE/SLICE_5196"
+ COMP "THE_IPU_STAGE/SLICE_5197"
+ COMP "THE_IPU_STAGE/SLICE_5198"
+ COMP "THE_IPU_STAGE/SLICE_5199"
+ COMP "THE_IPU_STAGE/SLICE_5200"
+ COMP "THE_IPU_STAGE/SLICE_5201"
+ COMP "THE_IPU_STAGE/SLICE_5202"
+ COMP "THE_IPU_STAGE/SLICE_5203"
+ COMP "THE_IPU_STAGE/SLICE_5204"
+ COMP "THE_IPU_STAGE/SLICE_5205"
+ COMP "THE_IPU_STAGE/SLICE_10783"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_10993"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_10994"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_10995"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_10996"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_10997"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_10998"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_10999"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_11000"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_11001"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_11002"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_11003"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_11004"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_11005"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_11006"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_11007"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_11008"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_11009"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_11010"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_11011"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_11012"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_11013"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_11014"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_11015"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_11016"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_11017"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_11018"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_11019"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_11020"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_11021"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_11022"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_11023"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_11024"
+ COMP "THE_IPU_STAGE/SLICE_11034"
+ COMP "THE_IPU_STAGE/SLICE_11035"
+ COMP "THE_IPU_STAGE/SLICE_11036"
+ COMP "THE_IPU_STAGE/SLICE_11037"
+ COMP "THE_IPU_STAGE/SLICE_11038"
+ COMP "THE_IPU_STAGE/SLICE_11039"
+ COMP "THE_IPU_STAGE/SLICE_11040"
+ COMP "THE_IPU_STAGE/SLICE_11041"
+ COMP "THE_IPU_STAGE/SLICE_11042"
+ COMP "THE_IPU_STAGE/SLICE_11043"
+ COMP "THE_IPU_STAGE/SLICE_11044"
+ COMP "THE_IPU_STAGE/SLICE_11045"
+ COMP "THE_IPU_STAGE/SLICE_11046"
+ COMP "THE_IPU_STAGE/SLICE_11047"
+ COMP "THE_IPU_STAGE/SLICE_11048"
+ COMP "THE_IPU_STAGE/SLICE_11049"
+ COMP "THE_IPU_STAGE/SLICE_11050"
+ COMP "THE_IPU_STAGE/SLICE_11051"
+ COMP "THE_IPU_STAGE/SLICE_11052"
+ COMP "THE_IPU_STAGE/SLICE_11053"
+ COMP "THE_IPU_STAGE/SLICE_11054"
+ COMP "THE_IPU_STAGE/SLICE_11055"
+ COMP "THE_IPU_STAGE/SLICE_11056"
+ COMP "THE_IPU_STAGE/SLICE_11057"
+ COMP "THE_IPU_STAGE/SLICE_11058"
+ COMP "THE_IPU_STAGE/SLICE_11067"
+ COMP "THE_IPU_STAGE/SLICE_11070"
+ COMP "THE_IPU_STAGE/SLICE_11071"
+ COMP "THE_IPU_STAGE/SLICE_11072"
+ COMP "THE_IPU_STAGE/SLICE_11073"
+ COMP "THE_IPU_STAGE/SLICE_11074"
+ COMP "THE_IPU_STAGE/SLICE_11075"
+ COMP "THE_IPU_STAGE/SLICE_11076"
+ COMP "THE_IPU_STAGE/SLICE_11077"
+ COMP "THE_IPU_STAGE/next_fifo_sel_m13_0/SLICE_11838"
+ COMP "THE_IPU_STAGE/next_fifo_last_m5/SLICE_11839"
+ COMP "THE_IPU_STAGE/next_fifo_sel_m13_1/SLICE_11840"
+ COMP "THE_IPU_STAGE/next_fifo_last_m8/SLICE_11841"
+ COMP "THE_IPU_STAGE/next_fifo_last_m11/SLICE_11842"
+ COMP "THE_IPU_STAGE/next_fifo_last_m14/SLICE_11843"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_11850"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_11851"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_11852"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_11853"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_11854"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_11855"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_11856"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_11857"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_11858"
+ COMP "THE_IPU_STAGE/SLICE_11859"
+ COMP "THE_IPU_STAGE/SLICE_11860"
+ COMP "THE_IPU_STAGE/SLICE_11861"
+ COMP "THE_IPU_STAGE/SLICE_11862"
+ COMP "THE_IPU_STAGE/SLICE_11863"
+ COMP "THE_IPU_STAGE/SLICE_11864"
+ COMP "THE_IPU_STAGE/SLICE_11865"
+ COMP "THE_IPU_STAGE/SLICE_11866"
+ COMP "THE_IPU_STAGE/SLICE_11867"
+ COMP "THE_IPU_STAGE/SLICE_11868"
+ COMP "THE_IPU_STAGE/SLICE_11869"
+ COMP "THE_IPU_STAGE/SLICE_11921"
+ COMP "THE_IPU_STAGE/SLICE_11922"
+ COMP "THE_IPU_STAGE/SLICE_11923"
+ COMP "THE_IPU_STAGE/SLICE_11924"
+ COMP "THE_IPU_STAGE/SLICE_11925"
+ COMP "THE_IPU_STAGE/SLICE_11926"
+ COMP "THE_IPU_STAGE/SLICE_11927"
+ COMP "THE_IPU_STAGE/SLICE_11928"
+ COMP "THE_IPU_STAGE/SLICE_11929"
+ COMP "THE_IPU_STAGE/SLICE_11930"
+ COMP "THE_IPU_STAGE/SLICE_11931"
+ COMP "THE_IPU_STAGE/SLICE_11932"
+ COMP "THE_IPU_STAGE/SLICE_11933"
+ COMP "THE_IPU_STAGE/SLICE_11934"
+ COMP "THE_IPU_STAGE/SLICE_11935"
+ COMP "THE_IPU_STAGE/SLICE_11936"
+ COMP "THE_IPU_STAGE/SLICE_11937"
+ COMP "THE_IPU_STAGE/SLICE_11938"
+ COMP "THE_IPU_STAGE/SLICE_11939"
+ COMP "THE_IPU_STAGE/SLICE_11940"
+ COMP "THE_IPU_STAGE/SLICE_11941"
+ COMP "THE_IPU_STAGE/SLICE_11942"
+ COMP "THE_IPU_STAGE/SLICE_11943"
+ COMP "THE_IPU_STAGE/SLICE_11944"
+ COMP "THE_IPU_STAGE/SLICE_11945"
+ COMP "THE_IPU_STAGE/SLICE_11946"
+ COMP "THE_IPU_STAGE/SLICE_11947"
+ COMP "THE_IPU_STAGE/SLICE_11948"
+ COMP "THE_IPU_STAGE/SLICE_11949"
+ COMP "THE_IPU_STAGE/SLICE_11950"
+ COMP "THE_IPU_STAGE/SLICE_11951"
+ COMP "THE_IPU_STAGE/SLICE_11952"
+ COMP "THE_IPU_STAGE/SLICE_11953"
+ COMP "THE_IPU_STAGE/SLICE_11954"
+ COMP "THE_IPU_STAGE/SLICE_11955"
+ COMP "THE_IPU_STAGE/SLICE_11956"
+ COMP "THE_IPU_STAGE/SLICE_11957"
+ COMP "THE_IPU_STAGE/SLICE_11958"
+ COMP "THE_IPU_STAGE/SLICE_11959"
+ COMP "THE_IPU_STAGE/SLICE_11960"
+ COMP "THE_IPU_STAGE/SLICE_11961"
+ COMP "THE_IPU_STAGE/SLICE_11962"
+ COMP "THE_IPU_STAGE/SLICE_11963"
+ COMP "THE_IPU_STAGE/SLICE_11964"
+ COMP "THE_IPU_STAGE/SLICE_11965"
+ COMP "THE_IPU_STAGE/SLICE_11966"
+ COMP "THE_IPU_STAGE/SLICE_11967"
+ COMP "THE_IPU_STAGE/SLICE_11968"
+ COMP "THE_IPU_STAGE/SLICE_11969"
+ COMP "THE_IPU_STAGE/SLICE_11970"
+ COMP "THE_IPU_STAGE/SLICE_11971"
+ COMP "THE_IPU_STAGE/SLICE_11972"
+ COMP "THE_IPU_STAGE/SLICE_11973"
+ COMP "THE_IPU_STAGE/SLICE_11974"
+ COMP "THE_IPU_STAGE/SLICE_11975"
+ COMP "THE_IPU_STAGE/SLICE_11976"
+ COMP "THE_IPU_STAGE/SLICE_11977"
+ COMP "THE_IPU_STAGE/SLICE_11978"
+ COMP "THE_IPU_STAGE/SLICE_11979"
+ COMP "THE_IPU_STAGE/SLICE_11980"
+ COMP "THE_IPU_STAGE/SLICE_11981"
+ COMP "THE_IPU_STAGE/SLICE_11982"
+ COMP "THE_IPU_STAGE/SLICE_11983"
+ COMP "THE_IPU_STAGE/SLICE_11984"
+ COMP "THE_IPU_STAGE/SLICE_11985"
+ COMP "THE_IPU_STAGE/SLICE_11986"
+ COMP "THE_IPU_STAGE/SLICE_11987"
+ COMP "THE_IPU_STAGE/SLICE_11988"
+ COMP "THE_IPU_STAGE/SLICE_11989"
+ COMP "THE_IPU_STAGE/SLICE_11990"
+ COMP "THE_IPU_STAGE/SLICE_12324"
+ COMP "THE_IPU_STAGE/SLICE_12325"
+ COMP "THE_IPU_STAGE/SLICE_12326"
+ COMP "THE_IPU_STAGE/SLICE_12327"
+ COMP "THE_IPU_STAGE/SLICE_12328"
+ COMP "THE_IPU_STAGE/SLICE_12329"
+ COMP "THE_IPU_STAGE/SLICE_12393"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12509"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12510"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12511"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12512"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12513"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12514"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12515"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12516"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12517"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12518"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12519"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12520"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12521"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12522"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12523"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12524"
+ COMP "THE_IPU_STAGE/SLICE_12543"
+ COMP "THE_IPU_STAGE/SLICE_12544"
+ COMP "THE_IPU_STAGE/SLICE_12601"
+ COMP "THE_IPU_STAGE/SLICE_12602"
+ COMP "THE_IPU_STAGE/SLICE_12603"
+ COMP "THE_IPU_STAGE/SLICE_12604"
+ COMP "THE_IPU_STAGE/SLICE_12605"
+ COMP "THE_IPU_STAGE/SLICE_12606"
+ COMP "THE_IPU_STAGE/SLICE_12607"
+ COMP "THE_IPU_STAGE/SLICE_12608"
+ COMP "THE_IPU_STAGE/SLICE_12609"
+ COMP "THE_IPU_STAGE/SLICE_12610"
+ COMP "THE_IPU_STAGE/SLICE_12611"
+ COMP "THE_IPU_STAGE/SLICE_12612"
+ COMP "THE_IPU_STAGE/SLICE_12613"
+ COMP "THE_IPU_STAGE/SLICE_12614"
+ COMP "THE_IPU_STAGE/SLICE_12615"
+ COMP "THE_IPU_STAGE/SLICE_12616"
+ COMP "THE_IPU_STAGE/SLICE_12617"
+ COMP "THE_IPU_STAGE/SLICE_12618"
+ COMP "THE_IPU_STAGE/SLICE_12619"
+ COMP "THE_IPU_STAGE/SLICE_12620"
+ COMP "THE_IPU_STAGE/SLICE_12621"
+ COMP "THE_IPU_STAGE/SLICE_12622"
+ COMP "THE_IPU_STAGE/SLICE_12709"
+ COMP "THE_IPU_STAGE/SLICE_12710"
+ COMP "THE_IPU_STAGE/SLICE_12711"
+ COMP "THE_IPU_STAGE/SLICE_12712"
+ COMP "THE_IPU_STAGE/SLICE_12713"
+ COMP "THE_IPU_STAGE/SLICE_12714"
+ COMP "THE_IPU_STAGE/SLICE_12715"
+ COMP "THE_IPU_STAGE/SLICE_12716"
+ COMP "THE_IPU_STAGE/SLICE_12717"
+ COMP "THE_IPU_STAGE/SLICE_12718"
+ COMP "THE_IPU_STAGE/SLICE_12719"
+ COMP "THE_IPU_STAGE/SLICE_12720"
+ COMP "THE_IPU_STAGE/SLICE_12721"
+ COMP "THE_IPU_STAGE/SLICE_12722"
+ COMP "THE_IPU_STAGE/SLICE_12723"
+ COMP "THE_IPU_STAGE/SLICE_12724"
+ COMP "THE_IPU_STAGE/SLICE_12725"
+ COMP "THE_IPU_STAGE/SLICE_12726"
+ COMP "THE_IPU_STAGE/SLICE_12727"
+ COMP "THE_IPU_STAGE/SLICE_12728"
+ COMP "THE_IPU_STAGE/SLICE_12729"
+ COMP "THE_IPU_STAGE/SLICE_12730"
+ COMP "THE_IPU_STAGE/SLICE_12731"
+ COMP "THE_IPU_STAGE/SLICE_12732"
+ COMP "THE_IPU_STAGE/SLICE_12733"
+ COMP "THE_IPU_STAGE/SLICE_12734"
+ COMP "THE_IPU_STAGE/SLICE_12735"
+ COMP "THE_IPU_STAGE/SLICE_12736"
+ COMP "THE_IPU_STAGE/SLICE_12737"
+ COMP "THE_IPU_STAGE/SLICE_12738"
+ COMP "THE_IPU_STAGE/SLICE_12739"
+ COMP "THE_IPU_STAGE/SLICE_12740"
+ COMP "THE_IPU_STAGE/SLICE_12741"
+ COMP "THE_IPU_STAGE/SLICE_12742"
+ COMP "THE_IPU_STAGE/SLICE_12743"
+ COMP "THE_IPU_STAGE/SLICE_12744"
+ COMP "THE_IPU_STAGE/SLICE_12745"
+ COMP "THE_IPU_STAGE/SLICE_12746"
+ COMP "THE_IPU_STAGE/SLICE_12747"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_12749"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_12750"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_12751"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_12752"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_12753"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_12754"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_12755"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_12756"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_12757"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_12758"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_12759"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_12760"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_12761"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_12762"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_12763"
+ COMP "THE_IPU_STAGE/SLICE_12830"
+ COMP "THE_IPU_STAGE/SLICE_12831"
+ COMP "THE_IPU_STAGE/SLICE_12832"
+ COMP "THE_IPU_STAGE/SLICE_12833"
+ COMP "THE_IPU_STAGE/SLICE_12834"
+ COMP "THE_IPU_STAGE/SLICE_12835"
+ COMP "THE_IPU_STAGE/SLICE_12836"
+ COMP "THE_IPU_STAGE/SLICE_12837"
+ COMP "THE_IPU_STAGE/SLICE_12861"
+ COMP "THE_IPU_STAGE/SLICE_12862"
+ COMP "THE_IPU_STAGE/SLICE_12863"
+ COMP "THE_IPU_STAGE/SLICE_12864"
+ COMP "THE_IPU_STAGE/SLICE_12865"
+ COMP "THE_IPU_STAGE/SLICE_12866"
+ COMP "THE_IPU_STAGE/SLICE_12867"
+ COMP "THE_IPU_STAGE/SLICE_12868"
+ COMP "THE_IPU_STAGE/SLICE_12869"
+ COMP "THE_IPU_STAGE/SLICE_12870"
+ COMP "THE_IPU_STAGE/SLICE_12874"
+ COMP "THE_IPU_STAGE/SLICE_12875"
+ COMP "THE_IPU_STAGE/SLICE_12876"
+ COMP "THE_IPU_STAGE/SLICE_12877"
+ COMP "THE_IPU_STAGE/SLICE_12878"
+ COMP "THE_IPU_STAGE/SLICE_12879"
+ COMP "THE_IPU_STAGE/SLICE_12880"
+ COMP "THE_IPU_STAGE/SLICE_12909"
+ COMP "THE_IPU_STAGE/SLICE_12910"
+ COMP "THE_IPU_STAGE/SLICE_12911"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_12925"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_12926"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_12927"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_12928"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_12929"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_12930"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_12931"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_12932"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_12933"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_12934"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_12935"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_12936"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_12937"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_12938"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_12939"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_12940"
+ COMP "THE_IPU_STAGE/SLICE_12957"
+ COMP "THE_IPU_STAGE/SLICE_12958"
+ COMP "THE_IPU_STAGE/SLICE_12959"
+ COMP "THE_IPU_STAGE/SLICE_12960"
+ COMP "THE_IPU_STAGE/SLICE_12961"
+ COMP "THE_IPU_STAGE/SLICE_12962"
+ COMP "THE_IPU_STAGE/SLICE_12963"
+ COMP "THE_IPU_STAGE/SLICE_12964"
+ COMP "THE_IPU_STAGE/SLICE_12965"
+ COMP "THE_IPU_STAGE/SLICE_12966"
+ COMP "THE_IPU_STAGE/SLICE_12967"
+ COMP "THE_IPU_STAGE/SLICE_12968"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_13778"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_13779"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_13780"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_13781"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_13782"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_13783"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_13784"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_13785"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_13786"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_13787"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_13788"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_13789"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_13790"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_13791"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_13792"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_13793"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_13794"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_13795"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_13796"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_13797"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_13798"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_13799"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_13800"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_13801"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_13802"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_13803"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_13804"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_13805"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_13806"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_13807"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_13808"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_13809"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_13810"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_13811"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_13812"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_13813"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_13814"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_13815"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_13816"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_13817"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_13818"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_13819"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_13820"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_13821"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_13822"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_13823"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_13824"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_13825"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_13826"
+ COMP "THE_IPU_STAGE/SLICE_13827"
+ COMP "THE_IPU_STAGE/SLICE_13828"
+ COMP "THE_IPU_STAGE/SLICE_13829"
+ COMP "THE_IPU_STAGE/SLICE_13830"
+ COMP "THE_IPU_STAGE/SLICE_13831"
+ COMP "THE_IPU_STAGE/SLICE_13832"
+ COMP "THE_IPU_STAGE/SLICE_13833"
+ COMP "THE_IPU_STAGE/SLICE_13834"
+ COMP "THE_IPU_STAGE/SLICE_13835"
+ COMP "THE_IPU_STAGE/SLICE_13836"
+ COMP "THE_IPU_STAGE/SLICE_13837"
+ COMP "THE_IPU_STAGE/SLICE_13838"
+ COMP "THE_IPU_STAGE/SLICE_13839"
+ COMP "THE_IPU_STAGE/SLICE_13840"
+ COMP "THE_IPU_STAGE/SLICE_13841"
+ COMP "THE_IPU_STAGE/SLICE_13842"
+ COMP "THE_IPU_STAGE/SLICE_13843"
+ COMP "THE_IPU_STAGE/SLICE_13844"
+ COMP "THE_IPU_STAGE/SLICE_13845"
+ COMP "THE_IPU_STAGE/SLICE_13846"
+ COMP "THE_IPU_STAGE/SLICE_13847"
+ COMP "THE_IPU_STAGE/SLICE_13848"
+ COMP "THE_IPU_STAGE/SLICE_13849"
+ COMP "THE_IPU_STAGE/SLICE_13850"
+ COMP "THE_IPU_STAGE/SLICE_13851"
+ COMP "THE_IPU_STAGE/SLICE_13852"
+ COMP "THE_IPU_STAGE/SLICE_13853"
+ COMP "THE_IPU_STAGE/SLICE_13854"
+ COMP "THE_IPU_STAGE/SLICE_13855"
+ COMP "THE_IPU_STAGE/SLICE_13856"
+ COMP "THE_IPU_STAGE/SLICE_13857"
+ COMP "THE_IPU_STAGE/SLICE_13858"
+ COMP "THE_IPU_STAGE/SLICE_13859"
+ COMP "THE_IPU_STAGE/SLICE_13860"
+ COMP "THE_IPU_STAGE/SLICE_13861"
+ COMP "THE_IPU_STAGE/SLICE_13862"
+ COMP "THE_IPU_STAGE/SLICE_13863"
+ COMP "THE_IPU_STAGE/SLICE_13864"
+ COMP "THE_IPU_STAGE/SLICE_13865"
+ COMP "THE_IPU_STAGE/SLICE_13866"
+ COMP "THE_IPU_STAGE/SLICE_13867"
+ COMP "THE_IPU_STAGE/SLICE_13868"
+ COMP "THE_IPU_STAGE/SLICE_13869"
+ COMP "THE_IPU_STAGE/SLICE_13870"
+ COMP "THE_IPU_STAGE/SLICE_13871"
+ COMP "THE_IPU_STAGE/SLICE_13872"
+ COMP "THE_IPU_STAGE/SLICE_13873"
+ COMP "THE_IPU_STAGE/SLICE_13874"
+ COMP "THE_IPU_STAGE/SLICE_13875"
+ COMP "THE_IPU_STAGE/SLICE_13876"
+ COMP "THE_IPU_STAGE/SLICE_13877"
+ COMP "THE_IPU_STAGE/SLICE_13878"
+ COMP "THE_IPU_STAGE/SLICE_13879"
+ COMP "THE_IPU_STAGE/SLICE_13880"
+ COMP "THE_IPU_STAGE/SLICE_13881"
+ COMP "THE_IPU_STAGE/SLICE_13882"
+ COMP "THE_IPU_STAGE/SLICE_13883"
+ COMP "THE_IPU_STAGE/SLICE_13884"
+ COMP "THE_IPU_STAGE/SLICE_13885"
+ COMP "THE_IPU_STAGE/SLICE_13886"
+ COMP "THE_IPU_STAGE/SLICE_13887"
+ COMP "THE_IPU_STAGE/SLICE_13888"
+ COMP "THE_IPU_STAGE/SLICE_13889"
+ COMP "THE_IPU_STAGE/SLICE_13890"
+ COMP "THE_IPU_STAGE/SLICE_13891"
+ COMP "THE_IPU_STAGE/SLICE_13892"
+ COMP "THE_IPU_STAGE/SLICE_13893"
+ COMP "THE_IPU_STAGE/SLICE_13894"
+ COMP "THE_IPU_STAGE/SLICE_13895"
+ COMP "THE_IPU_STAGE/SLICE_13896"
+ COMP "THE_IPU_STAGE/SLICE_13897"
+ COMP "THE_IPU_STAGE/SLICE_13898"
+ COMP "THE_IPU_STAGE/SLICE_13899"
+ COMP "THE_IPU_STAGE/SLICE_13900"
+ COMP "THE_IPU_STAGE/SLICE_13901"
+ COMP "THE_IPU_STAGE/SLICE_13902"
+ COMP "THE_IPU_STAGE/SLICE_13903"
+ COMP "THE_IPU_STAGE/SLICE_13904"
+ COMP "THE_IPU_STAGE/SLICE_13905"
+ COMP "THE_IPU_STAGE/SLICE_13906"
+ COMP "THE_IPU_STAGE/SLICE_13907"
+ COMP "THE_IPU_STAGE/SLICE_13908"
+ COMP "THE_IPU_STAGE/SLICE_13909"
+ COMP "THE_IPU_STAGE/SLICE_13910"
+ COMP "THE_IPU_STAGE/SLICE_13911"
+ COMP "THE_IPU_STAGE/SLICE_13912"
+ COMP "THE_IPU_STAGE/SLICE_13913"
+ COMP "THE_IPU_STAGE/SLICE_13914"
+ COMP "THE_IPU_STAGE/SLICE_13915"
+ COMP "THE_IPU_STAGE/SLICE_13916"
+ COMP "THE_IPU_STAGE/SLICE_13917"
+ COMP "THE_IPU_STAGE/SLICE_13918"
+ COMP "THE_IPU_STAGE/SLICE_13919"
+ COMP "THE_IPU_STAGE/SLICE_13920"
+ COMP "THE_IPU_STAGE/SLICE_13921"
+ COMP "THE_IPU_STAGE/SLICE_13922"
+ COMP "THE_IPU_STAGE/SLICE_13923"
+ COMP "THE_IPU_STAGE/SLICE_13924"
+ COMP "THE_IPU_STAGE/SLICE_13925"
+ COMP "THE_IPU_STAGE/SLICE_13926"
+ COMP "THE_IPU_STAGE/SLICE_13927"
+ COMP "THE_IPU_STAGE/SLICE_13928"
+ COMP "THE_IPU_STAGE/SLICE_13929"
+ COMP "THE_IPU_STAGE/SLICE_13930"
+ COMP "THE_IPU_STAGE/SLICE_13931"
+ COMP "THE_IPU_STAGE/SLICE_13932"
+ COMP "THE_IPU_STAGE/SLICE_13933"
+ COMP "THE_IPU_STAGE/SLICE_13934"
+ COMP "THE_IPU_STAGE/SLICE_13935"
+ COMP "THE_IPU_STAGE/SLICE_13936"
+ COMP "THE_IPU_STAGE/SLICE_13937"
+ COMP "THE_IPU_STAGE/SLICE_13938"
+ COMP "THE_IPU_STAGE/SLICE_13939"
+ COMP "THE_IPU_STAGE/SLICE_13940"
+ COMP "THE_IPU_STAGE/SLICE_13941"
+ COMP "THE_IPU_STAGE/SLICE_13942"
+ COMP "THE_IPU_STAGE/SLICE_13943"
+ COMP "THE_IPU_STAGE/SLICE_13944"
+ COMP "THE_IPU_STAGE/SLICE_13945"
+ COMP "THE_IPU_STAGE/SLICE_13946"
+ COMP "THE_IPU_STAGE/SLICE_13947"
+ COMP "THE_IPU_STAGE/SLICE_13948"
+ COMP "THE_IPU_STAGE/SLICE_13949"
+ COMP "THE_IPU_STAGE/SLICE_13950"
+ COMP "THE_IPU_STAGE/SLICE_13951"
+ COMP "THE_IPU_STAGE/SLICE_13952"
+ COMP "THE_IPU_STAGE/SLICE_13953"
+ COMP "THE_IPU_STAGE/SLICE_13954"
+ COMP "THE_IPU_STAGE/SLICE_13955"
+ COMP "THE_IPU_STAGE/SLICE_13956"
+ COMP "THE_IPU_STAGE/SLICE_13957"
+ COMP "THE_IPU_STAGE/SLICE_13958"
+ COMP "THE_IPU_STAGE/SLICE_13959"
+ COMP "THE_IPU_STAGE/SLICE_13960"
+ COMP "THE_IPU_STAGE/SLICE_13961"
+ COMP "THE_IPU_STAGE/SLICE_13962"
+ COMP "THE_IPU_STAGE/SLICE_13963"
+ COMP "THE_IPU_STAGE/SLICE_13964"
+ COMP "THE_IPU_STAGE/SLICE_13965"
+ COMP "THE_IPU_STAGE/SLICE_13966"
+ COMP "THE_IPU_STAGE/SLICE_13967"
+ COMP "THE_IPU_STAGE/SLICE_13968"
+ COMP "THE_IPU_STAGE/SLICE_13969"
+ COMP "THE_IPU_STAGE/SLICE_13970"
+ COMP "THE_IPU_STAGE/SLICE_13971"
+ COMP "THE_IPU_STAGE/SLICE_13972"
+ COMP "THE_IPU_STAGE/SLICE_13973"
+ COMP "THE_IPU_STAGE/SLICE_13974"
+ COMP "THE_IPU_STAGE/SLICE_13975"
+ COMP "THE_IPU_STAGE/SLICE_13976"
+ COMP "THE_IPU_STAGE/SLICE_13977"
+ COMP "THE_IPU_STAGE/SLICE_13978"
+ COMP "THE_IPU_STAGE/SLICE_13979"
+ COMP "THE_IPU_STAGE/SLICE_13980"
+ COMP "THE_IPU_STAGE/SLICE_13981"
+ COMP "THE_IPU_STAGE/SLICE_13982"
+ COMP "THE_IPU_STAGE/SLICE_13983"
+ COMP "THE_IPU_STAGE/SLICE_13984"
+ COMP "THE_IPU_STAGE/SLICE_13985"
+ COMP "THE_IPU_STAGE/SLICE_13986"
+ COMP "THE_IPU_STAGE/SLICE_13987"
+ COMP "THE_IPU_STAGE/SLICE_13988"
+ COMP "THE_IPU_STAGE/SLICE_13989"
+ COMP "THE_IPU_STAGE/SLICE_13990"
+ COMP "THE_IPU_STAGE/SLICE_13991"
+ COMP "THE_IPU_STAGE/SLICE_13992"
+ COMP "THE_IPU_STAGE/SLICE_13993"
+ COMP "THE_IPU_STAGE/SLICE_13994"
+ COMP "THE_IPU_STAGE/SLICE_13995"
+ COMP "THE_IPU_STAGE/SLICE_13996"
+ COMP "THE_IPU_STAGE/SLICE_13997"
+ COMP "THE_IPU_STAGE/SLICE_13998"
+ COMP "THE_IPU_STAGE/SLICE_13999"
+ COMP "THE_IPU_STAGE/SLICE_14000"
+ COMP "THE_IPU_STAGE/SLICE_14001"
+ COMP "THE_IPU_STAGE/SLICE_14002"
+ COMP "THE_IPU_STAGE/SLICE_14003"
+ COMP "THE_IPU_STAGE/SLICE_14004"
+ COMP "THE_IPU_STAGE/SLICE_14005"
+ COMP "THE_IPU_STAGE/SLICE_14006"
+ COMP "THE_IPU_STAGE/SLICE_14007"
+ COMP "THE_IPU_STAGE/SLICE_14008"
+ COMP "THE_IPU_STAGE/SLICE_14009"
+ COMP "THE_IPU_STAGE/SLICE_14010"
+ COMP "THE_IPU_STAGE/SLICE_14011"
+ COMP "THE_IPU_STAGE/SLICE_14012"
+ COMP "THE_IPU_STAGE/SLICE_14013"
+ COMP "THE_IPU_STAGE/SLICE_14014"
+ COMP "THE_IPU_STAGE/SLICE_14015"
+ COMP "THE_IPU_STAGE/SLICE_14016"
+ COMP "THE_IPU_STAGE/SLICE_14017"
+ COMP "THE_IPU_STAGE/SLICE_14018"
+ COMP "THE_IPU_STAGE/SLICE_14019"
+ COMP "THE_IPU_STAGE/SLICE_14020"
+ COMP "THE_IPU_STAGE/SLICE_14021"
+ COMP "THE_IPU_STAGE/SLICE_14022"
+ COMP "THE_IPU_STAGE/SLICE_14023"
+ COMP "THE_IPU_STAGE/SLICE_14024"
+ COMP "THE_IPU_STAGE/SLICE_14025"
+ COMP "THE_IPU_STAGE/SLICE_14026"
+ COMP "THE_IPU_STAGE/SLICE_14027"
+ COMP "THE_IPU_STAGE/SLICE_14028"
+ COMP "THE_IPU_STAGE/SLICE_14029"
+ COMP "THE_IPU_STAGE/SLICE_14030"
+ COMP "THE_IPU_STAGE/SLICE_14031"
+ COMP "THE_IPU_STAGE/SLICE_14032"
+ COMP "THE_IPU_STAGE/SLICE_14033"
+ COMP "THE_IPU_STAGE/SLICE_14034"
+ COMP "THE_IPU_STAGE/SLICE_14035"
+ COMP "THE_IPU_STAGE/SLICE_14036"
+ COMP "THE_IPU_STAGE/SLICE_14037"
+ COMP "THE_IPU_STAGE/SLICE_14038"
+ COMP "THE_IPU_STAGE/SLICE_14039"
+ COMP "THE_IPU_STAGE/SLICE_14040"
+ COMP "THE_IPU_STAGE/SLICE_14041"
+ COMP "THE_IPU_STAGE/SLICE_14042"
+ COMP "THE_IPU_STAGE/SLICE_14043"
+ COMP "THE_IPU_STAGE/SLICE_14044"
+ COMP "THE_IPU_STAGE/SLICE_14045"
+ COMP "THE_IPU_STAGE/SLICE_14046"
+ COMP "THE_IPU_STAGE/SLICE_14047"
+ COMP "THE_IPU_STAGE/SLICE_14048"
+ COMP "THE_IPU_STAGE/SLICE_14049"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_14078"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_14079"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_14080"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_14081"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_14082"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_14083"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_14084"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_14085"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_14086"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_14087"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_14088"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_14089"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_14090"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_14091"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_14092"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_14093"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1";
+REGION "ADC0_REGION" "R59C2" 46 4 DEVSIZE;
+PGROUP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4512"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4513"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4514"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4515"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4516"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4517"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4518"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4519"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4520"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4521"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4522"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4523"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4524"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4525"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4526"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4527"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4528"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4529"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4530"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4531"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4532"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4533"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4534"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4535"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4536"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4537"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4538"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4539"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4540"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4541"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4542"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4619"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4620"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4621"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4622"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4623"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4624"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4625"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4626"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4627"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4628"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4629"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4630"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4631"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4668";
+LOCATE PGROUP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;
+PGROUP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4543"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4544"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4545"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4546"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4547"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4548"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4549"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4550"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4551"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4552"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4553"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4554"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4555"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4556"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4557"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4558"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4559"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4560"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4561"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4562"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4563"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4564"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4565"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4566"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4632"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4633"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4634"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4635"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4636"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4637"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4638"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4639"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4640"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4641"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4642"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4643"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4693"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4694";
+LOCATE PGROUP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;
+PGROUP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4567"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4568"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4569"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4570"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4571"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4572"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4573"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4574"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4575"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4576"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4577"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4578"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4579"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4580"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4581"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4582"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4583"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4584"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4585"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4586"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4587"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4588"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4589"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4590"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4644"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4645"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4646"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4647"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4648"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4649"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4650"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4651"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4652"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4653"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4654"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4655";
+LOCATE PGROUP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;
+PGROUP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4591"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4592"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4593"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4594"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4595"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4596"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4597"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4598"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4599"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4600"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4601"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4602"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4603"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4604"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4605"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4606"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4607"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4608"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4609"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4610"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4611"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4612"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4613"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4614"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4656"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4657"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4658"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4659"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4660"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4661"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4662"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4663"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4664"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4665"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4666"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4667"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4669";
+LOCATE PGROUP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;
+PGROUP "THE_ADC0_HANDLER/ADC_DATA_HANDLER_group"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4615"
+ COMP "THE_ADC0_HANDLER/SLICE_4617"
+ COMP "THE_ADC0_HANDLER/SLICE_4618"
+ COMP "THE_ADC0_HANDLER/SLICE_4670"
+ COMP "THE_ADC0_HANDLER/SLICE_4671"
+ COMP "THE_ADC0_HANDLER/SLICE_4672"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4673"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4674"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4675"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4676"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4677"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4678"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4679"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4680"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4681"
+ COMP "THE_ADC0_HANDLER/SLICE_4683"
+ COMP "THE_ADC0_HANDLER/SLICE_4684"
+ COMP "THE_ADC0_HANDLER/SLICE_4685"
+ COMP "THE_ADC0_HANDLER/SLICE_4686"
+ COMP "THE_ADC0_HANDLER/SLICE_4687"
+ COMP "THE_ADC0_HANDLER/SLICE_4688"
+ COMP "THE_ADC0_HANDLER/SLICE_4689"
+ COMP "THE_ADC0_HANDLER/SLICE_4690"
+ COMP "THE_ADC0_HANDLER/SLICE_4691"
+ COMP "THE_ADC0_HANDLER/SLICE_4692"
+ COMP "THE_ADC0_HANDLER/SLICE_10479"
+ COMP "THE_ADC0_HANDLER/SLICE_10492"
+ COMP "THE_ADC0_HANDLER/SLICE_10527"
+ COMP "THE_ADC0_HANDLER/SLICE_10528"
+ COMP "THE_ADC0_HANDLER/SLICE_10529"
+ COMP "THE_ADC0_HANDLER/SLICE_10530"
+ COMP "THE_ADC0_HANDLER/SLICE_10531"
+ COMP "THE_ADC0_HANDLER/SLICE_10532"
+ COMP "THE_ADC0_HANDLER/SLICE_10569"
+ COMP "THE_ADC0_HANDLER/SLICE_10570"
+ COMP "THE_ADC0_HANDLER/SLICE_10571"
+ COMP "THE_ADC0_HANDLER/SLICE_10572"
+ COMP "THE_ADC0_HANDLER/SLICE_10573"
+ COMP "THE_ADC0_HANDLER/SLICE_10574"
+ COMP "THE_ADC0_HANDLER/SLICE_10575"
+ COMP "THE_ADC0_HANDLER/SLICE_10576"
+ COMP "THE_ADC0_HANDLER/SLICE_10577"
+ COMP "THE_ADC0_HANDLER/SLICE_10578"
+ COMP "THE_ADC0_HANDLER/SLICE_10579"
+ COMP "THE_ADC0_HANDLER/SLICE_10580"
+ COMP "THE_ADC0_HANDLER/SLICE_10581"
+ COMP "THE_ADC0_HANDLER/SLICE_10582"
+ COMP "THE_ADC0_HANDLER/SLICE_10583"
+ COMP "THE_ADC0_HANDLER/SLICE_10584"
+ COMP "THE_ADC0_HANDLER/SLICE_10585"
+ COMP "THE_ADC0_HANDLER/SLICE_10586"
+ COMP "THE_ADC0_HANDLER/SLICE_10587"
+ COMP "THE_ADC0_HANDLER/SLICE_10588"
+ COMP "THE_ADC0_HANDLER/SLICE_10589"
+ COMP "THE_ADC0_HANDLER/SLICE_10590"
+ COMP "THE_ADC0_HANDLER/SLICE_10591"
+ COMP "THE_ADC0_HANDLER/SLICE_10592"
+ COMP "THE_ADC0_HANDLER/SLICE_10593"
+ COMP "THE_ADC0_HANDLER/SLICE_10594"
+ COMP "THE_ADC0_HANDLER/SLICE_10595"
+ COMP "THE_ADC0_HANDLER/SLICE_10596"
+ COMP "THE_ADC0_HANDLER/SLICE_10597"
+ COMP "THE_ADC0_HANDLER/SLICE_10598"
+ COMP "THE_ADC0_HANDLER/SLICE_10599"
+ COMP "THE_ADC0_HANDLER/SLICE_10600"
+ COMP "THE_ADC0_HANDLER/SLICE_10601"
+ COMP "THE_ADC0_HANDLER/SLICE_10602"
+ COMP "THE_ADC0_HANDLER/SLICE_10603"
+ COMP "THE_ADC0_HANDLER/SLICE_10604"
+ COMP "THE_ADC0_HANDLER/SLICE_10605"
+ COMP "THE_ADC0_HANDLER/SLICE_10606"
+ COMP "THE_ADC0_HANDLER/SLICE_10607"
+ COMP "THE_ADC0_HANDLER/SLICE_10608"
+ COMP "THE_ADC0_HANDLER/SLICE_10609"
+ COMP "THE_ADC0_HANDLER/SLICE_10610"
+ COMP "THE_ADC0_HANDLER/SLICE_13384"
+ COMP "THE_ADC0_HANDLER/SLICE_13385";
+REGION "ADC1_REGION" "R9C2" 49 4 DEVSIZE;
+PGROUP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4720"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4721"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4722"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4723"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4724"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4725"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4726"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4727"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4728"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4729"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4730"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4731"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4732"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4733"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4734"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4735"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4736"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4737"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4738"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4739"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4740"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4741"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4742"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4743"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4744"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4745"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4746"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4747"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4748"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4749"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4750"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4827"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4828"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4829"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4830"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4831"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4832"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4833"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4834"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4835"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4836"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4837"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4838"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4839"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4876";
+LOCATE PGROUP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;
+PGROUP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4751"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4752"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4753"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4754"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4755"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4756"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4757"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4758"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4759"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4760"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4761"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4762"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4763"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4764"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4765"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4766"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4767"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4768"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4769"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4770"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4771"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4772"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4773"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4774"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4840"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4841"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4842"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4843"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4844"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4845"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4846"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4847"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4848"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4849"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4850"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4851"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4891"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4892";
+LOCATE PGROUP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;
+PGROUP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4775"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4776"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4777"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4778"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4779"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4780"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4781"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4782"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4783"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4784"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4785"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4786"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4787"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4788"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4789"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4790"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4791"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4792"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4793"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4794"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4795"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4796"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4797"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4798"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4852"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4853"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4854"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4855"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4856"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4857"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4858"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4859"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4860"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4861"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4862"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4863";
+LOCATE PGROUP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;
+PGROUP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4799"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4800"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4801"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4802"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4803"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4804"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4805"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4806"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4807"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4808"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4809"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4810"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4811"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4812"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4813"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4814"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4815"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4816"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4817"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4818"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4819"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4820"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4821"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4822"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4864"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4865"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4866"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4867"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4868"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4869"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4870"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4871"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4872"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4873"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4874"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4875"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4877";
+LOCATE PGROUP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;
+PGROUP "THE_ADC1_HANDLER/ADC_DATA_HANDLER_group"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4823"
+ COMP "THE_ADC1_HANDLER/SLICE_4825"
+ COMP "THE_ADC1_HANDLER/SLICE_4826"
+ COMP "THE_ADC1_HANDLER/SLICE_4878"
+ COMP "THE_ADC1_HANDLER/SLICE_4879"
+ COMP "THE_ADC1_HANDLER/SLICE_4880"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4881"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4882"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4883"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4884"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4885"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4886"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4887"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4888"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4889"
+ COMP "THE_ADC1_HANDLER/SLICE_4893"
+ COMP "THE_ADC1_HANDLER/SLICE_4894"
+ COMP "THE_ADC1_HANDLER/SLICE_4895"
+ COMP "THE_ADC1_HANDLER/SLICE_4896"
+ COMP "THE_ADC1_HANDLER/SLICE_4897"
+ COMP "THE_ADC1_HANDLER/SLICE_4898"
+ COMP "THE_ADC1_HANDLER/SLICE_4899"
+ COMP "THE_ADC1_HANDLER/SLICE_4900"
+ COMP "THE_ADC1_HANDLER/SLICE_4901"
+ COMP "THE_ADC1_HANDLER/SLICE_4902"
+ COMP "THE_ADC1_HANDLER/SLICE_10497"
+ COMP "THE_ADC1_HANDLER/SLICE_10510"
+ COMP "THE_ADC1_HANDLER/SLICE_10533"
+ COMP "THE_ADC1_HANDLER/SLICE_10534"
+ COMP "THE_ADC1_HANDLER/SLICE_10535"
+ COMP "THE_ADC1_HANDLER/SLICE_10536"
+ COMP "THE_ADC1_HANDLER/SLICE_10537"
+ COMP "THE_ADC1_HANDLER/SLICE_10538"
+ COMP "THE_ADC1_HANDLER/SLICE_10539"
+ COMP "THE_ADC1_HANDLER/SLICE_10540"
+ COMP "THE_ADC1_HANDLER/SLICE_10541"
+ COMP "THE_ADC1_HANDLER/SLICE_10542"
+ COMP "THE_ADC1_HANDLER/SLICE_10543"
+ COMP "THE_ADC1_HANDLER/SLICE_10544"
+ COMP "THE_ADC1_HANDLER/SLICE_10545"
+ COMP "THE_ADC1_HANDLER/SLICE_10546"
+ COMP "THE_ADC1_HANDLER/SLICE_10547"
+ COMP "THE_ADC1_HANDLER/SLICE_10548"
+ COMP "THE_ADC1_HANDLER/SLICE_10549"
+ COMP "THE_ADC1_HANDLER/SLICE_10550"
+ COMP "THE_ADC1_HANDLER/SLICE_10551"
+ COMP "THE_ADC1_HANDLER/SLICE_10552"
+ COMP "THE_ADC1_HANDLER/SLICE_10553"
+ COMP "THE_ADC1_HANDLER/SLICE_10554"
+ COMP "THE_ADC1_HANDLER/SLICE_10555"
+ COMP "THE_ADC1_HANDLER/SLICE_10556"
+ COMP "THE_ADC1_HANDLER/SLICE_10557"
+ COMP "THE_ADC1_HANDLER/SLICE_10558"
+ COMP "THE_ADC1_HANDLER/SLICE_10559"
+ COMP "THE_ADC1_HANDLER/SLICE_10560"
+ COMP "THE_ADC1_HANDLER/SLICE_10561"
+ COMP "THE_ADC1_HANDLER/SLICE_10562"
+ COMP "THE_ADC1_HANDLER/SLICE_10563"
+ COMP "THE_ADC1_HANDLER/SLICE_10564"
+ COMP "THE_ADC1_HANDLER/SLICE_10565"
+ COMP "THE_ADC1_HANDLER/SLICE_10566"
+ COMP "THE_ADC1_HANDLER/SLICE_10567"
+ COMP "THE_ADC1_HANDLER/SLICE_10568"
+ COMP "THE_ADC1_HANDLER/SLICE_10611"
+ COMP "THE_ADC1_HANDLER/SLICE_10612"
+ COMP "THE_ADC1_HANDLER/SLICE_10613"
+ COMP "THE_ADC1_HANDLER/SLICE_10614"
+ COMP "THE_ADC1_HANDLER/SLICE_10615"
+ COMP "THE_ADC1_HANDLER/SLICE_10616"
+ COMP "THE_ADC1_HANDLER/SLICE_10617"
+ COMP "THE_ADC1_HANDLER/SLICE_10618"
+ COMP "THE_ADC1_HANDLER/SLICE_10619"
+ COMP "THE_ADC1_HANDLER/SLICE_10620"
+ COMP "THE_ADC1_HANDLER/SLICE_10621"
+ COMP "THE_ADC1_HANDLER/SLICE_10622"
+ COMP "THE_ADC1_HANDLER/SLICE_13388"
+ COMP "THE_ADC1_HANDLER/SLICE_13389";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8229"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8230"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8231"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8240"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8241"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8242"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8243"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8244"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8245"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8246"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8247"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8248"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8249"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8250"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8251"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8252"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8253"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8254"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8255"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8256"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8257"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8258"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8259"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8260"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8261"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8262"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8263"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8264"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8265"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8266"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8267"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8268"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8269"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8309"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8310"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8323"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8324"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8325"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8326"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8327"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8328"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8329"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8330"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8331"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8332"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8333"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8334"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8335"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8336"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8337"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8338"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8339"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8340"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8341"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/ARBITER/SLICE_8342"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8343"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/ARBITER/SLICE_8344"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/ARBITER/SLICE_8345"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8346"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/ARBITER/SLICE_8347"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8348"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8349"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9281"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_9282"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9283"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9284"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9285"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9286"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9287"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9288"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9289"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9290"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9291"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9292"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9293"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9294"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/k_1_0/SLICE_11621"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_11849"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_11891"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_11892"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_11893"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_11894"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_11895"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_11896"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_11897"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12031"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12032"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12333"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12334"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12335"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12336"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12337"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12338"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12339"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12340"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12341"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12342"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12343"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12344"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12345"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12346"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12347"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12348"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12349"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12350"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12351"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12352"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12353"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12354"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12355"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12356"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12357"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12358"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12359"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12360"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12361"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12362"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12363"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12364"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12550"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12555"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12556"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12557"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12584"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12585"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12775"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/ARBITER/SLICE_12810"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12896"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12897"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12898"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_13106"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/ARBITER/SLICE_13107"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/ARBITER/SLICE_13108"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13109"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13110"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13111"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13112"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13113"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13114"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_14066"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_14067"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_14068"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_14069"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_14070"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_14071"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_14074";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8232"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8270"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8271"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8272"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8540"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8541"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8542"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8543"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8544"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8545"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8546"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8547"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8548"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8549"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12156"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12157"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12158"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_13326"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_13327"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_13328";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8234"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8281"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8282"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8283"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8436"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8438"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8440"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8675"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8676"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8677"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8678"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8679"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8680"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8681"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8682"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12141"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12142"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12143"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_13303"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_13304"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_13305";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/TRMBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8236"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8237"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8293"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8294"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8295"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8296"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8297"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8298"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8299"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8315"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8316"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8317"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8318"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8319"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8320"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8877"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8878"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8879"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8880"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8881"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8882"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8883"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8884"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_11844"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_11845"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_12033"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_12635"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_12636"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_12776"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_12843"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_13115";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8238"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8300"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8301"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8302"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8437"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8439"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8441"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8442"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8943"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8944"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8945"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8946"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8947"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8948"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8949"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12122"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12123"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_13280"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_13281"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_13282";
+PGROUP "THE_SLAVE_BUS/THE_BUS_HANDLER/Bus_handler_group"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_9348"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_9349"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_9350"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_9351"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_9352"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_9353"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_9354"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10185"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10186"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10187"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10188"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10189"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10190"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10191"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10428"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10429"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10430"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10431"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10432"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10433"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10434"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10435"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10436"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10437"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10438"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10439"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10440"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10441"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10442"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10443"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10444"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10445"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10446"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10447"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10448"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10449"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10450"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10451"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10452"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10453"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10454"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10455"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10456"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10457"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10458"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10459"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10460"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10461"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10462"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10463"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10464"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10474"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11154"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11155"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11156"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11157"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11158"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11159"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11160"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11161"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11162"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11163"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11164"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11165"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11166"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11167"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11168"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11169"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11170"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11171"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11172"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11173"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11174"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11175"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11176"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11177"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11178"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11179"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11180"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11181"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11182"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11183"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11184"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11201"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11203"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11204"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m113/SLICE_11526"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m150/SLICE_11527"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m174/SLICE_11528"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m178/SLICE_11529"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m188/SLICE_11530"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m197/SLICE_11531"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m227/SLICE_11532"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m283/SLICE_11533"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m377/SLICE_11534"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m406/SLICE_11535"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m468/SLICE_11536"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m484/SLICE_11537"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m512/SLICE_11538"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m559/SLICE_11539"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m671/SLICE_11540"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m677/SLICE_11541"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m681/SLICE_11542"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m687/SLICE_11543"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m887/SLICE_11544"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m889/SLICE_11545"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m923/SLICE_11546"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m946/SLICE_11547"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m961/SLICE_11548"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m966/SLICE_11549"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1020/SLICE_11550"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1027/SLICE_11551"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1035/SLICE_11552"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1042/SLICE_11553"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1046/SLICE_11554"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1164/SLICE_11555"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1300/SLICE_11556"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1341/SLICE_11557"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1472/SLICE_11558"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1553/SLICE_11559"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1557/SLICE_11560"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1571/SLICE_11561"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1626/SLICE_11562"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1846/SLICE_11563"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1852/SLICE_11564"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1855/SLICE_11565"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1942/SLICE_11566"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1981/SLICE_11567"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2091/SLICE_11568"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2243/SLICE_11569"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2318/SLICE_11570"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2369/SLICE_11571"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2687/SLICE_11572"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2693/SLICE_11573"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2723/SLICE_11574"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2726/SLICE_11575"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2737/SLICE_11576"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2746/SLICE_11577"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2749/SLICE_11578"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2755/SLICE_11579"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_DAT_WRITE_ACK_OUT_1_16_i_m2/SLICE_11580"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m656/SLICE_11581"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m651/SLICE_11582"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2707/SLICE_11583"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2139/SLICE_11584"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m909/SLICE_11585"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m437/SLICE_11586"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1625/SLICE_11587"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2502/SLICE_11588"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2608/SLICE_11589"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2673/SLICE_11590"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2702/SLICE_11591"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2732/SLICE_11592"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1013/SLICE_11593"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1398/SLICE_11594"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1399/SLICE_11595"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1672/SLICE_11596"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1727/SLICE_11597"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1748/SLICE_11598"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1764/SLICE_11599"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1796/SLICE_11600"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2057/SLICE_11601"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2098/SLICE_11602"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2309/SLICE_11603"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2572/SLICE_11604"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2601/SLICE_11605"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2615/SLICE_11606"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2628/SLICE_11607"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2634/SLICE_11608"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2641/SLICE_11609"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2651/SLICE_11610"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2656/SLICE_11611"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2661/SLICE_11612"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2682/SLICE_11613"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_DAT_WRITE_ACK_OUT_1_4_i_m2/SLICE_11614"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_DAT_WRITE_ACK_OUT_1_13_i_m2/SLICE_11615"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2779/SLICE_11616"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1173/SLICE_11617"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1674/SLICE_11618"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2630/SLICE_11619"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2636/SLICE_11620"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11882"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11883"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11884"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11885"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11886"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11887"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11888"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11889"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11890"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12018"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12019"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12020"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12021"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12022"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12023"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12024"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12025"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12026"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12027"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12028"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12029"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12030"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12332"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12548"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12549"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12575"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12576"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12577"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12578"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12579"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12580"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12581"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12582"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12583"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12633"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12634"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12773"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12774"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12806"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12807"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12808"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12809"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12842"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12883"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12901"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12941"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12942"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13033"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13034"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13035"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13036"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13037"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13038"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13039"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13040"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13041"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13042"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13043"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13044"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13045"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13046"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13047"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13048"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13049"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13050"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13051"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13052"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13053"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13054"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13055"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13056"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13057"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13058"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13059"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13060"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13061"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13062"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13063"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13064"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13065"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13066"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13067"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13068"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13069"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13070"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13071"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13072"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13073"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13074"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13075"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13076"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13077"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13078"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13079"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13080"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13081"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13082"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13083"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13084"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13085"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13086"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13087"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13088"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13089"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13090"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13091"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13092"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13093"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13094"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13095"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13096"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13097"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13098"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13099"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13100"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13101"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13102"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13103"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13104"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13105";
+PGROUP "THE_SLAVE_BUS/THE_SPI_MEMORY/SPI_group"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/SLICE_10146"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/SLICE_10147"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/SLICE_10148"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/SLICE_10149"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/SLICE_10195"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/SLICE_13000"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0";
+LOCATE COMP "APV0_SDA" SITE "Y6" ;
+LOCATE COMP "APV0A_CLK" SITE "AC7" ;
+LOCATE COMP "CLK100M" SITE "AJ14" ;
+LOCATE COMP "ADC0_OUT_7" SITE "T5" ;
+LOCATE COMP "ADC0_OUT_6" SITE "U3" ;
+LOCATE COMP "ADC0_OUT_5" SITE "U5" ;
+LOCATE COMP "ADC0_OUT_4" SITE "Y1" ;
+LOCATE COMP "ADC0_OUT_3" SITE "AA1" ;
+LOCATE COMP "ADC0_OUT_2" SITE "AB2" ;
+LOCATE COMP "ADC0_OUT_1" SITE "AC1" ;
+LOCATE COMP "ADC0_OUT_0" SITE "AD2" ;
+LOCATE COMP "ADC0_ADCLK" SITE "R3" ;
+LOCATE COMP "ADC1_OUT_7" SITE "E2" ;
+LOCATE COMP "ADC1_OUT_6" SITE "G2" ;
+LOCATE COMP "ADC1_OUT_5" SITE "J5" ;
+LOCATE COMP "ADC1_OUT_4" SITE "J3" ;
+LOCATE COMP "ADC1_OUT_3" SITE "K2" ;
+LOCATE COMP "ADC1_OUT_2" SITE "N5" ;
+LOCATE COMP "ADC1_OUT_1" SITE "M4" ;
+LOCATE COMP "ADC1_OUT_0" SITE "P3" ;
+LOCATE COMP "ADC1_ADCLK" SITE "D2" ;
+LOCATE COMP "U_SPI_SDO" SITE "AE24" ;
+LOCATE COMP "U_SPI_SDI" SITE "AE25" ;
+LOCATE COMP "U_SPI_SCK" SITE "AF26" ;
+LOCATE COMP "U_SPI_CS" SITE "AD24" ;
+LOCATE COMP "APV1_1W_7" SITE "B15" ;
+LOCATE COMP "APV1_1W_6" SITE "A16" ;
+LOCATE COMP "APV1_1W_5" SITE "B16" ;
+LOCATE COMP "APV1_1W_4" SITE "A17" ;
+LOCATE COMP "APV1_1W_3" SITE "B17" ;
+LOCATE COMP "APV1_1W_2" SITE "C16" ;
+LOCATE COMP "APV1_1W_1" SITE "C17" ;
+LOCATE COMP "APV1_1W_0" SITE "D16" ;
+LOCATE COMP "APV0_1W_7" SITE "AJ16" ;
+LOCATE COMP "APV0_1W_6" SITE "AK16" ;
+LOCATE COMP "APV0_1W_5" SITE "AJ17" ;
+LOCATE COMP "APV0_1W_4" SITE "AK17" ;
+LOCATE COMP "APV0_1W_3" SITE "AG18" ;
+LOCATE COMP "APV0_1W_2" SITE "AG19" ;
+LOCATE COMP "APV0_1W_1" SITE "AG20" ;
+LOCATE COMP "APV0_1W_0" SITE "AG21" ;
+LOCATE COMP "FPGA_LED_ADC_1" SITE "H3" ;
+LOCATE COMP "FPGA_LED_ADC_0" SITE "V2" ;
+LOCATE COMP "FPGA_LED_PLL" SITE "AG22" ;
+LOCATE COMP "FPGA_LED_LINK" SITE "K26" ;
+LOCATE COMP "FPGA_LED_TXD" SITE "J27" ;
+LOCATE COMP "FPGA_LED_RXD" SITE "J28" ;
+LOCATE COMP "FPGA_LED_6" SITE "G28" ;
+LOCATE COMP "FPGA_LED_5" SITE "G27" ;
+LOCATE COMP "FPGA_LED_4" SITE "H28" ;
+LOCATE COMP "FPGA_LED_3" SITE "H27" ;
+LOCATE COMP "BP_LED" SITE "AE8" ;
+LOCATE COMP "BP_ONEWIRE" SITE "F7" ;
+LOCATE COMP "BP_SECTOR_2" SITE "AF12" ;
+LOCATE COMP "BP_SECTOR_1" SITE "AF13" ;
+LOCATE COMP "BP_SECTOR_0" SITE "AF15" ;
+LOCATE COMP "BP_MODULE_2" SITE "F13" ;
+LOCATE COMP "BP_MODULE_1" SITE "E12" ;
+LOCATE COMP "BP_MODULE_0" SITE "G11" ;
+LOCATE COMP "ADCM_ONEWIRE" SITE "F29" ;
+LOCATE COMP "SD_TXDIS" SITE "J29" ;
+LOCATE COMP "SD_LOS" SITE "F30" ;
+LOCATE COMP "SD_PRESENT" SITE "G30" ;
+LOCATE COMP "UC_REBOOT" SITE "Y28" ;
+LOCATE COMP "UC_RESET" SITE "V26" ;
+LOCATE COMP "ADC1_LCLK" SITE "L3" ;
+LOCATE COMP "ADC1_SCK" SITE "F1" ;
+LOCATE COMP "ADC1_SDI" SITE "F2" ;
+LOCATE COMP "ADC1_CS" SITE "E1" ;
+LOCATE COMP "ADC1_PD" SITE "H1" ;
+LOCATE COMP "ADC1_RST" SITE "G3" ;
+LOCATE COMP "ADC1_CLK" SITE "H2" ;
+LOCATE COMP "ADC0_LCLK" SITE "T3" ;
+LOCATE COMP "ADC0_SCK" SITE "W2" ;
+LOCATE COMP "ADC0_SDI" SITE "AB1" ;
+LOCATE COMP "ADC0_CS" SITE "AC3" ;
+LOCATE COMP "ADC0_PD" SITE "V1" ;
+LOCATE COMP "ADC0_RST" SITE "AD3" ;
+LOCATE COMP "ADC0_CLK" SITE "W1" ;
+LOCATE COMP "ENB_LVDS_7" SITE "F6" ;
+LOCATE COMP "ENB_LVDS_6" SITE "D5" ;
+LOCATE COMP "ENB_LVDS_5" SITE "D4" ;
+LOCATE COMP "ENB_LVDS_4" SITE "E5" ;
+LOCATE COMP "ENB_LVDS_3" SITE "D15" ;
+LOCATE COMP "ENB_LVDS_2" SITE "E13" ;
+LOCATE COMP "ENB_LVDS_1" SITE "D13" ;
+LOCATE COMP "ENB_LVDS_0" SITE "D12" ;
+LOCATE COMP "APV1_SCL" SITE "K6" ;
+LOCATE COMP "APV1_SDA" SITE "K7" ;
+LOCATE COMP "APV1_RST" SITE "K5" ;
+LOCATE COMP "APV1B_TRG" SITE "G6" ;
+LOCATE COMP "APV1A_TRG" SITE "L5" ;
+LOCATE COMP "APV1B_CLK" SITE "G5" ;
+LOCATE COMP "APV1A_CLK" SITE "J8" ;
+LOCATE COMP "ENA_LVDS_7" SITE "AG2" ;
+LOCATE COMP "ENA_LVDS_6" SITE "AG3" ;
+LOCATE COMP "ENA_LVDS_5" SITE "AG4" ;
+LOCATE COMP "ENA_LVDS_4" SITE "AG5" ;
+LOCATE COMP "ENA_LVDS_3" SITE "AG11" ;
+LOCATE COMP "ENA_LVDS_2" SITE "AG12" ;
+LOCATE COMP "ENA_LVDS_1" SITE "AG13" ;
+LOCATE COMP "ENA_LVDS_0" SITE "AG15" ;
+LOCATE COMP "APV0_SCL" SITE "AA6" ;
+LOCATE COMP "APV0_RST" SITE "AA5" ;
+LOCATE COMP "APV0B_TRG" SITE "AB4" ;
+LOCATE COMP "APV0A_TRG" SITE "Y9" ;
+LOCATE COMP "APV0B_CLK" SITE "W3" ;
+LOCATE COMP "EXT_IN_3" SITE "AA30" ;
+LOCATE COMP "EXT_IN_2" SITE "AB30" ;
+LOCATE COMP "EXT_IN_1" SITE "AB29" ;
+LOCATE COMP "EXT_IN_0" SITE "AB28" ;
+LOCATE COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/PCSC_INST" SITE "URPCS" ;
+LOCATE COMP "THE_100M_DLL/dll_100m_0_0" SITE "DLL_R103C1" ;
+FREQUENCY NET "clk_adc" 40.000000 MHz ;
+FREQUENCY NET "CLK100M_c" 100.000000 MHz ;
+FREQUENCY NET "clk_apv_c" 40.000000 MHz ;
+FREQUENCY NET "cts_clk40m" 40.000000 MHz ;
+FREQUENCY NET "sysclk_c" 100.000000 MHz ;
+FREQUENCY NET "EXT_IN_c_3" 40.000000 MHz ;
+SCHEMATIC END ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+DEFINE PORT GROUP "enable_lvds_group" "EN?_LVDS_{0:7}" ;
+USERCODE HEX "DEADAFFE" ;
+REGION "MEDIA_INTERFACE_REGION" "R9C100" 10 28 DEVSIZE;
+PERIOD PORT "ADC0_LCLK" 4.166600 nS ;
+USE PRIMARY PURE NET "ADC0_LCLK_c" ;
+DEFINE PORT GROUP "ADC0_INPUT" "ADC0_OUT*"
+"ADC0_ADCLK*" ;
+INPUT_SETUP GROUP "ADC0_INPUT"0.600000 ns HOLD 0.600000 ns CLKPORT "ADC0_LCLK" ;
+PERIOD PORT "ADC1_LCLK" 4.166600 nS ;
+USE PRIMARY PURE NET "ADC1_LCLK_c" ;
+DEFINE PORT GROUP "ADC1_INPUT" "ADC1_OUT*"
+"ADC1_ADCLK*" ;
+INPUT_SETUP GROUP "ADC1_INPUT"0.600000 ns HOLD 0.600000 ns CLKPORT "ADC1_LCLK" ;
+COMMERCIAL ;
--- /dev/null
+#Build: Synplify Premier with Design Planner D-2010.03, Build 093R, Feb 19 2010
+#install: /usr/local/opt/synplify/premier
+#OS: Linux
+#Hostname: burke
+
+#Implementation: workdir
+
+#Mon Jun 14 22:07:57 2010
+
+$ Start of Compile
+#Mon Jun 14 22:08:00 2010
+
+Synopsys VHDL Compiler, version comp500rc, Build 027R, built Feb 19 2010
+Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved
+
+@N: CD720 :"/usr/local/opt/synplify/premier/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adcmv3.vhd":14:7:14:12|Top entity is set to adcmv3.
+VHDL syntax check successful!
+File /home/mboehmer/VHDL_Pro/comp_adcmv3/version.vhd changed - recompiling
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adcmv3.vhd":13:7:13:12|Synthesizing work.adcmv3.adcmv3
+@N: CD630 :"/usr/local/opt/synplify/premier/lib/lucent/ecp2m.vhd":1873:10:1873:15|Synthesizing ecp2m.oddrxc.syn_black_box
+Post processing for ecp2m.oddrxc.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trgctrl.vhd":8:7:8:17|Synthesizing work.apv_trgctrl.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_sync_handler.vhd":8:7:8:22|Synthesizing work.apv_sync_handler.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_sync_handler.vhd":27:12:27:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_sync_handler.vhd":107:2:107:15|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_sync_handler.vhd":125:2:125:15|OTHERS clause is not synthesized
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/pulse_sync.vhd":8:7:8:16|Synthesizing work.pulse_sync.behavioral
+Post processing for work.pulse_sync.behavioral
+Post processing for work.apv_sync_handler.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":8:7:8:21|Synthesizing work.apv_trg_handler.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":29:12:29:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":145:2:145:15|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":160:2:160:15|OTHERS clause is not synthesized
+Post processing for work.apv_trg_handler.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/eds_buf.vhd":8:7:8:13|Synthesizing work.eds_buf.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/eds_buffer_dpram.vhd":14:7:14:22|Synthesizing work.eds_buffer_dpram.structure
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/eds_buffer_dpram.vhd":103:14:103:16|Unbound component VLO mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/eds_buffer_dpram.vhd":100:14:100:16|Unbound component VHI mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/eds_buffer_dpram.vhd":83:14:83:20|Unbound component ROM16X1 mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/eds_buffer_dpram.vhd":76:14:76:20|Unbound component FD1P3DX mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/eds_buffer_dpram.vhd":90:14:90:21|Unbound component DPR16X4A mapped to black box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/eds_buffer_dpram.vhd":90:14:90:21|Synthesizing work.dpr16x4a.syn_black_box
+Post processing for work.dpr16x4a.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/eds_buffer_dpram.vhd":76:14:76:20|Synthesizing work.fd1p3dx.syn_black_box
+Post processing for work.fd1p3dx.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/eds_buffer_dpram.vhd":83:14:83:20|Synthesizing work.rom16x1.syn_black_box
+Post processing for work.rom16x1.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/eds_buffer_dpram.vhd":100:14:100:16|Synthesizing work.vhi.syn_black_box
+Post processing for work.vhi.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/eds_buffer_dpram.vhd":103:14:103:16|Synthesizing work.vlo.syn_black_box
+Post processing for work.vlo.syn_black_box
+Post processing for work.eds_buffer_dpram.structure
+@W: CL168 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/eds_buffer_dpram.vhd":152:4:152:17|Pruning instance scuba_vlo_inst - not in use ...
+Post processing for work.eds_buf.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/max_data.vhd":8:7:8:14|Synthesizing work.max_data.behavioral
+Post processing for work.max_data.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":13:7:13:22|Synthesizing work.real_trg_handler.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":55:12:55:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":457:2:457:15|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":483:2:483:15|OTHERS clause is not synthesized
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/state_sync.vhd":8:7:8:16|Synthesizing work.state_sync.behavioral
+Post processing for work.state_sync.behavioral
+Post processing for work.real_trg_handler.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/pulse_stretch.vhd":8:7:8:19|Synthesizing work.pulse_stretch.behavioral
+Post processing for work.pulse_stretch.behavioral
+Post processing for work.apv_trgctrl.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_channel_select.vhd":8:7:8:24|Synthesizing work.adc_channel_select.behavioral
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_channel_select.vhd":88:4:88:17|OTHERS clause is not synthesized
+Post processing for work.adc_channel_select.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_crossover.vhd":8:7:8:19|Synthesizing work.adc_crossover.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":14:7:14:15|Synthesizing work.crossover.structure
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":263:14:263:17|Unbound component AND2 mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":308:14:308:16|Unbound component INV mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":311:14:311:16|Unbound component OR2 mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":337:14:337:17|Unbound component XOR2 mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":280:14:280:20|Unbound component FD1P3BX mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":301:14:301:20|Unbound component FD1S3DX mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":294:14:294:20|Unbound component FD1S3BX mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":270:14:270:19|Unbound component FADD2B mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":266:14:266:16|Unbound component CU2 mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":275:14:275:19|Unbound component FSUB2B mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":259:14:259:18|Unbound component AGEB2 mapped to black box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":270:14:270:19|Synthesizing work.fadd2b.syn_black_box
+Post processing for work.fadd2b.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":259:14:259:18|Synthesizing work.ageb2.syn_black_box
+Post processing for work.ageb2.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":275:14:275:19|Synthesizing work.fsub2b.syn_black_box
+Post processing for work.fsub2b.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":266:14:266:16|Synthesizing work.cu2.syn_black_box
+Post processing for work.cu2.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":301:14:301:20|Synthesizing work.fd1s3dx.syn_black_box
+Post processing for work.fd1s3dx.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":294:14:294:20|Synthesizing work.fd1s3bx.syn_black_box
+Post processing for work.fd1s3bx.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":280:14:280:20|Synthesizing work.fd1p3bx.syn_black_box
+Post processing for work.fd1p3bx.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":337:14:337:17|Synthesizing work.xor2.syn_black_box
+Post processing for work.xor2.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":311:14:311:16|Synthesizing work.or2.syn_black_box
+Post processing for work.or2.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":308:14:308:16|Synthesizing work.inv.syn_black_box
+Post processing for work.inv.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":263:14:263:17|Synthesizing work.and2.syn_black_box
+Post processing for work.and2.syn_black_box
+Post processing for work.crossover.structure
+@W: CL168 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":1805:4:1805:9|Pruning instance rfilld - not in use ...
+@W: CL168 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":1783:4:1783:9|Pruning instance wfilld - not in use ...
+Post processing for work.adc_crossover.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_data_handler.vhd":8:7:8:22|Synthesizing work.adc_data_handler.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":8:7:8:21|Synthesizing work.adc_twochannels.behaviour
+Post processing for work.adc_twochannels.behaviour
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_ch_in.vhd":14:7:14:15|Synthesizing work.adc_ch_in.structure
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_ch_in.vhd":40:14:40:20|Unbound component IDDRFXA mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_ch_in.vhd":45:14:45:19|Unbound component DELAYB mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_ch_in.vhd":37:14:37:15|Unbound component IB mapped to black box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_ch_in.vhd":37:14:37:15|Synthesizing work.ib.syn_black_box
+Post processing for work.ib.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_ch_in.vhd":45:14:45:19|Synthesizing work.delayb.syn_black_box
+Post processing for work.delayb.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_ch_in.vhd":40:14:40:20|Synthesizing work.iddrfxa.syn_black_box
+Post processing for work.iddrfxa.syn_black_box
+Post processing for work.adc_ch_in.structure
+Post processing for work.adc_data_handler.behavioral
+@W: CL170 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_data_handler.vhd":278:1:278:2|Pruning bit <3> of recswap(3 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_data_handler.vhd":278:1:278:2|Pruning bit <2> of recswap(3 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_data_handler.vhd":278:1:278:2|Pruning bit <1> of recswap(3 downto 0) - not in use ...
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/raw_buf_stage.vhd":8:7:8:19|Synthesizing work.raw_buf_stage.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":17:7:17:20|Synthesizing work.apv_raw_buffer.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":14:7:14:22|Synthesizing work.frame_status_mem.structure
+Post processing for work.frame_status_mem.structure
+@W: CL168 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":96:4:96:17|Pruning instance scuba_vlo_inst - not in use ...
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":14:7:14:16|Synthesizing work.input_bram.structure
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":41:14:41:19|Unbound component DP16KB mapped to black box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":41:14:41:19|Synthesizing work.dp16kb.syn_black_box
+Post processing for work.dp16kb.syn_black_box
+Post processing for work.input_bram.structure
+@W: CL168 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":146:4:146:17|Pruning instance scuba_vhi_inst - not in use ...
+Post processing for work.apv_raw_buffer.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":11:7:11:16|Synthesizing work.apv_locker.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":8:7:8:17|Synthesizing work.apv_lock_sm.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":63:12:63:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":404:2:404:15|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":435:2:435:15|OTHERS clause is not synthesized
+Post processing for work.apv_lock_sm.behavioral
+@W: CL169 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Pruning Register dataframe
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":8:7:8:17|Synthesizing work.apv_digital.behavioral
+Post processing for work.apv_digital.behavioral
+Post processing for work.apv_locker.behavioral
+Post processing for work.raw_buf_stage.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":11:7:11:19|Synthesizing work.ped_corr_ctrl.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":114:12:114:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":238:2:238:15|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":544:2:544:15|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":582:2:582:15|OTHERS clause is not synthesized
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/decoder_8bit.vhd":14:7:14:18|Synthesizing work.decoder_8bit.structure
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/decoder_8bit.vhd":23:14:23:21|Unbound component ROM256X1 mapped to black box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/decoder_8bit.vhd":23:14:23:21|Synthesizing work.rom256x1.syn_black_box
+Post processing for work.rom256x1.syn_black_box
+Post processing for work.decoder_8bit.structure
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":15:7:15:19|Synthesizing work.apv_pc_nc_alu.behavioral
+Post processing for work.apv_pc_nc_alu.behavioral
+@W: CL170 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":206:1:206:2|Pruning bit <0> of loc_baseline_q(13 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Pruning bit <6> of off_int(6 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Pruning bit <5> of off_int(6 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Pruning bit <4> of off_int(6 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Pruning bit <6> of toggle(6 downto 0) - not in use ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":169:1:169:2|Register bit raw_data_q(12) is always 1, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":177:1:177:2|Register bit ped_data_q(12) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":177:1:177:2|Pruning Register bit 12 of ped_data_q(12 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":169:1:169:2|Pruning Register bit 12 of raw_data_q(12 downto 0)
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":11:7:11:13|Synthesizing work.buf_toc.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":32:12:32:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":195:2:195:15|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":212:2:212:15|OTHERS clause is not synthesized
+Post processing for work.buf_toc.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":15:7:15:17|Synthesizing work.ref_row_sel.behavioral
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":155:3:155:16|OTHERS clause is not synthesized
+Post processing for work.ref_row_sel.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frmctr_check.vhd":11:7:11:18|Synthesizing work.frmctr_check.behavioral
+Post processing for work.frmctr_check.behavioral
+Post processing for work.ped_corr_ctrl.behavioral
+@W: CL169 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":653:1:653:2|Pruning Register cleaned_up
+@W: CL169 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":369:1:369:2|Pruning Register buf_addr_init
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":653:1:653:2|Register bit small_0_sum(4) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":653:1:653:2|Register bit small_1_sum(4) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":653:1:653:2|Register bit max_num_words(0) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":653:1:653:2|Register bit max_num_words(5) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":653:1:653:2|Register bit max_num_words(11) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":653:1:653:2|Pruning Register bit 11 of max_num_words(11 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":653:1:653:2|Pruning Register bit 5 of max_num_words(11 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":653:1:653:2|Pruning Register bit 0 of max_num_words(11 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":653:1:653:2|Pruning Register bit 4 of small_0_sum(4 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":653:1:653:2|Pruning Register bit 4 of small_1_sum(4 downto 0)
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":10:7:10:20|Synthesizing work.ipu_fifo_stage.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":89:12:89:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":292:2:292:15|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":335:2:335:15|OTHERS clause is not synthesized
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_apv_map_mem.vhd":14:7:14:21|Synthesizing work.adc_apv_map_mem.structure
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_apv_map_mem.vhd":23:14:23:21|Unbound component ROM128X1 mapped to black box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_apv_map_mem.vhd":23:14:23:21|Synthesizing work.rom128x1.syn_black_box
+Post processing for work.rom128x1.syn_black_box
+Post processing for work.adc_apv_map_mem.structure
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":14:7:14:16|Synthesizing work.fifo_1kx18.structure
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":179:14:179:16|Unbound component CB2 mapped to black box
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":168:14:168:18|Unbound component ALEB2 mapped to black box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":168:14:168:18|Synthesizing work.aleb2.syn_black_box
+Post processing for work.aleb2.syn_black_box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":179:14:179:16|Synthesizing work.cb2.syn_black_box
+Post processing for work.cb2.syn_black_box
+Post processing for work.fifo_1kx18.structure
+@W: CL168 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":858:4:858:10|Pruning instance r_ctr_5 - not in use ...
+@W: CL168 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":829:4:829:10|Pruning instance w_ctr_5 - not in use ...
+@W: CL168 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":695:4:695:7|Pruning instance FF_1 - not in use ...
+@W: CL168 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":618:4:618:8|Pruning instance FF_12 - not in use ...
+@W: CL168 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":412:4:412:8|Pruning instance INV_1 - not in use ...
+@W: CL168 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":403:4:403:8|Pruning instance INV_4 - not in use ...
+@W: CL168 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":400:4:400:10|Pruning instance AND2_t0 - not in use ...
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":14:7:14:16|Synthesizing work.fifo_2kx27.structure
+Post processing for work.fifo_2kx27.structure
+Post processing for work.ipu_fifo_stage.behavioral
+@W: CL169 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":197:1:197:2|Pruning Register ack_todo
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":12:7:12:15|Synthesizing work.slave_bus.behavioral
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 32 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 33 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 34 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 35 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 36 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 37 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 38 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 39 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 40 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 41 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 42 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 43 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 44 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 45 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 46 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 47 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 96 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 97 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 98 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 99 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 100 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 101 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 102 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 103 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 104 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 105 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 106 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 107 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 108 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 109 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 110 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 111 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 112 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 113 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 114 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 115 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 116 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 117 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 118 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 119 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 120 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 121 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 122 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 123 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 124 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 125 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 126 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 127 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 144 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 145 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 146 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 147 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 148 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 149 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 150 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 151 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 152 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 153 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 154 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 155 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 156 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 157 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 158 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 159 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 160 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 161 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 162 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 163 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 164 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 165 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 166 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 167 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 168 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 169 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 170 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 171 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 172 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 173 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 174 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 175 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 176 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 177 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 178 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 179 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 180 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 181 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 182 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 183 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 184 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 185 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 186 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 187 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 188 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 189 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 190 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 191 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 224 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 225 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 226 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 227 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 228 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 229 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 230 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 231 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 232 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 233 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 234 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 235 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 236 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 237 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 238 of signal slv_addr is undriven
+@W: CD639 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slave_bus.vhd":176:7:176:14|Bit 239 of signal slv_addr is undriven
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":10:7:10:18|Synthesizing work.slv_register.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":36:12:36:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":136:2:136:19|OTHERS clause is not synthesized
+Post processing for work.slv_register.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":10:7:10:19|Synthesizing work.slv_adc_snoop.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":33:12:33:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":124:2:124:19|OTHERS clause is not synthesized
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":14:7:14:19|Synthesizing work.adc_snoop_mem.structure
+Post processing for work.adc_snoop_mem.structure
+Post processing for work.slv_adc_snoop.behavioral
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Register bit status_reg(26) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Register bit status_reg(27) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Register bit status_reg(28) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Register bit status_reg(29) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Register bit status_reg(30) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Register bit status_reg(31) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Pruning Register bit 31 of status_reg(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Pruning Register bit 30 of status_reg(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Pruning Register bit 29 of status_reg(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Pruning Register bit 28 of status_reg(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Pruning Register bit 27 of status_reg(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Pruning Register bit 26 of status_reg(31 downto 0)
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":10:7:10:23|Synthesizing work.slv_half_register.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":34:12:34:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":110:2:110:19|OTHERS clause is not synthesized
+Post processing for work.slv_half_register.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":10:7:10:18|Synthesizing work.slv_register.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":36:12:36:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":136:2:136:19|OTHERS clause is not synthesized
+Post processing for work.slv_register.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":10:7:10:18|Synthesizing work.slv_register.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":36:12:36:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":136:2:136:19|OTHERS clause is not synthesized
+Post processing for work.slv_register.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status.vhd":9:7:9:16|Synthesizing work.slv_status.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status.vhd":26:12:26:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status.vhd":88:2:88:19|OTHERS clause is not synthesized
+Post processing for work.slv_status.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":9:7:9:21|Synthesizing work.slv_status_bank.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":42:12:42:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":104:2:104:19|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":131:3:131:16|OTHERS clause is not synthesized
+Post processing for work.slv_status_bank.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":9:7:9:23|Synthesizing work.slv_register_bank.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":65:12:65:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":136:3:136:16|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":202:2:202:19|OTHERS clause is not synthesized
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_adc_map_mem.vhd":14:7:14:21|Synthesizing work.apv_adc_map_mem.structure
+Post processing for work.apv_adc_map_mem.structure
+Post processing for work.slv_register_bank.behavioral
+@W: CL169 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":148:1:148:2|Pruning Register store_rd
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":9:7:9:20|Synthesizing work.spi_adc_master.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":42:12:42:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":167:2:167:19|OTHERS clause is not synthesized
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_real_slim.vhd":9:7:9:19|Synthesizing work.spi_real_slim.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_real_slim.vhd":37:13:37:14|Using sequential encoding for type state_t
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_real_slim.vhd":194:2:194:15|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_real_slim.vhd":208:2:208:19|OTHERS clause is not synthesized
+Post processing for work.spi_real_slim.behavioral
+Post processing for work.spi_adc_master.behavioral
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Register bit reg_slv_data_out(9) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Register bit reg_slv_data_out(10) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Register bit reg_slv_data_out(11) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Register bit reg_slv_data_out(12) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Register bit reg_slv_data_out(13) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Register bit reg_slv_data_out(14) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Register bit reg_slv_data_out(15) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Register bit reg_slv_data_out(16) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Register bit reg_slv_data_out(17) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Register bit reg_slv_data_out(18) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Register bit reg_slv_data_out(19) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Register bit reg_slv_data_out(20) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Register bit reg_slv_data_out(21) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Register bit reg_slv_data_out(22) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Register bit reg_slv_data_out(23) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Pruning Register bit 23 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Pruning Register bit 22 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Pruning Register bit 21 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Pruning Register bit 20 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Pruning Register bit 19 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Pruning Register bit 18 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Pruning Register bit 17 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Pruning Register bit 16 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Pruning Register bit 15 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Pruning Register bit 14 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Pruning Register bit 13 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Pruning Register bit 12 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Pruning Register bit 11 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Pruning Register bit 10 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Pruning Register bit 9 of reg_slv_data_out(31 downto 0)
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_databus_memory.vhd":10:7:10:24|Synthesizing work.spi_databus_memory.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_databus_memory.vhd":37:14:37:15|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_databus_memory.vhd":122:8:122:24|OTHERS clause is not synthesized
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":14:7:14:23|Synthesizing work.spi_dpram_32_to_8.structure
+Post processing for work.spi_dpram_32_to_8.structure
+Post processing for work.spi_databus_memory.behavioral
+@W: CL169 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_databus_memory.vhd":61:6:61:7|Pruning Register store_rd
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":10:7:10:16|Synthesizing work.spi_master.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":44:16:44:17|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":194:6:194:24|OTHERS clause is not synthesized
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_slim.vhd":12:7:12:14|Synthesizing work.spi_slim.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_slim.vhd":50:13:50:14|Using sequential encoding for type state_t
+@W: CD604 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_slim.vhd":507:8:507:23|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_slim.vhd":523:8:523:23|OTHERS clause is not synthesized
+Post processing for work.spi_slim.behavioral
+Post processing for work.spi_master.behavioral
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <23> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <22> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <21> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <20> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <19> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <18> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <17> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <16> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <15> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <14> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <13> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <12> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <11> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <10> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <9> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <8> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <7> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <6> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <5> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <4> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <3> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <2> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <1> of reg_status_data(31 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":206:6:206:7|Pruning bit <0> of reg_status_data(31 downto 0) - not in use ...
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_memory.vhd":9:7:9:24|Synthesizing work.slv_onewire_memory.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_memory.vhd":34:12:34:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_memory.vhd":173:2:173:19|OTHERS clause is not synthesized
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_dpram.vhd":14:7:14:23|Synthesizing work.slv_onewire_dpram.structure
+Post processing for work.slv_onewire_dpram.structure
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/onewire_master.vhd":11:7:11:20|Synthesizing work.onewire_master.onewire_master_arch
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/onewire_master.vhd":37:13:37:14|Using sequential encoding for type state_t
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/onewire_master.vhd":381:2:381:15|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/onewire_master.vhd":405:2:405:27|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/onewire_master.vhd":510:3:510:16|OTHERS clause is not synthesized
+Post processing for work.onewire_master.onewire_master_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/onewire_spare_one.vhd":14:7:14:23|Synthesizing work.onewire_spare_one.structure
+Post processing for work.onewire_spare_one.structure
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_onewire_map_mem.vhd":14:7:14:25|Synthesizing work.adc_onewire_map_mem.structure
+Post processing for work.adc_onewire_map_mem.structure
+Post processing for work.slv_onewire_memory.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":9:7:9:16|Synthesizing work.i2c_master.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":33:12:33:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":166:2:166:19|OTHERS clause is not synthesized
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_slim.vhd":12:7:12:14|Synthesizing work.i2c_slim.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_slim.vhd":39:12:39:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_slim.vhd":261:2:261:19|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_slim.vhd":288:2:288:19|OTHERS clause is not synthesized
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_gstart.vhd":9:7:9:16|Synthesizing work.i2c_gstart.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_gstart.vhd":31:12:31:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_gstart.vhd":169:2:169:15|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_gstart.vhd":188:2:188:15|OTHERS clause is not synthesized
+Post processing for work.i2c_gstart.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_sendb.vhd":9:7:9:15|Synthesizing work.i2c_sendb.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_sendb.vhd":32:12:32:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_sendb.vhd":251:2:251:15|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_sendb.vhd":266:2:266:15|OTHERS clause is not synthesized
+Post processing for work.i2c_sendb.behavioral
+@W: CL170 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_sendb.vhd":129:1:129:2|Pruning bit <8> of in_sr(8 downto 0) - not in use ...
+Post processing for work.i2c_slim.behavioral
+@W: CL169 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_slim.vhd":116:1:116:2|Pruning Register load_d
+@W: CL169 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_slim.vhd":116:1:116:2|Pruning Register load_c
+@W: CL169 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_slim.vhd":116:1:116:2|Pruning Register load_a
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_slim.vhd":296:1:296:2|Register bit i2c_byte(0) is always 1, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_slim.vhd":296:1:296:2|Pruning Register bit 0 of i2c_byte(8 downto 0)
+Post processing for work.i2c_master.behavioral
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Register bit reg_slv_data_out(8) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Register bit reg_slv_data_out(9) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Register bit reg_slv_data_out(10) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Register bit reg_slv_data_out(11) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Register bit reg_slv_data_out(12) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Register bit reg_slv_data_out(13) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Register bit reg_slv_data_out(14) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Register bit reg_slv_data_out(15) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Register bit reg_slv_data_out(21) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Register bit reg_slv_data_out(22) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Register bit reg_slv_data_out(23) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Pruning Register bit 23 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Pruning Register bit 22 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Pruning Register bit 21 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Pruning Register bit 15 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Pruning Register bit 14 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Pruning Register bit 13 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Pruning Register bit 12 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Pruning Register bit 11 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Pruning Register bit 10 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Pruning Register bit 9 of reg_slv_data_out(31 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":189:1:189:2|Pruning Register bit 8 of reg_slv_data_out(31 downto 0)
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_ped_thr_mem.vhd":9:7:9:21|Synthesizing work.slv_ped_thr_mem.behavioral
+@N: CD233 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_ped_thr_mem.vhd":49:12:49:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_ped_thr_mem.vhd":120:3:120:16|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_ped_thr_mem.vhd":186:2:186:19|OTHERS clause is not synthesized
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":14:7:14:18|Synthesizing work.ped_thr_true.structure
+Post processing for work.ped_thr_true.structure
+Post processing for work.slv_ped_thr_mem.behavioral
+@W: CL169 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_ped_thr_mem.vhd":132:1:132:2|Pruning Register store_rd
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regio_bus_handler.vhd":10:7:10:33|Synthesizing work.trb_net16_regio_bus_handler.regio_bus_handler_arch
+Post processing for work.trb_net16_regio_bus_handler.regio_bus_handler_arch
+Post processing for work.slave_bus.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/rich_trb.vhd":12:7:12:14|Synthesizing work.rich_trb.rich_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":13:7:13:35|Synthesizing work.trb_net16_endpoint_hades_full.trb_net16_endpoint_hades_full_arch
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":265:8:265:12|Port stat_data_counter of entity work.trb_net16_iobuf is unconnected
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":265:8:265:12|Port stat_buffer_counter of entity work.trb_net16_iobuf is unconnected
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":265:8:265:12|Port stat_data_counter of entity work.trb_net16_iobuf is unconnected
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":265:8:265:12|Port stat_buffer_counter of entity work.trb_net16_iobuf is unconnected
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":460:10:460:24|Port ipu_code_out of entity work.trb_net16_ipudata is unconnected
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":265:8:265:12|Port stat_data_counter of entity work.trb_net16_iobuf is unconnected
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":265:8:265:12|Port stat_buffer_counter of entity work.trb_net16_iobuf is unconnected
+@W: CG296 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":746:30:746:36|Incomplete sensitivity list - assuming completeness
+@W: CG290 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":750:46:750:67|Referenced variable timing_trigger_missing is not in sensitivity list
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_io_multiplexer.vhd":11:7:11:30|Synthesizing work.trb_net16_io_multiplexer.trb_net16_io_multiplexer_arch
+@N: CD364 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_io_multiplexer.vhd":316:12:316:12|Removed redundant assignment
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_sbuf.vhd":27:7:27:20|Synthesizing work.trb_net16_sbuf.trb_net16_sbuf_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":23:7:23:18|Synthesizing work.trb_net_sbuf.trb_net_sbuf_arch
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":58:20:58:21|Using sequential encoding for type buffer_state
+Post processing for work.trb_net_sbuf.trb_net_sbuf_arch
+Post processing for work.trb_net16_sbuf.trb_net16_sbuf_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":9:7:9:30|Synthesizing work.trb_net_priority_arbiter.trb_net_priority_arbiter_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_encoder.vhd":9:7:9:30|Synthesizing work.trb_net_priority_encoder.trb_net_priority_encoder_arch
+Post processing for work.trb_net_priority_encoder.trb_net_priority_encoder_arch
+Post processing for work.trb_net_priority_arbiter.trb_net_priority_arbiter_arch
+Post processing for work.trb_net16_io_multiplexer.trb_net16_io_multiplexer_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_onewire.vhd":10:7:10:21|Synthesizing work.trb_net_onewire.trb_net_onewire_arch
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_onewire.vhd":35:15:35:16|Using sequential encoding for type state_t
+@W: CD604 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_onewire.vhd":260:8:260:21|OTHERS clause is not synthesized
+Post processing for work.trb_net_onewire.trb_net_onewire_arch
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_onewire.vhd":291:6:291:7|Register bit strong_pullup is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_onewire.vhd":339:6:339:7|Register bit ram_addr(2) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_onewire.vhd":339:6:339:7|Pruning Register bit 2 of ram_addr(2 downto 0)
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":13:7:13:21|Synthesizing work.trb_net16_regio.trb_net16_regio_arch
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":110:19:110:20|Using sequential encoding for type fsm_state_t
+@W: CD604 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":660:8:660:21|OTHERS clause is not synthesized
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/basics/rom_16x8.vhd":9:7:9:14|Synthesizing work.rom_16x8.rom_16x8_arch
+Post processing for work.rom_16x8.rom_16x8_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_addresses.vhd":9:7:9:25|Synthesizing work.trb_net16_addresses.trb_net16_addresses_arch
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_addresses.vhd":90:21:90:22|Using sequential encoding for type sending_state_t
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/basics/ram_16x16_dp.vhd":9:7:9:18|Synthesizing work.ram_16x16_dp.ram_16x16_dp_arch
+Post processing for work.ram_16x16_dp.ram_16x16_dp_arch
+@N: CL134 :"/home/mboehmer/VHDL_Pro/trbnet/basics/ram_16x16_dp.vhd":41:9:41:11|Found RAM ram, depth=16, width=16
+@N: CL134 :"/home/mboehmer/VHDL_Pro/trbnet/basics/ram_16x16_dp.vhd":41:9:41:11|Found RAM ram, depth=16, width=16
+Post processing for work.trb_net16_addresses.trb_net16_addresses_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_pattern_gen.vhd":13:7:13:25|Synthesizing work.trb_net_pattern_gen.trb_net_pattern_gen_arch
+Post processing for work.trb_net_pattern_gen.trb_net_pattern_gen_arch
+Post processing for work.trb_net16_regio.trb_net16_regio_arch
+@W: CL170 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":668:6:668:7|Pruning bit <1> of REGISTERS_OUT_write_enable(1 downto 0) - not in use ...
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":10:7:10:24|Synthesizing work.trb_net16_api_base.trb_net16_api_base_arch
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":144:21:144:22|Using sequential encoding for type output_select
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":158:30:158:31|Using sequential encoding for type pas_api_to_apl_state_t
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":161:22:161:23|Using sequential encoding for type state_to_int_t
+@W: CD434 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":626:87:626:103|Signal fifo_to_apl_empty in the sensitivity list is not used in the process
+@W: CD434 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":629:21:629:41|Signal reg_apl_dataready_out in the sensitivity list is not used in the process
+@W: CD434 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":629:44:629:56|Signal slave_running in the sensitivity list is not used in the process
+@W: CD434 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":630:51:630:62|Signal master_start in the sensitivity list is not used in the process
+@W: CD434 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":630:88:630:108|Signal sbuf_to_apl_next_read in the sensitivity list is not used in the process
+@W: CD434 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":699:68:699:83|Signal sequence_counter in the sensitivity list is not used in the process
+@W: CD434 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":700:21:700:32|Signal state_to_apl in the sensitivity list is not used in the process
+@W: CD604 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":982:8:982:30|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":996:8:996:27|OTHERS clause is not synthesized
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":120:9:120:29|Signal next_fifo_to_apl_full is undriven
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":146:26:146:46|Signal next_sequence_counter is undriven
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd":8:7:8:20|Synthesizing work.trb_net16_fifo.arch_trb_net16_fifo
+@W: CD276 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":24:8:24:17|Map for port almostfull of component lattice_ecp2m_fifo_18x1k not found
+@W: CD730 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd":94:4:94:7|Component declaration has 8 ports but entity declares 9 ports
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd":94:4:94:7|Port almostfull of entity work.lattice_ecp2m_fifo_18x1k is unconnected
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":14:7:14:30|Synthesizing work.lattice_ecp2m_fifo_18x1k.structure
+Post processing for work.lattice_ecp2m_fifo_18x1k.structure
+@W: CL168 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":857:4:857:10|Pruning instance r_ctr_5 - not in use ...
+@W: CL168 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":828:4:828:10|Pruning instance w_ctr_5 - not in use ...
+@W: CL168 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":694:4:694:7|Pruning instance FF_1 - not in use ...
+@W: CL168 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":617:4:617:8|Pruning instance FF_12 - not in use ...
+@W: CL168 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":411:4:411:8|Pruning instance INV_1 - not in use ...
+@W: CL168 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":402:4:402:8|Pruning instance INV_4 - not in use ...
+@W: CL168 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":399:4:399:10|Pruning instance AND2_t0 - not in use ...
+Post processing for work.trb_net16_fifo.arch_trb_net16_fifo
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd":8:7:8:20|Synthesizing work.trb_net16_fifo.arch_trb_net16_fifo
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd":94:4:94:7|Port almostfull of entity work.lattice_ecp2m_fifo_18x1k is unconnected
+Post processing for work.trb_net16_fifo.arch_trb_net16_fifo
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":23:7:23:18|Synthesizing work.trb_net_sbuf.trb_net_sbuf_arch
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":58:20:58:21|Using sequential encoding for type buffer_state
+Post processing for work.trb_net_sbuf.trb_net_sbuf_arch
+Post processing for work.trb_net16_api_base.trb_net16_api_base_arch
+@W: CL169 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":596:6:596:7|Pruning Register saved_fifo_to_int_long_packet_num_out(2 downto 0)
+@W: CL169 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":560:6:560:7|Pruning Register last_fifo_to_int_read
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Register bit registered_header_F3(12) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Register bit registered_header_F3(13) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Register bit registered_header_F3(14) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Register bit registered_header_F3(15) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(0) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(1) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(2) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(3) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(4) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(5) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(6) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(7) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(8) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(9) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(10) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(11) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(12) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(13) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(14) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F0(15) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F3(12) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F3(13) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F3(14) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Register bit registered_trailer_F3(15) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Pruning Register bit 15 of registered_trailer_F3(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Pruning Register bit 14 of registered_trailer_F3(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Pruning Register bit 13 of registered_trailer_F3(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Pruning Register bit 12 of registered_trailer_F3(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Pruning Register bit 15 of registered_header_F3(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Pruning Register bit 14 of registered_header_F3(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Pruning Register bit 13 of registered_header_F3(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Pruning Register bit 12 of registered_header_F3(15 downto 0)
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_iobuf.vhd":12:7:12:21|Synthesizing work.trb_net16_iobuf.trb_net16_iobuf_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":10:7:10:20|Synthesizing work.trb_net16_obuf.trb_net16_obuf_arch
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":79:23:79:24|Using sequential encoding for type sending_state_t
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_CRC.vhd":12:7:12:17|Synthesizing work.trb_net_crc.trb_net_crc_arch
+Post processing for work.trb_net_crc.trb_net_crc_arch
+Post processing for work.trb_net16_obuf.trb_net16_obuf_arch
+@N: CL226 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":10:7:10:20|Turning off resource sharing in module trb_net16_obuf (attribute syn_sharing has been specified)
+@W: CL169 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":138:6:138:7|Pruning Register last_buf_INT_READ_OUT
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":435:9:435:10|Register bit max_DATA_COUNT_minus_one(3) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":435:9:435:10|Register bit max_DATA_COUNT_minus_one(4) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":125:8:125:9|Pruning Register bit 1 of int_packet_num_in_i(2 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":125:8:125:9|Pruning Register bit 0 of int_packet_num_in_i(2 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":435:9:435:10|Pruning Register bit 4 of max_DATA_COUNT_minus_one(6 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":435:9:435:10|Pruning Register bit 3 of max_DATA_COUNT_minus_one(6 downto 0)
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":8:7:8:27|Synthesizing work.trb_net16_obuf_nodata.trb_net16_obuf_nodata_arch
+Post processing for work.trb_net16_obuf_nodata.trb_net16_obuf_nodata_arch
+@N: CL226 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":8:7:8:27|Turning off resource sharing in module trb_net16_obuf_nodata (attribute syn_sharing has been specified)
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Register bit buf_MED_DATA_OUT(4) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Register bit buf_MED_DATA_OUT(5) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Register bit buf_MED_DATA_OUT(6) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Register bit buf_MED_DATA_OUT(7) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Register bit buf_MED_DATA_OUT(8) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Register bit buf_MED_DATA_OUT(9) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Register bit buf_MED_DATA_OUT(10) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Register bit buf_MED_DATA_OUT(11) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Register bit buf_MED_DATA_OUT(12) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Register bit buf_MED_DATA_OUT(13) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Register bit buf_MED_DATA_OUT(14) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Register bit buf_MED_DATA_OUT(15) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Pruning Register bit 15 of buf_MED_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Pruning Register bit 14 of buf_MED_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Pruning Register bit 13 of buf_MED_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Pruning Register bit 12 of buf_MED_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Pruning Register bit 11 of buf_MED_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Pruning Register bit 10 of buf_MED_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Pruning Register bit 9 of buf_MED_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Pruning Register bit 8 of buf_MED_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Pruning Register bit 7 of buf_MED_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Pruning Register bit 6 of buf_MED_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Pruning Register bit 5 of buf_MED_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Pruning Register bit 4 of buf_MED_DATA_OUT(15 downto 0)
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":13:7:13:20|Synthesizing work.trb_net16_ibuf.trb_net16_ibuf_arch
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":84:19:84:20|Using sequential encoding for type error_state
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":61:9:61:27|Signal fifo_packet_num_out is undriven
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":70:9:70:28|Signal next_fifo_data_valid is undriven
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":95:9:95:24|Signal fifo_read_before is undriven
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":100:9:100:26|Signal fifo_value_waiting is undriven
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":106:9:106:22|Signal last_fifo_read is undriven
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":107:9:107:23|Signal last_fifo_empty is undriven
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd":8:7:8:20|Synthesizing work.trb_net16_fifo.arch_trb_net16_fifo
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd":94:4:94:7|Port almostfull of entity work.lattice_ecp2m_fifo_18x1k is unconnected
+Post processing for work.trb_net16_fifo.arch_trb_net16_fifo
+Post processing for work.trb_net16_ibuf.trb_net16_ibuf_arch
+@N: CL226 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":13:7:13:20|Turning off resource sharing in module trb_net16_ibuf (attribute syn_sharing has been specified)
+@W: CL169 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":412:6:412:7|Pruning Register reply_word_waiting
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":194:4:194:5|Register bit current_error_state(got_overflow_error) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":194:4:194:5|Pruning Register bit 1 of current_error_state(1 downto 0)
+Post processing for work.trb_net16_iobuf.trb_net16_iobuf_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":12:7:12:24|Synthesizing work.trb_net16_term_buf.trb_net16_term_buf_arch
+Post processing for work.trb_net16_term_buf.trb_net16_term_buf_arch
+@N: CL226 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":12:7:12:24|Turning off resource sharing in module trb_net16_term_buf (attribute syn_sharing has been specified)
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":196:8:196:9|Register bit buf_MED_REPLY_DATA_OUT(2) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":196:8:196:9|Register bit buf_MED_REPLY_DATA_OUT(3) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":196:8:196:9|Register bit buf_MED_REPLY_DATA_OUT(12) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":196:8:196:9|Register bit buf_MED_REPLY_DATA_OUT(13) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":196:8:196:9|Register bit buf_MED_REPLY_DATA_OUT(14) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":196:8:196:9|Register bit buf_MED_REPLY_DATA_OUT(15) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Register bit buf_MED_INIT_DATA_OUT(3) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Register bit buf_MED_INIT_DATA_OUT(4) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Register bit buf_MED_INIT_DATA_OUT(5) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Register bit buf_MED_INIT_DATA_OUT(6) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Register bit buf_MED_INIT_DATA_OUT(7) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Register bit buf_MED_INIT_DATA_OUT(8) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Register bit buf_MED_INIT_DATA_OUT(9) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Register bit buf_MED_INIT_DATA_OUT(10) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Register bit buf_MED_INIT_DATA_OUT(11) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Register bit buf_MED_INIT_DATA_OUT(12) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Register bit buf_MED_INIT_DATA_OUT(13) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Register bit buf_MED_INIT_DATA_OUT(14) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Register bit buf_MED_INIT_DATA_OUT(15) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":196:8:196:9|Pruning Register bit 15 of buf_MED_REPLY_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":196:8:196:9|Pruning Register bit 14 of buf_MED_REPLY_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":196:8:196:9|Pruning Register bit 13 of buf_MED_REPLY_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":196:8:196:9|Pruning Register bit 12 of buf_MED_REPLY_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":196:8:196:9|Pruning Register bit 3 of buf_MED_REPLY_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":196:8:196:9|Pruning Register bit 2 of buf_MED_REPLY_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Pruning Register bit 15 of buf_MED_INIT_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Pruning Register bit 14 of buf_MED_INIT_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Pruning Register bit 13 of buf_MED_INIT_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Pruning Register bit 12 of buf_MED_INIT_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Pruning Register bit 11 of buf_MED_INIT_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Pruning Register bit 10 of buf_MED_INIT_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Pruning Register bit 9 of buf_MED_INIT_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Pruning Register bit 8 of buf_MED_INIT_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Pruning Register bit 7 of buf_MED_INIT_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Pruning Register bit 6 of buf_MED_INIT_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Pruning Register bit 5 of buf_MED_INIT_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Pruning Register bit 4 of buf_MED_INIT_DATA_OUT(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Pruning Register bit 3 of buf_MED_INIT_DATA_OUT(15 downto 0)
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":9:7:9:23|Synthesizing work.trb_net16_ipudata.trb_net16_ipudata_arch
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":66:15:66:16|Using sequential encoding for type state_t
+@W: CD604 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":179:12:179:25|OTHERS clause is not synthesized
+Post processing for work.trb_net16_ipudata.trb_net16_ipudata_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":11:7:11:23|Synthesizing work.trb_net16_trigger.trb_net16_trigger_arch
+Post processing for work.trb_net16_trigger.trb_net16_trigger_arch
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Pruning Register bit 0 of buf_TRG_ERROR_PATTERN_IN(31 downto 0)
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_iobuf.vhd":12:7:12:21|Synthesizing work.trb_net16_iobuf.trb_net16_iobuf_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":10:7:10:20|Synthesizing work.trb_net16_obuf.trb_net16_obuf_arch
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":79:23:79:24|Using sequential encoding for type sending_state_t
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":91:9:91:17|Signal crc_match is undriven
+Post processing for work.trb_net16_obuf.trb_net16_obuf_arch
+@N: CL226 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":10:7:10:20|Turning off resource sharing in module trb_net16_obuf (attribute syn_sharing has been specified)
+@W: CL169 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":138:6:138:7|Pruning Register last_buf_INT_READ_OUT
+@W: CL169 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":125:8:125:9|Pruning Register int_packet_num_in_i(2 downto 0)
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":435:9:435:10|Register bit max_DATA_COUNT_minus_one(3) is always 0, optimizing ...
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":435:9:435:10|Register bit max_DATA_COUNT_minus_one(4) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":435:9:435:10|Pruning Register bit 4 of max_DATA_COUNT_minus_one(6 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":435:9:435:10|Pruning Register bit 3 of max_DATA_COUNT_minus_one(6 downto 0)
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":13:7:13:20|Synthesizing work.trb_net16_ibuf.trb_net16_ibuf_arch
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":84:19:84:20|Using sequential encoding for type error_state
+@W: CD434 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":356:58:356:67|Signal crc_active in the sensitivity list is not used in the process
+@W: CD434 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":357:53:357:65|Signal counter_match in the sensitivity list is not used in the process
+@W: CD434 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":358:10:358:18|Signal crc_match in the sensitivity list is not used in the process
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":61:9:61:27|Signal fifo_packet_num_out is undriven
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":70:9:70:28|Signal next_fifo_data_valid is undriven
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":89:20:89:29|Signal crc_enable is undriven
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":91:9:91:15|Signal crc_out is undriven
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":95:9:95:24|Signal fifo_read_before is undriven
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":100:9:100:26|Signal fifo_value_waiting is undriven
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":106:9:106:22|Signal last_fifo_read is undriven
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":107:9:107:23|Signal last_fifo_empty is undriven
+Post processing for work.trb_net16_ibuf.trb_net16_ibuf_arch
+@N: CL226 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":13:7:13:20|Turning off resource sharing in module trb_net16_ibuf (attribute syn_sharing has been specified)
+@W: CL240 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":89:20:89:29|CRC_enable is not assigned a value (floating) - a simulation mismatch is possible
+@W: CL169 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":412:6:412:7|Pruning Register reply_word_waiting
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":194:4:194:5|Register bit current_error_state(got_overflow_error) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":194:4:194:5|Pruning Register bit 1 of current_error_state(1 downto 0)
+Post processing for work.trb_net16_iobuf.trb_net16_iobuf_arch
+Post processing for work.trb_net16_endpoint_hades_full.trb_net16_endpoint_hades_full_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":14:7:14:31|Synthesizing work.trb_net16_med_ecp_sfp_gbe.med_ecp_sfp
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":927:0:927:19|Port almost_full_out of entity work.trb_net_fifo_16bit_bram_dualport is unconnected
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":927:0:927:19|Port almost_empty_out of entity work.trb_net_fifo_16bit_bram_dualport is unconnected
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":927:0:927:19|Port valid_read_out of entity work.trb_net_fifo_16bit_bram_dualport is unconnected
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":927:0:927:19|Port fifostatus_out of entity work.trb_net_fifo_16bit_bram_dualport is unconnected
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":1027:0:1027:19|Port almost_full_out of entity work.trb_net_fifo_16bit_bram_dualport is unconnected
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":1027:0:1027:19|Port almost_empty_out of entity work.trb_net_fifo_16bit_bram_dualport is unconnected
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":1027:0:1027:19|Port valid_read_out of entity work.trb_net_fifo_16bit_bram_dualport is unconnected
+@W: CD326 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":1027:0:1027:19|Port fifostatus_out of entity work.trb_net_fifo_16bit_bram_dualport is unconnected
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":424:9:424:16|Signal link_led is undriven
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":427:9:427:16|Signal info_led is undriven
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd":8:7:8:38|Synthesizing work.trb_net_fifo_16bit_bram_dualport.trb_net_fifo_16bit_bram_dualport_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":14:7:14:39|Synthesizing work.lattice_ecp2m_fifo_16bit_dualport.structure
+Post processing for work.lattice_ecp2m_fifo_16bit_dualport.structure
+Post processing for work.trb_net_fifo_16bit_bram_dualport.trb_net_fifo_16bit_bram_dualport_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd":1275:7:1275:18|Synthesizing work.serdes_gbe_2.serdes_gbe_2_arch
+@W: CD638 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd":1752:7:1752:9|Signal cin is undriven
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd":1327:10:1327:13|Synthesizing work.pcsc.syn_black_box
+Post processing for work.pcsc.syn_black_box
+Post processing for work.serdes_gbe_2.serdes_gbe_2_arch
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd":16:7:16:23|Synthesizing work.trb_net16_lsm_sfp.lsm_sfp
+@N: CD233 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd":46:12:46:13|Using sequential encoding for type states
+@W: CD604 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd":344:4:344:18|OTHERS clause is not synthesized
+@W: CD604 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd":377:4:377:18|OTHERS clause is not synthesized
+Post processing for work.trb_net16_lsm_sfp.lsm_sfp
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd":120:2:120:3|Pruning Register bit 3 of cv_ctr(3 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd":120:2:120:3|Pruning Register bit 2 of cv_ctr(3 downto 0)
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/basics/signal_sync.vhd":8:7:8:17|Synthesizing work.signal_sync.behavioral
+Post processing for work.signal_sync.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/basics/signal_sync.vhd":8:7:8:17|Synthesizing work.signal_sync.behavioral
+Post processing for work.signal_sync.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/basics/signal_sync.vhd":8:7:8:17|Synthesizing work.signal_sync.behavioral
+Post processing for work.signal_sync.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/trbnet/basics/signal_sync.vhd":8:7:8:17|Synthesizing work.signal_sync.behavioral
+Post processing for work.signal_sync.behavioral
+Post processing for work.trb_net16_med_ecp_sfp_gbe.med_ecp_sfp
+@N: CL226 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":14:7:14:31|Turning off resource sharing in module trb_net16_med_ecp_sfp_gbe (attribute syn_sharing has been specified)
+@W: CL169 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":476:6:476:7|Pruning Register pwr_up
+Post processing for work.rich_trb.rich_arch
+@W: CL240 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/rich_trb.vhd":70:1:70:12|TICK_10S_OUT is not assigned a value (floating) - a simulation mismatch is possible
+@W: CL169 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/rich_trb.vhd":305:1:305:2|Pruning Register tick_10s
+@W: CL169 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/rich_trb.vhd":305:1:305:2|Pruning Register rst_counter_10s
+@W: CL169 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/rich_trb.vhd":305:1:305:2|Pruning Register counter_10s(13 downto 0)
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/sync_pll_40m.vhd":14:7:14:18|Synthesizing work.sync_pll_40m.structure
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/sync_pll_40m.vhd":36:14:36:18|Unbound component EPLLD mapped to black box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/sync_pll_40m.vhd":36:14:36:18|Synthesizing work.eplld.syn_black_box
+Post processing for work.eplld.syn_black_box
+Post processing for work.sync_pll_40m.structure
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/dll_100m.vhd":14:7:14:14|Synthesizing work.dll_100m.structure
+@W: CD280 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/dll_100m.vhd":35:14:35:20|Unbound component CIDDLLA mapped to black box
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/dll_100m.vhd":35:14:35:20|Synthesizing work.ciddlla.syn_black_box
+Post processing for work.ciddlla.syn_black_box
+Post processing for work.dll_100m.structure
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/pll_40m.vhd":14:7:14:13|Synthesizing work.pll_40m.structure
+Post processing for work.pll_40m.structure
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/reboot_handler.vhd":8:7:8:20|Synthesizing work.reboot_handler.behavioral
+Post processing for work.reboot_handler.behavioral
+@N: CD630 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/reset_handler.vhd":11:7:11:19|Synthesizing work.reset_handler.behavioral
+Post processing for work.reset_handler.behavioral
+Post processing for work.adcmv3.adcmv3
+@W: CL170 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adcmv3.vhd":1326:1:1326:2|Pruning bit <3> of bp_sector_q(3 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adcmv3.vhd":1326:1:1326:2|Pruning bit <3> of bp_sector_qq(3 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adcmv3.vhd":1326:1:1326:2|Pruning bit <3> of bp_module_q(3 downto 0) - not in use ...
+@W: CL170 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adcmv3.vhd":1326:1:1326:2|Pruning bit <3> of bp_module_qq(3 downto 0) - not in use ...
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/basics/signal_sync.vhd":16:4:16:7|Input CLK1 is unused
+@N: CL177 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd":135:2:135:3|Sharing sequential element tx_allow.
+@N: CL201 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd":135:2:135:3|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 10 reachable states with original encodings of:
+ 0000
+ 0001
+ 0010
+ 0011
+ 0100
+ 0101
+ 0110
+ 0111
+ 1000
+ 1001
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd":23:4:23:16|Input SD_LINK_OK_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd":24:4:24:12|Input SD_LOS_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd":38:4:38:10|Input CTRL_OP is unused
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":1050:4:1050:5|Register bit tx_correct(0) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":1050:4:1050:5|Pruning Register bit 0 of tx_correct(1 downto 0)
+@W: CL247 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":28:4:28:20|Input port bit 1 of med_packet_num_in(2 downto 0) is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":25:4:25:9|Input CLK_EN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":34:4:34:14|Input MED_READ_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":41:4:41:17|Input SD_REFCLK_P_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":42:4:42:17|Input SD_REFCLK_N_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":50:4:50:13|Input CTRL_DEBUG is unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":48:4:48:12|Input port bits 15 to 1 of ctrl_stat(15 downto 0) are unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":42:4:42:20|Input INT_REPLY_READ_IN is unused
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":435:9:435:10|Pruning Register bit 6 of max_DATA_COUNT_minus_one(6 downto 5)
+@N: CL201 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":392:6:392:7|Trying to extract state machine for register sending_state
+Extracted state machine for register sending_state
+State machine has 3 reachable states with original encodings of:
+ 00
+ 01
+ 10
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":35:4:35:14|Input port bits 15 to 10 of ctrl_buffer(31 downto 0) are unused
+@W: CL247 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":35:4:35:14|Input port bit 7 of ctrl_buffer(31 downto 0) is unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":36:4:36:16|Input port bits 15 to 3 of ctrl_settings(15 downto 0) are unused
+@W: CL247 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":38:4:38:17|Input port bit 0 of timer_ticks_in(1 downto 0) is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":31:4:31:20|Input INT_PACKET_NUM_IN is unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_iobuf.vhd":74:4:74:21|Input port bits 15 to 0 of ctrl_obuf_settings(31 downto 0) are unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_iobuf.vhd":55:4:55:24|Input INT_INIT_DATAREADY_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_iobuf.vhd":56:4:56:19|Input INT_INIT_DATA_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_iobuf.vhd":57:4:57:25|Input INT_INIT_PACKET_NUM_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_iobuf.vhd":73:4:73:11|Input CTRL_GEN is unused
+@W: CL247 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":42:4:42:23|Input port bit 0 of trg_error_pattern_in(31 downto 0) is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":23:4:23:9|Input CLK_EN is unused
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":302:6:302:7|Register bit packet_number(2) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":302:6:302:7|Pruning Register bit 2 of packet_number(2 downto 0)
+@N: CL201 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":95:6:95:7|Trying to extract state machine for register state
+Extracted state machine for register state
+State machine has 4 reachable states with original encodings of:
+ 00
+ 01
+ 10
+ 11
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":51:4:51:23|Input port bits 18 to 16 of ipu_error_pattern_in(31 downto 0) are unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":14:4:14:9|Input CLK_EN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":31:4:31:13|Input API_RUN_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":32:4:32:15|Input API_SEQNR_IN is unused
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":183:8:183:9|Pruning Register bit 2 of buf_MED_INIT_DATA_OUT(2 downto 0)
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":30:4:30:14|Input port bits 15 to 12 of med_data_in(15 downto 0) are unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd":16:6:16:11|Input CLK_EN is unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":48:4:48:12|Input port bits 15 to 1 of ctrl_stat(15 downto 0) are unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":42:4:42:20|Input INT_REPLY_READ_IN is unused
+@N: CL201 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Trying to extract state machine for register buf_MED_PACKET_NUM_OUT
+Extracted state machine for register buf_MED_PACKET_NUM_OUT
+State machine has 8 reachable states with original encodings of:
+ 000
+ 001
+ 010
+ 011
+ 100
+ 101
+ 110
+ 111
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":21:4:21:14|Input port bits 31 to 9 of ctrl_buffer(31 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":21:4:21:14|Input port bits 7 to 4 of ctrl_buffer(31 downto 0) are unused
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":435:9:435:10|Pruning Register bit 6 of max_DATA_COUNT_minus_one(6 downto 5)
+@N: CL201 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":392:6:392:7|Trying to extract state machine for register sending_state
+Extracted state machine for register sending_state
+State machine has 3 reachable states with original encodings of:
+ 00
+ 01
+ 10
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":31:4:31:20|Input port bits 1 to 0 of int_packet_num_in(2 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":35:4:35:14|Input port bits 15 to 10 of ctrl_buffer(31 downto 0) are unused
+@W: CL247 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":35:4:35:14|Input port bit 7 of ctrl_buffer(31 downto 0) is unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":36:4:36:16|Input port bits 15 to 3 of ctrl_settings(15 downto 0) are unused
+@W: CL247 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":38:4:38:17|Input port bit 0 of timer_ticks_in(1 downto 0) is unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_iobuf.vhd":74:4:74:21|Input port bits 15 to 0 of ctrl_obuf_settings(31 downto 0) are unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_iobuf.vhd":55:4:55:24|Input INT_INIT_DATAREADY_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_iobuf.vhd":56:4:56:19|Input INT_INIT_DATA_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_iobuf.vhd":57:4:57:25|Input INT_INIT_PACKET_NUM_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_iobuf.vhd":73:4:73:11|Input CTRL_GEN is unused
+@N: CL201 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":218:4:218:5|Trying to extract state machine for register current_buffer_state
+Extracted state machine for register current_buffer_state
+State machine has 3 reachable states with original encodings of:
+ 00
+ 01
+ 10
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd":16:6:16:11|Input CLK_EN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd":16:6:16:11|Input CLK_EN is unused
+@N: CL201 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":787:6:787:7|Trying to extract state machine for register state_to_apl
+Extracted state machine for register state_to_apl
+State machine has 4 reachable states with original encodings of:
+ 00
+ 01
+ 10
+ 11
+@N: CL201 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":787:6:787:7|Trying to extract state machine for register state_to_int
+Extracted state machine for register state_to_int
+State machine has 6 reachable states with original encodings of:
+ 000
+ 001
+ 010
+ 011
+ 100
+ 101
+@W: CL247 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":33:4:33:20|Input port bit 1 of apl_packet_num_in(2 downto 0) is unused
+@W: CL247 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":38:4:38:23|Input port bit 0 of apl_error_pattern_in(31 downto 0) is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":40:4:40:24|Input APL_TARGET_ADDRESS_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":65:4:65:26|Input INT_MASTER_DATAREADY_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":66:4:66:21|Input INT_MASTER_DATA_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":67:4:67:27|Input INT_MASTER_PACKET_NUM_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":73:4:73:20|Input INT_SLAVE_READ_IN is unused
+@N: CL201 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_addresses.vhd":246:6:246:7|Trying to extract state machine for register state
+Extracted state machine for register state
+State machine has 5 reachable states with original encodings of:
+ 000
+ 001
+ 010
+ 011
+ 100
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/basics/rom_16x8.vhd":42:6:42:7|Pruning Register bit 15 of dout(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/basics/rom_16x8.vhd":42:6:42:7|Pruning Register bit 14 of dout(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/basics/rom_16x8.vhd":42:6:42:7|Pruning Register bit 13 of dout(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/basics/rom_16x8.vhd":42:6:42:7|Pruning Register bit 11 of dout(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/basics/rom_16x8.vhd":42:6:42:7|Pruning Register bit 9 of dout(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/basics/rom_16x8.vhd":42:6:42:7|Pruning Register bit 7 of dout(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/basics/rom_16x8.vhd":42:6:42:7|Pruning Register bit 6 of dout(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/basics/rom_16x8.vhd":42:6:42:7|Pruning Register bit 5 of dout(15 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/basics/rom_16x8.vhd":42:6:42:7|Pruning Register bit 4 of dout(15 downto 0)
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":720:6:720:7|Register bit packet_counter(2) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":720:6:720:7|Pruning Register bit 2 of packet_counter(2 downto 0)
+@N: CL201 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":668:6:668:7|Trying to extract state machine for register current_state
+Extracted state machine for register current_state
+State machine has 19 reachable states with original encodings of:
+ 00000
+ 00001
+ 00010
+ 00011
+ 00100
+ 00101
+ 00110
+ 00111
+ 01000
+ 01001
+ 01010
+ 01011
+ 01100
+ 01101
+ 01110
+ 01111
+ 10000
+ 10001
+ 10010
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":54:4:54:13|Input API_RUN_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":55:4:55:15|Input API_SEQNR_IN is unused
+@N: CL201 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_onewire.vhd":291:6:291:7|Trying to extract state machine for register state
+@N: CL201 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":218:4:218:5|Trying to extract state machine for register current_buffer_state
+Extracted state machine for register current_buffer_state
+State machine has 3 reachable states with original encodings of:
+ 00
+ 01
+ 10
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_io_multiplexer.vhd":98:8:98:9|Pruning Register bit 11 of buf_INT_PACKET_NUM_OUT(11 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_io_multiplexer.vhd":98:8:98:9|Pruning Register bit 10 of buf_INT_PACKET_NUM_OUT(11 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_io_multiplexer.vhd":98:8:98:9|Pruning Register bit 9 of buf_INT_PACKET_NUM_OUT(11 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_io_multiplexer.vhd":98:8:98:9|Pruning Register bit 8 of buf_INT_PACKET_NUM_OUT(11 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_io_multiplexer.vhd":98:8:98:9|Pruning Register bit 7 of buf_INT_PACKET_NUM_OUT(11 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_io_multiplexer.vhd":98:8:98:9|Pruning Register bit 6 of buf_INT_PACKET_NUM_OUT(11 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_io_multiplexer.vhd":98:8:98:9|Pruning Register bit 5 of buf_INT_PACKET_NUM_OUT(11 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_io_multiplexer.vhd":98:8:98:9|Pruning Register bit 4 of buf_INT_PACKET_NUM_OUT(11 downto 0)
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_io_multiplexer.vhd":98:8:98:9|Pruning Register bit 3 of buf_INT_PACKET_NUM_OUT(11 downto 0)
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_io_multiplexer.vhd":41:4:41:7|Input port bits 31 to 10 of ctrl(31 downto 0) are unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_io_multiplexer.vhd":33:4:33:14|Input INT_READ_IN is unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":105:4:105:27|Input port bits 47 to 20 of regio_common_stat_reg_in(63 downto 0) are unused
+@W: CL247 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":105:4:105:27|Input port bit 8 of regio_common_stat_reg_in(63 downto 0) is unused
+@W: CL247 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":105:4:105:27|Input port bit 4 of regio_common_stat_reg_in(63 downto 0) is unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":144:4:144:17|Input port bits 95 to 64 of iobuf_ctrl_gen(127 downto 0) are unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":125:4:125:22|Input REGIO_IDRAM_DATA_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":127:4:127:22|Input REGIO_IDRAM_ADDR_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":128:4:128:20|Input REGIO_IDRAM_WR_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":130:4:130:27|Input REGIO_ONEWIRE_MONITOR_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":132:4:132:24|Input REGIO_VAR_ENDPOINT_ID is unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/rich_trb.vhd":27:1:27:18|Input port bits 31 to 20 of common_stat_reg_in(63 downto 0) are unused
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_ped_thr_mem.vhd":132:1:132:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 10 reachable states with original encodings of:
+ 0000
+ 0001
+ 0010
+ 0011
+ 0100
+ 0101
+ 0110
+ 0111
+ 1000
+ 1001
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_ped_thr_mem.vhd":18:1:18:11|Input port bits 31 to 18 of slv_data_in(31 downto 0) are unused
+@N: CL177 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_sendb.vhd":159:1:159:2|Sharing sequential element shift_o.
+@N: CL177 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_sendb.vhd":159:1:159:2|Sharing sequential element rst_bit.
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_sendb.vhd":159:1:159:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 7 reachable states with original encodings of:
+ 000
+ 001
+ 010
+ 011
+ 100
+ 101
+ 110
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_gstart.vhd":79:1:79:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 11 reachable states with original encodings of:
+ 0000
+ 0001
+ 0010
+ 0011
+ 0100
+ 0101
+ 0110
+ 0111
+ 1000
+ 1001
+ 1010
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_slim.vhd":116:1:116:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 19 reachable states with original encodings of:
+ 00000
+ 00001
+ 00010
+ 00011
+ 00100
+ 00101
+ 00110
+ 00111
+ 01000
+ 01001
+ 01010
+ 01011
+ 01100
+ 01101
+ 01110
+ 01111
+ 10000
+ 10001
+ 10010
+@W: CL247 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_slim.vhd":20:1:20:10|Input port bit 7 of i2c_adr_in(7 downto 0) is unused
+@W: CL247 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_slim.vhd":21:1:21:10|Input port bit 0 of i2c_cmd_in(7 downto 0) is unused
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":95:1:95:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 8 reachable states with original encodings of:
+ 000
+ 001
+ 010
+ 011
+ 100
+ 101
+ 110
+ 111
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/onewire_master.vhd":145:1:145:2|Trying to extract state machine for register STATE
+Extracted state machine for register STATE
+State machine has 15 reachable states with original encodings of:
+ 0000
+ 0001
+ 0010
+ 0011
+ 0100
+ 0101
+ 0110
+ 0111
+ 1000
+ 1001
+ 1010
+ 1011
+ 1100
+ 1101
+ 1110
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_memory.vhd":111:1:111:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 7 reachable states with original encodings of:
+ 000
+ 001
+ 010
+ 011
+ 100
+ 101
+ 110
+@W: CL189 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_slim.vhd":551:4:551:5|Register bit rx_bit_cnt(3) is always 0, optimizing ...
+@W: CL260 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_slim.vhd":551:4:551:5|Pruning Register bit 3 of rx_bit_cnt(3 downto 0)
+@N: CL201 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_slim.vhd":225:4:225:5|Trying to extract state machine for register STATE
+Extracted state machine for register STATE
+State machine has 16 reachable states with original encodings of:
+ 00000
+ 00001
+ 00010
+ 00011
+ 00100
+ 00101
+ 00110
+ 00111
+ 01000
+ 01001
+ 01010
+ 01011
+ 01101
+ 01110
+ 01111
+ 10000
+@N: CL201 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":110:2:110:3|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 8 reachable states with original encodings of:
+ 000
+ 001
+ 010
+ 011
+ 100
+ 101
+ 110
+ 111
+@N: CL201 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_databus_memory.vhd":61:6:61:7|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 6 reachable states with original encodings of:
+ 000
+ 001
+ 010
+ 011
+ 100
+ 101
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_real_slim.vhd":138:1:138:2|Trying to extract state machine for register STATE
+Extracted state machine for register STATE
+State machine has 4 reachable states with original encodings of:
+ 00
+ 01
+ 10
+ 11
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":96:1:96:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 8 reachable states with original encodings of:
+ 000
+ 001
+ 010
+ 011
+ 100
+ 101
+ 110
+ 111
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":21:1:21:11|Input port bits 23 to 8 of slv_data_in(31 downto 0) are unused
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":148:1:148:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 10 reachable states with original encodings of:
+ 0000
+ 0001
+ 0010
+ 0011
+ 0100
+ 0101
+ 0110
+ 0111
+ 1000
+ 1001
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":21:1:21:11|Input port bits 31 to 16 of slv_data_in(31 downto 0) are unused
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":58:1:58:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 10 reachable states with original encodings of:
+ 0000
+ 0001
+ 0010
+ 0011
+ 0100
+ 0101
+ 0110
+ 0111
+ 1000
+ 1001
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status.vhd":42:1:42:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 10 reachable states with original encodings of:
+ 0000
+ 0001
+ 0010
+ 0011
+ 0100
+ 0101
+ 0110
+ 0111
+ 1000
+ 1001
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":65:1:65:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 8 reachable states with original encodings of:
+ 000
+ 001
+ 010
+ 011
+ 100
+ 101
+ 110
+ 111
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":65:1:65:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 8 reachable states with original encodings of:
+ 000
+ 001
+ 010
+ 011
+ 100
+ 101
+ 110
+ 111
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":60:1:60:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 6 reachable states with original encodings of:
+ 000
+ 001
+ 010
+ 011
+ 100
+ 101
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":21:1:21:11|Input port bits 31 to 16 of slv_data_in(31 downto 0) are unused
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":70:1:70:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 10 reachable states with original encodings of:
+ 0000
+ 0001
+ 0010
+ 0011
+ 0100
+ 0101
+ 0110
+ 0111
+ 1000
+ 1001
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":19:1:19:11|Input port bits 31 to 16 of slv_data_in(31 downto 0) are unused
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":65:1:65:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 8 reachable states with original encodings of:
+ 000
+ 001
+ 010
+ 011
+ 100
+ 101
+ 110
+ 111
+@N: CL177 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":197:1:197:2|Sharing sequential element set_hdr.
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":197:1:197:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 10 reachable states with original encodings of:
+ 0000
+ 0001
+ 0010
+ 0011
+ 0100
+ 0101
+ 0110
+ 0111
+ 1000
+ 1001
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":38:1:38:14|Input port bits 39 to 38 of fifo_0_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":39:1:39:14|Input port bits 39 to 38 of fifo_1_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":40:1:40:14|Input port bits 39 to 38 of fifo_2_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":41:1:41:14|Input port bits 39 to 38 of fifo_3_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":42:1:42:14|Input port bits 39 to 38 of fifo_4_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":43:1:43:14|Input port bits 39 to 38 of fifo_5_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":44:1:44:14|Input port bits 39 to 38 of fifo_6_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":45:1:45:14|Input port bits 39 to 38 of fifo_7_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":46:1:46:14|Input port bits 39 to 38 of fifo_8_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":47:1:47:14|Input port bits 39 to 38 of fifo_9_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":48:1:48:15|Input port bits 39 to 38 of fifo_10_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":49:1:49:15|Input port bits 39 to 38 of fifo_11_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":50:1:50:15|Input port bits 39 to 38 of fifo_12_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":51:1:51:15|Input port bits 39 to 38 of fifo_13_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":52:1:52:15|Input port bits 39 to 38 of fifo_14_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":53:1:53:15|Input port bits 39 to 38 of fifo_15_data_in(39 downto 0) are unused
+@W: CL157 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":27:1:27:21|Output IPU_ERROR_PATTERN_OUT has undriven bits - a simulation mismatch is possible
+@W: CL159 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":20:1:20:18|Input IPU_INFORMATION_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":33:1:33:13|Input DHDR_STORE_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":36:1:36:13|Input FIFO_START_IN is unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":20:1:20:10|Input port bits 11 to 9 of frame_0_in(11 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":21:1:21:10|Input port bits 11 to 9 of frame_1_in(11 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":22:1:22:10|Input port bits 11 to 9 of frame_2_in(11 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":23:1:23:10|Input port bits 11 to 9 of frame_3_in(11 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":24:1:24:10|Input port bits 11 to 9 of frame_4_in(11 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":25:1:25:10|Input port bits 11 to 9 of frame_5_in(11 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":26:1:26:10|Input port bits 11 to 9 of frame_6_in(11 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":27:1:27:10|Input port bits 11 to 9 of frame_7_in(11 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":28:1:28:10|Input port bits 11 to 9 of frame_8_in(11 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":29:1:29:10|Input port bits 11 to 9 of frame_9_in(11 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":30:1:30:11|Input port bits 11 to 9 of frame_10_in(11 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":31:1:31:11|Input port bits 11 to 9 of frame_11_in(11 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":32:1:32:11|Input port bits 11 to 9 of frame_12_in(11 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":33:1:33:11|Input port bits 11 to 9 of frame_13_in(11 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":34:1:34:11|Input port bits 11 to 9 of frame_14_in(11 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":35:1:35:11|Input port bits 11 to 9 of frame_15_in(11 downto 0) are unused
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 9 reachable states with original encodings of:
+ 0000
+ 0001
+ 0010
+ 0011
+ 0100
+ 0101
+ 0110
+ 0111
+ 1000
+@W: CL247 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":19:1:19:10|Input port bit 6 of buf_lvl_in(7 downto 0) is unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":24:1:24:11|Input port bits 39 to 32 of eds_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":24:1:24:11|Input port bits 15 to 12 of eds_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":24:1:24:11|Input port bits 7 to 0 of eds_data_in(39 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":34:1:34:11|Input port bits 6 to 1 of raw_addr_in(6 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":35:1:35:11|Input port bits 37 to 27 of raw_data_in(37 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":35:1:35:11|Input port bits 17 to 14 of raw_data_in(37 downto 0) are unused
+@W: CL247 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":36:1:36:11|Input port bit 17 of ped_data_in(17 downto 0) is unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":36:1:36:11|Input port bits 15 to 12 of ped_data_in(17 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":37:1:37:11|Input port bits 17 to 12 of thr_data_in(17 downto 0) are unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":22:1:22:14|Input LOC_FRM_CTR_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":23:1:23:14|Input EDS_FRM_CTR_IN is unused
+@W: CL159 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":27:1:27:13|Input BUF_IGNORE_IN is unused
+@N: CL135 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":653:1:653:2|Found seqShift thr_addr, depth=3, width=7
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":369:1:369:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 30 reachable states with original encodings of:
+ 00000
+ 00001
+ 00010
+ 00011
+ 00100
+ 00101
+ 00110
+ 00111
+ 01000
+ 01001
+ 01010
+ 01011
+ 01100
+ 01101
+ 01110
+ 01111
+ 10000
+ 10001
+ 10010
+ 10011
+ 10100
+ 10101
+ 10110
+ 10111
+ 11000
+ 11001
+ 11010
+ 11011
+ 11100
+ 11101
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 22 reachable states with original encodings of:
+ 00000
+ 00001
+ 00010
+ 00011
+ 00100
+ 00101
+ 00110
+ 00111
+ 01000
+ 01001
+ 01010
+ 01011
+ 01100
+ 01101
+ 01110
+ 01111
+ 10000
+ 10001
+ 10010
+ 10011
+ 10100
+ 10101
+@N: CL177 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":350:1:350:2|Sharing sequential element rst_local.
+@N: CL177 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":350:1:350:2|Sharing sequential element store_local.
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":350:1:350:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 17 reachable states with original encodings of:
+ 00000
+ 00001
+ 00010
+ 00011
+ 00100
+ 00101
+ 00110
+ 00111
+ 01000
+ 01001
+ 01010
+ 01011
+ 01100
+ 01101
+ 01110
+ 01111
+ 10000
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":27:1:27:9|Input port bits 2 to 1 of sector_in(2 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":32:1:32:12|Input port bits 23 to 11 of trb_tinfo_in(23 downto 0) are unused
+@W: CL246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":32:1:32:12|Input port bits 6 to 1 of trb_tinfo_in(23 downto 0) are unused
+@N: CL177 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":75:1:75:2|Sharing sequential element delay_ctr_ld.
+@W: CL169 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":75:1:75:2|Pruning Register todo_ctr_ce
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":75:1:75:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 7 reachable states with original encodings of:
+ 000
+ 001
+ 010
+ 011
+ 100
+ 101
+ 110
+@N: CL201 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_sync_handler.vhd":62:1:62:2|Trying to extract state machine for register CURRENT_STATE
+Extracted state machine for register CURRENT_STATE
+State machine has 10 reachable states with original encodings of:
+ 0000
+ 0001
+ 0010
+ 0011
+ 0100
+ 0101
+ 0110
+ 0111
+ 1000
+ 1001
+@W: CL247 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adcmv3.vhd":68:1:68:9|Input port bit 3 of bp_module(3 downto 0) is unused
+@W: CL247 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adcmv3.vhd":69:1:69:9|Input port bit 3 of bp_sector(3 downto 0) is unused
+@END
+Process took 0h:00m:15s realtime, 0h:00m:15s cputime
+# Mon Jun 14 22:08:15 2010
+
+###########################################################]
+Synopsys Generic Technology Mapper, Version map510rc, Build 066R, Built Feb 19 2010 21:25:50
+Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved
+Product Version D-2010.03
+@N: MF249 |Running in 32-bit mode.
+@N: MF257 |Gated clock conversion enabled
+@N|Running in logic synthesis mode without enhanced optimization
+@W: FX474 |User specified initial value found in some of the sequential elements in the design. Applying an initial value to a register may not deliver the best synthesis results. For example, registers with initial values may be preserved and retiming/pipelining may not be performed. To improve synthesis results you may want to remove the register initialization from the RTL code
+@W: BN287 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_io_multiplexer.vhd":258:6:258:7|Register current_mux_packet_number[2:0] with reset has an initial value of 1. Ignoring initial value.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_a of instance adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_b of instance adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_a of instance adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_b of instance adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":150:4:150:26|Expect property csdecode_a of instance spi_dpram_32_to_8_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":150:4:150:26|Expect property csdecode_b of instance spi_dpram_32_to_8_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":198:4:198:26|Expect property csdecode_a of instance spi_dpram_32_to_8_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":198:4:198:26|Expect property csdecode_b of instance spi_dpram_32_to_8_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_dpram.vhd":140:4:140:26|Expect property csdecode_a of instance slv_onewire_dpram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_dpram.vhd":140:4:140:26|Expect property csdecode_b of instance slv_onewire_dpram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_dpram.vhd":140:4:140:26|Expect property csdecode_a of instance slv_onewire_dpram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_dpram.vhd":140:4:140:26|Expect property csdecode_b of instance slv_onewire_dpram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_a of instance adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_b of instance adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":150:4:150:26|Expect property csdecode_a of instance spi_dpram_32_to_8_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":150:4:150:26|Expect property csdecode_b of instance spi_dpram_32_to_8_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":198:4:198:26|Expect property csdecode_a of instance spi_dpram_32_to_8_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":198:4:198:26|Expect property csdecode_b of instance spi_dpram_32_to_8_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: MO111 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":27:1:27:21|tristate driver IPU_ERROR_PATTERN_OUT_1 on net IPU_ERROR_PATTERN_OUT_1 has its enable tied to GND (module ipu_fifo_stage)
+Automatic dissolve during optimization of view:work.apv_locker(behavioral) of THE_APVON_SYNCER(state_sync)
+Automatic dissolve during optimization of view:work.apv_raw_buffer(behavioral) of THE_APV_ADCOK_SYNC(state_sync_0)
+Automatic dissolve during optimization of view:work.apv_raw_buffer(behavioral) of THE_APV_LOCKED_SYNC(state_sync_0)
+Automatic dissolve during optimization of view:work.apv_raw_buffer(behavioral) of THE_APV_ON_SYNC(state_sync_0)
+Automatic dissolve during optimization of view:work.apv_raw_buffer_GEN_ADC1\.11\.THE_APV_RAW_BUFFER(behavioral) of THE_APV_ADCOK_SYNC(state_sync_0)
+Automatic dissolve during optimization of view:work.apv_raw_buffer_GEN_ADC1\.11\.THE_APV_RAW_BUFFER(behavioral) of THE_APV_LOCKED_SYNC(state_sync_0)
+Automatic dissolve during optimization of view:work.apv_raw_buffer_GEN_ADC1\.11\.THE_APV_RAW_BUFFER(behavioral) of THE_APV_ON_SYNC(state_sync_0)
+Automatic dissolve during optimization of view:work.raw_buf_stage(behavioral) of THE_RESET_SYNC(state_sync)
+Automatic dissolve during optimization of view:work.adc_data_handler_THE_ADC1_HANDLER(behavioral) of THE_RESET_SYNC(state_sync_THE_RESET_SYNC_1)
+Automatic dissolve during optimization of view:work.adc_crossover_THE_ADC1_CROSSOVER(behavioral) of THE_RESET_STATE_SYNC(state_sync)
+Automatic dissolve during optimization of view:work.adc_channel_select(behavioral) of THE_SEL0_SYNC(state_sync)
+Automatic dissolve during optimization of view:work.adc_channel_select(behavioral) of THE_SEL1_SYNC(state_sync)
+Automatic dissolve during optimization of view:work.adc_channel_select(behavioral) of THE_SEL2_SYNC(state_sync)
+Automatic dissolve during optimization of view:work.adc_channel_select(behavioral) of THE_RESET_SYNC(state_sync)
+Automatic dissolve during optimization of view:work.adc_data_handler_THE_ADC0_HANDLER(behavioral) of THE_RESET_SYNC(state_sync_THE_RESET_SYNC_3_THE_RESET_SYNC_0)
+Automatic dissolve during optimization of view:work.adc_crossover_THE_ADC0_CROSSOVER(behavioral) of THE_RESET_STATE_SYNC(state_sync)
+Automatic dissolve during optimization of view:work.real_trg_handler(behavioral) of THE_TIME_TRG_0_SYNC(state_sync_0)
+Automatic dissolve during optimization of view:work.real_trg_handler(behavioral) of THE_TIME_TRG_1_SYNC(state_sync_0)
+Automatic dissolve during optimization of view:work.real_trg_handler(behavioral) of THE_TIME_TRG_2_SYNC(state_sync_0)
+Automatic dissolve during optimization of view:work.real_trg_handler(behavioral) of THE_TIME_TRG_3_SYNC(state_sync_0)
+Automatic dissolve during optimization of view:work.apv_trgctrl(behavioral) of THE_RESET_SYNC(state_sync)
+Automatic dissolve during optimization of view:work.trb_net16_med_ecp_sfp_gbe(med_ecp_sfp) of THE_FIFO_FPGA_TO_SFP(trb_net_fifo_16bit_bram_dualport)
+Automatic dissolve during optimization of view:work.trb_net16_med_ecp_sfp_gbe(med_ecp_sfp) of THE_FIFO_SFP_TO_FPGA(trb_net_fifo_16bit_bram_dualport)
+Automatic dissolve during optimization of view:work.trb_net16_ibuf_6_1_1_0_0_1_0(trb_net16_ibuf_arch) of gen_init_sbuf\.SBUF_INIT(trb_net16_sbuf)
+Automatic dissolve during optimization of view:work.trb_net16_ibuf_6_1_1_0_0_1_0(trb_net16_ibuf_arch) of THE_FIFO(trb_net16_fifoZ0)
+Automatic dissolve during optimization of view:work.trb_net16_obuf_1_0_7_0(trb_net16_obuf_arch) of THE_SBUF(trb_net16_sbuf)
+Automatic dissolve during optimization of view:work.trb_net16_ibuf_6_1_1_1_0_1_0(trb_net16_ibuf_arch) of gen_init_sbuf\.SBUF_INIT(trb_net16_sbuf)
+Automatic dissolve during optimization of view:work.trb_net16_ibuf_6_1_1_1_0_1_0(trb_net16_ibuf_arch) of THE_FIFO(trb_net16_fifoZ0)
+Automatic dissolve during optimization of view:work.trb_net16_obuf_1_1_7_0(trb_net16_obuf_arch) of THE_SBUF(trb_net16_sbuf)
+Automatic dissolve during optimization of view:work.trb_net16_api_base(trb_net16_api_base_arch) of GEN_FIFO_TO_INT\.FIFO_TO_INT(trb_net16_fifo_1_6)
+Automatic dissolve during optimization of view:work.trb_net16_api_base(trb_net16_api_base_arch) of GEN_FIFO_TO_APL\.FIFO_TO_APL(trb_net16_fifo_1_1)
+Automatic dissolve during optimization of view:work.trb_net16_api_base(trb_net16_api_base_arch) of SBUF_TO_APL(trb_net16_sbuf)
+Automatic dissolve during optimization of view:work.trb_net16_api_base(trb_net16_api_base_arch) of SBUF(trb_net16_sbuf)
+Automatic dissolve during optimization of view:work.trb_net16_regIO(trb_net16_regio_arch) of pattern_gen_inst(trb_net_pattern_gen)
+Automatic dissolve during optimization of view:work.trb_net16_io_multiplexer(trb_net16_io_multiplexer_arch) of MUX_SBUF(trb_net16_sbuf)
+Automatic dissolve during optimization of view:work.slv_adc_snoop(behavioral) of THE_CE_SYNC(state_sync)
+Automatic dissolve during optimization of view:work.slv_adc_snoop(behavioral) of THE_RST_SYNC(state_sync)
+Automatic dissolve during optimization of view:work.slv_adc_snoop(behavioral) of THE_RESET_SYNC(state_sync)
+@W: MO111 :|tristate driver ipu_error_pattern_t[22] on net ipu_error_pattern[22] has its enable tied to GND (module adcmv3)
+@W: MO129 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":476:6:476:7|Sequential instance PROC_RESET.send_reset_in has been reduced to a combinational gate by constant propagation
+Dissolving instances under view:work.trb_net16_io_multiplexer(trb_net16_io_multiplexer_arch) (flattening)
+Dissolving instances under view:work.trb_net_sbufZ0_gen_version_0\.sbuf_5_gen_version_0\.sbuf_1_MUX_SBUF_gen_version_0\.sbuf_MUX_SBUF_gen_version_0\.sbuf(trb_net_sbuf_arch) (flattening)
+Automatic dissolve at startup in view:work.trb_net16_io_multiplexer(trb_net16_io_multiplexer_arch) of ARBITER(trb_net_priority_arbiter)
+Automatic dissolve at startup in view:work.trb_net16_io_multiplexer(trb_net16_io_multiplexer_arch) of ARBITER.ENC3(trb_net_priority_encoder)
+Automatic dissolve at startup in view:work.trb_net16_io_multiplexer(trb_net16_io_multiplexer_arch) of ARBITER.ENC2(trb_net_priority_encoder)
+Automatic dissolve at startup in view:work.trb_net16_io_multiplexer(trb_net16_io_multiplexer_arch) of ARBITER.ENC1(trb_net_priority_encoder)
+
+Dissolving instances under view:work.trb_net16_term_buf(trb_net16_term_buf_arch) (flattening)
+Dissolving instances under view:work.trb_net_sbuf_3_0(trb_net_sbuf_arch) (flattening)
+Dissolving instances under view:work.trb_net16_obuf_1_1_7_0(trb_net16_obuf_arch) (flattening)
+Automatic dissolve at startup in view:work.trb_net16_obuf_1_1_7_0(trb_net16_obuf_arch) of GEN_CRC\.CRC_gen(trb_net_CRC)
+Dissolving instances under view:work.trb_net_sbufZ0_gen_version_0\.sbuf_5_gen_version_0\.sbuf_1_MUX_SBUF_gen_version_0\.sbuf_THE_SBUF_gen_version_0\.sbuf(trb_net_sbuf_arch) (flattening)
+
+Dissolving instances under view:work.trb_net_sbufZ0_gen_version_0\.sbuf_5_gen_version_0\.sbuf_1_gen_init_sbuf\.SBUF_INIT_gen_version_0\.sbuf(trb_net_sbuf_arch) (flattening)
+Dissolving instances under view:work.trb_net16_obuf_1_0_7_0(trb_net16_obuf_arch) (flattening)
+Dissolving instances under view:work.trb_net_sbufZ0_gen_version_0\.sbuf_5_gen_version_0\.sbuf_1_gen_init_sbuf\.SBUF_INIT_gen_version_0\.sbuf_gen_init_sbuf\.SBUF_INIT_gen_version_0\.sbuf(trb_net_sbuf_arch) (flattening)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of THE_ADC_APV_MAP_MEM(adc_apv_map_mem)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.1\.THE_LFIFO(fifo_1kx18)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.4\.THE_LFIFO(fifo_1kx18)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.3\.THE_LFIFO(fifo_1kx18)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.5\.THE_LFIFO(fifo_1kx18)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.2\.THE_LFIFO(fifo_1kx18)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.7\.THE_LFIFO(fifo_1kx18)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.15\.THE_LFIFO(fifo_1kx18)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.0\.THE_LFIFO(fifo_1kx18)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.6\.THE_LFIFO(fifo_1kx18)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.8\.THE_LFIFO(fifo_1kx18)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.9\.THE_LFIFO(fifo_1kx18_GEN_FIFO\.9\.THE_LFIFO_0)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.14\.THE_LFIFO(fifo_1kx18)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.11\.THE_LFIFO(fifo_1kx18)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.10\.THE_LFIFO(fifo_1kx18_GEN_FIFO\.10\.THE_LFIFO_0)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.13\.THE_LFIFO(fifo_1kx18)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.12\.THE_LFIFO(fifo_1kx18)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.5\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.2\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.11\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.8\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.0\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.3\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.15\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.1\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.7\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.6\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.4\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.14\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.9\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.13\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.12\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ipu_fifo_stage(behavioral) of GEN_FIFO\.10\.THE_DFIFO(fifo_2kx27)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of THE_DECODER_1(decoder_8bit)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of THE_DECODER_0(decoder_8bit)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.1\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.8\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.2\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.13\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.6\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.15\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.0\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.9\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.12\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.7\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.5\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.3\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.11\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.4\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.10\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.ped_corr_ctrl(behavioral) of GEN_ALU\.14\.THE_ALU(apv_pc_nc_alu)
+Automatic dissolve at startup in view:work.apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER(behavioral) of THE_APV_DIGITAL(apv_digital)
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance THE_APV_DIGITAL.bit_valid[11:0] of view:PrimLib.sdffr(prim) because there are no references to its outputs
+Automatic dissolve at startup in view:work.apv_raw_buffer(behavioral) of THE_FRAME_STATUS_MEM(frame_status_mem)
+Automatic dissolve at startup in view:work.apv_raw_buffer(behavioral) of THE_INPUT_BRAM(input_bram)
+Automatic dissolve at startup in view:work.apv_raw_buffer(behavioral) of THE_TICKMARK_SYNCER(pulse_sync_0)
+Automatic dissolve at startup in view:work.apv_raw_buffer(behavioral) of THE_ADC_LAST_SYNCER(pulse_sync_0)
+Automatic dissolve at startup in view:work.apv_raw_buffer(behavioral) of THE_ADC_START_SYNCER(pulse_sync_0)
+Automatic dissolve at startup in view:work.apv_raw_buffer_GEN_ADC1\.11\.THE_APV_RAW_BUFFER(behavioral) of THE_FRAME_STATUS_MEM(frame_status_mem)
+Automatic dissolve at startup in view:work.apv_raw_buffer_GEN_ADC1\.11\.THE_APV_RAW_BUFFER(behavioral) of THE_INPUT_BRAM(input_bram)
+Automatic dissolve at startup in view:work.apv_raw_buffer_GEN_ADC1\.11\.THE_APV_RAW_BUFFER(behavioral) of THE_TICKMARK_SYNCER(pulse_sync_0)
+Automatic dissolve at startup in view:work.apv_raw_buffer_GEN_ADC1\.11\.THE_APV_RAW_BUFFER(behavioral) of THE_ADC_LAST_SYNCER(pulse_sync_0)
+Automatic dissolve at startup in view:work.apv_raw_buffer_GEN_ADC1\.11\.THE_APV_RAW_BUFFER(behavioral) of THE_ADC_START_SYNCER(pulse_sync_0)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.11\.THE_APV_RAW_BUFFER(apv_raw_buffer_GEN_ADC1\.11\.THE_APV_RAW_BUFFER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.9\.THE_APV_RAW_BUFFER(apv_raw_buffer)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.8\.THE_APV_RAW_BUFFER(apv_raw_buffer)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.15\.THE_APV_RAW_BUFFER(apv_raw_buffer)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.14\.THE_APV_RAW_BUFFER(apv_raw_buffer)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.12\.THE_APV_RAW_BUFFER(apv_raw_buffer)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.13\.THE_APV_RAW_BUFFER(apv_raw_buffer)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.10\.THE_APV_RAW_BUFFER(apv_raw_buffer)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.10\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.12\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.15\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.11\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.14\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.8\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.9\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC1\.13\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.0\.THE_APV_RAW_BUFFER(apv_raw_buffer)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.6\.THE_APV_RAW_BUFFER(apv_raw_buffer)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.7\.THE_APV_RAW_BUFFER(apv_raw_buffer)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.2\.THE_APV_RAW_BUFFER(apv_raw_buffer)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.5\.THE_APV_RAW_BUFFER(apv_raw_buffer)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.1\.THE_APV_RAW_BUFFER(apv_raw_buffer)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.3\.THE_APV_RAW_BUFFER(apv_raw_buffer)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.4\.THE_APV_RAW_BUFFER(apv_raw_buffer)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.4\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.0\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.1\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.3\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.5\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.7\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.2\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+Automatic dissolve at startup in view:work.raw_buf_stage(behavioral) of GEN_ADC0\.6\.THE_APV_LOCKER(apv_locker_GEN_ADC0\.6\.THE_APV_LOCKER)
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.11\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.11\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.9\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.9\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.8\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.8\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.15\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.15\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.14\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.14\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.12\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.12\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.13\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.13\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.10\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC1\.10\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.0\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.0\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.6\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.6\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.7\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.7\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.2\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.2\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.5\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.5\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.1\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.1\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.3\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.3\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.4\.THE_APV_RAW_BUFFER.adc_status_qq[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":173:1:173:2|Removing sequential instance GEN_ADC0\.4\.THE_APV_RAW_BUFFER.adc_status_q[7:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC1_HANDLER(behavioral) of THE_ADC_6_7_CH(adc_twochannels_0)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC1_HANDLER(behavioral) of THE_DIN_7(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC1_HANDLER(behavioral) of THE_DIN_6(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC1_HANDLER(behavioral) of THE_ADC_4_5_CH(adc_twochannels_0)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC1_HANDLER(behavioral) of THE_DIN_5(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC1_HANDLER(behavioral) of THE_DIN_4(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC1_HANDLER(behavioral) of THE_ADC_2_3_CH(adc_twochannels_0)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC1_HANDLER(behavioral) of THE_DIN_3(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC1_HANDLER(behavioral) of THE_DIN_2(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC1_HANDLER(behavioral) of THE_ADC_0_1_CH(adc_twochannels_0)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC1_HANDLER(behavioral) of THE_DIN_1(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC1_HANDLER(behavioral) of THE_DIN_0(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC1_HANDLER(behavioral) of THE_ADC_ADCLK_IN(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_crossover_THE_ADC1_CROSSOVER(behavioral) of THE_CROSSOVER(crossover_THE_CROSSOVER)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC0_HANDLER(behavioral) of THE_ADC_6_7_CH(adc_twochannels)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC0_HANDLER(behavioral) of THE_DIN_7(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC0_HANDLER(behavioral) of THE_DIN_6(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC0_HANDLER(behavioral) of THE_ADC_4_5_CH(adc_twochannels)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC0_HANDLER(behavioral) of THE_DIN_5(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC0_HANDLER(behavioral) of THE_DIN_4(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC0_HANDLER(behavioral) of THE_ADC_2_3_CH(adc_twochannels)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC0_HANDLER(behavioral) of THE_DIN_3(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC0_HANDLER(behavioral) of THE_DIN_2(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC0_HANDLER(behavioral) of THE_ADC_0_1_CH(adc_twochannels)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC0_HANDLER(behavioral) of THE_DIN_1(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC0_HANDLER(behavioral) of THE_DIN_0(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_data_handler_THE_ADC0_HANDLER(behavioral) of THE_ADC_ADCLK_IN(adc_ch_in)
+Automatic dissolve at startup in view:work.adc_crossover_THE_ADC0_CROSSOVER(behavioral) of THE_CROSSOVER(crossover_THE_CROSSOVER_0)
+Automatic dissolve at startup in view:work.eds_buf(behavioral) of THE_EDS_BUFFER(eds_buffer_dpram)
+Automatic dissolve at startup in view:work.apv_trg_handler(behavioral) of THE_APVTRGDONE_SYNC(pulse_sync_0)
+Automatic dissolve at startup in view:work.apv_trg_handler(behavioral) of THE_APVTRGSENT_SYNC(pulse_sync_0)
+Automatic dissolve at startup in view:work.apv_trg_handler(behavioral) of THE_APVTRGSTART_SYNC(pulse_sync)
+Automatic dissolve at startup in view:work.apv_sync_handler(behavioral) of THE_APVTRGDONE_SYNC(pulse_sync_0)
+Automatic dissolve at startup in view:work.apv_sync_handler(behavioral) of THE_APVTRGSTART_SYNC(pulse_sync)
+Automatic dissolve at startup in view:work.apv_trgctrl(behavioral) of THE_EDS_BUF(eds_buf)
+Automatic dissolve at startup in view:work.apv_trgctrl(behavioral) of THE_MAX_TRG(max_data)
+Automatic dissolve at startup in view:work.apv_trgctrl(behavioral) of SC_TRG3_STRECH(pulse_stretch)
+Automatic dissolve at startup in view:work.apv_trgctrl(behavioral) of SC_TRG2_STRECH(pulse_stretch)
+Automatic dissolve at startup in view:work.apv_trgctrl(behavioral) of SC_TRG1_STRECH(pulse_stretch)
+Automatic dissolve at startup in view:work.apv_trgctrl(behavioral) of SC_TRG0_STRECH(pulse_stretch)
+Automatic dissolve at startup in view:work.trb_net16_med_ecp_sfp_gbe(med_ecp_sfp) of THE_FIFO_FPGA_TO_SFP.FIFO_DP_BRAM(lattice_ecp2m_fifo_16bit_dualport)
+Automatic dissolve at startup in view:work.trb_net16_med_ecp_sfp_gbe(med_ecp_sfp) of THE_FIFO_SFP_TO_FPGA.FIFO_DP_BRAM(lattice_ecp2m_fifo_16bit_dualport)
+Automatic dissolve at startup in view:work.trb_net16_med_ecp_sfp_gbe(med_ecp_sfp) of gen_serdes_2\.THE_SERDES(serdes_gbe_2)
+Automatic dissolve at startup in view:work.trb_net16_med_ecp_sfp_gbe(med_ecp_sfp) of THE_RX_ALLOW_SYNC(signal_sync_2_2)
+Automatic dissolve at startup in view:work.trb_net16_med_ecp_sfp_gbe(med_ecp_sfp) of THE_RX_K_DELAY(signal_sync_2_2)
+Automatic dissolve at startup in view:work.trb_net16_med_ecp_sfp_gbe(med_ecp_sfp) of THE_RX_DATA_DELAY(signal_sync_16_2)
+Automatic dissolve at startup in view:work.trb_net16_med_ecp_sfp_gbe(med_ecp_sfp) of THE_RX_K_SYNC(signal_sync_2_1)
+Automatic dissolve at startup in view:work.trb_net16_med_ecp_sfp_gbe(med_ecp_sfp) of THE_SFP_STATUS_SYNC(signal_sync_2_3)
+Automatic dissolve at startup in view:work.trb_net16_ibuf_6_1_1_0_0_1_0(trb_net16_ibuf_arch) of THE_FIFO.fifo(lattice_ecp2m_fifo_18x1k)
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":701:4:701:7|Removing sequential instance THE_FIFO.fifo.FF_0 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":889:4:889:11|Removing instance THE_FIFO.fifo.af_cmp_5 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":885:4:885:11|Removing instance THE_FIFO.fifo.af_cmp_4 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":878:4:878:11|Removing instance THE_FIFO.fifo.af_cmp_3 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":874:4:874:11|Removing instance THE_FIFO.fifo.af_cmp_2 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":870:4:870:11|Removing instance THE_FIFO.fifo.af_cmp_1 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":866:4:866:11|Removing instance THE_FIFO.fifo.af_cmp_0 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+Automatic dissolve at startup in view:work.trb_net16_iobufZ1(trb_net16_iobuf_arch) of GEN_IBUF\.THE_IBUF(trb_net16_ibuf_6_1_1_0_0_1_0)
+Automatic dissolve at startup in view:work.trb_net16_ibuf_6_1_1_1_0_1_0(trb_net16_ibuf_arch) of THE_FIFO.fifo(lattice_ecp2m_fifo_18x1k)
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":701:4:701:7|Removing sequential instance THE_FIFO.fifo.FF_0 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":889:4:889:11|Removing instance THE_FIFO.fifo.af_cmp_5 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":885:4:885:11|Removing instance THE_FIFO.fifo.af_cmp_4 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":878:4:878:11|Removing instance THE_FIFO.fifo.af_cmp_3 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":874:4:874:11|Removing instance THE_FIFO.fifo.af_cmp_2 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":870:4:870:11|Removing instance THE_FIFO.fifo.af_cmp_1 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":866:4:866:11|Removing instance THE_FIFO.fifo.af_cmp_0 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+Automatic dissolve at startup in view:work.trb_net16_iobufZ0_genbuffers\.1\.geniobuf\.IOBUF(trb_net16_iobuf_arch) of GEN_IBUF\.THE_IBUF(trb_net16_ibuf_6_1_1_1_0_1_0)
+Automatic dissolve at startup in view:work.trb_net16_api_base_genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API_genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API(trb_net16_api_base_arch) of GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo(lattice_ecp2m_fifo_18x1k_GEN_FIFO_TO_INT\.FIFO_TO_INT_fifo)
+Automatic dissolve at startup in view:work.trb_net16_api_base_genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API_genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API(trb_net16_api_base_arch) of GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo(lattice_ecp2m_fifo_18x1k)
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":701:4:701:7|Removing sequential instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.FF_0 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":889:4:889:11|Removing instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.af_cmp_5 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":885:4:885:11|Removing instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.af_cmp_4 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":878:4:878:11|Removing instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.af_cmp_3 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":874:4:874:11|Removing instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.af_cmp_2 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":870:4:870:11|Removing instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.af_cmp_1 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":866:4:866:11|Removing instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.af_cmp_0 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":701:4:701:7|Removing sequential instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.FF_0 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":889:4:889:11|Removing instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.af_cmp_5 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":885:4:885:11|Removing instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.af_cmp_4 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":878:4:878:11|Removing instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.af_cmp_3 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":874:4:874:11|Removing instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.af_cmp_2 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":870:4:870:11|Removing instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.af_cmp_1 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":866:4:866:11|Removing instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.af_cmp_0 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+Automatic dissolve at startup in view:work.trb_net16_api_base_genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API(trb_net16_api_base_arch) of GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo(lattice_ecp2m_fifo_18x1k)
+Automatic dissolve at startup in view:work.trb_net16_api_base_genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API(trb_net16_api_base_arch) of GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo(lattice_ecp2m_fifo_18x1k)
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":701:4:701:7|Removing sequential instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.FF_0 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":889:4:889:11|Removing instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.af_cmp_5 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":885:4:885:11|Removing instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.af_cmp_4 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":878:4:878:11|Removing instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.af_cmp_3 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":874:4:874:11|Removing instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.af_cmp_2 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":870:4:870:11|Removing instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.af_cmp_1 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":866:4:866:11|Removing instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.af_cmp_0 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":701:4:701:7|Removing sequential instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.FF_0 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":889:4:889:11|Removing instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.af_cmp_5 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":885:4:885:11|Removing instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.af_cmp_4 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":878:4:878:11|Removing instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.af_cmp_3 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":874:4:874:11|Removing instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.af_cmp_2 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":870:4:870:11|Removing instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.af_cmp_1 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+@N: BN114 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":866:4:866:11|Removing instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.af_cmp_0 of black_box view:work.AGEB2(syn_black_box) because there are no references to its outputs
+Automatic dissolve at startup in view:work.trb_net16_addresses(trb_net16_addresses_arch) of THE_STAT_RAM(ram_16x16_dp)
+Automatic dissolve at startup in view:work.rich_trb(rich_arch) of THE_MEDIA_INTERFACE(trb_net16_med_ecp_sfp_gbe)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.13\.THE_PED_MEM(ped_thr_true)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.9\.THE_PED_MEM(ped_thr_true_GEN_PED_MEM\.9\.THE_PED_MEM_0)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.15\.THE_PED_MEM(ped_thr_true_GEN_PED_MEM\.15\.THE_PED_MEM_0)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.14\.THE_PED_MEM(ped_thr_true_GEN_PED_MEM\.14\.THE_PED_MEM_0)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.4\.THE_PED_MEM(ped_thr_true_GEN_PED_MEM\.4\.THE_PED_MEM_0)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.8\.THE_PED_MEM(ped_thr_true_GEN_PED_MEM\.8\.THE_PED_MEM_0)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.12\.THE_PED_MEM(ped_thr_true_GEN_PED_MEM\.12\.THE_PED_MEM_0)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.7\.THE_PED_MEM(ped_thr_true_GEN_PED_MEM\.7\.THE_PED_MEM_0)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.11\.THE_PED_MEM(ped_thr_true_GEN_PED_MEM\.11\.THE_PED_MEM_0)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.5\.THE_PED_MEM(ped_thr_true_GEN_PED_MEM\.5\.THE_PED_MEM_0)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.6\.THE_PED_MEM(ped_thr_true_GEN_PED_MEM\.6\.THE_PED_MEM_0)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.10\.THE_PED_MEM(ped_thr_true_GEN_PED_MEM\.10\.THE_PED_MEM_0)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.1\.THE_PED_MEM(ped_thr_true_GEN_PED_MEM\.1\.THE_PED_MEM_0)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.0\.THE_PED_MEM(ped_thr_true_GEN_PED_MEM\.0\.THE_PED_MEM_0)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.2\.THE_PED_MEM(ped_thr_true_GEN_PED_MEM\.2\.THE_PED_MEM_0)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of GEN_PED_MEM\.3\.THE_PED_MEM(ped_thr_true_GEN_PED_MEM\.3\.THE_PED_MEM)
+Automatic dissolve at startup in view:work.slv_ped_thr_mem(behavioral) of THE_APV_ADC_MAP_MEM(apv_adc_map_mem)
+Automatic dissolve at startup in view:work.spi_databus_memory(behavioral) of THE_BUS_SPI_DPRAM(spi_dpram_32_to_8)
+Automatic dissolve at startup in view:work.slv_register_bank(behavioral) of THE_APV_ADC_MAP_MEM(apv_adc_map_mem)
+Automatic dissolve at startup in view:work.slv_adc_snoop(behavioral) of THE_ADC0_SNOOP_MEM(adc_snoop_mem)
+Automatic dissolve at startup in view:work.slv_onewire_memory(behavioral) of THE_SLV_ONEWIRE_DPRAM(slv_onewire_dpram)
+Automatic dissolve at startup in view:work.slv_onewire_memory(behavioral) of THE_ONEWIRE_SPARE_ONE(onewire_spare_one)
+Automatic dissolve at startup in view:work.slv_onewire_memory(behavioral) of THE_ADC_ONEWIRE_MAP_MEM(adc_onewire_map_mem)
+Automatic dissolve at startup in view:work.slave_bus(behavioral) of THE_BUS_HANDLER(trb_net16_regio_bus_handler)
+Automatic dissolve at startup in view:work.adcmv3(adcmv3) of THE_RICH_TRB(rich_trb)
+Automatic dissolve at startup in view:work.adcmv3(adcmv3) of THE_ADC_0_SELECT(adc_channel_select)
+Automatic dissolve at startup in view:work.adcmv3(adcmv3) of THE_ADC0_CROSSOVER(adc_crossover_THE_ADC0_CROSSOVER)
+Automatic dissolve at startup in view:work.adcmv3(adcmv3) of THE_ADC_1_SELECT(adc_channel_select)
+Automatic dissolve at startup in view:work.adcmv3(adcmv3) of THE_ADC1_CROSSOVER(adc_crossover_THE_ADC1_CROSSOVER)
+Automatic dissolve at startup in view:work.adcmv3(adcmv3) of THE_IPU_STAGE(ipu_fifo_stage)
+Automatic dissolve at startup in view:work.adcmv3(adcmv3) of THE_APV_PULSE_STRETCH(pulse_stretch)
+Automatic dissolve at startup in view:work.adcmv3(adcmv3) of THE_SYNC_PLL(sync_pll_40m)
+Automatic dissolve at startup in view:work.adcmv3(adcmv3) of THE_100M_DLL(dll_100m)
+Automatic dissolve at startup in view:work.adcmv3(adcmv3) of THE_40M_PLL(pll_40m)
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_crossover.vhd":92:1:92:2|Removing sequential instance THE_ADC0_CROSSOVER.apv_data_valid[2:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":1662:4:1662:8|Removing sequential instance THE_ADC0_CROSSOVER.THE_CROSSOVER.FF_11 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":1668:4:1668:8|Removing sequential instance THE_ADC0_CROSSOVER.THE_CROSSOVER.FF_10 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":1674:4:1674:7|Removing sequential instance THE_ADC0_CROSSOVER.THE_CROSSOVER.FF_9 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":1680:4:1680:7|Removing sequential instance THE_ADC0_CROSSOVER.THE_CROSSOVER.FF_8 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":1686:4:1686:7|Removing sequential instance THE_ADC0_CROSSOVER.THE_CROSSOVER.FF_7 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_crossover.vhd":92:1:92:2|Removing sequential instance THE_ADC1_CROSSOVER.apv_data_valid[2:0] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":1662:4:1662:8|Removing sequential instance THE_ADC1_CROSSOVER.THE_CROSSOVER.FF_11 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":1668:4:1668:8|Removing sequential instance THE_ADC1_CROSSOVER.THE_CROSSOVER.FF_10 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":1674:4:1674:7|Removing sequential instance THE_ADC1_CROSSOVER.THE_CROSSOVER.FF_9 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":1680:4:1680:7|Removing sequential instance THE_ADC1_CROSSOVER.THE_CROSSOVER.FF_8 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/crossover.vhd":1686:4:1686:7|Removing sequential instance THE_ADC1_CROSSOVER.THE_CROSSOVER.FF_7 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/state_sync.vhd":27:1:27:2|Removing sequential instance THE_ADC_0_SELECT.THE_RESET_SYNC.sync[1:0], because it is equivalent to instance THE_ADC_1_SELECT.THE_RESET_SYNC.sync[1:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.10.THE_ALU.lcb_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.lcb_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.4.THE_ALU.lcb_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.lcb_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.11.THE_ALU.lcb_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.lcb_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.3.THE_ALU.lcb_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.lcb_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.5.THE_ALU.lcb_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.lcb_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.7.THE_ALU.lcb_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.lcb_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.12.THE_ALU.lcb_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.lcb_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.9.THE_ALU.lcb_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.lcb_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.0.THE_ALU.lcb_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.lcb_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.15.THE_ALU.lcb_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.lcb_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.6.THE_ALU.lcb_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.lcb_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.13.THE_ALU.lcb_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.lcb_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.2.THE_ALU.lcb_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.lcb_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.8.THE_ALU.lcb_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.lcb_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.1.THE_ALU.lcb_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.lcb_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.10.THE_ALU.ped_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.ped_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.4.THE_ALU.ped_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.ped_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.11.THE_ALU.ped_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.ped_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.3.THE_ALU.ped_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.ped_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.5.THE_ALU.ped_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.ped_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.7.THE_ALU.ped_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.ped_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.12.THE_ALU.ped_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.ped_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.9.THE_ALU.ped_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.ped_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.0.THE_ALU.ped_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.ped_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.15.THE_ALU.ped_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.ped_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.6.THE_ALU.ped_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.ped_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.13.THE_ALU.ped_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.ped_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.2.THE_ALU.ped_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.ped_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.8.THE_ALU.ped_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.ped_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.1.THE_ALU.ped_off, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.ped_off
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.1.THE_ALU.frame_int[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.8.THE_ALU.frame_int[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.8.THE_ALU.frame_int[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.13.THE_ALU.frame_int[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.2.THE_ALU.frame_int[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.6.THE_ALU.frame_int[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.13.THE_ALU.frame_int[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.15.THE_ALU.frame_int[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.6.THE_ALU.frame_int[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.0.THE_ALU.frame_int[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.15.THE_ALU.frame_int[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.9.THE_ALU.frame_int[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.0.THE_ALU.frame_int[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.12.THE_ALU.frame_int[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.9.THE_ALU.frame_int[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.7.THE_ALU.frame_int[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.12.THE_ALU.frame_int[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.5.THE_ALU.frame_int[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.7.THE_ALU.frame_int[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.3.THE_ALU.frame_int[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.5.THE_ALU.frame_int[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.11.THE_ALU.frame_int[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.3.THE_ALU.frame_int[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.4.THE_ALU.frame_int[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.11.THE_ALU.frame_int[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.10.THE_ALU.frame_int[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.4.THE_ALU.frame_int[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.frame_int[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.10.THE_ALU.frame_int[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.frame_int[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.1.THE_ALU.toggle[5:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.8.THE_ALU.toggle[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.8.THE_ALU.toggle[5:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.13.THE_ALU.toggle[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.2.THE_ALU.toggle[5:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.6.THE_ALU.toggle[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.13.THE_ALU.toggle[5:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.15.THE_ALU.toggle[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.6.THE_ALU.toggle[5:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.0.THE_ALU.toggle[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.15.THE_ALU.toggle[5:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.9.THE_ALU.toggle[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.0.THE_ALU.toggle[5:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.12.THE_ALU.toggle[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.9.THE_ALU.toggle[5:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.7.THE_ALU.toggle[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.12.THE_ALU.toggle[5:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.5.THE_ALU.toggle[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.7.THE_ALU.toggle[5:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.3.THE_ALU.toggle[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.5.THE_ALU.toggle[5:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.11.THE_ALU.toggle[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.3.THE_ALU.toggle[5:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.4.THE_ALU.toggle[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.11.THE_ALU.toggle[5:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.10.THE_ALU.toggle[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.4.THE_ALU.toggle[5:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.toggle[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":303:1:303:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.1.THE_ALU.channel[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.8.THE_ALU.channel[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":303:1:303:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.8.THE_ALU.channel[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.13.THE_ALU.channel[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":303:1:303:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.2.THE_ALU.channel[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.6.THE_ALU.channel[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":303:1:303:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.13.THE_ALU.channel[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.15.THE_ALU.channel[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":303:1:303:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.6.THE_ALU.channel[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.0.THE_ALU.channel[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":303:1:303:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.15.THE_ALU.channel[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.9.THE_ALU.channel[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":303:1:303:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.0.THE_ALU.channel[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.12.THE_ALU.channel[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":303:1:303:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.9.THE_ALU.channel[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.7.THE_ALU.channel[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":303:1:303:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.12.THE_ALU.channel[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.5.THE_ALU.channel[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":303:1:303:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.7.THE_ALU.channel[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.3.THE_ALU.channel[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":303:1:303:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.5.THE_ALU.channel[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.11.THE_ALU.channel[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":303:1:303:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.3.THE_ALU.channel[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.4.THE_ALU.channel[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":303:1:303:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.11.THE_ALU.channel[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.10.THE_ALU.channel[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":303:1:303:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.4.THE_ALU.channel[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.channel[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":303:1:303:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.10.THE_ALU.channel[6:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.channel[6:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Removing sequential instance THE_PED_CORR_STAGE.GEN_ALU.10.THE_ALU.toggle[5:0], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.toggle[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":58:1:58:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.qc_0[5:0], because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.qc_0[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":58:1:58:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.qc_0[5:0], because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.qc_0[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":58:1:58:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.qc_1[5:0], because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.qc_1[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":58:1:58:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.qc_1[5:0], because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.qc_1[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":36:7:36:8|Removing user instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.un1_qc_1[6], because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.un1_qc_1[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":36:7:36:8|Removing user instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.un1_qc_1[6], because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.un1_qc_1[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":36:7:36:8|Removing user instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.un1_qc_0[6], because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.un1_qc_0[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":36:7:36:8|Removing user instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.un1_qc_0[6], because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.un1_qc_0[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":108:26:108:53|Removing user instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.un4_next_store_a, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.un4_next_store_a
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":108:26:108:53|Removing user instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.un4_next_store_a, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.un4_next_store_a
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":109:26:109:53|Removing user instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.un1_next_store_b, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.un1_next_store_b
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":109:26:109:53|Removing user instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.un1_next_store_b, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.un1_next_store_b
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":58:1:58:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_2_3_CH.qc_0[5:0], because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.qc_0[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.store_b, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.store_b
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.store_b, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.store_b
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.check, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.check
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.check, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.check
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":58:1:58:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_2_3_CH.qc_1[5:0], because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.qc_1[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":44:7:44:13|Removing user instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.un1_store_b, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.un1_store_b
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":44:7:44:13|Removing user instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.un1_store_b, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.un1_store_b
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.store_a, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.store_a
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.store_a, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.store_a
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.swap, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.swap
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.swap, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.swap
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_4_5_CH.store, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.store
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.store, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.store
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.store_a, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_2_3_CH.store_a
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.store_b, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_2_3_CH.store_b
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_2_3_CH.store, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.store
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_2_3_CH.check, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_0_1_CH.check
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC1_HANDLER.THE_ADC_2_3_CH.swap, because it is equivalent to instance THE_ADC1_HANDLER.THE_ADC_6_7_CH.swap
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":58:1:58:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.qc_0[5:0], because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.qc_0[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":58:1:58:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.qc_0[5:0], because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.qc_0[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":58:1:58:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.qc_1[5:0], because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.qc_1[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":58:1:58:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.qc_1[5:0], because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.qc_1[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":36:7:36:8|Removing user instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.un1_qc_1[6], because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.un1_qc_1[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":36:7:36:8|Removing user instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.un1_qc_1[6], because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.un1_qc_1[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":36:7:36:8|Removing user instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.un1_qc_0[6], because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.un1_qc_0[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":36:7:36:8|Removing user instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.un1_qc_0[6], because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.un1_qc_0[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":108:26:108:53|Removing user instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.un4_next_store_a, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.un4_next_store_a
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":108:26:108:53|Removing user instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.un4_next_store_a, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.un4_next_store_a
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":109:26:109:53|Removing user instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.un1_next_store_b, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.un1_next_store_b
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":109:26:109:53|Removing user instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.un1_next_store_b, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.un1_next_store_b
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":58:1:58:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_2_3_CH.qc_0[5:0], because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.qc_0[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.store_b, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.store_b
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.store_b, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.store_b
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.check, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.check
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.check, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.check
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":58:1:58:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_2_3_CH.qc_1[5:0], because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.qc_1[5:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":44:7:44:13|Removing user instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.un1_store_b, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.un1_store_b
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":44:7:44:13|Removing user instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.un1_store_b, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.un1_store_b
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.store_a, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.store_a
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.store_a, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.store_a
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.swap, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.swap
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.swap, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.swap
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_4_5_CH.store, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.store
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.store, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.store
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.store_a, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_2_3_CH.store_a
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.store_b, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_2_3_CH.store_b
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_2_3_CH.store, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.store
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_2_3_CH.check, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_0_1_CH.check
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_twochannels.vhd":98:1:98:2|Removing sequential instance THE_ADC0_HANDLER.THE_ADC_2_3_CH.swap, because it is equivalent to instance THE_ADC0_HANDLER.THE_ADC_6_7_CH.swap
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regio_bus_handler.vhd":148:6:148:7|Removing sequential instance THE_SLAVE_BUS.THE_BUS_HANDLER.DAT_WRITE_ACK_OUT, because it is equivalent to instance THE_SLAVE_BUS.THE_BUS_HANDLER.DAT_DATAREADY_OUT
+
+Available hyper_sources - for debug and ip models
+ None Found
+
+@N: FX493 |Applying Initial value "00" on instance: THE_RESET_HANDLER.reset_pulse[1:0]
+@N: FX493 |Applying Initial value "11" on instance: THE_RESET_HANDLER.final_reset[1:0]
+@N: FX493 |Applying Initial value "00" on instance: THE_RESET_HANDLER.trb_reset_pulse[1:0]
+@N: FX493 |Applying Initial value "0000000000000000" on instance: THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.IOBUF.GEN_IBUF.THE_IBUF.gen_crc.THE_CRC.CRC[15:0]
+@N: FX493 |Applying Initial value "0000000000000000" on instance: THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.IOBUF.genREPLYOBUF1.REPLYOBUF.GEN_CRC.CRC_gen.CRC[15:0]
+@N: FX493 |Applying Initial value "0000000000000000" on instance: THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.IOBUF.GEN_IBUF.THE_IBUF.gen_crc.THE_CRC.CRC[15:0]
+@N: FX493 |Applying Initial value "0000000000000000" on instance: THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.IOBUF.genREPLYOBUF1.REPLYOBUF.GEN_CRC.CRC_gen.CRC[15:0]
+@N: FX493 |Applying Initial value "1111101100000000" on instance: THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_regio.regIO.the_addresses.buf_ADDRESS_OUT[15:0]
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_dpram.vhd":140:4:140:26|Expect property csdecode_a of instance THE_SLV_ONEWIRE_DPRAM.slv_onewire_dpram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_dpram.vhd":140:4:140:26|Expect property csdecode_b of instance THE_SLV_ONEWIRE_DPRAM.slv_onewire_dpram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_a of instance THE_ADC0_SNOOP_MEM.adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_b of instance THE_ADC0_SNOOP_MEM.adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_a of instance THE_ADC0_SNOOP_MEM.adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_b of instance THE_ADC0_SNOOP_MEM.adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":150:4:150:26|Expect property csdecode_a of instance THE_BUS_SPI_DPRAM.spi_dpram_32_to_8_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":150:4:150:26|Expect property csdecode_b of instance THE_BUS_SPI_DPRAM.spi_dpram_32_to_8_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":198:4:198:26|Expect property csdecode_a of instance THE_BUS_SPI_DPRAM.spi_dpram_32_to_8_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":198:4:198:26|Expect property csdecode_b of instance THE_BUS_SPI_DPRAM.spi_dpram_32_to_8_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.13\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.13\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.9\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.9\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.15\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.15\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.14\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.14\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.4\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.4\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.8\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.8\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.12\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.12\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.7\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.7\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.11\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.11\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.5\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.5\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.6\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.6\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.10\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.10\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.1\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.1\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.0\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.0\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.2\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.2\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.3\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.3\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.13\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.13\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.9\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.9\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.15\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.15\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.14\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.14\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.4\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.4\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.8\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.8\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.12\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.12\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.7\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.7\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.11\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.11\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.5\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.5\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.6\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.6\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.10\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.10\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.1\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.1\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.0\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.0\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.2\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.2\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.3\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.3\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_a of instance THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_FPGA_TO_SFP.FIFO_DP_BRAM.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_b of instance THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_FPGA_TO_SFP.FIFO_DP_BRAM.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_a of instance THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_SFP_TO_FPGA.FIFO_DP_BRAM.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_b of instance THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_SFP_TO_FPGA.FIFO_DP_BRAM.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@N: FA239 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_onewire.vhd":94:6:94:9|Rom inc_bitcounter mapped in logic.
+@N: FA239 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_onewire.vhd":94:6:94:9|Rom inc_bitcounter mapped in logic.
+@N: MO106 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_onewire.vhd":94:6:94:9|Found ROM, 'inc_bitcounter', 14 words by 1 bits
+@N: FA239 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_ped_thr_mem.vhd":87:2:87:5|Rom THE_MEM_SEL_PROC\.mem_sel_17[15:0] mapped in logic.
+@N: FA239 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_ped_thr_mem.vhd":87:2:87:5|Rom THE_MEM_SEL_PROC\.mem_sel_17[15:0] mapped in logic.
+@N: MO106 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_ped_thr_mem.vhd":87:2:87:5|Found ROM, 'THE_MEM_SEL_PROC\.mem_sel_17[15:0]', 16 words by 16 bits
+@N: FA239 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_ped_thr_mem.vhd":87:2:87:5|Rom THE_MEM_SEL_PROC\.mem_sel_17[15:0] mapped in logic.
+@N: FA239 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_ped_thr_mem.vhd":87:2:87:5|Rom THE_MEM_SEL_PROC\.mem_sel_17[15:0] mapped in logic.
+@N: MO106 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_ped_thr_mem.vhd":87:2:87:5|Found ROM, 'THE_MEM_SEL_PROC\.mem_sel_17[15:0]', 16 words by 16 bits
+@N: FA239 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":103:2:103:5|Rom THE_REG_SEL_PROC\.reg_sel_17[15:0] mapped in logic.
+@N: FA239 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":103:2:103:5|Rom THE_REG_SEL_PROC\.reg_sel_17[15:0] mapped in logic.
+@N: MO106 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":103:2:103:5|Found ROM, 'THE_REG_SEL_PROC\.reg_sel_17[15:0]', 16 words by 16 bits
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_dpram.vhd":140:4:140:26|Expect property csdecode_a of instance THE_SLV_ONEWIRE_DPRAM.slv_onewire_dpram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_dpram.vhd":140:4:140:26|Expect property csdecode_b of instance THE_SLV_ONEWIRE_DPRAM.slv_onewire_dpram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_a of instance THE_ADC0_SNOOP_MEM.adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_b of instance THE_ADC0_SNOOP_MEM.adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_a of instance THE_ADC0_SNOOP_MEM.adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_b of instance THE_ADC0_SNOOP_MEM.adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":150:4:150:26|Expect property csdecode_a of instance THE_BUS_SPI_DPRAM.spi_dpram_32_to_8_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":150:4:150:26|Expect property csdecode_b of instance THE_BUS_SPI_DPRAM.spi_dpram_32_to_8_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":198:4:198:26|Expect property csdecode_a of instance THE_BUS_SPI_DPRAM.spi_dpram_32_to_8_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":198:4:198:26|Expect property csdecode_b of instance THE_BUS_SPI_DPRAM.spi_dpram_32_to_8_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.13\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.13\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.9\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.9\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.15\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.15\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.14\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.14\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.4\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.4\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.8\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.8\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.12\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.12\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.7\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.7\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.11\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.11\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.5\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.5\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.6\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.6\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.10\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.10\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.1\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.1\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.0\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.0\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.2\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.2\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.3\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.3\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.13\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.13\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.9\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.9\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.15\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.15\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.14\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.14\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.4\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.4\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.8\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.8\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.12\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.12\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.7\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.7\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.11\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.11\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.5\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.5\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.6\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.6\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.10\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.10\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.1\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.1\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.0\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.0\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.2\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.2\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance GEN_PED_MEM\.3\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance GEN_PED_MEM\.3\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_a of instance THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_FPGA_TO_SFP.FIFO_DP_BRAM.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_b of instance THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_FPGA_TO_SFP.FIFO_DP_BRAM.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_a of instance THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_SFP_TO_FPGA.FIFO_DP_BRAM.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_b of instance THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_SFP_TO_FPGA.FIFO_DP_BRAM.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+Finished RTL optimizations (Time elapsed 0h:00m:07s; Memory used current: 130MB peak: 139MB)
+
+Encoding state machine work.adcmv3(adcmv3)-THE_IPU_STAGE.CURRENT_STATE[0:9]
+original code -> new code
+ 0000 -> 0000000001
+ 0001 -> 0000000010
+ 0010 -> 0000000100
+ 0011 -> 0000001000
+ 0100 -> 0000010000
+ 0101 -> 0000100000
+ 0110 -> 0001000000
+ 0111 -> 0010000000
+ 1000 -> 0100000000
+ 1001 -> 1000000000
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[31] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[30] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[29] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[28] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[27] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[26] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[25] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[24] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[23] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[22] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[21] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[20] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[19] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[18] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[17] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":469:1:469:2|Removing sequential instance THE_IPU_STAGE.my_trg_number[16] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N:"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":1009:4:1009:5|Found counter in view:work.adcmv3(adcmv3) inst THE_RICH_TRB.THE_MEDIA_INTERFACE.rx_counter[2:0]
+@N:"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":968:4:968:5|Found counter in view:work.adcmv3(adcmv3) inst THE_RICH_TRB.THE_MEDIA_INTERFACE.reset_word_cnt[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.8\.THE_TODO_CTR_PROC\.fifo_todo_8_3[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo_15[0:9]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.1\.THE_TODO_CTR_PROC\.fifo_todo_1_3[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo_14[0:9]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.6\.THE_TODO_CTR_PROC\.fifo_todo_6_3[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo_13[0:9]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.4\.THE_TODO_CTR_PROC\.fifo_todo_4_3[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo_12[0:9]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.12\.THE_TODO_CTR_PROC\.fifo_todo_12_3[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo_11[0:9]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.5\.THE_TODO_CTR_PROC\.fifo_todo_5_3[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo_10[0:9]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.10\.THE_TODO_CTR_PROC\.fifo_todo_10_3[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo_9[0:9]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.0\.THE_TODO_CTR_PROC\.fifo_todo_0_4[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo_8[0:9]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.11\.THE_TODO_CTR_PROC\.fifo_todo_11_3[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo_7[0:9]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.9\.THE_TODO_CTR_PROC\.fifo_todo_9_3[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo_6[0:9]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.14\.THE_TODO_CTR_PROC\.fifo_todo_14_3[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo_5[0:9]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.2\.THE_TODO_CTR_PROC\.fifo_todo_2_3[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo_4[0:9]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.7\.THE_TODO_CTR_PROC\.fifo_todo_7_3[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo_3[0:9]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.13\.THE_TODO_CTR_PROC\.fifo_todo_13_3[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo_2[0:9]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.15\.THE_TODO_CTR_PROC\.fifo_todo_15_3[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo_1[0:9]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":427:3:427:4|Found addmux in view:work.adcmv3(adcmv3) inst THE_IPU_STAGE.GEN_FIFO\.3\.THE_TODO_CTR_PROC\.fifo_todo_3_3[9:0] from THE_IPU_STAGE.un1_comb_rd_dfifo[0:9]
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":465:32:465:78|Found 16 bit by 16 bit '==' comparator, 'THE_IPU_STAGE.un1_next_trgnum_match'
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/reset_handler.vhd":106:1:106:2|Found counter in view:work.reset_handler(behavioral) inst reset_cnt[15:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/reboot_handler.vhd":43:1:43:2|Found counter in view:work.reboot_handler(behavioral) inst reboot_counter[15:0]
+Encoding state machine work.ped_corr_ctrl(behavioral)-CURRENT_STATE[0:29]
+original code -> new code
+ 00000 -> 000000000000000000000000000001
+ 00001 -> 000000000000000000000000000010
+ 00010 -> 000000000000000000000000000100
+ 00011 -> 000000000000000000000000001000
+ 00100 -> 000000000000000000000000010000
+ 00101 -> 000000000000000000000000100000
+ 00110 -> 000000000000000000000001000000
+ 00111 -> 000000000000000000000010000000
+ 01000 -> 000000000000000000000100000000
+ 01001 -> 000000000000000000001000000000
+ 01010 -> 000000000000000000010000000000
+ 01011 -> 000000000000000000100000000000
+ 01100 -> 000000000000000001000000000000
+ 01101 -> 000000000000000010000000000000
+ 01110 -> 000000000000000100000000000000
+ 01111 -> 000000000000001000000000000000
+ 10000 -> 000000000000010000000000000000
+ 10001 -> 000000000000100000000000000000
+ 10010 -> 000000000001000000000000000000
+ 10011 -> 000000000010000000000000000000
+ 10100 -> 000000000100000000000000000000
+ 10101 -> 000000001000000000000000000000
+ 10110 -> 000000010000000000000000000000
+ 10111 -> 000000100000000000000000000000
+ 11000 -> 000001000000000000000000000000
+ 11001 -> 000010000000000000000000000000
+ 11010 -> 000100000000000000000000000000
+ 11011 -> 001000000000000000000000000000
+ 11100 -> 010000000000000000000000000000
+ 11101 -> 100000000000000000000000000000
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.10.THE_ALU.nc_corr_data_qqq[21], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[21]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.4.THE_ALU.nc_corr_data_qqq[21], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[21]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.11.THE_ALU.nc_corr_data_qqq[21], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[21]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.3.THE_ALU.nc_corr_data_qqq[21], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[21]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.5.THE_ALU.nc_corr_data_qqq[21], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[21]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.7.THE_ALU.nc_corr_data_qqq[21], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[21]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.12.THE_ALU.nc_corr_data_qqq[21], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[21]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.9.THE_ALU.nc_corr_data_qqq[21], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[21]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.0.THE_ALU.nc_corr_data_qqq[21], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[21]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.15.THE_ALU.nc_corr_data_qqq[21], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[21]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.6.THE_ALU.nc_corr_data_qqq[21], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[21]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.13.THE_ALU.nc_corr_data_qqq[21], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[21]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.2.THE_ALU.nc_corr_data_qqq[21], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[21]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.8.THE_ALU.nc_corr_data_qqq[21], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[21]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.1.THE_ALU.nc_corr_data_qqq[21], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[21]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.1\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.1\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.8\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.8\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.2\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.2\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.13\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.13\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.6\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.6\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.15\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.15\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.0\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.0\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.9\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.9\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.12\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.12\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.7\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.7\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.5\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.5\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.3\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.3\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.11\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.11\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.4\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.4\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.10\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.10\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":218:1:218:2|Found addmux in view:work.ped_corr_ctrl(behavioral) inst GEN_ALU\.14\.THE_ALU.nc_corr_data_q_0[13:0] from GEN_ALU\.14\.THE_ALU.THE_NC_CORR_PROC\.nc_corr_data_q_2[13:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.10.THE_ALU.nc_corr_data_qqq[14], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.4.THE_ALU.nc_corr_data_qqq[14], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.11.THE_ALU.nc_corr_data_qqq[14], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.3.THE_ALU.nc_corr_data_qqq[14], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.5.THE_ALU.nc_corr_data_qqq[14], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.7.THE_ALU.nc_corr_data_qqq[14], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.12.THE_ALU.nc_corr_data_qqq[14], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.9.THE_ALU.nc_corr_data_qqq[14], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.0.THE_ALU.nc_corr_data_qqq[14], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.15.THE_ALU.nc_corr_data_qqq[14], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.6.THE_ALU.nc_corr_data_qqq[14], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.13.THE_ALU.nc_corr_data_qqq[14], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.2.THE_ALU.nc_corr_data_qqq[14], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.8.THE_ALU.nc_corr_data_qqq[14], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.1.THE_ALU.nc_corr_data_qqq[14], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.10.THE_ALU.nc_corr_data_qqq[15], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.4.THE_ALU.nc_corr_data_qqq[15], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.11.THE_ALU.nc_corr_data_qqq[15], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.3.THE_ALU.nc_corr_data_qqq[15], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.5.THE_ALU.nc_corr_data_qqq[15], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.7.THE_ALU.nc_corr_data_qqq[15], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.12.THE_ALU.nc_corr_data_qqq[15], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.9.THE_ALU.nc_corr_data_qqq[15], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.0.THE_ALU.nc_corr_data_qqq[15], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.15.THE_ALU.nc_corr_data_qqq[15], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.6.THE_ALU.nc_corr_data_qqq[15], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.13.THE_ALU.nc_corr_data_qqq[15], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.2.THE_ALU.nc_corr_data_qqq[15], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.8.THE_ALU.nc_corr_data_qqq[15], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.1.THE_ALU.nc_corr_data_qqq[15], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.10.THE_ALU.nc_corr_data_qqq[16], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.4.THE_ALU.nc_corr_data_qqq[16], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.11.THE_ALU.nc_corr_data_qqq[16], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.3.THE_ALU.nc_corr_data_qqq[16], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.5.THE_ALU.nc_corr_data_qqq[16], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.7.THE_ALU.nc_corr_data_qqq[16], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.12.THE_ALU.nc_corr_data_qqq[16], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.9.THE_ALU.nc_corr_data_qqq[16], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.0.THE_ALU.nc_corr_data_qqq[16], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.15.THE_ALU.nc_corr_data_qqq[16], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.6.THE_ALU.nc_corr_data_qqq[16], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.13.THE_ALU.nc_corr_data_qqq[16], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.2.THE_ALU.nc_corr_data_qqq[16], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.8.THE_ALU.nc_corr_data_qqq[16], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.1.THE_ALU.nc_corr_data_qqq[16], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.10.THE_ALU.nc_corr_data_qqq[17], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[17]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.4.THE_ALU.nc_corr_data_qqq[17], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[17]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.11.THE_ALU.nc_corr_data_qqq[17], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[17]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.3.THE_ALU.nc_corr_data_qqq[17], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[17]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.5.THE_ALU.nc_corr_data_qqq[17], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[17]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.7.THE_ALU.nc_corr_data_qqq[17], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[17]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.12.THE_ALU.nc_corr_data_qqq[17], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[17]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.9.THE_ALU.nc_corr_data_qqq[17], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[17]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.0.THE_ALU.nc_corr_data_qqq[17], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[17]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.15.THE_ALU.nc_corr_data_qqq[17], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[17]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.6.THE_ALU.nc_corr_data_qqq[17], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[17]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.13.THE_ALU.nc_corr_data_qqq[17], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[17]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.2.THE_ALU.nc_corr_data_qqq[17], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[17]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.8.THE_ALU.nc_corr_data_qqq[17], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[17]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.1.THE_ALU.nc_corr_data_qqq[17], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[17]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.10.THE_ALU.nc_corr_data_qqq[18], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[18]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.4.THE_ALU.nc_corr_data_qqq[18], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[18]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.11.THE_ALU.nc_corr_data_qqq[18], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[18]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.3.THE_ALU.nc_corr_data_qqq[18], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[18]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.5.THE_ALU.nc_corr_data_qqq[18], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[18]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.7.THE_ALU.nc_corr_data_qqq[18], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[18]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.12.THE_ALU.nc_corr_data_qqq[18], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[18]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.9.THE_ALU.nc_corr_data_qqq[18], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[18]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.0.THE_ALU.nc_corr_data_qqq[18], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[18]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.15.THE_ALU.nc_corr_data_qqq[18], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[18]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.6.THE_ALU.nc_corr_data_qqq[18], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[18]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.13.THE_ALU.nc_corr_data_qqq[18], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[18]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.2.THE_ALU.nc_corr_data_qqq[18], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[18]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.8.THE_ALU.nc_corr_data_qqq[18], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[18]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.1.THE_ALU.nc_corr_data_qqq[18], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[18]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.10.THE_ALU.nc_corr_data_qqq[19], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[19]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.4.THE_ALU.nc_corr_data_qqq[19], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[19]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.11.THE_ALU.nc_corr_data_qqq[19], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[19]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.3.THE_ALU.nc_corr_data_qqq[19], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[19]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.5.THE_ALU.nc_corr_data_qqq[19], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[19]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.7.THE_ALU.nc_corr_data_qqq[19], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[19]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.12.THE_ALU.nc_corr_data_qqq[19], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[19]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.9.THE_ALU.nc_corr_data_qqq[19], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[19]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.0.THE_ALU.nc_corr_data_qqq[19], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[19]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.15.THE_ALU.nc_corr_data_qqq[19], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[19]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.6.THE_ALU.nc_corr_data_qqq[19], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[19]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.13.THE_ALU.nc_corr_data_qqq[19], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[19]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.2.THE_ALU.nc_corr_data_qqq[19], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[19]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.8.THE_ALU.nc_corr_data_qqq[19], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[19]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":254:1:254:2|Removing instance THE_PED_CORR_STAGE.GEN_ALU.1.THE_ALU.nc_corr_data_qqq[19], because it is equivalent to instance THE_PED_CORR_STAGE.GEN_ALU.14.THE_ALU.nc_corr_data_qqq[19]
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":203:39:203:72|Found 8 bit by 8 bit '==' comparator, 'un317_next_row_match'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":206:39:206:72|Found 8 bit by 8 bit '==' comparator, 'un341_next_row_match'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":209:39:209:72|Found 8 bit by 8 bit '==' comparator, 'un365_next_row_match'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":164:38:164:70|Found 8 bit by 8 bit '==' comparator, 'un5_next_row_match'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":167:38:167:70|Found 8 bit by 8 bit '==' comparator, 'un29_next_row_match'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":170:38:170:70|Found 8 bit by 8 bit '==' comparator, 'un53_next_row_match'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":173:38:173:70|Found 8 bit by 8 bit '==' comparator, 'un77_next_row_match'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":176:38:176:70|Found 8 bit by 8 bit '==' comparator, 'un101_next_row_match'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":179:38:179:70|Found 8 bit by 8 bit '==' comparator, 'un125_next_row_match'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":182:38:182:70|Found 8 bit by 8 bit '==' comparator, 'un149_next_row_match'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":185:38:185:70|Found 8 bit by 8 bit '==' comparator, 'un173_next_row_match'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":188:38:188:70|Found 8 bit by 8 bit '==' comparator, 'un197_next_row_match'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":191:38:191:70|Found 8 bit by 8 bit '==' comparator, 'un221_next_row_match'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":194:39:194:72|Found 8 bit by 8 bit '==' comparator, 'un245_next_row_match'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":197:39:197:72|Found 8 bit by 8 bit '==' comparator, 'un269_next_row_match'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ref_row_sel.vhd":200:39:200:72|Found 8 bit by 8 bit '==' comparator, 'un293_next_row_match'
+Encoding state machine work.buf_toc(behavioral)-CURRENT_STATE[0:8]
+original code -> new code
+ 0000 -> 000000001
+ 0001 -> 000000010
+ 0010 -> 000000100
+ 0011 -> 000001000
+ 0100 -> 000010000
+ 0101 -> 000100000
+ 0110 -> 001000000
+ 0111 -> 010000000
+ 1000 -> 100000000
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.6\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.6\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.6\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.2\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.2\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.2\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.7\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.7\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.7\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.5\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.5\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.5\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.3\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.3\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.3\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.1\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.1\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.1\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.13\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.13\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.13\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.9\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.9\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.9\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.8\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.8\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.8\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.14\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.14\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.14\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.11\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.11\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.11\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.15\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.15\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.15\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.12\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.12\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.12\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.10\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.10\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_digital.vhd":97:1:97:2|Removing sequential instance GEN_ADC1\.10\.THE_APV_LOCKER.THE_APV_DIGITAL.bit_data[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.10\.THE_APV_LOCKER.pc_ctr[5:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.12\.THE_APV_LOCKER.pc_ctr[5:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.15\.THE_APV_LOCKER.pc_ctr[5:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.11\.THE_APV_LOCKER.pc_ctr[5:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.14\.THE_APV_LOCKER.pc_ctr[5:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.8\.THE_APV_LOCKER.pc_ctr[5:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.9\.THE_APV_LOCKER.pc_ctr[5:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.13\.THE_APV_LOCKER.pc_ctr[5:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.4\.THE_APV_LOCKER.pc_ctr[5:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.0\.THE_APV_LOCKER.pc_ctr[5:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.1\.THE_APV_LOCKER.pc_ctr[5:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.3\.THE_APV_LOCKER.pc_ctr[5:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.5\.THE_APV_LOCKER.pc_ctr[5:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.7\.THE_APV_LOCKER.pc_ctr[5:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.2\.THE_APV_LOCKER.pc_ctr[5:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":249:1:249:2|Found counter in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.6\.THE_APV_LOCKER.pc_ctr[5:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC1\.11\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC1\.11\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC1\.11\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC1\.9\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC1\.9\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC1\.9\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC1\.8\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC1\.8\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC1\.8\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC1\.15\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC1\.15\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC1\.15\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC1\.14\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC1\.14\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC1\.14\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC1\.12\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC1\.12\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC1\.12\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC1\.13\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC1\.13\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC1\.13\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC1\.10\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC1\.10\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC1\.10\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC0\.0\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC0\.0\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC0\.0\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC0\.6\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC0\.6\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC0\.6\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC0\.7\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC0\.7\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC0\.7\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC0\.2\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC0\.2\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC0\.2\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC0\.5\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC0\.5\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC0\.5\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC0\.1\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC0\.1\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC0\.1\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC0\.3\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC0\.3\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC0\.3\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":258:2:258:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_BUF_LEVEL_COUNTER_PROC\.buf_level_4[4:0] from GEN_ADC0\.4\.THE_APV_RAW_BUFFER.un1_buf_level[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":341:2:341:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_BUF_FREE_COUNTER_PROC\.buf_free_ctr_3[4:0] from GEN_ADC0\.4\.THE_APV_RAW_BUFFER.un1_buf_free_ctr[4:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_raw_buffer.vhd":321:2:321:3|Found addmux in view:work.raw_buf_stage(behavioral) inst GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_APV_FREE_COUNTER_PROC\.apv_free_ctr_4[4:0] from GEN_ADC0\.4\.THE_APV_RAW_BUFFER.un1_apv_free_ctr[4:0]
+Encoding state machine work.apv_lock_sm(behavioral)-CURRENT_STATE[0:21]
+original code -> new code
+ 00000 -> 0000000000000000000001
+ 00001 -> 0000000000000000000010
+ 00010 -> 0000000000000000000100
+ 00011 -> 0000000000000000001000
+ 00100 -> 0000000000000000010000
+ 00101 -> 0000000000000000100000
+ 00110 -> 0000000000000001000000
+ 00111 -> 0000000000000010000000
+ 01000 -> 0000000000000100000000
+ 01001 -> 0000000000001000000000
+ 01010 -> 0000000000010000000000
+ 01011 -> 0000000000100000000000
+ 01100 -> 0000000001000000000000
+ 01101 -> 0000000010000000000000
+ 01110 -> 0000000100000000000000
+ 01111 -> 0000001000000000000000
+ 10000 -> 0000010000000000000000
+ 10001 -> 0000100000000000000000
+ 10010 -> 0001000000000000000000
+ 10011 -> 0010000000000000000000
+ 10100 -> 0100000000000000000000
+ 10101 -> 1000000000000000000000
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_data_handler.vhd":295:1:295:2|Found counter in view:work.adc_data_handler_THE_ADC1_HANDLER(behavioral) inst bitcounter[2:0]
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_data_handler.vhd":295:1:295:2|Found counter in view:work.adc_data_handler_THE_ADC0_HANDLER(behavioral) inst bitcounter[2:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/eds_buf.vhd":91:2:91:3|Found addmux in view:work.apv_trgctrl(behavioral) inst THE_EDS_BUF.THE_EDS_FREE_COUNTER_PROC\.eds_free_ctr_4[4:0] from THE_EDS_BUF.un1_eds_free_ctr_1[4:0]
+Encoding state machine work.real_trg_handler(behavioral)-CURRENT_STATE[0:16]
+original code -> new code
+ 00000 -> 00000000000000001
+ 00001 -> 00000000000000010
+ 00010 -> 00000000000000100
+ 00011 -> 00000000000001000
+ 00100 -> 00000000000010000
+ 00101 -> 00000000000100000
+ 00110 -> 00000000001000000
+ 00111 -> 00000000010000000
+ 01000 -> 00000000100000000
+ 01001 -> 00000001000000000
+ 01010 -> 00000010000000000
+ 01011 -> 00000100000000000
+ 01100 -> 00001000000000000
+ 01101 -> 00010000000000000
+ 01110 -> 00100000000000000
+ 01111 -> 01000000000000000
+ 10000 -> 10000000000000000
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":492:2:492:3|Found addmux in view:work.real_trg_handler(behavioral) inst THE_EVENT_COUNTER_PROC\.evtctr_4[15:0] from un1_ce_evtctr[16:1]
+Encoding state machine work.apv_trg_handler(behavioral)-CURRENT_STATE[0:6]
+original code -> new code
+ 000 -> 0000001
+ 001 -> 0000010
+ 010 -> 0000100
+ 011 -> 0001000
+ 100 -> 0010000
+ 101 -> 0100000
+ 110 -> 1000000
+Encoding state machine work.apv_sync_handler(behavioral)-CURRENT_STATE[0:9]
+original code -> new code
+ 0000 -> 0000000001
+ 0001 -> 0000000010
+ 0010 -> 0000000100
+ 0011 -> 0000001000
+ 0100 -> 0000010000
+ 0101 -> 0000100000
+ 0110 -> 0001000000
+ 0111 -> 0010000000
+ 1000 -> 0100000000
+ 1001 -> 1000000000
+Encoding state machine work.trb_net16_lsm_sfp(lsm_sfp)-CURRENT_STATE[0:9]
+original code -> new code
+ 0000 -> 0000
+ 0001 -> 0001
+ 0010 -> 0010
+ 0011 -> 0011
+ 0100 -> 0100
+ 0101 -> 0101
+ 0110 -> 0110
+ 0111 -> 0111
+ 1000 -> 1000
+ 1001 -> 1001
+@N:"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd":106:2:106:3|Found counter in view:work.trb_net16_lsm_sfp(lsm_sfp) inst timing_ctr[28:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":763:8:763:9|Found addmux in view:work.trb_net16_endpoint_hades_full(trb_net16_endpoint_hades_full_arch) inst proc_internal_trigger_number\.int_trigger_num_4[15:0] from un1_LVL1_TRG_RECEIVED_OUT_falling[16:1]
+@N: MF179 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_endpoint_hades_full.vhd":779:13:779:53|Found 16 bit by 16 bit '==' comparator, 'proc_check_trigger_number\.un4_lvl1_trg_received_out_rising'
+@N:"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Found counter in view:work.trb_net16_iobufZ1(trb_net16_iobuf_arch) inst GEN_IBUF\.THE_IBUF.data_counter[31:0]
+@N:"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Found counter in view:work.trb_net16_iobufZ1(trb_net16_iobuf_arch) inst GEN_IBUF\.THE_IBUF.reply_buffer_number[15:0]
+@N:"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Found counter in view:work.trb_net16_iobufZ1(trb_net16_iobuf_arch) inst GEN_IBUF\.THE_IBUF.init_buffer_number[15:0]
+Encoding state machine work.trb_net_sbufZ0_gen_version_0\.sbuf_5_gen_version_0\.sbuf_1_gen_init_sbuf\.SBUF_INIT_gen_version_0\.sbuf_gen_init_sbuf\.SBUF_INIT_gen_version_0\.sbuf(trb_net_sbuf_arch)-current_buffer_state[0:2]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+Encoding state machine work.trb_net16_obuf_nodata_genINITOBUF2\.gen_INITOBUF3\.INITOBUF_0_genINITOBUF2\.gen_INITOBUF3\.INITOBUF(trb_net16_obuf_nodata_arch)-buf_MED_PACKET_NUM_OUT[0:7]
+original code -> new code
+ 000 -> 00000001
+ 001 -> 00000010
+ 010 -> 00000100
+ 011 -> 00001000
+ 100 -> 00010000
+ 101 -> 00100000
+ 110 -> 01000000
+ 111 -> 10000000
+@N: BN116 :|Removing sequential instance buf_MED_PACKET_NUM_OUT_i[7] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Removing sequential instance buf_MED_DATA_OUT[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+Encoding state machine work.trb_net16_obuf_1_0_7_0(trb_net16_obuf_arch)-sending_state[0:2]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+@N:"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":448:8:448:9|Found counter in view:work.trb_net16_obuf_1_0_7_0(trb_net16_obuf_arch) inst buffer_number[15:0]
+@N:"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":249:6:249:7|Found counter in view:work.trb_net16_obuf_1_0_7_0(trb_net16_obuf_arch) inst transfer_counter[2:0]
+@N:"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":411:8:411:9|Found counter in view:work.trb_net16_obuf_1_0_7_0(trb_net16_obuf_arch) inst CURRENT_DATA_COUNT[6:0]
+@N: MF179 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":198:30:198:74|Found 7 bit by 7 bit '==' comparator, 'gen1\.send_eob'
+Encoding state machine work.trb_net_sbufZ0_gen_version_0\.sbuf_5_gen_version_0\.sbuf_1_MUX_SBUF_gen_version_0\.sbuf_THE_SBUF_gen_version_0\.sbuf_THE_SBUF_gen_version_0\.sbuf(trb_net_sbuf_arch)-current_buffer_state[0:2]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+Encoding state machine work.trb_net_sbufZ0_gen_version_0\.sbuf_5_gen_version_0\.sbuf_1_gen_init_sbuf\.SBUF_INIT_gen_version_0\.sbuf_GEN_IBUF\.THE_IBUF_gen_init_sbuf\.SBUF_INIT_gen_version_0\.sbuf(trb_net_sbuf_arch)-current_buffer_state[0:2]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+Encoding state machine work.trb_net16_obuf_nodata_genINITOBUF2\.gen_INITOBUF3\.INITOBUF_0_genINITOBUF2\.gen_INITOBUF3\.INITOBUF_1_genINITOBUF2\.gen_INITOBUF3\.INITOBUF(trb_net16_obuf_nodata_arch)-buf_MED_PACKET_NUM_OUT[0:7]
+original code -> new code
+ 000 -> 00000001
+ 001 -> 00000010
+ 010 -> 00000100
+ 011 -> 00001000
+ 100 -> 00010000
+ 101 -> 00100000
+ 110 -> 01000000
+ 111 -> 10000000
+@N: BN116 :|Removing sequential instance buf_MED_PACKET_NUM_OUT_i[7] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Removing sequential instance buf_MED_DATA_OUT[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+Encoding state machine work.trb_net16_obuf_1_1_7_0(trb_net16_obuf_arch)-sending_state[0:2]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+@N: MF179 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":198:30:198:74|Found 7 bit by 7 bit '==' comparator, 'gen1\.send_eob'
+Encoding state machine work.trb_net_sbufZ0(trb_net_sbuf_arch)-current_buffer_state[0:2]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+Encoding state machine work.trb_net_sbufZ0_gen_version_0\.sbuf_5_gen_version_0\.sbuf_1_gen_init_sbuf\.SBUF_INIT_gen_version_0\.sbuf_GEN_IBUF\.THE_IBUF_gen_init_sbuf\.SBUF_INIT_gen_version_0\.sbuf_0(trb_net_sbuf_arch)-current_buffer_state[0:2]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+Encoding state machine work.trb_net16_obuf_nodata_genINITOBUF2\.gen_INITOBUF3\.INITOBUF_0_genINITOBUF2\.gen_INITOBUF3\.INITOBUF_1_genINITOBUF2\.gen_INITOBUF3\.INITOBUF_0(trb_net16_obuf_nodata_arch)-buf_MED_PACKET_NUM_OUT[0:7]
+original code -> new code
+ 000 -> 00000001
+ 001 -> 00000010
+ 010 -> 00000100
+ 011 -> 00001000
+ 100 -> 00010000
+ 101 -> 00100000
+ 110 -> 01000000
+ 111 -> 10000000
+@N: BN116 :|Removing sequential instance buf_MED_PACKET_NUM_OUT_i[7] of view:PrimLib.dff(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf_nodata.vhd":62:6:62:7|Removing sequential instance buf_MED_DATA_OUT[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+Encoding state machine work.trb_net16_api_base_genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API_genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API(trb_net16_api_base_arch)-state_to_int[0:5]
+original code -> new code
+ 000 -> 000001
+ 001 -> 000010
+ 010 -> 000100
+ 011 -> 001000
+ 100 -> 010000
+ 101 -> 100000
+Encoding state machine work.trb_net16_api_base_genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API_genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API(trb_net16_api_base_arch)-state_to_apl[0:3]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+ 11 -> 11
+@N: MF179 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":651:21:651:93|Found 16 bit by 16 bit '==' comparator, 'to_apl\.un9_int_slave_dataready_in'
+Encoding state machine work.trb_net_sbufZ0_gen_version_0\.sbuf_5_gen_version_0\.sbuf_1_MUX_SBUF_gen_version_0\.sbuf_MUX_SBUF_gen_version_0\.sbuf_SBUF_gen_version_0\.sbuf(trb_net_sbuf_arch)-current_buffer_state[0:2]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+Encoding state machine work.trb_net_sbufZ0_gen_version_0\.sbuf_5_gen_version_0\.sbuf_1_MUX_SBUF_gen_version_0\.sbuf_MUX_SBUF_gen_version_0\.sbuf_SBUF_TO_APL_gen_version_0\.sbuf(trb_net_sbuf_arch)-current_buffer_state[0:2]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+Encoding state machine work.trb_net_sbuf_3_0_SBUF_TO_APL2(trb_net_sbuf_arch)-current_buffer_state[0:2]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+Encoding state machine work.trb_net16_api_base_genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API(trb_net16_api_base_arch)-state_to_int[0:5]
+original code -> new code
+ 000 -> 000001
+ 001 -> 000010
+ 010 -> 000100
+ 011 -> 001000
+ 100 -> 010000
+ 101 -> 100000
+Encoding state machine work.trb_net16_api_base_genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API(trb_net16_api_base_arch)-state_to_apl[0:3]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+ 11 -> 11
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[14], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[13], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[12], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[11], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[10], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[9], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[8], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[7], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[6], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[5], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[4], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[3], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[2], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[1], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[0], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API.registered_header_F2[15]
+@N: MF179 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":651:21:651:93|Found 16 bit by 16 bit '==' comparator, 'to_apl\.un9_int_slave_dataready_in'
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F1[15] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F1[14] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F1[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F1[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F1[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F1[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F1[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F1[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F1[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F1[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F1[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F1[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F1[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F2[15] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F2[14] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F2[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F2[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F2[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F2[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F2[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F2[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F2[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F2[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F2[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F2[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F2[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance registered_trailer_F2[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+Encoding state machine work.trb_net_sbufZ0_gen_version_0\.sbuf_5_gen_version_0\.sbuf_1_MUX_SBUF_gen_version_0\.sbuf_MUX_SBUF_gen_version_0\.sbuf_SBUF_gen_version_0\.sbuf_0(trb_net_sbuf_arch)-current_buffer_state[0:2]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+Encoding state machine work.trb_net_sbufZ0_gen_version_0\.sbuf_5_gen_version_0\.sbuf_1_MUX_SBUF_gen_version_0\.sbuf_MUX_SBUF_gen_version_0\.sbuf_SBUF_TO_APL_gen_version_0\.sbuf_0(trb_net_sbuf_arch)-current_buffer_state[0:2]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+Encoding state machine work.trb_net_sbuf_3_0_SBUF_TO_APL2_1(trb_net_sbuf_arch)-current_buffer_state[0:2]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+@N:"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":164:6:164:7|Found counter in view:work.trb_net16_trigger(trb_net16_trigger_arch) inst transfer_counter[2:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[30], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[29], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[28], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[27], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[26], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[25], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[24], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[21], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[20], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[19], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[18], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[15], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[14], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[13], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[12], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[11], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[10], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[9], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[8], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[7], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[6], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[5], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[4], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[3], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[2], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[1], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_TRG_ERROR_PATTERN_IN[31]
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":150:6:150:7|Removing sequential instance buf_TRG_ERROR_PATTERN_IN[31] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":183:6:183:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_INT_DATA_OUT[14], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_INT_DATA_OUT[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":183:6:183:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_INT_DATA_OUT[13], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_INT_DATA_OUT[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":183:6:183:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_INT_DATA_OUT[12], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_INT_DATA_OUT[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":183:6:183:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_INT_DATA_OUT[3], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_INT_DATA_OUT[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":183:6:183:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_INT_DATA_OUT[2], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.gentrgapi.the_trigger_apl.buf_INT_DATA_OUT[15]
+Encoding state machine work.trb_net16_ipudata(trb_net16_ipudata_arch)-state[0:3]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+ 11 -> 11
+@N:"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Found counter in view:work.trb_net16_ipudata(trb_net16_ipudata_arch) inst buf_IPU_LENGTH_IN[15:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[30], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[29], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[28], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[27], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[26], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[25], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[24], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[23], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[21], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[19], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[15], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[14], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[13], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[12], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[11], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[10], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[9], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[8], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[7], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[6], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[5], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[4], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[3], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[2], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[1], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[0], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_ipu_apl.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[31]
+@N: MF179 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":275:13:275:54|Found 8 bit by 8 bit '==' comparator, 'PROC_compare\.un20_make_compare'
+@N: MF179 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":272:13:272:51|Found 16 bit by 16 bit '==' comparator, 'PROC_compare\.un15_make_compare'
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing sequential instance buf_IPU_ERROR_PATTERN_IN[31] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+Encoding state machine work.trb_net16_regIO(trb_net16_regio_arch)-current_state[0:18]
+original code -> new code
+ 00000 -> 0000000000000000001
+ 00001 -> 0000000000000000010
+ 00010 -> 0000000000000000100
+ 00011 -> 0000000000000001000
+ 00100 -> 0000000000000010000
+ 00101 -> 0000000000000100000
+ 00110 -> 0000000000001000000
+ 00111 -> 0000000000010000000
+ 01000 -> 0000000000100000000
+ 01001 -> 0000000001000000000
+ 01010 -> 0000000010000000000
+ 01011 -> 0000000100000000000
+ 01100 -> 0000001000000000000
+ 01101 -> 0000010000000000000
+ 01110 -> 0000100000000000000
+ 01111 -> 0001000000000000000
+ 10000 -> 0010000000000000000
+ 10001 -> 0100000000000000000
+ 10010 -> 1000000000000000000
+@N:"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":921:6:921:7|Found counter in view:work.trb_net16_regIO(trb_net16_regio_arch) inst time_since_last_trg_i[31:0]
+@N:"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":884:6:884:7|Found counter in view:work.trb_net16_regIO(trb_net16_regio_arch) inst global_time_i[31:0]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":669:8:669:9|Found addmux in view:work.trb_net16_regIO(trb_net16_regio_arch) inst reg_fsm\.length_3[15:0] from un1_next_length_1_sqmuxa[16:1]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":299:6:299:9|Found addmux in view:work.trb_net16_regIO(trb_net16_regio_arch) inst next_address[15:0] from un1_next_address_1_sqmuxa_2[16:1]
+@N: FX404 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":299:6:299:9|Found addmux in view:work.trb_net16_regIO(trb_net16_regio_arch) inst next_dat_data_counter[15:0] from un1_next_Reg_low_1_sqmuxa[16:1]
+Encoding state machine work.trb_net16_addresses(trb_net16_addresses_arch)-state[0:4]
+original code -> new code
+ 000 -> 00001
+ 001 -> 00010
+ 010 -> 00100
+ 011 -> 01000
+ 100 -> 10000
+@N: MF235 :"/home/mboehmer/VHDL_Pro/trbnet/basics/ram_16x16_dp.vhd":41:9:41:11|Found startup values on ram instance THE_STAT_RAM.ram_1[15:0]
+@N: MF179 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_addresses.vhd":138:17:138:43|Found 16 bit by 16 bit '==' comparator, 'proc_read_id\.un29_clk_en'
+@N: FX276 :"/home/mboehmer/VHDL_Pro/trbnet/basics/ram_16x16_dp.vhd":41:9:41:11|Startup value ram_1_0_0.INITVAL_00 = 0000000000000000000000000000000000005EAD01111022220ACAD000010DEAD0BEEF0AFFE0D00F
+@N:"/home/mboehmer/VHDL_Pro/trbnet/trb_net_onewire.vhd":268:6:268:7|Found counter in view:work.trb_net_onewire(trb_net_onewire_arch) inst timecounter[27:0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_term_buf.vhd":196:8:196:9|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.2.gentermbuf.termbuf.buf_MED_REPLY_DATA_OUT[0], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.2.gentermbuf.termbuf.buf_MED_REPLY_DATA_OUT[1]
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_rr_mask[7] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_rr_mask[6] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_rr_mask[5] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_rr_mask[4] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_rr_mask[3] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_rr_mask[2] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_rr_mask[1] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_rr_mask[0] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p2_pattern[7] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p2_pattern[6] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p2_pattern[5] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p2_pattern[4] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p2_pattern[3] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p2_pattern[2] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p2_pattern[1] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p2_pattern[0] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p1_pattern[7] of view:UNILIB.FDSE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p1_pattern[6] of view:UNILIB.FDSE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p1_pattern[5] of view:UNILIB.FDSE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p1_pattern[4] of view:UNILIB.FDSE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p1_pattern[3] of view:UNILIB.FDSE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p1_pattern[2] of view:UNILIB.FDSE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p1_pattern[1] of view:UNILIB.FDSE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_priority_arbiter.vhd":159:4:159:5|Removing sequential instance ARBITER.current_p1_pattern[0] of view:UNILIB.FDSE(PRIM) because there are no references to its outputs
+Encoding state machine work.trb_net_sbufZ0_gen_version_0\.sbuf_5_gen_version_0\.sbuf_1_MUX_SBUF_gen_version_0\.sbuf_MUX_SBUF_gen_version_0\.sbuf_MUX_SBUF_gen_version_0\.sbuf(trb_net_sbuf_arch)-current_buffer_state[0:2]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regio_bus_handler.vhd":90:6:90:7|Removing sequential instance THE_BUS_HANDLER.buf_BUS_ADDR_OUT[15] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regio_bus_handler.vhd":90:6:90:7|Removing sequential instance THE_BUS_HANDLER.buf_BUS_ADDR_OUT[14] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regio_bus_handler.vhd":90:6:90:7|Removing sequential instance THE_BUS_HANDLER.buf_BUS_ADDR_OUT[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regio_bus_handler.vhd":90:6:90:7|Removing sequential instance THE_BUS_HANDLER.buf_BUS_ADDR_OUT[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regio_bus_handler.vhd":90:6:90:7|Removing sequential instance THE_BUS_HANDLER.buf_BUS_ADDR_OUT[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+Encoding state machine work.slv_ped_thr_mem_THE_PED_MEM(behavioral)-CURRENT_STATE[0:9]
+original code -> new code
+ 0000 -> 0000000001
+ 0001 -> 0000000010
+ 0010 -> 0000000100
+ 0011 -> 0000001000
+ 0100 -> 0000010000
+ 0101 -> 0000100000
+ 0110 -> 0001000000
+ 0111 -> 0010000000
+ 1000 -> 0100000000
+ 1001 -> 1000000000
+Encoding state machine work.slv_ped_thr_mem_THE_THR_MEM_0(behavioral)-CURRENT_STATE[0:9]
+original code -> new code
+ 0000 -> 0000000001
+ 0001 -> 0000000010
+ 0010 -> 0000000100
+ 0011 -> 0000001000
+ 0100 -> 0000010000
+ 0101 -> 0000100000
+ 0110 -> 0001000000
+ 0111 -> 0010000000
+ 1000 -> 0100000000
+ 1001 -> 1000000000
+Encoding state machine work.i2c_master(behavioral)-CURRENT_STATE[0:7]
+original code -> new code
+ 000 -> 00000001
+ 001 -> 00000010
+ 010 -> 00000100
+ 011 -> 00001000
+ 100 -> 00010000
+ 101 -> 00100000
+ 110 -> 01000000
+ 111 -> 10000000
+Encoding state machine work.i2c_slim(behavioral)-CURRENT_STATE[0:18]
+original code -> new code
+ 00000 -> 0000000000000000001
+ 00001 -> 0000000000000000010
+ 00010 -> 0000000000000000100
+ 00011 -> 0000000000000001000
+ 00100 -> 0000000000000010000
+ 00101 -> 0000000000000100000
+ 00110 -> 0000000000001000000
+ 00111 -> 0000000000010000000
+ 01000 -> 0000000000100000000
+ 01001 -> 0000000001000000000
+ 01010 -> 0000000010000000000
+ 01011 -> 0000000100000000000
+ 01100 -> 0000001000000000000
+ 01101 -> 0000010000000000000
+ 01110 -> 0000100000000000000
+ 01111 -> 0001000000000000000
+ 10000 -> 0010000000000000000
+ 10001 -> 0100000000000000000
+ 10010 -> 1000000000000000000
+Encoding state machine work.i2c_sendb(behavioral)-CURRENT_STATE[0:6]
+original code -> new code
+ 000 -> 0000001
+ 001 -> 0000010
+ 010 -> 0000100
+ 011 -> 0001000
+ 100 -> 0010000
+ 101 -> 0100000
+ 110 -> 1000000
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_sendb.vhd":96:2:96:3|Found addmux in view:work.i2c_sendb(behavioral) inst THE_CYC_CTR_PROC\.cctr_4[7:0] from un1_dec_cyc[8:1]
+Encoding state machine work.I2C_GSTART(behavioral)-CURRENT_STATE[0:10]
+original code -> new code
+ 0000 -> 00000000001
+ 0001 -> 00000000010
+ 0010 -> 00000000100
+ 0011 -> 00000001000
+ 0100 -> 00000010000
+ 0101 -> 00000100000
+ 0110 -> 00001000000
+ 0111 -> 00010000000
+ 1000 -> 00100000000
+ 1001 -> 01000000000
+ 1010 -> 10000000000
+@N: FX404 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_gstart.vhd":62:2:62:3|Found addmux in view:work.I2C_GSTART(behavioral) inst THE_CYC_CTR_PROC\.cctr_4[7:0] from un1_dec_cyc[8:1]
+Encoding state machine work.spi_master(behavioral)-CURRENT_STATE[0:7]
+original code -> new code
+ 000 -> 00000001
+ 001 -> 00000010
+ 010 -> 00000100
+ 011 -> 00001000
+ 100 -> 00010000
+ 101 -> 00100000
+ 110 -> 01000000
+ 111 -> 10000000
+Encoding state machine work.spi_slim(behavioral)-STATE[0:15]
+original code -> new code
+ 00000 -> 0000000000000001
+ 00001 -> 0000000000000010
+ 00010 -> 0000000000000100
+ 00011 -> 0000000000001000
+ 00100 -> 0000000000010000
+ 00101 -> 0000000000100000
+ 00110 -> 0000000001000000
+ 00111 -> 0000000010000000
+ 01000 -> 0000000100000000
+ 01001 -> 0000001000000000
+ 01010 -> 0000010000000000
+ 01011 -> 0000100000000000
+ 01101 -> 0001000000000000
+ 01110 -> 0010000000000000
+ 01111 -> 0100000000000000
+ 10000 -> 1000000000000000
+@N:"/home/mboehmer/VHDL_Pro/trbnet/special/spi_slim.vhd":551:4:551:5|Found counter in view:work.spi_slim(behavioral) inst rx_bit_cnt[2:0]
+@N:"/home/mboehmer/VHDL_Pro/trbnet/special/spi_slim.vhd":530:4:530:5|Found counter in view:work.spi_slim(behavioral) inst tx_bit_cnt[3:0]
+@N:"/home/mboehmer/VHDL_Pro/trbnet/special/spi_slim.vhd":588:4:588:5|Found counter in view:work.spi_slim(behavioral) inst addr_ctr[7:0]
+@N: MF179 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_slim.vhd":611:28:611:45|Found 8 bit by 8 bit '==' comparator, 'data_done_x'
+Encoding state machine work.spi_databus_memory(behavioral)-CURRENT_STATE[0:5]
+original code -> new code
+ 000 -> 000001
+ 001 -> 000010
+ 010 -> 000100
+ 011 -> 001000
+ 100 -> 010000
+ 101 -> 100000
+Encoding state machine work.spi_adc_master(behavioral)-CURRENT_STATE[0:7]
+original code -> new code
+ 000 -> 00000001
+ 001 -> 00000010
+ 010 -> 00000100
+ 011 -> 00001000
+ 100 -> 00010000
+ 101 -> 00100000
+ 110 -> 01000000
+ 111 -> 10000000
+Encoding state machine work.spi_real_slim(behavioral)-STATE[0:3]
+original code -> new code
+ 00 -> 00
+ 01 -> 01
+ 10 -> 10
+ 11 -> 11
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_real_slim.vhd":218:1:218:2|Found counter in view:work.spi_real_slim(behavioral) inst tx_bit_cnt[3:0]
+Encoding state machine work.slv_register_bank(behavioral)-CURRENT_STATE[0:9]
+original code -> new code
+ 0000 -> 0000000001
+ 0001 -> 0000000010
+ 0010 -> 0000000100
+ 0011 -> 0000001000
+ 0100 -> 0000010000
+ 0101 -> 0000100000
+ 0110 -> 0001000000
+ 0111 -> 0010000000
+ 1000 -> 0100000000
+ 1001 -> 1000000000
+Encoding state machine work.slv_status_bank(behavioral)-CURRENT_STATE[0:9]
+original code -> new code
+ 0000 -> 0000000001
+ 0001 -> 0000000010
+ 0010 -> 0000000100
+ 0011 -> 0000001000
+ 0100 -> 0000010000
+ 0101 -> 0000100000
+ 0110 -> 0001000000
+ 0111 -> 0010000000
+ 1000 -> 0100000000
+ 1001 -> 1000000000
+@W: MO129 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":113:1:113:2|Sequential instance THE_SLAVE_BUS.THE_FIFO_STATUS_BANK.rdback_data[12] has been reduced to a combinational gate by constant propagation
+@W: MO129 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":113:1:113:2|Sequential instance THE_SLAVE_BUS.THE_FIFO_STATUS_BANK.rdback_data[13] has been reduced to a combinational gate by constant propagation
+@W: MO129 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":113:1:113:2|Sequential instance THE_SLAVE_BUS.THE_FIFO_STATUS_BANK.rdback_data[14] has been reduced to a combinational gate by constant propagation
+@W: MO129 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":113:1:113:2|Sequential instance THE_SLAVE_BUS.THE_FIFO_STATUS_BANK.rdback_data[15] has been reduced to a combinational gate by constant propagation
+@W: MO129 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":113:1:113:2|Sequential instance THE_SLAVE_BUS.THE_FIFO_STATUS_BANK.rdback_data[19] has been reduced to a combinational gate by constant propagation
+@W: MO129 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":113:1:113:2|Sequential instance THE_SLAVE_BUS.THE_FIFO_STATUS_BANK.rdback_data[20] has been reduced to a combinational gate by constant propagation
+@W: MO129 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":113:1:113:2|Sequential instance THE_SLAVE_BUS.THE_FIFO_STATUS_BANK.rdback_data[21] has been reduced to a combinational gate by constant propagation
+@W: MO129 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":113:1:113:2|Sequential instance THE_SLAVE_BUS.THE_FIFO_STATUS_BANK.rdback_data[22] has been reduced to a combinational gate by constant propagation
+@W: MO129 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":113:1:113:2|Sequential instance THE_SLAVE_BUS.THE_FIFO_STATUS_BANK.rdback_data[23] has been reduced to a combinational gate by constant propagation
+@W: MO129 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":113:1:113:2|Sequential instance THE_SLAVE_BUS.THE_FIFO_STATUS_BANK.rdback_data[27] has been reduced to a combinational gate by constant propagation
+@W: MO129 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":113:1:113:2|Sequential instance THE_SLAVE_BUS.THE_FIFO_STATUS_BANK.rdback_data[28] has been reduced to a combinational gate by constant propagation
+@W: MO129 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":113:1:113:2|Sequential instance THE_SLAVE_BUS.THE_FIFO_STATUS_BANK.rdback_data[29] has been reduced to a combinational gate by constant propagation
+@W: MO129 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":113:1:113:2|Sequential instance THE_SLAVE_BUS.THE_FIFO_STATUS_BANK.rdback_data[30] has been reduced to a combinational gate by constant propagation
+@W: MO129 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_status_bank.vhd":113:1:113:2|Sequential instance THE_SLAVE_BUS.THE_FIFO_STATUS_BANK.rdback_data[31] has been reduced to a combinational gate by constant propagation
+Encoding state machine work.slv_status_THE_LVL1_RELEASE_STATUS(behavioral)-CURRENT_STATE[0:9]
+original code -> new code
+ 0000 -> 0000000001
+ 0001 -> 0000000010
+ 0010 -> 0000000100
+ 0011 -> 0000001000
+ 0100 -> 0000010000
+ 0101 -> 0000100000
+ 0110 -> 0001000000
+ 0111 -> 0010000000
+ 1000 -> 0100000000
+ 1001 -> 1000000000
+Encoding state machine work.slv_status(behavioral)-CURRENT_STATE[0:9]
+original code -> new code
+ 0000 -> 0000000001
+ 0001 -> 0000000010
+ 0010 -> 0000000100
+ 0011 -> 0000001000
+ 0100 -> 0000010000
+ 0101 -> 0000100000
+ 0110 -> 0001000000
+ 0111 -> 0010000000
+ 1000 -> 0100000000
+ 1001 -> 1000000000
+Encoding state machine work.slv_registerZ2(behavioral)-CURRENT_STATE[0:7]
+original code -> new code
+ 000 -> 00000001
+ 001 -> 00000010
+ 010 -> 00000100
+ 011 -> 00001000
+ 100 -> 00010000
+ 101 -> 00100000
+ 110 -> 01000000
+ 111 -> 10000000
+Encoding state machine work.slv_registerZ1(behavioral)-CURRENT_STATE[0:7]
+original code -> new code
+ 000 -> 00000001
+ 001 -> 00000010
+ 010 -> 00000100
+ 011 -> 00001000
+ 100 -> 00010000
+ 101 -> 00100000
+ 110 -> 01000000
+ 111 -> 10000000
+Encoding state machine work.slv_half_register(behavioral)-CURRENT_STATE[0:5]
+original code -> new code
+ 000 -> 000001
+ 001 -> 000010
+ 010 -> 000100
+ 011 -> 001000
+ 100 -> 010000
+ 101 -> 100000
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Removing instance THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out[19], because it is equivalent to instance THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out[23]
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Removing sequential instance reg_slv_data_out[23] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register reg_slv_data_out[23] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+Encoding state machine work.slv_adc_snoop(behavioral)-CURRENT_STATE[0:9]
+original code -> new code
+ 0000 -> 0000000001
+ 0001 -> 0000000010
+ 0010 -> 0000000100
+ 0011 -> 0000001000
+ 0100 -> 0000010000
+ 0101 -> 0000100000
+ 0110 -> 0001000000
+ 0111 -> 0010000000
+ 1000 -> 0100000000
+ 1001 -> 1000000000
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Found counter in view:work.slv_adc_snoop(behavioral) inst wr_ctr[9:0]
+Encoding state machine work.slv_registerZ0(behavioral)-CURRENT_STATE[0:7]
+original code -> new code
+ 000 -> 00000001
+ 001 -> 00000010
+ 010 -> 00000100
+ 011 -> 00001000
+ 100 -> 00010000
+ 101 -> 00100000
+ 110 -> 01000000
+ 111 -> 10000000
+Encoding state machine work.slv_onewire_memory(behavioral)-CURRENT_STATE[0:6]
+original code -> new code
+ 000 -> 0000001
+ 001 -> 0000010
+ 010 -> 0000100
+ 011 -> 0001000
+ 100 -> 0010000
+ 101 -> 0100000
+ 110 -> 1000000
+Encoding state machine work.onewire_master(onewire_master_arch)-STATE[0:14]
+original code -> new code
+ 0000 -> 000000000000001
+ 0001 -> 000000000000010
+ 0010 -> 000000000000100
+ 0011 -> 000000000001000
+ 0100 -> 000000000010000
+ 0101 -> 000000000100000
+ 0110 -> 000000001000000
+ 0111 -> 000000010000000
+ 1000 -> 000000100000000
+ 1001 -> 000001000000000
+ 1010 -> 000010000000000
+ 1011 -> 000100000000000
+ 1100 -> 001000000000000
+ 1101 -> 010000000000000
+ 1110 -> 100000000000000
+@N:"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/onewire_master.vhd":415:1:415:2|Found counter in view:work.onewire_master(onewire_master_arch) inst timecounter[27:0]
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.11\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.11\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.4\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.4\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.5\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.5\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.13\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.13\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.1\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.1\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.10\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.10\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.7\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.7\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.3\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.3\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.8\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.8\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.9\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.9\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.14\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.14\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.12\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.12\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.15\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.15\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.6\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.6\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.2\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.2\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing sequential instance GEN_TOC\.0\.THE_BUF_TOC.nodata of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":240:1:240:2|Removing sequential instance GEN_TOC\.0\.THE_BUF_TOC.stat_ignore of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[14], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[13], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[12], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[11], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[10], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[9], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[8], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[7], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[5], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[3], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F2[15], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F2[14], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F2[13], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F2[12], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F2[11], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F2[10], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F2[9], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F2[8], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F2[7], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F2[6], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F2[5], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F2[4], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F2[3], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F2[2], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F2[1], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API.registered_trailer_F1[15]
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":302:6:302:7|Removing sequential instance genbuffers\.1\.geniobuf\.gen_ipu_apl\.the_ipudata_apl.packet_number[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":225:6:225:7|Removing sequential instance genbuffers\.1\.geniobuf\.gen_ipu_apl\.the_ipudata_apl.buf_IPU_ERROR_PATTERN_IN[22] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":183:6:183:7|Removing sequential instance genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.buf_INT_DATA_OUT[15] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":502:6:502:7|Removing sequential instance genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.fifo_to_apl_empty of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":883:6:883:7|Removing sequential instance genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.master_running of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":502:6:502:7|Removing sequential instance genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.fifo_to_apl_empty of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.registered_trailer_F1[15] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":883:6:883:7|Removing sequential instance genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.slave_running of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":859:6:859:7|Removing sequential instance genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.buf_APL_RUN_OUT of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":883:6:883:7|Removing sequential instance genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.master_running of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/state_sync.vhd":27:1:27:2|Removing instance THE_SLAVE_BUS.THE_ADC0_SNOOPER.THE_RESET_SYNC.sync[0], because it is equivalent to instance THE_SLAVE_BUS.THE_ADC1_SNOOPER.THE_RESET_SYNC.sync[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/state_sync.vhd":27:1:27:2|Removing instance THE_SLAVE_BUS.THE_ADC1_SNOOPER.THE_RESET_SYNC.sync[1], because it is equivalent to instance THE_SLAVE_BUS.THE_ADC0_SNOOPER.THE_RESET_SYNC.sync[1]
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_memory.vhd":111:1:111:2|Removing sequential instance THE_ONEWIRE_MEMORY.store_rd of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC1_SNOOPER.ctrl_reg[13] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC1_SNOOPER.ctrl_reg[13] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC1_SNOOPER.ctrl_reg[12] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC1_SNOOPER.ctrl_reg[12] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC1_SNOOPER.ctrl_reg[11] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC1_SNOOPER.ctrl_reg[11] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC1_SNOOPER.ctrl_reg[10] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC1_SNOOPER.ctrl_reg[10] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC1_SNOOPER.ctrl_reg[9] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC1_SNOOPER.ctrl_reg[9] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC1_SNOOPER.ctrl_reg[8] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC1_SNOOPER.ctrl_reg[8] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC1_SNOOPER.ctrl_reg[7] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC1_SNOOPER.ctrl_reg[7] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC1_SNOOPER.ctrl_reg[6] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC1_SNOOPER.ctrl_reg[6] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC1_SNOOPER.ctrl_reg[5] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC1_SNOOPER.ctrl_reg[5] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC1_SNOOPER.ctrl_reg[4] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC1_SNOOPER.ctrl_reg[4] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC1_SNOOPER.ctrl_reg[3] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC1_SNOOPER.ctrl_reg[3] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC0_SNOOPER.ctrl_reg[13] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC0_SNOOPER.ctrl_reg[13] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC0_SNOOPER.ctrl_reg[12] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC0_SNOOPER.ctrl_reg[12] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC0_SNOOPER.ctrl_reg[11] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC0_SNOOPER.ctrl_reg[11] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC0_SNOOPER.ctrl_reg[10] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC0_SNOOPER.ctrl_reg[10] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC0_SNOOPER.ctrl_reg[9] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC0_SNOOPER.ctrl_reg[9] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC0_SNOOPER.ctrl_reg[8] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC0_SNOOPER.ctrl_reg[8] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC0_SNOOPER.ctrl_reg[7] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC0_SNOOPER.ctrl_reg[7] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC0_SNOOPER.ctrl_reg[6] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC0_SNOOPER.ctrl_reg[6] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC0_SNOOPER.ctrl_reg[5] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC0_SNOOPER.ctrl_reg[5] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC0_SNOOPER.ctrl_reg[4] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC0_SNOOPER.ctrl_reg[4] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Removing sequential instance THE_ADC0_SNOOPER.ctrl_reg[3] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_ADC0_SNOOPER.ctrl_reg[3] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_real_slim.vhd":218:1:218:2|Removing sequential instance THE_SPI_ADC1_MASTER.THE_SPI_REAL_SLIM.last_tx_bit of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_real_slim.vhd":218:1:218:2|Removing sequential instance THE_SPI_ADC0_MASTER.THE_SPI_REAL_SLIM.last_tx_bit of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_slim.vhd":225:4:225:5|Removing sequential instance THE_SPI_MASTER.THE_SPI_SLIM.tx_done of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":177:1:177:2|Removing sequential instance THE_I2C_MASTER.reg_slv_data_in[23] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":177:1:177:2|Removing sequential instance THE_I2C_MASTER.reg_slv_data_in[8] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd":135:2:135:3|Removing sequential instance THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.resync of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/pulse_sync.vhd":45:1:45:2|Removing sequential instance THE_APV_TRGCTRL.THE_APV_SYNC_HANDLER.THE_APVTRGDONE_SYNC.sync_q of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/pulse_sync.vhd":45:1:45:2|Boundary register THE_APV_TRGCTRL.THE_APV_SYNC_HANDLER.THE_APVTRGDONE_SYNC.sync_q has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/pulse_sync.vhd":45:1:45:2|Removing sequential instance THE_APV_TRGCTRL.THE_APV_SYNC_HANDLER.THE_APVTRGDONE_SYNC.sync_qqq of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/pulse_sync.vhd":33:1:33:2|Removing sequential instance THE_APV_TRGCTRL.THE_APV_SYNC_HANDLER.THE_APVTRGDONE_SYNC.toggle_ff of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/pulse_sync.vhd":33:1:33:2|Boundary register THE_APV_TRGCTRL.THE_APV_SYNC_HANDLER.THE_APVTRGDONE_SYNC.toggle_ff has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/pulse_sync.vhd":45:1:45:2|Removing sequential instance THE_APV_TRGCTRL.THE_APV_SYNC_HANDLER.THE_APVTRGDONE_SYNC.sync_qq of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/pulse_sync.vhd":59:1:59:2|Removing sequential instance THE_APV_TRGCTRL.THE_APV_SYNC_HANDLER.THE_APVTRGDONE_SYNC.pulse_b of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_sync_handler.vhd":62:1:62:2|Removing sequential instance THE_APV_TRGCTRL.THE_APV_SYNC_HANDLER.apv_done of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+Finished factoring (Time elapsed 0h:00m:34s; Memory used current: 250MB peak: 250MB)
+
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd":968:4:968:5|Removing sequential instance THE_RICH_TRB.THE_MEDIA_INTERFACE.send_reset_words of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":218:4:218:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.MUX_SBUF.gen_version_0\.sbuf.current_got_overflow of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":235:4:235:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.MUX_SBUF.gen_version_0\.sbuf.current_b1_buffer[17] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":245:4:245:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.MUX_SBUF.gen_version_0\.sbuf.current_b2_buffer[17] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_onewire.vhd":69:6:69:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.gen_1wire\.onewire_interface.MONITOR_OUT of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_onewire.vhd":339:6:339:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.gen_1wire\.onewire_interface.buf_STAT of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":978:6:978:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.STAT_REG_STROBE[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":978:6:978:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.STAT_REG_STROBE[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":978:6:978:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.COMMON_STAT_REG_STROBE[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":978:6:978:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.COMMON_STAT_REG_STROBE[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":978:6:978:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.next_COMMON_CTRL_REG_STROBE[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":978:6:978:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.next_COMMON_CTRL_REG_STROBE[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":978:6:978:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.next_CTRL_REG_STROBE[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":978:6:978:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.next_CTRL_REG_STROBE[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":978:6:978:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.STAT_REG_STROBE[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":978:6:978:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.STAT_REG_STROBE[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":978:6:978:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.COMMON_CTRL_REG_STROBE[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":978:6:978:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.COMMON_CTRL_REG_STROBE[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":978:6:978:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.CTRL_REG_STROBE[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":978:6:978:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.CTRL_REG_STROBE[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":747:6:747:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.buf_API_PACKET_NUM_OUT[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":95:6:95:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_ipu_apl\.the_ipudata_apl.buf_INFORMATION[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":95:6:95:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_ipu_apl\.the_ipudata_apl.buf_INFORMATION[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":95:6:95:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_ipu_apl\.the_ipudata_apl.buf_INFORMATION[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":95:6:95:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_ipu_apl\.the_ipudata_apl.buf_INFORMATION[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":95:6:95:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_ipu_apl\.the_ipudata_apl.buf_INFORMATION[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":95:6:95:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_ipu_apl\.the_ipudata_apl.buf_INFORMATION[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":95:6:95:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_ipu_apl\.the_ipudata_apl.buf_INFORMATION[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ipudata.vhd":95:6:95:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_ipu_apl\.the_ipudata_apl.buf_INFORMATION[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[23] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[22] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[21] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[20] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[19] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[18] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[17] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[16] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[15] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[14] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[13] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[12] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[11] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[6] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[5] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[4] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[3] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[2] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_trigger.vhd":224:8:224:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.gentrgapi\.the_trigger_apl.reg_TRG_INFORMATION_OUT[1] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":883:6:883:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.slave_running of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":859:6:859:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.buf_APL_RUN_OUT of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":218:4:218:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.SBUF_TO_APL2.current_got_overflow of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":218:4:218:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.SBUF_TO_APL.gen_version_0\.sbuf.current_got_overflow of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":218:4:218:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.SBUF.gen_version_0\.sbuf.current_got_overflow of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":235:4:235:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.SBUF.gen_version_0\.sbuf.current_b1_buffer[17] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":235:4:235:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.SBUF.gen_version_0\.sbuf.current_b1_buffer[16] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":245:4:245:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.SBUF.gen_version_0\.sbuf.current_b2_buffer[17] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":245:4:245:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.SBUF.gen_version_0\.sbuf.current_b2_buffer[16] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":218:4:218:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.SBUF_TO_APL2.current_got_overflow of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":218:4:218:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.SBUF_TO_APL.gen_version_0\.sbuf.current_got_overflow of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":218:4:218:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.SBUF.gen_version_0\.sbuf.current_got_overflow of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":235:4:235:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.SBUF.gen_version_0\.sbuf.current_b1_buffer[17] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":235:4:235:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.SBUF.gen_version_0\.sbuf.current_b1_buffer[16] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":245:4:245:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.SBUF.gen_version_0\.sbuf.current_b2_buffer[17] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":245:4:245:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.SBUF.gen_version_0\.sbuf.current_b2_buffer[16] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[15] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[14] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[13] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[12] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[11] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[10] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[9] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[8] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[7] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[6] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[5] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[4] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[3] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[2] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[1] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[0] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[31] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[30] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[29] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[28] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[27] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[26] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[25] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[24] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[23] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[22] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[21] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[20] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[19] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[18] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[17] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[16] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[15] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[14] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[13] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[12] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[8] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[7] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[6] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[5] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[4] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[3] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[2] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[1] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[0] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":194:4:194:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.current_rec_buffer_size_out[3] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":194:4:194:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.reg_ack_init_internal of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":218:4:218:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.genREPLYOBUF1\.REPLYOBUF.THE_SBUF.gen_version_0\.sbuf.current_got_overflow of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":218:4:218:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.gen_init_sbuf\.SBUF_INIT.gen_version_0\.sbuf.current_got_overflow of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[15] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[14] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[13] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[12] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[11] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[10] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[9] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[8] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[7] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[6] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[5] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[4] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[3] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[2] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[1] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[0] of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[31] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[30] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[29] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[28] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[27] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[26] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[25] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[24] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[23] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[22] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[21] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[20] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[19] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[18] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[17] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[16] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[15] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[14] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[13] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[12] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[8] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[7] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[6] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[5] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[4] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[3] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[2] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[1] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[0] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":194:4:194:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.current_rec_buffer_size_out[3] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":194:4:194:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.reg_ack_init_internal of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":218:4:218:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.genREPLYOBUF1\.REPLYOBUF.THE_SBUF.gen_version_0\.sbuf.current_got_overflow of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":218:4:218:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.gen_init_sbuf\.SBUF_INIT.gen_version_0\.sbuf.current_got_overflow of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":447:8:447:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.init_buffer_number[15:0] of view:PrimLib.counter(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":466:6:466:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.data_counter[31:0] of view:PrimLib.counter(prim) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":194:4:194:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.current_rec_buffer_size_out[3] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_ibuf.vhd":194:4:194:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.reg_ack_init_internal of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":218:4:218:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.IOBUF.genREPLYOBUF1\.REPLYOBUF.THE_SBUF.gen_version_0\.sbuf.current_got_overflow of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_iobuf.vhd":202:6:202:13|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.IOBUF.genINITOBUF2\.gen_INITOBUF3\.INITOBUF.buf_MED_PACKET_NUM_OUT[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net_sbuf.vhd":218:4:218:5|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.gen_init_sbuf\.SBUF_INIT.gen_version_0\.sbuf.current_got_overflow of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd":135:2:135:3|Removing sequential instance THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.med_error[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd":135:2:135:3|Removing sequential instance THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.med_error[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.12\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.12\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.12\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.12\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.12\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.12\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.11\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.11\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.11\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.11\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.11\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.11\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.13\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.13\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.13\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.13\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC1\.13\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC1\.13\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":109:4:109:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_11 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":116:4:116:8|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_10 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/frame_status_mem.vhd":123:4:123:7|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM.FF_9 of view:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_LOCKER.THE_APV_LOCK_SM.noapv of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_LOCKER.THE_APV_LOCK_SM.nosync of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown of view:UNILIB.FDS(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_LOCKER.THE_APV_LOCK_SM.unknown has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Removing sequential instance THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_lock_sm.vhd":104:1:104:2|Boundary register THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_LOCKER.THE_APV_LOCK_SM.lost has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":369:1:369:2|Removing sequential instance THE_PED_CORR_STAGE.do_start of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/state_sync.vhd":27:1:27:2|Removing instance THE_APV_TRGCTRL.THE_RESET_SYNC.sync[0], because it is equivalent to instance THE_SLAVE_BUS.THE_ADC1_SNOOPER.THE_RESET_SYNC.sync[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/state_sync.vhd":27:1:27:2|Removing instance THE_SLAVE_BUS.THE_ADC0_SNOOPER.THE_RESET_SYNC.sync[1], because it is equivalent to instance THE_APV_TRGCTRL.THE_RESET_SYNC.sync[1]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":125:8:125:9|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.IOBUF.genREPLYOBUF1.REPLYOBUF.int_data_in_i[14], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.IOBUF.genREPLYOBUF1.REPLYOBUF.int_data_in_i[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":125:8:125:9|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.IOBUF.genREPLYOBUF1.REPLYOBUF.int_data_in_i[13], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.IOBUF.genREPLYOBUF1.REPLYOBUF.int_data_in_i[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":125:8:125:9|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.IOBUF.genREPLYOBUF1.REPLYOBUF.int_data_in_i[12], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.IOBUF.genREPLYOBUF1.REPLYOBUF.int_data_in_i[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":125:8:125:9|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.IOBUF.genREPLYOBUF1.REPLYOBUF.int_data_in_i[3], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.IOBUF.genREPLYOBUF1.REPLYOBUF.int_data_in_i[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":125:8:125:9|Removing instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.IOBUF.genREPLYOBUF1.REPLYOBUF.int_data_in_i[2], because it is equivalent to instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers.0.geniobuf.IOBUF.genREPLYOBUF1.REPLYOBUF.int_data_in_i[15]
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_dpram.vhd":140:4:140:26|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_ONEWIRE_MEMORY.THE_SLV_ONEWIRE_DPRAM.slv_onewire_dpram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_dpram.vhd":140:4:140:26|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_ONEWIRE_MEMORY.THE_SLV_ONEWIRE_DPRAM.slv_onewire_dpram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_ADC1_SNOOPER.THE_ADC0_SNOOP_MEM.adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_ADC1_SNOOPER.THE_ADC0_SNOOP_MEM.adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_ADC0_SNOOPER.THE_ADC0_SNOOP_MEM.adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_snoop_mem.vhd":140:4:140:22|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_ADC0_SNOOPER.THE_ADC0_SNOOP_MEM.adc_snoop_mem_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":150:4:150:26|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_SPI_MEMORY.THE_BUS_SPI_DPRAM.spi_dpram_32_to_8_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":150:4:150:26|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_SPI_MEMORY.THE_BUS_SPI_DPRAM.spi_dpram_32_to_8_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":198:4:198:26|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_SPI_MEMORY.THE_BUS_SPI_DPRAM.spi_dpram_32_to_8_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd":198:4:198:26|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_SPI_MEMORY.THE_BUS_SPI_DPRAM.spi_dpram_32_to_8_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.13\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.13\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.9\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.9\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.15\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.15\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.14\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.14\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.4\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.4\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.8\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.8\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.12\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.12\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.7\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.7\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.11\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.11\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.5\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.5\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.6\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.6\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.10\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.10\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.1\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.1\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.0\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.0\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.2\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.2\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.3\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.3\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.13\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.13\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.9\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.9\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.15\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.15\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.14\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.14\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.4\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.4\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.8\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.8\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.12\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.12\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.7\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.7\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.11\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.11\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.5\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.5\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.6\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.6\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.10\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.10\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.1\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.1\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.0\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.0\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.2\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.2\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_a of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.3\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_thr_true.vhd":144:4:144:21|Expect property csdecode_b of instance THE_SLAVE_BUS.THE_PED_MEM.GEN_PED_MEM\.3\.THE_PED_MEM.ped_thr_true_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.GEN_FIFO_TO_INT\.FIFO_TO_INT.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.GEN_FIFO_TO_APL\.FIFO_TO_APL.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_a of instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd":417:4:417:16|Expect property csdecode_b of instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.IOBUF.GEN_IBUF\.THE_IBUF.THE_FIFO.fifo.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_a of instance THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_FPGA_TO_SFP.FIFO_DP_BRAM.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_b of instance THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_FPGA_TO_SFP.FIFO_DP_BRAM.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_a of instance THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_SFP_TO_FPGA.FIFO_DP_BRAM.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd":828:4:828:16|Expect property csdecode_b of instance THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_SFP_TO_FPGA.FIFO_DP_BRAM.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.11\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.12\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.13\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":149:4:149:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_0_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_a of instance THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/input_bram.vhd":194:4:194:19|Expect property csdecode_b of instance THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_RAW_BUFFER.THE_INPUT_BRAM.input_bram_0_1_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_1kx18.vhd":418:4:418:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_LFIFO.pdp_ram_0_0_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.5\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.2\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.11\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.8\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.3\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.7\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.4\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.14\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.9\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.13\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.12\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":417:4:417:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_0_2 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":458:4:458:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_1_1 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_a of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@W: BN283 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":500:4:500:16|Expect property csdecode_b of instance THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.pdp_ram_0_2_0 to be binary, but 0b000 is seen.
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":944:6:944:7|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.1\.geniobuf\.gen_api\.DAT_PASSIVE_API.registered_trailer_F1[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":125:8:125:9|Removing sequential instance THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.0\.geniobuf\.IOBUF.genREPLYOBUF1\.REPLYOBUF.int_data_in_i[15] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
+
+
+#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[
+
+======================================================================================
+ Instance:Pin Generated Clock Optimization Status
+======================================================================================
+THE_ADC0_CROSSOVER.THE_RESET_STATE_SYNC.sync[0]:C Not Done
+THE_IPU_STAGE.GEN_FIFO.5.THE_SMALL_SYNCER.dfifo_available[5]:C Not Done
+ test_reg40m:C Not Done
+
+
+##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]
+
+Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:40s; Memory used current: 241MB peak: 259MB)
+
+
+Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:48s; Memory used current: 221MB peak: 259MB)
+
+Starting Early Timing Optimization (Time elapsed 0h:01m:03s; Memory used current: 228MB peak: 259MB)
+
+Finished Early Timing Optimization (Time elapsed 0h:01m:39s; Memory used current: 230MB peak: 259MB)
+
+Finished generic timing optimizations - Pass 2 (Time elapsed 0h:01m:42s; Memory used current: 225MB peak: 259MB)
+
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":369:1:369:2|Removing instance THE_PED_CORR_STAGE.eds_done, because it is equivalent to instance THE_PED_CORR_STAGE.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.11.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.11.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":350:1:350:2|Removing instance THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.ce_frmctr, because it is equivalent to instance THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.CURRENT_STATE[13]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_slim.vhd":225:4:225:5|Removing instance THE_SLAVE_BUS.THE_SPI_MASTER.THE_SPI_SLIM.rst_addr, because it is equivalent to instance THE_SLAVE_BUS.THE_SPI_MASTER.THE_SPI_SLIM.STATE[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":75:1:75:2|Removing instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_0.apv_trgcnt, because it is equivalent to instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_0.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":75:1:75:2|Removing instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_1.apv_trgcnt, because it is equivalent to instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_1.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":75:1:75:2|Removing instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_2.apv_trgcnt, because it is equivalent to instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_2.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":75:1:75:2|Removing instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_3.apv_trgcnt, because it is equivalent to instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_3.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":350:1:350:2|Removing instance THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.apv_trgstart, because it is equivalent to instance THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.CURRENT_STATE[14]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":350:1:350:2|Removing instance THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.ce_evtctr, because it is equivalent to instance THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":350:1:350:2|Removing instance THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.eds_we, because it is equivalent to instance THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_sendb.vhd":159:1:159:2|Removing instance THE_SLAVE_BUS.THE_I2C_MASTER.THE_I2C_SLIM.THE_I2C_SENDB.inc_bit, because it is equivalent to instance THE_SLAVE_BUS.THE_I2C_MASTER.THE_I2C_SLIM.THE_I2C_SENDB.CURRENT_STATE[5]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_memory.vhd":111:1:111:2|Removing instance THE_SLAVE_BUS.THE_ONEWIRE_MEMORY.slv_busy, because it is equivalent to instance THE_SLAVE_BUS.THE_ONEWIRE_MEMORY.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_slim.vhd":116:1:116:2|Removing instance THE_SLAVE_BUS.THE_I2C_MASTER.THE_I2C_SLIM.start, because it is equivalent to instance THE_SLAVE_BUS.THE_I2C_MASTER.THE_I2C_SLIM.CURRENT_STATE[16]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.0.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.0.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.0.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.0.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.0.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.0.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.2.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.2.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.2.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.2.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.2.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.2.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.6.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.6.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.6.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.6.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.6.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.6.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.15.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.15.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.15.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.15.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.15.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.15.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.12.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.12.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.12.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.12.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.12.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.12.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.14.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.14.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.14.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.14.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.14.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.14.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.9.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.9.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.9.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.9.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.9.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.9.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.8.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.8.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.8.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.8.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.8.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.8.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.3.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.3.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.3.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.3.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.3.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.3.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.7.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.7.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.7.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.7.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.7.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.7.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.10.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.10.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.10.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.10.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.10.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.10.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.1.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.1.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.1.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.1.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.1.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.1.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.13.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.13.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.13.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.13.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.13.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.13.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.5.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.5.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.5.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.5.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.5.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.5.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.4.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.4.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.4.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.4.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.4.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.4.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.11.THE_BUF_TOC.ready, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.11.THE_BUF_TOC.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.11.THE_BUF_TOC.toc_rst, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.11.THE_BUF_TOC.CURRENT_STATE[6]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.11.THE_BUF_TOC.baddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.11.THE_BUF_TOC.CURRENT_STATE[2]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":369:1:369:2|Removing instance THE_PED_CORR_STAGE.eds_wr, because it is equivalent to instance THE_PED_CORR_STAGE.CURRENT_STATE[8]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.0.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.0.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.0.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.0.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.2.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.2.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.2.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.2.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.6.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.6.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.6.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.6.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.15.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.15.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.15.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.15.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.12.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.12.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.12.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.12.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.14.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.14.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.14.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.14.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.9.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.9.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.9.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.9.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.8.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.8.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.8.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.8.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.3.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.3.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.3.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.3.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.7.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.7.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.7.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.7.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.10.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.10.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.10.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.10.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.1.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.1.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.1.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.1.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.13.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.13.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.13.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.13.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.5.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.5.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.5.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.5.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.4.THE_BUF_TOC.gooddata, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.4.THE_BUF_TOC.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.4.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.4.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/buf_toc.vhd":112:1:112:2|Removing instance THE_PED_CORR_STAGE.GEN_TOC.11.THE_BUF_TOC.stat_clr, because it is equivalent to instance THE_PED_CORR_STAGE.GEN_TOC.11.THE_BUF_TOC.CURRENT_STATE[7]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":350:1:350:2|Removing instance THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.eds_start, because it is equivalent to instance THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.CURRENT_STATE[15]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/real_trg_handler.vhd":350:1:350:2|Removing instance THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.missed_trg, because it is equivalent to instance THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.CURRENT_STATE[1]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":110:2:110:3|Removing instance THE_SLAVE_BUS.THE_SPI_MASTER.store_wr, because it is equivalent to instance THE_SLAVE_BUS.THE_SPI_MASTER.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_master.vhd":110:2:110:3|Removing instance THE_SLAVE_BUS.THE_SPI_MASTER.store_rd, because it is equivalent to instance THE_SLAVE_BUS.THE_SPI_MASTER.CURRENT_STATE[4]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_onewire_memory.vhd":111:1:111:2|Removing instance THE_SLAVE_BUS.THE_ONEWIRE_MEMORY.store_wr, because it is equivalent to instance THE_SLAVE_BUS.THE_ONEWIRE_MEMORY.CURRENT_STATE[4]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":96:1:96:2|Removing instance THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.store_rd, because it is equivalent to instance THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.CURRENT_STATE[4]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":96:1:96:2|Removing instance THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.store_wr, because it is equivalent to instance THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":96:1:96:2|Removing instance THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.store_rd, because it is equivalent to instance THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.CURRENT_STATE[4]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":96:1:96:2|Removing instance THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.store_wr, because it is equivalent to instance THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":95:1:95:2|Removing instance THE_SLAVE_BUS.THE_I2C_MASTER.store_rd, because it is equivalent to instance THE_SLAVE_BUS.THE_I2C_MASTER.CURRENT_STATE[4]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_master.vhd":95:1:95:2|Removing instance THE_SLAVE_BUS.THE_I2C_MASTER.store_wr, because it is equivalent to instance THE_SLAVE_BUS.THE_I2C_MASTER.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/trbnet/special/spi_databus_memory.vhd":61:6:61:7|Removing instance THE_SLAVE_BUS.THE_SPI_MEMORY.store_wr, because it is equivalent to instance THE_SLAVE_BUS.THE_SPI_MEMORY.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":75:1:75:2|Removing instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_0.apv_done, because it is equivalent to instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_0.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":75:1:75:2|Removing instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_1.apv_done, because it is equivalent to instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_1.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":75:1:75:2|Removing instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_2.apv_done, because it is equivalent to instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_2.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":75:1:75:2|Removing instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_3.apv_done, because it is equivalent to instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_3.CURRENT_STATE[0]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/i2c_sendb.vhd":159:1:159:2|Removing instance THE_SLAVE_BUS.THE_I2C_MASTER.THE_I2C_SLIM.THE_I2C_SENDB.s_scl, because it is equivalent to instance THE_SLAVE_BUS.THE_I2C_MASTER.THE_I2C_SLIM.THE_I2C_SENDB.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":369:1:369:2|Removing instance THE_PED_CORR_STAGE.ld_frm_ctr, because it is equivalent to instance THE_PED_CORR_STAGE.CURRENT_STATE[28]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":75:1:75:2|Removing instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_3.apv_trg, because it is equivalent to instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_3.CURRENT_STATE[4]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":75:1:75:2|Removing instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_2.apv_trg, because it is equivalent to instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_2.CURRENT_STATE[4]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":75:1:75:2|Removing instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_1.apv_trg, because it is equivalent to instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_1.CURRENT_STATE[4]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_trg_handler.vhd":75:1:75:2|Removing instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_0.apv_trg, because it is equivalent to instance THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_0.CURRENT_STATE[4]
+Finished preparing to map (Time elapsed 0h:02m:01s; Memory used current: 232MB peak: 259MB)
+
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_ped_thr_mem.vhd":132:1:132:2|Removing instance THE_SLAVE_BUS.THE_PED_MEM.store_wr, because it is equivalent to instance THE_SLAVE_BUS.THE_PED_MEM.CURRENT_STATE[5]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_ped_thr_mem.vhd":132:1:132:2|Removing instance THE_SLAVE_BUS.THE_THR_MEM.store_wr, because it is equivalent to instance THE_SLAVE_BUS.THE_THR_MEM.CURRENT_STATE[5]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":148:1:148:2|Removing instance THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.store_wr, because it is equivalent to instance THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.CURRENT_STATE[5]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":65:1:65:2|Removing instance THE_SLAVE_BUS.THE_TRG_CTRL_REG.store_wr, because it is equivalent to instance THE_SLAVE_BUS.THE_TRG_CTRL_REG.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":60:1:60:2|Removing instance THE_SLAVE_BUS.THE_PLL_CTRL_REG.store_wr, because it is equivalent to instance THE_SLAVE_BUS.THE_PLL_CTRL_REG.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":65:1:65:2|Removing instance THE_SLAVE_BUS.THE_GOOD_TEST_REG.store_wr, because it is equivalent to instance THE_SLAVE_BUS.THE_GOOD_TEST_REG.CURRENT_STATE[3]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":70:1:70:2|Removing instance THE_SLAVE_BUS.THE_ADC1_SNOOPER.store_wr, because it is equivalent to instance THE_SLAVE_BUS.THE_ADC1_SNOOPER.CURRENT_STATE[5]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":70:1:70:2|Removing instance THE_SLAVE_BUS.THE_ADC0_SNOOPER.store_wr, because it is equivalent to instance THE_SLAVE_BUS.THE_ADC0_SNOOPER.CURRENT_STATE[5]
+@W: BN132 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":65:1:65:2|Removing instance THE_SLAVE_BUS.THE_ADC_LVL_REG.store_wr, because it is equivalent to instance THE_SLAVE_BUS.THE_ADC_LVL_REG.CURRENT_STATE[3]
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":122:2:122:19|Removing sequential instance THE_SLAVE_BUS.THE_GOOD_TEST_REG.CURRENT_STATE[6] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":128:2:128:19|Removing sequential instance THE_SLAVE_BUS.THE_GOOD_TEST_REG.CURRENT_STATE[5] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":122:2:122:19|Removing sequential instance THE_SLAVE_BUS.THE_TRG_CTRL_REG.CURRENT_STATE[6] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":128:2:128:19|Removing sequential instance THE_SLAVE_BUS.THE_TRG_CTRL_REG.CURRENT_STATE[5] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":122:2:122:19|Removing sequential instance THE_SLAVE_BUS.THE_ADC_LVL_REG.CURRENT_STATE[6] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":128:2:128:19|Removing sequential instance THE_SLAVE_BUS.THE_ADC_LVL_REG.CURRENT_STATE[5] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":65:1:65:2|Removing sequential instance THE_SLAVE_BUS.THE_GOOD_TEST_REG.slv_busy of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":65:1:65:2|Removing sequential instance THE_SLAVE_BUS.THE_TRG_CTRL_REG.slv_busy of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+@N: BN116 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":65:1:65:2|Removing sequential instance THE_SLAVE_BUS.THE_ADC_LVL_REG.slv_busy of view:UNILIB.FDR(PRIM) because there are no references to its outputs
+Finished technology mapping (Time elapsed 0h:02m:13s; Memory used current: 286MB peak: 296MB)
+
+Pass CPU time Worst Slack Luts / Registers
+------------------------------------------------------------
+Pass CPU time Worst Slack Luts / Registers
+------------------------------------------------------------
+ 1 0h:02m:19s -0.27ns 9810 / 12669
+ 2 0h:02m:21s -0.27ns 9810 / 12669
+------------------------------------------------------------
+
+Timing driven replication report
+@N: FX271 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/reset_handler.vhd":86:1:86:2|Instance "THE_RESET_HANDLER.final_reset[1]" with 3044 loads has been replicated 1 time(s) to improve timing
+@N: FX271 :|Instance "THE_IPU_STAGE.reset_all_li_i" with 1335 loads has been replicated 1 time(s) to improve timing
+@N: FX271 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/reset_handler.vhd":86:1:86:2|Instance "THE_RESET_HANDLER.final_reset[1]" with 417 loads has been replicated 3 time(s) to improve timing
+Added 4 Registers via timing driven replication
+Added 1 LUTs via timing driven replication
+
+Pass CPU time Worst Slack Luts / Registers
+------------------------------------------------------------
+------------------------------------------------------------
+
+Net buffering Report for view:work.adcmv3(adcmv3):
+@N: FX103 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/state_sync.vhd":27:1:27:2|Instance "THE_RAW_BUF_STAGE.THE_RESET_SYNC.sync[1]" with "321" loads has been replicated "4" time(s) due to a soft fanout limit of "100"
+@N: FX103 :|Instance "THE_SLAVE_BUS.THE_ONEWIRE_MEMORY.THE_ONEWIRE_MASTER.THE_DATA_SAVE_PROC\.ram_addr_7_0_311_i_i_0_o3" with "276" loads has been replicated "2" time(s) due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_obuf.vhd":455:19:455:91|Instance "THE_RICH_TRB.THE_UNIFIED_ENDPOINT.reset_no_link_i_i" with "105" loads has been replicated "2" time(s) due to a soft fanout limit of "100"
+@N: FX104 |Net "THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.adc_addr[3]" with "240" loads has been buffered by "4" buffers due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":287:3:297:43|Instance "THE_PED_CORR_STAGE.GEN_ALU\.1\.THE_ALU.un3_next_data_we_i_o2_0_i_i2_0_o2_i_o2" with "129" loads has been replicated "1" time(s) due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":255:2:255:3|Instance "THE_PED_CORR_STAGE.GEN_ALU\.12\.THE_ALU.nc_corr_data_qqq_15_i_a2_2[6]" with "128" loads has been replicated "1" time(s) due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/onewire_master.vhd":439:1:439:2|Instance "THE_SLAVE_BUS.THE_ONEWIRE_MEMORY.THE_ONEWIRE_MASTER.N_5_i" with "272" loads has been replicated "2" time(s) due to a soft fanout limit of "100"
+@N: FX104 |Net "THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.adc_addr[2]" with "123" loads has been buffered by "3" buffers due to a soft fanout limit of "100"
+@N: FX104 |Net "THE_SLAVE_BUS.un1_THE_THR_MEM[19]" with "159" loads has been buffered by "3" buffers due to a soft fanout limit of "100"
+@N: FX104 |Net "THE_SLAVE_BUS.un1_THE_PED_MEM[19]" with "159" loads has been buffered by "3" buffers due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/raw_buf_stage.vhd":162:1:162:2|Instance "THE_RAW_BUF_STAGE.reset" with "360" loads has been replicated "4" time(s) due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ipu_fifo_stage.vhd":197:1:197:2|Instance "THE_IPU_STAGE.ld_todo" with "405" loads has been replicated "4" time(s) due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regio_bus_handler.vhd":90:6:90:7|Instance "THE_SLAVE_BUS.THE_BUS_HANDLER.port_select_int[2]" with "258" loads has been replicated "2" time(s) due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regIO.vhd":668:6:668:7|Instance "THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_regio\.regIO.address[0]" with "210" loads has been replicated "2" time(s) due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_sync_handler.vhd":62:1:62:2|Instance "THE_APV_TRGCTRL.THE_APV_SYNC_HANDLER.apv_sync" with "193" loads has been replicated "2" time(s) due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regio_bus_handler.vhd":90:6:90:7|Instance "THE_SLAVE_BUS.THE_BUS_HANDLER.buf_BUS_ADDR_OUT[3]" with "188" loads has been replicated "1" time(s) due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":369:1:369:2|Instance "THE_PED_CORR_STAGE.do_hdr" with "176" loads has been replicated "1" time(s) due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":369:1:369:2|Instance "THE_PED_CORR_STAGE.do_error" with "161" loads has been replicated "1" time(s) due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regio_bus_handler.vhd":90:6:90:7|Instance "THE_SLAVE_BUS.THE_BUS_HANDLER.port_select_int[1]" with "141" loads has been replicated "1" time(s) due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/onewire_master.vhd":478:1:478:2|Instance "THE_SLAVE_BUS.THE_ONEWIRE_MEMORY.THE_ONEWIRE_MASTER.ext_ram_addr[3]" with "132" loads has been replicated "1" time(s) due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":369:1:369:2|Instance "THE_PED_CORR_STAGE.buf_done" with "128" loads has been replicated "1" time(s) due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_regio_bus_handler.vhd":90:6:90:7|Instance "THE_SLAVE_BUS.THE_BUS_HANDLER.buf_BUS_ADDR_OUT[2]" with "116" loads has been replicated "1" time(s) due to a soft fanout limit of "100"
+@N: FX104 |Net "THE_ADC0_CROSSOVER.THE_CROSSOVER.rden_i" with "113" loads has been buffered by "2" buffers due to a soft fanout limit of "100"
+@N: FX104 |Net "THE_ADC1_CROSSOVER.THE_CROSSOVER.rden_i" with "113" loads has been buffered by "2" buffers due to a soft fanout limit of "100"
+@N: FX104 |Net "THE_ADC1_CROSSOVER.THE_CROSSOVER.rRst" with "127" loads has been buffered by "2" buffers due to a soft fanout limit of "100"
+@N: FX103 :|Instance "THE_IPU_STAGE.reset_all_li_i" with "1280" loads has been replicated "12" time(s) due to a soft fanout limit of "100"
+@N: FX104 |Net "THE_ADC0_CROSSOVER.THE_CROSSOVER.rRst" with "127" loads has been buffered by "2" buffers due to a soft fanout limit of "100"
+@N: FX103 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/reset_handler.vhd":86:1:86:2|Instance "THE_RESET_HANDLER.final_reset[1]" with "270" loads has been replicated "2" time(s) due to a soft fanout limit of "100"
+Added 17 Buffers
+Added 27 Registers via replication
+Added 31 LUTs via replication
+
+Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:02m:34s; Memory used current: 287MB peak: 296MB)
+
+@N: FX623 |Packing into LUT62
+@W: MO161 :"/home/mboehmer/VHDL_Pro/trbnet/trb_net16_api_base.vhd":961:6:961:7|Register bit THE_RICH_TRB.THE_UNIFIED_ENDPOINT.genbuffers\.3\.geniobuf\.gen_api\.DAT_PASSIVE_API.registered_header_F2[15] is always 1, optimizing ...
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_pc_nc_alu.vhd":151:1:151:2|Generating RAM THE_PED_CORR_STAGE.GEN_ALU\.14\.THE_ALU.frame_int_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC1\.13\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC1\.11\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC1\.12\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/apv_locker.vhd":299:1:299:2|Generating RAM THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_LOCKER.delay_store_CR0[0:0]
+@N: FO126 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/ped_corr_ctrl.vhd":653:1:653:2|Generating RAM THE_PED_CORR_STAGE.thr_addr_CR6[6:0]
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.wr_ctr_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.wr_ctr_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.wr_ctr_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.wr_ctr_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.wr_ctr_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.wr_ctr_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.wr_ctr_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.wr_ctr_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.wr_ctr_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.wr_ctr_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.wr_ctr_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.wr_ctr_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.wr_ctr_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.wr_ctr_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.wr_ctr_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.wr_ctr_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.wr_ctr_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.wr_ctr_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.wr_ctr_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":158:1:158:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.wr_ctr_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.ctrl_reg_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.ctrl_reg_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.ctrl_reg_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.ctrl_reg_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.ctrl_reg_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_25_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_24_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_23_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_22_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_21_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_20_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_19_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_18_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_17_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_16_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC1_SNOOPER.status_reg_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.ctrl_reg_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.ctrl_reg_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.ctrl_reg_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.ctrl_reg_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":186:1:186:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.ctrl_reg_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_25_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_24_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_23_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_22_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_21_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_20_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_19_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_18_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_17_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_16_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_adc_snoop.vhd":198:1:198:2|Boundary register THE_SLAVE_BUS.THE_ADC0_SNOOPER.status_reg_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_31_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_30_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_29_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_28_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_27_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_26_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_25_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_24_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_22_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_21_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_20_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_18_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_17_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_16_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_half_register.vhd":133:1:133:2|Boundary register THE_SLAVE_BUS.THE_PLL_CTRL_REG.reg_slv_data_out_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_31_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_30_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_29_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_28_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_27_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_26_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_25_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_24_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_23_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_22_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_21_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_20_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_19_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_18_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_17_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_16_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_TRG_CTRL_REG.reg_slv_data_in_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_31_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_30_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_29_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_28_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_27_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_26_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_25_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_24_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_23_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_22_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_21_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_20_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_19_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_18_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_17_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_16_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register.vhd":147:1:147:2|Boundary register THE_SLAVE_BUS.THE_ADC_LVL_REG.reg_slv_data_in_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_0_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_1_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_2_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_3_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_4_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_5_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_6_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_7_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_8_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_9_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_10_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_11_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_12_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_13_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_14_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/slv_register_bank.vhd":214:2:214:3|Boundary register THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.ctrl_reg_15_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.reg_slv_data_out_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.reg_slv_data_out_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.reg_slv_data_out_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.reg_slv_data_out_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.reg_slv_data_out_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.reg_slv_data_out_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.reg_slv_data_out_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.reg_slv_data_out_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.reg_slv_data_out_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.adc_ctrl_data_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.adc_ctrl_data_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.adc_ctrl_data_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.adc_ctrl_data_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.adc_ctrl_data_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.adc_ctrl_data_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.adc_ctrl_data_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.adc_ctrl_data_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.reg_slv_data_out_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.reg_slv_data_out_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.reg_slv_data_out_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.reg_slv_data_out_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.reg_slv_data_out_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.reg_slv_data_out_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.reg_slv_data_out_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.reg_slv_data_out_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":196:1:196:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.reg_slv_data_out_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.adc_ctrl_data_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.adc_ctrl_data_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.adc_ctrl_data_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.adc_ctrl_data_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.adc_ctrl_data_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.adc_ctrl_data_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.adc_ctrl_data_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+@A: BN291 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/spi_adc_master.vhd":178:1:178:2|Boundary register THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.adc_ctrl_data_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
+Replicating THE_RAW_BUF_STAGE.THE_RESET_SYNC.sync_1[1], loads=113, segments=16
+Replicating THE_PED_CORR_STAGE.GEN_ALU\.1\.THE_ALU.N_4294_i, loads=208, segments=16
+Replicating THE_PED_CORR_STAGE.N_4286_i, loads=205, segments=22
+Replicating THE_PED_CORR_STAGE.GEN_ALU\.1\.THE_ALU.N_4295_i, loads=192, segments=16
+Replicating THE_IPU_STAGE.N_2035_i, loads=160, segments=16
+Replicating THE_RICH_TRB.THE_UNIFIED_ENDPOINT.reset_no_link_i_i, loads=233, segments=27
+Replicating THE_PED_CORR_STAGE.do_error, loads=318, segments=44
+Replicating THE_PED_CORR_STAGE.do_hdr, loads=325, segments=45
+Replicating THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_LOCKER.THE_APV_LOCK_SM.CURRENT_STATE_srsts_i_i_o2[12], loads=176, segments=25
+Replicating THE_ADC1_HANDLER.THE_RESET_SYNC.sync[1], loads=114, segments=19
+Replicating THE_ADC0_HANDLER.THE_RESET_SYNC.sync[1], loads=114, segments=19
+Replicating THE_APV_TRGCTRL.THE_RESET_SYNC.sync[1], loads=118, segments=15
+Replicating THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.reset_me, loads=153, segments=17
+Replicating THE_PED_CORR_STAGE.buf_done, loads=112, segments=15
+@W: MT420 |Found inferred clock adcmv3|CLK100M with period 10.00ns. A user-defined clock should be declared on object "p:CLK100M"
+
+@W: MT420 |Found inferred clock adcmv3|ADC0_LCLK with period 10.00ns. A user-defined clock should be declared on object "p:ADC0_LCLK"
+
+@W: MT420 |Found inferred clock adcmv3|ADC1_LCLK with period 10.00ns. A user-defined clock should be declared on object "p:ADC1_LCLK"
+
+@W: MT420 |Found inferred clock pll_40m|CLKOP_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:THE_40M_PLL.CLKOP"
+
+@W: MT420 |Found inferred clock dll_100m|clkop_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:THE_100M_DLL.clkop"
+
+@W: MT420 |Found inferred clock sync_pll_40m|CLKOP_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:THE_SYNC_PLL.CLKOP"
+
+@W: MT246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/pll_40m.vhd":109:4:109:13|Blackbox EPLLD is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/dll_100m.vhd":96:4:96:15|Blackbox CIDDLLA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":839:4:839:10|Blackbox ALEB2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/fifo_2kx27.vhd":873:4:873:10|Blackbox AGEB2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_ch_in.vhd":57:4:57:7|Blackbox IDDRFXA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adc_ch_in.vhd":61:4:61:9|Blackbox DELAYB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT246 :"/home/mboehmer/VHDL_Pro/comp_adcmv3/design/adcmv3.vhd":1207:0:1207:14|Blackbox ODDRXC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT246 :"/home/mboehmer/VHDL_Pro/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd":1760:0:1760:8|Blackbox PCSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Mon Jun 14 22:11:24 2010
+#
+
+
+Top view: adcmv3
+Requested Frequency: 100.0 MHz
+Wire load mode: top
+Paths requested: 5
+Constraint File(s):
+@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
+
+@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 1.396
+
+ Requested Estimated Requested Estimated Clock Clock
+Starting Clock Frequency Frequency Period Period Slack Type Group
+----------------------------------------------------------------------------------------------------------------------------------------
+adcmv3|ADC0_LCLK 100.0 MHz 379.4 MHz 10.000 2.636 7.364 inferred Inferred_clkgroup_3
+adcmv3|ADC1_LCLK 100.0 MHz 379.4 MHz 10.000 2.636 7.364 inferred Inferred_clkgroup_4
+adcmv3|CLK100M 100.0 MHz 207.2 MHz 10.000 4.825 5.175 inferred Inferred_clkgroup_5
+dll_100m|clkop_inferred_clock 100.0 MHz 116.2 MHz 10.000 8.604 1.396 inferred Inferred_clkgroup_0
+pll_40m|CLKOP_inferred_clock 100.0 MHz 198.5 MHz 10.000 5.037 4.963 inferred Inferred_clkgroup_2
+sync_pll_40m|CLKOP_inferred_clock 100.0 MHz 587.6 MHz 10.000 1.702 8.298 inferred Inferred_clkgroup_1
+System 100.0 MHz 869.4 MHz 10.000 1.150 8.850 system default_clkgroup
+========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks | rise to rise | fall to fall | rise to fall | fall to rise
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+dll_100m|clkop_inferred_clock dll_100m|clkop_inferred_clock | 10.000 1.396 | No paths - | No paths - | No paths -
+dll_100m|clkop_inferred_clock pll_40m|CLKOP_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+dll_100m|clkop_inferred_clock adcmv3|ADC0_LCLK | Diff grp - | No paths - | No paths - | No paths -
+dll_100m|clkop_inferred_clock adcmv3|ADC1_LCLK | Diff grp - | No paths - | No paths - | No paths -
+dll_100m|clkop_inferred_clock adcmv3|CLK100M | Diff grp - | No paths - | No paths - | No paths -
+sync_pll_40m|CLKOP_inferred_clock dll_100m|clkop_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+sync_pll_40m|CLKOP_inferred_clock sync_pll_40m|CLKOP_inferred_clock | 10.000 8.298 | No paths - | No paths - | No paths -
+pll_40m|CLKOP_inferred_clock dll_100m|clkop_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+pll_40m|CLKOP_inferred_clock pll_40m|CLKOP_inferred_clock | 10.000 4.963 | No paths - | No paths - | No paths -
+pll_40m|CLKOP_inferred_clock adcmv3|ADC0_LCLK | Diff grp - | No paths - | No paths - | No paths -
+pll_40m|CLKOP_inferred_clock adcmv3|ADC1_LCLK | Diff grp - | No paths - | No paths - | No paths -
+adcmv3|ADC0_LCLK dll_100m|clkop_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+adcmv3|ADC0_LCLK pll_40m|CLKOP_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+adcmv3|ADC0_LCLK adcmv3|ADC0_LCLK | 10.000 7.364 | No paths - | No paths - | No paths -
+adcmv3|ADC1_LCLK dll_100m|clkop_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+adcmv3|ADC1_LCLK pll_40m|CLKOP_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+adcmv3|ADC1_LCLK adcmv3|ADC1_LCLK | 10.000 7.364 | No paths - | No paths - | No paths -
+adcmv3|CLK100M dll_100m|clkop_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+adcmv3|CLK100M adcmv3|CLK100M | 10.000 5.175 | No paths - | No paths - | No paths -
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+ 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information
+*********************
+
+ No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: adcmv3|ADC0_LCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+-------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_ADC0_HANDLER.swapcounter[0] adcmv3|ADC0_LCLK FD1S3IX Q un1_THE_ADC0_HANDLER[8] 1.091 7.364
+THE_ADC0_HANDLER.synccounter[0] adcmv3|ADC0_LCLK FD1S3IX Q THE_ADC0_HANDLER.synccounter[0] 1.091 7.364
+THE_ADC0_HANDLER.swap_dec adcmv3|ADC0_LCLK FD1S3IX Q un1_THE_ADC0_HANDLER[5] 1.075 7.380
+THE_ADC0_HANDLER.swap_inc adcmv3|ADC0_LCLK FD1S3IX Q un1_THE_ADC0_HANDLER[4] 1.075 7.380
+THE_ADC0_HANDLER.swapcounter[1] adcmv3|ADC0_LCLK FD1S3IX Q un1_THE_ADC0_HANDLER[9] 1.075 7.380
+THE_ADC0_HANDLER.sync_dec adcmv3|ADC0_LCLK FD1S3IX Q THE_ADC0_HANDLER.sync_dec 1.075 7.380
+THE_ADC0_HANDLER.sync_inc adcmv3|ADC0_LCLK FD1S3IX Q THE_ADC0_HANDLER.sync_inc 1.075 7.380
+THE_ADC0_HANDLER.synccounter[1] adcmv3|ADC0_LCLK FD1S3IX Q THE_ADC0_HANDLER.synccounter[1] 1.075 7.380
+THE_ADC0_CROSSOVER.THE_CROSSOVER.FF_12 adcmv3|ADC0_LCLK FD1S3DX Q THE_ADC0_CROSSOVER.THE_CROSSOVER.r_gcount_w24 1.091 7.685
+THE_ADC0_CROSSOVER.THE_CROSSOVER.FF_13 adcmv3|ADC0_LCLK FD1S3DX Q THE_ADC0_CROSSOVER.THE_CROSSOVER.r_gcount_w23 1.067 7.710
+=======================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_ADC0_HANDLER.swapcounter[2] adcmv3|ADC0_LCLK FD1S3IX D THE_ADC0_HANDLER.un1_swapcounter_1[2] 9.624 7.364
+THE_ADC0_HANDLER.synccounter[2] adcmv3|ADC0_LCLK FD1S3IX D THE_ADC0_HANDLER.un1_synccounter_1[2] 9.624 7.364
+THE_ADC0_CROSSOVER.THE_CROSSOVER.full_cmp_0 adcmv3|ADC0_LCLK AGEB2 B0 THE_ADC0_CROSSOVER.THE_CROSSOVER.rcount_w0 10.000 7.685
+THE_ADC0_HANDLER.THE_ADC_0_1_CH.data_0[0] adcmv3|ADC0_LCLK FD1P3AX D THE_ADC0_HANDLER.THE_ADC_0_1_CH.muxed_0[0] 9.624 7.888
+THE_ADC0_HANDLER.THE_ADC_0_1_CH.data_0[1] adcmv3|ADC0_LCLK FD1P3AX D THE_ADC0_HANDLER.THE_ADC_0_1_CH.muxed_0[1] 9.624 7.888
+THE_ADC0_HANDLER.THE_ADC_0_1_CH.data_0[2] adcmv3|ADC0_LCLK FD1P3AX D THE_ADC0_HANDLER.THE_ADC_0_1_CH.muxed_0[2] 9.624 7.888
+THE_ADC0_HANDLER.THE_ADC_0_1_CH.data_0[3] adcmv3|ADC0_LCLK FD1P3AX D THE_ADC0_HANDLER.THE_ADC_0_1_CH.muxed_0[3] 9.624 7.888
+THE_ADC0_HANDLER.THE_ADC_0_1_CH.data_0[4] adcmv3|ADC0_LCLK FD1P3AX D THE_ADC0_HANDLER.THE_ADC_0_1_CH.muxed_0[4] 9.624 7.888
+THE_ADC0_HANDLER.THE_ADC_0_1_CH.data_0[5] adcmv3|ADC0_LCLK FD1P3AX D THE_ADC0_HANDLER.THE_ADC_0_1_CH.muxed_0[5] 9.624 7.888
+THE_ADC0_HANDLER.THE_ADC_0_1_CH.data_0[6] adcmv3|ADC0_LCLK FD1P3AX D THE_ADC0_HANDLER.THE_ADC_0_1_CH.muxed_0[6] 9.624 7.888
+==========================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 10.000
+ - Setup time: 0.376
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 9.624
+
+ - Propagation time: 2.260
+ - Clock delay at starting point: 0.000 (ideal)
+ = Slack (non-critical) : 7.364
+
+ Number of logic level(s): 2
+ Starting point: THE_ADC0_HANDLER.swapcounter[0] / Q
+ Ending point: THE_ADC0_HANDLER.swapcounter[2] / D
+ The start point is clocked by adcmv3|ADC0_LCLK [rising] on pin CK
+ The end point is clocked by adcmv3|ADC0_LCLK [rising] on pin CK
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+--------------------------------------------------------------------------------------------------------------
+THE_ADC0_HANDLER.swapcounter[0] FD1S3IX Q Out 1.091 1.091 -
+un1_THE_ADC0_HANDLER[8] Net - - - - 5
+THE_ADC0_HANDLER.un1_swapcounter_1_1.CO1 ORCALUT4 C In 0.000 1.091 -
+THE_ADC0_HANDLER.un1_swapcounter_1_1.CO1 ORCALUT4 Z Out 0.754 1.846 -
+THE_ADC0_HANDLER.un1_swapcounter_1_1.N_2 Net - - - - 1
+THE_ADC0_HANDLER.un1_swapcounter_1_1.SUM2_0 ORCALUT4 A In 0.000 1.846 -
+THE_ADC0_HANDLER.un1_swapcounter_1_1.SUM2_0 ORCALUT4 Z Out 0.415 2.260 -
+THE_ADC0_HANDLER.un1_swapcounter_1[2] Net - - - - 1
+THE_ADC0_HANDLER.swapcounter[2] FD1S3IX D In 0.000 2.260 -
+==============================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: adcmv3|ADC1_LCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+-------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_ADC1_HANDLER.swapcounter[0] adcmv3|ADC1_LCLK FD1S3IX Q un1_THE_ADC1_HANDLER[8] 1.091 7.364
+THE_ADC1_HANDLER.synccounter[0] adcmv3|ADC1_LCLK FD1S3IX Q THE_ADC1_HANDLER.synccounter[0] 1.091 7.364
+THE_ADC1_HANDLER.swap_dec adcmv3|ADC1_LCLK FD1S3IX Q un1_THE_ADC1_HANDLER[5] 1.075 7.380
+THE_ADC1_HANDLER.swap_inc adcmv3|ADC1_LCLK FD1S3IX Q un1_THE_ADC1_HANDLER[4] 1.075 7.380
+THE_ADC1_HANDLER.swapcounter[1] adcmv3|ADC1_LCLK FD1S3IX Q un1_THE_ADC1_HANDLER[9] 1.075 7.380
+THE_ADC1_HANDLER.sync_dec adcmv3|ADC1_LCLK FD1S3IX Q THE_ADC1_HANDLER.sync_dec 1.075 7.380
+THE_ADC1_HANDLER.sync_inc adcmv3|ADC1_LCLK FD1S3IX Q THE_ADC1_HANDLER.sync_inc 1.075 7.380
+THE_ADC1_HANDLER.synccounter[1] adcmv3|ADC1_LCLK FD1S3IX Q THE_ADC1_HANDLER.synccounter[1] 1.075 7.380
+THE_ADC1_CROSSOVER.THE_CROSSOVER.FF_12 adcmv3|ADC1_LCLK FD1S3DX Q THE_ADC1_CROSSOVER.THE_CROSSOVER.r_gcount_w24 1.091 7.685
+THE_ADC1_CROSSOVER.THE_CROSSOVER.FF_13 adcmv3|ADC1_LCLK FD1S3DX Q THE_ADC1_CROSSOVER.THE_CROSSOVER.r_gcount_w23 1.067 7.710
+=======================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_ADC1_HANDLER.swapcounter[2] adcmv3|ADC1_LCLK FD1S3IX D THE_ADC1_HANDLER.N_296 9.624 7.364
+THE_ADC1_HANDLER.synccounter[2] adcmv3|ADC1_LCLK FD1S3IX D THE_ADC1_HANDLER.N_301 9.624 7.364
+THE_ADC1_CROSSOVER.THE_CROSSOVER.full_cmp_0 adcmv3|ADC1_LCLK AGEB2 B0 THE_ADC1_CROSSOVER.THE_CROSSOVER.rcount_w0 10.000 7.685
+THE_ADC1_HANDLER.THE_ADC_0_1_CH.data_0[0] adcmv3|ADC1_LCLK FD1P3AX D THE_ADC1_HANDLER.THE_ADC_0_1_CH.muxed_0[0] 9.624 7.888
+THE_ADC1_HANDLER.THE_ADC_0_1_CH.data_0[1] adcmv3|ADC1_LCLK FD1P3AX D THE_ADC1_HANDLER.THE_ADC_0_1_CH.muxed_0[1] 9.624 7.888
+THE_ADC1_HANDLER.THE_ADC_0_1_CH.data_0[2] adcmv3|ADC1_LCLK FD1P3AX D THE_ADC1_HANDLER.THE_ADC_0_1_CH.muxed_0[2] 9.624 7.888
+THE_ADC1_HANDLER.THE_ADC_0_1_CH.data_0[3] adcmv3|ADC1_LCLK FD1P3AX D THE_ADC1_HANDLER.THE_ADC_0_1_CH.muxed_0[3] 9.624 7.888
+THE_ADC1_HANDLER.THE_ADC_0_1_CH.data_0[4] adcmv3|ADC1_LCLK FD1P3AX D THE_ADC1_HANDLER.THE_ADC_0_1_CH.muxed_0[4] 9.624 7.888
+THE_ADC1_HANDLER.THE_ADC_0_1_CH.data_0[5] adcmv3|ADC1_LCLK FD1P3AX D THE_ADC1_HANDLER.THE_ADC_0_1_CH.muxed_0[5] 9.624 7.888
+THE_ADC1_HANDLER.THE_ADC_0_1_CH.data_0[6] adcmv3|ADC1_LCLK FD1P3AX D THE_ADC1_HANDLER.THE_ADC_0_1_CH.muxed_0[6] 9.624 7.888
+==========================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 10.000
+ - Setup time: 0.376
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 9.624
+
+ - Propagation time: 2.260
+ - Clock delay at starting point: 0.000 (ideal)
+ = Slack (non-critical) : 7.364
+
+ Number of logic level(s): 2
+ Starting point: THE_ADC1_HANDLER.swapcounter[0] / Q
+ Ending point: THE_ADC1_HANDLER.swapcounter[2] / D
+ The start point is clocked by adcmv3|ADC1_LCLK [rising] on pin CK
+ The end point is clocked by adcmv3|ADC1_LCLK [rising] on pin CK
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+--------------------------------------------------------------------------------------------------------------
+THE_ADC1_HANDLER.swapcounter[0] FD1S3IX Q Out 1.091 1.091 -
+un1_THE_ADC1_HANDLER[8] Net - - - - 5
+THE_ADC1_HANDLER.un1_swapcounter_1_1.CO1 ORCALUT4 C In 0.000 1.091 -
+THE_ADC1_HANDLER.un1_swapcounter_1_1.CO1 ORCALUT4 Z Out 0.754 1.846 -
+THE_ADC1_HANDLER.un1_swapcounter_1_1.N_2 Net - - - - 1
+THE_ADC1_HANDLER.un1_swapcounter_1_1.SUM2_0 ORCALUT4 A In 0.000 1.846 -
+THE_ADC1_HANDLER.un1_swapcounter_1_1.SUM2_0 ORCALUT4 Z Out 0.415 2.260 -
+THE_ADC1_HANDLER.N_296 Net - - - - 1
+THE_ADC1_HANDLER.swapcounter[2] FD1S3IX D In 0.000 2.260 -
+==============================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: adcmv3|CLK100M
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+--------------------------------------------------------------------------------------------------------------------------
+THE_RESET_HANDLER.reset_cnt[0] adcmv3|CLK100M FD1S3AX Q un1_THE_RESET_HANDLER_1[0] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[1] adcmv3|CLK100M FD1S3AX Q un1_THE_RESET_HANDLER_1[1] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[2] adcmv3|CLK100M FD1S3AX Q un1_THE_RESET_HANDLER_1[2] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[3] adcmv3|CLK100M FD1S3AX Q un1_THE_RESET_HANDLER_1[3] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[4] adcmv3|CLK100M FD1S3AX Q un1_THE_RESET_HANDLER_1[4] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[5] adcmv3|CLK100M FD1S3AX Q un1_THE_RESET_HANDLER_1[5] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[6] adcmv3|CLK100M FD1S3AX Q un1_THE_RESET_HANDLER_1[6] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[7] adcmv3|CLK100M FD1S3AX Q un1_THE_RESET_HANDLER_1[7] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[8] adcmv3|CLK100M FD1S3AX Q un1_THE_RESET_HANDLER_1[8] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[9] adcmv3|CLK100M FD1S3AX Q un1_THE_RESET_HANDLER_1[9] 1.035 5.175
+==========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+-----------------------------------------------------------------------------------------------------------------------------------
+THE_RESET_HANDLER.reset_cnt[1] adcmv3|CLK100M FD1S3AX D THE_RESET_HANDLER.reset_cnt_s[1] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[2] adcmv3|CLK100M FD1S3AX D THE_RESET_HANDLER.reset_cnt_s[2] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[3] adcmv3|CLK100M FD1S3AX D THE_RESET_HANDLER.reset_cnt_s[3] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[4] adcmv3|CLK100M FD1S3AX D THE_RESET_HANDLER.reset_cnt_s[4] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[5] adcmv3|CLK100M FD1S3AX D THE_RESET_HANDLER.reset_cnt_s[5] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[6] adcmv3|CLK100M FD1S3AX D THE_RESET_HANDLER.reset_cnt_s[6] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[7] adcmv3|CLK100M FD1S3AX D THE_RESET_HANDLER.reset_cnt_s[7] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[8] adcmv3|CLK100M FD1S3AX D THE_RESET_HANDLER.reset_cnt_s[8] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[9] adcmv3|CLK100M FD1S3AX D THE_RESET_HANDLER.reset_cnt_s[9] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[10] adcmv3|CLK100M FD1S3AX D THE_RESET_HANDLER.reset_cnt_s[10] 10.069 5.175
+===================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 10.000
+ - Setup time: -0.069
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 10.069
+
+ - Propagation time: 4.894
+ - Clock delay at starting point: 0.000 (ideal)
+ = Slack (non-critical) : 5.175
+
+ Number of logic level(s): 5
+ Starting point: THE_RESET_HANDLER.reset_cnt[0] / Q
+ Ending point: THE_RESET_HANDLER.reset_cnt[2] / D
+ The start point is clocked by adcmv3|CLK100M [rising] on pin CK
+ The end point is clocked by adcmv3|CLK100M [rising] on pin CK
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------
+THE_RESET_HANDLER.reset_cnt[0] FD1S3AX Q Out 1.035 1.035 -
+un1_THE_RESET_HANDLER_1[0] Net - - - - 2
+THE_RESET_HANDLER.THE_GLOBAL_RESET_PROC\.un6_reset_cnt_9 ORCALUT4 A In 0.000 1.035 -
+THE_RESET_HANDLER.THE_GLOBAL_RESET_PROC\.un6_reset_cnt_9 ORCALUT4 Z Out 0.754 1.789 -
+THE_RESET_HANDLER.THE_GLOBAL_RESET_PROC\.un6_reset_cnt_9 Net - - - - 1
+THE_RESET_HANDLER.THE_GLOBAL_RESET_PROC\.un6_reset_cnt ORCALUT4 B In 0.000 1.789 -
+THE_RESET_HANDLER.THE_GLOBAL_RESET_PROC\.un6_reset_cnt ORCALUT4 Z Out 0.827 2.616 -
+THE_RESET_HANDLER.THE_GLOBAL_RESET_PROC\.un6_reset_cnt Net - - - - 2
+THE_RESET_HANDLER.un1_reset2 ORCALUT4 A In 0.000 2.616 -
+THE_RESET_HANDLER.un1_reset2 ORCALUT4 Z Out 1.054 3.671 -
+THE_RESET_HANDLER.reset_cnt Net - - - - 17
+THE_RESET_HANDLER.reset_cnt_cry_0[0] CCU2B A1 In 0.000 3.671 -
+THE_RESET_HANDLER.reset_cnt_cry_0[0] CCU2B COUT Out 0.648 4.319 -
+THE_RESET_HANDLER.reset_cnt_cry[0] Net - - - - 1
+THE_RESET_HANDLER.reset_cnt_cry_0[1] CCU2B CIN In 0.000 4.319 -
+THE_RESET_HANDLER.reset_cnt_cry_0[1] CCU2B S1 Out 0.575 4.894 -
+THE_RESET_HANDLER.reset_cnt_s[2] Net - - - - 1
+THE_RESET_HANDLER.reset_cnt[2] FD1S3AX D In 0.000 4.894 -
+==========================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: dll_100m|clkop_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.last_mux_enable dll_100m|clkop_inferred_clock FD1S3IX Q THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.last_mux_enable 1.120 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[5] dll_100m|clkop_inferred_clock FD1P3IX Q THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.final_INT_READ_OUT_1[5] 0.994 1.522
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[4] dll_100m|clkop_inferred_clock FD1P3IX Q THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.final_INT_READ_OUT_1[4] 0.994 1.546
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[1] dll_100m|clkop_inferred_clock FD1P3IX Q THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.final_INT_READ_OUT_1[1] 0.994 1.740
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[2] dll_100m|clkop_inferred_clock FD1P3IX Q THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.final_INT_READ_OUT_1[2] 0.994 1.781
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[6] dll_100m|clkop_inferred_clock FD1P3IX Q THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.final_INT_READ_OUT_1[6] 0.994 1.781
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[0] dll_100m|clkop_inferred_clock FD1P3IX Q THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.final_INT_READ_OUT_1[0] 0.994 1.793
+THE_SLAVE_BUS.THE_SPI_MASTER.THE_SPI_SLIM.cmd_int[4] dll_100m|clkop_inferred_clock FD1P3IX Q THE_SLAVE_BUS.THE_SPI_MASTER.THE_SPI_SLIM.cmd_int[4] 1.140 2.007
+THE_SLAVE_BUS.THE_SPI_MASTER.THE_SPI_SLIM.cmd_int[3] dll_100m|clkop_inferred_clock FD1P3IX Q THE_SLAVE_BUS.THE_SPI_MASTER.THE_SPI_SLIM.cmd_int[3] 1.116 2.031
+THE_SLAVE_BUS.THE_SPI_MASTER.THE_SPI_SLIM.cmd_int[2] dll_100m|clkop_inferred_clock FD1P3IX Q THE_SLAVE_BUS.THE_SPI_MASTER.THE_SPI_SLIM.cmd_int[2] 1.140 2.047
+========================================================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[0] dll_100m|clkop_inferred_clock FD1P3IX SP THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.N_4_i 9.701 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[1] dll_100m|clkop_inferred_clock FD1P3IX SP THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.N_4_i 9.701 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[2] dll_100m|clkop_inferred_clock FD1P3IX SP THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.N_4_i 9.701 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[3] dll_100m|clkop_inferred_clock FD1P3IX SP THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.N_4_i 9.701 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[4] dll_100m|clkop_inferred_clock FD1P3IX SP THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.N_4_i 9.701 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[5] dll_100m|clkop_inferred_clock FD1P3IX SP THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.N_4_i 9.701 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[6] dll_100m|clkop_inferred_clock FD1P3IX SP THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.N_4_i 9.701 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[7] dll_100m|clkop_inferred_clock FD1P3IX SP THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.N_4_i 9.701 1.396
+THE_SLAVE_BUS.THE_SPI_MASTER.THE_SPI_SLIM.STATE[0] dll_100m|clkop_inferred_clock FD1P3IX D THE_SLAVE_BUS.N_2665_i 9.624 2.007
+THE_IPU_STAGE.fifo_last dll_100m|clkop_inferred_clock FD1S3AX D THE_IPU_STAGE.next_fifo_last 9.624 2.554
+=======================================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 10.000
+ - Setup time: 0.299
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 9.701
+
+ - Propagation time: 8.305
+ - Clock delay at starting point: 0.000 (ideal)
+ = Slack (critical) : 1.396
+
+ Number of logic level(s): 8
+ Starting point: THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.last_mux_enable / Q
+ Ending point: THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[0] / SP
+ The start point is clocked by dll_100m|clkop_inferred_clock [rising] on pin CK
+ The end point is clocked by dll_100m|clkop_inferred_clock [rising] on pin CK
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.last_mux_enable FD1S3IX Q Out 1.120 1.120 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.last_mux_enable Net - - - - 8
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.current_INT_READ_OUT_4[5] ORCALUT4 B In 0.000 1.120 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.current_INT_READ_OUT_4[5] ORCALUT4 Z Out 1.046 2.166 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.current_INT_READ_OUT_4[5] Net - - - - 16(15)
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.real_reading_6[5] ORCALUT4 B In 0.000 2.166 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.real_reading_6[5] ORCALUT4 Z Out 1.022 3.188 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.real_reading_6[5] Net - - - - 6
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.or_all\.tmp_3 ORCALUT4 B In 0.000 3.188 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.or_all\.tmp_3 ORCALUT4 Z Out 0.754 3.942 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.or_all\.tmp_3 Net - - - - 1
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.N_919_i ORCALUT4 A In 0.000 3.942 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.N_919_i ORCALUT4 Z Out 1.022 4.964 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.N_919_i Net - - - - 11
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.un1_current_p1_pattern4_2_i_a2_1 ORCALUT4 D In 0.000 4.964 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.un1_current_p1_pattern4_2_i_a2_1 ORCALUT4 Z Out 0.754 5.718 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.N_101 Net - - - - 1
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.un1_current_p1_pattern4_2_i_o2_0 ORCALUT4 A In 0.000 5.718 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.un1_current_p1_pattern4_2_i_o2_0 ORCALUT4 Z Out 0.754 6.472 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.un1_current_p1_pattern4_2_i_o2_0 Net - - - - 1
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.un1_current_p1_pattern4_2_i_o2 ORCALUT4 A In 0.000 6.472 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.un1_current_p1_pattern4_2_i_o2 ORCALUT4 Z Out 0.827 7.300 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.un1_MPLEX[20] Net - - - - 2
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.N_4_i ORCALUT4 D In 0.000 7.300 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.N_4_i ORCALUT4 Z Out 1.006 8.305 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.N_4_i Net - - - - 8
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[0] FD1P3IX SP In 0.000 8.305 -
+===================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll_40m|CLKOP_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_LOCKER.tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_LOCKER.tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_LOCKER.tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_LOCKER.tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_LOCKER.tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_LOCKER.tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_LOCKER.tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_LOCKER.tickmark_found 1.156 4.963
+==============================================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_LOCKER.THE_APV_LOCK_SM.N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_LOCKER.THE_APV_LOCK_SM.N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D THE_RAW_BUF_STAGE.GEN_ADC0\.3\.THE_APV_LOCKER.THE_APV_LOCK_SM.N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D THE_RAW_BUF_STAGE.GEN_ADC0\.5\.THE_APV_LOCKER.THE_APV_LOCK_SM.N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_LOCKER.THE_APV_LOCK_SM.N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_LOCKER.THE_APV_LOCK_SM.N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_LOCKER.THE_APV_LOCK_SM.N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_LOCKER.THE_APV_LOCK_SM.N_47_i 9.624 4.963
+=====================================================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 10.000
+ - Setup time: 0.376
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 9.624
+
+ - Propagation time: 4.661
+ - Clock delay at starting point: 0.000 (ideal)
+ = Slack (non-critical) : 4.963
+
+ Number of logic level(s): 5
+ Starting point: THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark / Q
+ Ending point: THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked / D
+ The start point is clocked by pll_40m|CLKOP_inferred_clock [rising] on pin CK
+ The end point is clocked by pll_40m|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark FD1S3IX Q Out 1.156 1.156 -
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.tickmark_found Net - - - - 15
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.next_locked_i_a2_1_0_a2_i_x2 ORCALUT4 B In 0.000 1.156 -
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.next_locked_i_a2_1_0_a2_i_x2 ORCALUT4 Z Out 0.827 1.984 -
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.N_66_i Net - - - - 2
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.next_locked_i_i_o2 ORCALUT4 B In 0.000 1.984 -
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.next_locked_i_i_o2 ORCALUT4 Z Out 0.754 2.738 -
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.N_81 Net - - - - 1
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.next_locked_i_i_582_tz_1 ORCALUT4 C In 0.000 2.738 -
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.next_locked_i_i_582_tz_1 ORCALUT4 Z Out 0.754 3.492 -
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.next_locked_i_i_582_tz_1 Net - - - - 1
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.next_locked_i_i_582_tz ORCALUT4 D In 0.000 3.492 -
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.next_locked_i_i_582_tz ORCALUT4 Z Out 0.754 4.247 -
+N_8886_tz Net - - - - 1
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.N_47_i ORCALUT4 A In 0.000 4.247 -
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.N_47_i ORCALUT4 Z Out 0.415 4.661 -
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.N_47_i Net - - - - 1
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked FD1S3IX D In 0.000 4.661 -
+===========================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sync_pll_40m|CLKOP_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+-----------------------------------------------------------------------------------------------------------
+test_reg40m sync_pll_40m|CLKOP_inferred_clock FD1S3DX Q test_reg40m 1.035 8.298
+===========================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+--------------------------------------------------------------------------------------------------------------
+test_reg40m sync_pll_40m|CLKOP_inferred_clock FD1S3DX D test_reg40m_i 9.908 8.298
+==============================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 10.000
+ - Setup time: 0.092
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 9.908
+
+ - Propagation time: 1.610
+ - Clock delay at starting point: 0.000 (ideal)
+ = Slack (non-critical) : 8.298
+
+ Number of logic level(s): 1
+ Starting point: test_reg40m / Q
+ Ending point: test_reg40m / D
+ The start point is clocked by sync_pll_40m|CLKOP_inferred_clock [rising] on pin CK
+ The end point is clocked by sync_pll_40m|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+--------------------------------------------------------------------------------
+test_reg40m FD1S3DX Q Out 1.035 1.035 -
+test_reg40m Net - - - - 2
+test_reg40m_i INV A In 0.000 1.035 -
+test_reg40m_i INV Z Out 0.575 1.610 -
+test_reg40m_i Net - - - - 1
+test_reg40m FD1S3DX D In 0.000 1.610 -
+================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RICH_TRB.THE_MEDIA_INTERFACE.gen_serdes_2\.THE_SERDES.PCSC_INST System PCSC FF_RX_D_2_10 THE_RICH_TRB.THE_MEDIA_INTERFACE.link_error[6] 0.000 6.736
+THE_RICH_TRB.THE_MEDIA_INTERFACE.gen_serdes_2\.THE_SERDES.PCSC_INST System PCSC FF_RX_D_2_22 THE_RICH_TRB.THE_MEDIA_INTERFACE.link_error[7] 0.000 6.736
+THE_RICH_TRB.THE_MEDIA_INTERFACE.gen_serdes_2\.THE_SERDES.PCSC_INST System PCSC FFS_PLOL THE_RICH_TRB.THE_MEDIA_INTERFACE.link_error[5] 0.000 6.874
+THE_RICH_TRB.THE_MEDIA_INTERFACE.gen_serdes_2\.THE_SERDES.PCSC_INST System PCSC FFS_RLOL_2 THE_RICH_TRB.THE_MEDIA_INTERFACE.link_error[4] 0.000 6.874
+THE_100M_DLL.dll_100m_0_0 System CIDDLLA CLKOP THE_100M_DLL.clkop_i 0.000 7.344
+THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.AND2_t2 System AND2 Z THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.rden_i 0.000 8.500
+THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.AND2_t3 System AND2 Z THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.wren_i 0.000 8.500
+THE_IPU_STAGE.GEN_FIFO\.0\.THE_LFIFO.AND2_t3 System AND2 Z THE_IPU_STAGE.GEN_FIFO\.0\.THE_LFIFO.rden_i 0.000 8.500
+THE_IPU_STAGE.GEN_FIFO\.0\.THE_LFIFO.AND2_t4 System AND2 Z THE_IPU_STAGE.GEN_FIFO\.0\.THE_LFIFO.wren_i 0.000 8.500
+THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.AND2_t2 System AND2 Z THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.rden_i 0.000 8.500
+======================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE[0] System FD1S3IX D THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATEc 9.624 6.736
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.rst_tctr System FD1S3IX D THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.rst_tctrc 9.624 6.736
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.ce_tctr System FD1S3AX D THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.next_ce_tctr 10.621 7.202
+THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.0\.THE_PED_MEM.ped_thr_true_0_0_0 System DP16KB ADB7 thr_addr[3] 8.500 7.344
+THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.1\.THE_PED_MEM.ped_thr_true_0_0_0 System DP16KB ADB7 thr_addr[3] 8.500 7.344
+THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.2\.THE_PED_MEM.ped_thr_true_0_0_0 System DP16KB ADB7 thr_addr[3] 8.500 7.344
+THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.3\.THE_PED_MEM.ped_thr_true_0_0_0 System DP16KB ADB7 thr_addr[3] 8.500 7.344
+THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.4\.THE_PED_MEM.ped_thr_true_0_0_0 System DP16KB ADB7 thr_addr[3] 8.500 7.344
+THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.5\.THE_PED_MEM.ped_thr_true_0_0_0 System DP16KB ADB7 thr_addr[3] 8.500 7.344
+THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.6\.THE_PED_MEM.ped_thr_true_0_0_0 System DP16KB ADB7 thr_addr[3] 8.500 7.344
+================================================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 10.000
+ - Setup time: 0.376
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 9.624
+
+ - Propagation time: 2.888
+ - Clock delay at starting point: 0.000 (ideal)
+ - Estimated clock delay at start point: -0.000
+ = Slack (non-critical) : 6.736
+
+ Number of logic level(s): 4
+ Starting point: THE_RICH_TRB.THE_MEDIA_INTERFACE.gen_serdes_2\.THE_SERDES.PCSC_INST / FF_RX_D_2_10
+ Ending point: THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE[0] / D
+ The start point is clocked by System [rising]
+ The end point is clocked by dll_100m|clkop_inferred_clock [rising] on pin CK
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RICH_TRB.THE_MEDIA_INTERFACE.gen_serdes_2\.THE_SERDES.PCSC_INST PCSC FF_RX_D_2_10 Out 0.000 0.000 -
+THE_RICH_TRB.THE_MEDIA_INTERFACE.link_error[6] Net - - - - 4
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE_ns_i_o3[0] ORCALUT4 A In 0.000 0.000 -
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE_ns_i_o3[0] ORCALUT4 Z Out 0.965 0.965 -
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.N_409_li Net - - - - 5
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE_ns_i_a5_1_0_0[0] ORCALUT4 D In 0.000 0.965 -
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE_ns_i_a5_1_0_0[0] ORCALUT4 Z Out 0.754 1.719 -
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE_ns_i_a5_1_0[0] Net - - - - 1
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE_ns_i_615_tz_1 ORCALUT4 A In 0.000 1.719 -
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE_ns_i_615_tz_1 ORCALUT4 Z Out 0.754 2.474 -
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE_ns_i_615_tz_1 Net - - - - 1
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATEc ORCALUT4 A In 0.000 2.474 -
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATEc ORCALUT4 Z Out 0.415 2.888 -
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATEc Net - - - - 1
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE[0] FD1S3IX D In 0.000 2.888 -
+======================================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+---------------------------------------
+Resource Usage Report
+Part: lfe2m100e-6
+
+Register bits: 15072 of 95000 (16%)
+PIC Latch: 0
+I/O cells: 111
+Block Rams : 143 of 288 (49%)
+
+
+Details:
+AND2: 125
+BB: 22
+CB2: 234
+CCU2B: 2527
+CU2: 458
+DP16KB: 143
+DPR16X4A: 108
+FADD2B: 329
+FD1P3AX: 1792
+FD1P3AY: 7
+FD1P3BX: 8
+FD1P3DX: 1849
+FD1P3IX: 1506
+FD1P3JX: 155
+FD1S3AX: 3720
+FD1S3AY: 8
+FD1S3BX: 43
+FD1S3DX: 198
+FD1S3IX: 5591
+FD1S3JX: 164
+FSUB2B: 6
+GSR: 1
+IB: 35
+IFS1P3DX: 17
+IFS1P3IX: 4
+INV: 396
+L6MUX21: 408
+OB: 54
+OFS1P3DX: 3
+OFS1P3IX: 4
+OFS1P3JX: 3
+OR2: 4
+ORCALUT4: 9810
+PFUMX: 833
+PUR: 1
+ROM128X1: 20
+ROM16X1: 181
+ROM256X1: 8
+SPR16X4A: 17
+VHI: 1
+VLO: 1
+XOR2: 97
+Finished restoring hierarchy (Time elapsed 0h:03m:11s; Memory used current: 303MB peak: 303MB)
+
+Writing Analyst data base /home/mboehmer/VHDL_Pro/comp_adcmv3/workdir/adcmv3.srm
+Finished Writing Netlist Databases (Time elapsed 0h:03m:21s; Memory used current: 265MB peak: 303MB)
+
+Writing EDIF Netlist and constraint files
+D-2010.03
+Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:03m:25s; Memory used current: 286MB peak: 303MB)
+
+Writing VHDL Simulation files
+Finished Writing VHDL Simulation files (Time elapsed 0h:03m:29s; Memory used current: 288MB peak: 303MB)
+
+Starting Writing Gated Clock Conversion Report (Time elapsed 0h:03m:30s; Memory used current: 285MB peak: 303MB)
+
+@N: MF276 |Gated clock conversion enabled, but no gated clocks found in design
+Finished Writing Gated Clock Conversion Report (Time elapsed 0h:03m:30s; Memory used current: 285MB peak: 303MB)
+
+Starting Writing Generated Clock Conversion Report (Time elapsed 0h:03m:30s; Memory used current: 285MB peak: 303MB)
+
+@N: MF333 |Generated clock conversion enabled, but no generated clocks found in design
+Finished Writing Generated Clock Conversion Report (Time elapsed 0h:03m:30s; Memory used current: 285MB peak: 303MB)
+
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Mon Jun 14 22:11:58 2010
+#
+
+
+Top view: adcmv3
+Requested Frequency: 100.0 MHz
+Wire load mode: top
+Paths requested: 5
+Constraint File(s):
+@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
+
+@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 1.396
+
+ Requested Estimated Requested Estimated Clock Clock
+Starting Clock Frequency Frequency Period Period Slack Type Group
+----------------------------------------------------------------------------------------------------------------------------------------
+adcmv3|ADC0_LCLK 100.0 MHz 379.4 MHz 10.000 2.636 7.364 inferred Inferred_clkgroup_3
+adcmv3|ADC1_LCLK 100.0 MHz 379.4 MHz 10.000 2.636 7.364 inferred Inferred_clkgroup_4
+adcmv3|CLK100M 100.0 MHz 207.2 MHz 10.000 4.825 5.175 inferred Inferred_clkgroup_5
+dll_100m|clkop_inferred_clock 100.0 MHz 116.2 MHz 10.000 8.604 1.396 inferred Inferred_clkgroup_0
+pll_40m|CLKOP_inferred_clock 100.0 MHz 198.5 MHz 10.000 5.037 4.963 inferred Inferred_clkgroup_2
+sync_pll_40m|CLKOP_inferred_clock 100.0 MHz 587.6 MHz 10.000 1.702 8.298 inferred Inferred_clkgroup_1
+System 100.0 MHz 869.4 MHz 10.000 1.150 8.850 system default_clkgroup
+========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks | rise to rise | fall to fall | rise to fall | fall to rise
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+dll_100m|clkop_inferred_clock dll_100m|clkop_inferred_clock | 10.000 1.396 | No paths - | No paths - | No paths -
+dll_100m|clkop_inferred_clock pll_40m|CLKOP_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+dll_100m|clkop_inferred_clock adcmv3|ADC0_LCLK | Diff grp - | No paths - | No paths - | No paths -
+dll_100m|clkop_inferred_clock adcmv3|ADC1_LCLK | Diff grp - | No paths - | No paths - | No paths -
+dll_100m|clkop_inferred_clock adcmv3|CLK100M | Diff grp - | No paths - | No paths - | No paths -
+sync_pll_40m|CLKOP_inferred_clock dll_100m|clkop_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+sync_pll_40m|CLKOP_inferred_clock sync_pll_40m|CLKOP_inferred_clock | 10.000 8.298 | No paths - | No paths - | No paths -
+pll_40m|CLKOP_inferred_clock dll_100m|clkop_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+pll_40m|CLKOP_inferred_clock pll_40m|CLKOP_inferred_clock | 10.000 4.963 | No paths - | No paths - | No paths -
+pll_40m|CLKOP_inferred_clock adcmv3|ADC0_LCLK | Diff grp - | No paths - | No paths - | No paths -
+pll_40m|CLKOP_inferred_clock adcmv3|ADC1_LCLK | Diff grp - | No paths - | No paths - | No paths -
+adcmv3|ADC0_LCLK dll_100m|clkop_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+adcmv3|ADC0_LCLK pll_40m|CLKOP_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+adcmv3|ADC0_LCLK adcmv3|ADC0_LCLK | 10.000 7.364 | No paths - | No paths - | No paths -
+adcmv3|ADC1_LCLK dll_100m|clkop_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+adcmv3|ADC1_LCLK pll_40m|CLKOP_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+adcmv3|ADC1_LCLK adcmv3|ADC1_LCLK | 10.000 7.364 | No paths - | No paths - | No paths -
+adcmv3|CLK100M dll_100m|clkop_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
+adcmv3|CLK100M adcmv3|CLK100M | 10.000 5.175 | No paths - | No paths - | No paths -
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+ 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information
+*********************
+
+ No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: adcmv3|ADC0_LCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+--------------------------------------------------------------------------------------------------------------------------
+THE_ADC0_HANDLER.swapcounter[0] adcmv3|ADC0_LCLK FD1S3IX Q swapcounter_Q[0] 1.091 7.364
+THE_ADC0_HANDLER.synccounter[0] adcmv3|ADC0_LCLK FD1S3IX Q synccounter[0] 1.091 7.364
+THE_ADC0_HANDLER.swap_dec adcmv3|ADC0_LCLK FD1S3IX Q swap_dec_Q 1.075 7.380
+THE_ADC0_HANDLER.swap_inc adcmv3|ADC0_LCLK FD1S3IX Q swap_inc_Q 1.075 7.380
+THE_ADC0_HANDLER.swapcounter[1] adcmv3|ADC0_LCLK FD1S3IX Q swapcounter_Q[1] 1.075 7.380
+THE_ADC0_HANDLER.sync_dec adcmv3|ADC0_LCLK FD1S3IX Q sync_dec 1.075 7.380
+THE_ADC0_HANDLER.sync_inc adcmv3|ADC0_LCLK FD1S3IX Q sync_inc 1.075 7.380
+THE_ADC0_HANDLER.synccounter[1] adcmv3|ADC0_LCLK FD1S3IX Q synccounter[1] 1.075 7.380
+THE_ADC0_CROSSOVER.THE_CROSSOVER.FF_12 adcmv3|ADC0_LCLK FD1S3DX Q r_gcount_w24 1.091 7.685
+THE_ADC0_CROSSOVER.THE_CROSSOVER.FF_13 adcmv3|ADC0_LCLK FD1S3DX Q r_gcount_w23 1.067 7.710
+==========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+------------------------------------------------------------------------------------------------------------------------------------
+THE_ADC0_HANDLER.swapcounter[2] adcmv3|ADC0_LCLK FD1S3IX D un1_swapcounter_1[2] 9.624 7.364
+THE_ADC0_HANDLER.synccounter[2] adcmv3|ADC0_LCLK FD1S3IX D un1_synccounter_1[2] 9.624 7.364
+THE_ADC0_CROSSOVER.THE_CROSSOVER.full_cmp_0 adcmv3|ADC0_LCLK AGEB2 B0 rcount_w0 10.000 7.685
+THE_ADC0_HANDLER.THE_ADC_4_5_CH.data_0[0] adcmv3|ADC0_LCLK FD1P3AX D muxed_0[0] 9.624 7.888
+THE_ADC0_HANDLER.THE_ADC_6_7_CH.data_0[0] adcmv3|ADC0_LCLK FD1P3AX D muxed_0[0] 9.624 7.888
+THE_ADC0_HANDLER.THE_ADC_0_1_CH.data_0[0] adcmv3|ADC0_LCLK FD1P3AX D muxed_0[0] 9.624 7.888
+THE_ADC0_HANDLER.THE_ADC_2_3_CH.data_0[0] adcmv3|ADC0_LCLK FD1P3AX D muxed_0[0] 9.624 7.888
+THE_ADC0_HANDLER.THE_ADC_4_5_CH.data_0[1] adcmv3|ADC0_LCLK FD1P3AX D muxed_0[1] 9.624 7.888
+THE_ADC0_HANDLER.THE_ADC_6_7_CH.data_0[1] adcmv3|ADC0_LCLK FD1P3AX D muxed_0[1] 9.624 7.888
+THE_ADC0_HANDLER.THE_ADC_0_1_CH.data_0[1] adcmv3|ADC0_LCLK FD1P3AX D muxed_0[1] 9.624 7.888
+====================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 10.000
+ - Setup time: 0.376
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 9.624
+
+ - Propagation time: 2.260
+ - Clock delay at starting point: 0.000 (ideal)
+ = Slack (non-critical) : 7.364
+
+ Number of logic level(s): 2
+ Starting point: THE_ADC0_HANDLER.swapcounter[0] / Q
+ Ending point: THE_ADC0_HANDLER.swapcounter[2] / D
+ The start point is clocked by adcmv3|ADC0_LCLK [rising] on pin CK
+ The end point is clocked by adcmv3|ADC0_LCLK [rising] on pin CK
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+--------------------------------------------------------------------------------------------------------------
+THE_ADC0_HANDLER.swapcounter[0] FD1S3IX Q Out 1.091 1.091 -
+swapcounter_Q[0] Net - - - - 5
+THE_ADC0_HANDLER.un1_swapcounter_1_1.CO1 ORCALUT4 C In 0.000 1.091 -
+THE_ADC0_HANDLER.un1_swapcounter_1_1.CO1 ORCALUT4 Z Out 0.754 1.846 -
+N_2 Net - - - - 1
+THE_ADC0_HANDLER.un1_swapcounter_1_1.SUM2_0 ORCALUT4 A In 0.000 1.846 -
+THE_ADC0_HANDLER.un1_swapcounter_1_1.SUM2_0 ORCALUT4 Z Out 0.415 2.260 -
+un1_swapcounter_1[2] Net - - - - 1
+THE_ADC0_HANDLER.swapcounter[2] FD1S3IX D In 0.000 2.260 -
+==============================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: adcmv3|ADC1_LCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+----------------------------------------------------------------------------------------------------------------------------
+THE_ADC1_HANDLER.swapcounter[0] adcmv3|ADC1_LCLK FD1S3IX Q swapcounter_Q_0[0] 1.091 7.364
+THE_ADC1_HANDLER.synccounter[0] adcmv3|ADC1_LCLK FD1S3IX Q synccounter[0] 1.091 7.364
+THE_ADC1_HANDLER.swap_dec adcmv3|ADC1_LCLK FD1S3IX Q swap_dec_Q_0 1.075 7.380
+THE_ADC1_HANDLER.swap_inc adcmv3|ADC1_LCLK FD1S3IX Q swap_inc_Q_0 1.075 7.380
+THE_ADC1_HANDLER.swapcounter[1] adcmv3|ADC1_LCLK FD1S3IX Q swapcounter_Q_0[1] 1.075 7.380
+THE_ADC1_HANDLER.sync_dec adcmv3|ADC1_LCLK FD1S3IX Q sync_dec 1.075 7.380
+THE_ADC1_HANDLER.sync_inc adcmv3|ADC1_LCLK FD1S3IX Q sync_inc 1.075 7.380
+THE_ADC1_HANDLER.synccounter[1] adcmv3|ADC1_LCLK FD1S3IX Q synccounter[1] 1.075 7.380
+THE_ADC1_CROSSOVER.THE_CROSSOVER.FF_12 adcmv3|ADC1_LCLK FD1S3DX Q r_gcount_w24 1.091 7.685
+THE_ADC1_CROSSOVER.THE_CROSSOVER.FF_13 adcmv3|ADC1_LCLK FD1S3DX Q r_gcount_w23 1.067 7.710
+============================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+--------------------------------------------------------------------------------------------------------------------------
+THE_ADC1_HANDLER.swapcounter[2] adcmv3|ADC1_LCLK FD1S3IX D N_296 9.624 7.364
+THE_ADC1_HANDLER.synccounter[2] adcmv3|ADC1_LCLK FD1S3IX D N_301 9.624 7.364
+THE_ADC1_CROSSOVER.THE_CROSSOVER.full_cmp_0 adcmv3|ADC1_LCLK AGEB2 B0 rcount_w0 10.000 7.685
+THE_ADC1_HANDLER.THE_ADC_4_5_CH.data_0[0] adcmv3|ADC1_LCLK FD1P3AX D muxed_0[0] 9.624 7.888
+THE_ADC1_HANDLER.THE_ADC_6_7_CH.data_0[0] adcmv3|ADC1_LCLK FD1P3AX D muxed_0[0] 9.624 7.888
+THE_ADC1_HANDLER.THE_ADC_0_1_CH.data_0[0] adcmv3|ADC1_LCLK FD1P3AX D muxed_0[0] 9.624 7.888
+THE_ADC1_HANDLER.THE_ADC_2_3_CH.data_0[0] adcmv3|ADC1_LCLK FD1P3AX D muxed_0[0] 9.624 7.888
+THE_ADC1_HANDLER.THE_ADC_4_5_CH.data_0[1] adcmv3|ADC1_LCLK FD1P3AX D muxed_0[1] 9.624 7.888
+THE_ADC1_HANDLER.THE_ADC_6_7_CH.data_0[1] adcmv3|ADC1_LCLK FD1P3AX D muxed_0[1] 9.624 7.888
+THE_ADC1_HANDLER.THE_ADC_0_1_CH.data_0[1] adcmv3|ADC1_LCLK FD1P3AX D muxed_0[1] 9.624 7.888
+==========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 10.000
+ - Setup time: 0.376
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 9.624
+
+ - Propagation time: 2.260
+ - Clock delay at starting point: 0.000 (ideal)
+ = Slack (non-critical) : 7.364
+
+ Number of logic level(s): 2
+ Starting point: THE_ADC1_HANDLER.swapcounter[0] / Q
+ Ending point: THE_ADC1_HANDLER.swapcounter[2] / D
+ The start point is clocked by adcmv3|ADC1_LCLK [rising] on pin CK
+ The end point is clocked by adcmv3|ADC1_LCLK [rising] on pin CK
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+--------------------------------------------------------------------------------------------------------------
+THE_ADC1_HANDLER.swapcounter[0] FD1S3IX Q Out 1.091 1.091 -
+swapcounter_Q_0[0] Net - - - - 5
+THE_ADC1_HANDLER.un1_swapcounter_1_1.CO1 ORCALUT4 C In 0.000 1.091 -
+THE_ADC1_HANDLER.un1_swapcounter_1_1.CO1 ORCALUT4 Z Out 0.754 1.846 -
+N_2 Net - - - - 1
+THE_ADC1_HANDLER.un1_swapcounter_1_1.SUM2_0 ORCALUT4 A In 0.000 1.846 -
+THE_ADC1_HANDLER.un1_swapcounter_1_1.SUM2_0 ORCALUT4 Z Out 0.415 2.260 -
+N_296 Net - - - - 1
+THE_ADC1_HANDLER.swapcounter[2] FD1S3IX D In 0.000 2.260 -
+==============================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: adcmv3|CLK100M
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+--------------------------------------------------------------------------------------------------------------
+THE_RESET_HANDLER.reset_cnt[0] adcmv3|CLK100M FD1S3AX Q reset_cnt_Q[0] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[1] adcmv3|CLK100M FD1S3AX Q reset_cnt_Q[1] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[2] adcmv3|CLK100M FD1S3AX Q reset_cnt_Q[2] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[3] adcmv3|CLK100M FD1S3AX Q reset_cnt_Q[3] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[4] adcmv3|CLK100M FD1S3AX Q reset_cnt_Q[4] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[5] adcmv3|CLK100M FD1S3AX Q reset_cnt_Q[5] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[6] adcmv3|CLK100M FD1S3AX Q reset_cnt_Q[6] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[7] adcmv3|CLK100M FD1S3AX Q reset_cnt_Q[7] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[8] adcmv3|CLK100M FD1S3AX Q reset_cnt_Q[8] 1.035 5.175
+THE_RESET_HANDLER.reset_cnt[9] adcmv3|CLK100M FD1S3AX Q reset_cnt_Q[9] 1.035 5.175
+==============================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+-----------------------------------------------------------------------------------------------------------------
+THE_RESET_HANDLER.reset_cnt[1] adcmv3|CLK100M FD1S3AX D reset_cnt_s[1] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[2] adcmv3|CLK100M FD1S3AX D reset_cnt_s[2] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[3] adcmv3|CLK100M FD1S3AX D reset_cnt_s[3] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[4] adcmv3|CLK100M FD1S3AX D reset_cnt_s[4] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[5] adcmv3|CLK100M FD1S3AX D reset_cnt_s[5] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[6] adcmv3|CLK100M FD1S3AX D reset_cnt_s[6] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[7] adcmv3|CLK100M FD1S3AX D reset_cnt_s[7] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[8] adcmv3|CLK100M FD1S3AX D reset_cnt_s[8] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[9] adcmv3|CLK100M FD1S3AX D reset_cnt_s[9] 10.069 5.175
+THE_RESET_HANDLER.reset_cnt[10] adcmv3|CLK100M FD1S3AX D reset_cnt_s[10] 10.069 5.175
+=================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 10.000
+ - Setup time: -0.069
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 10.069
+
+ - Propagation time: 4.894
+ - Clock delay at starting point: 0.000 (ideal)
+ = Slack (non-critical) : 5.175
+
+ Number of logic level(s): 5
+ Starting point: THE_RESET_HANDLER.reset_cnt[0] / Q
+ Ending point: THE_RESET_HANDLER.reset_cnt[2] / D
+ The start point is clocked by adcmv3|CLK100M [rising] on pin CK
+ The end point is clocked by adcmv3|CLK100M [rising] on pin CK
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+--------------------------------------------------------------------------------------------------------------------------
+THE_RESET_HANDLER.reset_cnt[0] FD1S3AX Q Out 1.035 1.035 -
+reset_cnt_Q[0] Net - - - - 2
+THE_RESET_HANDLER.THE_GLOBAL_RESET_PROC\.un6_reset_cnt_9 ORCALUT4 A In 0.000 1.035 -
+THE_RESET_HANDLER.THE_GLOBAL_RESET_PROC\.un6_reset_cnt_9 ORCALUT4 Z Out 0.754 1.789 -
+un6_reset_cnt_9 Net - - - - 1
+THE_RESET_HANDLER.THE_GLOBAL_RESET_PROC\.un6_reset_cnt ORCALUT4 B In 0.000 1.789 -
+THE_RESET_HANDLER.THE_GLOBAL_RESET_PROC\.un6_reset_cnt ORCALUT4 Z Out 0.827 2.616 -
+un6_reset_cnt Net - - - - 2
+THE_RESET_HANDLER.un1_reset2 ORCALUT4 A In 0.000 2.616 -
+THE_RESET_HANDLER.un1_reset2 ORCALUT4 Z Out 1.054 3.671 -
+reset_cnt Net - - - - 17
+THE_RESET_HANDLER.reset_cnt_cry_0[0] CCU2B A1 In 0.000 3.671 -
+THE_RESET_HANDLER.reset_cnt_cry_0[0] CCU2B COUT Out 0.648 4.319 -
+reset_cnt_cry[0] Net - - - - 1
+THE_RESET_HANDLER.reset_cnt_cry_0[1] CCU2B CIN In 0.000 4.319 -
+THE_RESET_HANDLER.reset_cnt_cry_0[1] CCU2B S1 Out 0.575 4.894 -
+reset_cnt_s[2] Net - - - - 1
+THE_RESET_HANDLER.reset_cnt[2] FD1S3AX D In 0.000 4.894 -
+==========================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: dll_100m|clkop_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.last_mux_enable dll_100m|clkop_inferred_clock FD1S3IX Q last_mux_enable 1.120 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[5] dll_100m|clkop_inferred_clock FD1P3IX Q final_INT_READ_OUT_1[5] 0.994 1.522
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[4] dll_100m|clkop_inferred_clock FD1P3IX Q final_INT_READ_OUT_1[4] 0.994 1.546
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[1] dll_100m|clkop_inferred_clock FD1P3IX Q final_INT_READ_OUT_1[1] 0.994 1.740
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[2] dll_100m|clkop_inferred_clock FD1P3IX Q final_INT_READ_OUT_1[2] 0.994 1.781
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[6] dll_100m|clkop_inferred_clock FD1P3IX Q final_INT_READ_OUT_1[6] 0.994 1.781
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[0] dll_100m|clkop_inferred_clock FD1P3IX Q final_INT_READ_OUT_1[0] 0.994 1.793
+THE_SLAVE_BUS.THE_SPI_MASTER.THE_SPI_SLIM.cmd_int[4] dll_100m|clkop_inferred_clock FD1P3IX Q cmd_int[4] 1.140 2.007
+THE_SLAVE_BUS.THE_SPI_MASTER.THE_SPI_SLIM.cmd_int[3] dll_100m|clkop_inferred_clock FD1P3IX Q cmd_int[3] 1.116 2.031
+THE_SLAVE_BUS.THE_SPI_MASTER.THE_SPI_SLIM.cmd_int[2] dll_100m|clkop_inferred_clock FD1P3IX Q cmd_int[2] 1.140 2.047
+================================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[0] dll_100m|clkop_inferred_clock FD1P3IX SP N_4_i 9.701 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[1] dll_100m|clkop_inferred_clock FD1P3IX SP N_4_i 9.701 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[2] dll_100m|clkop_inferred_clock FD1P3IX SP N_4_i 9.701 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[3] dll_100m|clkop_inferred_clock FD1P3IX SP N_4_i 9.701 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[4] dll_100m|clkop_inferred_clock FD1P3IX SP N_4_i 9.701 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[5] dll_100m|clkop_inferred_clock FD1P3IX SP N_4_i 9.701 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[6] dll_100m|clkop_inferred_clock FD1P3IX SP N_4_i 9.701 1.396
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[7] dll_100m|clkop_inferred_clock FD1P3IX SP N_4_i 9.701 1.396
+THE_SLAVE_BUS.THE_SPI_MASTER.THE_SPI_SLIM.STATE[0] dll_100m|clkop_inferred_clock FD1P3IX D N_2665_i 9.624 2.007
+THE_IPU_STAGE.fifo_last dll_100m|clkop_inferred_clock FD1S3AX D next_fifo_last 9.624 2.554
+========================================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 10.000
+ - Setup time: 0.299
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 9.701
+
+ - Propagation time: 8.305
+ - Clock delay at starting point: 0.000 (ideal)
+ = Slack (critical) : 1.396
+
+ Number of logic level(s): 8
+ Starting point: THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.last_mux_enable / Q
+ Ending point: THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[0] / SP
+ The start point is clocked by dll_100m|clkop_inferred_clock [rising] on pin CK
+ The end point is clocked by dll_100m|clkop_inferred_clock [rising] on pin CK
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.last_mux_enable FD1S3IX Q Out 1.120 1.120 -
+last_mux_enable Net - - - - 8
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.current_INT_READ_OUT_4[5] ORCALUT4 B In 0.000 1.120 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.current_INT_READ_OUT_4[5] ORCALUT4 Z Out 1.046 2.166 -
+current_INT_READ_OUT_4[5] Net - - - - 16(15)
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.real_reading_6[5] ORCALUT4 B In 0.000 2.166 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.real_reading_6[5] ORCALUT4 Z Out 1.022 3.188 -
+real_reading_6[5] Net - - - - 7(6)
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.or_all\.tmp_3 ORCALUT4 B In 0.000 3.188 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.or_all\.tmp_3 ORCALUT4 Z Out 0.754 3.942 -
+tmp_3 Net - - - - 1
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.mux_read_RNO ORCALUT4 A In 0.000 3.942 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.mux_read_RNO ORCALUT4 Z Out 1.022 4.964 -
+N_919_i Net - - - - 7(11)
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.un1_current_p1_pattern4_2_i_a2_1 ORCALUT4 D In 0.000 4.964 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.un1_current_p1_pattern4_2_i_a2_1 ORCALUT4 Z Out 0.754 5.718 -
+N_101 Net - - - - 1
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.un1_current_p1_pattern4_2_i_o2_0 ORCALUT4 A In 0.000 5.718 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.un1_current_p1_pattern4_2_i_o2_0 ORCALUT4 Z Out 0.754 6.472 -
+un1_current_p1_pattern4_2_i_o2_0 Net - - - - 1
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.un1_current_p1_pattern4_2_i_o2 ORCALUT4 A In 0.000 6.472 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.un1_current_p1_pattern4_2_i_o2 ORCALUT4 Z Out 0.827 7.300 -
+un1_current_p1_pattern4_2_i_o2 Net - - - - 2
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.un1_current_p1_pattern4_2_i_o2_RNII0ED ORCALUT4 D In 0.000 7.300 -
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.un1_current_p1_pattern4_2_i_o2_RNII0ED ORCALUT4 Z Out 1.006 8.305 -
+N_4_i Net - - - - 8
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.current_final_pattern[0] FD1P3IX SP In 0.000 8.305 -
+=========================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: pll_40m|CLKOP_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC1\.8\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC1\.13\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC1\.9\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q tickmark_found 1.156 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark pll_40m|CLKOP_inferred_clock FD1S3IX Q tickmark_found 1.156 4.963
+===================================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RAW_BUF_STAGE.GEN_ADC0\.7\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC1\.14\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC1\.12\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.1\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC1\.10\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.6\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.2\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC1\.15\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D N_47_i 9.624 4.963
+THE_RAW_BUF_STAGE.GEN_ADC0\.0\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked pll_40m|CLKOP_inferred_clock FD1S3IX D N_47_i 9.624 4.963
+==========================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 10.000
+ - Setup time: 0.376
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 9.624
+
+ - Propagation time: 4.661
+ - Clock delay at starting point: 0.000 (ideal)
+ = Slack (non-critical) : 4.963
+
+ Number of logic level(s): 5
+ Starting point: THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark / Q
+ Ending point: THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked / D
+ The start point is clocked by pll_40m|CLKOP_inferred_clock [rising] on pin CK
+ The end point is clocked by pll_40m|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_DIGITAL.tickmark FD1S3IX Q Out 1.156 1.156 -
+tickmark_found Net - - - - 15
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.next_locked_i_a2_1_0_a2_i_x2 ORCALUT4 B In 0.000 1.156 -
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.next_locked_i_a2_1_0_a2_i_x2 ORCALUT4 Z Out 0.827 1.984 -
+N_66_i Net - - - - 2
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.next_locked_i_i_o2 ORCALUT4 B In 0.000 1.984 -
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.next_locked_i_i_o2 ORCALUT4 Z Out 0.754 2.738 -
+N_81 Net - - - - 1
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked_RNO_1 ORCALUT4 C In 0.000 2.738 -
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked_RNO_1 ORCALUT4 Z Out 0.754 3.492 -
+next_locked_i_i_601_tz_1 Net - - - - 1
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked_RNO_0 ORCALUT4 D In 0.000 3.492 -
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked_RNO_0 ORCALUT4 Z Out 0.754 4.247 -
+N_8905_tz Net - - - - 1
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked_RNO ORCALUT4 A In 0.000 4.247 -
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked_RNO ORCALUT4 Z Out 0.415 4.661 -
+N_47_i Net - - - - 1
+THE_RAW_BUF_STAGE.GEN_ADC0\.4\.THE_APV_LOCKER.THE_APV_LOCK_SM.locked FD1S3IX D In 0.000 4.661 -
+===========================================================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sync_pll_40m|CLKOP_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+-----------------------------------------------------------------------------------------------------------
+test_reg40m sync_pll_40m|CLKOP_inferred_clock FD1S3DX Q test_reg40m 1.035 8.298
+===========================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+--------------------------------------------------------------------------------------------------------------
+test_reg40m sync_pll_40m|CLKOP_inferred_clock FD1S3DX D test_reg40m_i 9.908 8.298
+==============================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 10.000
+ - Setup time: 0.092
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 9.908
+
+ - Propagation time: 1.610
+ - Clock delay at starting point: 0.000 (ideal)
+ = Slack (non-critical) : 8.298
+
+ Number of logic level(s): 1
+ Starting point: test_reg40m / Q
+ Ending point: test_reg40m / D
+ The start point is clocked by sync_pll_40m|CLKOP_inferred_clock [rising] on pin CK
+ The end point is clocked by sync_pll_40m|CLKOP_inferred_clock [rising] on pin CK
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+---------------------------------------------------------------------------------
+test_reg40m FD1S3DX Q Out 1.035 1.035 -
+test_reg40m Net - - - - 2
+test_reg40m_RNO INV A In 0.000 1.035 -
+test_reg40m_RNO INV Z Out 0.575 1.610 -
+test_reg40m_i Net - - - - 1
+test_reg40m FD1S3DX D In 0.000 1.610 -
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+ Starting Arrival
+Instance Reference Type Pin Net Time Slack
+ Clock
+-----------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RICH_TRB.THE_MEDIA_INTERFACE.gen_serdes_2\.THE_SERDES.PCSC_INST System PCSC FF_RX_D_2_10 link_error[6] 0.000 6.736
+THE_RICH_TRB.THE_MEDIA_INTERFACE.gen_serdes_2\.THE_SERDES.PCSC_INST System PCSC FF_RX_D_2_22 link_error[7] 0.000 6.736
+THE_RICH_TRB.THE_MEDIA_INTERFACE.gen_serdes_2\.THE_SERDES.PCSC_INST System PCSC FFS_PLOL link_error[5] 0.000 6.874
+THE_RICH_TRB.THE_MEDIA_INTERFACE.gen_serdes_2\.THE_SERDES.PCSC_INST System PCSC FFS_RLOL_2 link_error[4] 0.000 6.874
+THE_100M_DLL.dll_100m_0_0 System CIDDLLA CLKOP clkop_i 0.000 7.344
+THE_IPU_STAGE.GEN_FIFO\.10\.THE_DFIFO.AND2_t2 System AND2 Z rden_i 0.000 8.500
+THE_IPU_STAGE.GEN_FIFO\.0\.THE_DFIFO.AND2_t2 System AND2 Z rden_i 0.000 8.500
+THE_IPU_STAGE.GEN_FIFO\.15\.THE_DFIFO.AND2_t2 System AND2 Z rden_i 0.000 8.500
+THE_IPU_STAGE.GEN_FIFO\.6\.THE_DFIFO.AND2_t2 System AND2 Z rden_i 0.000 8.500
+THE_IPU_STAGE.GEN_FIFO\.1\.THE_DFIFO.AND2_t2 System AND2 Z rden_i 0.000 8.500
+=====================================================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+ Starting Required
+Instance Reference Type Pin Net Time Slack
+ Clock
+----------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE[0] System FD1S3IX D CURRENT_STATEc 9.624 6.736
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.rst_tctr System FD1S3IX D rst_tctrc 9.624 6.736
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.ce_tctr System FD1S3AX D next_ce_tctr 10.621 7.202
+THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.5\.THE_PED_MEM.ped_thr_true_0_0_0 System DP16KB ADB7 thr_addr[3] 8.500 7.344
+THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.11\.THE_PED_MEM.ped_thr_true_0_0_0 System DP16KB ADB7 thr_addr[3] 8.500 7.344
+THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.13\.THE_PED_MEM.ped_thr_true_0_0_0 System DP16KB ADB7 thr_addr[3] 8.500 7.344
+THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.6\.THE_PED_MEM.ped_thr_true_0_0_0 System DP16KB ADB7 thr_addr[3] 8.500 7.344
+THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.10\.THE_PED_MEM.ped_thr_true_0_0_0 System DP16KB ADB7 thr_addr[3] 8.500 7.344
+THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.14\.THE_PED_MEM.ped_thr_true_0_0_0 System DP16KB ADB7 thr_addr[3] 8.500 7.344
+THE_SLAVE_BUS.THE_THR_MEM.GEN_PED_MEM\.4\.THE_PED_MEM.ped_thr_true_0_0_0 System DP16KB ADB7 thr_addr[3] 8.500 7.344
+====================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1:
+ Requested Period: 10.000
+ - Setup time: 0.376
+ + Clock delay at ending point: 0.000 (ideal)
+ = Required time: 9.624
+
+ - Propagation time: 2.888
+ - Clock delay at starting point: 0.000 (ideal)
+ - Estimated clock delay at start point: -0.000
+ = Slack (non-critical) : 6.736
+
+ Number of logic level(s): 4
+ Starting point: THE_RICH_TRB.THE_MEDIA_INTERFACE.gen_serdes_2\.THE_SERDES.PCSC_INST / FF_RX_D_2_10
+ Ending point: THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE[0] / D
+ The start point is clocked by System [rising]
+ The end point is clocked by dll_100m|clkop_inferred_clock [rising] on pin CK
+
+Instance / Net Pin Pin Arrival No. of
+Name Type Name Dir Delay Time Fan Out(s)
+------------------------------------------------------------------------------------------------------------------------------------------------------
+THE_RICH_TRB.THE_MEDIA_INTERFACE.gen_serdes_2\.THE_SERDES.PCSC_INST PCSC FF_RX_D_2_10 Out 0.000 0.000 -
+link_error[6] Net - - - - 4
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE_ns_i_o3[0] ORCALUT4 A In 0.000 0.000 -
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE_ns_i_o3[0] ORCALUT4 Z Out 0.965 0.965 -
+N_409_li Net - - - - 5
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE_ns_i_a5_1_0_0[0] ORCALUT4 D In 0.000 0.965 -
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE_ns_i_a5_1_0_0[0] ORCALUT4 Z Out 0.754 1.719 -
+CURRENT_STATE_ns_i_a5_1_0[0] Net - - - - 1
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATEc_RNO ORCALUT4 A In 0.000 1.719 -
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATEc_RNO ORCALUT4 Z Out 0.754 2.474 -
+CURRENT_STATE_ns_i_615_tz_1 Net - - - - 1
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATEc ORCALUT4 A In 0.000 2.474 -
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATEc ORCALUT4 Z Out 0.415 2.888 -
+CURRENT_STATEc Net - - - - 1
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM.CURRENT_STATE[0] FD1S3IX D In 0.000 2.888 -
+======================================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Mapper successful!
+Process took 0h:03m:41s realtime, 0h:03m:40s cputime
+# Mon Jun 14 22:12:06 2010
+
+###########################################################]
--- /dev/null
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version ispLever_v8.0_PROD_Build (41)
+Mon Jun 14 22:58:49 2010
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.
+
+Report Information
+------------------
+Command line: trce -hld -c -v 5 -o adcmv3.twr.hold adcmv3.ncd adcmv3.prf
+Design file: adcmv3.ncd
+Preference file: adcmv3.prf
+Device,speed: LFE2M100E,M
+Report level: verbose report, limited to 5 items per preference
+--------------------------------------------------------------------------------
+
+WARNING - trce: Cannot find feedback frequency for THE_SYNC_PLL/PLLDInst_0
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "clk_adc" 40.000000 MHz ;
+ 0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY NET "CLK100M_c" 100.000000 MHz ;
+ 3360 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.153ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/async_sampler_3 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/async_sampler_4 (to CLK100M_c +)
+
+ Delay: 0.141ns (74.5% logic, 25.5% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.141ns physical path delay THE_RESET_HANDLER/SLICE_8035 to THE_RESET_HANDLER/SLICE_8036 meets
+ -0.012ns M_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.012ns) by 0.153ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R46C52C.CLK to R46C52C.Q1 THE_RESET_HANDLER/SLICE_8035 (from CLK100M_c)
+ROUTE 2 0.036 R46C52C.Q1 to R46C52B.M0 THE_RESET_HANDLER/async_sampler_3 (to CLK100M_c)
+ --------
+ 0.141 (74.5% logic, 25.5% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.462ns AJ14.PADDI to R46C52C.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.462ns AJ14.PADDI to R46C52B.CLK
+
+
+Passed: The following path meets requirements by 0.212ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/async_sampler_5 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/async_sampler_6 (to CLK100M_c +)
+
+ Delay: 0.200ns (52.5% logic, 47.5% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.200ns physical path delay THE_RESET_HANDLER/SLICE_8036 to THE_RESET_HANDLER/SLICE_8037 meets
+ -0.012ns M_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.012ns) by 0.212ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R46C52B.CLK to R46C52B.Q1 THE_RESET_HANDLER/SLICE_8036 (from CLK100M_c)
+ROUTE 2 0.095 R46C52B.Q1 to R46C51C.M0 THE_RESET_HANDLER/async_sampler_5 (to CLK100M_c)
+ --------
+ 0.200 (52.5% logic, 47.5% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.462ns AJ14.PADDI to R46C52B.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.462ns AJ14.PADDI to R46C51C.CLK
+
+
+Passed: The following path meets requirements by 0.270ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_2 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_2 (to CLK100M_c +)
+
+ Delay: 0.271ns (55.0% logic, 45.0% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.271ns physical path delay THE_RESET_HANDLER/SLICE_3978 to THE_RESET_HANDLER/SLICE_3978 meets
+ 0.001ns DIN_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling 0.001ns) by 0.270ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R63C53B.CLK to R63C53B.Q1 THE_RESET_HANDLER/SLICE_3978 (from CLK100M_c)
+ROUTE 2 0.122 R63C53B.Q1 to R63C53B.C1 THE_RESET_HANDLER/reset_cnt_Q_2
+CTOF_DEL --- 0.044 R63C53B.C1 to R63C53B.F1 THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.F1 to R63C53B.DI1 THE_RESET_HANDLER/reset_cnt_s_2 (to CLK100M_c)
+ --------
+ 0.271 (55.0% logic, 45.0% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.462ns AJ14.PADDI to R63C53B.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.462ns AJ14.PADDI to R63C53B.CLK
+
+
+Passed: The following path meets requirements by 0.270ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_3 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_3 (to CLK100M_c +)
+
+ Delay: 0.271ns (55.0% logic, 45.0% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.271ns physical path delay THE_RESET_HANDLER/SLICE_3977 to THE_RESET_HANDLER/SLICE_3977 meets
+ 0.001ns DIN_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling 0.001ns) by 0.270ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R63C53C.CLK to R63C53C.Q0 THE_RESET_HANDLER/SLICE_3977 (from CLK100M_c)
+ROUTE 2 0.122 R63C53C.Q0 to R63C53C.C0 THE_RESET_HANDLER/reset_cnt_Q_3
+CTOF_DEL --- 0.044 R63C53C.C0 to R63C53C.F0 THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.F0 to R63C53C.DI0 THE_RESET_HANDLER/reset_cnt_s_3 (to CLK100M_c)
+ --------
+ 0.271 (55.0% logic, 45.0% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.462ns AJ14.PADDI to R63C53C.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.462ns AJ14.PADDI to R63C53C.CLK
+
+
+Passed: The following path meets requirements by 0.270ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_10 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_10 (to CLK100M_c +)
+
+ Delay: 0.271ns (55.0% logic, 45.0% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.271ns physical path delay THE_RESET_HANDLER/SLICE_3974 to THE_RESET_HANDLER/SLICE_3974 meets
+ 0.001ns DIN_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling 0.001ns) by 0.270ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R63C54C.CLK to R63C54C.Q1 THE_RESET_HANDLER/SLICE_3974 (from CLK100M_c)
+ROUTE 2 0.122 R63C54C.Q1 to R63C54C.C1 THE_RESET_HANDLER/reset_cnt_Q_10
+CTOF_DEL --- 0.044 R63C54C.C1 to R63C54C.F1 THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.F1 to R63C54C.DI1 THE_RESET_HANDLER/reset_cnt_s_10 (to CLK100M_c)
+ --------
+ 0.271 (55.0% logic, 45.0% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.462ns AJ14.PADDI to R63C54C.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.462ns AJ14.PADDI to R63C54C.CLK
+
+
+================================================================================
+Preference: FREQUENCY NET "clk_apv_c" 40.000000 MHz ;
+ 4096 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.107ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/wr_pointer_3 (from clk_apv_c +)
+ Destination: FF Unknown THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/RAM0 (to THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/WCK_INT +)
+
+ Delay: 0.207ns (50.7% logic, 49.3% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.207ns physical path delay THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6884 to THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4266 meets
+ 0.100ns WAD_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew less
+ 0.000ns feedback compensation requirement (totaling 0.100ns) by 0.107ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R86C35A.CLK to R86C35A.Q0 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6884 (from clk_apv_c)
+ROUTE 6 0.102 R86C35A.Q0 to R86C36B.D0 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/wr_pointer_3
+ZERO_DEL --- 0.000 R86C36B.D0 to R86C36B.WADO3 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4265
+ROUTE 1 0.000 R86C36B.WADO3 to R86C36A.WAD3 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/WAD3_INT (to THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/WCK_INT)
+ --------
+ 0.207 (50.7% logic, 49.3% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 0.506 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.518 *_R103C3.CLKOP to R86C35A.CLK clk_apv_c
+ --------
+ 1.277 (19.8% logic, 80.2% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 0.506 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.518 *_R103C3.CLKOP to R86C36B.CLK clk_apv_c
+ZERO_DEL --- 0.000 R86C36B.CLK to R86C36B.WCKO THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4265
+ROUTE 2 0.000 R86C36B.WCKO to R86C36A.WCK THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/WCK_INT
+ --------
+ 1.277 (19.8% logic, 80.2% route), 3 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.561 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 0.561 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.561 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 0.561 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 0.107ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/wr_pointer_3 (from clk_apv_c +)
+ Destination: FF Unknown THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/RAM2 (to THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WCK_INT +)
+ FF THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/RAM2
+
+ Delay: 0.207ns (50.7% logic, 49.3% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.207ns physical path delay THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6540 to THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4277 meets
+ 0.100ns WAD_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew less
+ 0.000ns feedback compensation requirement (totaling 0.100ns) by 0.107ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R99C31A.CLK to R99C31A.Q0 THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6540 (from clk_apv_c)
+ROUTE 6 0.102 R99C31A.Q0 to R99C33B.D0 THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/wr_pointer_3
+ZERO_DEL --- 0.000 R99C33B.D0 to R99C33B.WADO3 THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4275
+ROUTE 2 0.000 R99C33B.WADO3 to R99C33C.WAD3 THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WAD3_INT (to THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WCK_INT)
+ --------
+ 0.207 (50.7% logic, 49.3% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 0.506 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.518 *_R103C3.CLKOP to R99C31A.CLK clk_apv_c
+ --------
+ 1.277 (19.8% logic, 80.2% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 0.506 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.518 *_R103C3.CLKOP to R99C33B.CLK clk_apv_c
+ZERO_DEL --- 0.000 R99C33B.CLK to R99C33B.WCKO THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4275
+ROUTE 2 0.000 R99C33B.WCKO to R99C33C.WCK THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WCK_INT
+ --------
+ 1.277 (19.8% logic, 80.2% route), 3 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.561 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 0.561 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.561 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 0.561 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 0.107ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/wr_pointer_3 (from clk_apv_c +)
+ Destination: FF Unknown THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/RAM2 (to THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WCK_INT +)
+ FF THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/RAM2
+
+ Delay: 0.207ns (50.7% logic, 49.3% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.207ns physical path delay THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6884 to THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4269 meets
+ 0.100ns WAD_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew less
+ 0.000ns feedback compensation requirement (totaling 0.100ns) by 0.107ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R86C35A.CLK to R86C35A.Q0 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6884 (from clk_apv_c)
+ROUTE 6 0.102 R86C35A.Q0 to R86C37B.D0 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/wr_pointer_3
+ZERO_DEL --- 0.000 R86C37B.D0 to R86C37B.WADO3 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4267
+ROUTE 2 0.000 R86C37B.WADO3 to R86C37C.WAD3 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WAD3_INT (to THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WCK_INT)
+ --------
+ 0.207 (50.7% logic, 49.3% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 0.506 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.518 *_R103C3.CLKOP to R86C35A.CLK clk_apv_c
+ --------
+ 1.277 (19.8% logic, 80.2% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 0.506 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.518 *_R103C3.CLKOP to R86C37B.CLK clk_apv_c
+ZERO_DEL --- 0.000 R86C37B.CLK to R86C37B.WCKO THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4267
+ROUTE 2 0.000 R86C37B.WCKO to R86C37C.WCK THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WCK_INT
+ --------
+ 1.277 (19.8% logic, 80.2% route), 3 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.561 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 0.561 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.561 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 0.561 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 0.107ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/wr_pointer_3 (from clk_apv_c +)
+ Destination: FF Unknown THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/RAM0 (to THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WCK_INT +)
+ FF THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/RAM0
+
+ Delay: 0.207ns (50.7% logic, 49.3% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.207ns physical path delay THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6884 to THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4268 meets
+ 0.100ns WAD_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew less
+ 0.000ns feedback compensation requirement (totaling 0.100ns) by 0.107ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R86C35A.CLK to R86C35A.Q0 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6884 (from clk_apv_c)
+ROUTE 6 0.102 R86C35A.Q0 to R86C37B.D0 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/wr_pointer_3
+ZERO_DEL --- 0.000 R86C37B.D0 to R86C37B.WADO3 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4267
+ROUTE 2 0.000 R86C37B.WADO3 to R86C37A.WAD3 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WAD3_INT (to THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WCK_INT)
+ --------
+ 0.207 (50.7% logic, 49.3% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 0.506 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.518 *_R103C3.CLKOP to R86C35A.CLK clk_apv_c
+ --------
+ 1.277 (19.8% logic, 80.2% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 0.506 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.518 *_R103C3.CLKOP to R86C37B.CLK clk_apv_c
+ZERO_DEL --- 0.000 R86C37B.CLK to R86C37B.WCKO THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4267
+ROUTE 2 0.000 R86C37B.WCKO to R86C37A.WCK THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WCK_INT
+ --------
+ 1.277 (19.8% logic, 80.2% route), 3 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.561 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 0.561 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.561 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 0.561 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 0.107ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/wr_pointer_3 (from clk_apv_c +)
+ Destination: FF Unknown THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/RAM0 (to THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WCK_INT +)
+ FF THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/RAM0
+
+ Delay: 0.207ns (50.7% logic, 49.3% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.207ns physical path delay THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6540 to THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4276 meets
+ 0.100ns WAD_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew less
+ 0.000ns feedback compensation requirement (totaling 0.100ns) by 0.107ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R99C31A.CLK to R99C31A.Q0 THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6540 (from clk_apv_c)
+ROUTE 6 0.102 R99C31A.Q0 to R99C33B.D0 THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/wr_pointer_3
+ZERO_DEL --- 0.000 R99C33B.D0 to R99C33B.WADO3 THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4275
+ROUTE 2 0.000 R99C33B.WADO3 to R99C33A.WAD3 THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WAD3_INT (to THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WCK_INT)
+ --------
+ 0.207 (50.7% logic, 49.3% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 0.506 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.518 *_R103C3.CLKOP to R99C31A.CLK clk_apv_c
+ --------
+ 1.277 (19.8% logic, 80.2% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 0.506 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.518 *_R103C3.CLKOP to R99C33B.CLK clk_apv_c
+ZERO_DEL --- 0.000 R99C33B.CLK to R99C33B.WCKO THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4275
+ROUTE 2 0.000 R99C33B.WCKO to R99C33A.WCK THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/WCK_INT
+ --------
+ 1.277 (19.8% logic, 80.2% route), 3 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.561 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 0.561 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 0.561 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 0.561 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+================================================================================
+Preference: FREQUENCY NET "cts_clk40m" 40.000000 MHz ;
+ 1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.198ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q test_reg40m (from cts_clk40m +)
+ Destination: FF Data in test_reg40m (to cts_clk40m +)
+
+ Delay: 0.199ns (74.9% logic, 25.1% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.199ns physical path delay SLICE_11207 to SLICE_11207 meets
+ 0.001ns DIN_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling 0.001ns) by 0.198ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R53C47C.CLK to R53C47C.Q0 SLICE_11207 (from cts_clk40m)
+ROUTE 2 0.050 R53C47C.Q0 to R53C47C.D0 test_reg40m
+CTOF_DEL --- 0.044 R53C47C.D0 to R53C47C.F0 SLICE_11207
+ROUTE 1 0.000 R53C47C.F0 to R53C47C.DI0 test_reg40m_i (to cts_clk40m)
+ --------
+ 0.199 (74.9% logic, 25.1% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.518ns PLL_R103C126.CLKOP to R53C47C.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.518ns PLL_R103C126.CLKOP to R53C47C.CLK
+
+
+================================================================================
+Preference: FREQUENCY NET "sysclk_c" 100.000000 MHz ;
+ 4096 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.122ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/current_b2_buffer_10 (from sysclk_c +)
+ Destination: DP16KB Port THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/pdp_ram_0_0_0(ASIC) (to sysclk_c +)
+
+ Delay: 0.230ns (45.7% logic, 54.3% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.230ns physical path delay THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8464 to THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/pdp_ram_0_0_0 meets
+ 0.065ns DATA_HLD and
+ 0.000ns delay constraint less
+ -0.043ns skew requirement (totaling 0.108ns) by 0.122ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R66C102C.CLK to R66C102C.Q0 THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8464 (from sysclk_c)
+ROUTE 3 0.125 R66C102C.Q0 to *R67C101.DIA10 THE_RICH_TRB/THE_UNIFIED_ENDPOINT/buf_to_apl_INIT_DATA_26 (to sysclk_c)
+ --------
+ 0.230 (45.7% logic, 54.3% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.518ns DLL_R103C1.CLKOP to R66C102C.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.561ns DLL_R103C1.CLKOP to EBR_R67C101.CLKA
+
+
+Passed: The following path meets requirements by 0.122ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/current_b2_buffer_11 (from sysclk_c +)
+ Destination: DP16KB Port THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/pdp_ram_0_0_0(ASIC) (to sysclk_c +)
+
+ Delay: 0.230ns (45.7% logic, 54.3% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.230ns physical path delay THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8464 to THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/pdp_ram_0_0_0 meets
+ 0.065ns DATA_HLD and
+ 0.000ns delay constraint less
+ -0.043ns skew requirement (totaling 0.108ns) by 0.122ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R66C102C.CLK to R66C102C.Q1 THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8464 (from sysclk_c)
+ROUTE 3 0.125 R66C102C.Q1 to *R67C101.DIA11 THE_RICH_TRB/THE_UNIFIED_ENDPOINT/buf_to_apl_INIT_DATA_27 (to sysclk_c)
+ --------
+ 0.230 (45.7% logic, 54.3% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.518ns DLL_R103C1.CLKOP to R66C102C.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.561ns DLL_R103C1.CLKOP to EBR_R67C101.CLKA
+
+
+Passed: The following path meets requirements by 0.124ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/FF_4 (from sysclk_c +)
+ Destination: DP16KB Port THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0(ASIC) (to sysclk_c +)
+
+ Delay: 0.218ns (48.2% logic, 51.8% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.218ns physical path delay THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2368 to THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0 meets
+ 0.051ns ADDR_HLD and
+ 0.000ns delay constraint less
+ -0.043ns skew requirement (totaling 0.094ns) by 0.124ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R34C91B.CLK to R34C91B.Q1 THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2368 (from sysclk_c)
+ROUTE 2 0.113 R34C91B.Q1 to *_R36C89.ADB11 THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/rcount_7 (to sysclk_c)
+ --------
+ 0.218 (48.2% logic, 51.8% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.518ns DLL_R103C1.CLKOP to R34C91B.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.561ns DLL_R103C1.CLKOP to EBR_R36C89.CLKB
+
+
+Passed: The following path meets requirements by 0.124ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/FF_14 (from sysclk_c +)
+ Destination: DP16KB Port THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/pdp_ram_0_0_0(ASIC) (to sysclk_c +)
+
+ Delay: 0.218ns (48.2% logic, 51.8% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.218ns physical path delay THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_180 to THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/pdp_ram_0_0_0 meets
+ 0.051ns ADDR_HLD and
+ 0.000ns delay constraint less
+ -0.043ns skew requirement (totaling 0.094ns) by 0.124ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R47C91C.CLK to R47C91C.Q0 THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_180 (from sysclk_c)
+ROUTE 2 0.113 R47C91C.Q0 to *_R49C89.ADA12 THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/wcount_8 (to sysclk_c)
+ --------
+ 0.218 (48.2% logic, 51.8% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.518ns DLL_R103C1.CLKOP to R47C91C.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.561ns DLL_R103C1.CLKOP to EBR_R49C89.CLKA
+
+
+Passed: The following path meets requirements by 0.124ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/FF_2 (from sysclk_c +)
+ Destination: DP16KB Port THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/pdp_ram_0_0_0(ASIC) (to sysclk_c +)
+
+ Delay: 0.218ns (48.2% logic, 51.8% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.218ns physical path delay THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_221 to THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/pdp_ram_0_0_0 meets
+ 0.051ns ADDR_HLD and
+ 0.000ns delay constraint less
+ -0.043ns skew requirement (totaling 0.094ns) by 0.124ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R47C94C.CLK to R47C94C.Q1 THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_221 (from sysclk_c)
+ROUTE 2 0.113 R47C94C.Q1 to *_R49C92.ADB13 THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/rcount_9 (to sysclk_c)
+ --------
+ 0.218 (48.2% logic, 51.8% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.518ns DLL_R103C1.CLKOP to R47C94C.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.561ns DLL_R103C1.CLKOP to EBR_R49C92.CLKB
+
+
+================================================================================
+Preference: FREQUENCY NET "EXT_IN_c_3" 40.000000 MHz ;
+ 0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD PORT "ADC0_LCLK" 4.166600 nS ;
+ 1273 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.150ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_144 (from ADC0_LCLK_c +)
+ Destination: FF Unknown THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/RAM0 (to THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/WCK_INT +)
+ FF THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/RAM0
+
+ Delay: 0.250ns (42.0% logic, 58.0% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.250ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4507 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4022 meets
+ 0.100ns WAD_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling 0.100ns) by 0.150ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R71C20C.CLK to R71C20C.Q1 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4507 (from ADC0_LCLK_c)
+ROUTE 24 0.145 R71C20C.Q1 to R72C20B.D0 THE_ADC0_CROSSOVER/THE_CROSSOVER/wptr_3
+ZERO_DEL --- 0.000 R72C20B.D0 to R72C20B.WADO3 THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/SLICE_4021
+ROUTE 2 0.000 R72C20B.WADO3 to R72C20A.WAD3 THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/WAD3_INT (to THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/WCK_INT)
+ --------
+ 0.250 (42.0% logic, 58.0% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.856 T3.PADDI to R71C20C.CLK ADC0_LCLK_c
+ --------
+ 1.109 (22.8% logic, 77.2% route), 1 logic levels.
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.856 T3.PADDI to R72C20B.CLK ADC0_LCLK_c
+ZERO_DEL --- 0.000 R72C20B.CLK to R72C20B.WCKO THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/SLICE_4021
+ROUTE 2 0.000 R72C20B.WCKO to R72C20A.WCK THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/WCK_INT
+ --------
+ 1.109 (22.8% logic, 77.2% route), 2 logic levels.
+
+
+Passed: The following path meets requirements by 0.150ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_144 (from ADC0_LCLK_c +)
+ Destination: FF Unknown THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/RAM2 (to THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/WCK_INT +)
+ FF THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/RAM2
+
+ Delay: 0.250ns (42.0% logic, 58.0% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.250ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4507 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4023 meets
+ 0.100ns WAD_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling 0.100ns) by 0.150ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R71C20C.CLK to R71C20C.Q1 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4507 (from ADC0_LCLK_c)
+ROUTE 24 0.145 R71C20C.Q1 to R72C20B.D0 THE_ADC0_CROSSOVER/THE_CROSSOVER/wptr_3
+ZERO_DEL --- 0.000 R72C20B.D0 to R72C20B.WADO3 THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/SLICE_4021
+ROUTE 2 0.000 R72C20B.WADO3 to R72C20C.WAD3 THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/WAD3_INT (to THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/WCK_INT)
+ --------
+ 0.250 (42.0% logic, 58.0% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.856 T3.PADDI to R71C20C.CLK ADC0_LCLK_c
+ --------
+ 1.109 (22.8% logic, 77.2% route), 1 logic levels.
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.856 T3.PADDI to R72C20B.CLK ADC0_LCLK_c
+ZERO_DEL --- 0.000 R72C20B.CLK to R72C20B.WCKO THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/SLICE_4021
+ROUTE 2 0.000 R72C20B.WCKO to R72C20C.WCK THE_ADC0_CROSSOVER/THE_CROSSOVER/fifo_pfu_0_4/WCK_INT
+ --------
+ 1.109 (22.8% logic, 77.2% route), 2 logic levels.
+
+
+Passed: The following path meets requirements by 0.153ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_HANDLER/THE_ADC_2_3_CH/qda_1_1 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_HANDLER/THE_ADC_2_3_CH/parda_1_1 (to ADC0_LCLK_c +)
+
+ Delay: 0.141ns (74.5% logic, 25.5% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.141ns physical path delay THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4558 to THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4546 meets
+ -0.012ns M_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.012ns) by 0.153ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R75C3B.CLK to R75C3B.Q1 THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4558 (from ADC0_LCLK_c)
+ROUTE 2 0.036 R75C3B.Q1 to R75C3C.M1 THE_ADC0_HANDLER/THE_ADC_2_3_CH/qda_1_1 (to ADC0_LCLK_c)
+ --------
+ 0.141 (74.5% logic, 25.5% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.856ns T3.PADDI to R75C3B.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.856ns T3.PADDI to R75C3C.CLK
+
+
+Passed: The following path meets requirements by 0.153ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_HANDLER/THE_ADC_2_3_CH/qda_0_1 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_HANDLER/THE_ADC_2_3_CH/parda_0_1 (to ADC0_LCLK_c +)
+
+ Delay: 0.141ns (74.5% logic, 25.5% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.141ns physical path delay THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4555 to THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4543 meets
+ -0.012ns M_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.012ns) by 0.153ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R75C2B.CLK to R75C2B.Q1 THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4555 (from ADC0_LCLK_c)
+ROUTE 2 0.036 R75C2B.Q1 to R75C2C.M1 THE_ADC0_HANDLER/THE_ADC_2_3_CH/qda_0_1 (to ADC0_LCLK_c)
+ --------
+ 0.141 (74.5% logic, 25.5% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.856ns T3.PADDI to R75C2B.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.856ns T3.PADDI to R75C2C.CLK
+
+
+Passed: The following path meets requirements by 0.153ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_HANDLER/THE_ADC_2_3_CH/qdb_1_3 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_HANDLER/THE_ADC_2_3_CH/pardb_1_3 (to ADC0_LCLK_c +)
+
+ Delay: 0.141ns (74.5% logic, 25.5% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.141ns physical path delay THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4565 to THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4553 meets
+ -0.012ns M_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.012ns) by 0.153ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R74C4B.CLK to R74C4B.Q1 THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4565 (from ADC0_LCLK_c)
+ROUTE 2 0.036 R74C4B.Q1 to R74C4C.M1 THE_ADC0_HANDLER/THE_ADC_2_3_CH/qdb_1_3 (to ADC0_LCLK_c)
+ --------
+ 0.141 (74.5% logic, 25.5% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.856ns T3.PADDI to R74C4B.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.856ns T3.PADDI to R74C4C.CLK
+
+
+================================================================================
+Preference: INPUT_SETUP GROUP "ADC0_INPUT" 0.600000 ns HOLD 0.600000 ns CLKPORT "ADC0_LCLK" ;
+ 9 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.135ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC0_OUT_2
+ Destination: FF Unknown THE_ADC0_HANDLER/THE_DIN_2/ud_0 (to ADC0_LCLK_c +)
+ FF THE_ADC0_HANDLER/THE_DIN_2/ud_0
+
+ Min Data Path Delay: 0.250ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Max Clock Path Delay: 0.722ns (35.0% logic, 65.0% route), 1 logic levels.
+
+IOL_L95A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.250ns delay ADC0_OUT_2 to ADC0_OUT_2_MGIOL plus
+ 0.600ns hold offset ADC0_OUT_2 to ADC0_LCLK (totaling 0.850ns) meets
+ 0.722ns delay ADC0_LCLK to ADC0_OUT_2_MGIOL plus
+ -0.007ns DI_HLD requirement (totaling 0.715ns) by 0.135ns
+
+ Physical Path Details:
+
+ Data path ADC0_OUT_2 to ADC0_OUT_2_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.250 AB2.PAD to AB2.PADDI ADC0_OUT_2
+ROUTE 1 0.000 AB2.PADDI to IOL_L95A.DI THE_ADC0_HANDLER/THE_DIN_2/buf_Data0 (to ADC0_LCLK_c)
+ --------
+ 0.250 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC0_LCLK to ADC0_OUT_2_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.469 T3.PADDI to IOL_L95A.ECLKI ADC0_LCLK_c
+ --------
+ 0.722 (35.0% logic, 65.0% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 0.135ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC0_OUT_6
+ Destination: FF Unknown THE_ADC0_HANDLER/THE_DIN_6/ud_0 (to ADC0_LCLK_c +)
+ FF THE_ADC0_HANDLER/THE_DIN_6/ud_0
+
+ Min Data Path Delay: 0.250ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Max Clock Path Delay: 0.722ns (35.0% logic, 65.0% route), 1 logic levels.
+
+IOL_L70A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.250ns delay ADC0_OUT_6 to ADC0_OUT_6_MGIOL plus
+ 0.600ns hold offset ADC0_OUT_6 to ADC0_LCLK (totaling 0.850ns) meets
+ 0.722ns delay ADC0_LCLK to ADC0_OUT_6_MGIOL plus
+ -0.007ns DI_HLD requirement (totaling 0.715ns) by 0.135ns
+
+ Physical Path Details:
+
+ Data path ADC0_OUT_6 to ADC0_OUT_6_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.250 U3.PAD to U3.PADDI ADC0_OUT_6
+ROUTE 1 0.000 U3.PADDI to IOL_L70A.DI THE_ADC0_HANDLER/THE_DIN_6/buf_Data0 (to ADC0_LCLK_c)
+ --------
+ 0.250 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC0_LCLK to ADC0_OUT_6_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.469 T3.PADDI to IOL_L70A.ECLKI ADC0_LCLK_c
+ --------
+ 0.722 (35.0% logic, 65.0% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 0.135ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC0_OUT_0
+ Destination: FF Unknown THE_ADC0_HANDLER/THE_DIN_0/ud_0 (to ADC0_LCLK_c +)
+ FF THE_ADC0_HANDLER/THE_DIN_0/ud_0
+
+ Min Data Path Delay: 0.250ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Max Clock Path Delay: 0.722ns (35.0% logic, 65.0% route), 1 logic levels.
+
+IOL_L104A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.250ns delay ADC0_OUT_0 to ADC0_OUT_0_MGIOL plus
+ 0.600ns hold offset ADC0_OUT_0 to ADC0_LCLK (totaling 0.850ns) meets
+ 0.722ns delay ADC0_LCLK to ADC0_OUT_0_MGIOL plus
+ -0.007ns DI_HLD requirement (totaling 0.715ns) by 0.135ns
+
+ Physical Path Details:
+
+ Data path ADC0_OUT_0 to ADC0_OUT_0_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.250 AD2.PAD to AD2.PADDI ADC0_OUT_0
+ROUTE 1 0.000 AD2.PADDI to IOL_L104A.DI THE_ADC0_HANDLER/THE_DIN_0/buf_Data0 (to ADC0_LCLK_c)
+ --------
+ 0.250 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC0_LCLK to ADC0_OUT_0_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.469 T3.PADDI to *L_L104A.ECLKI ADC0_LCLK_c
+ --------
+ 0.722 (35.0% logic, 65.0% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 0.135ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC0_ADCLK
+ Destination: FF Unknown THE_ADC0_HANDLER/THE_ADC_ADCLK_IN/ud_0 (to ADC0_LCLK_c +)
+ FF THE_ADC0_HANDLER/THE_ADC_ADCLK_IN/ud_0
+
+ Min Data Path Delay: 0.250ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Max Clock Path Delay: 0.722ns (35.0% logic, 65.0% route), 1 logic levels.
+
+IOL_L61A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.250ns delay ADC0_ADCLK to ADC0_ADCLK_MGIOL plus
+ 0.600ns hold offset ADC0_ADCLK to ADC0_LCLK (totaling 0.850ns) meets
+ 0.722ns delay ADC0_LCLK to ADC0_ADCLK_MGIOL plus
+ -0.007ns DI_HLD requirement (totaling 0.715ns) by 0.135ns
+
+ Physical Path Details:
+
+ Data path ADC0_ADCLK to ADC0_ADCLK_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.250 R3.PAD to R3.PADDI ADC0_ADCLK
+ROUTE 1 0.000 R3.PADDI to IOL_L61A.DI THE_ADC0_HANDLER/THE_ADC_ADCLK_IN/buf_Data0 (to ADC0_LCLK_c)
+ --------
+ 0.250 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC0_LCLK to ADC0_ADCLK_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.469 T3.PADDI to IOL_L61A.ECLKI ADC0_LCLK_c
+ --------
+ 0.722 (35.0% logic, 65.0% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 0.135ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC0_OUT_5
+ Destination: FF Unknown THE_ADC0_HANDLER/THE_DIN_5/ud_0 (to ADC0_LCLK_c +)
+ FF THE_ADC0_HANDLER/THE_DIN_5/ud_0
+
+ Min Data Path Delay: 0.250ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Max Clock Path Delay: 0.722ns (35.0% logic, 65.0% route), 1 logic levels.
+
+IOL_L68A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.250ns delay ADC0_OUT_5 to ADC0_OUT_5_MGIOL plus
+ 0.600ns hold offset ADC0_OUT_5 to ADC0_LCLK (totaling 0.850ns) meets
+ 0.722ns delay ADC0_LCLK to ADC0_OUT_5_MGIOL plus
+ -0.007ns DI_HLD requirement (totaling 0.715ns) by 0.135ns
+
+ Physical Path Details:
+
+ Data path ADC0_OUT_5 to ADC0_OUT_5_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.250 U5.PAD to U5.PADDI ADC0_OUT_5
+ROUTE 1 0.000 U5.PADDI to IOL_L68A.DI THE_ADC0_HANDLER/THE_DIN_5/buf_Data0 (to ADC0_LCLK_c)
+ --------
+ 0.250 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC0_LCLK to ADC0_OUT_5_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.469 T3.PADDI to IOL_L68A.ECLKI ADC0_LCLK_c
+ --------
+ 0.722 (35.0% logic, 65.0% route), 1 logic levels.
+
+Report: 0.465ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: PERIOD PORT "ADC1_LCLK" 4.166600 nS ;
+ 1273 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.153ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_HANDLER/THE_ADC_4_5_CH/qdb_1_0 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_HANDLER/THE_ADC_4_5_CH/pardb_1_0 (to ADC1_LCLK_c +)
+
+ Delay: 0.141ns (74.5% logic, 25.5% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.141ns physical path delay THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4796 to THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4784 meets
+ -0.012ns M_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.012ns) by 0.153ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R48C5B.CLK to R48C5B.Q0 THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4796 (from ADC1_LCLK_c)
+ROUTE 2 0.036 R48C5B.Q0 to R48C5A.M0 THE_ADC1_HANDLER/THE_ADC_4_5_CH/qdb_1_0 (to ADC1_LCLK_c)
+ --------
+ 0.141 (74.5% logic, 25.5% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.779ns L3.PADDI to R48C5B.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.779ns L3.PADDI to R48C5A.CLK
+
+
+Passed: The following path meets requirements by 0.153ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_HANDLER/THE_ADC_6_7_CH/qda_0_5 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_HANDLER/THE_ADC_6_7_CH/parda_0_5 (to ADC1_LCLK_c +)
+
+ Delay: 0.141ns (74.5% logic, 25.5% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.141ns physical path delay THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4813 to THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4801 meets
+ -0.012ns M_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.012ns) by 0.153ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R44C2B.CLK to R44C2B.Q1 THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4813 (from ADC1_LCLK_c)
+ROUTE 1 0.036 R44C2B.Q1 to R44C2C.M1 THE_ADC1_HANDLER/THE_ADC_6_7_CH/qda_0_5 (to ADC1_LCLK_c)
+ --------
+ 0.141 (74.5% logic, 25.5% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.779ns L3.PADDI to R44C2B.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.779ns L3.PADDI to R44C2C.CLK
+
+
+Passed: The following path meets requirements by 0.153ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_HANDLER/THE_ADC_4_5_CH/qdb_1_3 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_HANDLER/THE_ADC_4_5_CH/pardb_1_3 (to ADC1_LCLK_c +)
+
+ Delay: 0.141ns (74.5% logic, 25.5% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.141ns physical path delay THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4797 to THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4785 meets
+ -0.012ns M_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.012ns) by 0.153ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R48C4B.CLK to R48C4B.Q1 THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4797 (from ADC1_LCLK_c)
+ROUTE 2 0.036 R48C4B.Q1 to R48C4C.M1 THE_ADC1_HANDLER/THE_ADC_4_5_CH/qdb_1_3 (to ADC1_LCLK_c)
+ --------
+ 0.141 (74.5% logic, 25.5% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.779ns L3.PADDI to R48C4B.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.779ns L3.PADDI to R48C4C.CLK
+
+
+Passed: The following path meets requirements by 0.153ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_HANDLER/THE_ADC_4_5_CH/qda_1_1 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_HANDLER/THE_ADC_4_5_CH/qda_1_2 (to ADC1_LCLK_c +)
+
+ Delay: 0.141ns (74.5% logic, 25.5% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.141ns physical path delay THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4790 to THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4791 meets
+ -0.012ns M_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.012ns) by 0.153ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R47C4C.CLK to R47C4C.Q1 THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4790 (from ADC1_LCLK_c)
+ROUTE 2 0.036 R47C4C.Q1 to R47C4A.M0 THE_ADC1_HANDLER/THE_ADC_4_5_CH/qda_1_1 (to ADC1_LCLK_c)
+ --------
+ 0.141 (74.5% logic, 25.5% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.779ns L3.PADDI to R47C4C.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.779ns L3.PADDI to R47C4A.CLK
+
+
+Passed: The following path meets requirements by 0.153ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_HANDLER/THE_ADC_4_5_CH/qdb_0_0 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_HANDLER/THE_ADC_4_5_CH/pardb_0_0 (to ADC1_LCLK_c +)
+
+ Delay: 0.141ns (74.5% logic, 25.5% route), 1 logic levels.
+
+ Constraint Details:
+
+ 0.141ns physical path delay THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4793 to THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4781 meets
+ -0.012ns M_HLD and
+ 0.000ns delay constraint less
+ 0.000ns skew requirement (totaling -0.012ns) by 0.153ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.105 R47C2C.CLK to R47C2C.Q0 THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4793 (from ADC1_LCLK_c)
+ROUTE 2 0.036 R47C2C.Q0 to R47C2B.M0 THE_ADC1_HANDLER/THE_ADC_4_5_CH/qdb_0_0 (to ADC1_LCLK_c)
+ --------
+ 0.141 (74.5% logic, 25.5% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 0.779ns L3.PADDI to R47C2C.CLK
+
+ Destination Clock:
+ Delay Connection
+ 0.779ns L3.PADDI to R47C2B.CLK
+
+
+================================================================================
+Preference: INPUT_SETUP GROUP "ADC1_INPUT" 0.600000 ns HOLD 0.600000 ns CLKPORT "ADC1_LCLK" ;
+ 9 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.151ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC1_OUT_2
+ Destination: FF Unknown THE_ADC1_HANDLER/THE_DIN_2/ud_0 (to ADC1_LCLK_c +)
+ FF THE_ADC1_HANDLER/THE_DIN_2/ud_0
+
+ Min Data Path Delay: 0.250ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Max Clock Path Delay: 0.706ns (35.8% logic, 64.2% route), 1 logic levels.
+
+IOL_L46A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.250ns delay ADC1_OUT_2 to ADC1_OUT_2_MGIOL plus
+ 0.600ns hold offset ADC1_OUT_2 to ADC1_LCLK (totaling 0.850ns) meets
+ 0.706ns delay ADC1_LCLK to ADC1_OUT_2_MGIOL plus
+ -0.007ns DI_HLD requirement (totaling 0.699ns) by 0.151ns
+
+ Physical Path Details:
+
+ Data path ADC1_OUT_2 to ADC1_OUT_2_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.250 N5.PAD to N5.PADDI ADC1_OUT_2
+ROUTE 1 0.000 N5.PADDI to IOL_L46A.DI THE_ADC1_HANDLER/THE_DIN_2/buf_Data0 (to ADC1_LCLK_c)
+ --------
+ 0.250 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC1_LCLK to ADC1_OUT_2_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 L3.PAD to L3.PADDI ADC1_LCLK
+ROUTE 289 0.453 L3.PADDI to IOL_L46A.ECLKI ADC1_LCLK_c
+ --------
+ 0.706 (35.8% logic, 64.2% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 0.151ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC1_OUT_3
+ Destination: FF Unknown THE_ADC1_HANDLER/THE_DIN_3/ud_0 (to ADC1_LCLK_c +)
+ FF THE_ADC1_HANDLER/THE_DIN_3/ud_0
+
+ Min Data Path Delay: 0.250ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Max Clock Path Delay: 0.706ns (35.8% logic, 64.2% route), 1 logic levels.
+
+IOL_L43A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.250ns delay ADC1_OUT_3 to ADC1_OUT_3_MGIOL plus
+ 0.600ns hold offset ADC1_OUT_3 to ADC1_LCLK (totaling 0.850ns) meets
+ 0.706ns delay ADC1_LCLK to ADC1_OUT_3_MGIOL plus
+ -0.007ns DI_HLD requirement (totaling 0.699ns) by 0.151ns
+
+ Physical Path Details:
+
+ Data path ADC1_OUT_3 to ADC1_OUT_3_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.250 K2.PAD to K2.PADDI ADC1_OUT_3
+ROUTE 1 0.000 K2.PADDI to IOL_L43A.DI THE_ADC1_HANDLER/THE_DIN_3/buf_Data0 (to ADC1_LCLK_c)
+ --------
+ 0.250 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC1_LCLK to ADC1_OUT_3_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 L3.PAD to L3.PADDI ADC1_LCLK
+ROUTE 289 0.453 L3.PADDI to IOL_L43A.ECLKI ADC1_LCLK_c
+ --------
+ 0.706 (35.8% logic, 64.2% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 0.151ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC1_OUT_0
+ Destination: FF Unknown THE_ADC1_HANDLER/THE_DIN_0/ud_0 (to ADC1_LCLK_c +)
+ FF THE_ADC1_HANDLER/THE_DIN_0/ud_0
+
+ Min Data Path Delay: 0.250ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Max Clock Path Delay: 0.706ns (35.8% logic, 64.2% route), 1 logic levels.
+
+IOL_L56A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.250ns delay ADC1_OUT_0 to ADC1_OUT_0_MGIOL plus
+ 0.600ns hold offset ADC1_OUT_0 to ADC1_LCLK (totaling 0.850ns) meets
+ 0.706ns delay ADC1_LCLK to ADC1_OUT_0_MGIOL plus
+ -0.007ns DI_HLD requirement (totaling 0.699ns) by 0.151ns
+
+ Physical Path Details:
+
+ Data path ADC1_OUT_0 to ADC1_OUT_0_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.250 P3.PAD to P3.PADDI ADC1_OUT_0
+ROUTE 1 0.000 P3.PADDI to IOL_L56A.DI THE_ADC1_HANDLER/THE_DIN_0/buf_Data0 (to ADC1_LCLK_c)
+ --------
+ 0.250 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC1_LCLK to ADC1_OUT_0_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 L3.PAD to L3.PADDI ADC1_LCLK
+ROUTE 289 0.453 L3.PADDI to IOL_L56A.ECLKI ADC1_LCLK_c
+ --------
+ 0.706 (35.8% logic, 64.2% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 0.151ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC1_OUT_4
+ Destination: FF Unknown THE_ADC1_HANDLER/THE_DIN_4/ud_0 (to ADC1_LCLK_c +)
+ FF THE_ADC1_HANDLER/THE_DIN_4/ud_0
+
+ Min Data Path Delay: 0.250ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Max Clock Path Delay: 0.706ns (35.8% logic, 64.2% route), 1 logic levels.
+
+IOL_L34A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.250ns delay ADC1_OUT_4 to ADC1_OUT_4_MGIOL plus
+ 0.600ns hold offset ADC1_OUT_4 to ADC1_LCLK (totaling 0.850ns) meets
+ 0.706ns delay ADC1_LCLK to ADC1_OUT_4_MGIOL plus
+ -0.007ns DI_HLD requirement (totaling 0.699ns) by 0.151ns
+
+ Physical Path Details:
+
+ Data path ADC1_OUT_4 to ADC1_OUT_4_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.250 J3.PAD to J3.PADDI ADC1_OUT_4
+ROUTE 1 0.000 J3.PADDI to IOL_L34A.DI THE_ADC1_HANDLER/THE_DIN_4/buf_Data0 (to ADC1_LCLK_c)
+ --------
+ 0.250 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC1_LCLK to ADC1_OUT_4_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 L3.PAD to L3.PADDI ADC1_LCLK
+ROUTE 289 0.453 L3.PADDI to IOL_L34A.ECLKI ADC1_LCLK_c
+ --------
+ 0.706 (35.8% logic, 64.2% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 0.151ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC1_OUT_6
+ Destination: FF Unknown THE_ADC1_HANDLER/THE_DIN_6/ud_0 (to ADC1_LCLK_c +)
+ FF THE_ADC1_HANDLER/THE_DIN_6/ud_0
+
+ Min Data Path Delay: 0.250ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Max Clock Path Delay: 0.706ns (35.8% logic, 64.2% route), 1 logic levels.
+
+IOL_L28A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.250ns delay ADC1_OUT_6 to ADC1_OUT_6_MGIOL plus
+ 0.600ns hold offset ADC1_OUT_6 to ADC1_LCLK (totaling 0.850ns) meets
+ 0.706ns delay ADC1_LCLK to ADC1_OUT_6_MGIOL plus
+ -0.007ns DI_HLD requirement (totaling 0.699ns) by 0.151ns
+
+ Physical Path Details:
+
+ Data path ADC1_OUT_6 to ADC1_OUT_6_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.250 G2.PAD to G2.PADDI ADC1_OUT_6
+ROUTE 1 0.000 G2.PADDI to IOL_L28A.DI THE_ADC1_HANDLER/THE_DIN_6/buf_Data0 (to ADC1_LCLK_c)
+ --------
+ 0.250 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC1_LCLK to ADC1_OUT_6_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.253 L3.PAD to L3.PADDI ADC1_LCLK
+ROUTE 289 0.453 L3.PADDI to IOL_L28A.ECLKI ADC1_LCLK_c
+ --------
+ 0.706 (35.8% logic, 64.2% route), 1 logic levels.
+
+Report: 0.449ns is the minimum offset for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays) | Constraint| Actual|Levels
+----------------------------------------------------------------------------
+ | | |
+FREQUENCY NET "clk_adc" 40.000000 MHz ; | -| -| 0
+ | | |
+FREQUENCY NET "CLK100M_c" 100.000000 | | |
+MHz ; | -| -| 1
+ | | |
+FREQUENCY NET "clk_apv_c" 40.000000 MHz | | |
+; | -| -| 2
+ | | |
+FREQUENCY NET "cts_clk40m" 40.000000 | | |
+MHz ; | -| -| 2
+ | | |
+FREQUENCY NET "sysclk_c" 100.000000 MHz | | |
+; | -| -| 1
+ | | |
+FREQUENCY NET "EXT_IN_c_3" 40.000000 | | |
+MHz ; | -| -| 0
+ | | |
+PERIOD PORT "ADC0_LCLK" 4.166600 nS ; | -| -| 2
+ | | |
+INPUT_SETUP GROUP "ADC0_INPUT" 0.600000 | | |
+ns HOLD 0.600000 ns CLKPORT "ADC0_LCLK" | | |
+; | 0.600 ns| 0.465 ns| 1
+ | | |
+PERIOD PORT "ADC1_LCLK" 4.166600 nS ; | -| -| 1
+ | | |
+INPUT_SETUP GROUP "ADC1_INPUT" 0.600000 | | |
+ns HOLD 0.600000 ns CLKPORT "ADC1_LCLK" | | |
+; | 0.600 ns| 0.449 ns| 1
+ | | |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 13 clocks:
+
+Clock Domain: GND Source: SLICE_14065.F0 Loads: 114
+ No transfer within this clock domain is found
+
+Clock Domain: clk_adc Source: THE_40M_PLL/PLLDInst_0.CLKOS Loads: 2
+ No transfer within this clock domain is found
+
+Clock Domain: CLK100M_c Source: CLK100M.PAD Loads: 21
+ Covered under: FREQUENCY NET "CLK100M_c" 100.000000 MHz ;
+
+ Data transfers from:
+ Clock Domain: sysclk_c Source: THE_100M_DLL/dll_100m_0_0.CLKOP
+ Covered under: FREQUENCY NET "CLK100M_c" 100.000000 MHz ; Transfers: 2
+
+Clock Domain: clk_apv_c Source: THE_40M_PLL/PLLDInst_0.CLKOP Loads: 2043
+ Covered under: FREQUENCY NET "clk_apv_c" 40.000000 MHz ;
+
+ Data transfers from:
+ Clock Domain: sysclk_c Source: THE_100M_DLL/dll_100m_0_0.CLKOP
+ Covered under: FREQUENCY NET "clk_apv_c" 40.000000 MHz ; Transfers: 148
+
+ Clock Domain: ADC0_LCLK_c Source: ADC0_LCLK.PAD
+ Not reported because source and destination domains are unrelated.
+
+ Clock Domain: ADC1_LCLK_c Source: ADC1_LCLK.PAD
+ Not reported because source and destination domains are unrelated.
+
+Clock Domain: cts_clk40m Source: THE_SYNC_PLL/PLLDInst_0.CLKOP Loads: 1
+ Covered under: FREQUENCY NET "cts_clk40m" 40.000000 MHz ;
+
+Clock Domain: sysclk_c Source: THE_100M_DLL/dll_100m_0_0.CLKOP Loads: 7152
+ Covered under: FREQUENCY NET "sysclk_c" 100.000000 MHz ;
+
+ Data transfers from:
+ Clock Domain: CLK100M_c Source: CLK100M.PAD
+ Covered under: FREQUENCY NET "sysclk_c" 100.000000 MHz ; Transfers: 1
+
+ Clock Domain: clk_apv_c Source: THE_40M_PLL/PLLDInst_0.CLKOP
+ Covered under: FREQUENCY NET "sysclk_c" 100.000000 MHz ; Transfers: 335
+
+ Clock Domain: cts_clk40m Source: THE_SYNC_PLL/PLLDInst_0.CLKOP
+ Not reported because source and destination domains are unrelated.
+
+ Clock Domain: ADC0_LCLK_c Source: ADC0_LCLK.PAD
+ Not reported because source and destination domains are unrelated.
+
+ Clock Domain: ADC1_LCLK_c Source: ADC1_LCLK.PAD
+ Not reported because source and destination domains are unrelated.
+
+Clock Domain: THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/ff_txfullclk Source: THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/PCSC_INST.FF_TX_F_CLK Loads: 1
+ No transfer within this clock domain is found
+
+Clock Domain: EXT_IN_c_3 Source: EXT_IN_3.PAD Loads: 2
+ No transfer within this clock domain is found
+
+Clock Domain: ADC0_LCLK_c Source: ADC0_LCLK.PAD Loads: 289
+ Covered under: PERIOD PORT "ADC0_LCLK" 4.166600 nS ;
+
+ Data transfers from:
+ Clock Domain: clk_apv_c Source: THE_40M_PLL/PLLDInst_0.CLKOP
+ Not reported because source and destination domains are unrelated.
+
+ Clock Domain: sysclk_c Source: THE_100M_DLL/dll_100m_0_0.CLKOP
+ Not reported because source and destination domains are unrelated.
+
+Clock Domain: ADC1_LCLK_c Source: ADC1_LCLK.PAD Loads: 289
+ Covered under: PERIOD PORT "ADC1_LCLK" 4.166600 nS ;
+
+ Data transfers from:
+ Clock Domain: clk_apv_c Source: THE_40M_PLL/PLLDInst_0.CLKOP
+ Not reported because source and destination domains are unrelated.
+
+ Clock Domain: sysclk_c Source: THE_100M_DLL/dll_100m_0_0.CLKOP
+ Not reported because source and destination domains are unrelated.
+
+Clock Domain: E5ADCS10_THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/ff_txfullclk Source: E5ADCS10.DCSOUT Loads: 1
+ No transfer within this clock domain is found
+
+Clock Domain: E5ADCS01_clk_adc Source: E5ADCS01.DCSOUT Loads: 1
+ No transfer within this clock domain is found
+
+Clock Domain: E5ADCS21_clk_adc Source: E5ADCS21.DCSOUT Loads: 1
+ No transfer within this clock domain is found
+
+
+--------------------------------------------------------------------------------
+ Connections not covered by the preferences
+--------------------------------------------------------------------------------
+
+ Delay Element Net
+
+ 0.453ns PLL/PLLDInst_0.CLKOS to E5ADCS01.CLK0 clk_adc
+ 0.453ns PLL/PLLDInst_0.CLKOS to E5ADCS21.CLK0 clk_adc
+ 0.000ns ADC1_CLK_MGIOL.IOLDO to ADC1_CLK.IOLDO ADC1_CLK_c
+ 1.823ns _SLIM/SLICE_10627.Q0 to APV0_SDA.PADDT apv_sda_out
+ 1.806ns _SLIM/SLICE_10627.Q0 to APV1_SDA.PADDT apv_sda_out
+ 1.823ns APV0_SDA.PADDI to C_SLIM/SLICE_9428.C0 APV0_SDA_in
+ 1.702ns APV0_SDA.PADDI to START/SLICE_13025.D0 APV0_SDA_in
+ 0.000ns PV0A_CLK_MGIOL.IOLDO to APV0A_CLK.IOLDO APV0A_CLK_c
+ 0.385ns SLICE_11207.Q0 to L_REG/SLICE_10364.M1 test_reg40m
+ 0.000ns ADC0_CS_MGIOL.IOLDO to ADC0_CS.IOLDO ADC0_CS_c
+ 0.000ns ADC0_SCK_MGIOL.IOLDO to ADC0_SCK.IOLDO ADC0_SCK_c
+ 0.000ns EXT_IN_0.PADDI to EXT_IN_0_MGIOL.DI EXT_IN_c_0
+ 0.000ns C_REBOOT_MGIOL.IOLDO to UC_REBOOT.IOLDO UC_REBOOT_c
+ 0.000ns APV0_1W_0.PADDI to APV0_1W_0_MGIOL.DI APV0_1W_in_0
+ 0.064ns MASTER/SLICE_9644.Q0 to MASTER/SLICE_9644.D0 THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/strong_pullup_Q
+ 0.411ns ASTER/SLICE_11101.Q0 to MASTER/SLICE_9644.B0 output
+ 1.446ns ASTER/SLICE_11101.Q0 to APV1_1W_7.PADDO output
+ 1.614ns ASTER/SLICE_11101.Q0 to APV1_1W_6.PADDO output
+ 1.558ns ASTER/SLICE_11101.Q0 to APV1_1W_5.PADDO output
+ 1.948ns ASTER/SLICE_11101.Q0 to APV1_1W_4.PADDO output
+ 1.893ns ASTER/SLICE_11101.Q0 to APV1_1W_3.PADDO output
+ 1.513ns ASTER/SLICE_11101.Q0 to APV1_1W_2.PADDO output
+ 1.972ns ASTER/SLICE_11101.Q0 to APV1_1W_1.PADDO output
+ 1.457ns ASTER/SLICE_11101.Q0 to APV1_1W_0.PADDO output
+ 1.936ns ASTER/SLICE_11101.Q0 to APV0_1W_7.PADDO output
+ 2.018ns ASTER/SLICE_11101.Q0 to APV0_1W_6.PADDO output
+ 2.024ns ASTER/SLICE_11101.Q0 to APV0_1W_5.PADDO output
+ 2.021ns ASTER/SLICE_11101.Q0 to APV0_1W_4.PADDO output
+ 1.992ns ASTER/SLICE_11101.Q0 to APV0_1W_3.PADDO output
+ 2.366ns ASTER/SLICE_11101.Q0 to APV0_1W_2.PADDO output
+ 2.077ns ASTER/SLICE_11101.Q0 to APV0_1W_1.PADDO output
+ 2.021ns ASTER/SLICE_11101.Q0 to APV0_1W_0.PADDO output
+ 1.233ns ASTER/SLICE_11101.Q0 to BP_ONEWIRE.PADDO output
+ 1.351ns MASTER/SLICE_9644.F0 to APV1_1W_7.PADDT IO_GEN_0_un8_onewire
+ 1.328ns MASTER/SLICE_9644.F0 to APV1_1W_6.PADDT IO_GEN_0_un8_onewire
+ 1.328ns MASTER/SLICE_9644.F0 to APV1_1W_5.PADDT IO_GEN_0_un8_onewire
+ 1.600ns MASTER/SLICE_9644.F0 to APV1_1W_4.PADDT IO_GEN_0_un8_onewire
+ 1.600ns MASTER/SLICE_9644.F0 to APV1_1W_3.PADDT IO_GEN_0_un8_onewire
+ 1.333ns MASTER/SLICE_9644.F0 to APV1_1W_2.PADDT IO_GEN_0_un8_onewire
+ 1.674ns MASTER/SLICE_9644.F0 to APV1_1W_1.PADDT IO_GEN_0_un8_onewire
+ 1.333ns MASTER/SLICE_9644.F0 to APV1_1W_0.PADDT IO_GEN_0_un8_onewire
+ 1.899ns MASTER/SLICE_9644.F0 to APV0_1W_7.PADDT IO_GEN_0_un8_onewire
+ 1.794ns MASTER/SLICE_9644.F0 to APV0_1W_6.PADDT IO_GEN_0_un8_onewire
+ 1.981ns MASTER/SLICE_9644.F0 to APV0_1W_5.PADDT IO_GEN_0_un8_onewire
+ 1.978ns MASTER/SLICE_9644.F0 to APV0_1W_4.PADDT IO_GEN_0_un8_onewire
+ 1.899ns MASTER/SLICE_9644.F0 to APV0_1W_3.PADDT IO_GEN_0_un8_onewire
+ 2.157ns MASTER/SLICE_9644.F0 to APV0_1W_2.PADDT IO_GEN_0_un8_onewire
+ 1.984ns MASTER/SLICE_9644.F0 to APV0_1W_1.PADDT IO_GEN_0_un8_onewire
+ 1.984ns MASTER/SLICE_9644.F0 to APV0_1W_0.PADDT IO_GEN_0_un8_onewire
+ 1.501ns MASTER/SLICE_9644.F0 to BP_ONEWIRE.PADDT IO_GEN_0_un8_onewire
+ 1.180ns NDLER/SLICE_10479.Q0 to L_REG/SLICE_10365.M0 adc0_swap
+ 0.649ns NDLER/SLICE_10497.Q0 to L_REG/SLICE_10365.M1 adc1_swap
+ 1.194ns NDLER/SLICE_10492.Q0 to SSOVER/SLICE_4509.B0 adc0_valid
+ 1.201ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6373.C0 adc0_valid
+ 1.160ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6380.D0 adc0_valid
+ 1.387ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6381.B0 adc0_valid
+ 1.201ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6382.C1 adc0_valid
+ 1.245ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6384.D0 adc0_valid
+ 1.342ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6389.C0 adc0_valid
+ 1.245ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6392.D0 adc0_valid
+ 0.997ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6459.B0 adc0_valid
+ 0.997ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6466.B0 adc0_valid
+ 0.997ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6467.B0 adc0_valid
+ 0.997ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6468.B1 adc0_valid
+ 0.805ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6470.A0 adc0_valid
+ 0.890ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6475.A0 adc0_valid
+ 0.782ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6478.C0 adc0_valid
+ 0.741ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6545.D0 adc0_valid
+ 0.992ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6551.B1 adc0_valid
+ 0.741ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6552.D0 adc0_valid
+ 0.741ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6553.D0 adc0_valid
+ 0.741ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6554.D1 adc0_valid
+ 0.997ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6556.B0 adc0_valid
+ 0.826ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6561.D0 adc0_valid
+ 0.997ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6564.B0 adc0_valid
+ 0.418ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6631.B0 adc0_valid
+ 0.498ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6637.B1 adc0_valid
+ 0.458ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6638.C0 adc0_valid
+ 0.418ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6639.B0 adc0_valid
+ 0.452ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6640.A1 adc0_valid
+ 0.429ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6642.C0 adc0_valid
+ 0.332ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6647.D0 adc0_valid
+ 0.396ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6650.A0 adc0_valid
+ 1.641ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6717.C0 adc0_valid
+ 1.805ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6724.A0 adc0_valid
+ 1.641ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6725.C0 adc0_valid
+ 1.599ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6726.D1 adc0_valid
+ 1.547ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6728.A0 adc0_valid
+ 1.514ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6733.D0 adc0_valid
+ 1.426ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6736.D0 adc0_valid
+ 0.498ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6803.B0 adc0_valid
+ 0.498ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6809.B1 adc0_valid
+ 0.631ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6810.D0 adc0_valid
+ 0.498ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6811.B0 adc0_valid
+ 0.498ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6812.B1 adc0_valid
+ 0.561ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6814.A0 adc0_valid
+ 0.583ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6819.B0 adc0_valid
+ 0.538ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6822.C0 adc0_valid
+ 0.623ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6889.C0 adc0_valid
+ 0.775ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6895.A1 adc0_valid
+ 0.581ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6896.D0 adc0_valid
+ 0.637ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6897.D0 adc0_valid
+ 0.693ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6898.A1 adc0_valid
+ 0.708ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6900.C0 adc0_valid
+ 0.666ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6905.D0 adc0_valid
+ 0.708ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6908.C0 adc0_valid
+ 0.916ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6975.C0 adc0_valid
+ 1.096ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6981.B1 adc0_valid
+ 0.916ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6982.C0 adc0_valid
+ 0.874ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6983.D0 adc0_valid
+ 0.930ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6984.D1 adc0_valid
+ 0.939ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6986.A0 adc0_valid
+ 1.012ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6991.A0 adc0_valid
+ 0.910ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6994.C0 adc0_valid
+ 1.496ns NDLER/SLICE_10492.Q0 to ASTER/SLICE_10275.M0 adc0_valid
+ 1.569ns NDLER/SLICE_10492.Q0 to L_REG/SLICE_10366.M0 adc0_valid
+ 0.065ns NDLER/SLICE_10492.Q0 to NDLER/SLICE_10492.D0 adc0_valid
+ 1.491ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12238.M0 adc0_valid
+ 1.236ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12243.M0 adc0_valid
+ 0.806ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12247.M0 adc0_valid
+ 0.383ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12251.M0 adc0_valid
+ 0.646ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12256.M0 adc0_valid
+ 1.225ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12260.M0 adc0_valid
+ 0.976ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12264.M0 adc0_valid
+ 1.022ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12268.M0 adc0_valid
+ 1.685ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13541.D0 adc0_valid
+ 1.241ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13548.B0 adc0_valid
+ 0.827ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13555.B0 adc0_valid
+ 0.559ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13563.B0 adc0_valid
+ 0.583ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13571.B0 adc0_valid
+ 1.187ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13578.C0 adc0_valid
+ 0.997ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13587.B0 adc0_valid
+ 0.702ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13596.C0 adc0_valid
+ 0.974ns NDLER/SLICE_10510.Q0 to SSOVER/SLICE_4717.C0 adc1_valid
+ 0.691ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7061.B0 adc1_valid
+ 0.816ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7067.A1 adc1_valid
+ 0.805ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7068.C0 adc1_valid
+ 0.838ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7069.B0 adc1_valid
+ 0.756ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7070.B1 adc1_valid
+ 0.711ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7072.C0 adc1_valid
+ 0.591ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7077.D0 adc1_valid
+ 0.682ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7080.C0 adc1_valid
+ 0.769ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7147.D0 adc1_valid
+ 1.048ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7153.A1 adc1_valid
+ 0.825ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7154.D0 adc1_valid
+ 0.862ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7155.B0 adc1_valid
+ 0.776ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7156.B1 adc1_valid
+ 1.042ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7158.A0 adc1_valid
+ 0.941ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7163.B0 adc1_valid
+ 1.033ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7166.D0 adc1_valid
+ 1.338ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7233.A0 adc1_valid
+ 1.371ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7239.C1 adc1_valid
+ 1.360ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7240.B0 adc1_valid
+ 1.338ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7241.A0 adc1_valid
+ 1.360ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7242.B1 adc1_valid
+ 1.175ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7244.C0 adc1_valid
+ 1.255ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7249.C0 adc1_valid
+ 1.175ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7252.C0 adc1_valid
+ 0.684ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7319.D0 adc1_valid
+ 0.785ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7325.B1 adc1_valid
+ 0.699ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7326.D0 adc1_valid
+ 0.740ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7327.C0 adc1_valid
+ 0.785ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7328.B1 adc1_valid
+ 0.605ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7330.D0 adc1_valid
+ 0.744ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7335.C0 adc1_valid
+ 0.605ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7338.D0 adc1_valid
+ 1.197ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7405.C0 adc1_valid
+ 1.321ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7411.B1 adc1_valid
+ 1.197ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7412.C0 adc1_valid
+ 1.155ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7413.D0 adc1_valid
+ 1.155ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7414.D1 adc1_valid
+ 1.197ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7416.C0 adc1_valid
+ 1.197ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7421.C0 adc1_valid
+ 1.197ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7424.C0 adc1_valid
+ 0.879ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7491.B0 adc1_valid
+ 0.964ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7497.B1 adc1_valid
+ 0.879ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7498.B0 adc1_valid
+ 0.857ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7499.A0 adc1_valid
+ 0.879ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7500.B1 adc1_valid
+ 1.049ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7502.B0 adc1_valid
+ 1.014ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7507.B0 adc1_valid
+ 1.018ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7510.D0 adc1_valid
+ 1.018ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7577.A0 adc1_valid
+ 1.098ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7583.A1 adc1_valid
+ 1.040ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7584.B0 adc1_valid
+ 1.018ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7585.A0 adc1_valid
+ 1.098ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7586.A1 adc1_valid
+ 1.116ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7588.C0 adc1_valid
+ 1.136ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7593.C0 adc1_valid
+ 0.954ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7596.D0 adc1_valid
+ 0.591ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7663.D0 adc1_valid
+ 0.733ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7669.B1 adc1_valid
+ 0.742ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7670.B0 adc1_valid
+ 0.762ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7671.B0 adc1_valid
+ 0.773ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7672.C1 adc1_valid
+ 0.591ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7674.A0 adc1_valid
+ 0.688ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7679.C0 adc1_valid
+ 0.568ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7682.C0 adc1_valid
+ 0.972ns NDLER/SLICE_10510.Q0 to ASTER/SLICE_10284.M0 adc1_valid
+ 1.119ns NDLER/SLICE_10510.Q0 to L_REG/SLICE_10366.M1 adc1_valid
+ 0.065ns NDLER/SLICE_10510.Q0 to NDLER/SLICE_10510.D0 adc1_valid
+ 0.582ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12205.M0 adc1_valid
+ 1.436ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12209.M0 adc1_valid
+ 0.937ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12213.M0 adc1_valid
+ 0.846ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12217.M0 adc1_valid
+ 1.286ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12221.M0 adc1_valid
+ 1.110ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12225.M0 adc1_valid
+ 0.568ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12229.M0 adc1_valid
+ 0.676ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12233.M0 adc1_valid
+ 0.811ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13435.C0 adc1_valid
+ 1.531ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13445.B0 adc1_valid
+ 1.128ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13453.B0 adc1_valid
+ 0.839ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13461.A0 adc1_valid
+ 1.276ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13469.C0 adc1_valid
+ 1.103ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13478.A0 adc1_valid
+ 0.842ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13486.B0 adc1_valid
+ 0.599ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13495.D0 adc1_valid
+ 0.065ns SLICE_10526.Q0 to SLICE_10526.D0 adc_ctrl_reg_9_0
+ 0.207ns SLICE_10526.Q1 to SLICE_10526.C0 adc_ctrl_reg_9_1
+ 0.065ns SLICE_10525.Q0 to SLICE_10525.D0 adc_ctrl_reg_8_0
+ 0.247ns SLICE_10525.Q1 to SLICE_10525.B0 adc_ctrl_reg_8_1
+ 0.065ns SLICE_10524.Q0 to SLICE_10524.D0 adc_ctrl_reg_7_0
+ 0.247ns SLICE_10524.Q1 to SLICE_10524.B0 adc_ctrl_reg_7_1
+ 0.065ns SLICE_10523.Q0 to SLICE_10523.D0 adc_ctrl_reg_6_0
+ 0.230ns SLICE_10523.Q1 to SLICE_10523.A0 adc_ctrl_reg_6_1
+ 0.065ns SLICE_10522.Q0 to SLICE_10522.D0 adc_ctrl_reg_5_0
+ 0.204ns SLICE_10522.Q1 to SLICE_10522.B0 adc_ctrl_reg_5_1
+ 0.247ns SLICE_10521.Q0 to SLICE_10521.B0 adc_ctrl_reg_4_0
+ 0.160ns SLICE_10521.Q1 to SLICE_10521.D0 adc_ctrl_reg_4_1
+ 0.204ns SLICE_10520.Q0 to SLICE_10520.B0 adc_ctrl_reg_3_0
+ 0.160ns SLICE_10520.Q1 to SLICE_10520.D0 adc_ctrl_reg_3_1
+ 0.065ns SLICE_10519.Q0 to SLICE_10519.D0 adc_ctrl_reg_2_0
+ 0.204ns SLICE_10519.Q1 to SLICE_10519.B0 adc_ctrl_reg_2_1
+ 0.065ns SLICE_10518.Q0 to SLICE_10518.D0 adc_ctrl_reg_1_0
+ 0.065ns SLICE_10517.Q0 to SLICE_10517.D0 adc_ctrl_reg_15_0
+ 0.247ns SLICE_10517.Q1 to SLICE_10517.B0 adc_ctrl_reg_15_1
+ 0.247ns SLICE_10518.Q1 to SLICE_10518.B0 adc_ctrl_reg_1_1
+ 0.225ns SLICE_10516.Q1 to SLICE_10516.A0 adc_ctrl_reg_14_1
+ 0.065ns SLICE_10516.Q0 to SLICE_10516.D0 adc_ctrl_reg_14_0
+ 0.247ns SLICE_10515.Q1 to SLICE_10515.B0 adc_ctrl_reg_13_1
+ 0.065ns SLICE_10515.Q0 to SLICE_10515.D0 adc_ctrl_reg_13_0
+ 0.065ns SLICE_10514.Q0 to SLICE_10514.D0 adc_ctrl_reg_12_0
+ 0.247ns SLICE_10514.Q1 to SLICE_10514.B0 adc_ctrl_reg_12_1
+ 0.065ns SLICE_10513.Q0 to SLICE_10513.D0 adc_ctrl_reg_11_0
+ 0.247ns SLICE_10513.Q1 to SLICE_10513.B0 adc_ctrl_reg_11_1
+ 0.202ns SLICE_10512.Q0 to SLICE_10512.C0 adc_ctrl_reg_10_0
+ 0.160ns SLICE_10512.Q1 to SLICE_10512.D0 adc_ctrl_reg_10_1
+ 0.065ns SLICE_10511.Q0 to SLICE_10511.D0 adc_ctrl_reg_0_0
+ 0.230ns SLICE_10511.Q1 to SLICE_10511.A0 adc_ctrl_reg_0_1
+ 0.065ns ASTER/SLICE_10053.Q0 to ASTER/SLICE_10053.D0 THE_SLAVE_BUS/THE_SPI_ADC1_MASTER/adc_ctrl_data_0
+ 0.930ns MASTER/SLICE_4355.Q0 to ADC1_PD.PADDO ADC1_PD_c
+ 0.676ns ASTER/SLICE_10624.Q0 to SLICE_11033.B1 apv1_reset
+ 1.313ns ASTER/SLICE_10053.F0 to ADC1_RST.PADDO THE_SLAVE_BUS_THE_SPI_ADC1_MASTER_adc_ctrl_data_i_0
+ 0.065ns ASTER/SLICE_10021.Q0 to ASTER/SLICE_10021.D0 THE_SLAVE_BUS/THE_SPI_ADC0_MASTER/adc_ctrl_data_0
+ 1.351ns MASTER/SLICE_4354.Q0 to ADC0_PD.PADDO ADC0_PD_c
+ 0.950ns ASTER/SLICE_10623.Q0 to SLICE_11033.C1 apv0_reset
+ 1.813ns ASTER/SLICE_10021.F0 to ADC0_RST.PADDO THE_SLAVE_BUS_THE_SPI_ADC0_MASTER_adc_ctrl_data_i_0
+ 2.031ns APV0_SCL.PADDI to GSTART/SLICE_9406.D0 APV0_SCL_in
+ 2.158ns APV0_SCL.PADDI to GSTART/SLICE_9454.C1 APV0_SCL_in
+ 2.158ns APV0_SCL.PADDI to START/SLICE_13024.C0 APV0_SCL_in
+ 1.302ns APV1_SCL.PADDI to GSTART/SLICE_9406.C0 APV1_SCL_in
+ 1.346ns APV1_SCL.PADDI to GSTART/SLICE_9454.D1 APV1_SCL_in
+ 1.346ns APV1_SCL.PADDI to START/SLICE_13024.D0 APV1_SCL_in
+ 0.513ns START/SLICE_13024.F0 to GSTART/SLICE_9409.A0 THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/THE_I2C_GSTART/apv_scl_in
+ 0.107ns START/SLICE_13024.F0 to GSTART/SLICE_9455.C0 THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/THE_I2C_GSTART/apv_scl_in
+ 1.641ns APV1_SDA.PADDI to C_SLIM/SLICE_9428.B0 APV1_SDA_in
+ 1.833ns APV1_SDA.PADDI to START/SLICE_13025.A0 APV1_SDA_in
+ 0.446ns C_SLIM/SLICE_9428.F0 to GSTART/SLICE_9406.A0 THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/apv_sda_in
+ 0.001ns C_SLIM/SLICE_9428.F0 to _SLIM/SLICE_9428.DI0 THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/apv_sda_in
+ 0.215ns C_SLIM/SLICE_9428.F0 to C_SLIM/SLICE_9449.M0 THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/apv_sda_in
+ 0.384ns C_SLIM/SLICE_9428.F0 to GSTART/SLICE_9454.A1 THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/apv_sda_in
+ 0.375ns C_SLIM/SLICE_9428.F0 to GSTART/SLICE_9455.D0 THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/apv_sda_in
+ 1.375ns _SLIM/SLICE_10626.Q0 to APV1_SCL.PADDT apv_scl_out
+ 2.365ns _SLIM/SLICE_10626.Q0 to APV0_SCL.PADDT apv_scl_out
+ 0.612ns rface/SLICE_11230.Q0 to ADCM_ONEWIRE.PADDT un1_THE_UNIFIED_ENDPOINT_2_2
+ 0.556ns rface/SLICE_11230.Q0 to ADCM_ONEWIRE.PADDO un1_THE_UNIFIED_ENDPOINT_2_2
+ 0.552ns ADCM_ONEWIRE.PADDI to erface/SLICE_9111.C0 ADCM_ONEWIRE_in
+ 0.568ns FP_LSM/SLICE_4486.Q0 to SD_TXDIS.PADDO SD_TXDIS_c
+ 0.395ns FP_LSM/SLICE_8165.Q0 to P_LSM/SLICE_12923.C0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_1
+ 0.395ns FP_LSM/SLICE_8165.Q0 to P_LSM/SLICE_12923.C1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_1
+ 0.395ns FP_LSM/SLICE_8165.Q0 to P_LSM/SLICE_12924.C0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_1
+ 0.395ns FP_LSM/SLICE_8165.Q0 to P_LSM/SLICE_12924.C1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_1
+ 0.233ns FP_LSM/SLICE_8166.Q0 to led_4/SLICE_11783.M0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_3
+ 0.469ns FP_LSM/SLICE_8166.Q0 to P_LSM/SLICE_12923.B0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_3
+ 0.469ns FP_LSM/SLICE_8166.Q0 to P_LSM/SLICE_12923.B1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_3
+ 0.383ns FP_LSM/SLICE_8166.Q0 to P_LSM/SLICE_12924.D0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_3
+ 0.383ns FP_LSM/SLICE_8166.Q0 to P_LSM/SLICE_12924.D1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_3
+ 0.300ns FP_LSM/SLICE_8164.Q0 to led_4/SLICE_11783.C1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_0
+ 0.300ns FP_LSM/SLICE_8164.Q0 to led_u/SLICE_11784.C1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_0
+ 0.400ns FP_LSM/SLICE_8164.Q0 to P_LSM/SLICE_12923.D0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_0
+ 0.400ns FP_LSM/SLICE_8164.Q0 to P_LSM/SLICE_12923.D1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_0
+ 0.486ns FP_LSM/SLICE_8164.Q0 to P_LSM/SLICE_12924.B0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_0
+ 0.486ns FP_LSM/SLICE_8164.Q0 to P_LSM/SLICE_12924.B1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_0
+ 0.306ns FP_LSM/SLICE_8165.Q1 to led_4/SLICE_11783.C0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_2
+ 0.306ns FP_LSM/SLICE_8165.Q1 to led_u/SLICE_11784.C0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_2
+ 0.329ns FP_LSM/SLICE_8165.Q1 to led_u/SLICE_11784.A1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_2
+ 0.329ns FP_LSM/SLICE_8165.Q1 to P_LSM/SLICE_12923.A0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_2
+ 0.329ns FP_LSM/SLICE_8165.Q1 to P_LSM/SLICE_12923.A1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_2
+ 0.329ns FP_LSM/SLICE_8165.Q1 to P_LSM/SLICE_12924.A0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_2
+ 0.329ns FP_LSM/SLICE_8165.Q1 to P_LSM/SLICE_12924.A1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_2
+ 0.834ns P_LSM/SLICE_12923.F0 to FPGA_LED_3.PADDO FPGA_LED_c_3
+ 0.483ns P_LSM/SLICE_12923.F1 to FPGA_LED_6.PADDO FPGA_LED_c_6
+ 0.538ns P_LSM/SLICE_12924.F1 to FPGA_LED_4.PADDO FPGA_LED_c_4
+ 0.301ns P_LSM/SLICE_13366.F0 to led_u/SLICE_11784.M0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/N_345_li
+ 0.273ns SFP_LSM/SLICE_572.Q1 to led_u/SLICE_11784.D0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_22
+ 0.144ns SFP_LSM/SLICE_571.Q0 to led_4/SLICE_11783.D0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_23
+ 0.144ns SFP_LSM/SLICE_571.Q0 to led_4/SLICE_11783.D1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_23
+ 0.144ns SFP_LSM/SLICE_571.Q0 to led_u/SLICE_11784.D1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_23
+ 0.230ns SFP_LSM/SLICE_571.Q1 to led_4/SLICE_11783.B0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_24
+ 0.230ns SFP_LSM/SLICE_571.Q1 to led_4/SLICE_11783.B1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_24
+ 0.230ns SFP_LSM/SLICE_571.Q1 to led_u/SLICE_11784.B1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_24
+ 0.264ns SFP_LSM/SLICE_570.Q0 to led_4/SLICE_11783.A0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_25
+ 0.264ns SFP_LSM/SLICE_570.Q0 to led_4/SLICE_11783.A1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_25
+ 0.378ns P_LSM/SLICE_13364.F0 to led_u/SLICE_11784.B0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/N_413_i
+ 0.538ns P_LSM/SLICE_12924.F0 to FPGA_LED_5.PADDO FPGA_LED_c_5
+ 0.224ns d_4/SLICE_11783.OFX0 to led_u/SLICE_11784.A0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/N_453
+ 0.224ns d_u/SLICE_11784.OFX0 to P_LSM/SLICE_13370.A0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/med_stat_op_9
+ 0.682ns P_LSM/SLICE_13370.F0 to FPGA_LED_LINK.PADDO THE_RICH_TRB_med_stat_op_i_9
+ 0.326ns SD_PRESENT.PADDI to S_SYNC/SLICE_8173.M0 SD_PRESENT_c
+ 0.326ns SD_LOS.PADDI to S_SYNC/SLICE_8173.M1 SD_LOS_c
+ 0.541ns ERFACE/SLICE_4356.Q0 to FPGA_LED_RXD.PADDO FPGA_LED_RXD_c
+ 0.661ns RFACE/SLICE_12688.Q0 to FPGA_LED_TXD.PADDO FPGA_LED_TXD_c
+ 2.387ns RFACE/SLICE_11206.Q0 to T_SYNC/SLICE_4615.M0 reset_by_trb
+ 1.982ns RFACE/SLICE_11206.Q0 to T_SYNC/SLICE_4823.M0 reset_by_trb
+ 1.806ns EXT_IN_3.PADDI to 3_SYNC/SLICE_5058.M0 EXT_IN_c_3
+ 0.000ns EXT_IN_3.PADDI to _PLL/PLLDInst_0.CLKI EXT_IN_c_3
+ 0.249ns E_SYNC/SLICE_4511.Q0 to SSOVER/SLICE_659.LSR THE_ADC0_CROSSOVER/reset
+ 0.249ns E_SYNC/SLICE_4511.Q0 to SSOVER/SLICE_660.LSR THE_ADC0_CROSSOVER/reset
+ 0.247ns E_SYNC/SLICE_4511.Q0 to SSOVER/SLICE_661.LSR THE_ADC0_CROSSOVER/reset
+ 0.247ns E_SYNC/SLICE_4511.Q0 to SSOVER/SLICE_672.LSR THE_ADC0_CROSSOVER/reset
+ 0.332ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4490.LSR THE_ADC0_CROSSOVER/reset
+ 0.334ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4491.LSR THE_ADC0_CROSSOVER/reset
+ 0.332ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4492.LSR THE_ADC0_CROSSOVER/reset
+ 0.334ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4493.LSR THE_ADC0_CROSSOVER/reset
+ 0.334ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4494.LSR THE_ADC0_CROSSOVER/reset
+ 0.513ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4498.LSR THE_ADC0_CROSSOVER/reset
+ 0.428ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4499.LSR THE_ADC0_CROSSOVER/reset
+ 0.513ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4500.LSR THE_ADC0_CROSSOVER/reset
+ 0.337ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4506.LSR THE_ADC0_CROSSOVER/reset
+ 0.428ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4507.LSR THE_ADC0_CROSSOVER/reset
+ 0.247ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4508.LSR THE_ADC0_CROSSOVER/reset
+ 0.300ns SSOVER/SLICE_4498.Q0 to SSOVER/SLICE_4501.M0 THE_ADC0_CROSSOVER/THE_CROSSOVER/w_gcount_0
+ 0.221ns SSOVER/SLICE_4498.Q1 to SSOVER/SLICE_4501.M1 THE_ADC0_CROSSOVER/THE_CROSSOVER/w_gcount_1
+ 0.221ns SSOVER/SLICE_4499.Q0 to SSOVER/SLICE_4502.M0 THE_ADC0_CROSSOVER/THE_CROSSOVER/w_gcount_2
+ 0.225ns SSOVER/SLICE_4499.Q1 to SSOVER/SLICE_4502.M1 THE_ADC0_CROSSOVER/THE_CROSSOVER/w_gcount_3
+ 0.300ns SSOVER/SLICE_4500.Q0 to SSOVER/SLICE_4503.M0 THE_ADC0_CROSSOVER/THE_CROSSOVER/w_gcount_4
+ 0.221ns SSOVER/SLICE_4487.Q0 to SSOVER/SLICE_4490.M0 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_0
+ 0.380ns SSOVER/SLICE_4487.Q1 to SSOVER/SLICE_4490.M1 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_1
+ 0.305ns SSOVER/SLICE_4488.Q0 to SSOVER/SLICE_4491.M0 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_2
+ 0.221ns SSOVER/SLICE_4488.Q1 to SSOVER/SLICE_4491.M1 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_3
+ 0.129ns SSOVER/SLICE_4489.Q0 to SSOVER/SLICE_4492.M0 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_4
+ 0.546ns NDLER/SLICE_10492.F0 to FPGA_LED_ADC_0.PADDO adc0_valid_i
+ 0.297ns E_SYNC/SLICE_4719.Q0 to SSOVER/SLICE_685.LSR THE_ADC1_CROSSOVER/reset
+ 0.297ns E_SYNC/SLICE_4719.Q0 to SSOVER/SLICE_686.LSR THE_ADC1_CROSSOVER/reset
+ 0.481ns E_SYNC/SLICE_4719.Q0 to SSOVER/SLICE_687.LSR THE_ADC1_CROSSOVER/reset
+ 0.375ns E_SYNC/SLICE_4719.Q0 to SSOVER/SLICE_697.LSR THE_ADC1_CROSSOVER/reset
+ 0.371ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4698.LSR THE_ADC1_CROSSOVER/reset
+ 0.292ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4699.LSR THE_ADC1_CROSSOVER/reset
+ 0.385ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4700.LSR THE_ADC1_CROSSOVER/reset
+ 0.460ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4701.LSR THE_ADC1_CROSSOVER/reset
+ 0.460ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4702.LSR THE_ADC1_CROSSOVER/reset
+ 0.377ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4706.LSR THE_ADC1_CROSSOVER/reset
+ 0.566ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4707.LSR THE_ADC1_CROSSOVER/reset
+ 0.566ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4708.LSR THE_ADC1_CROSSOVER/reset
+ 0.481ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4714.LSR THE_ADC1_CROSSOVER/reset
+ 0.377ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4715.LSR THE_ADC1_CROSSOVER/reset
+ 0.460ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4716.LSR THE_ADC1_CROSSOVER/reset
+ 0.053ns SSOVER/SLICE_4706.Q0 to SSOVER/SLICE_4709.M0 THE_ADC1_CROSSOVER/THE_CROSSOVER/w_gcount_0
+ 0.384ns SSOVER/SLICE_4706.Q1 to SSOVER/SLICE_4709.M1 THE_ADC1_CROSSOVER/THE_CROSSOVER/w_gcount_1
+ 0.053ns SSOVER/SLICE_4707.Q0 to SSOVER/SLICE_4710.M0 THE_ADC1_CROSSOVER/THE_CROSSOVER/w_gcount_2
+ 0.053ns SSOVER/SLICE_4707.Q1 to SSOVER/SLICE_4710.M1 THE_ADC1_CROSSOVER/THE_CROSSOVER/w_gcount_3
+ 0.225ns SSOVER/SLICE_4708.Q0 to SSOVER/SLICE_4711.M0 THE_ADC1_CROSSOVER/THE_CROSSOVER/w_gcount_4
+ 0.300ns SSOVER/SLICE_4695.Q0 to SSOVER/SLICE_4698.M0 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_0
+ 0.310ns SSOVER/SLICE_4695.Q1 to SSOVER/SLICE_4698.M1 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_1
+ 0.221ns SSOVER/SLICE_4696.Q0 to SSOVER/SLICE_4699.M0 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_2
+ 0.300ns SSOVER/SLICE_4696.Q1 to SSOVER/SLICE_4699.M1 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_3
+ 0.244ns SSOVER/SLICE_4697.Q0 to SSOVER/SLICE_4700.M0 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_4
+ 0.897ns NDLER/SLICE_10510.F0 to FPGA_LED_ADC_1.PADDO adc1_valid_i
+ 0.160ns SLICE_11033.Q0 to SLICE_11033.D1 frontend_reset
+ 0.000ns /PLLDInst_0.CLKINTFB to PLL/PLLDInst_0.CLKFB THE_SYNC_PLL/CLKFB_t
+ 0.000ns ANDLER/SLICE_8034.F0 to NDLER/SLICE_8034.DI0 THE_RESET_HANDLER/comb_async_rst
+ 1.390ns UC_RESET.PADDI to ANDLER/SLICE_8034.D0 UC_RESET_c
+ 0.000ns APV1_1W_1.PADDI to APV1_1W_1_MGIOL.DI APV1_1W_in_1
+ 0.000ns APV1_1W_0.PADDI to APV1_1W_0_MGIOL.DI APV1_1W_in_0
+ 0.000ns APV0_1W_7.PADDI to APV0_1W_7_MGIOL.DI APV0_1W_in_7
+ 0.000ns APV0_1W_6.PADDI to APV0_1W_6_MGIOL.DI APV0_1W_in_6
+ 0.000ns APV0_1W_5.PADDI to APV0_1W_5_MGIOL.DI APV0_1W_in_5
+ 0.000ns APV0_1W_4.PADDI to APV0_1W_4_MGIOL.DI APV0_1W_in_4
+ 0.000ns APV0_1W_3.PADDI to APV0_1W_3_MGIOL.DI APV0_1W_in_3
+ 0.000ns APV0_1W_2.PADDI to APV0_1W_2_MGIOL.DI APV0_1W_in_2
+ 0.000ns BP_ONEWIRE.PADDI to BP_ONEWIRE_MGIOL.DI BP_ONEWIRE_in
+ 0.000ns APV1_1W_7.PADDI to APV1_1W_7_MGIOL.DI APV1_1W_in_7
+ 0.000ns APV1_1W_6.PADDI to APV1_1W_6_MGIOL.DI APV1_1W_in_6
+ 0.000ns APV1_1W_3.PADDI to APV1_1W_3_MGIOL.DI APV1_1W_in_3
+ 0.000ns APV0_1W_1.PADDI to APV0_1W_1_MGIOL.DI APV0_1W_in_1
+ 0.000ns APV1_1W_5.PADDI to APV1_1W_5_MGIOL.DI APV1_1W_in_5
+ 0.000ns APV1_1W_4.PADDI to APV1_1W_4_MGIOL.DI APV1_1W_in_4
+ 0.000ns APV1_1W_2.PADDI to APV1_1W_2_MGIOL.DI APV1_1W_in_2
+ 0.000ns U_SPI_SDO.PADDI to U_SPI_SDO_MGIOL.DI U_SPI_SDO_c
+ 0.000ns EXT_IN_2.PADDI to EXT_IN_2_MGIOL.DI EXT_IN_c_2
+ 0.000ns EXT_IN_1.PADDI to EXT_IN_1_MGIOL.DI EXT_IN_c_1
+ 0.000ns _SPI_SDI_MGIOL.IOLDO to U_SPI_SDI.IOLDO U_SPI_SDI_c
+ 0.000ns _SPI_SCK_MGIOL.IOLDO to U_SPI_SCK.IOLDO U_SPI_SCK_c
+ 0.000ns U_SPI_CS_MGIOL.IOLDO to U_SPI_CS.IOLDO U_SPI_CS_c
+ 0.000ns ADC1_SDI_MGIOL.IOLDO to ADC1_SDI.IOLDO ADC1_SDI_c
+ 0.000ns ADC1_SCK_MGIOL.IOLDO to ADC1_SCK.IOLDO ADC1_SCK_c
+ 0.000ns ADC1_CS_MGIOL.IOLDO to ADC1_CS.IOLDO ADC1_CS_c
+ 0.000ns ADC0_SDI_MGIOL.IOLDO to ADC0_SDI.IOLDO ADC0_SDI_c
+ 0.000ns SLICE_10636.F0 to SLICE_10636.DI0 BP_SECTOR_c_i_0
+ 0.000ns SLICE_10636.F1 to SLICE_10636.DI1 BP_SECTOR_c_i_1
+ 0.000ns SLICE_10637.F0 to SLICE_10637.DI0 BP_SECTOR_c_i_2
+ 0.000ns SLICE_10632.F0 to SLICE_10632.DI0 BP_MODULE_c_i_0
+ 0.000ns SLICE_10632.F1 to SLICE_10632.DI1 BP_MODULE_c_i_1
+ 0.000ns SLICE_10633.F0 to SLICE_10633.DI0 BP_MODULE_c_i_2
+ 0.495ns BP_SECTOR_2.PADDI to SLICE_10637.D0 BP_SECTOR_c_2
+ 0.495ns BP_SECTOR_1.PADDI to SLICE_10636.A1 BP_SECTOR_c_1
+ 0.376ns BP_SECTOR_0.PADDI to SLICE_10636.C0 BP_SECTOR_c_0
+ 1.132ns BP_MODULE_2.PADDI to SLICE_10633.B0 BP_MODULE_c_2
+ 0.977ns BP_MODULE_1.PADDI to SLICE_10632.C1 BP_MODULE_c_1
+ 0.903ns BP_MODULE_0.PADDI to SLICE_10632.A0 BP_MODULE_c_0
+ 0.000ns ADC0_CLK_MGIOL.IOLDO to ADC0_CLK.IOLDO ADC0_CLK_c
+ 1.525ns SLICE_10526.F0 to ENB_LVDS_7.PADDO N_1999_i
+ 1.512ns SLICE_10516.F0 to ENB_LVDS_6.PADDO N_2000_i
+ 1.527ns SLICE_10525.F0 to ENB_LVDS_5.PADDO N_2001_i
+ 1.290ns SLICE_10517.F0 to ENB_LVDS_4.PADDO N_2002_i
+ 1.632ns SLICE_10513.F0 to ENB_LVDS_3.PADDO N_2003_i
+ 1.401ns SLICE_10514.F0 to ENB_LVDS_2.PADDO N_2004_i
+ 1.548ns SLICE_10512.F0 to ENB_LVDS_1.PADDO N_2005_i
+ 1.389ns SLICE_10515.F0 to ENB_LVDS_0.PADDO N_2006_i
+ 0.982ns SLICE_11033.F1 to APV1_RST.PADDO APV0_RST_c
+ 1.759ns SLICE_11033.F1 to APV0_RST.PADDO APV0_RST_c
+ 0.000ns PV1B_TRG_MGIOL.IOLDO to APV1B_TRG.IOLDO APV1B_TRG_c
+ 0.000ns PV1A_TRG_MGIOL.IOLDO to APV1A_TRG.IOLDO APV1A_TRG_c
+ 0.000ns PV1B_CLK_MGIOL.IOLDO to APV1B_CLK.IOLDO APV1B_CLK_c
+ 0.000ns PV1A_CLK_MGIOL.IOLDO to APV1A_CLK.IOLDO APV1A_CLK_c
+ 1.361ns SLICE_10511.F0 to ENA_LVDS_7.PADDO N_2007_i
+ 1.305ns SLICE_10524.F0 to ENA_LVDS_6.PADDO N_2008_i
+ 1.273ns SLICE_10518.F0 to ENA_LVDS_5.PADDO N_2009_i
+ 1.226ns SLICE_10523.F0 to ENA_LVDS_4.PADDO N_2010_i
+ 1.454ns SLICE_10519.F0 to ENA_LVDS_3.PADDO N_2011_i
+ 1.373ns SLICE_10522.F0 to ENA_LVDS_2.PADDO N_2012_i
+ 1.515ns SLICE_10520.F0 to ENA_LVDS_1.PADDO N_2013_i
+ 1.445ns SLICE_10521.F0 to ENA_LVDS_0.PADDO N_2014_i
+ 0.000ns PV0B_TRG_MGIOL.IOLDO to APV0B_TRG.IOLDO APV0B_TRG_c
+ 0.000ns PV0A_TRG_MGIOL.IOLDO to APV0A_TRG.IOLDO APV0A_TRG_c
+ 0.000ns PV0B_CLK_MGIOL.IOLDO to APV0B_CLK.IOLDO APV0B_CLK_c
+
+--------------------------------------------------------------------------------
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0 Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 270407 paths, 138 nets, and 98840 connections (99.6% coverage)
+
+--------------------------------------------------------------------------------
+
--- /dev/null
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version ispLever_v8.0_PROD_Build (41)
+Mon Jun 14 22:58:22 2010
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.
+
+Report Information
+------------------
+Command line: trce -c -v 15 -o adcmv3.twr.setup adcmv3.ncd adcmv3.prf
+Design file: adcmv3.ncd
+Preference file: adcmv3.prf
+Device,speed: LFE2M100E,6
+Report level: verbose report, limited to 15 items per preference
+--------------------------------------------------------------------------------
+
+WARNING - trce: Cannot find feedback frequency for THE_SYNC_PLL/PLLDInst_0
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "clk_adc" 40.000000 MHz ;
+ 0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: FREQUENCY NET "CLK100M_c" 100.000000 MHz ;
+ 3360 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 4.832ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_14 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_15 (to CLK100M_c +)
+
+ Delay: 5.097ns (42.2% logic, 57.8% route), 13 logic levels.
+
+ Constraint Details:
+
+ 5.097ns physical path delay THE_RESET_HANDLER/SLICE_3972 to THE_RESET_HANDLER/SLICE_3971 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.929ns) by 4.832ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R63C55B.CLK to R63C55B.Q1 THE_RESET_HANDLER/SLICE_3972 (from CLK100M_c)
+ROUTE 2 0.670 R63C55B.Q1 to R63C55D.B0 THE_RESET_HANDLER/reset_cnt_14
+CTOF_DEL --- 0.198 R63C55D.B0 to R63C55D.F0 THE_RESET_HANDLER/SLICE_14053
+ROUTE 1 0.747 R63C55D.F0 to R62C54A.C0 THE_RESET_HANDLER/un6_reset_cnt_10
+CTOF_DEL --- 0.198 R62C54A.C0 to R62C54A.F0 THE_RESET_HANDLER/SLICE_12748
+ROUTE 2 0.670 R62C54A.F0 to R62C55B.B0 THE_RESET_HANDLER/un6_reset_cnt
+CTOF_DEL --- 0.198 R62C55B.B0 to R62C55B.F0 THE_RESET_HANDLER/SLICE_8041
+ROUTE 17 0.858 R62C55B.F0 to R63C53A.B0 THE_RESET_HANDLER/reset_cnt
+C0TOFCO_DE --- 0.440 R63C53A.B0 to R63C53A.FCO THE_RESET_HANDLER/SLICE_3970
+ROUTE 1 0.000 R63C53A.FCO to R63C53B.FCI THE_RESET_HANDLER/reset_cnt_cry_0
+FCITOFCO_D --- 0.081 R63C53B.FCI to R63C53B.FCO THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.FCO to R63C53C.FCI THE_RESET_HANDLER/reset_cnt_cry_2
+FCITOFCO_D --- 0.081 R63C53C.FCI to R63C53C.FCO THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.FCO to R63C54A.FCI THE_RESET_HANDLER/reset_cnt_cry_4
+FCITOFCO_D --- 0.081 R63C54A.FCI to R63C54A.FCO THE_RESET_HANDLER/SLICE_3976
+ROUTE 1 0.000 R63C54A.FCO to R63C54B.FCI THE_RESET_HANDLER/reset_cnt_cry_6
+FCITOFCO_D --- 0.081 R63C54B.FCI to R63C54B.FCO THE_RESET_HANDLER/SLICE_3975
+ROUTE 1 0.000 R63C54B.FCO to R63C54C.FCI THE_RESET_HANDLER/reset_cnt_cry_8
+FCITOFCO_D --- 0.081 R63C54C.FCI to R63C54C.FCO THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.FCO to R63C55A.FCI THE_RESET_HANDLER/reset_cnt_cry_10
+FCITOFCO_D --- 0.081 R63C55A.FCI to R63C55A.FCO THE_RESET_HANDLER/SLICE_3973
+ROUTE 1 0.000 R63C55A.FCO to R63C55B.FCI THE_RESET_HANDLER/reset_cnt_cry_12
+FCITOFCO_D --- 0.081 R63C55B.FCI to R63C55B.FCO THE_RESET_HANDLER/SLICE_3972
+ROUTE 1 0.000 R63C55B.FCO to R63C55C.FCI THE_RESET_HANDLER/reset_cnt_cry_14
+FCITOF0_DE --- 0.242 R63C55C.FCI to R63C55C.F0 THE_RESET_HANDLER/SLICE_3971
+ROUTE 1 0.000 R63C55C.F0 to R63C55C.DI0 THE_RESET_HANDLER/reset_cnt_s_15 (to CLK100M_c)
+ --------
+ 5.097 (42.2% logic, 57.8% route), 13 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55C.CLK
+
+
+Passed: The following path meets requirements by 4.842ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_14 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_14 (to CLK100M_c +)
+
+ Delay: 5.087ns (42.1% logic, 57.9% route), 12 logic levels.
+
+ Constraint Details:
+
+ 5.087ns physical path delay THE_RESET_HANDLER/SLICE_3972 to THE_RESET_HANDLER/SLICE_3972 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.929ns) by 4.842ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R63C55B.CLK to R63C55B.Q1 THE_RESET_HANDLER/SLICE_3972 (from CLK100M_c)
+ROUTE 2 0.670 R63C55B.Q1 to R63C55D.B0 THE_RESET_HANDLER/reset_cnt_14
+CTOF_DEL --- 0.198 R63C55D.B0 to R63C55D.F0 THE_RESET_HANDLER/SLICE_14053
+ROUTE 1 0.747 R63C55D.F0 to R62C54A.C0 THE_RESET_HANDLER/un6_reset_cnt_10
+CTOF_DEL --- 0.198 R62C54A.C0 to R62C54A.F0 THE_RESET_HANDLER/SLICE_12748
+ROUTE 2 0.670 R62C54A.F0 to R62C55B.B0 THE_RESET_HANDLER/un6_reset_cnt
+CTOF_DEL --- 0.198 R62C55B.B0 to R62C55B.F0 THE_RESET_HANDLER/SLICE_8041
+ROUTE 17 0.858 R62C55B.F0 to R63C53A.B0 THE_RESET_HANDLER/reset_cnt
+C0TOFCO_DE --- 0.440 R63C53A.B0 to R63C53A.FCO THE_RESET_HANDLER/SLICE_3970
+ROUTE 1 0.000 R63C53A.FCO to R63C53B.FCI THE_RESET_HANDLER/reset_cnt_cry_0
+FCITOFCO_D --- 0.081 R63C53B.FCI to R63C53B.FCO THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.FCO to R63C53C.FCI THE_RESET_HANDLER/reset_cnt_cry_2
+FCITOFCO_D --- 0.081 R63C53C.FCI to R63C53C.FCO THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.FCO to R63C54A.FCI THE_RESET_HANDLER/reset_cnt_cry_4
+FCITOFCO_D --- 0.081 R63C54A.FCI to R63C54A.FCO THE_RESET_HANDLER/SLICE_3976
+ROUTE 1 0.000 R63C54A.FCO to R63C54B.FCI THE_RESET_HANDLER/reset_cnt_cry_6
+FCITOFCO_D --- 0.081 R63C54B.FCI to R63C54B.FCO THE_RESET_HANDLER/SLICE_3975
+ROUTE 1 0.000 R63C54B.FCO to R63C54C.FCI THE_RESET_HANDLER/reset_cnt_cry_8
+FCITOFCO_D --- 0.081 R63C54C.FCI to R63C54C.FCO THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.FCO to R63C55A.FCI THE_RESET_HANDLER/reset_cnt_cry_10
+FCITOFCO_D --- 0.081 R63C55A.FCI to R63C55A.FCO THE_RESET_HANDLER/SLICE_3973
+ROUTE 1 0.000 R63C55A.FCO to R63C55B.FCI THE_RESET_HANDLER/reset_cnt_cry_12
+FCITOF1_DE --- 0.313 R63C55B.FCI to R63C55B.F1 THE_RESET_HANDLER/SLICE_3972
+ROUTE 1 0.000 R63C55B.F1 to R63C55B.DI1 THE_RESET_HANDLER/reset_cnt_s_14 (to CLK100M_c)
+ --------
+ 5.087 (42.1% logic, 57.9% route), 12 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+
+Passed: The following path meets requirements by 4.897ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_13 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_15 (to CLK100M_c +)
+
+ Delay: 5.032ns (42.8% logic, 57.2% route), 13 logic levels.
+
+ Constraint Details:
+
+ 5.032ns physical path delay THE_RESET_HANDLER/SLICE_3972 to THE_RESET_HANDLER/SLICE_3971 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.929ns) by 4.897ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R63C55B.CLK to R63C55B.Q0 THE_RESET_HANDLER/SLICE_3972 (from CLK100M_c)
+ROUTE 2 0.605 R63C55B.Q0 to R63C55D.A0 THE_RESET_HANDLER/reset_cnt_13
+CTOF_DEL --- 0.198 R63C55D.A0 to R63C55D.F0 THE_RESET_HANDLER/SLICE_14053
+ROUTE 1 0.747 R63C55D.F0 to R62C54A.C0 THE_RESET_HANDLER/un6_reset_cnt_10
+CTOF_DEL --- 0.198 R62C54A.C0 to R62C54A.F0 THE_RESET_HANDLER/SLICE_12748
+ROUTE 2 0.670 R62C54A.F0 to R62C55B.B0 THE_RESET_HANDLER/un6_reset_cnt
+CTOF_DEL --- 0.198 R62C55B.B0 to R62C55B.F0 THE_RESET_HANDLER/SLICE_8041
+ROUTE 17 0.858 R62C55B.F0 to R63C53A.B0 THE_RESET_HANDLER/reset_cnt
+C0TOFCO_DE --- 0.440 R63C53A.B0 to R63C53A.FCO THE_RESET_HANDLER/SLICE_3970
+ROUTE 1 0.000 R63C53A.FCO to R63C53B.FCI THE_RESET_HANDLER/reset_cnt_cry_0
+FCITOFCO_D --- 0.081 R63C53B.FCI to R63C53B.FCO THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.FCO to R63C53C.FCI THE_RESET_HANDLER/reset_cnt_cry_2
+FCITOFCO_D --- 0.081 R63C53C.FCI to R63C53C.FCO THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.FCO to R63C54A.FCI THE_RESET_HANDLER/reset_cnt_cry_4
+FCITOFCO_D --- 0.081 R63C54A.FCI to R63C54A.FCO THE_RESET_HANDLER/SLICE_3976
+ROUTE 1 0.000 R63C54A.FCO to R63C54B.FCI THE_RESET_HANDLER/reset_cnt_cry_6
+FCITOFCO_D --- 0.081 R63C54B.FCI to R63C54B.FCO THE_RESET_HANDLER/SLICE_3975
+ROUTE 1 0.000 R63C54B.FCO to R63C54C.FCI THE_RESET_HANDLER/reset_cnt_cry_8
+FCITOFCO_D --- 0.081 R63C54C.FCI to R63C54C.FCO THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.FCO to R63C55A.FCI THE_RESET_HANDLER/reset_cnt_cry_10
+FCITOFCO_D --- 0.081 R63C55A.FCI to R63C55A.FCO THE_RESET_HANDLER/SLICE_3973
+ROUTE 1 0.000 R63C55A.FCO to R63C55B.FCI THE_RESET_HANDLER/reset_cnt_cry_12
+FCITOFCO_D --- 0.081 R63C55B.FCI to R63C55B.FCO THE_RESET_HANDLER/SLICE_3972
+ROUTE 1 0.000 R63C55B.FCO to R63C55C.FCI THE_RESET_HANDLER/reset_cnt_cry_14
+FCITOF0_DE --- 0.242 R63C55C.FCI to R63C55C.F0 THE_RESET_HANDLER/SLICE_3971
+ROUTE 1 0.000 R63C55C.F0 to R63C55C.DI0 THE_RESET_HANDLER/reset_cnt_s_15 (to CLK100M_c)
+ --------
+ 5.032 (42.8% logic, 57.2% route), 13 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55C.CLK
+
+
+Passed: The following path meets requirements by 4.903ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_14 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_15 (to CLK100M_c +)
+
+ Delay: 5.026ns (41.4% logic, 58.6% route), 13 logic levels.
+
+ Constraint Details:
+
+ 5.026ns physical path delay THE_RESET_HANDLER/SLICE_3972 to THE_RESET_HANDLER/SLICE_3971 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.929ns) by 4.903ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R63C55B.CLK to R63C55B.Q1 THE_RESET_HANDLER/SLICE_3972 (from CLK100M_c)
+ROUTE 2 0.670 R63C55B.Q1 to R63C55D.B0 THE_RESET_HANDLER/reset_cnt_14
+CTOF_DEL --- 0.198 R63C55D.B0 to R63C55D.F0 THE_RESET_HANDLER/SLICE_14053
+ROUTE 1 0.747 R63C55D.F0 to R62C54A.C0 THE_RESET_HANDLER/un6_reset_cnt_10
+CTOF_DEL --- 0.198 R62C54A.C0 to R62C54A.F0 THE_RESET_HANDLER/SLICE_12748
+ROUTE 2 0.670 R62C54A.F0 to R62C55B.B0 THE_RESET_HANDLER/un6_reset_cnt
+CTOF_DEL --- 0.198 R62C55B.B0 to R62C55B.F0 THE_RESET_HANDLER/SLICE_8041
+ROUTE 17 0.858 R62C55B.F0 to R63C53A.B1 THE_RESET_HANDLER/reset_cnt
+C1TOFCO_DE --- 0.369 R63C53A.B1 to R63C53A.FCO THE_RESET_HANDLER/SLICE_3970
+ROUTE 1 0.000 R63C53A.FCO to R63C53B.FCI THE_RESET_HANDLER/reset_cnt_cry_0
+FCITOFCO_D --- 0.081 R63C53B.FCI to R63C53B.FCO THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.FCO to R63C53C.FCI THE_RESET_HANDLER/reset_cnt_cry_2
+FCITOFCO_D --- 0.081 R63C53C.FCI to R63C53C.FCO THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.FCO to R63C54A.FCI THE_RESET_HANDLER/reset_cnt_cry_4
+FCITOFCO_D --- 0.081 R63C54A.FCI to R63C54A.FCO THE_RESET_HANDLER/SLICE_3976
+ROUTE 1 0.000 R63C54A.FCO to R63C54B.FCI THE_RESET_HANDLER/reset_cnt_cry_6
+FCITOFCO_D --- 0.081 R63C54B.FCI to R63C54B.FCO THE_RESET_HANDLER/SLICE_3975
+ROUTE 1 0.000 R63C54B.FCO to R63C54C.FCI THE_RESET_HANDLER/reset_cnt_cry_8
+FCITOFCO_D --- 0.081 R63C54C.FCI to R63C54C.FCO THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.FCO to R63C55A.FCI THE_RESET_HANDLER/reset_cnt_cry_10
+FCITOFCO_D --- 0.081 R63C55A.FCI to R63C55A.FCO THE_RESET_HANDLER/SLICE_3973
+ROUTE 1 0.000 R63C55A.FCO to R63C55B.FCI THE_RESET_HANDLER/reset_cnt_cry_12
+FCITOFCO_D --- 0.081 R63C55B.FCI to R63C55B.FCO THE_RESET_HANDLER/SLICE_3972
+ROUTE 1 0.000 R63C55B.FCO to R63C55C.FCI THE_RESET_HANDLER/reset_cnt_cry_14
+FCITOF0_DE --- 0.242 R63C55C.FCI to R63C55C.F0 THE_RESET_HANDLER/SLICE_3971
+ROUTE 1 0.000 R63C55C.F0 to R63C55C.DI0 THE_RESET_HANDLER/reset_cnt_s_15 (to CLK100M_c)
+ --------
+ 5.026 (41.4% logic, 58.6% route), 13 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55C.CLK
+
+
+Passed: The following path meets requirements by 4.907ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_13 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_14 (to CLK100M_c +)
+
+ Delay: 5.022ns (42.7% logic, 57.3% route), 12 logic levels.
+
+ Constraint Details:
+
+ 5.022ns physical path delay THE_RESET_HANDLER/SLICE_3972 to THE_RESET_HANDLER/SLICE_3972 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.929ns) by 4.907ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R63C55B.CLK to R63C55B.Q0 THE_RESET_HANDLER/SLICE_3972 (from CLK100M_c)
+ROUTE 2 0.605 R63C55B.Q0 to R63C55D.A0 THE_RESET_HANDLER/reset_cnt_13
+CTOF_DEL --- 0.198 R63C55D.A0 to R63C55D.F0 THE_RESET_HANDLER/SLICE_14053
+ROUTE 1 0.747 R63C55D.F0 to R62C54A.C0 THE_RESET_HANDLER/un6_reset_cnt_10
+CTOF_DEL --- 0.198 R62C54A.C0 to R62C54A.F0 THE_RESET_HANDLER/SLICE_12748
+ROUTE 2 0.670 R62C54A.F0 to R62C55B.B0 THE_RESET_HANDLER/un6_reset_cnt
+CTOF_DEL --- 0.198 R62C55B.B0 to R62C55B.F0 THE_RESET_HANDLER/SLICE_8041
+ROUTE 17 0.858 R62C55B.F0 to R63C53A.B0 THE_RESET_HANDLER/reset_cnt
+C0TOFCO_DE --- 0.440 R63C53A.B0 to R63C53A.FCO THE_RESET_HANDLER/SLICE_3970
+ROUTE 1 0.000 R63C53A.FCO to R63C53B.FCI THE_RESET_HANDLER/reset_cnt_cry_0
+FCITOFCO_D --- 0.081 R63C53B.FCI to R63C53B.FCO THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.FCO to R63C53C.FCI THE_RESET_HANDLER/reset_cnt_cry_2
+FCITOFCO_D --- 0.081 R63C53C.FCI to R63C53C.FCO THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.FCO to R63C54A.FCI THE_RESET_HANDLER/reset_cnt_cry_4
+FCITOFCO_D --- 0.081 R63C54A.FCI to R63C54A.FCO THE_RESET_HANDLER/SLICE_3976
+ROUTE 1 0.000 R63C54A.FCO to R63C54B.FCI THE_RESET_HANDLER/reset_cnt_cry_6
+FCITOFCO_D --- 0.081 R63C54B.FCI to R63C54B.FCO THE_RESET_HANDLER/SLICE_3975
+ROUTE 1 0.000 R63C54B.FCO to R63C54C.FCI THE_RESET_HANDLER/reset_cnt_cry_8
+FCITOFCO_D --- 0.081 R63C54C.FCI to R63C54C.FCO THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.FCO to R63C55A.FCI THE_RESET_HANDLER/reset_cnt_cry_10
+FCITOFCO_D --- 0.081 R63C55A.FCI to R63C55A.FCO THE_RESET_HANDLER/SLICE_3973
+ROUTE 1 0.000 R63C55A.FCO to R63C55B.FCI THE_RESET_HANDLER/reset_cnt_cry_12
+FCITOF1_DE --- 0.313 R63C55B.FCI to R63C55B.F1 THE_RESET_HANDLER/SLICE_3972
+ROUTE 1 0.000 R63C55B.F1 to R63C55B.DI1 THE_RESET_HANDLER/reset_cnt_s_14 (to CLK100M_c)
+ --------
+ 5.022 (42.7% logic, 57.3% route), 12 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+
+Passed: The following path meets requirements by 4.913ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_14 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_14 (to CLK100M_c +)
+
+ Delay: 5.016ns (41.3% logic, 58.7% route), 12 logic levels.
+
+ Constraint Details:
+
+ 5.016ns physical path delay THE_RESET_HANDLER/SLICE_3972 to THE_RESET_HANDLER/SLICE_3972 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.929ns) by 4.913ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R63C55B.CLK to R63C55B.Q1 THE_RESET_HANDLER/SLICE_3972 (from CLK100M_c)
+ROUTE 2 0.670 R63C55B.Q1 to R63C55D.B0 THE_RESET_HANDLER/reset_cnt_14
+CTOF_DEL --- 0.198 R63C55D.B0 to R63C55D.F0 THE_RESET_HANDLER/SLICE_14053
+ROUTE 1 0.747 R63C55D.F0 to R62C54A.C0 THE_RESET_HANDLER/un6_reset_cnt_10
+CTOF_DEL --- 0.198 R62C54A.C0 to R62C54A.F0 THE_RESET_HANDLER/SLICE_12748
+ROUTE 2 0.670 R62C54A.F0 to R62C55B.B0 THE_RESET_HANDLER/un6_reset_cnt
+CTOF_DEL --- 0.198 R62C55B.B0 to R62C55B.F0 THE_RESET_HANDLER/SLICE_8041
+ROUTE 17 0.858 R62C55B.F0 to R63C53A.B1 THE_RESET_HANDLER/reset_cnt
+C1TOFCO_DE --- 0.369 R63C53A.B1 to R63C53A.FCO THE_RESET_HANDLER/SLICE_3970
+ROUTE 1 0.000 R63C53A.FCO to R63C53B.FCI THE_RESET_HANDLER/reset_cnt_cry_0
+FCITOFCO_D --- 0.081 R63C53B.FCI to R63C53B.FCO THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.FCO to R63C53C.FCI THE_RESET_HANDLER/reset_cnt_cry_2
+FCITOFCO_D --- 0.081 R63C53C.FCI to R63C53C.FCO THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.FCO to R63C54A.FCI THE_RESET_HANDLER/reset_cnt_cry_4
+FCITOFCO_D --- 0.081 R63C54A.FCI to R63C54A.FCO THE_RESET_HANDLER/SLICE_3976
+ROUTE 1 0.000 R63C54A.FCO to R63C54B.FCI THE_RESET_HANDLER/reset_cnt_cry_6
+FCITOFCO_D --- 0.081 R63C54B.FCI to R63C54B.FCO THE_RESET_HANDLER/SLICE_3975
+ROUTE 1 0.000 R63C54B.FCO to R63C54C.FCI THE_RESET_HANDLER/reset_cnt_cry_8
+FCITOFCO_D --- 0.081 R63C54C.FCI to R63C54C.FCO THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.FCO to R63C55A.FCI THE_RESET_HANDLER/reset_cnt_cry_10
+FCITOFCO_D --- 0.081 R63C55A.FCI to R63C55A.FCO THE_RESET_HANDLER/SLICE_3973
+ROUTE 1 0.000 R63C55A.FCO to R63C55B.FCI THE_RESET_HANDLER/reset_cnt_cry_12
+FCITOF1_DE --- 0.313 R63C55B.FCI to R63C55B.F1 THE_RESET_HANDLER/SLICE_3972
+ROUTE 1 0.000 R63C55B.F1 to R63C55B.DI1 THE_RESET_HANDLER/reset_cnt_s_14 (to CLK100M_c)
+ --------
+ 5.016 (41.3% logic, 58.7% route), 12 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+
+Passed: The following path meets requirements by 4.913ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_14 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_15 (to CLK100M_c +)
+
+ Delay: 5.016ns (41.3% logic, 58.7% route), 12 logic levels.
+
+ Constraint Details:
+
+ 5.016ns physical path delay THE_RESET_HANDLER/SLICE_3972 to THE_RESET_HANDLER/SLICE_3971 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.929ns) by 4.913ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R63C55B.CLK to R63C55B.Q1 THE_RESET_HANDLER/SLICE_3972 (from CLK100M_c)
+ROUTE 2 0.670 R63C55B.Q1 to R63C55D.B0 THE_RESET_HANDLER/reset_cnt_14
+CTOF_DEL --- 0.198 R63C55D.B0 to R63C55D.F0 THE_RESET_HANDLER/SLICE_14053
+ROUTE 1 0.747 R63C55D.F0 to R62C54A.C0 THE_RESET_HANDLER/un6_reset_cnt_10
+CTOF_DEL --- 0.198 R62C54A.C0 to R62C54A.F0 THE_RESET_HANDLER/SLICE_12748
+ROUTE 2 0.670 R62C54A.F0 to R62C55B.B0 THE_RESET_HANDLER/un6_reset_cnt
+CTOF_DEL --- 0.198 R62C55B.B0 to R62C55B.F0 THE_RESET_HANDLER/SLICE_8041
+ROUTE 17 0.858 R62C55B.F0 to R63C53B.B0 THE_RESET_HANDLER/reset_cnt
+C0TOFCO_DE --- 0.440 R63C53B.B0 to R63C53B.FCO THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.FCO to R63C53C.FCI THE_RESET_HANDLER/reset_cnt_cry_2
+FCITOFCO_D --- 0.081 R63C53C.FCI to R63C53C.FCO THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.FCO to R63C54A.FCI THE_RESET_HANDLER/reset_cnt_cry_4
+FCITOFCO_D --- 0.081 R63C54A.FCI to R63C54A.FCO THE_RESET_HANDLER/SLICE_3976
+ROUTE 1 0.000 R63C54A.FCO to R63C54B.FCI THE_RESET_HANDLER/reset_cnt_cry_6
+FCITOFCO_D --- 0.081 R63C54B.FCI to R63C54B.FCO THE_RESET_HANDLER/SLICE_3975
+ROUTE 1 0.000 R63C54B.FCO to R63C54C.FCI THE_RESET_HANDLER/reset_cnt_cry_8
+FCITOFCO_D --- 0.081 R63C54C.FCI to R63C54C.FCO THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.FCO to R63C55A.FCI THE_RESET_HANDLER/reset_cnt_cry_10
+FCITOFCO_D --- 0.081 R63C55A.FCI to R63C55A.FCO THE_RESET_HANDLER/SLICE_3973
+ROUTE 1 0.000 R63C55A.FCO to R63C55B.FCI THE_RESET_HANDLER/reset_cnt_cry_12
+FCITOFCO_D --- 0.081 R63C55B.FCI to R63C55B.FCO THE_RESET_HANDLER/SLICE_3972
+ROUTE 1 0.000 R63C55B.FCO to R63C55C.FCI THE_RESET_HANDLER/reset_cnt_cry_14
+FCITOF0_DE --- 0.242 R63C55C.FCI to R63C55C.F0 THE_RESET_HANDLER/SLICE_3971
+ROUTE 1 0.000 R63C55C.F0 to R63C55C.DI0 THE_RESET_HANDLER/reset_cnt_s_15 (to CLK100M_c)
+ --------
+ 5.016 (41.3% logic, 58.7% route), 12 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55C.CLK
+
+
+Passed: The following path meets requirements by 4.913ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_14 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_13 (to CLK100M_c +)
+
+ Delay: 5.016ns (41.3% logic, 58.7% route), 12 logic levels.
+
+ Constraint Details:
+
+ 5.016ns physical path delay THE_RESET_HANDLER/SLICE_3972 to THE_RESET_HANDLER/SLICE_3972 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.929ns) by 4.913ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R63C55B.CLK to R63C55B.Q1 THE_RESET_HANDLER/SLICE_3972 (from CLK100M_c)
+ROUTE 2 0.670 R63C55B.Q1 to R63C55D.B0 THE_RESET_HANDLER/reset_cnt_14
+CTOF_DEL --- 0.198 R63C55D.B0 to R63C55D.F0 THE_RESET_HANDLER/SLICE_14053
+ROUTE 1 0.747 R63C55D.F0 to R62C54A.C0 THE_RESET_HANDLER/un6_reset_cnt_10
+CTOF_DEL --- 0.198 R62C54A.C0 to R62C54A.F0 THE_RESET_HANDLER/SLICE_12748
+ROUTE 2 0.670 R62C54A.F0 to R62C55B.B0 THE_RESET_HANDLER/un6_reset_cnt
+CTOF_DEL --- 0.198 R62C55B.B0 to R62C55B.F0 THE_RESET_HANDLER/SLICE_8041
+ROUTE 17 0.858 R62C55B.F0 to R63C53A.B0 THE_RESET_HANDLER/reset_cnt
+C0TOFCO_DE --- 0.440 R63C53A.B0 to R63C53A.FCO THE_RESET_HANDLER/SLICE_3970
+ROUTE 1 0.000 R63C53A.FCO to R63C53B.FCI THE_RESET_HANDLER/reset_cnt_cry_0
+FCITOFCO_D --- 0.081 R63C53B.FCI to R63C53B.FCO THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.FCO to R63C53C.FCI THE_RESET_HANDLER/reset_cnt_cry_2
+FCITOFCO_D --- 0.081 R63C53C.FCI to R63C53C.FCO THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.FCO to R63C54A.FCI THE_RESET_HANDLER/reset_cnt_cry_4
+FCITOFCO_D --- 0.081 R63C54A.FCI to R63C54A.FCO THE_RESET_HANDLER/SLICE_3976
+ROUTE 1 0.000 R63C54A.FCO to R63C54B.FCI THE_RESET_HANDLER/reset_cnt_cry_6
+FCITOFCO_D --- 0.081 R63C54B.FCI to R63C54B.FCO THE_RESET_HANDLER/SLICE_3975
+ROUTE 1 0.000 R63C54B.FCO to R63C54C.FCI THE_RESET_HANDLER/reset_cnt_cry_8
+FCITOFCO_D --- 0.081 R63C54C.FCI to R63C54C.FCO THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.FCO to R63C55A.FCI THE_RESET_HANDLER/reset_cnt_cry_10
+FCITOFCO_D --- 0.081 R63C55A.FCI to R63C55A.FCO THE_RESET_HANDLER/SLICE_3973
+ROUTE 1 0.000 R63C55A.FCO to R63C55B.FCI THE_RESET_HANDLER/reset_cnt_cry_12
+FCITOF0_DE --- 0.242 R63C55B.FCI to R63C55B.F0 THE_RESET_HANDLER/SLICE_3972
+ROUTE 1 0.000 R63C55B.F0 to R63C55B.DI0 THE_RESET_HANDLER/reset_cnt_s_13 (to CLK100M_c)
+ --------
+ 5.016 (41.3% logic, 58.7% route), 12 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+
+Passed: The following path meets requirements by 4.923ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_14 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_14 (to CLK100M_c +)
+
+ Delay: 5.006ns (41.2% logic, 58.8% route), 11 logic levels.
+
+ Constraint Details:
+
+ 5.006ns physical path delay THE_RESET_HANDLER/SLICE_3972 to THE_RESET_HANDLER/SLICE_3972 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.929ns) by 4.923ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R63C55B.CLK to R63C55B.Q1 THE_RESET_HANDLER/SLICE_3972 (from CLK100M_c)
+ROUTE 2 0.670 R63C55B.Q1 to R63C55D.B0 THE_RESET_HANDLER/reset_cnt_14
+CTOF_DEL --- 0.198 R63C55D.B0 to R63C55D.F0 THE_RESET_HANDLER/SLICE_14053
+ROUTE 1 0.747 R63C55D.F0 to R62C54A.C0 THE_RESET_HANDLER/un6_reset_cnt_10
+CTOF_DEL --- 0.198 R62C54A.C0 to R62C54A.F0 THE_RESET_HANDLER/SLICE_12748
+ROUTE 2 0.670 R62C54A.F0 to R62C55B.B0 THE_RESET_HANDLER/un6_reset_cnt
+CTOF_DEL --- 0.198 R62C55B.B0 to R62C55B.F0 THE_RESET_HANDLER/SLICE_8041
+ROUTE 17 0.858 R62C55B.F0 to R63C53B.B0 THE_RESET_HANDLER/reset_cnt
+C0TOFCO_DE --- 0.440 R63C53B.B0 to R63C53B.FCO THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.FCO to R63C53C.FCI THE_RESET_HANDLER/reset_cnt_cry_2
+FCITOFCO_D --- 0.081 R63C53C.FCI to R63C53C.FCO THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.FCO to R63C54A.FCI THE_RESET_HANDLER/reset_cnt_cry_4
+FCITOFCO_D --- 0.081 R63C54A.FCI to R63C54A.FCO THE_RESET_HANDLER/SLICE_3976
+ROUTE 1 0.000 R63C54A.FCO to R63C54B.FCI THE_RESET_HANDLER/reset_cnt_cry_6
+FCITOFCO_D --- 0.081 R63C54B.FCI to R63C54B.FCO THE_RESET_HANDLER/SLICE_3975
+ROUTE 1 0.000 R63C54B.FCO to R63C54C.FCI THE_RESET_HANDLER/reset_cnt_cry_8
+FCITOFCO_D --- 0.081 R63C54C.FCI to R63C54C.FCO THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.FCO to R63C55A.FCI THE_RESET_HANDLER/reset_cnt_cry_10
+FCITOFCO_D --- 0.081 R63C55A.FCI to R63C55A.FCO THE_RESET_HANDLER/SLICE_3973
+ROUTE 1 0.000 R63C55A.FCO to R63C55B.FCI THE_RESET_HANDLER/reset_cnt_cry_12
+FCITOF1_DE --- 0.313 R63C55B.FCI to R63C55B.F1 THE_RESET_HANDLER/SLICE_3972
+ROUTE 1 0.000 R63C55B.F1 to R63C55B.DI1 THE_RESET_HANDLER/reset_cnt_s_14 (to CLK100M_c)
+ --------
+ 5.006 (41.2% logic, 58.8% route), 11 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+
+Passed: The following path meets requirements by 4.923ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_14 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_12 (to CLK100M_c +)
+
+ Delay: 5.006ns (41.2% logic, 58.8% route), 11 logic levels.
+
+ Constraint Details:
+
+ 5.006ns physical path delay THE_RESET_HANDLER/SLICE_3972 to THE_RESET_HANDLER/SLICE_3973 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.929ns) by 4.923ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R63C55B.CLK to R63C55B.Q1 THE_RESET_HANDLER/SLICE_3972 (from CLK100M_c)
+ROUTE 2 0.670 R63C55B.Q1 to R63C55D.B0 THE_RESET_HANDLER/reset_cnt_14
+CTOF_DEL --- 0.198 R63C55D.B0 to R63C55D.F0 THE_RESET_HANDLER/SLICE_14053
+ROUTE 1 0.747 R63C55D.F0 to R62C54A.C0 THE_RESET_HANDLER/un6_reset_cnt_10
+CTOF_DEL --- 0.198 R62C54A.C0 to R62C54A.F0 THE_RESET_HANDLER/SLICE_12748
+ROUTE 2 0.670 R62C54A.F0 to R62C55B.B0 THE_RESET_HANDLER/un6_reset_cnt
+CTOF_DEL --- 0.198 R62C55B.B0 to R62C55B.F0 THE_RESET_HANDLER/SLICE_8041
+ROUTE 17 0.858 R62C55B.F0 to R63C53A.B0 THE_RESET_HANDLER/reset_cnt
+C0TOFCO_DE --- 0.440 R63C53A.B0 to R63C53A.FCO THE_RESET_HANDLER/SLICE_3970
+ROUTE 1 0.000 R63C53A.FCO to R63C53B.FCI THE_RESET_HANDLER/reset_cnt_cry_0
+FCITOFCO_D --- 0.081 R63C53B.FCI to R63C53B.FCO THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.FCO to R63C53C.FCI THE_RESET_HANDLER/reset_cnt_cry_2
+FCITOFCO_D --- 0.081 R63C53C.FCI to R63C53C.FCO THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.FCO to R63C54A.FCI THE_RESET_HANDLER/reset_cnt_cry_4
+FCITOFCO_D --- 0.081 R63C54A.FCI to R63C54A.FCO THE_RESET_HANDLER/SLICE_3976
+ROUTE 1 0.000 R63C54A.FCO to R63C54B.FCI THE_RESET_HANDLER/reset_cnt_cry_6
+FCITOFCO_D --- 0.081 R63C54B.FCI to R63C54B.FCO THE_RESET_HANDLER/SLICE_3975
+ROUTE 1 0.000 R63C54B.FCO to R63C54C.FCI THE_RESET_HANDLER/reset_cnt_cry_8
+FCITOFCO_D --- 0.081 R63C54C.FCI to R63C54C.FCO THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.FCO to R63C55A.FCI THE_RESET_HANDLER/reset_cnt_cry_10
+FCITOF1_DE --- 0.313 R63C55A.FCI to R63C55A.F1 THE_RESET_HANDLER/SLICE_3973
+ROUTE 1 0.000 R63C55A.F1 to R63C55A.DI1 THE_RESET_HANDLER/reset_cnt_s_12 (to CLK100M_c)
+ --------
+ 5.006 (41.2% logic, 58.8% route), 11 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55A.CLK
+
+
+Passed: The following path meets requirements by 4.965ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_9 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_15 (to CLK100M_c +)
+
+ Delay: 4.964ns (43.4% logic, 56.6% route), 13 logic levels.
+
+ Constraint Details:
+
+ 4.964ns physical path delay THE_RESET_HANDLER/SLICE_3974 to THE_RESET_HANDLER/SLICE_3971 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.929ns) by 4.965ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R63C54C.CLK to R63C54C.Q0 THE_RESET_HANDLER/SLICE_3974 (from CLK100M_c)
+ROUTE 2 0.670 R63C54C.Q0 to R63C54D.B0 THE_RESET_HANDLER/reset_cnt_Q_9
+CTOF_DEL --- 0.198 R63C54D.B0 to R63C54D.F0 THE_RESET_HANDLER/SLICE_14054
+ROUTE 1 0.614 R63C54D.F0 to R62C54A.A0 THE_RESET_HANDLER/un6_reset_cnt_11
+CTOF_DEL --- 0.198 R62C54A.A0 to R62C54A.F0 THE_RESET_HANDLER/SLICE_12748
+ROUTE 2 0.670 R62C54A.F0 to R62C55B.B0 THE_RESET_HANDLER/un6_reset_cnt
+CTOF_DEL --- 0.198 R62C55B.B0 to R62C55B.F0 THE_RESET_HANDLER/SLICE_8041
+ROUTE 17 0.858 R62C55B.F0 to R63C53A.B0 THE_RESET_HANDLER/reset_cnt
+C0TOFCO_DE --- 0.440 R63C53A.B0 to R63C53A.FCO THE_RESET_HANDLER/SLICE_3970
+ROUTE 1 0.000 R63C53A.FCO to R63C53B.FCI THE_RESET_HANDLER/reset_cnt_cry_0
+FCITOFCO_D --- 0.081 R63C53B.FCI to R63C53B.FCO THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.FCO to R63C53C.FCI THE_RESET_HANDLER/reset_cnt_cry_2
+FCITOFCO_D --- 0.081 R63C53C.FCI to R63C53C.FCO THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.FCO to R63C54A.FCI THE_RESET_HANDLER/reset_cnt_cry_4
+FCITOFCO_D --- 0.081 R63C54A.FCI to R63C54A.FCO THE_RESET_HANDLER/SLICE_3976
+ROUTE 1 0.000 R63C54A.FCO to R63C54B.FCI THE_RESET_HANDLER/reset_cnt_cry_6
+FCITOFCO_D --- 0.081 R63C54B.FCI to R63C54B.FCO THE_RESET_HANDLER/SLICE_3975
+ROUTE 1 0.000 R63C54B.FCO to R63C54C.FCI THE_RESET_HANDLER/reset_cnt_cry_8
+FCITOFCO_D --- 0.081 R63C54C.FCI to R63C54C.FCO THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.FCO to R63C55A.FCI THE_RESET_HANDLER/reset_cnt_cry_10
+FCITOFCO_D --- 0.081 R63C55A.FCI to R63C55A.FCO THE_RESET_HANDLER/SLICE_3973
+ROUTE 1 0.000 R63C55A.FCO to R63C55B.FCI THE_RESET_HANDLER/reset_cnt_cry_12
+FCITOFCO_D --- 0.081 R63C55B.FCI to R63C55B.FCO THE_RESET_HANDLER/SLICE_3972
+ROUTE 1 0.000 R63C55B.FCO to R63C55C.FCI THE_RESET_HANDLER/reset_cnt_cry_14
+FCITOF0_DE --- 0.242 R63C55C.FCI to R63C55C.F0 THE_RESET_HANDLER/SLICE_3971
+ROUTE 1 0.000 R63C55C.F0 to R63C55C.DI0 THE_RESET_HANDLER/reset_cnt_s_15 (to CLK100M_c)
+ --------
+ 4.964 (43.4% logic, 56.6% route), 13 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C54C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55C.CLK
+
+
+Passed: The following path meets requirements by 4.968ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_13 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_15 (to CLK100M_c +)
+
+ Delay: 4.961ns (41.9% logic, 58.1% route), 13 logic levels.
+
+ Constraint Details:
+
+ 4.961ns physical path delay THE_RESET_HANDLER/SLICE_3972 to THE_RESET_HANDLER/SLICE_3971 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.929ns) by 4.968ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R63C55B.CLK to R63C55B.Q0 THE_RESET_HANDLER/SLICE_3972 (from CLK100M_c)
+ROUTE 2 0.605 R63C55B.Q0 to R63C55D.A0 THE_RESET_HANDLER/reset_cnt_13
+CTOF_DEL --- 0.198 R63C55D.A0 to R63C55D.F0 THE_RESET_HANDLER/SLICE_14053
+ROUTE 1 0.747 R63C55D.F0 to R62C54A.C0 THE_RESET_HANDLER/un6_reset_cnt_10
+CTOF_DEL --- 0.198 R62C54A.C0 to R62C54A.F0 THE_RESET_HANDLER/SLICE_12748
+ROUTE 2 0.670 R62C54A.F0 to R62C55B.B0 THE_RESET_HANDLER/un6_reset_cnt
+CTOF_DEL --- 0.198 R62C55B.B0 to R62C55B.F0 THE_RESET_HANDLER/SLICE_8041
+ROUTE 17 0.858 R62C55B.F0 to R63C53A.B1 THE_RESET_HANDLER/reset_cnt
+C1TOFCO_DE --- 0.369 R63C53A.B1 to R63C53A.FCO THE_RESET_HANDLER/SLICE_3970
+ROUTE 1 0.000 R63C53A.FCO to R63C53B.FCI THE_RESET_HANDLER/reset_cnt_cry_0
+FCITOFCO_D --- 0.081 R63C53B.FCI to R63C53B.FCO THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.FCO to R63C53C.FCI THE_RESET_HANDLER/reset_cnt_cry_2
+FCITOFCO_D --- 0.081 R63C53C.FCI to R63C53C.FCO THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.FCO to R63C54A.FCI THE_RESET_HANDLER/reset_cnt_cry_4
+FCITOFCO_D --- 0.081 R63C54A.FCI to R63C54A.FCO THE_RESET_HANDLER/SLICE_3976
+ROUTE 1 0.000 R63C54A.FCO to R63C54B.FCI THE_RESET_HANDLER/reset_cnt_cry_6
+FCITOFCO_D --- 0.081 R63C54B.FCI to R63C54B.FCO THE_RESET_HANDLER/SLICE_3975
+ROUTE 1 0.000 R63C54B.FCO to R63C54C.FCI THE_RESET_HANDLER/reset_cnt_cry_8
+FCITOFCO_D --- 0.081 R63C54C.FCI to R63C54C.FCO THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.FCO to R63C55A.FCI THE_RESET_HANDLER/reset_cnt_cry_10
+FCITOFCO_D --- 0.081 R63C55A.FCI to R63C55A.FCO THE_RESET_HANDLER/SLICE_3973
+ROUTE 1 0.000 R63C55A.FCO to R63C55B.FCI THE_RESET_HANDLER/reset_cnt_cry_12
+FCITOFCO_D --- 0.081 R63C55B.FCI to R63C55B.FCO THE_RESET_HANDLER/SLICE_3972
+ROUTE 1 0.000 R63C55B.FCO to R63C55C.FCI THE_RESET_HANDLER/reset_cnt_cry_14
+FCITOF0_DE --- 0.242 R63C55C.FCI to R63C55C.F0 THE_RESET_HANDLER/SLICE_3971
+ROUTE 1 0.000 R63C55C.F0 to R63C55C.DI0 THE_RESET_HANDLER/reset_cnt_s_15 (to CLK100M_c)
+ --------
+ 4.961 (41.9% logic, 58.1% route), 13 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55C.CLK
+
+
+Passed: The following path meets requirements by 4.975ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_9 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_14 (to CLK100M_c +)
+
+ Delay: 4.954ns (43.2% logic, 56.8% route), 12 logic levels.
+
+ Constraint Details:
+
+ 4.954ns physical path delay THE_RESET_HANDLER/SLICE_3974 to THE_RESET_HANDLER/SLICE_3972 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.929ns) by 4.975ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R63C54C.CLK to R63C54C.Q0 THE_RESET_HANDLER/SLICE_3974 (from CLK100M_c)
+ROUTE 2 0.670 R63C54C.Q0 to R63C54D.B0 THE_RESET_HANDLER/reset_cnt_Q_9
+CTOF_DEL --- 0.198 R63C54D.B0 to R63C54D.F0 THE_RESET_HANDLER/SLICE_14054
+ROUTE 1 0.614 R63C54D.F0 to R62C54A.A0 THE_RESET_HANDLER/un6_reset_cnt_11
+CTOF_DEL --- 0.198 R62C54A.A0 to R62C54A.F0 THE_RESET_HANDLER/SLICE_12748
+ROUTE 2 0.670 R62C54A.F0 to R62C55B.B0 THE_RESET_HANDLER/un6_reset_cnt
+CTOF_DEL --- 0.198 R62C55B.B0 to R62C55B.F0 THE_RESET_HANDLER/SLICE_8041
+ROUTE 17 0.858 R62C55B.F0 to R63C53A.B0 THE_RESET_HANDLER/reset_cnt
+C0TOFCO_DE --- 0.440 R63C53A.B0 to R63C53A.FCO THE_RESET_HANDLER/SLICE_3970
+ROUTE 1 0.000 R63C53A.FCO to R63C53B.FCI THE_RESET_HANDLER/reset_cnt_cry_0
+FCITOFCO_D --- 0.081 R63C53B.FCI to R63C53B.FCO THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.FCO to R63C53C.FCI THE_RESET_HANDLER/reset_cnt_cry_2
+FCITOFCO_D --- 0.081 R63C53C.FCI to R63C53C.FCO THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.FCO to R63C54A.FCI THE_RESET_HANDLER/reset_cnt_cry_4
+FCITOFCO_D --- 0.081 R63C54A.FCI to R63C54A.FCO THE_RESET_HANDLER/SLICE_3976
+ROUTE 1 0.000 R63C54A.FCO to R63C54B.FCI THE_RESET_HANDLER/reset_cnt_cry_6
+FCITOFCO_D --- 0.081 R63C54B.FCI to R63C54B.FCO THE_RESET_HANDLER/SLICE_3975
+ROUTE 1 0.000 R63C54B.FCO to R63C54C.FCI THE_RESET_HANDLER/reset_cnt_cry_8
+FCITOFCO_D --- 0.081 R63C54C.FCI to R63C54C.FCO THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.FCO to R63C55A.FCI THE_RESET_HANDLER/reset_cnt_cry_10
+FCITOFCO_D --- 0.081 R63C55A.FCI to R63C55A.FCO THE_RESET_HANDLER/SLICE_3973
+ROUTE 1 0.000 R63C55A.FCO to R63C55B.FCI THE_RESET_HANDLER/reset_cnt_cry_12
+FCITOF1_DE --- 0.313 R63C55B.FCI to R63C55B.F1 THE_RESET_HANDLER/SLICE_3972
+ROUTE 1 0.000 R63C55B.F1 to R63C55B.DI1 THE_RESET_HANDLER/reset_cnt_s_14 (to CLK100M_c)
+ --------
+ 4.954 (43.2% logic, 56.8% route), 12 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C54C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+
+Passed: The following path meets requirements by 4.978ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_13 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_13 (to CLK100M_c +)
+
+ Delay: 4.951ns (41.8% logic, 58.2% route), 12 logic levels.
+
+ Constraint Details:
+
+ 4.951ns physical path delay THE_RESET_HANDLER/SLICE_3972 to THE_RESET_HANDLER/SLICE_3972 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.929ns) by 4.978ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R63C55B.CLK to R63C55B.Q0 THE_RESET_HANDLER/SLICE_3972 (from CLK100M_c)
+ROUTE 2 0.605 R63C55B.Q0 to R63C55D.A0 THE_RESET_HANDLER/reset_cnt_13
+CTOF_DEL --- 0.198 R63C55D.A0 to R63C55D.F0 THE_RESET_HANDLER/SLICE_14053
+ROUTE 1 0.747 R63C55D.F0 to R62C54A.C0 THE_RESET_HANDLER/un6_reset_cnt_10
+CTOF_DEL --- 0.198 R62C54A.C0 to R62C54A.F0 THE_RESET_HANDLER/SLICE_12748
+ROUTE 2 0.670 R62C54A.F0 to R62C55B.B0 THE_RESET_HANDLER/un6_reset_cnt
+CTOF_DEL --- 0.198 R62C55B.B0 to R62C55B.F0 THE_RESET_HANDLER/SLICE_8041
+ROUTE 17 0.858 R62C55B.F0 to R63C53A.B0 THE_RESET_HANDLER/reset_cnt
+C0TOFCO_DE --- 0.440 R63C53A.B0 to R63C53A.FCO THE_RESET_HANDLER/SLICE_3970
+ROUTE 1 0.000 R63C53A.FCO to R63C53B.FCI THE_RESET_HANDLER/reset_cnt_cry_0
+FCITOFCO_D --- 0.081 R63C53B.FCI to R63C53B.FCO THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.FCO to R63C53C.FCI THE_RESET_HANDLER/reset_cnt_cry_2
+FCITOFCO_D --- 0.081 R63C53C.FCI to R63C53C.FCO THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.FCO to R63C54A.FCI THE_RESET_HANDLER/reset_cnt_cry_4
+FCITOFCO_D --- 0.081 R63C54A.FCI to R63C54A.FCO THE_RESET_HANDLER/SLICE_3976
+ROUTE 1 0.000 R63C54A.FCO to R63C54B.FCI THE_RESET_HANDLER/reset_cnt_cry_6
+FCITOFCO_D --- 0.081 R63C54B.FCI to R63C54B.FCO THE_RESET_HANDLER/SLICE_3975
+ROUTE 1 0.000 R63C54B.FCO to R63C54C.FCI THE_RESET_HANDLER/reset_cnt_cry_8
+FCITOFCO_D --- 0.081 R63C54C.FCI to R63C54C.FCO THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.FCO to R63C55A.FCI THE_RESET_HANDLER/reset_cnt_cry_10
+FCITOFCO_D --- 0.081 R63C55A.FCI to R63C55A.FCO THE_RESET_HANDLER/SLICE_3973
+ROUTE 1 0.000 R63C55A.FCO to R63C55B.FCI THE_RESET_HANDLER/reset_cnt_cry_12
+FCITOF0_DE --- 0.242 R63C55B.FCI to R63C55B.F0 THE_RESET_HANDLER/SLICE_3972
+ROUTE 1 0.000 R63C55B.F0 to R63C55B.DI0 THE_RESET_HANDLER/reset_cnt_s_13 (to CLK100M_c)
+ --------
+ 4.951 (41.8% logic, 58.2% route), 12 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+
+Passed: The following path meets requirements by 4.978ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/reset_cnt_13 (from CLK100M_c +)
+ Destination: FF Data in THE_RESET_HANDLER/reset_cnt_14 (to CLK100M_c +)
+
+ Delay: 4.951ns (41.8% logic, 58.2% route), 12 logic levels.
+
+ Constraint Details:
+
+ 4.951ns physical path delay THE_RESET_HANDLER/SLICE_3972 to THE_RESET_HANDLER/SLICE_3972 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.929ns) by 4.978ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R63C55B.CLK to R63C55B.Q0 THE_RESET_HANDLER/SLICE_3972 (from CLK100M_c)
+ROUTE 2 0.605 R63C55B.Q0 to R63C55D.A0 THE_RESET_HANDLER/reset_cnt_13
+CTOF_DEL --- 0.198 R63C55D.A0 to R63C55D.F0 THE_RESET_HANDLER/SLICE_14053
+ROUTE 1 0.747 R63C55D.F0 to R62C54A.C0 THE_RESET_HANDLER/un6_reset_cnt_10
+CTOF_DEL --- 0.198 R62C54A.C0 to R62C54A.F0 THE_RESET_HANDLER/SLICE_12748
+ROUTE 2 0.670 R62C54A.F0 to R62C55B.B0 THE_RESET_HANDLER/un6_reset_cnt
+CTOF_DEL --- 0.198 R62C55B.B0 to R62C55B.F0 THE_RESET_HANDLER/SLICE_8041
+ROUTE 17 0.858 R62C55B.F0 to R63C53A.B1 THE_RESET_HANDLER/reset_cnt
+C1TOFCO_DE --- 0.369 R63C53A.B1 to R63C53A.FCO THE_RESET_HANDLER/SLICE_3970
+ROUTE 1 0.000 R63C53A.FCO to R63C53B.FCI THE_RESET_HANDLER/reset_cnt_cry_0
+FCITOFCO_D --- 0.081 R63C53B.FCI to R63C53B.FCO THE_RESET_HANDLER/SLICE_3978
+ROUTE 1 0.000 R63C53B.FCO to R63C53C.FCI THE_RESET_HANDLER/reset_cnt_cry_2
+FCITOFCO_D --- 0.081 R63C53C.FCI to R63C53C.FCO THE_RESET_HANDLER/SLICE_3977
+ROUTE 1 0.000 R63C53C.FCO to R63C54A.FCI THE_RESET_HANDLER/reset_cnt_cry_4
+FCITOFCO_D --- 0.081 R63C54A.FCI to R63C54A.FCO THE_RESET_HANDLER/SLICE_3976
+ROUTE 1 0.000 R63C54A.FCO to R63C54B.FCI THE_RESET_HANDLER/reset_cnt_cry_6
+FCITOFCO_D --- 0.081 R63C54B.FCI to R63C54B.FCO THE_RESET_HANDLER/SLICE_3975
+ROUTE 1 0.000 R63C54B.FCO to R63C54C.FCI THE_RESET_HANDLER/reset_cnt_cry_8
+FCITOFCO_D --- 0.081 R63C54C.FCI to R63C54C.FCO THE_RESET_HANDLER/SLICE_3974
+ROUTE 1 0.000 R63C54C.FCO to R63C55A.FCI THE_RESET_HANDLER/reset_cnt_cry_10
+FCITOFCO_D --- 0.081 R63C55A.FCI to R63C55A.FCO THE_RESET_HANDLER/SLICE_3973
+ROUTE 1 0.000 R63C55A.FCO to R63C55B.FCI THE_RESET_HANDLER/reset_cnt_cry_12
+FCITOF1_DE --- 0.313 R63C55B.FCI to R63C55B.F1 THE_RESET_HANDLER/SLICE_3972
+ROUTE 1 0.000 R63C55B.F1 to R63C55B.DI1 THE_RESET_HANDLER/reset_cnt_s_14 (to CLK100M_c)
+ --------
+ 4.951 (41.8% logic, 58.2% route), 12 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.359ns AJ14.PADDI to R63C55B.CLK
+
+Report: 193.498MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "clk_apv_c" 40.000000 MHz ;
+ 4096 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 1.128ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RICH_TRB/THE_MEDIA_INTERFACE/make_trbnet_reset (from sysclk_c +)
+ Destination: FF Data in THE_ADC_1_SELECT/THE_RESET_SYNC/sync_0 (to clk_apv_c +)
+
+ Delay: 3.743ns (8.3% logic, 91.7% route), 1 logic levels.
+
+ Constraint Details:
+
+ 3.743ns physical path delay THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_11206 to THE_ADC_1_SELECT/THE_RESET_SYNC/SLICE_4909 meets
+ 5.000ns delay constraint less
+ 7.500ns skew and
+ -7.500ns feedback compensation and
+ 0.129ns M_SET requirement (totaling 4.871ns) by 1.128ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R50C110A.CLK to R50C110A.Q0 THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_11206 (from sysclk_c)
+ROUTE 27 3.434 R50C110A.Q0 to R52C26B.M0 reset_by_trb (to clk_apv_c)
+ --------
+ 3.743 (8.3% logic, 91.7% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C1.CLKI CLK100M_c
+CK2OUT_DEL --- 7.500 *L_R103C1.CLKI to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.469 *_R103C1.CLKOP to R50C110A.CLK sysclk_c
+ --------
+ 11.098 (73.6% logic, 26.4% route), 2 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.469 *_R103C3.CLKOP to R52C26B.CLK clk_apv_c
+ --------
+ 3.598 (18.5% logic, 81.5% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CK2OUT_DEL --- 7.500 *_R103C1.CLKFB to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.575 *_R103C1.CLKOP to *_R103C1.CLKFB sysclk_c
+ --------
+ 9.075 (82.6% logic, 17.4% route), 1 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.575 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 1.575 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 1.282ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_SLAVE_BUS/THE_ADC_LVL_REG/reg_slv_data_in_20 (from sysclk_c +)
+ Destination: FF Data in THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/bit_low (to clk_apv_c +)
+
+ Delay: 3.647ns (29.4% logic, 70.6% route), 4 logic levels.
+
+ Constraint Details:
+
+ 3.647ns physical path delay THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10754 to THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1300 meets
+ 5.000ns delay constraint less
+ 7.500ns skew and
+ -7.500ns feedback compensation and
+ 0.071ns DIN_SET requirement (totaling 4.929ns) by 1.282ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R55C47A.CLK to R55C47A.Q0 THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10754 (from sysclk_c)
+ROUTE 17 2.575 R55C47A.Q0 to R68C21C.A1 ctrl_lvl_20
+C1TOFCO_DE --- 0.369 R68C21C.A1 to R68C21C.FCO THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1302
+ROUTE 1 0.000 R68C21C.FCO to R68C22A.FCI THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_8
+FCITOFCO_D --- 0.081 R68C22A.FCI to R68C22A.FCO THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1301
+ROUTE 1 0.000 R68C22A.FCO to R68C22B.FCI THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_10
+FCITOF1_DE --- 0.313 R68C22B.FCI to R68C22B.F1 THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1300
+ROUTE 1 0.000 R68C22B.F1 to R68C22B.DI1 THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in (to clk_apv_c)
+ --------
+ 3.647 (29.4% logic, 70.6% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C1.CLKI CLK100M_c
+CK2OUT_DEL --- 7.500 *L_R103C1.CLKI to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.469 *_R103C1.CLKOP to R55C47A.CLK sysclk_c
+ --------
+ 11.098 (73.6% logic, 26.4% route), 2 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.469 *_R103C3.CLKOP to R68C22B.CLK clk_apv_c
+ --------
+ 3.598 (18.5% logic, 81.5% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CK2OUT_DEL --- 7.500 *_R103C1.CLKFB to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.575 *_R103C1.CLKOP to *_R103C1.CLKFB sysclk_c
+ --------
+ 9.075 (82.6% logic, 17.4% route), 1 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.575 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 1.575 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 1.321ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_SLAVE_BUS/THE_ADC_LVL_REG/reg_slv_data_in_18 (from sysclk_c +)
+ Destination: FF Data in THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/bit_low (to clk_apv_c +)
+
+ Delay: 3.608ns (32.0% logic, 68.0% route), 5 logic levels.
+
+ Constraint Details:
+
+ 3.608ns physical path delay THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10753 to THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1364 meets
+ 5.000ns delay constraint less
+ 7.500ns skew and
+ -7.500ns feedback compensation and
+ 0.071ns DIN_SET requirement (totaling 4.929ns) by 1.321ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C45B.CLK to R56C45B.Q0 THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10753 (from sysclk_c)
+ROUTE 17 2.455 R56C45B.Q0 to R69C23B.A1 ctrl_lvl_18
+C1TOFCO_DE --- 0.369 R69C23B.A1 to R69C23B.FCO THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1367
+ROUTE 1 0.000 R69C23B.FCO to R69C23C.FCI THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_6
+FCITOFCO_D --- 0.081 R69C23C.FCI to R69C23C.FCO THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1366
+ROUTE 1 0.000 R69C23C.FCO to R69C24A.FCI THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_8
+FCITOFCO_D --- 0.081 R69C24A.FCI to R69C24A.FCO THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1365
+ROUTE 1 0.000 R69C24A.FCO to R69C24B.FCI THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_10
+FCITOF1_DE --- 0.313 R69C24B.FCI to R69C24B.F1 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1364
+ROUTE 1 0.000 R69C24B.F1 to R69C24B.DI1 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in (to clk_apv_c)
+ --------
+ 3.608 (32.0% logic, 68.0% route), 5 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C1.CLKI CLK100M_c
+CK2OUT_DEL --- 7.500 *L_R103C1.CLKI to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.469 *_R103C1.CLKOP to R56C45B.CLK sysclk_c
+ --------
+ 11.098 (73.6% logic, 26.4% route), 2 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.469 *_R103C3.CLKOP to R69C24B.CLK clk_apv_c
+ --------
+ 3.598 (18.5% logic, 81.5% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CK2OUT_DEL --- 7.500 *_R103C1.CLKFB to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.575 *_R103C1.CLKOP to *_R103C1.CLKFB sysclk_c
+ --------
+ 9.075 (82.6% logic, 17.4% route), 1 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.575 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 1.575 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 1.331ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_SLAVE_BUS/THE_ADC_LVL_REG/reg_slv_data_in_19 (from sysclk_c +)
+ Destination: FF Data in THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/bit_low (to clk_apv_c +)
+
+ Delay: 3.598ns (31.8% logic, 68.2% route), 4 logic levels.
+
+ Constraint Details:
+
+ 3.598ns physical path delay THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10753 to THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1364 meets
+ 5.000ns delay constraint less
+ 7.500ns skew and
+ -7.500ns feedback compensation and
+ 0.071ns DIN_SET requirement (totaling 4.929ns) by 1.331ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C45B.CLK to R56C45B.Q1 THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10753 (from sysclk_c)
+ROUTE 17 2.455 R56C45B.Q1 to R69C23C.A0 ctrl_lvl_19
+C0TOFCO_DE --- 0.440 R69C23C.A0 to R69C23C.FCO THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1366
+ROUTE 1 0.000 R69C23C.FCO to R69C24A.FCI THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_8
+FCITOFCO_D --- 0.081 R69C24A.FCI to R69C24A.FCO THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1365
+ROUTE 1 0.000 R69C24A.FCO to R69C24B.FCI THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_10
+FCITOF1_DE --- 0.313 R69C24B.FCI to R69C24B.F1 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1364
+ROUTE 1 0.000 R69C24B.F1 to R69C24B.DI1 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in (to clk_apv_c)
+ --------
+ 3.598 (31.8% logic, 68.2% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C1.CLKI CLK100M_c
+CK2OUT_DEL --- 7.500 *L_R103C1.CLKI to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.469 *_R103C1.CLKOP to R56C45B.CLK sysclk_c
+ --------
+ 11.098 (73.6% logic, 26.4% route), 2 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.469 *_R103C3.CLKOP to R69C24B.CLK clk_apv_c
+ --------
+ 3.598 (18.5% logic, 81.5% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CK2OUT_DEL --- 7.500 *_R103C1.CLKFB to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.575 *_R103C1.CLKOP to *_R103C1.CLKFB sysclk_c
+ --------
+ 9.075 (82.6% logic, 17.4% route), 1 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.575 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 1.575 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 1.420ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_SLAVE_BUS/THE_ADC_LVL_REG/reg_slv_data_in_24 (from sysclk_c +)
+ Destination: FF Data in THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/bit_high (to clk_apv_c +)
+
+ Delay: 3.509ns (35.2% logic, 64.8% route), 6 logic levels.
+
+ Constraint Details:
+
+ 3.509ns physical path delay THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10756 to THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1009 meets
+ 5.000ns delay constraint less
+ 7.500ns skew and
+ -7.500ns feedback compensation and
+ 0.071ns DIN_SET requirement (totaling 4.929ns) by 1.420ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R59C40A.CLK to R59C40A.Q0 THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10756 (from sysclk_c)
+ROUTE 17 2.275 R59C40A.Q0 to R62C16C.A1 ctrl_lvl_24
+C1TOFCO_DE --- 0.369 R62C16C.A1 to R62C16C.FCO THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1013
+ROUTE 1 0.000 R62C16C.FCO to R62C17A.FCI THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high2_cry_4
+FCITOFCO_D --- 0.081 R62C17A.FCI to R62C17A.FCO THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1012
+ROUTE 1 0.000 R62C17A.FCO to R62C17B.FCI THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high2_cry_6
+FCITOFCO_D --- 0.081 R62C17B.FCI to R62C17B.FCO THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1011
+ROUTE 1 0.000 R62C17B.FCO to R62C17C.FCI THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high2_cry_8
+FCITOFCO_D --- 0.081 R62C17C.FCI to R62C17C.FCO THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1010
+ROUTE 1 0.000 R62C17C.FCO to R62C18A.FCI THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high2_cry_10
+FCITOF1_DE --- 0.313 R62C18A.FCI to R62C18A.F1 THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1009
+ROUTE 1 0.000 R62C18A.F1 to R62C18A.DI1 THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high2 (to clk_apv_c)
+ --------
+ 3.509 (35.2% logic, 64.8% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C1.CLKI CLK100M_c
+CK2OUT_DEL --- 7.500 *L_R103C1.CLKI to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.469 *_R103C1.CLKOP to R59C40A.CLK sysclk_c
+ --------
+ 11.098 (73.6% logic, 26.4% route), 2 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.469 *_R103C3.CLKOP to R62C18A.CLK clk_apv_c
+ --------
+ 3.598 (18.5% logic, 81.5% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CK2OUT_DEL --- 7.500 *_R103C1.CLKFB to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.575 *_R103C1.CLKOP to *_R103C1.CLKFB sysclk_c
+ --------
+ 9.075 (82.6% logic, 17.4% route), 1 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.575 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 1.575 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 1.455ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_SLAVE_BUS/THE_ADC_LVL_REG/reg_slv_data_in_8 (from sysclk_c +)
+ Destination: FF Data in THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/fl_high (to clk_apv_c +)
+
+ Delay: 3.474ns (35.5% logic, 64.5% route), 6 logic levels.
+
+ Constraint Details:
+
+ 3.474ns physical path delay THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10748 to THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1351 meets
+ 5.000ns delay constraint less
+ 7.500ns skew and
+ -7.500ns feedback compensation and
+ 0.071ns DIN_SET requirement (totaling 4.929ns) by 1.455ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R50C34A.CLK to R50C34A.Q0 THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10748 (from sysclk_c)
+ROUTE 17 2.240 R50C34A.Q0 to R63C18A.B1 ctrl_lvl_8
+C1TOFCO_DE --- 0.369 R63C18A.B1 to R63C18A.FCO THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1355
+ROUTE 1 0.000 R63C18A.FCO to R63C18B.FCI THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_in_cry_4
+FCITOFCO_D --- 0.081 R63C18B.FCI to R63C18B.FCO THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1354
+ROUTE 1 0.000 R63C18B.FCO to R63C18C.FCI THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_in_cry_6
+FCITOFCO_D --- 0.081 R63C18C.FCI to R63C18C.FCO THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1353
+ROUTE 1 0.000 R63C18C.FCO to R63C19A.FCI THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_in_cry_8
+FCITOFCO_D --- 0.081 R63C19A.FCI to R63C19A.FCO THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1352
+ROUTE 1 0.000 R63C19A.FCO to R63C19B.FCI THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_in_cry_10
+FCITOF1_DE --- 0.313 R63C19B.FCI to R63C19B.F1 THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1351
+ROUTE 1 0.000 R63C19B.F1 to R63C19B.DI1 THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_in (to clk_apv_c)
+ --------
+ 3.474 (35.5% logic, 64.5% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C1.CLKI CLK100M_c
+CK2OUT_DEL --- 7.500 *L_R103C1.CLKI to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.469 *_R103C1.CLKOP to R50C34A.CLK sysclk_c
+ --------
+ 11.098 (73.6% logic, 26.4% route), 2 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.469 *_R103C3.CLKOP to R63C19B.CLK clk_apv_c
+ --------
+ 3.598 (18.5% logic, 81.5% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CK2OUT_DEL --- 7.500 *_R103C1.CLKFB to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.575 *_R103C1.CLKOP to *_R103C1.CLKFB sysclk_c
+ --------
+ 9.075 (82.6% logic, 17.4% route), 1 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.575 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 1.575 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 1.464ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_SLAVE_BUS/THE_ADC_LVL_REG/reg_slv_data_in_24 (from sysclk_c +)
+ Destination: FF Data in THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/bit_high (to clk_apv_c +)
+
+ Delay: 3.465ns (35.6% logic, 64.4% route), 6 logic levels.
+
+ Constraint Details:
+
+ 3.465ns physical path delay THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10756 to THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_849 meets
+ 5.000ns delay constraint less
+ 7.500ns skew and
+ -7.500ns feedback compensation and
+ 0.071ns DIN_SET requirement (totaling 4.929ns) by 1.464ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R59C40A.CLK to R59C40A.Q0 THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10756 (from sysclk_c)
+ROUTE 17 2.231 R59C40A.Q0 to R51C16C.B1 ctrl_lvl_24
+C1TOFCO_DE --- 0.369 R51C16C.B1 to R51C16C.FCO THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_853
+ROUTE 1 0.000 R51C16C.FCO to R51C17A.FCI THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high2_cry_4
+FCITOFCO_D --- 0.081 R51C17A.FCI to R51C17A.FCO THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_852
+ROUTE 1 0.000 R51C17A.FCO to R51C17B.FCI THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high2_cry_6
+FCITOFCO_D --- 0.081 R51C17B.FCI to R51C17B.FCO THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_851
+ROUTE 1 0.000 R51C17B.FCO to R51C17C.FCI THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high2_cry_8
+FCITOFCO_D --- 0.081 R51C17C.FCI to R51C17C.FCO THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_850
+ROUTE 1 0.000 R51C17C.FCO to R51C18A.FCI THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high2_cry_10
+FCITOF1_DE --- 0.313 R51C18A.FCI to R51C18A.F1 THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_849
+ROUTE 1 0.000 R51C18A.F1 to R51C18A.DI1 THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high2 (to clk_apv_c)
+ --------
+ 3.465 (35.6% logic, 64.4% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C1.CLKI CLK100M_c
+CK2OUT_DEL --- 7.500 *L_R103C1.CLKI to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.469 *_R103C1.CLKOP to R59C40A.CLK sysclk_c
+ --------
+ 11.098 (73.6% logic, 26.4% route), 2 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.469 *_R103C3.CLKOP to R51C18A.CLK clk_apv_c
+ --------
+ 3.598 (18.5% logic, 81.5% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CK2OUT_DEL --- 7.500 *_R103C1.CLKFB to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.575 *_R103C1.CLKOP to *_R103C1.CLKFB sysclk_c
+ --------
+ 9.075 (82.6% logic, 17.4% route), 1 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.575 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 1.575 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 1.464ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_SLAVE_BUS/THE_ADC_LVL_REG/reg_slv_data_in_20 (from sysclk_c +)
+ Destination: FF Data in THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/bit_low (to clk_apv_c +)
+
+ Delay: 3.465ns (30.9% logic, 69.1% route), 4 logic levels.
+
+ Constraint Details:
+
+ 3.465ns physical path delay THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10754 to THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1332 meets
+ 5.000ns delay constraint less
+ 7.500ns skew and
+ -7.500ns feedback compensation and
+ 0.071ns DIN_SET requirement (totaling 4.929ns) by 1.464ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R55C47A.CLK to R55C47A.Q0 THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10754 (from sysclk_c)
+ROUTE 17 2.393 R55C47A.Q0 to R69C20C.A1 ctrl_lvl_20
+C1TOFCO_DE --- 0.369 R69C20C.A1 to R69C20C.FCO THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1334
+ROUTE 1 0.000 R69C20C.FCO to R69C21A.FCI THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_8
+FCITOFCO_D --- 0.081 R69C21A.FCI to R69C21A.FCO THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1333
+ROUTE 1 0.000 R69C21A.FCO to R69C21B.FCI THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_10
+FCITOF1_DE --- 0.313 R69C21B.FCI to R69C21B.F1 THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1332
+ROUTE 1 0.000 R69C21B.F1 to R69C21B.DI1 THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in (to clk_apv_c)
+ --------
+ 3.465 (30.9% logic, 69.1% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C1.CLKI CLK100M_c
+CK2OUT_DEL --- 7.500 *L_R103C1.CLKI to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.469 *_R103C1.CLKOP to R55C47A.CLK sysclk_c
+ --------
+ 11.098 (73.6% logic, 26.4% route), 2 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.469 *_R103C3.CLKOP to R69C21B.CLK clk_apv_c
+ --------
+ 3.598 (18.5% logic, 81.5% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CK2OUT_DEL --- 7.500 *_R103C1.CLKFB to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.575 *_R103C1.CLKOP to *_R103C1.CLKFB sysclk_c
+ --------
+ 9.075 (82.6% logic, 17.4% route), 1 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.575 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 1.575 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 1.514ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_RESET_HANDLER/final_reset_1 (from sysclk_c +)
+ Destination: FF Data in THE_ADC0_CROSSOVER/THE_RESET_STATE_SYNC/sync_0 (to clk_apv_c +)
+
+ Delay: 3.415ns (14.8% logic, 85.2% route), 2 logic levels.
+
+ Constraint Details:
+
+ 3.415ns physical path delay THE_RESET_HANDLER/SLICE_8044 to THE_ADC0_CROSSOVER/SLICE_4509 meets
+ 5.000ns delay constraint less
+ 7.500ns skew and
+ -7.500ns feedback compensation and
+ 0.071ns DIN_SET requirement (totaling 4.929ns) by 1.514ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R38C69A.CLK to R38C69A.Q0 THE_RESET_HANDLER/SLICE_8044 (from sysclk_c)
+ROUTE 90 2.908 R38C69A.Q0 to R64C33B.D0 THE_RESET_HANDLER_final_reset_1
+CTOF_DEL --- 0.198 R64C33B.D0 to R64C33B.F0 THE_ADC0_CROSSOVER/SLICE_4509
+ROUTE 1 0.000 R64C33B.F0 to R64C33B.DI0 THE_ADC0_CROSSOVER/N_11 (to clk_apv_c)
+ --------
+ 3.415 (14.8% logic, 85.2% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C1.CLKI CLK100M_c
+CK2OUT_DEL --- 7.500 *L_R103C1.CLKI to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.469 *_R103C1.CLKOP to R38C69A.CLK sysclk_c
+ --------
+ 11.098 (73.6% logic, 26.4% route), 2 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.469 *_R103C3.CLKOP to R64C33B.CLK clk_apv_c
+ --------
+ 3.598 (18.5% logic, 81.5% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CK2OUT_DEL --- 7.500 *_R103C1.CLKFB to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.575 *_R103C1.CLKOP to *_R103C1.CLKFB sysclk_c
+ --------
+ 9.075 (82.6% logic, 17.4% route), 1 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.575 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 1.575 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 1.529ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_SLAVE_BUS/THE_ADC_LVL_REG/reg_slv_data_in_18 (from sysclk_c +)
+ Destination: FF Data in THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/bit_low (to clk_apv_c +)
+
+ Delay: 3.400ns (33.9% logic, 66.1% route), 5 logic levels.
+
+ Constraint Details:
+
+ 3.400ns physical path delay THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10753 to THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1332 meets
+ 5.000ns delay constraint less
+ 7.500ns skew and
+ -7.500ns feedback compensation and
+ 0.071ns DIN_SET requirement (totaling 4.929ns) by 1.529ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C45B.CLK to R56C45B.Q0 THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10753 (from sysclk_c)
+ROUTE 17 2.247 R56C45B.Q0 to R69C20B.A1 ctrl_lvl_18
+C1TOFCO_DE --- 0.369 R69C20B.A1 to R69C20B.FCO THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1335
+ROUTE 1 0.000 R69C20B.FCO to R69C20C.FCI THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_6
+FCITOFCO_D --- 0.081 R69C20C.FCI to R69C20C.FCO THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1334
+ROUTE 1 0.000 R69C20C.FCO to R69C21A.FCI THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_8
+FCITOFCO_D --- 0.081 R69C21A.FCI to R69C21A.FCO THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1333
+ROUTE 1 0.000 R69C21A.FCO to R69C21B.FCI THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_10
+FCITOF1_DE --- 0.313 R69C21B.FCI to R69C21B.F1 THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1332
+ROUTE 1 0.000 R69C21B.F1 to R69C21B.DI1 THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in (to clk_apv_c)
+ --------
+ 3.400 (33.9% logic, 66.1% route), 5 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C1.CLKI CLK100M_c
+CK2OUT_DEL --- 7.500 *L_R103C1.CLKI to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.469 *_R103C1.CLKOP to R56C45B.CLK sysclk_c
+ --------
+ 11.098 (73.6% logic, 26.4% route), 2 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.469 *_R103C3.CLKOP to R69C21B.CLK clk_apv_c
+ --------
+ 3.598 (18.5% logic, 81.5% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CK2OUT_DEL --- 7.500 *_R103C1.CLKFB to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.575 *_R103C1.CLKOP to *_R103C1.CLKFB sysclk_c
+ --------
+ 9.075 (82.6% logic, 17.4% route), 1 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.575 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 1.575 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 1.537ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_SLAVE_BUS/THE_ADC_LVL_REG/reg_slv_data_in_9 (from sysclk_c +)
+ Destination: FF Data in THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/fl_high (to clk_apv_c +)
+
+ Delay: 3.392ns (36.1% logic, 63.9% route), 5 logic levels.
+
+ Constraint Details:
+
+ 3.392ns physical path delay THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10748 to THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1351 meets
+ 5.000ns delay constraint less
+ 7.500ns skew and
+ -7.500ns feedback compensation and
+ 0.071ns DIN_SET requirement (totaling 4.929ns) by 1.537ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R50C34A.CLK to R50C34A.Q1 THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10748 (from sysclk_c)
+ROUTE 17 2.168 R50C34A.Q1 to R63C18B.A0 ctrl_lvl_9
+C0TOFCO_DE --- 0.440 R63C18B.A0 to R63C18B.FCO THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1354
+ROUTE 1 0.000 R63C18B.FCO to R63C18C.FCI THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_in_cry_6
+FCITOFCO_D --- 0.081 R63C18C.FCI to R63C18C.FCO THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1353
+ROUTE 1 0.000 R63C18C.FCO to R63C19A.FCI THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_in_cry_8
+FCITOFCO_D --- 0.081 R63C19A.FCI to R63C19A.FCO THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1352
+ROUTE 1 0.000 R63C19A.FCO to R63C19B.FCI THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_in_cry_10
+FCITOF1_DE --- 0.313 R63C19B.FCI to R63C19B.F1 THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1351
+ROUTE 1 0.000 R63C19B.F1 to R63C19B.DI1 THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/un1_adc_raw_in (to clk_apv_c)
+ --------
+ 3.392 (36.1% logic, 63.9% route), 5 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C1.CLKI CLK100M_c
+CK2OUT_DEL --- 7.500 *L_R103C1.CLKI to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.469 *_R103C1.CLKOP to R50C34A.CLK sysclk_c
+ --------
+ 11.098 (73.6% logic, 26.4% route), 2 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.469 *_R103C3.CLKOP to R63C19B.CLK clk_apv_c
+ --------
+ 3.598 (18.5% logic, 81.5% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CK2OUT_DEL --- 7.500 *_R103C1.CLKFB to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.575 *_R103C1.CLKOP to *_R103C1.CLKFB sysclk_c
+ --------
+ 9.075 (82.6% logic, 17.4% route), 1 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.575 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 1.575 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 1.538ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_SLAVE_BUS/THE_ADC_LVL_REG/reg_slv_data_in_3 (from sysclk_c +)
+ Destination: FF Data in THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/fl_low (to clk_apv_c +)
+
+ Delay: 3.391ns (33.7% logic, 66.3% route), 4 logic levels.
+
+ Constraint Details:
+
+ 3.391ns physical path delay THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10745 to THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1376 meets
+ 5.000ns delay constraint less
+ 7.500ns skew and
+ -7.500ns feedback compensation and
+ 0.071ns DIN_SET requirement (totaling 4.929ns) by 1.538ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R52C34C.CLK to R52C34C.Q1 THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10745 (from sysclk_c)
+ROUTE 17 2.248 R52C34C.Q1 to R65C15B.B0 ctrl_lvl_3
+C0TOFCO_DE --- 0.440 R65C15B.B0 to R65C15B.FCO THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1378
+ROUTE 1 0.000 R65C15B.FCO to R65C15C.FCI THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_cry_8
+FCITOFCO_D --- 0.081 R65C15C.FCI to R65C15C.FCO THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1377
+ROUTE 1 0.000 R65C15C.FCO to R65C16A.FCI THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2_cry_10
+FCITOF1_DE --- 0.313 R65C16A.FCI to R65C16A.F1 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1376
+ROUTE 1 0.000 R65C16A.F1 to R65C16A.DI1 THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_LOCKER/THE_APV_DIGITAL/next_fl_low2 (to clk_apv_c)
+ --------
+ 3.391 (33.7% logic, 66.3% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C1.CLKI CLK100M_c
+CK2OUT_DEL --- 7.500 *L_R103C1.CLKI to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.469 *_R103C1.CLKOP to R52C34C.CLK sysclk_c
+ --------
+ 11.098 (73.6% logic, 26.4% route), 2 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.469 *_R103C3.CLKOP to R65C16A.CLK clk_apv_c
+ --------
+ 3.598 (18.5% logic, 81.5% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CK2OUT_DEL --- 7.500 *_R103C1.CLKFB to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.575 *_R103C1.CLKOP to *_R103C1.CLKFB sysclk_c
+ --------
+ 9.075 (82.6% logic, 17.4% route), 1 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.575 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 1.575 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 1.539ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_SLAVE_BUS/THE_ADC_LVL_REG/reg_slv_data_in_19 (from sysclk_c +)
+ Destination: FF Data in THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/bit_low (to clk_apv_c +)
+
+ Delay: 3.390ns (33.7% logic, 66.3% route), 4 logic levels.
+
+ Constraint Details:
+
+ 3.390ns physical path delay THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10753 to THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1332 meets
+ 5.000ns delay constraint less
+ 7.500ns skew and
+ -7.500ns feedback compensation and
+ 0.071ns DIN_SET requirement (totaling 4.929ns) by 1.539ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C45B.CLK to R56C45B.Q1 THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10753 (from sysclk_c)
+ROUTE 17 2.247 R56C45B.Q1 to R69C20C.A0 ctrl_lvl_19
+C0TOFCO_DE --- 0.440 R69C20C.A0 to R69C20C.FCO THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1334
+ROUTE 1 0.000 R69C20C.FCO to R69C21A.FCI THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_8
+FCITOFCO_D --- 0.081 R69C21A.FCI to R69C21A.FCO THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1333
+ROUTE 1 0.000 R69C21A.FCO to R69C21B.FCI THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_10
+FCITOF1_DE --- 0.313 R69C21B.FCI to R69C21B.F1 THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1332
+ROUTE 1 0.000 R69C21B.F1 to R69C21B.DI1 THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in (to clk_apv_c)
+ --------
+ 3.390 (33.7% logic, 66.3% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C1.CLKI CLK100M_c
+CK2OUT_DEL --- 7.500 *L_R103C1.CLKI to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.469 *_R103C1.CLKOP to R56C45B.CLK sysclk_c
+ --------
+ 11.098 (73.6% logic, 26.4% route), 2 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.469 *_R103C3.CLKOP to R69C21B.CLK clk_apv_c
+ --------
+ 3.598 (18.5% logic, 81.5% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CK2OUT_DEL --- 7.500 *_R103C1.CLKFB to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.575 *_R103C1.CLKOP to *_R103C1.CLKFB sysclk_c
+ --------
+ 9.075 (82.6% logic, 17.4% route), 1 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.575 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 1.575 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 1.549ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_SLAVE_BUS/THE_ADC_LVL_REG/reg_slv_data_in_24 (from sysclk_c +)
+ Destination: FF Data in THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/bit_high (to clk_apv_c +)
+
+ Delay: 3.380ns (36.5% logic, 63.5% route), 6 logic levels.
+
+ Constraint Details:
+
+ 3.380ns physical path delay THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10756 to THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1413 meets
+ 5.000ns delay constraint less
+ 7.500ns skew and
+ -7.500ns feedback compensation and
+ 0.071ns DIN_SET requirement (totaling 4.929ns) by 1.549ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R59C40A.CLK to R59C40A.Q0 THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10756 (from sysclk_c)
+ROUTE 17 2.146 R59C40A.Q0 to R61C17C.B1 ctrl_lvl_24
+C1TOFCO_DE --- 0.369 R61C17C.B1 to R61C17C.FCO THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1417
+ROUTE 1 0.000 R61C17C.FCO to R61C18A.FCI THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high2_cry_4
+FCITOFCO_D --- 0.081 R61C18A.FCI to R61C18A.FCO THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1416
+ROUTE 1 0.000 R61C18A.FCO to R61C18B.FCI THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high2_cry_6
+FCITOFCO_D --- 0.081 R61C18B.FCI to R61C18B.FCO THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1415
+ROUTE 1 0.000 R61C18B.FCO to R61C18C.FCI THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high2_cry_8
+FCITOFCO_D --- 0.081 R61C18C.FCI to R61C18C.FCO THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1414
+ROUTE 1 0.000 R61C18C.FCO to R61C19A.FCI THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high2_cry_10
+FCITOF1_DE --- 0.313 R61C19A.FCI to R61C19A.F1 THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1413
+ROUTE 1 0.000 R61C19A.F1 to R61C19A.DI1 THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_LOCKER/THE_APV_DIGITAL/next_bit_high2 (to clk_apv_c)
+ --------
+ 3.380 (36.5% logic, 63.5% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C1.CLKI CLK100M_c
+CK2OUT_DEL --- 7.500 *L_R103C1.CLKI to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.469 *_R103C1.CLKOP to R59C40A.CLK sysclk_c
+ --------
+ 11.098 (73.6% logic, 26.4% route), 2 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.469 *_R103C3.CLKOP to R61C19A.CLK clk_apv_c
+ --------
+ 3.598 (18.5% logic, 81.5% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CK2OUT_DEL --- 7.500 *_R103C1.CLKFB to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.575 *_R103C1.CLKOP to *_R103C1.CLKFB sysclk_c
+ --------
+ 9.075 (82.6% logic, 17.4% route), 1 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.575 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 1.575 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+
+Passed: The following path meets requirements by 1.591ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_SLAVE_BUS/THE_ADC_LVL_REG/reg_slv_data_in_20 (from sysclk_c +)
+ Destination: FF Data in THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/bit_low (to clk_apv_c +)
+
+ Delay: 3.338ns (32.1% logic, 67.9% route), 4 logic levels.
+
+ Constraint Details:
+
+ 3.338ns physical path delay THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10754 to THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1460 meets
+ 5.000ns delay constraint less
+ 7.500ns skew and
+ -7.500ns feedback compensation and
+ 0.071ns DIN_SET requirement (totaling 4.929ns) by 1.591ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R55C47A.CLK to R55C47A.Q0 THE_SLAVE_BUS/THE_ADC_LVL_REG/SLICE_10754 (from sysclk_c)
+ROUTE 17 2.266 R55C47A.Q0 to R68C27C.A1 ctrl_lvl_20
+C1TOFCO_DE --- 0.369 R68C27C.A1 to R68C27C.FCO THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1462
+ROUTE 1 0.000 R68C27C.FCO to R68C28A.FCI THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_8
+FCITOFCO_D --- 0.081 R68C28A.FCI to R68C28A.FCO THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1461
+ROUTE 1 0.000 R68C28A.FCO to R68C28B.FCI THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in_cry_10
+FCITOF1_DE --- 0.313 R68C28B.FCI to R68C28B.F1 THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/SLICE_1460
+ROUTE 1 0.000 R68C28B.F1 to R68C28B.DI1 THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_LOCKER/THE_APV_DIGITAL/adc_raw_in (to clk_apv_c)
+ --------
+ 3.338 (32.1% logic, 67.9% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock Path::
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C1.CLKI CLK100M_c
+CK2OUT_DEL --- 7.500 *L_R103C1.CLKI to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.469 *_R103C1.CLKOP to R55C47A.CLK sysclk_c
+ --------
+ 11.098 (73.6% logic, 26.4% route), 2 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock Path:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AJ14.PAD to AJ14.PADDI CLK100M
+ROUTE 21 1.465 AJ14.PADDI to *L_R103C3.CLKI CLK100M_c
+CLK2OUT_DE --- 0.000 *L_R103C3.CLKI to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.469 *_R103C3.CLKOP to R68C28B.CLK clk_apv_c
+ --------
+ 3.598 (18.5% logic, 81.5% route), 2 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+ Source Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CK2OUT_DEL --- 7.500 *_R103C1.CLKFB to *_R103C1.CLKOP THE_100M_DLL/dll_100m_0_0
+ROUTE 999 1.575 *_R103C1.CLKOP to *_R103C1.CLKFB sysclk_c
+ --------
+ 9.075 (82.6% logic, 17.4% route), 1 logic levels.
+
+DLL_R103C1.CLKOP attributes: MODE=CIDDLLA
+
+ Destination Clock f/b:
+
+ Name Fanout Delay (ns) Site Resource
+CLKOP_DEL --- 0.000 *_R103C3.CLKFB to *_R103C3.CLKOP THE_40M_PLL/PLLDInst_0
+ROUTE 999 1.575 *_R103C3.CLKOP to *_R103C3.CLKFB clk_apv_c
+ --------
+ 1.575 (0.0% logic, 100.0% route), 1 logic levels.
+
+PLL_R103C3.CLKOP attributes:
+
+Report: 51.653MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "cts_clk40m" 40.000000 MHz ;
+ 1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 24.000ns
+ The internal maximum frequency of the following component is 1000.000 MHz
+
+ Logical Details: Cell type Pin name Component name
+
+ Destination: FSLICE CLK SLICE_11207
+
+ Delay: 1.000ns -- based on Minimum Pulse Width
+
+
+Passed: The following path meets requirements by 24.246ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q test_reg40m (from cts_clk40m +)
+ Destination: FF Data in test_reg40m (to cts_clk40m +)
+
+ Delay: 0.683ns (74.2% logic, 25.8% route), 2 logic levels.
+
+ Constraint Details:
+
+ 0.683ns physical path delay SLICE_11207 to SLICE_11207 meets
+ 25.000ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 24.929ns) by 24.246ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R53C47C.CLK to R53C47C.Q0 SLICE_11207 (from cts_clk40m)
+ROUTE 2 0.176 R53C47C.Q0 to R53C47C.D0 test_reg40m
+CTOF_DEL --- 0.198 R53C47C.D0 to R53C47C.F0 SLICE_11207
+ROUTE 1 0.000 R53C47C.F0 to R53C47C.DI0 test_reg40m_i (to cts_clk40m)
+ --------
+ 0.683 (74.2% logic, 25.8% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.469ns PLL_R103C126.CLKOP to R53C47C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 1.469ns PLL_R103C126.CLKOP to R53C47C.CLK
+
+Report: 1000.000MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "sysclk_c" 100.000000 MHz ;
+ 4096 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.733ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: DP16KB Port THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2(ASIC) (from sysclk_c +)
+ Destination: FF Data in THE_IPU_STAGE/ipu_out_data_8 (to sysclk_c +)
+
+ Delay: 9.090ns (41.3% logic, 58.7% route), 6 logic levels.
+
+ Constraint Details:
+
+ 9.090ns physical path delay THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2 to THE_IPU_STAGE/SLICE_11038 meets
+ 10.000ns delay constraint less
+ 0.106ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.823ns) by 0.733ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2Q_DEL --- 2.752 *_R36C110.CLKB to *_R36C110.DOB8 THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2 (from sysclk_c)
+ROUTE 1 1.470 *_R36C110.DOB8 to R34C99B.C0 THE_IPU_STAGE/fifo_out_data_11_8
+CTOF_DEL --- 0.198 R34C99B.C0 to R34C99B.F0 THE_IPU_STAGE/SLICE_13887
+ROUTE 1 1.719 R34C99B.F0 to R25C73A.M0 THE_IPU_STAGE/m282_e_0_3
+MTOOFX_DEL --- 0.207 R25C73A.M0 to R25C73A.OFX0 THE_IPU_STAGE/SLICE_11864
+ROUTE 1 1.017 R25C73A.OFX0 to R25C66B.D0 THE_IPU_STAGE/m282_e_0_6
+CTOF_DEL --- 0.198 R25C66B.D0 to R25C66B.F0 THE_IPU_STAGE/SLICE_12729
+ROUTE 1 0.958 R25C66B.F0 to R25C80A.C0 THE_IPU_STAGE/ipu_out_data_RNO_2_8
+CTOF_DEL --- 0.198 R25C80A.C0 to R25C80A.F0 THE_IPU_STAGE/SLICE_12618
+ROUTE 1 0.175 R25C80A.F0 to R25C80B.D0 THE_IPU_STAGE/N_283_i_1
+CTOF_DEL --- 0.198 R25C80B.D0 to R25C80B.F0 THE_IPU_STAGE/SLICE_11038
+ROUTE 1 0.000 R25C80B.F0 to R25C80B.DI0 THE_IPU_STAGE/N_283_i (to sysclk_c)
+ --------
+ 9.090 (41.3% logic, 58.7% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R36C110.CLKB
+
+ Destination Clock :
+ Delay Connection
+ 1.469ns DLL_R103C1.CLKOP to R25C80B.CLK
+
+
+Passed: The following path meets requirements by 0.814ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: DP16KB Port THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1(ASIC) (from sysclk_c +)
+ Destination: FF Data in THE_IPU_STAGE/ipu_out_data_12 (to sysclk_c +)
+
+ Delay: 9.009ns (41.6% logic, 58.4% route), 6 logic levels.
+
+ Constraint Details:
+
+ 9.009ns physical path delay THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1 to THE_IPU_STAGE/SLICE_11040 meets
+ 10.000ns delay constraint less
+ 0.106ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.823ns) by 0.814ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2Q_DEL --- 2.752 *_R36C113.CLKB to *_R36C113.DOB3 THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1 (from sysclk_c)
+ROUTE 1 1.562 *_R36C113.DOB3 to R28C102B.B0 THE_IPU_STAGE/fifo_out_data_0_12
+CTOF_DEL --- 0.198 R28C102B.B0 to R28C102B.F0 THE_IPU_STAGE/SLICE_13881
+ROUTE 1 1.206 R28C102B.F0 to R28C79B.M0 THE_IPU_STAGE/m350_e_0_3
+MTOOFX_DEL --- 0.207 R28C79B.M0 to R28C79B.OFX0 THE_IPU_STAGE/SLICE_11866
+ROUTE 1 1.017 R28C79B.OFX0 to R29C67A.D0 THE_IPU_STAGE/m350_e_0_6
+CTOF_DEL --- 0.198 R29C67A.D0 to R29C67A.F0 THE_IPU_STAGE/SLICE_12731
+ROUTE 1 1.051 R29C67A.F0 to R31C76A.B0 THE_IPU_STAGE/ipu_out_data_RNO_2_12
+CTOF_DEL --- 0.198 R31C76A.B0 to R31C76A.F0 THE_IPU_STAGE/SLICE_12616
+ROUTE 1 0.422 R31C76A.F0 to R32C76C.D0 THE_IPU_STAGE/N_2632_i_1
+CTOF_DEL --- 0.198 R32C76C.D0 to R32C76C.F0 THE_IPU_STAGE/SLICE_11040
+ROUTE 1 0.000 R32C76C.F0 to R32C76C.DI0 THE_IPU_STAGE/N_2632_i (to sysclk_c)
+ --------
+ 9.009 (41.6% logic, 58.4% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R36C113.CLKB
+
+ Destination Clock :
+ Delay Connection
+ 1.469ns DLL_R103C1.CLKOP to R32C76C.CLK
+
+
+Passed: The following path meets requirements by 0.887ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: DP16KB Port THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2(ASIC) (from sysclk_c +)
+ Destination: FF Data in THE_IPU_STAGE/ipu_out_data_2 (to sysclk_c +)
+
+ Delay: 8.936ns (42.0% logic, 58.0% route), 6 logic levels.
+
+ Constraint Details:
+
+ 8.936ns physical path delay THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2 to THE_IPU_STAGE/SLICE_11035 meets
+ 10.000ns delay constraint less
+ 0.106ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.823ns) by 0.887ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2Q_DEL --- 2.752 *_R36C110.CLKB to *_R36C110.DOB2 THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2 (from sysclk_c)
+ROUTE 1 1.883 *_R36C110.DOB2 to R35C98A.C0 THE_IPU_STAGE/fifo_out_data_11_2
+CTOF_DEL --- 0.198 R35C98A.C0 to R35C98A.F0 THE_IPU_STAGE/SLICE_13890
+ROUTE 1 1.642 R35C98A.F0 to R31C68C.M0 THE_IPU_STAGE/m180_e_0_3
+MTOOFX_DEL --- 0.207 R31C68C.M0 to R31C68C.OFX0 THE_IPU_STAGE/SLICE_11861
+ROUTE 1 0.422 R31C68C.OFX0 to R31C67A.D0 THE_IPU_STAGE/m180_e_0_6
+CTOF_DEL --- 0.198 R31C67A.D0 to R31C67A.F0 THE_IPU_STAGE/SLICE_12726
+ROUTE 1 0.833 R31C67A.F0 to R30C73A.B0 THE_IPU_STAGE/ipu_out_data_RNO_2_2
+CTOF_DEL --- 0.198 R30C73A.B0 to R30C73A.F0 THE_IPU_STAGE/SLICE_12621
+ROUTE 1 0.405 R30C73A.F0 to R29C73C.D0 THE_IPU_STAGE/N_181_0_i_1
+CTOF_DEL --- 0.198 R29C73C.D0 to R29C73C.F0 THE_IPU_STAGE/SLICE_11035
+ROUTE 1 0.000 R29C73C.F0 to R29C73C.DI0 THE_IPU_STAGE/N_181_0_i (to sysclk_c)
+ --------
+ 8.936 (42.0% logic, 58.0% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R36C110.CLKB
+
+ Destination Clock :
+ Delay Connection
+ 1.469ns DLL_R103C1.CLKOP to R29C73C.CLK
+
+
+Passed: The following path meets requirements by 0.902ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: DP16KB Port THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1(ASIC) (from sysclk_c +)
+ Destination: FF Data in THE_IPU_STAGE/ipu_out_data_12 (to sysclk_c +)
+
+ Delay: 8.921ns (41.2% logic, 58.8% route), 5 logic levels.
+
+ Constraint Details:
+
+ 8.921ns physical path delay THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1 to THE_IPU_STAGE/SLICE_11040 meets
+ 10.000ns delay constraint less
+ 0.106ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.823ns) by 0.902ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2Q_DEL --- 2.752 *R_R10C35.CLKB to *R_R10C35.DOB3 THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1 (from sysclk_c)
+ROUTE 1 2.754 *R_R10C35.DOB3 to R28C79B.D1 THE_IPU_STAGE/fifo_out_data_7_12
+CTOOFX_DEL --- 0.331 R28C79B.D1 to R28C79B.OFX0 THE_IPU_STAGE/SLICE_11866
+ROUTE 1 1.017 R28C79B.OFX0 to R29C67A.D0 THE_IPU_STAGE/m350_e_0_6
+CTOF_DEL --- 0.198 R29C67A.D0 to R29C67A.F0 THE_IPU_STAGE/SLICE_12731
+ROUTE 1 1.051 R29C67A.F0 to R31C76A.B0 THE_IPU_STAGE/ipu_out_data_RNO_2_12
+CTOF_DEL --- 0.198 R31C76A.B0 to R31C76A.F0 THE_IPU_STAGE/SLICE_12616
+ROUTE 1 0.422 R31C76A.F0 to R32C76C.D0 THE_IPU_STAGE/N_2632_i_1
+CTOF_DEL --- 0.198 R32C76C.D0 to R32C76C.F0 THE_IPU_STAGE/SLICE_11040
+ROUTE 1 0.000 R32C76C.F0 to R32C76C.DI0 THE_IPU_STAGE/N_2632_i (to sysclk_c)
+ --------
+ 8.921 (41.2% logic, 58.8% route), 5 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R10C35.CLKB
+
+ Destination Clock :
+ Delay Connection
+ 1.469ns DLL_R103C1.CLKOP to R32C76C.CLK
+
+
+Passed: The following path meets requirements by 0.907ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: DP16KB Port THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1(ASIC) (from sysclk_c +)
+ Destination: FF Data in THE_IPU_STAGE/ipu_out_data_12 (to sysclk_c +)
+
+ Delay: 8.916ns (42.1% logic, 57.9% route), 6 logic levels.
+
+ Constraint Details:
+
+ 8.916ns physical path delay THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1 to THE_IPU_STAGE/SLICE_11040 meets
+ 10.000ns delay constraint less
+ 0.106ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.823ns) by 0.907ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2Q_DEL --- 2.752 *_R10C107.CLKB to *_R10C107.DOB3 THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1 (from sysclk_c)
+ROUTE 1 1.469 *_R10C107.DOB3 to R28C102B.D0 THE_IPU_STAGE/fifo_out_data_11_12
+CTOF_DEL --- 0.198 R28C102B.D0 to R28C102B.F0 THE_IPU_STAGE/SLICE_13881
+ROUTE 1 1.206 R28C102B.F0 to R28C79B.M0 THE_IPU_STAGE/m350_e_0_3
+MTOOFX_DEL --- 0.207 R28C79B.M0 to R28C79B.OFX0 THE_IPU_STAGE/SLICE_11866
+ROUTE 1 1.017 R28C79B.OFX0 to R29C67A.D0 THE_IPU_STAGE/m350_e_0_6
+CTOF_DEL --- 0.198 R29C67A.D0 to R29C67A.F0 THE_IPU_STAGE/SLICE_12731
+ROUTE 1 1.051 R29C67A.F0 to R31C76A.B0 THE_IPU_STAGE/ipu_out_data_RNO_2_12
+CTOF_DEL --- 0.198 R31C76A.B0 to R31C76A.F0 THE_IPU_STAGE/SLICE_12616
+ROUTE 1 0.422 R31C76A.F0 to R32C76C.D0 THE_IPU_STAGE/N_2632_i_1
+CTOF_DEL --- 0.198 R32C76C.D0 to R32C76C.F0 THE_IPU_STAGE/SLICE_11040
+ROUTE 1 0.000 R32C76C.F0 to R32C76C.DI0 THE_IPU_STAGE/N_2632_i (to sysclk_c)
+ --------
+ 8.916 (42.1% logic, 57.9% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R10C107.CLKB
+
+ Destination Clock :
+ Delay Connection
+ 1.469ns DLL_R103C1.CLKOP to R32C76C.CLK
+
+
+Passed: The following path meets requirements by 0.918ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: DP16KB Port THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2(ASIC) (from sysclk_c +)
+ Destination: FF Data in THE_IPU_STAGE/ipu_out_data_6 (to sysclk_c +)
+
+ Delay: 8.905ns (42.1% logic, 57.9% route), 6 logic levels.
+
+ Constraint Details:
+
+ 8.905ns physical path delay THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2 to THE_IPU_STAGE/SLICE_11037 meets
+ 10.000ns delay constraint less
+ 0.106ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.823ns) by 0.918ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2Q_DEL --- 2.752 *_R36C110.CLKB to *_R36C110.DOB6 THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2 (from sysclk_c)
+ROUTE 1 1.361 *_R36C110.DOB6 to R35C99B.B0 THE_IPU_STAGE/fifo_out_data_11_6
+CTOF_DEL --- 0.198 R35C99B.B0 to R35C99B.F0 THE_IPU_STAGE/SLICE_13893
+ROUTE 1 1.424 R35C99B.F0 to R30C75A.M0 THE_IPU_STAGE/m248_e_0_3
+MTOOFX_DEL --- 0.207 R30C75A.M0 to R30C75A.OFX0 THE_IPU_STAGE/SLICE_11863
+ROUTE 1 0.799 R30C75A.OFX0 to R30C70D.D0 THE_IPU_STAGE/m248_e_0_6
+CTOF_DEL --- 0.198 R30C70D.D0 to R30C70D.F0 THE_IPU_STAGE/SLICE_12728
+ROUTE 1 1.395 R30C70D.F0 to R31C83A.C0 THE_IPU_STAGE/ipu_out_data_RNO_2_6
+CTOF_DEL --- 0.198 R31C83A.C0 to R31C83A.F0 THE_IPU_STAGE/SLICE_12619
+ROUTE 1 0.175 R31C83A.F0 to R31C83B.D0 THE_IPU_STAGE/N_249_i_1
+CTOF_DEL --- 0.198 R31C83B.D0 to R31C83B.F0 THE_IPU_STAGE/SLICE_11037
+ROUTE 1 0.000 R31C83B.F0 to R31C83B.DI0 THE_IPU_STAGE/N_249_i (to sysclk_c)
+ --------
+ 8.905 (42.1% logic, 57.9% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R36C110.CLKB
+
+ Destination Clock :
+ Delay Connection
+ 1.469ns DLL_R103C1.CLKOP to R31C83B.CLK
+
+
+Passed: The following path meets requirements by 0.966ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: DP16KB Port THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1(ASIC) (from sysclk_c +)
+ Destination: FF Data in THE_IPU_STAGE/ipu_out_data_10 (to sysclk_c +)
+
+ Delay: 8.857ns (42.2% logic, 57.8% route), 6 logic levels.
+
+ Constraint Details:
+
+ 8.857ns physical path delay THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1 to THE_IPU_STAGE/SLICE_11039 meets
+ 10.000ns delay constraint less
+ 0.106ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.823ns) by 0.966ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2Q_DEL --- 2.752 *R_R10C26.CLKB to *R_R10C26.DOB1 THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1 (from sysclk_c)
+ROUTE 1 3.313 *R_R10C26.DOB1 to R24C71C.D0 THE_IPU_STAGE/fifo_out_data_12_10
+CTOF_DEL --- 0.198 R24C71C.D0 to R24C71C.F0 THE_IPU_STAGE/SLICE_13858
+ROUTE 1 0.727 R24C71C.F0 to R25C77B.D0 THE_IPU_STAGE/m293_e_0_1
+CTOF_DEL --- 0.198 R25C77B.D0 to R25C77B.F0 THE_IPU_STAGE/SLICE_12719
+ROUTE 1 0.347 R25C77B.F0 to R25C76C.D1 THE_IPU_STAGE/ipu_out_data_RNO_3_10
+CTOF_DEL --- 0.198 R25C76C.D1 to R25C76C.F1 THE_IPU_STAGE/SLICE_12617
+ROUTE 1 0.306 R25C76C.F1 to R25C76C.D0 THE_IPU_STAGE/N_294
+CTOF_DEL --- 0.198 R25C76C.D0 to R25C76C.F0 THE_IPU_STAGE/SLICE_12617
+ROUTE 1 0.422 R25C76C.F0 to R26C76B.D0 THE_IPU_STAGE/N_2614_i_1
+CTOF_DEL --- 0.198 R26C76B.D0 to R26C76B.F0 THE_IPU_STAGE/SLICE_11039
+ROUTE 1 0.000 R26C76B.F0 to R26C76B.DI0 THE_IPU_STAGE/N_2614_i (to sysclk_c)
+ --------
+ 8.857 (42.2% logic, 57.8% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R10C26.CLKB
+
+ Destination Clock :
+ Delay Connection
+ 1.469ns DLL_R103C1.CLKOP to R26C76B.CLK
+
+
+Passed: The following path meets requirements by 0.989ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: DP16KB Port THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0(ASIC) (from sysclk_c +)
+ Destination: FF Data in THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/FF_25 (to sysclk_c +)
+
+ Delay: 8.834ns (47.9% logic, 52.1% route), 10 logic levels.
+
+ Constraint Details:
+
+ 8.834ns physical path delay THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0 to THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_10999 meets
+ 10.000ns delay constraint less
+ 0.106ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.823ns) by 0.989ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2Q_DEL --- 2.752 *_R10C104.CLKB to *R10C104.DOB10 THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0 (from sysclk_c)
+ROUTE 13 2.284 *R10C104.DOB10 to R24C86A.B0 THE_IPU_STAGE/fifo_ldata_12_10
+CTOF_DEL --- 0.198 R24C86A.B0 to R24C86A.F0 THE_IPU_STAGE/SLICE_12879
+ROUTE 12 2.009 R24C86A.F0 to R16C70B.A0 THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/rden_i
+C0TOFCO_DE --- 0.440 R16C70B.A0 to R16C70B.FCO THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3589
+ROUTE 1 0.000 R16C70B.FCO to R16C70C.FCI THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/co0_1
+FCITOFCO_D --- 0.081 R16C70C.FCI to R16C70C.FCO THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3588
+ROUTE 1 0.000 R16C70C.FCO to R16C71A.FCI THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/co1_1
+FCITOFCO_D --- 0.081 R16C71A.FCI to R16C71A.FCO THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3587
+ROUTE 1 0.000 R16C71A.FCO to R16C71B.FCI THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/co2_1
+FCITOFCO_D --- 0.081 R16C71B.FCI to R16C71B.FCO THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3586
+ROUTE 1 0.000 R16C71B.FCO to R16C71C.FCI THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/co3_1
+FCITOFCO_D --- 0.081 R16C71C.FCI to R16C71C.FCO THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3585
+ROUTE 1 0.000 R16C71C.FCO to R16C72A.FCI THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/co4_1
+FCITOFCO_D --- 0.081 R16C72A.FCI to R16C72A.FCO THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3584
+ROUTE 1 0.000 R16C72A.FCO to R16C72B.FCI THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/cmp_le_1_c
+FCITOF0_DE --- 0.242 R16C72B.FCI to R16C72B.F0 THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3561
+ROUTE 1 0.306 R16C72B.F0 to R16C72C.D0 THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/cmp_le_1
+CTOF_DEL --- 0.198 R16C72C.D0 to R16C72C.F0 THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_10999
+ROUTE 1 0.000 R16C72C.F0 to R16C72C.DI0 THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/empty_d (to sysclk_c)
+ --------
+ 8.834 (47.9% logic, 52.1% route), 10 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R10C104.CLKB
+
+ Destination Clock :
+ Delay Connection
+ 1.469ns DLL_R103C1.CLKOP to R16C72C.CLK
+
+
+Passed: The following path meets requirements by 0.999ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: DP16KB Port THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0(ASIC) (from sysclk_c +)
+ Destination: FF Data in THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/FF_25 (to sysclk_c +)
+
+ Delay: 8.824ns (49.5% logic, 50.5% route), 10 logic levels.
+
+ Constraint Details:
+
+ 8.824ns physical path delay THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0 to THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_11005 meets
+ 10.000ns delay constraint less
+ 0.106ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.823ns) by 0.999ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2Q_DEL --- 2.752 *R_R10C89.CLKB to *_R10C89.DOB10 THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0 (from sysclk_c)
+ROUTE 4 2.973 *_R10C89.DOB10 to R30C69D.A0 THE_IPU_STAGE/fifo_ldata_15_10
+CTOOFX_DEL --- 0.331 R30C69D.A0 to R30C69D.OFX0 THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_11857
+ROUTE 13 0.935 R30C69D.OFX0 to R30C70B.A0 THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/rden_i
+C0TOFCO_DE --- 0.440 R30C70B.A0 to R30C70B.FCO THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3293
+ROUTE 1 0.000 R30C70B.FCO to R30C70C.FCI THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/co0_1
+FCITOFCO_D --- 0.081 R30C70C.FCI to R30C70C.FCO THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3292
+ROUTE 1 0.000 R30C70C.FCO to R30C71A.FCI THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/co1_1
+FCITOFCO_D --- 0.081 R30C71A.FCI to R30C71A.FCO THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3291
+ROUTE 1 0.000 R30C71A.FCO to R30C71B.FCI THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/co2_1
+FCITOFCO_D --- 0.081 R30C71B.FCI to R30C71B.FCO THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3290
+ROUTE 1 0.000 R30C71B.FCO to R30C71C.FCI THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/co3_1
+FCITOFCO_D --- 0.081 R30C71C.FCI to R30C71C.FCO THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3289
+ROUTE 1 0.000 R30C71C.FCO to R30C72A.FCI THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/co4_1
+FCITOFCO_D --- 0.081 R30C72A.FCI to R30C72A.FCO THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3288
+ROUTE 1 0.000 R30C72A.FCO to R30C72B.FCI THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/cmp_le_1_c
+FCITOF0_DE --- 0.242 R30C72B.FCI to R30C72B.F0 THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3265
+ROUTE 1 0.548 R30C72B.F0 to R30C69C.D0 THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/cmp_le_1
+CTOF_DEL --- 0.198 R30C69C.D0 to R30C69C.F0 THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_11005
+ROUTE 1 0.000 R30C69C.F0 to R30C69C.DI0 THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/empty_d (to sysclk_c)
+ --------
+ 8.824 (49.5% logic, 50.5% route), 10 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R10C89.CLKB
+
+ Destination Clock :
+ Delay Connection
+ 1.469ns DLL_R103C1.CLKOP to R30C69C.CLK
+
+
+Passed: The following path meets requirements by 1.106ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: DP16KB Port THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1(ASIC) (from sysclk_c +)
+ Destination: FF Data in THE_IPU_STAGE/ipu_out_data_16 (to sysclk_c +)
+
+ Delay: 8.717ns (43.0% logic, 57.0% route), 6 logic levels.
+
+ Constraint Details:
+
+ 8.717ns physical path delay THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1 to THE_IPU_STAGE/SLICE_11042 meets
+ 10.000ns delay constraint less
+ 0.106ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.823ns) by 1.106ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2Q_DEL --- 2.752 *_R36C113.CLKB to *_R36C113.DOB7 THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1 (from sysclk_c)
+ROUTE 1 1.610 *_R36C113.DOB7 to R19C102B.D0 THE_IPU_STAGE/fifo_out_data_0_16
+CTOF_DEL --- 0.198 R19C102B.D0 to R19C102B.F0 THE_IPU_STAGE/SLICE_13875
+ROUTE 1 1.642 R19C102B.F0 to R19C68C.M0 THE_IPU_STAGE/m40_s_e_3
+MTOOFX_DEL --- 0.207 R19C68C.M0 to R19C68C.OFX0 THE_IPU_STAGE/SLICE_11859
+ROUTE 1 0.970 R19C68C.OFX0 to R26C68A.C0 THE_IPU_STAGE/m40_s_e_6
+CTOF_DEL --- 0.198 R26C68A.C0 to R26C68A.F0 THE_IPU_STAGE/SLICE_12724
+ROUTE 1 0.175 R26C68A.F0 to R26C68B.D0 THE_IPU_STAGE/ipu_out_data_RNO_2_16
+CTOF_DEL --- 0.198 R26C68B.D0 to R26C68B.F0 THE_IPU_STAGE/SLICE_12612
+ROUTE 1 0.569 R26C68B.F0 to R26C74C.D0 THE_IPU_STAGE/m40_s_1
+CTOF_DEL --- 0.198 R26C74C.D0 to R26C74C.F0 THE_IPU_STAGE/SLICE_11042
+ROUTE 1 0.000 R26C74C.F0 to R26C74C.DI0 THE_IPU_STAGE/N_41_0 (to sysclk_c)
+ --------
+ 8.717 (43.0% logic, 57.0% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R36C113.CLKB
+
+ Destination Clock :
+ Delay Connection
+ 1.469ns DLL_R103C1.CLKOP to R26C74C.CLK
+
+
+Passed: The following path meets requirements by 1.106ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: DP16KB Port THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2(ASIC) (from sysclk_c +)
+ Destination: FF Data in THE_IPU_STAGE/ipu_out_data_8 (to sysclk_c +)
+
+ Delay: 8.717ns (43.0% logic, 57.0% route), 6 logic levels.
+
+ Constraint Details:
+
+ 8.717ns physical path delay THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2 to THE_IPU_STAGE/SLICE_11038 meets
+ 10.000ns delay constraint less
+ 0.106ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.823ns) by 1.106ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2Q_DEL --- 2.752 *_R36C116.CLKB to *_R36C116.DOB8 THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2 (from sysclk_c)
+ROUTE 1 1.097 *_R36C116.DOB8 to R34C99B.D0 THE_IPU_STAGE/fifo_out_data_0_8
+CTOF_DEL --- 0.198 R34C99B.D0 to R34C99B.F0 THE_IPU_STAGE/SLICE_13887
+ROUTE 1 1.719 R34C99B.F0 to R25C73A.M0 THE_IPU_STAGE/m282_e_0_3
+MTOOFX_DEL --- 0.207 R25C73A.M0 to R25C73A.OFX0 THE_IPU_STAGE/SLICE_11864
+ROUTE 1 1.017 R25C73A.OFX0 to R25C66B.D0 THE_IPU_STAGE/m282_e_0_6
+CTOF_DEL --- 0.198 R25C66B.D0 to R25C66B.F0 THE_IPU_STAGE/SLICE_12729
+ROUTE 1 0.958 R25C66B.F0 to R25C80A.C0 THE_IPU_STAGE/ipu_out_data_RNO_2_8
+CTOF_DEL --- 0.198 R25C80A.C0 to R25C80A.F0 THE_IPU_STAGE/SLICE_12618
+ROUTE 1 0.175 R25C80A.F0 to R25C80B.D0 THE_IPU_STAGE/N_283_i_1
+CTOF_DEL --- 0.198 R25C80B.D0 to R25C80B.F0 THE_IPU_STAGE/SLICE_11038
+ROUTE 1 0.000 R25C80B.F0 to R25C80B.DI0 THE_IPU_STAGE/N_283_i (to sysclk_c)
+ --------
+ 8.717 (43.0% logic, 57.0% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R36C116.CLKB
+
+ Destination Clock :
+ Delay Connection
+ 1.469ns DLL_R103C1.CLKOP to R25C80B.CLK
+
+
+Passed: The following path meets requirements by 1.119ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: DP16KB Port THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0(ASIC) (from sysclk_c +)
+ Destination: DP16KB Port THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0(ASIC) (to sysclk_c +)
+
+ Delay: 8.747ns (35.2% logic, 64.8% route), 2 logic levels.
+
+ Constraint Details:
+
+ 8.747ns physical path delay THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0 to THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.134ns CE_SET requirement (totaling 9.866ns) by 1.119ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2Q_DEL --- 2.752 *R_R10C89.CLKB to *_R10C89.DOB10 THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0 (from sysclk_c)
+ROUTE 4 2.973 *_R10C89.DOB10 to R30C69D.A0 THE_IPU_STAGE/fifo_ldata_15_10
+CTOOFX_DEL --- 0.331 R30C69D.A0 to R30C69D.OFX0 THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_11857
+ROUTE 13 2.691 R30C69D.OFX0 to EBR_R36C23.CEB THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/rden_i (to sysclk_c)
+ --------
+ 8.747 (35.2% logic, 64.8% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R10C89.CLKB
+
+ Destination Clock :
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R36C23.CLKB
+
+
+Passed: The following path meets requirements by 1.136ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: DP16KB Port THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0(ASIC) (from sysclk_c +)
+ Destination: DP16KB Port THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1(ASIC) (to sysclk_c +)
+
+ Delay: 8.730ns (35.3% logic, 64.7% route), 2 logic levels.
+
+ Constraint Details:
+
+ 8.730ns physical path delay THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0 to THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1 meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ 0.134ns CE_SET requirement (totaling 9.866ns) by 1.136ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2Q_DEL --- 2.752 *R_R10C89.CLKB to *_R10C89.DOB10 THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0 (from sysclk_c)
+ROUTE 4 2.973 *_R10C89.DOB10 to R30C69D.A0 THE_IPU_STAGE/fifo_ldata_15_10
+CTOOFX_DEL --- 0.331 R30C69D.A0 to R30C69D.OFX0 THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_11857
+ROUTE 13 2.674 R30C69D.OFX0 to EBR_R36C26.CEB THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/rden_i (to sysclk_c)
+ --------
+ 8.730 (35.3% logic, 64.7% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R10C89.CLKB
+
+ Destination Clock :
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R36C26.CLKB
+
+
+Passed: The following path meets requirements by 1.165ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: DP16KB Port THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0(ASIC) (from sysclk_c +)
+ Destination: FF Unknown THE_SLAVE_BUS_THE_SPI_MASTER_THE_SPI_SLIM_tx_sregio_7 (to sysclk_c +)
+
+ Delay: 8.930ns (37.5% logic, 62.5% route), 4 logic levels.
+
+ Constraint Details:
+
+ 8.930ns physical path delay THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0 to U_SPI_SDI_MGIOL meets
+ 10.000ns delay constraint less
+ 0.000ns skew and
+ -0.095ns ONEG0_SET requirement (totaling 10.095ns) by 1.165ns
+
+IOL_B82B attributes: FINE=FDEL0
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2Q_DEL --- 2.752 *R_R49C59.CLKB to *R_R49C59.DOB3 THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0 (from sysclk_c)
+ROUTE 1 1.610 *R_R49C59.DOB3 to R55C81D.D0 THE_SLAVE_BUS/spi_bram_wr_d_7
+CTOF_DEL --- 0.198 R55C81D.D0 to R55C81D.F0 THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13013
+ROUTE 1 0.405 R55C81D.F0 to R55C82D.D0 THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/tx_sregc_6_1
+CTOF_DEL --- 0.198 R55C82D.D0 to R55C82D.F0 THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12572
+ROUTE 1 0.306 R55C82D.F0 to R55C82A.D0 THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/tx_sregc_6_3
+CTOF_DEL --- 0.198 R55C82A.D0 to R55C82A.F0 THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12803
+ROUTE 1 3.263 R55C82A.F0 to IOL_B82B.ONEG0 THE_SLAVE_BUS_THE_SPI_MASTER_THE_SPI_SLIM_tx_sregc_6_i (to sysclk_c)
+ --------
+ 8.930 (37.5% logic, 62.5% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R49C59.CLKB
+
+ Destination Clock :
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to IOL_B82B.CLK
+
+
+Passed: The following path meets requirements by 1.178ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: DP16KB Port THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2(ASIC) (from sysclk_c +)
+ Destination: FF Data in THE_IPU_STAGE/ipu_out_data_6 (to sysclk_c +)
+
+ Delay: 8.645ns (42.5% logic, 57.5% route), 5 logic levels.
+
+ Constraint Details:
+
+ 8.645ns physical path delay THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2 to THE_IPU_STAGE/SLICE_11037 meets
+ 10.000ns delay constraint less
+ 0.106ns skew and
+ 0.071ns DIN_SET requirement (totaling 9.823ns) by 1.178ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2Q_DEL --- 2.752 *R_R10C98.CLKB to *R_R10C98.DOB6 THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2 (from sysclk_c)
+ROUTE 1 2.599 *R_R10C98.DOB6 to R30C75A.B1 THE_IPU_STAGE/fifo_out_data_3_6
+CTOOFX_DEL --- 0.331 R30C75A.B1 to R30C75A.OFX0 THE_IPU_STAGE/SLICE_11863
+ROUTE 1 0.799 R30C75A.OFX0 to R30C70D.D0 THE_IPU_STAGE/m248_e_0_6
+CTOF_DEL --- 0.198 R30C70D.D0 to R30C70D.F0 THE_IPU_STAGE/SLICE_12728
+ROUTE 1 1.395 R30C70D.F0 to R31C83A.C0 THE_IPU_STAGE/ipu_out_data_RNO_2_6
+CTOF_DEL --- 0.198 R31C83A.C0 to R31C83A.F0 THE_IPU_STAGE/SLICE_12619
+ROUTE 1 0.175 R31C83A.F0 to R31C83B.D0 THE_IPU_STAGE/N_249_i_1
+CTOF_DEL --- 0.198 R31C83B.D0 to R31C83B.F0 THE_IPU_STAGE/SLICE_11037
+ROUTE 1 0.000 R31C83B.F0 to R31C83B.DI0 THE_IPU_STAGE/N_249_i (to sysclk_c)
+ --------
+ 8.645 (42.5% logic, 57.5% route), 5 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 1.575ns DLL_R103C1.CLKOP to EBR_R10C98.CLKB
+
+ Destination Clock :
+ Delay Connection
+ 1.469ns DLL_R103C1.CLKOP to R31C83B.CLK
+
+Report: 107.910MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "EXT_IN_c_3" 40.000000 MHz ;
+ 0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD PORT "ADC0_LCLK" 4.166600 nS ;
+ 1273 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 1.234ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_15 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC0_LCLK_c +)
+
+ Delay: 2.861ns (51.9% logic, 48.1% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.861ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4493 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.234ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R72C22C.CLK to R72C22C.Q0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4493 (from ADC0_LCLK_c)
+ROUTE 3 0.784 R72C22C.Q0 to R72C22D.A1 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_w21
+CTOOFX_DEL --- 0.331 R72C22D.A1 to R72C22D.OFX0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_12187
+ROUTE 1 0.593 R72C22D.OFX0 to R70C22B.D0 THE_ADC0_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R70C22B.D0 to R70C22B.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_675
+ROUTE 1 0.000 R70C22B.FCO to R70C22C.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R70C22C.FCI to R70C22C.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_674
+ROUTE 1 0.000 R70C22C.FCO to R70C23A.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R70C23A.FCI to R70C23A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_673
+ROUTE 1 0.000 R70C23A.FCO to R70C23B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R70C23B.FCI to R70C23B.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672
+ROUTE 1 0.000 R70C23B.F0 to R70C23B.DI0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d (to ADC0_LCLK_c)
+ --------
+ 2.861 (51.9% logic, 48.1% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.338ns T3.PADDI to R72C22C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+
+Passed: The following path meets requirements by 1.234ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_15 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC0_LCLK_c +)
+
+ Delay: 2.861ns (51.9% logic, 48.1% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.861ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4493 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.234ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R72C22C.CLK to R72C22C.Q0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4493 (from ADC0_LCLK_c)
+ROUTE 3 0.784 R72C22C.Q0 to R72C22D.A0 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_w21
+CTOOFX_DEL --- 0.331 R72C22D.A0 to R72C22D.OFX0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_12187
+ROUTE 1 0.593 R72C22D.OFX0 to R70C22B.D0 THE_ADC0_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R70C22B.D0 to R70C22B.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_675
+ROUTE 1 0.000 R70C22B.FCO to R70C22C.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R70C22C.FCI to R70C22C.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_674
+ROUTE 1 0.000 R70C22C.FCO to R70C23A.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R70C23A.FCI to R70C23A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_673
+ROUTE 1 0.000 R70C23A.FCO to R70C23B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R70C23B.FCI to R70C23B.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672
+ROUTE 1 0.000 R70C23B.F0 to R70C23B.DI0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d (to ADC0_LCLK_c)
+ --------
+ 2.861 (51.9% logic, 48.1% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.338ns T3.PADDI to R72C22C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+
+Passed: The following path meets requirements by 1.340ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_14 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC0_LCLK_c +)
+
+ Delay: 2.755ns (53.9% logic, 46.1% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.755ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4493 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.340ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R72C22C.CLK to R72C22C.Q1 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4493 (from ADC0_LCLK_c)
+ROUTE 4 0.678 R72C22C.Q1 to R72C22D.B1 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_w22
+CTOOFX_DEL --- 0.331 R72C22D.B1 to R72C22D.OFX0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_12187
+ROUTE 1 0.593 R72C22D.OFX0 to R70C22B.D0 THE_ADC0_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R70C22B.D0 to R70C22B.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_675
+ROUTE 1 0.000 R70C22B.FCO to R70C22C.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R70C22C.FCI to R70C22C.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_674
+ROUTE 1 0.000 R70C22C.FCO to R70C23A.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R70C23A.FCI to R70C23A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_673
+ROUTE 1 0.000 R70C23A.FCO to R70C23B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R70C23B.FCI to R70C23B.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672
+ROUTE 1 0.000 R70C23B.F0 to R70C23B.DI0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d (to ADC0_LCLK_c)
+ --------
+ 2.755 (53.9% logic, 46.1% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.338ns T3.PADDI to R72C22C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+
+Passed: The following path meets requirements by 1.340ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_14 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC0_LCLK_c +)
+
+ Delay: 2.755ns (53.9% logic, 46.1% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.755ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4493 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.340ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R72C22C.CLK to R72C22C.Q1 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4493 (from ADC0_LCLK_c)
+ROUTE 4 0.678 R72C22C.Q1 to R72C22D.B0 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_w22
+CTOOFX_DEL --- 0.331 R72C22D.B0 to R72C22D.OFX0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_12187
+ROUTE 1 0.593 R72C22D.OFX0 to R70C22B.D0 THE_ADC0_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R70C22B.D0 to R70C22B.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_675
+ROUTE 1 0.000 R70C22B.FCO to R70C22C.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R70C22C.FCI to R70C22C.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_674
+ROUTE 1 0.000 R70C22C.FCO to R70C23A.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R70C23A.FCI to R70C23A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_673
+ROUTE 1 0.000 R70C23A.FCO to R70C23B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R70C23B.FCI to R70C23B.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672
+ROUTE 1 0.000 R70C23B.F0 to R70C23B.DI0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d (to ADC0_LCLK_c)
+ --------
+ 2.755 (53.9% logic, 46.1% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.338ns T3.PADDI to R72C22C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+
+Passed: The following path meets requirements by 1.521ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC0_LCLK_c +)
+
+ Delay: 2.574ns (52.9% logic, 47.1% route), 7 logic levels.
+
+ Constraint Details:
+
+ 2.574ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.521ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R70C23B.CLK to R70C23B.Q0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 (from ADC0_LCLK_c)
+ROUTE 1 0.518 R70C23B.Q0 to R70C23C.C0 THE_ADC0_CROSSOVER/THE_CROSSOVER/un1_THE_CROSSOVER_1
+CTOF_DEL --- 0.198 R70C23C.C0 to R70C23C.F0 THE_ADC0_CROSSOVER/SLICE_4510
+ROUTE 35 0.695 R70C23C.F0 to R70C22A.B1 THE_ADC0_CROSSOVER/THE_CROSSOVER/wren_i
+C1TOFCO_DE --- 0.369 R70C22A.B1 to R70C22A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_671
+ROUTE 1 0.000 R70C22A.FCO to R70C22B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/cmp_ci_1
+FCITOFCO_D --- 0.081 R70C22B.FCI to R70C22B.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_675
+ROUTE 1 0.000 R70C22B.FCO to R70C22C.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R70C22C.FCI to R70C22C.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_674
+ROUTE 1 0.000 R70C22C.FCO to R70C23A.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R70C23A.FCI to R70C23A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_673
+ROUTE 1 0.000 R70C23A.FCO to R70C23B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R70C23B.FCI to R70C23B.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672
+ROUTE 1 0.000 R70C23B.F0 to R70C23B.DI0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d (to ADC0_LCLK_c)
+ --------
+ 2.574 (52.9% logic, 47.1% route), 7 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+
+Passed: The following path meets requirements by 1.532ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_12 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC0_LCLK_c +)
+
+ Delay: 2.563ns (57.9% logic, 42.1% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.563ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4494 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.532ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R72C22A.CLK to R72C22A.Q1 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4494 (from ADC0_LCLK_c)
+ROUTE 7 0.486 R72C22A.Q1 to R72C22D.C1 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_w24
+CTOOFX_DEL --- 0.331 R72C22D.C1 to R72C22D.OFX0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_12187
+ROUTE 1 0.593 R72C22D.OFX0 to R70C22B.D0 THE_ADC0_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R70C22B.D0 to R70C22B.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_675
+ROUTE 1 0.000 R70C22B.FCO to R70C22C.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R70C22C.FCI to R70C22C.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_674
+ROUTE 1 0.000 R70C22C.FCO to R70C23A.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R70C23A.FCI to R70C23A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_673
+ROUTE 1 0.000 R70C23A.FCO to R70C23B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R70C23B.FCI to R70C23B.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672
+ROUTE 1 0.000 R70C23B.F0 to R70C23B.DI0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d (to ADC0_LCLK_c)
+ --------
+ 2.563 (57.9% logic, 42.1% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.338ns T3.PADDI to R72C22A.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+
+Passed: The following path meets requirements by 1.532ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_12 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC0_LCLK_c +)
+
+ Delay: 2.563ns (57.9% logic, 42.1% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.563ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4494 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.532ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R72C22A.CLK to R72C22A.Q1 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4494 (from ADC0_LCLK_c)
+ROUTE 7 0.486 R72C22A.Q1 to R72C22D.C0 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_w24
+CTOOFX_DEL --- 0.331 R72C22D.C0 to R72C22D.OFX0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_12187
+ROUTE 1 0.593 R72C22D.OFX0 to R70C22B.D0 THE_ADC0_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R70C22B.D0 to R70C22B.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_675
+ROUTE 1 0.000 R70C22B.FCO to R70C22C.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R70C22C.FCI to R70C22C.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_674
+ROUTE 1 0.000 R70C22C.FCO to R70C23A.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R70C23A.FCI to R70C23A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_673
+ROUTE 1 0.000 R70C23A.FCO to R70C23B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R70C23B.FCI to R70C23B.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672
+ROUTE 1 0.000 R70C23B.F0 to R70C23B.DI0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d (to ADC0_LCLK_c)
+ --------
+ 2.563 (57.9% logic, 42.1% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.338ns T3.PADDI to R72C22A.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+
+Passed: The following path meets requirements by 1.534ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_15 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC0_LCLK_c +)
+
+ Delay: 2.561ns (50.0% logic, 50.0% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.561ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4493 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.534ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R72C22C.CLK to R72C22C.Q0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4493 (from ADC0_LCLK_c)
+ROUTE 3 0.776 R72C22C.Q0 to R72C22C.A0 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_w21
+CTOF_DEL --- 0.198 R72C22C.A0 to R72C22C.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4493
+ROUTE 1 0.505 R72C22C.F0 to R70C22B.D1 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_g2b_xor_cluster_0
+C1TOFCO_DE --- 0.369 R70C22B.D1 to R70C22B.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_675
+ROUTE 1 0.000 R70C22B.FCO to R70C22C.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R70C22C.FCI to R70C22C.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_674
+ROUTE 1 0.000 R70C22C.FCO to R70C23A.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R70C23A.FCI to R70C23A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_673
+ROUTE 1 0.000 R70C23A.FCO to R70C23B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R70C23B.FCI to R70C23B.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672
+ROUTE 1 0.000 R70C23B.F0 to R70C23B.DI0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d (to ADC0_LCLK_c)
+ --------
+ 2.561 (50.0% logic, 50.0% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.338ns T3.PADDI to R72C22C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+
+Passed: The following path meets requirements by 1.604ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_13 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC0_LCLK_c +)
+
+ Delay: 2.491ns (59.6% logic, 40.4% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.491ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4494 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.604ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R72C22A.CLK to R72C22A.Q0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4494 (from ADC0_LCLK_c)
+ROUTE 5 0.414 R72C22A.Q0 to R72C22D.D1 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_w23
+CTOOFX_DEL --- 0.331 R72C22D.D1 to R72C22D.OFX0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_12187
+ROUTE 1 0.593 R72C22D.OFX0 to R70C22B.D0 THE_ADC0_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R70C22B.D0 to R70C22B.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_675
+ROUTE 1 0.000 R70C22B.FCO to R70C22C.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R70C22C.FCI to R70C22C.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_674
+ROUTE 1 0.000 R70C22C.FCO to R70C23A.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R70C23A.FCI to R70C23A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_673
+ROUTE 1 0.000 R70C23A.FCO to R70C23B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R70C23B.FCI to R70C23B.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672
+ROUTE 1 0.000 R70C23B.F0 to R70C23B.DI0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d (to ADC0_LCLK_c)
+ --------
+ 2.491 (59.6% logic, 40.4% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.338ns T3.PADDI to R72C22A.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+
+Passed: The following path meets requirements by 1.604ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_13 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC0_LCLK_c +)
+
+ Delay: 2.491ns (59.6% logic, 40.4% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.491ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4494 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.604ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R72C22A.CLK to R72C22A.Q0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4494 (from ADC0_LCLK_c)
+ROUTE 5 0.414 R72C22A.Q0 to R72C22D.D0 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_w23
+CTOOFX_DEL --- 0.331 R72C22D.D0 to R72C22D.OFX0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_12187
+ROUTE 1 0.593 R72C22D.OFX0 to R70C22B.D0 THE_ADC0_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R70C22B.D0 to R70C22B.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_675
+ROUTE 1 0.000 R70C22B.FCO to R70C22C.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R70C22C.FCI to R70C22C.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_674
+ROUTE 1 0.000 R70C22C.FCO to R70C23A.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R70C23A.FCI to R70C23A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_673
+ROUTE 1 0.000 R70C23A.FCO to R70C23B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R70C23B.FCI to R70C23B.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672
+ROUTE 1 0.000 R70C23B.F0 to R70C23B.DI0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d (to ADC0_LCLK_c)
+ --------
+ 2.491 (59.6% logic, 40.4% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.338ns T3.PADDI to R72C22A.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+
+Passed: The following path meets requirements by 1.614ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_153 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC0_LCLK_c +)
+
+ Delay: 2.481ns (47.9% logic, 52.1% route), 4 logic levels.
+
+ Constraint Details:
+
+ 2.481ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_661 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.614ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R71C23A.CLK to R71C23A.Q0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_661 (from ADC0_LCLK_c)
+ROUTE 6 0.678 R71C23A.Q0 to R71C23C.B0 THE_ADC0_CROSSOVER/THE_CROSSOVER/wcount_4
+CTOF_DEL --- 0.198 R71C23C.B0 to R71C23C.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4508
+ROUTE 1 0.614 R71C23C.F0 to R70C23A.A0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_cmp_set
+C0TOFCO_DE --- 0.440 R70C23A.A0 to R70C23A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_673
+ROUTE 1 0.000 R70C23A.FCO to R70C23B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R70C23B.FCI to R70C23B.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672
+ROUTE 1 0.000 R70C23B.F0 to R70C23B.DI0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d (to ADC0_LCLK_c)
+ --------
+ 2.481 (47.9% logic, 52.1% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.338ns T3.PADDI to R71C23A.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+
+Passed: The following path meets requirements by 1.618ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC0_LCLK_c +)
+
+ Delay: 2.477ns (54.9% logic, 45.1% route), 7 logic levels.
+
+ Constraint Details:
+
+ 2.477ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.618ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R70C23B.CLK to R70C23B.Q0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 (from ADC0_LCLK_c)
+ROUTE 1 0.518 R70C23B.Q0 to R70C23C.C0 THE_ADC0_CROSSOVER/THE_CROSSOVER/un1_THE_CROSSOVER_1
+CTOF_DEL --- 0.198 R70C23C.C0 to R70C23C.F0 THE_ADC0_CROSSOVER/SLICE_4510
+ROUTE 35 0.598 R70C23C.F0 to R70C22A.A1 THE_ADC0_CROSSOVER/THE_CROSSOVER/wren_i
+C1TOFCO_DE --- 0.369 R70C22A.A1 to R70C22A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_671
+ROUTE 1 0.000 R70C22A.FCO to R70C22B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/cmp_ci_1
+FCITOFCO_D --- 0.081 R70C22B.FCI to R70C22B.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_675
+ROUTE 1 0.000 R70C22B.FCO to R70C22C.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R70C22C.FCI to R70C22C.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_674
+ROUTE 1 0.000 R70C22C.FCO to R70C23A.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R70C23A.FCI to R70C23A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_673
+ROUTE 1 0.000 R70C23A.FCO to R70C23B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R70C23B.FCI to R70C23B.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672
+ROUTE 1 0.000 R70C23B.F0 to R70C23B.DI0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d (to ADC0_LCLK_c)
+ --------
+ 2.477 (54.9% logic, 45.1% route), 7 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+
+Passed: The following path meets requirements by 1.637ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_14 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC0_LCLK_c +)
+
+ Delay: 2.458ns (51.7% logic, 48.3% route), 5 logic levels.
+
+ Constraint Details:
+
+ 2.458ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4493 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.637ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R72C22C.CLK to R72C22C.Q1 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4493 (from ADC0_LCLK_c)
+ROUTE 4 0.612 R72C22C.Q1 to R72C22A.B0 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_w22
+CTOF_DEL --- 0.198 R72C22A.B0 to R72C22A.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4494
+ROUTE 1 0.576 R72C22A.F0 to R70C22C.D0 THE_ADC0_CROSSOVER/THE_CROSSOVER/rcount_w2
+C0TOFCO_DE --- 0.440 R70C22C.D0 to R70C22C.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_674
+ROUTE 1 0.000 R70C22C.FCO to R70C23A.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R70C23A.FCI to R70C23A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_673
+ROUTE 1 0.000 R70C23A.FCO to R70C23B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R70C23B.FCI to R70C23B.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672
+ROUTE 1 0.000 R70C23B.F0 to R70C23B.DI0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d (to ADC0_LCLK_c)
+ --------
+ 2.458 (51.7% logic, 48.3% route), 5 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.338ns T3.PADDI to R72C22C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+
+Passed: The following path meets requirements by 1.664ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_HANDLER/synccounter_2 (from ADC0_LCLK_c +)
+ Destination: FF Set/Reset THE_ADC0_HANDLER/sync_high (to ADC0_LCLK_c +)
+
+ Delay: 2.140ns (23.7% logic, 76.3% route), 2 logic levels.
+
+ Constraint Details:
+
+ 2.140ns physical path delay THE_ADC0_HANDLER/SLICE_4692 to THE_ADC0_HANDLER/SLICE_10492 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.362ns LSR_SET requirement (totaling 3.804ns) by 1.664ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R79C11B.CLK to R79C11B.Q0 THE_ADC0_HANDLER/SLICE_4692 (from ADC0_LCLK_c)
+ROUTE 4 0.678 R79C11B.Q0 to R79C11D.B0 THE_ADC0_HANDLER/synccounter_2
+CTOF_DEL --- 0.198 R79C11D.B0 to R79C11D.F0 THE_ADC0_HANDLER/SLICE_13385
+ROUTE 1 0.955 R79C11D.F0 to R79C10A.LSR THE_ADC0_HANDLER/sync_highc_i (to ADC0_LCLK_c)
+ --------
+ 2.140 (23.7% logic, 76.3% route), 2 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.338ns T3.PADDI to R79C11B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.338ns T3.PADDI to R79C10A.CLK
+
+
+Passed: The following path meets requirements by 1.687ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_143 (from ADC0_LCLK_c +)
+ Destination: FF Data in THE_ADC0_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC0_LCLK_c +)
+
+ Delay: 2.408ns (49.4% logic, 50.6% route), 4 logic levels.
+
+ Constraint Details:
+
+ 2.408ns physical path delay THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4508 to THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.687ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R71C23C.CLK to R71C23C.Q0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4508 (from ADC0_LCLK_c)
+ROUTE 2 0.605 R71C23C.Q0 to R71C23C.A0 THE_ADC0_CROSSOVER/THE_CROSSOVER/wptr_4
+CTOF_DEL --- 0.198 R71C23C.A0 to R71C23C.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_4508
+ROUTE 1 0.614 R71C23C.F0 to R70C23A.A0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_cmp_set
+C0TOFCO_DE --- 0.440 R70C23A.A0 to R70C23A.FCO THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_673
+ROUTE 1 0.000 R70C23A.FCO to R70C23B.FCI THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R70C23B.FCI to R70C23B.F0 THE_ADC0_CROSSOVER/THE_CROSSOVER/SLICE_672
+ROUTE 1 0.000 R70C23B.F0 to R70C23B.DI0 THE_ADC0_CROSSOVER/THE_CROSSOVER/full_d (to ADC0_LCLK_c)
+ --------
+ 2.408 (49.4% logic, 50.6% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.338ns T3.PADDI to R71C23C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.338ns T3.PADDI to R70C23B.CLK
+
+Report: 2.932ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: INPUT_SETUP GROUP "ADC0_INPUT" 0.600000 ns HOLD 0.600000 ns CLKPORT "ADC0_LCLK" ; Setup Analysis.
+ 9 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 1.135ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC0_OUT_2
+ Destination: FF Data in THE_ADC0_HANDLER/THE_DIN_2/ud_0 (to ADC0_LCLK_c +)
+ FF THE_ADC0_HANDLER/THE_DIN_2/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.494ns (36.3% logic, 63.7% route), 1 logic levels.
+
+IOL_L95A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC0_OUT_2 to ADC0_OUT_2_MGIOL less
+ 0.600ns offset ADC0_OUT_2 to ADC0_LCLK (totaling 0.064ns) meets
+ 1.494ns delay ADC0_LCLK to ADC0_OUT_2_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.199ns) by 1.135ns
+
+ Physical Path Details:
+
+ Data path ADC0_OUT_2 to ADC0_OUT_2_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AB2.PAD to AB2.PADDI ADC0_OUT_2
+ROUTE 1 0.000 AB2.PADDI to IOL_L95A.DI THE_ADC0_HANDLER/THE_DIN_2/buf_Data0 (to ADC0_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC0_LCLK to ADC0_OUT_2_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.952 T3.PADDI to IOL_L95A.ECLKI ADC0_LCLK_c
+ --------
+ 1.494 (36.3% logic, 63.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.135ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC0_OUT_6
+ Destination: FF Data in THE_ADC0_HANDLER/THE_DIN_6/ud_0 (to ADC0_LCLK_c +)
+ FF THE_ADC0_HANDLER/THE_DIN_6/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.494ns (36.3% logic, 63.7% route), 1 logic levels.
+
+IOL_L70A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC0_OUT_6 to ADC0_OUT_6_MGIOL less
+ 0.600ns offset ADC0_OUT_6 to ADC0_LCLK (totaling 0.064ns) meets
+ 1.494ns delay ADC0_LCLK to ADC0_OUT_6_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.199ns) by 1.135ns
+
+ Physical Path Details:
+
+ Data path ADC0_OUT_6 to ADC0_OUT_6_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 U3.PAD to U3.PADDI ADC0_OUT_6
+ROUTE 1 0.000 U3.PADDI to IOL_L70A.DI THE_ADC0_HANDLER/THE_DIN_6/buf_Data0 (to ADC0_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC0_LCLK to ADC0_OUT_6_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.952 T3.PADDI to IOL_L70A.ECLKI ADC0_LCLK_c
+ --------
+ 1.494 (36.3% logic, 63.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.135ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC0_OUT_5
+ Destination: FF Data in THE_ADC0_HANDLER/THE_DIN_5/ud_0 (to ADC0_LCLK_c +)
+ FF THE_ADC0_HANDLER/THE_DIN_5/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.494ns (36.3% logic, 63.7% route), 1 logic levels.
+
+IOL_L68A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC0_OUT_5 to ADC0_OUT_5_MGIOL less
+ 0.600ns offset ADC0_OUT_5 to ADC0_LCLK (totaling 0.064ns) meets
+ 1.494ns delay ADC0_LCLK to ADC0_OUT_5_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.199ns) by 1.135ns
+
+ Physical Path Details:
+
+ Data path ADC0_OUT_5 to ADC0_OUT_5_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 U5.PAD to U5.PADDI ADC0_OUT_5
+ROUTE 1 0.000 U5.PADDI to IOL_L68A.DI THE_ADC0_HANDLER/THE_DIN_5/buf_Data0 (to ADC0_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC0_LCLK to ADC0_OUT_5_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.952 T3.PADDI to IOL_L68A.ECLKI ADC0_LCLK_c
+ --------
+ 1.494 (36.3% logic, 63.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.135ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC0_ADCLK
+ Destination: FF Data in THE_ADC0_HANDLER/THE_ADC_ADCLK_IN/ud_0 (to ADC0_LCLK_c +)
+ FF THE_ADC0_HANDLER/THE_ADC_ADCLK_IN/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.494ns (36.3% logic, 63.7% route), 1 logic levels.
+
+IOL_L61A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC0_ADCLK to ADC0_ADCLK_MGIOL less
+ 0.600ns offset ADC0_ADCLK to ADC0_LCLK (totaling 0.064ns) meets
+ 1.494ns delay ADC0_LCLK to ADC0_ADCLK_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.199ns) by 1.135ns
+
+ Physical Path Details:
+
+ Data path ADC0_ADCLK to ADC0_ADCLK_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 R3.PAD to R3.PADDI ADC0_ADCLK
+ROUTE 1 0.000 R3.PADDI to IOL_L61A.DI THE_ADC0_HANDLER/THE_ADC_ADCLK_IN/buf_Data0 (to ADC0_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC0_LCLK to ADC0_ADCLK_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.952 T3.PADDI to IOL_L61A.ECLKI ADC0_LCLK_c
+ --------
+ 1.494 (36.3% logic, 63.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.135ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC0_OUT_0
+ Destination: FF Data in THE_ADC0_HANDLER/THE_DIN_0/ud_0 (to ADC0_LCLK_c +)
+ FF THE_ADC0_HANDLER/THE_DIN_0/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.494ns (36.3% logic, 63.7% route), 1 logic levels.
+
+IOL_L104A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC0_OUT_0 to ADC0_OUT_0_MGIOL less
+ 0.600ns offset ADC0_OUT_0 to ADC0_LCLK (totaling 0.064ns) meets
+ 1.494ns delay ADC0_LCLK to ADC0_OUT_0_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.199ns) by 1.135ns
+
+ Physical Path Details:
+
+ Data path ADC0_OUT_0 to ADC0_OUT_0_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AD2.PAD to AD2.PADDI ADC0_OUT_0
+ROUTE 1 0.000 AD2.PADDI to IOL_L104A.DI THE_ADC0_HANDLER/THE_DIN_0/buf_Data0 (to ADC0_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC0_LCLK to ADC0_OUT_0_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.952 T3.PADDI to *L_L104A.ECLKI ADC0_LCLK_c
+ --------
+ 1.494 (36.3% logic, 63.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.135ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC0_OUT_3
+ Destination: FF Data in THE_ADC0_HANDLER/THE_DIN_3/ud_0 (to ADC0_LCLK_c +)
+ FF THE_ADC0_HANDLER/THE_DIN_3/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.494ns (36.3% logic, 63.7% route), 1 logic levels.
+
+IOL_L81A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC0_OUT_3 to ADC0_OUT_3_MGIOL less
+ 0.600ns offset ADC0_OUT_3 to ADC0_LCLK (totaling 0.064ns) meets
+ 1.494ns delay ADC0_LCLK to ADC0_OUT_3_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.199ns) by 1.135ns
+
+ Physical Path Details:
+
+ Data path ADC0_OUT_3 to ADC0_OUT_3_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AA1.PAD to AA1.PADDI ADC0_OUT_3
+ROUTE 1 0.000 AA1.PADDI to IOL_L81A.DI THE_ADC0_HANDLER/THE_DIN_3/buf_Data0 (to ADC0_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC0_LCLK to ADC0_OUT_3_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.952 T3.PADDI to IOL_L81A.ECLKI ADC0_LCLK_c
+ --------
+ 1.494 (36.3% logic, 63.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.135ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC0_OUT_7
+ Destination: FF Data in THE_ADC0_HANDLER/THE_DIN_7/ud_0 (to ADC0_LCLK_c +)
+ FF THE_ADC0_HANDLER/THE_DIN_7/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.494ns (36.3% logic, 63.7% route), 1 logic levels.
+
+IOL_L59A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC0_OUT_7 to ADC0_OUT_7_MGIOL less
+ 0.600ns offset ADC0_OUT_7 to ADC0_LCLK (totaling 0.064ns) meets
+ 1.494ns delay ADC0_LCLK to ADC0_OUT_7_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.199ns) by 1.135ns
+
+ Physical Path Details:
+
+ Data path ADC0_OUT_7 to ADC0_OUT_7_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 T5.PAD to T5.PADDI ADC0_OUT_7
+ROUTE 1 0.000 T5.PADDI to IOL_L59A.DI THE_ADC0_HANDLER/THE_DIN_7/buf_Data0 (to ADC0_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC0_LCLK to ADC0_OUT_7_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.952 T3.PADDI to IOL_L59A.ECLKI ADC0_LCLK_c
+ --------
+ 1.494 (36.3% logic, 63.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.135ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC0_OUT_1
+ Destination: FF Data in THE_ADC0_HANDLER/THE_DIN_1/ud_0 (to ADC0_LCLK_c +)
+ FF THE_ADC0_HANDLER/THE_DIN_1/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.494ns (36.3% logic, 63.7% route), 1 logic levels.
+
+IOL_L99A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC0_OUT_1 to ADC0_OUT_1_MGIOL less
+ 0.600ns offset ADC0_OUT_1 to ADC0_LCLK (totaling 0.064ns) meets
+ 1.494ns delay ADC0_LCLK to ADC0_OUT_1_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.199ns) by 1.135ns
+
+ Physical Path Details:
+
+ Data path ADC0_OUT_1 to ADC0_OUT_1_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 AC1.PAD to AC1.PADDI ADC0_OUT_1
+ROUTE 1 0.000 AC1.PADDI to IOL_L99A.DI THE_ADC0_HANDLER/THE_DIN_1/buf_Data0 (to ADC0_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC0_LCLK to ADC0_OUT_1_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.952 T3.PADDI to IOL_L99A.ECLKI ADC0_LCLK_c
+ --------
+ 1.494 (36.3% logic, 63.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.135ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC0_OUT_4
+ Destination: FF Data in THE_ADC0_HANDLER/THE_DIN_4/ud_0 (to ADC0_LCLK_c +)
+ FF THE_ADC0_HANDLER/THE_DIN_4/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.494ns (36.3% logic, 63.7% route), 1 logic levels.
+
+IOL_L79A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC0_OUT_4 to ADC0_OUT_4_MGIOL less
+ 0.600ns offset ADC0_OUT_4 to ADC0_LCLK (totaling 0.064ns) meets
+ 1.494ns delay ADC0_LCLK to ADC0_OUT_4_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.199ns) by 1.135ns
+
+ Physical Path Details:
+
+ Data path ADC0_OUT_4 to ADC0_OUT_4_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 Y1.PAD to Y1.PADDI ADC0_OUT_4
+ROUTE 1 0.000 Y1.PADDI to IOL_L79A.DI THE_ADC0_HANDLER/THE_DIN_4/buf_Data0 (to ADC0_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC0_LCLK to ADC0_OUT_4_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 T3.PAD to T3.PADDI ADC0_LCLK
+ROUTE 289 0.952 T3.PADDI to IOL_L79A.ECLKI ADC0_LCLK_c
+ --------
+ 1.494 (36.3% logic, 63.7% route), 1 logic levels.
+
+Report: There is no minimum offset greater than zero for this preference.
+
+
+================================================================================
+Preference: PERIOD PORT "ADC1_LCLK" 4.166600 nS ;
+ 1273 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.975ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_HANDLER/THE_ADC_ADCLK_IN/ud_0 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_HANDLER/THE_ADC_0_1_CH/qc_1_0 (to ADC1_LCLK_c +)
+
+ Delay: 2.956ns (10.7% logic, 89.3% route), 1 logic levels.
+
+ Constraint Details:
+
+ 2.956ns physical path delay ADC1_ADCLK_MGIOL to THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4736 meets
+ 4.166ns delay constraint less
+ 0.106ns skew and
+ 0.129ns M_SET requirement (totaling 3.931ns) by 0.975ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2OUT_DEL --- 0.317 IOL_L9A.CLK to IOL_L9A.QPOS0 ADC1_ADCLK_MGIOL (from ADC1_LCLK_c)
+ROUTE 1 2.639 IOL_L9A.QPOS0 to R55C3B.M0 THE_ADC1_HANDLER/adc_adclk_1 (to ADC1_LCLK_c)
+ --------
+ 2.956 (10.7% logic, 89.3% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.244ns L3.PADDI to IOL_L9A.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.138ns L3.PADDI to R55C3B.CLK
+
+
+Passed: The following path meets requirements by 0.997ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_HANDLER/THE_ADC_ADCLK_IN/ud_0 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_HANDLER/THE_ADC_0_1_CH/qc_0_0 (to ADC1_LCLK_c +)
+
+ Delay: 2.934ns (9.3% logic, 90.7% route), 1 logic levels.
+
+ Constraint Details:
+
+ 2.934ns physical path delay ADC1_ADCLK_MGIOL to THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4732 meets
+ 4.166ns delay constraint less
+ 0.106ns skew and
+ 0.129ns M_SET requirement (totaling 3.931ns) by 0.997ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+C2OUT_DEL --- 0.274 IOL_L9A.CLK to IOL_L9A.QPOS1 ADC1_ADCLK_MGIOL (from ADC1_LCLK_c)
+ROUTE 1 2.660 IOL_L9A.QPOS1 to R55C2B.M0 THE_ADC1_HANDLER/adc_adclk_0 (to ADC1_LCLK_c)
+ --------
+ 2.934 (9.3% logic, 90.7% route), 1 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.244ns L3.PADDI to IOL_L9A.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.138ns L3.PADDI to R55C2B.CLK
+
+
+Passed: The following path meets requirements by 1.450ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_13 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC1_LCLK_c +)
+
+ Delay: 2.645ns (56.1% logic, 43.9% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.645ns physical path delay THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702 to THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.450ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C15C.CLK to R56C15C.Q0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702 (from ADC1_LCLK_c)
+ROUTE 5 0.585 R56C15C.Q0 to R56C15D.C1 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_w23
+CTOOFX_DEL --- 0.331 R56C15D.C1 to R56C15D.OFX0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_12188
+ROUTE 1 0.576 R56C15D.OFX0 to R56C16B.D0 THE_ADC1_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R56C16B.D0 to R56C16B.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_700
+ROUTE 1 0.000 R56C16B.FCO to R56C16C.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R56C16C.FCI to R56C16C.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_699
+ROUTE 1 0.000 R56C16C.FCO to R56C17A.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R56C17A.FCI to R56C17A.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_698
+ROUTE 1 0.000 R56C17A.FCO to R56C17B.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R56C17B.FCI to R56C17B.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697
+ROUTE 1 0.000 R56C17B.F0 to R56C17B.DI0 THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d (to ADC1_LCLK_c)
+ --------
+ 2.645 (56.1% logic, 43.9% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.138ns L3.PADDI to R56C15C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.138ns L3.PADDI to R56C17B.CLK
+
+
+Passed: The following path meets requirements by 1.450ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_13 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC1_LCLK_c +)
+
+ Delay: 2.645ns (56.1% logic, 43.9% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.645ns physical path delay THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702 to THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.450ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C15C.CLK to R56C15C.Q0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702 (from ADC1_LCLK_c)
+ROUTE 5 0.585 R56C15C.Q0 to R56C15D.C0 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_w23
+CTOOFX_DEL --- 0.331 R56C15D.C0 to R56C15D.OFX0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_12188
+ROUTE 1 0.576 R56C15D.OFX0 to R56C16B.D0 THE_ADC1_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R56C16B.D0 to R56C16B.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_700
+ROUTE 1 0.000 R56C16B.FCO to R56C16C.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R56C16C.FCI to R56C16C.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_699
+ROUTE 1 0.000 R56C16C.FCO to R56C17A.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R56C17A.FCI to R56C17A.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_698
+ROUTE 1 0.000 R56C17A.FCO to R56C17B.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R56C17B.FCI to R56C17B.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697
+ROUTE 1 0.000 R56C17B.F0 to R56C17B.DI0 THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d (to ADC1_LCLK_c)
+ --------
+ 2.645 (56.1% logic, 43.9% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.138ns L3.PADDI to R56C15C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.138ns L3.PADDI to R56C17B.CLK
+
+
+Passed: The following path meets requirements by 1.450ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_12 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC1_LCLK_c +)
+
+ Delay: 2.645ns (56.1% logic, 43.9% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.645ns physical path delay THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702 to THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.450ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C15C.CLK to R56C15C.Q1 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702 (from ADC1_LCLK_c)
+ROUTE 7 0.585 R56C15C.Q1 to R56C15D.D1 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_w24
+CTOOFX_DEL --- 0.331 R56C15D.D1 to R56C15D.OFX0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_12188
+ROUTE 1 0.576 R56C15D.OFX0 to R56C16B.D0 THE_ADC1_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R56C16B.D0 to R56C16B.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_700
+ROUTE 1 0.000 R56C16B.FCO to R56C16C.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R56C16C.FCI to R56C16C.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_699
+ROUTE 1 0.000 R56C16C.FCO to R56C17A.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R56C17A.FCI to R56C17A.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_698
+ROUTE 1 0.000 R56C17A.FCO to R56C17B.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R56C17B.FCI to R56C17B.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697
+ROUTE 1 0.000 R56C17B.F0 to R56C17B.DI0 THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d (to ADC1_LCLK_c)
+ --------
+ 2.645 (56.1% logic, 43.9% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.138ns L3.PADDI to R56C15C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.138ns L3.PADDI to R56C17B.CLK
+
+
+Passed: The following path meets requirements by 1.450ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_12 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC1_LCLK_c +)
+
+ Delay: 2.645ns (56.1% logic, 43.9% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.645ns physical path delay THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702 to THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.450ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C15C.CLK to R56C15C.Q1 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702 (from ADC1_LCLK_c)
+ROUTE 7 0.585 R56C15C.Q1 to R56C15D.D0 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_w24
+CTOOFX_DEL --- 0.331 R56C15D.D0 to R56C15D.OFX0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_12188
+ROUTE 1 0.576 R56C15D.OFX0 to R56C16B.D0 THE_ADC1_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R56C16B.D0 to R56C16B.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_700
+ROUTE 1 0.000 R56C16B.FCO to R56C16C.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R56C16C.FCI to R56C16C.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_699
+ROUTE 1 0.000 R56C16C.FCO to R56C17A.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R56C17A.FCI to R56C17A.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_698
+ROUTE 1 0.000 R56C17A.FCO to R56C17B.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R56C17B.FCI to R56C17B.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697
+ROUTE 1 0.000 R56C17B.F0 to R56C17B.DI0 THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d (to ADC1_LCLK_c)
+ --------
+ 2.645 (56.1% logic, 43.9% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.138ns L3.PADDI to R56C15C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.138ns L3.PADDI to R56C17B.CLK
+
+
+Passed: The following path meets requirements by 1.456ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_14 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC1_LCLK_c +)
+
+ Delay: 2.639ns (56.2% logic, 43.8% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.639ns physical path delay THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4701 to THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.456ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C15A.CLK to R56C15A.Q1 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4701 (from ADC1_LCLK_c)
+ROUTE 4 0.579 R56C15A.Q1 to R56C15D.B1 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_w22
+CTOOFX_DEL --- 0.331 R56C15D.B1 to R56C15D.OFX0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_12188
+ROUTE 1 0.576 R56C15D.OFX0 to R56C16B.D0 THE_ADC1_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R56C16B.D0 to R56C16B.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_700
+ROUTE 1 0.000 R56C16B.FCO to R56C16C.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R56C16C.FCI to R56C16C.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_699
+ROUTE 1 0.000 R56C16C.FCO to R56C17A.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R56C17A.FCI to R56C17A.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_698
+ROUTE 1 0.000 R56C17A.FCO to R56C17B.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R56C17B.FCI to R56C17B.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697
+ROUTE 1 0.000 R56C17B.F0 to R56C17B.DI0 THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d (to ADC1_LCLK_c)
+ --------
+ 2.639 (56.2% logic, 43.8% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.138ns L3.PADDI to R56C15A.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.138ns L3.PADDI to R56C17B.CLK
+
+
+Passed: The following path meets requirements by 1.456ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_14 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC1_LCLK_c +)
+
+ Delay: 2.639ns (56.2% logic, 43.8% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.639ns physical path delay THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4701 to THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.456ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C15A.CLK to R56C15A.Q1 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4701 (from ADC1_LCLK_c)
+ROUTE 4 0.579 R56C15A.Q1 to R56C15D.B0 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_w22
+CTOOFX_DEL --- 0.331 R56C15D.B0 to R56C15D.OFX0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_12188
+ROUTE 1 0.576 R56C15D.OFX0 to R56C16B.D0 THE_ADC1_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R56C16B.D0 to R56C16B.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_700
+ROUTE 1 0.000 R56C16B.FCO to R56C16C.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R56C16C.FCI to R56C16C.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_699
+ROUTE 1 0.000 R56C16C.FCO to R56C17A.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R56C17A.FCI to R56C17A.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_698
+ROUTE 1 0.000 R56C17A.FCO to R56C17B.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R56C17B.FCI to R56C17B.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697
+ROUTE 1 0.000 R56C17B.F0 to R56C17B.DI0 THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d (to ADC1_LCLK_c)
+ --------
+ 2.639 (56.2% logic, 43.8% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.138ns L3.PADDI to R56C15A.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.138ns L3.PADDI to R56C17B.CLK
+
+
+Passed: The following path meets requirements by 1.487ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_15 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC1_LCLK_c +)
+
+ Delay: 2.608ns (56.9% logic, 43.1% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.608ns physical path delay THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4701 to THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.487ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C15A.CLK to R56C15A.Q0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4701 (from ADC1_LCLK_c)
+ROUTE 3 0.548 R56C15A.Q0 to R56C15D.A1 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_w21
+CTOOFX_DEL --- 0.331 R56C15D.A1 to R56C15D.OFX0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_12188
+ROUTE 1 0.576 R56C15D.OFX0 to R56C16B.D0 THE_ADC1_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R56C16B.D0 to R56C16B.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_700
+ROUTE 1 0.000 R56C16B.FCO to R56C16C.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R56C16C.FCI to R56C16C.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_699
+ROUTE 1 0.000 R56C16C.FCO to R56C17A.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R56C17A.FCI to R56C17A.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_698
+ROUTE 1 0.000 R56C17A.FCO to R56C17B.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R56C17B.FCI to R56C17B.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697
+ROUTE 1 0.000 R56C17B.F0 to R56C17B.DI0 THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d (to ADC1_LCLK_c)
+ --------
+ 2.608 (56.9% logic, 43.1% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.138ns L3.PADDI to R56C15A.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.138ns L3.PADDI to R56C17B.CLK
+
+
+Passed: The following path meets requirements by 1.487ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_15 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC1_LCLK_c +)
+
+ Delay: 2.608ns (56.9% logic, 43.1% route), 6 logic levels.
+
+ Constraint Details:
+
+ 2.608ns physical path delay THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4701 to THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.487ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C15A.CLK to R56C15A.Q0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4701 (from ADC1_LCLK_c)
+ROUTE 3 0.548 R56C15A.Q0 to R56C15D.A0 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_w21
+CTOOFX_DEL --- 0.331 R56C15D.A0 to R56C15D.OFX0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_12188
+ROUTE 1 0.576 R56C15D.OFX0 to R56C16B.D0 THE_ADC1_CROSSOVER/THE_CROSSOVER/rcount_w0
+C0TOFCO_DE --- 0.440 R56C16B.D0 to R56C16B.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_700
+ROUTE 1 0.000 R56C16B.FCO to R56C16C.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R56C16C.FCI to R56C16C.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_699
+ROUTE 1 0.000 R56C16C.FCO to R56C17A.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R56C17A.FCI to R56C17A.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_698
+ROUTE 1 0.000 R56C17A.FCO to R56C17B.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R56C17B.FCI to R56C17B.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697
+ROUTE 1 0.000 R56C17B.F0 to R56C17B.DI0 THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d (to ADC1_LCLK_c)
+ --------
+ 2.608 (56.9% logic, 43.1% route), 6 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.138ns L3.PADDI to R56C15A.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.138ns L3.PADDI to R56C17B.CLK
+
+
+Passed: The following path meets requirements by 1.518ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_12 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC1_LCLK_c +)
+
+ Delay: 2.577ns (46.1% logic, 53.9% route), 4 logic levels.
+
+ Constraint Details:
+
+ 2.577ns physical path delay THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702 to THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.518ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C15C.CLK to R56C15C.Q1 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702 (from ADC1_LCLK_c)
+ROUTE 7 0.620 R56C15C.Q1 to R56C15B.B0 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_w24
+CTOF_DEL --- 0.198 R56C15B.B0 to R56C15B.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4716
+ROUTE 1 0.768 R56C15B.F0 to R56C17A.A0 THE_ADC1_CROSSOVER/THE_CROSSOVER/full_cmp_set
+C0TOFCO_DE --- 0.440 R56C17A.A0 to R56C17A.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_698
+ROUTE 1 0.000 R56C17A.FCO to R56C17B.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R56C17B.FCI to R56C17B.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697
+ROUTE 1 0.000 R56C17B.F0 to R56C17B.DI0 THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d (to ADC1_LCLK_c)
+ --------
+ 2.577 (46.1% logic, 53.9% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.138ns L3.PADDI to R56C15C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.138ns L3.PADDI to R56C17B.CLK
+
+
+Passed: The following path meets requirements by 1.525ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_13 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC1_LCLK_c +)
+
+ Delay: 2.570ns (46.7% logic, 53.3% route), 5 logic levels.
+
+ Constraint Details:
+
+ 2.570ns physical path delay THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702 to THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.525ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C15C.CLK to R56C15C.Q0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702 (from ADC1_LCLK_c)
+ROUTE 5 0.577 R56C15C.Q0 to R56C15C.C1 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_w23
+CTOF_DEL --- 0.198 R56C15C.C1 to R56C15C.F1 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702
+ROUTE 1 0.794 R56C15C.F1 to R56C16C.D1 THE_ADC1_CROSSOVER/THE_CROSSOVER/rcount_w3
+C1TOFCO_DE --- 0.369 R56C16C.D1 to R56C16C.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_699
+ROUTE 1 0.000 R56C16C.FCO to R56C17A.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R56C17A.FCI to R56C17A.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_698
+ROUTE 1 0.000 R56C17A.FCO to R56C17B.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R56C17B.FCI to R56C17B.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697
+ROUTE 1 0.000 R56C17B.F0 to R56C17B.DI0 THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d (to ADC1_LCLK_c)
+ --------
+ 2.570 (46.7% logic, 53.3% route), 5 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.138ns L3.PADDI to R56C15C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.138ns L3.PADDI to R56C17B.CLK
+
+
+Passed: The following path meets requirements by 1.612ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_143 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC1_LCLK_c +)
+
+ Delay: 2.483ns (47.9% logic, 52.1% route), 4 logic levels.
+
+ Constraint Details:
+
+ 2.483ns physical path delay THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4716 to THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.612ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C15B.CLK to R56C15B.Q0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4716 (from ADC1_LCLK_c)
+ROUTE 2 0.526 R56C15B.Q0 to R56C15B.C0 THE_ADC1_CROSSOVER/THE_CROSSOVER/wptr_4
+CTOF_DEL --- 0.198 R56C15B.C0 to R56C15B.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4716
+ROUTE 1 0.768 R56C15B.F0 to R56C17A.A0 THE_ADC1_CROSSOVER/THE_CROSSOVER/full_cmp_set
+C0TOFCO_DE --- 0.440 R56C17A.A0 to R56C17A.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_698
+ROUTE 1 0.000 R56C17A.FCO to R56C17B.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R56C17B.FCI to R56C17B.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697
+ROUTE 1 0.000 R56C17B.F0 to R56C17B.DI0 THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d (to ADC1_LCLK_c)
+ --------
+ 2.483 (47.9% logic, 52.1% route), 4 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.138ns L3.PADDI to R56C15B.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.138ns L3.PADDI to R56C17B.CLK
+
+
+Passed: The following path meets requirements by 1.642ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_13 (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC1_LCLK_c +)
+
+ Delay: 2.453ns (51.8% logic, 48.2% route), 5 logic levels.
+
+ Constraint Details:
+
+ 2.453ns physical path delay THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702 to THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.642ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C15C.CLK to R56C15C.Q0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702 (from ADC1_LCLK_c)
+ROUTE 5 0.678 R56C15C.Q0 to R56C15C.B0 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_w23
+CTOF_DEL --- 0.198 R56C15C.B0 to R56C15C.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_4702
+ROUTE 1 0.505 R56C15C.F0 to R56C16C.D0 THE_ADC1_CROSSOVER/THE_CROSSOVER/rcount_w2
+C0TOFCO_DE --- 0.440 R56C16C.D0 to R56C16C.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_699
+ROUTE 1 0.000 R56C16C.FCO to R56C17A.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R56C17A.FCI to R56C17A.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_698
+ROUTE 1 0.000 R56C17A.FCO to R56C17B.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R56C17B.FCI to R56C17B.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697
+ROUTE 1 0.000 R56C17B.F0 to R56C17B.DI0 THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d (to ADC1_LCLK_c)
+ --------
+ 2.453 (51.8% logic, 48.2% route), 5 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.138ns L3.PADDI to R56C15C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.138ns L3.PADDI to R56C17B.CLK
+
+
+Passed: The following path meets requirements by 1.651ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: FF Q THE_ADC1_CROSSOVER/fifo_wr_ena (from ADC1_LCLK_c +)
+ Destination: FF Data in THE_ADC1_CROSSOVER/THE_CROSSOVER/FF_0 (to ADC1_LCLK_c +)
+
+ Delay: 2.444ns (55.7% logic, 44.3% route), 7 logic levels.
+
+ Constraint Details:
+
+ 2.444ns physical path delay THE_ADC1_CROSSOVER/SLICE_4718 to THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697 meets
+ 4.166ns delay constraint less
+ 0.000ns skew and
+ 0.071ns DIN_SET requirement (totaling 4.095ns) by 1.651ns
+
+ Physical Path Details:
+
+ Name Fanout Delay (ns) Site Resource
+REG_DEL --- 0.309 R56C17C.CLK to R56C17C.Q0 THE_ADC1_CROSSOVER/SLICE_4718 (from ADC1_LCLK_c)
+ROUTE 1 0.477 R56C17C.Q0 to R56C17C.C0 THE_ADC1_CROSSOVER/fifo_wr_ena
+CTOF_DEL --- 0.198 R56C17C.C0 to R56C17C.F0 THE_ADC1_CROSSOVER/SLICE_4718
+ROUTE 35 0.606 R56C17C.F0 to R56C16A.A1 THE_ADC1_CROSSOVER/THE_CROSSOVER/wren_i
+C1TOFCO_DE --- 0.369 R56C16A.A1 to R56C16A.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_696
+ROUTE 1 0.000 R56C16A.FCO to R56C16B.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/cmp_ci_1
+FCITOFCO_D --- 0.081 R56C16B.FCI to R56C16B.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_700
+ROUTE 1 0.000 R56C16B.FCO to R56C16C.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co0_5
+FCITOFCO_D --- 0.081 R56C16C.FCI to R56C16C.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_699
+ROUTE 1 0.000 R56C16C.FCO to R56C17A.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/co1_5
+FCITOFCO_D --- 0.081 R56C17A.FCI to R56C17A.FCO THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_698
+ROUTE 1 0.000 R56C17A.FCO to R56C17B.FCI THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d_c
+FCITOF0_DE --- 0.242 R56C17B.FCI to R56C17B.F0 THE_ADC1_CROSSOVER/THE_CROSSOVER/SLICE_697
+ROUTE 1 0.000 R56C17B.F0 to R56C17B.DI0 THE_ADC1_CROSSOVER/THE_CROSSOVER/full_d (to ADC1_LCLK_c)
+ --------
+ 2.444 (55.7% logic, 44.3% route), 7 logic levels.
+
+ Clock Skew Details:
+
+ Source Clock:
+ Delay Connection
+ 2.138ns L3.PADDI to R56C17C.CLK
+
+ Destination Clock :
+ Delay Connection
+ 2.138ns L3.PADDI to R56C17B.CLK
+
+Report: 3.191ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: INPUT_SETUP GROUP "ADC1_INPUT" 0.600000 ns HOLD 0.600000 ns CLKPORT "ADC1_LCLK" ; Setup Analysis.
+ 9 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 1.094ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC1_OUT_2
+ Destination: FF Data in THE_ADC1_HANDLER/THE_DIN_2/ud_0 (to ADC1_LCLK_c +)
+ FF THE_ADC1_HANDLER/THE_DIN_2/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.453ns (37.3% logic, 62.7% route), 1 logic levels.
+
+IOL_L46A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC1_OUT_2 to ADC1_OUT_2_MGIOL less
+ 0.600ns offset ADC1_OUT_2 to ADC1_LCLK (totaling 0.064ns) meets
+ 1.453ns delay ADC1_LCLK to ADC1_OUT_2_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.158ns) by 1.094ns
+
+ Physical Path Details:
+
+ Data path ADC1_OUT_2 to ADC1_OUT_2_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 N5.PAD to N5.PADDI ADC1_OUT_2
+ROUTE 1 0.000 N5.PADDI to IOL_L46A.DI THE_ADC1_HANDLER/THE_DIN_2/buf_Data0 (to ADC1_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC1_LCLK to ADC1_OUT_2_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 L3.PAD to L3.PADDI ADC1_LCLK
+ROUTE 289 0.911 L3.PADDI to IOL_L46A.ECLKI ADC1_LCLK_c
+ --------
+ 1.453 (37.3% logic, 62.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.094ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC1_OUT_3
+ Destination: FF Data in THE_ADC1_HANDLER/THE_DIN_3/ud_0 (to ADC1_LCLK_c +)
+ FF THE_ADC1_HANDLER/THE_DIN_3/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.453ns (37.3% logic, 62.7% route), 1 logic levels.
+
+IOL_L43A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC1_OUT_3 to ADC1_OUT_3_MGIOL less
+ 0.600ns offset ADC1_OUT_3 to ADC1_LCLK (totaling 0.064ns) meets
+ 1.453ns delay ADC1_LCLK to ADC1_OUT_3_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.158ns) by 1.094ns
+
+ Physical Path Details:
+
+ Data path ADC1_OUT_3 to ADC1_OUT_3_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 K2.PAD to K2.PADDI ADC1_OUT_3
+ROUTE 1 0.000 K2.PADDI to IOL_L43A.DI THE_ADC1_HANDLER/THE_DIN_3/buf_Data0 (to ADC1_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC1_LCLK to ADC1_OUT_3_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 L3.PAD to L3.PADDI ADC1_LCLK
+ROUTE 289 0.911 L3.PADDI to IOL_L43A.ECLKI ADC1_LCLK_c
+ --------
+ 1.453 (37.3% logic, 62.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.094ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC1_OUT_6
+ Destination: FF Data in THE_ADC1_HANDLER/THE_DIN_6/ud_0 (to ADC1_LCLK_c +)
+ FF THE_ADC1_HANDLER/THE_DIN_6/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.453ns (37.3% logic, 62.7% route), 1 logic levels.
+
+IOL_L28A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC1_OUT_6 to ADC1_OUT_6_MGIOL less
+ 0.600ns offset ADC1_OUT_6 to ADC1_LCLK (totaling 0.064ns) meets
+ 1.453ns delay ADC1_LCLK to ADC1_OUT_6_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.158ns) by 1.094ns
+
+ Physical Path Details:
+
+ Data path ADC1_OUT_6 to ADC1_OUT_6_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 G2.PAD to G2.PADDI ADC1_OUT_6
+ROUTE 1 0.000 G2.PADDI to IOL_L28A.DI THE_ADC1_HANDLER/THE_DIN_6/buf_Data0 (to ADC1_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC1_LCLK to ADC1_OUT_6_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 L3.PAD to L3.PADDI ADC1_LCLK
+ROUTE 289 0.911 L3.PADDI to IOL_L28A.ECLKI ADC1_LCLK_c
+ --------
+ 1.453 (37.3% logic, 62.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.094ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC1_OUT_4
+ Destination: FF Data in THE_ADC1_HANDLER/THE_DIN_4/ud_0 (to ADC1_LCLK_c +)
+ FF THE_ADC1_HANDLER/THE_DIN_4/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.453ns (37.3% logic, 62.7% route), 1 logic levels.
+
+IOL_L34A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC1_OUT_4 to ADC1_OUT_4_MGIOL less
+ 0.600ns offset ADC1_OUT_4 to ADC1_LCLK (totaling 0.064ns) meets
+ 1.453ns delay ADC1_LCLK to ADC1_OUT_4_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.158ns) by 1.094ns
+
+ Physical Path Details:
+
+ Data path ADC1_OUT_4 to ADC1_OUT_4_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 J3.PAD to J3.PADDI ADC1_OUT_4
+ROUTE 1 0.000 J3.PADDI to IOL_L34A.DI THE_ADC1_HANDLER/THE_DIN_4/buf_Data0 (to ADC1_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC1_LCLK to ADC1_OUT_4_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 L3.PAD to L3.PADDI ADC1_LCLK
+ROUTE 289 0.911 L3.PADDI to IOL_L34A.ECLKI ADC1_LCLK_c
+ --------
+ 1.453 (37.3% logic, 62.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.094ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC1_OUT_0
+ Destination: FF Data in THE_ADC1_HANDLER/THE_DIN_0/ud_0 (to ADC1_LCLK_c +)
+ FF THE_ADC1_HANDLER/THE_DIN_0/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.453ns (37.3% logic, 62.7% route), 1 logic levels.
+
+IOL_L56A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC1_OUT_0 to ADC1_OUT_0_MGIOL less
+ 0.600ns offset ADC1_OUT_0 to ADC1_LCLK (totaling 0.064ns) meets
+ 1.453ns delay ADC1_LCLK to ADC1_OUT_0_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.158ns) by 1.094ns
+
+ Physical Path Details:
+
+ Data path ADC1_OUT_0 to ADC1_OUT_0_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 P3.PAD to P3.PADDI ADC1_OUT_0
+ROUTE 1 0.000 P3.PADDI to IOL_L56A.DI THE_ADC1_HANDLER/THE_DIN_0/buf_Data0 (to ADC1_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC1_LCLK to ADC1_OUT_0_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 L3.PAD to L3.PADDI ADC1_LCLK
+ROUTE 289 0.911 L3.PADDI to IOL_L56A.ECLKI ADC1_LCLK_c
+ --------
+ 1.453 (37.3% logic, 62.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.094ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC1_OUT_7
+ Destination: FF Data in THE_ADC1_HANDLER/THE_DIN_7/ud_0 (to ADC1_LCLK_c +)
+ FF THE_ADC1_HANDLER/THE_DIN_7/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.453ns (37.3% logic, 62.7% route), 1 logic levels.
+
+IOL_L14A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC1_OUT_7 to ADC1_OUT_7_MGIOL less
+ 0.600ns offset ADC1_OUT_7 to ADC1_LCLK (totaling 0.064ns) meets
+ 1.453ns delay ADC1_LCLK to ADC1_OUT_7_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.158ns) by 1.094ns
+
+ Physical Path Details:
+
+ Data path ADC1_OUT_7 to ADC1_OUT_7_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 E2.PAD to E2.PADDI ADC1_OUT_7
+ROUTE 1 0.000 E2.PADDI to IOL_L14A.DI THE_ADC1_HANDLER/THE_DIN_7/buf_Data0 (to ADC1_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC1_LCLK to ADC1_OUT_7_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 L3.PAD to L3.PADDI ADC1_LCLK
+ROUTE 289 0.911 L3.PADDI to IOL_L14A.ECLKI ADC1_LCLK_c
+ --------
+ 1.453 (37.3% logic, 62.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.094ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC1_ADCLK
+ Destination: FF Data in THE_ADC1_HANDLER/THE_ADC_ADCLK_IN/ud_0 (to ADC1_LCLK_c +)
+ FF THE_ADC1_HANDLER/THE_ADC_ADCLK_IN/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.453ns (37.3% logic, 62.7% route), 1 logic levels.
+
+IOL_L9A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC1_ADCLK to ADC1_ADCLK_MGIOL less
+ 0.600ns offset ADC1_ADCLK to ADC1_LCLK (totaling 0.064ns) meets
+ 1.453ns delay ADC1_LCLK to ADC1_ADCLK_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.158ns) by 1.094ns
+
+ Physical Path Details:
+
+ Data path ADC1_ADCLK to ADC1_ADCLK_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 D2.PAD to D2.PADDI ADC1_ADCLK
+ROUTE 1 0.000 D2.PADDI to IOL_L9A.DI THE_ADC1_HANDLER/THE_ADC_ADCLK_IN/buf_Data0 (to ADC1_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC1_LCLK to ADC1_ADCLK_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 L3.PAD to L3.PADDI ADC1_LCLK
+ROUTE 289 0.911 L3.PADDI to IOL_L9A.ECLKI ADC1_LCLK_c
+ --------
+ 1.453 (37.3% logic, 62.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.094ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC1_OUT_1
+ Destination: FF Data in THE_ADC1_HANDLER/THE_DIN_1/ud_0 (to ADC1_LCLK_c +)
+ FF THE_ADC1_HANDLER/THE_DIN_1/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.453ns (37.3% logic, 62.7% route), 1 logic levels.
+
+IOL_L47A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC1_OUT_1 to ADC1_OUT_1_MGIOL less
+ 0.600ns offset ADC1_OUT_1 to ADC1_LCLK (totaling 0.064ns) meets
+ 1.453ns delay ADC1_LCLK to ADC1_OUT_1_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.158ns) by 1.094ns
+
+ Physical Path Details:
+
+ Data path ADC1_OUT_1 to ADC1_OUT_1_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 M4.PAD to M4.PADDI ADC1_OUT_1
+ROUTE 1 0.000 M4.PADDI to IOL_L47A.DI THE_ADC1_HANDLER/THE_DIN_1/buf_Data0 (to ADC1_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC1_LCLK to ADC1_OUT_1_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 L3.PAD to L3.PADDI ADC1_LCLK
+ROUTE 289 0.911 L3.PADDI to IOL_L47A.ECLKI ADC1_LCLK_c
+ --------
+ 1.453 (37.3% logic, 62.7% route), 1 logic levels.
+
+
+Passed: The following path meets requirements by 1.094ns
+
+ Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
+
+ Source: Port Pad ADC1_OUT_5
+ Destination: FF Data in THE_ADC1_HANDLER/THE_DIN_5/ud_0 (to ADC1_LCLK_c +)
+ FF THE_ADC1_HANDLER/THE_DIN_5/ud_0
+
+ Max Data Path Delay: 0.664ns (100.0% logic, 0.0% route), 1 logic levels.
+
+ Min Clock Path Delay: 1.453ns (37.3% logic, 62.7% route), 1 logic levels.
+
+IOL_L26A attributes: FINE=FDEL0
+
+ Constraint Details:
+
+ 0.664ns delay ADC1_OUT_5 to ADC1_OUT_5_MGIOL less
+ 0.600ns offset ADC1_OUT_5 to ADC1_LCLK (totaling 0.064ns) meets
+ 1.453ns delay ADC1_LCLK to ADC1_OUT_5_MGIOL less
+ 0.295ns DI_SET requirement (totaling 1.158ns) by 1.094ns
+
+ Physical Path Details:
+
+ Data path ADC1_OUT_5 to ADC1_OUT_5_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.664 J5.PAD to J5.PADDI ADC1_OUT_5
+ROUTE 1 0.000 J5.PADDI to IOL_L26A.DI THE_ADC1_HANDLER/THE_DIN_5/buf_Data0 (to ADC1_LCLK_c)
+ --------
+ 0.664 (100.0% logic, 0.0% route), 1 logic levels.
+
+ Clock path ADC1_LCLK to ADC1_OUT_5_MGIOL:
+
+ Name Fanout Delay (ns) Site Resource
+PADI_DEL --- 0.542 L3.PAD to L3.PADDI ADC1_LCLK
+ROUTE 289 0.911 L3.PADDI to IOL_L26A.ECLKI ADC1_LCLK_c
+ --------
+ 1.453 (37.3% logic, 62.7% route), 1 logic levels.
+
+Report: There is no minimum offset greater than zero for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference | Constraint| Actual|Levels
+----------------------------------------------------------------------------
+ | | |
+FREQUENCY NET "clk_adc" 40.000000 MHz ; | -| -| 0
+ | | |
+FREQUENCY NET "CLK100M_c" 100.000000 | | |
+MHz ; | 100.000 MHz| 193.498 MHz| 13
+ | | |
+FREQUENCY NET "clk_apv_c" 40.000000 MHz | | |
+; | 40.000 MHz| 51.653 MHz| 1
+ | | |
+FREQUENCY NET "cts_clk40m" 40.000000 | | |
+MHz ; | 40.000 MHz| 1000.000 MHz| 2
+ | | |
+FREQUENCY NET "sysclk_c" 100.000000 MHz | | |
+; | 100.000 MHz| 107.910 MHz| 6
+ | | |
+FREQUENCY NET "EXT_IN_c_3" 40.000000 | | |
+MHz ; | -| -| 0
+ | | |
+PERIOD PORT "ADC0_LCLK" 4.166600 nS ; | 4.166 ns| 2.932 ns| 6
+ | | |
+INPUT_SETUP GROUP "ADC0_INPUT" 0.600000 | | |
+ns HOLD 0.600000 ns CLKPORT "ADC0_LCLK" | | |
+; Setup Analysis. | 0.600 ns| -0.535 ns| 1
+ | | |
+PERIOD PORT "ADC1_LCLK" 4.166600 nS ; | 4.166 ns| 3.191 ns| 1
+ | | |
+INPUT_SETUP GROUP "ADC1_INPUT" 0.600000 | | |
+ns HOLD 0.600000 ns CLKPORT "ADC1_LCLK" | | |
+; Setup Analysis. | 0.600 ns| -0.494 ns| 1
+ | | |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 13 clocks:
+
+Clock Domain: GND Source: SLICE_14065.F0 Loads: 114
+ No transfer within this clock domain is found
+
+Clock Domain: clk_adc Source: THE_40M_PLL/PLLDInst_0.CLKOS Loads: 2
+ No transfer within this clock domain is found
+
+Clock Domain: CLK100M_c Source: CLK100M.PAD Loads: 21
+ Covered under: FREQUENCY NET "CLK100M_c" 100.000000 MHz ;
+
+ Data transfers from:
+ Clock Domain: sysclk_c Source: THE_100M_DLL/dll_100m_0_0.CLKOP
+ Covered under: FREQUENCY NET "CLK100M_c" 100.000000 MHz ; Transfers: 2
+
+Clock Domain: clk_apv_c Source: THE_40M_PLL/PLLDInst_0.CLKOP Loads: 2043
+ Covered under: FREQUENCY NET "clk_apv_c" 40.000000 MHz ;
+
+ Data transfers from:
+ Clock Domain: sysclk_c Source: THE_100M_DLL/dll_100m_0_0.CLKOP
+ Covered under: FREQUENCY NET "clk_apv_c" 40.000000 MHz ; Transfers: 148
+
+ Clock Domain: ADC0_LCLK_c Source: ADC0_LCLK.PAD
+ Not reported because source and destination domains are unrelated.
+
+ Clock Domain: ADC1_LCLK_c Source: ADC1_LCLK.PAD
+ Not reported because source and destination domains are unrelated.
+
+Clock Domain: cts_clk40m Source: THE_SYNC_PLL/PLLDInst_0.CLKOP Loads: 1
+ Covered under: FREQUENCY NET "cts_clk40m" 40.000000 MHz ;
+
+Clock Domain: sysclk_c Source: THE_100M_DLL/dll_100m_0_0.CLKOP Loads: 7152
+ Covered under: FREQUENCY NET "sysclk_c" 100.000000 MHz ;
+
+ Data transfers from:
+ Clock Domain: CLK100M_c Source: CLK100M.PAD
+ Covered under: FREQUENCY NET "sysclk_c" 100.000000 MHz ; Transfers: 1
+
+ Clock Domain: clk_apv_c Source: THE_40M_PLL/PLLDInst_0.CLKOP
+ Covered under: FREQUENCY NET "sysclk_c" 100.000000 MHz ; Transfers: 335
+
+ Clock Domain: cts_clk40m Source: THE_SYNC_PLL/PLLDInst_0.CLKOP
+ Not reported because source and destination domains are unrelated.
+
+ Clock Domain: ADC0_LCLK_c Source: ADC0_LCLK.PAD
+ Not reported because source and destination domains are unrelated.
+
+ Clock Domain: ADC1_LCLK_c Source: ADC1_LCLK.PAD
+ Not reported because source and destination domains are unrelated.
+
+Clock Domain: THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/ff_txfullclk Source: THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/PCSC_INST.FF_TX_F_CLK Loads: 1
+ No transfer within this clock domain is found
+
+Clock Domain: EXT_IN_c_3 Source: EXT_IN_3.PAD Loads: 2
+ No transfer within this clock domain is found
+
+Clock Domain: ADC0_LCLK_c Source: ADC0_LCLK.PAD Loads: 289
+ Covered under: PERIOD PORT "ADC0_LCLK" 4.166600 nS ;
+
+ Data transfers from:
+ Clock Domain: clk_apv_c Source: THE_40M_PLL/PLLDInst_0.CLKOP
+ Not reported because source and destination domains are unrelated.
+
+ Clock Domain: sysclk_c Source: THE_100M_DLL/dll_100m_0_0.CLKOP
+ Not reported because source and destination domains are unrelated.
+
+Clock Domain: ADC1_LCLK_c Source: ADC1_LCLK.PAD Loads: 289
+ Covered under: PERIOD PORT "ADC1_LCLK" 4.166600 nS ;
+
+ Data transfers from:
+ Clock Domain: clk_apv_c Source: THE_40M_PLL/PLLDInst_0.CLKOP
+ Not reported because source and destination domains are unrelated.
+
+ Clock Domain: sysclk_c Source: THE_100M_DLL/dll_100m_0_0.CLKOP
+ Not reported because source and destination domains are unrelated.
+
+Clock Domain: E5ADCS10_THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/ff_txfullclk Source: E5ADCS10.DCSOUT Loads: 1
+ No transfer within this clock domain is found
+
+Clock Domain: E5ADCS01_clk_adc Source: E5ADCS01.DCSOUT Loads: 1
+ No transfer within this clock domain is found
+
+Clock Domain: E5ADCS21_clk_adc Source: E5ADCS21.DCSOUT Loads: 1
+ No transfer within this clock domain is found
+
+
+--------------------------------------------------------------------------------
+ Connections not covered by the preferences
+--------------------------------------------------------------------------------
+
+ Delay Element Net
+
+ 1.273ns PLL/PLLDInst_0.CLKOS to E5ADCS01.CLK0 clk_adc
+ 1.273ns PLL/PLLDInst_0.CLKOS to E5ADCS21.CLK0 clk_adc
+ 0.000ns ADC1_CLK_MGIOL.IOLDO to ADC1_CLK.IOLDO ADC1_CLK_c
+ 4.483ns _SLIM/SLICE_10627.Q0 to APV0_SDA.PADDT apv_sda_out
+ 4.470ns _SLIM/SLICE_10627.Q0 to APV1_SDA.PADDT apv_sda_out
+ 4.618ns APV0_SDA.PADDI to C_SLIM/SLICE_9428.C0 APV0_SDA_in
+ 4.246ns APV0_SDA.PADDI to START/SLICE_13025.D0 APV0_SDA_in
+ 0.000ns PV0A_CLK_MGIOL.IOLDO to APV0A_CLK.IOLDO APV0A_CLK_c
+ 0.979ns SLICE_11207.Q0 to L_REG/SLICE_10364.M1 test_reg40m
+ 0.000ns ADC0_CS_MGIOL.IOLDO to ADC0_CS.IOLDO ADC0_CS_c
+ 0.000ns ADC0_SCK_MGIOL.IOLDO to ADC0_SCK.IOLDO ADC0_SCK_c
+ 0.000ns EXT_IN_0.PADDI to EXT_IN_0_MGIOL.DI EXT_IN_c_0
+ 0.000ns C_REBOOT_MGIOL.IOLDO to UC_REBOOT.IOLDO UC_REBOOT_c
+ 0.000ns APV0_1W_0.PADDI to APV0_1W_0_MGIOL.DI APV0_1W_in_0
+ 0.175ns MASTER/SLICE_9644.Q0 to MASTER/SLICE_9644.D0 THE_SLAVE_BUS/THE_ONEWIRE_MEMORY/THE_ONEWIRE_MASTER/strong_pullup_Q
+ 1.071ns ASTER/SLICE_11101.Q0 to MASTER/SLICE_9644.B0 output
+ 3.567ns ASTER/SLICE_11101.Q0 to APV1_1W_7.PADDO output
+ 4.006ns ASTER/SLICE_11101.Q0 to APV1_1W_6.PADDO output
+ 3.848ns ASTER/SLICE_11101.Q0 to APV1_1W_5.PADDO output
+ 4.844ns ASTER/SLICE_11101.Q0 to APV1_1W_4.PADDO output
+ 4.686ns ASTER/SLICE_11101.Q0 to APV1_1W_3.PADDO output
+ 3.741ns ASTER/SLICE_11101.Q0 to APV1_1W_2.PADDO output
+ 4.887ns ASTER/SLICE_11101.Q0 to APV1_1W_1.PADDO output
+ 3.583ns ASTER/SLICE_11101.Q0 to APV1_1W_0.PADDO output
+ 4.742ns ASTER/SLICE_11101.Q0 to APV0_1W_7.PADDO output
+ 4.952ns ASTER/SLICE_11101.Q0 to APV0_1W_6.PADDO output
+ 4.960ns ASTER/SLICE_11101.Q0 to APV0_1W_5.PADDO output
+ 4.951ns ASTER/SLICE_11101.Q0 to APV0_1W_4.PADDO output
+ 4.900ns ASTER/SLICE_11101.Q0 to APV0_1W_3.PADDO output
+ 5.837ns ASTER/SLICE_11101.Q0 to APV0_1W_2.PADDO output
+ 5.109ns ASTER/SLICE_11101.Q0 to APV0_1W_1.PADDO output
+ 4.951ns ASTER/SLICE_11101.Q0 to APV0_1W_0.PADDO output
+ 3.041ns ASTER/SLICE_11101.Q0 to BP_ONEWIRE.PADDO output
+ 3.306ns MASTER/SLICE_9644.F0 to APV1_1W_7.PADDT IO_GEN_0_un8_onewire
+ 3.263ns MASTER/SLICE_9644.F0 to APV1_1W_6.PADDT IO_GEN_0_un8_onewire
+ 3.263ns MASTER/SLICE_9644.F0 to APV1_1W_5.PADDT IO_GEN_0_un8_onewire
+ 3.934ns MASTER/SLICE_9644.F0 to APV1_1W_4.PADDT IO_GEN_0_un8_onewire
+ 3.934ns MASTER/SLICE_9644.F0 to APV1_1W_3.PADDT IO_GEN_0_un8_onewire
+ 3.271ns MASTER/SLICE_9644.F0 to APV1_1W_2.PADDT IO_GEN_0_un8_onewire
+ 4.127ns MASTER/SLICE_9644.F0 to APV1_1W_1.PADDT IO_GEN_0_un8_onewire
+ 3.271ns MASTER/SLICE_9644.F0 to APV1_1W_0.PADDT IO_GEN_0_un8_onewire
+ 4.692ns MASTER/SLICE_9644.F0 to APV0_1W_7.PADDT IO_GEN_0_un8_onewire
+ 4.450ns MASTER/SLICE_9644.F0 to APV0_1W_6.PADDT IO_GEN_0_un8_onewire
+ 4.902ns MASTER/SLICE_9644.F0 to APV0_1W_5.PADDT IO_GEN_0_un8_onewire
+ 4.893ns MASTER/SLICE_9644.F0 to APV0_1W_4.PADDT IO_GEN_0_un8_onewire
+ 4.692ns MASTER/SLICE_9644.F0 to APV0_1W_3.PADDT IO_GEN_0_un8_onewire
+ 5.338ns MASTER/SLICE_9644.F0 to APV0_1W_2.PADDT IO_GEN_0_un8_onewire
+ 4.901ns MASTER/SLICE_9644.F0 to APV0_1W_1.PADDT IO_GEN_0_un8_onewire
+ 4.901ns MASTER/SLICE_9644.F0 to APV0_1W_0.PADDT IO_GEN_0_un8_onewire
+ 3.700ns MASTER/SLICE_9644.F0 to BP_ONEWIRE.PADDT IO_GEN_0_un8_onewire
+ 2.924ns NDLER/SLICE_10479.Q0 to L_REG/SLICE_10365.M0 adc0_swap
+ 1.626ns NDLER/SLICE_10497.Q0 to L_REG/SLICE_10365.M1 adc1_swap
+ 3.038ns NDLER/SLICE_10492.Q0 to SSOVER/SLICE_4509.B0 adc0_valid
+ 3.055ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6373.C0 adc0_valid
+ 2.884ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6380.D0 adc0_valid
+ 3.515ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6381.B0 adc0_valid
+ 3.055ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6382.C1 adc0_valid
+ 3.093ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6384.D0 adc0_valid
+ 3.422ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6389.C0 adc0_valid
+ 3.093ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6392.D0 adc0_valid
+ 2.519ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6459.B0 adc0_valid
+ 2.519ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6466.B0 adc0_valid
+ 2.519ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6467.B0 adc0_valid
+ 2.519ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6468.B1 adc0_valid
+ 2.029ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6470.A0 adc0_valid
+ 2.238ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6475.A0 adc0_valid
+ 2.008ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6478.C0 adc0_valid
+ 1.837ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6545.D0 adc0_valid
+ 2.511ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6551.B1 adc0_valid
+ 1.837ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6552.D0 adc0_valid
+ 1.837ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6553.D0 adc0_valid
+ 1.837ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6554.D1 adc0_valid
+ 2.519ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6556.B0 adc0_valid
+ 2.046ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6561.D0 adc0_valid
+ 2.519ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6564.B0 adc0_valid
+ 1.076ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6631.B0 adc0_valid
+ 1.277ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6637.B1 adc0_valid
+ 1.192ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6638.C0 adc0_valid
+ 1.076ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6639.B0 adc0_valid
+ 1.162ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6640.A1 adc0_valid
+ 1.141ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6642.C0 adc0_valid
+ 0.812ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6647.D0 adc0_valid
+ 1.004ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6650.A0 adc0_valid
+ 4.145ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6717.C0 adc0_valid
+ 4.533ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6724.A0 adc0_valid
+ 4.145ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6725.C0 adc0_valid
+ 3.974ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6726.D1 adc0_valid
+ 3.897ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6728.A0 adc0_valid
+ 3.765ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6733.D0 adc0_valid
+ 3.547ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6736.D0 adc0_valid
+ 1.277ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6803.B0 adc0_valid
+ 1.277ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6809.B1 adc0_valid
+ 1.581ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6810.D0 adc0_valid
+ 1.277ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6811.B0 adc0_valid
+ 1.277ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6812.B1 adc0_valid
+ 1.414ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6814.A0 adc0_valid
+ 1.486ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6819.B0 adc0_valid
+ 1.393ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6822.C0 adc0_valid
+ 1.602ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6889.C0 adc0_valid
+ 1.974ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6895.A1 adc0_valid
+ 1.431ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6896.D0 adc0_valid
+ 1.589ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6897.D0 adc0_valid
+ 1.774ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6898.A1 adc0_valid
+ 1.811ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6900.C0 adc0_valid
+ 1.640ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6905.D0 adc0_valid
+ 1.811ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6908.C0 adc0_valid
+ 2.346ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6975.C0 adc0_valid
+ 2.798ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6981.B1 adc0_valid
+ 2.346ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6982.C0 adc0_valid
+ 2.175ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6983.D0 adc0_valid
+ 2.333ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6984.D1 adc0_valid
+ 2.367ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6986.A0 adc0_valid
+ 2.560ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6991.A0 adc0_valid
+ 2.338ns NDLER/SLICE_10492.Q0 to OCK_SM/SLICE_6994.C0 adc0_valid
+ 3.753ns NDLER/SLICE_10492.Q0 to ASTER/SLICE_10275.M0 adc0_valid
+ 3.936ns NDLER/SLICE_10492.Q0 to L_REG/SLICE_10366.M0 adc0_valid
+ 0.176ns NDLER/SLICE_10492.Q0 to NDLER/SLICE_10492.D0 adc0_valid
+ 3.723ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12238.M0 adc0_valid
+ 3.076ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12243.M0 adc0_valid
+ 2.013ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12247.M0 adc0_valid
+ 0.963ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12251.M0 adc0_valid
+ 1.607ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12256.M0 adc0_valid
+ 3.092ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12260.M0 adc0_valid
+ 2.431ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12264.M0 adc0_valid
+ 2.565ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_12268.M0 adc0_valid
+ 4.183ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13541.D0 adc0_valid
+ 3.140ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13548.B0 adc0_valid
+ 2.101ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13555.B0 adc0_valid
+ 1.443ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13563.B0 adc0_valid
+ 1.486ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13571.B0 adc0_valid
+ 3.062ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13578.C0 adc0_valid
+ 2.519ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13587.B0 adc0_valid
+ 1.803ns NDLER/SLICE_10492.Q0 to CK_SM/SLICE_13596.C0 adc0_valid
+ 2.526ns NDLER/SLICE_10510.Q0 to SSOVER/SLICE_4717.C0 adc1_valid
+ 1.764ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7061.B0 adc1_valid
+ 2.067ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7067.A1 adc1_valid
+ 2.073ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7068.C0 adc1_valid
+ 2.139ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7069.B0 adc1_valid
+ 1.940ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7070.B1 adc1_valid
+ 1.847ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7072.C0 adc1_valid
+ 1.475ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7077.D0 adc1_valid
+ 1.796ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7080.C0 adc1_valid
+ 1.910ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7147.D0 adc1_valid
+ 2.662ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7153.A1 adc1_valid
+ 2.068ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7154.D0 adc1_valid
+ 2.182ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7155.B0 adc1_valid
+ 1.973ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7156.B1 adc1_valid
+ 2.637ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7158.A0 adc1_valid
+ 2.383ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7163.B0 adc1_valid
+ 2.603ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7166.D0 adc1_valid
+ 3.368ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7233.A0 adc1_valid
+ 3.505ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7239.C1 adc1_valid
+ 3.440ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7240.B0 adc1_valid
+ 3.368ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7241.A0 adc1_valid
+ 3.440ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7242.B1 adc1_valid
+ 3.028ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7244.C0 adc1_valid
+ 3.229ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7249.C0 adc1_valid
+ 3.028ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7252.C0 adc1_valid
+ 1.701ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7319.D0 adc1_valid
+ 1.990ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7325.B1 adc1_valid
+ 1.726ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7326.D0 adc1_valid
+ 1.897ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7327.C0 adc1_valid
+ 1.990ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7328.B1 adc1_valid
+ 1.500ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7330.D0 adc1_valid
+ 1.910ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7335.C0 adc1_valid
+ 1.500ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7338.D0 adc1_valid
+ 3.011ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7405.C0 adc1_valid
+ 3.305ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7411.B1 adc1_valid
+ 3.011ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7412.C0 adc1_valid
+ 2.840ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7413.D0 adc1_valid
+ 2.840ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7414.D1 adc1_valid
+ 3.011ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7416.C0 adc1_valid
+ 3.011ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7421.C0 adc1_valid
+ 3.011ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7424.C0 adc1_valid
+ 2.216ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7491.B0 adc1_valid
+ 2.425ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7497.B1 adc1_valid
+ 2.216ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7498.B0 adc1_valid
+ 2.144ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7499.A0 adc1_valid
+ 2.216ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7500.B1 adc1_valid
+ 2.634ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7502.B0 adc1_valid
+ 2.575ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7507.B0 adc1_valid
+ 2.528ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7510.D0 adc1_valid
+ 2.583ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7577.A0 adc1_valid
+ 2.784ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7583.A1 adc1_valid
+ 2.655ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7584.B0 adc1_valid
+ 2.583ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7585.A0 adc1_valid
+ 2.784ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7586.A1 adc1_valid
+ 2.928ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7588.C0 adc1_valid
+ 2.929ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7593.C0 adc1_valid
+ 2.391ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7596.D0 adc1_valid
+ 1.475ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7663.D0 adc1_valid
+ 1.897ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7669.B1 adc1_valid
+ 1.915ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7670.B0 adc1_valid
+ 1.948ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7671.B0 adc1_valid
+ 2.013ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7672.C1 adc1_valid
+ 1.507ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7674.A0 adc1_valid
+ 1.804ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7679.C0 adc1_valid
+ 1.486ns NDLER/SLICE_10510.Q0 to OCK_SM/SLICE_7682.C0 adc1_valid
+ 2.415ns NDLER/SLICE_10510.Q0 to ASTER/SLICE_10284.M0 adc1_valid
+ 2.777ns NDLER/SLICE_10510.Q0 to L_REG/SLICE_10366.M1 adc1_valid
+ 0.176ns NDLER/SLICE_10510.Q0 to NDLER/SLICE_10510.D0 adc1_valid
+ 1.458ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12205.M0 adc1_valid
+ 3.591ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12209.M0 adc1_valid
+ 2.329ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12213.M0 adc1_valid
+ 2.102ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12217.M0 adc1_valid
+ 3.192ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12221.M0 adc1_valid
+ 2.784ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12225.M0 adc1_valid
+ 1.433ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12229.M0 adc1_valid
+ 1.684ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_12233.M0 adc1_valid
+ 2.081ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13435.C0 adc1_valid
+ 3.872ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13445.B0 adc1_valid
+ 2.835ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13453.B0 adc1_valid
+ 2.110ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13461.A0 adc1_valid
+ 3.212ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13469.C0 adc1_valid
+ 2.792ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13478.A0 adc1_valid
+ 2.149ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13486.B0 adc1_valid
+ 1.492ns NDLER/SLICE_10510.Q0 to CK_SM/SLICE_13495.D0 adc1_valid
+ 0.176ns SLICE_10526.Q0 to SLICE_10526.D0 adc_ctrl_reg_9_0
+ 0.584ns SLICE_10526.Q1 to SLICE_10526.C0 adc_ctrl_reg_9_1
+ 0.176ns SLICE_10525.Q0 to SLICE_10525.D0 adc_ctrl_reg_8_0
+ 0.670ns SLICE_10525.Q1 to SLICE_10525.B0 adc_ctrl_reg_8_1
+ 0.176ns SLICE_10524.Q0 to SLICE_10524.D0 adc_ctrl_reg_7_0
+ 0.670ns SLICE_10524.Q1 to SLICE_10524.B0 adc_ctrl_reg_7_1
+ 0.176ns SLICE_10523.Q0 to SLICE_10523.D0 adc_ctrl_reg_6_0
+ 0.605ns SLICE_10523.Q1 to SLICE_10523.A0 adc_ctrl_reg_6_1
+ 0.176ns SLICE_10522.Q0 to SLICE_10522.D0 adc_ctrl_reg_5_0
+ 0.571ns SLICE_10522.Q1 to SLICE_10522.B0 adc_ctrl_reg_5_1
+ 0.670ns SLICE_10521.Q0 to SLICE_10521.B0 adc_ctrl_reg_4_0
+ 0.406ns SLICE_10521.Q1 to SLICE_10521.D0 adc_ctrl_reg_4_1
+ 0.571ns SLICE_10520.Q0 to SLICE_10520.B0 adc_ctrl_reg_3_0
+ 0.406ns SLICE_10520.Q1 to SLICE_10520.D0 adc_ctrl_reg_3_1
+ 0.176ns SLICE_10519.Q0 to SLICE_10519.D0 adc_ctrl_reg_2_0
+ 0.571ns SLICE_10519.Q1 to SLICE_10519.B0 adc_ctrl_reg_2_1
+ 0.176ns SLICE_10518.Q0 to SLICE_10518.D0 adc_ctrl_reg_1_0
+ 0.176ns SLICE_10517.Q0 to SLICE_10517.D0 adc_ctrl_reg_15_0
+ 0.670ns SLICE_10517.Q1 to SLICE_10517.B0 adc_ctrl_reg_15_1
+ 0.670ns SLICE_10518.Q1 to SLICE_10518.B0 adc_ctrl_reg_1_1
+ 0.598ns SLICE_10516.Q1 to SLICE_10516.A0 adc_ctrl_reg_14_1
+ 0.176ns SLICE_10516.Q0 to SLICE_10516.D0 adc_ctrl_reg_14_0
+ 0.670ns SLICE_10515.Q1 to SLICE_10515.B0 adc_ctrl_reg_13_1
+ 0.176ns SLICE_10515.Q0 to SLICE_10515.D0 adc_ctrl_reg_13_0
+ 0.176ns SLICE_10514.Q0 to SLICE_10514.D0 adc_ctrl_reg_12_0
+ 0.670ns SLICE_10514.Q1 to SLICE_10514.B0 adc_ctrl_reg_12_1
+ 0.176ns SLICE_10513.Q0 to SLICE_10513.D0 adc_ctrl_reg_11_0
+ 0.670ns SLICE_10513.Q1 to SLICE_10513.B0 adc_ctrl_reg_11_1
+ 0.577ns SLICE_10512.Q0 to SLICE_10512.C0 adc_ctrl_reg_10_0
+ 0.406ns SLICE_10512.Q1 to SLICE_10512.D0 adc_ctrl_reg_10_1
+ 0.176ns SLICE_10511.Q0 to SLICE_10511.D0 adc_ctrl_reg_0_0
+ 0.605ns SLICE_10511.Q1 to SLICE_10511.A0 adc_ctrl_reg_0_1
+ 0.176ns ASTER/SLICE_10053.Q0 to ASTER/SLICE_10053.D0 THE_SLAVE_BUS/THE_SPI_ADC1_MASTER/adc_ctrl_data_0
+ 2.283ns MASTER/SLICE_4355.Q0 to ADC1_PD.PADDO ADC1_PD_c
+ 1.726ns ASTER/SLICE_10624.Q0 to SLICE_11033.B1 apv1_reset
+ 3.231ns ASTER/SLICE_10053.F0 to ADC1_RST.PADDO THE_SLAVE_BUS_THE_SPI_ADC1_MASTER_adc_ctrl_data_i_0
+ 0.176ns ASTER/SLICE_10021.Q0 to ASTER/SLICE_10021.D0 THE_SLAVE_BUS/THE_SPI_ADC0_MASTER/adc_ctrl_data_0
+ 3.364ns MASTER/SLICE_4354.Q0 to ADC0_PD.PADDO ADC0_PD_c
+ 2.424ns ASTER/SLICE_10623.Q0 to SLICE_11033.C1 apv0_reset
+ 4.473ns ASTER/SLICE_10021.F0 to ADC0_RST.PADDO THE_SLAVE_BUS_THE_SPI_ADC0_MASTER_adc_ctrl_data_i_0
+ 5.032ns APV0_SCL.PADDI to GSTART/SLICE_9406.D0 APV0_SCL_in
+ 5.412ns APV0_SCL.PADDI to GSTART/SLICE_9454.C1 APV0_SCL_in
+ 5.412ns APV0_SCL.PADDI to START/SLICE_13024.C0 APV0_SCL_in
+ 3.315ns APV1_SCL.PADDI to GSTART/SLICE_9406.C0 APV1_SCL_in
+ 3.353ns APV1_SCL.PADDI to GSTART/SLICE_9454.D1 APV1_SCL_in
+ 3.353ns APV1_SCL.PADDI to START/SLICE_13024.D0 APV1_SCL_in
+ 1.346ns START/SLICE_13024.F0 to GSTART/SLICE_9409.A0 THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/THE_I2C_GSTART/apv_scl_in
+ 0.347ns START/SLICE_13024.F0 to GSTART/SLICE_9455.C0 THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/THE_I2C_GSTART/apv_scl_in
+ 4.157ns APV1_SDA.PADDI to C_SLIM/SLICE_9428.B0 APV1_SDA_in
+ 4.645ns APV1_SDA.PADDI to START/SLICE_13025.A0 APV1_SDA_in
+ 1.151ns C_SLIM/SLICE_9428.F0 to GSTART/SLICE_9406.A0 THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/apv_sda_in
+ 0.001ns C_SLIM/SLICE_9428.F0 to _SLIM/SLICE_9428.DI0 THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/apv_sda_in
+ 0.540ns C_SLIM/SLICE_9428.F0 to C_SLIM/SLICE_9449.M0 THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/apv_sda_in
+ 0.995ns C_SLIM/SLICE_9428.F0 to GSTART/SLICE_9454.A1 THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/apv_sda_in
+ 0.961ns C_SLIM/SLICE_9428.F0 to GSTART/SLICE_9455.D0 THE_SLAVE_BUS/THE_I2C_MASTER/THE_I2C_SLIM/apv_sda_in
+ 3.380ns _SLIM/SLICE_10626.Q0 to APV1_SCL.PADDT apv_scl_out
+ 5.873ns _SLIM/SLICE_10626.Q0 to APV0_SCL.PADDT apv_scl_out
+ 1.511ns rface/SLICE_11230.Q0 to ADCM_ONEWIRE.PADDT un1_THE_UNIFIED_ENDPOINT_2_2
+ 1.353ns rface/SLICE_11230.Q0 to ADCM_ONEWIRE.PADDO un1_THE_UNIFIED_ENDPOINT_2_2
+ 1.469ns ADCM_ONEWIRE.PADDI to erface/SLICE_9111.C0 ADCM_ONEWIRE_in
+ 1.383ns FP_LSM/SLICE_4486.Q0 to SD_TXDIS.PADDO SD_TXDIS_c
+ 1.033ns FP_LSM/SLICE_8165.Q0 to P_LSM/SLICE_12923.C0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_1
+ 1.033ns FP_LSM/SLICE_8165.Q0 to P_LSM/SLICE_12923.C1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_1
+ 1.033ns FP_LSM/SLICE_8165.Q0 to P_LSM/SLICE_12924.C0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_1
+ 1.033ns FP_LSM/SLICE_8165.Q0 to P_LSM/SLICE_12924.C1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_1
+ 0.576ns FP_LSM/SLICE_8166.Q0 to led_4/SLICE_11783.M0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_3
+ 1.224ns FP_LSM/SLICE_8166.Q0 to P_LSM/SLICE_12923.B0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_3
+ 1.224ns FP_LSM/SLICE_8166.Q0 to P_LSM/SLICE_12923.B1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_3
+ 0.960ns FP_LSM/SLICE_8166.Q0 to P_LSM/SLICE_12924.D0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_3
+ 0.960ns FP_LSM/SLICE_8166.Q0 to P_LSM/SLICE_12924.D1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_3
+ 0.803ns FP_LSM/SLICE_8164.Q0 to led_4/SLICE_11783.C1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_0
+ 0.803ns FP_LSM/SLICE_8164.Q0 to led_u/SLICE_11784.C1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_0
+ 0.999ns FP_LSM/SLICE_8164.Q0 to P_LSM/SLICE_12923.D0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_0
+ 0.999ns FP_LSM/SLICE_8164.Q0 to P_LSM/SLICE_12923.D1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_0
+ 1.263ns FP_LSM/SLICE_8164.Q0 to P_LSM/SLICE_12924.B0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_0
+ 1.263ns FP_LSM/SLICE_8164.Q0 to P_LSM/SLICE_12924.B1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_0
+ 0.811ns FP_LSM/SLICE_8165.Q1 to led_4/SLICE_11783.C0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_2
+ 0.811ns FP_LSM/SLICE_8165.Q1 to led_u/SLICE_11784.C0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_2
+ 0.832ns FP_LSM/SLICE_8165.Q1 to led_u/SLICE_11784.A1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_2
+ 0.832ns FP_LSM/SLICE_8165.Q1 to P_LSM/SLICE_12923.A0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_2
+ 0.832ns FP_LSM/SLICE_8165.Q1 to P_LSM/SLICE_12923.A1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_2
+ 0.832ns FP_LSM/SLICE_8165.Q1 to P_LSM/SLICE_12924.A0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_2
+ 0.832ns FP_LSM/SLICE_8165.Q1 to P_LSM/SLICE_12924.A1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_2
+ 2.080ns P_LSM/SLICE_12923.F0 to FPGA_LED_3.PADDO FPGA_LED_c_3
+ 1.191ns P_LSM/SLICE_12923.F1 to FPGA_LED_6.PADDO FPGA_LED_c_6
+ 1.349ns P_LSM/SLICE_12924.F1 to FPGA_LED_4.PADDO FPGA_LED_c_4
+ 0.761ns P_LSM/SLICE_13366.F0 to led_u/SLICE_11784.M0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/N_345_li
+ 0.707ns SFP_LSM/SLICE_572.Q1 to led_u/SLICE_11784.D0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_22
+ 0.356ns SFP_LSM/SLICE_571.Q0 to led_4/SLICE_11783.D0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_23
+ 0.356ns SFP_LSM/SLICE_571.Q0 to led_4/SLICE_11783.D1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_23
+ 0.356ns SFP_LSM/SLICE_571.Q0 to led_u/SLICE_11784.D1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_23
+ 0.620ns SFP_LSM/SLICE_571.Q1 to led_4/SLICE_11783.B0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_24
+ 0.620ns SFP_LSM/SLICE_571.Q1 to led_4/SLICE_11783.B1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_24
+ 0.620ns SFP_LSM/SLICE_571.Q1 to led_u/SLICE_11784.B1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_24
+ 0.706ns SFP_LSM/SLICE_570.Q0 to led_4/SLICE_11783.A0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_25
+ 0.706ns SFP_LSM/SLICE_570.Q0 to led_4/SLICE_11783.A1 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/timing_ctr_25
+ 1.007ns P_LSM/SLICE_13364.F0 to led_u/SLICE_11784.B0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/N_413_i
+ 1.349ns P_LSM/SLICE_12924.F0 to FPGA_LED_5.PADDO FPGA_LED_c_5
+ 0.597ns d_4/SLICE_11783.OFX0 to led_u/SLICE_11784.A0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/N_453
+ 0.597ns d_u/SLICE_11784.OFX0 to P_LSM/SLICE_13370.A0 THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/med_stat_op_9
+ 1.687ns P_LSM/SLICE_13370.F0 to FPGA_LED_LINK.PADDO THE_RICH_TRB_med_stat_op_i_9
+ 0.845ns SD_PRESENT.PADDI to S_SYNC/SLICE_8173.M0 SD_PRESENT_c
+ 0.845ns SD_LOS.PADDI to S_SYNC/SLICE_8173.M1 SD_LOS_c
+ 1.328ns ERFACE/SLICE_4356.Q0 to FPGA_LED_RXD.PADDO FPGA_LED_RXD_c
+ 1.623ns RFACE/SLICE_12688.Q0 to FPGA_LED_TXD.PADDO FPGA_LED_TXD_c
+ 5.932ns RFACE/SLICE_11206.Q0 to T_SYNC/SLICE_4615.M0 reset_by_trb
+ 4.900ns RFACE/SLICE_11206.Q0 to T_SYNC/SLICE_4823.M0 reset_by_trb
+ 4.500ns EXT_IN_3.PADDI to 3_SYNC/SLICE_5058.M0 EXT_IN_c_3
+ 0.000ns EXT_IN_3.PADDI to _PLL/PLLDInst_0.CLKI EXT_IN_c_3
+ 0.614ns E_SYNC/SLICE_4511.Q0 to SSOVER/SLICE_659.LSR THE_ADC0_CROSSOVER/reset
+ 0.614ns E_SYNC/SLICE_4511.Q0 to SSOVER/SLICE_660.LSR THE_ADC0_CROSSOVER/reset
+ 0.613ns E_SYNC/SLICE_4511.Q0 to SSOVER/SLICE_661.LSR THE_ADC0_CROSSOVER/reset
+ 0.613ns E_SYNC/SLICE_4511.Q0 to SSOVER/SLICE_672.LSR THE_ADC0_CROSSOVER/reset
+ 0.822ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4490.LSR THE_ADC0_CROSSOVER/reset
+ 0.823ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4491.LSR THE_ADC0_CROSSOVER/reset
+ 0.822ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4492.LSR THE_ADC0_CROSSOVER/reset
+ 0.823ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4493.LSR THE_ADC0_CROSSOVER/reset
+ 0.823ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4494.LSR THE_ADC0_CROSSOVER/reset
+ 1.258ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4498.LSR THE_ADC0_CROSSOVER/reset
+ 1.049ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4499.LSR THE_ADC0_CROSSOVER/reset
+ 1.258ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4500.LSR THE_ADC0_CROSSOVER/reset
+ 0.832ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4506.LSR THE_ADC0_CROSSOVER/reset
+ 1.049ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4507.LSR THE_ADC0_CROSSOVER/reset
+ 0.613ns E_SYNC/SLICE_4511.Q0 to SOVER/SLICE_4508.LSR THE_ADC0_CROSSOVER/reset
+ 0.760ns SSOVER/SLICE_4498.Q0 to SSOVER/SLICE_4501.M0 THE_ADC0_CROSSOVER/THE_CROSSOVER/w_gcount_0
+ 0.559ns SSOVER/SLICE_4498.Q1 to SSOVER/SLICE_4501.M1 THE_ADC0_CROSSOVER/THE_CROSSOVER/w_gcount_1
+ 0.559ns SSOVER/SLICE_4499.Q0 to SSOVER/SLICE_4502.M0 THE_ADC0_CROSSOVER/THE_CROSSOVER/w_gcount_2
+ 0.576ns SSOVER/SLICE_4499.Q1 to SSOVER/SLICE_4502.M1 THE_ADC0_CROSSOVER/THE_CROSSOVER/w_gcount_3
+ 0.760ns SSOVER/SLICE_4500.Q0 to SSOVER/SLICE_4503.M0 THE_ADC0_CROSSOVER/THE_CROSSOVER/w_gcount_4
+ 0.559ns SSOVER/SLICE_4487.Q0 to SSOVER/SLICE_4490.M0 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_0
+ 0.961ns SSOVER/SLICE_4487.Q1 to SSOVER/SLICE_4490.M1 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_1
+ 0.777ns SSOVER/SLICE_4488.Q0 to SSOVER/SLICE_4491.M0 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_2
+ 0.559ns SSOVER/SLICE_4488.Q1 to SSOVER/SLICE_4491.M1 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_3
+ 0.330ns SSOVER/SLICE_4489.Q0 to SSOVER/SLICE_4492.M0 THE_ADC0_CROSSOVER/THE_CROSSOVER/r_gcount_4
+ 1.350ns NDLER/SLICE_10492.F0 to FPGA_LED_ADC_0.PADDO adc0_valid_i
+ 0.755ns E_SYNC/SLICE_4719.Q0 to SSOVER/SLICE_685.LSR THE_ADC1_CROSSOVER/reset
+ 0.755ns E_SYNC/SLICE_4719.Q0 to SSOVER/SLICE_686.LSR THE_ADC1_CROSSOVER/reset
+ 1.202ns E_SYNC/SLICE_4719.Q0 to SSOVER/SLICE_687.LSR THE_ADC1_CROSSOVER/reset
+ 0.955ns E_SYNC/SLICE_4719.Q0 to SSOVER/SLICE_697.LSR THE_ADC1_CROSSOVER/reset
+ 0.948ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4698.LSR THE_ADC1_CROSSOVER/reset
+ 0.747ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4699.LSR THE_ADC1_CROSSOVER/reset
+ 0.977ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4700.LSR THE_ADC1_CROSSOVER/reset
+ 1.164ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4701.LSR THE_ADC1_CROSSOVER/reset
+ 1.164ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4702.LSR THE_ADC1_CROSSOVER/reset
+ 0.956ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4706.LSR THE_ADC1_CROSSOVER/reset
+ 1.411ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4707.LSR THE_ADC1_CROSSOVER/reset
+ 1.411ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4708.LSR THE_ADC1_CROSSOVER/reset
+ 1.202ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4714.LSR THE_ADC1_CROSSOVER/reset
+ 0.956ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4715.LSR THE_ADC1_CROSSOVER/reset
+ 1.164ns E_SYNC/SLICE_4719.Q0 to SOVER/SLICE_4716.LSR THE_ADC1_CROSSOVER/reset
+ 0.131ns SSOVER/SLICE_4706.Q0 to SSOVER/SLICE_4709.M0 THE_ADC1_CROSSOVER/THE_CROSSOVER/w_gcount_0
+ 0.978ns SSOVER/SLICE_4706.Q1 to SSOVER/SLICE_4709.M1 THE_ADC1_CROSSOVER/THE_CROSSOVER/w_gcount_1
+ 0.131ns SSOVER/SLICE_4707.Q0 to SSOVER/SLICE_4710.M0 THE_ADC1_CROSSOVER/THE_CROSSOVER/w_gcount_2
+ 0.131ns SSOVER/SLICE_4707.Q1 to SSOVER/SLICE_4710.M1 THE_ADC1_CROSSOVER/THE_CROSSOVER/w_gcount_3
+ 0.576ns SSOVER/SLICE_4708.Q0 to SSOVER/SLICE_4711.M0 THE_ADC1_CROSSOVER/THE_CROSSOVER/w_gcount_4
+ 0.760ns SSOVER/SLICE_4695.Q0 to SSOVER/SLICE_4698.M0 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_0
+ 0.782ns SSOVER/SLICE_4695.Q1 to SSOVER/SLICE_4698.M1 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_1
+ 0.559ns SSOVER/SLICE_4696.Q0 to SSOVER/SLICE_4699.M0 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_2
+ 0.760ns SSOVER/SLICE_4696.Q1 to SSOVER/SLICE_4699.M1 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_3
+ 0.606ns SSOVER/SLICE_4697.Q0 to SSOVER/SLICE_4700.M0 THE_ADC1_CROSSOVER/THE_CROSSOVER/r_gcount_4
+ 2.201ns NDLER/SLICE_10510.F0 to FPGA_LED_ADC_1.PADDO adc1_valid_i
+ 0.406ns SLICE_11033.Q0 to SLICE_11033.D1 frontend_reset
+ 0.000ns /PLLDInst_0.CLKINTFB to PLL/PLLDInst_0.CLKFB THE_SYNC_PLL/CLKFB_t
+ 0.000ns ANDLER/SLICE_8034.F0 to NDLER/SLICE_8034.DI0 THE_RESET_HANDLER/comb_async_rst
+ 3.478ns UC_RESET.PADDI to ANDLER/SLICE_8034.D0 UC_RESET_c
+ 0.000ns APV1_1W_1.PADDI to APV1_1W_1_MGIOL.DI APV1_1W_in_1
+ 0.000ns APV1_1W_0.PADDI to APV1_1W_0_MGIOL.DI APV1_1W_in_0
+ 0.000ns APV0_1W_7.PADDI to APV0_1W_7_MGIOL.DI APV0_1W_in_7
+ 0.000ns APV0_1W_6.PADDI to APV0_1W_6_MGIOL.DI APV0_1W_in_6
+ 0.000ns APV0_1W_5.PADDI to APV0_1W_5_MGIOL.DI APV0_1W_in_5
+ 0.000ns APV0_1W_4.PADDI to APV0_1W_4_MGIOL.DI APV0_1W_in_4
+ 0.000ns APV0_1W_3.PADDI to APV0_1W_3_MGIOL.DI APV0_1W_in_3
+ 0.000ns APV0_1W_2.PADDI to APV0_1W_2_MGIOL.DI APV0_1W_in_2
+ 0.000ns BP_ONEWIRE.PADDI to BP_ONEWIRE_MGIOL.DI BP_ONEWIRE_in
+ 0.000ns APV1_1W_7.PADDI to APV1_1W_7_MGIOL.DI APV1_1W_in_7
+ 0.000ns APV1_1W_6.PADDI to APV1_1W_6_MGIOL.DI APV1_1W_in_6
+ 0.000ns APV1_1W_3.PADDI to APV1_1W_3_MGIOL.DI APV1_1W_in_3
+ 0.000ns APV0_1W_1.PADDI to APV0_1W_1_MGIOL.DI APV0_1W_in_1
+ 0.000ns APV1_1W_5.PADDI to APV1_1W_5_MGIOL.DI APV1_1W_in_5
+ 0.000ns APV1_1W_4.PADDI to APV1_1W_4_MGIOL.DI APV1_1W_in_4
+ 0.000ns APV1_1W_2.PADDI to APV1_1W_2_MGIOL.DI APV1_1W_in_2
+ 0.000ns U_SPI_SDO.PADDI to U_SPI_SDO_MGIOL.DI U_SPI_SDO_c
+ 0.000ns EXT_IN_2.PADDI to EXT_IN_2_MGIOL.DI EXT_IN_c_2
+ 0.000ns EXT_IN_1.PADDI to EXT_IN_1_MGIOL.DI EXT_IN_c_1
+ 0.000ns _SPI_SDI_MGIOL.IOLDO to U_SPI_SDI.IOLDO U_SPI_SDI_c
+ 0.000ns _SPI_SCK_MGIOL.IOLDO to U_SPI_SCK.IOLDO U_SPI_SCK_c
+ 0.000ns U_SPI_CS_MGIOL.IOLDO to U_SPI_CS.IOLDO U_SPI_CS_c
+ 0.000ns ADC1_SDI_MGIOL.IOLDO to ADC1_SDI.IOLDO ADC1_SDI_c
+ 0.000ns ADC1_SCK_MGIOL.IOLDO to ADC1_SCK.IOLDO ADC1_SCK_c
+ 0.000ns ADC1_CS_MGIOL.IOLDO to ADC1_CS.IOLDO ADC1_CS_c
+ 0.000ns ADC0_SDI_MGIOL.IOLDO to ADC0_SDI.IOLDO ADC0_SDI_c
+ 0.000ns SLICE_10636.F0 to SLICE_10636.DI0 BP_SECTOR_c_i_0
+ 0.000ns SLICE_10636.F1 to SLICE_10636.DI1 BP_SECTOR_c_i_1
+ 0.000ns SLICE_10637.F0 to SLICE_10637.DI0 BP_SECTOR_c_i_2
+ 0.000ns SLICE_10632.F0 to SLICE_10632.DI0 BP_MODULE_c_i_0
+ 0.000ns SLICE_10632.F1 to SLICE_10632.DI1 BP_MODULE_c_i_1
+ 0.000ns SLICE_10633.F0 to SLICE_10633.DI0 BP_MODULE_c_i_2
+ 1.251ns BP_SECTOR_2.PADDI to SLICE_10637.D0 BP_SECTOR_c_2
+ 1.289ns BP_SECTOR_1.PADDI to SLICE_10636.A1 BP_SECTOR_c_1
+ 1.033ns BP_SECTOR_0.PADDI to SLICE_10636.C0 BP_SECTOR_c_0
+ 2.905ns BP_MODULE_2.PADDI to SLICE_10633.B0 BP_MODULE_c_2
+ 2.512ns BP_MODULE_1.PADDI to SLICE_10632.C1 BP_MODULE_c_1
+ 2.298ns BP_MODULE_0.PADDI to SLICE_10632.A0 BP_MODULE_c_0
+ 0.000ns ADC0_CLK_MGIOL.IOLDO to ADC0_CLK.IOLDO ADC0_CLK_c
+ 3.795ns SLICE_10526.F0 to ENB_LVDS_7.PADDO N_1999_i
+ 3.766ns SLICE_10516.F0 to ENB_LVDS_6.PADDO N_2000_i
+ 3.773ns SLICE_10525.F0 to ENB_LVDS_5.PADDO N_2001_i
+ 3.167ns SLICE_10517.F0 to ENB_LVDS_4.PADDO N_2002_i
+ 4.044ns SLICE_10513.F0 to ENB_LVDS_3.PADDO N_2003_i
+ 3.445ns SLICE_10514.F0 to ENB_LVDS_2.PADDO N_2004_i
+ 3.815ns SLICE_10512.F0 to ENB_LVDS_1.PADDO N_2005_i
+ 3.439ns SLICE_10515.F0 to ENB_LVDS_0.PADDO N_2006_i
+ 2.431ns SLICE_11033.F1 to APV1_RST.PADDO APV0_RST_c
+ 4.342ns SLICE_11033.F1 to APV0_RST.PADDO APV0_RST_c
+ 0.000ns PV1B_TRG_MGIOL.IOLDO to APV1B_TRG.IOLDO APV1B_TRG_c
+ 0.000ns PV1A_TRG_MGIOL.IOLDO to APV1A_TRG.IOLDO APV1A_TRG_c
+ 0.000ns PV1B_CLK_MGIOL.IOLDO to APV1B_CLK.IOLDO APV1B_CLK_c
+ 0.000ns PV1A_CLK_MGIOL.IOLDO to APV1A_CLK.IOLDO APV1A_CLK_c
+ 3.368ns SLICE_10511.F0 to ENA_LVDS_7.PADDO N_2007_i
+ 3.210ns SLICE_10524.F0 to ENA_LVDS_6.PADDO N_2008_i
+ 3.150ns SLICE_10518.F0 to ENA_LVDS_5.PADDO N_2009_i
+ 3.039ns SLICE_10523.F0 to ENA_LVDS_4.PADDO N_2010_i
+ 3.622ns SLICE_10519.F0 to ENA_LVDS_3.PADDO N_2011_i
+ 3.383ns SLICE_10522.F0 to ENA_LVDS_2.PADDO N_2012_i
+ 3.779ns SLICE_10520.F0 to ENA_LVDS_1.PADDO N_2013_i
+ 3.597ns SLICE_10521.F0 to ENA_LVDS_0.PADDO N_2014_i
+ 0.000ns PV0B_TRG_MGIOL.IOLDO to APV0B_TRG.IOLDO APV0B_TRG_c
+ 0.000ns PV0A_TRG_MGIOL.IOLDO to APV0A_TRG.IOLDO APV0A_TRG_c
+ 0.000ns PV0B_CLK_MGIOL.IOLDO to APV0B_CLK.IOLDO APV0B_CLK_c
+
+--------------------------------------------------------------------------------
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0 Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 270407 paths, 138 nets, and 98840 connections (99.6% coverage)
+
+--------------------------------------------------------------------------------
+
--- /dev/null
+
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSC quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSC quad to the final design requirements.
+
+DEVICE_NAME "LFE2M100E"
+PROTOCOL "GIGE"
+CH0_MODE "DISABLE"
+CH1_MODE "DISABLE"
+CH2_MODE "SINGLE"
+CH3_MODE "DISABLE"
+PLL_SRC "CORE_TXREFCLK"
+DATARANGE "MEDHIGH"
+CH2_CDR_SRC "CORE_RXREFCLK"
+CH2_DATA_WIDTH "16"
+CH2_REFCK_MULT "20X"
+#REFCLK_RATE 100.0
+#FPGAINTCLK_RATE 100.0
+CH2_TDRV_AMP "0"
+CH2_TX_PRE "DISABLE"
+CH2_RTERM_TX "50"
+CH2_RX_EQ "DISABLE"
+CH2_RTERM_RX "50"
+CH2_RX_DCC "DC"
+LOS_THRESHOLD "0"
+PLL_TERM "50"
+PLL_DCC "AC"
+PLL_LOL_SET "0"
+CH2_TX_SB "NORMAL"
+CH2_RX_SB "NORMAL"
+CH2_8B10B "NORMAL"
+COMMA_A "1100000101"
+COMMA_B "0011111010"
+COMMA_M "1111111111"
+CH2_COMMA_ALIGN "AUTO"
+CH2_CTC_BYP "NORMAL"
+CC_MATCH1 "0000000000"
+CC_MATCH2 "0000000000"
+CC_MATCH3 "0110111100"
+CC_MATCH4 "0001010000"
+CC_MATCH_MODE "MATCH_3_4"
+CC_MIN_IPG "3"
+CCHMARK "9"
+CCLMARK "7"
+OS_REFCK2CORE "1"
+OS_PLLQCLKPORTS "0"
+OS_INT_ALL "0"
+
+++ /dev/null
-Slave bus usage\r
-===============\r
-\r
-0x8000 - 0x8001 : test register\r
-\r
-0x8040 - 0x8040 X: I2C master for APV slow control\r
-\r
-0xa000 - 0xa07f : pedestal memory APV0\r
-0xa080 - 0xa0ff : pedestal memory APV1\r
-0xa100 - 0xa17f : pedestal memory APV2\r
-0xa180 - 0xa1ff : pedestal memory APV3\r
-0xa200 - 0xa27f : pedestal memory APV4\r
-0xa280 - 0xa2ff : pedestal memory APV5\r
-0xa300 - 0xa37f : pedestal memory APV6\r
-0xa380 - 0xa3ff : pedestal memory APV7\r
-0xa400 - 0xa47f : pedestal memory APV8\r
-0xa480 - 0xa4ff : pedestal memory APV9\r
-0xa500 - 0xa57f : pedestal memory APV10\r
-0xa580 - 0xa5ff : pedestal memory APV11\r
-0xa600 - 0xa67f : pedestal memory APV12\r
-0xa680 - 0xa6ff : pedestal memory APV13\r
-0xa700 - 0xa77f : pedestal memory APV14\r
-0xa780 - 0xa7ff : pedestal memory APV15\r
-\r
-0xa800 - 0xa87f : threshold memory APV0\r
-0xa880 - 0xa8ff : threshold memory APV1\r
-0xa900 - 0xa97f : threshold memory APV2\r
-0xa980 - 0xa9ff : threshold memory APV3\r
-0xaa00 - 0xaa7f : threshold memory APV4\r
-0xaa80 - 0xaaff : threshold memory APV5\r
-0xab00 - 0xab7f : threshold memory APV6\r
-0xab80 - 0xabff : threshold memory APV7\r
-0xac00 - 0xac7f : threshold memory APV8\r
-0xac80 - 0xacff : threshold memory APV9\r
-0xad00 - 0xad7f : threshold memory APV10\r
-0xad80 - 0xadff : threshold memory APV11\r
-0xae00 - 0xae7f : threshold memory APV12\r
-0xae80 - 0xaeff : threshold memory APV13\r
-0xaf00 - 0xaf7f : threshold memory APV14\r
-0xaf80 - 0xafff : threshold memory APV15\r
-\r
-0xb000 - 0xb00f X: APV control and status\r
-\r
-0xb010 - 0xb010 X: ADC level settings\r
-\r
-0xb020 - 0xb020 X: trigger settings\r
-\r
-0xb030 - 0xb030 X: PLL settings\r
-\r
-0xc000 - 0xc03f X: 1Wire master for APV and backplane\r
-\r
-0xd000 - 0xd001 X: SPI master for FlashROM\r
-\r
-0xd010 - 0xd010 X: ADC0 control and SPI\r
-\r
-0xd020 - 0xd020 X: ADC1 control and SPI\r
-\r
-0xd100 - 0xd03f X: SPI data memory (FlashROM)\r
-\r
-0xf000 - 0xf3ff : ADC 0 snooper\r
-\r
-0xf400 - 0xf7ff : ADC 1 snooper\r
-\r
-\r
-==========================================================================\r
-== Detailed description\r
-==========================================================================\r
-\r
-\r
-#################################################################################\r
-# #\r
-# SPI master for ADC slow control, ADC configuration bits, APV reset #\r
-# #\r
-#################################################################################\r
-\r
-0xd010 - 0xd010 : ADC0 control and SPI\r
-0xd020 - 0xd020 : ADC0 control and SPI\r
----------------------------------------\r
-\r
-D[31:24] SPI command\r
-D[23:12] ADC channel 4 current data for testing\r
-D[11:9] reserved\r
-D[8] ADC PLL status 0 -> bad, 1 -> locked\r
-D[7:4] ADC input delay (0x6 is standard)\r
-D[3] SPI start 0 -> wait, 1 -> start\r
-D[2] APV reset 0 -> normal, 1 -> reset\r
-D[1] ADC power down 0 -> normal, 1 -> powerdown\r
-D[0] ADC reset 0 -> normal, 1 -> reset\r
-\r
-This register is 32bit wide with full read/write access. \r
-It controls a simple (one byte only) SPI master for configuring the ADC via SPI.\r
-Besides it allows to reset the ADC, power it down and also reset the connected \r
-APVs (eight modules).\r
-\r
-Take care not to change bits unintentionally when working with this register.\r
-A read-modify-write sequence is mandatory.\r
-\r
-\r
-SPI access to ADC is handled as following:\r
-\r
-(1) be sure that SPI start bit D[16] is zero\r
-(2) read register and set D[31:24] to the command to be sent\r
-(3) write back new value with SPI start bit set\r
-(4) clear the SPI start bit\r
-\r
-The SPI hardware access is 25MHz based and will be over before next TRBnet access\r
-to this register is possible. This SPI master can only transfer command to the ADC, \r
-and not read back (due to ADC constraints).\r
-\r
-\r
-Reset value of register is 0x00000060. \r
-\r
-#################################################################################\r
-# #\r
-# APV control and status register #\r
-# #\r
-#################################################################################\r
-\r
-0xb000 - 0xb00f : APV control and status\r
------------------------------------------\r
-\r
-D[31] buffer good 1 -> APV switched on and sync'ed\r
-D[30] buffer broken 1 -> APV switched on and off sync\r
-D[29] buffer ignore 1 -> APV not used\r
-D[28:24] number of events in buffer\r
-D[23:20] reserved\r
-D[19:16] hardware APV number before mapping([15:8] -> ADC1, [7:0] -> ADC0)\r
-D[15:1] reserved\r
-D[0] APV on 0 -> off, 1 -> on\r
-\r
-This register is divided into read only bits (D[31:16]) and read/write bits (D[15:0]).\r
-\r
-APV on bit (D[0]) is on by default.\r
-D[31] (buffer good) will only be set if the APV is switched on and a SYNC trigger has\r
-been sent.\r
-To activate an APV it is mandatory to set APV on bit (D[0]) and send a SYNC trigger.\r
-\r
-\r
-Reset value of register is 0xZZZZ0001 (Z depends on APV connections).\r
-\r
-#################################################################################\r
-# #\r
-# configuration register for ADC levels (bit recognition) #\r
-# #\r
-#################################################################################\r
-\r
-0xb010 - 0xb010 : ADC level settings\r
--------------------------------------\r
-\r
-D[31:24] bit high D[11:4] setting, D[3:0] is fixed to 0x0\r
-D[23:16] bit low D[11:4] setting, D[3:0] is fixed to 0x0\r
-D[15:8] flat high D[11:4] setting, D[3:0] is fixed to 0x0\r
-D[7:0] flat low D[11:4] setting, D[3:0] is fixed to 0x0\r
-\r
-This register is 32bit wide with full read/write access. \r
-It is used to configure the APV digital header reconstruction. The ADCs use 12bit,\r
-with 0x000 as lowest value and 0xfff as highest value. There is no OutOfRange, UnderFlow \r
-or OverFlow bit in the ADC.\r
-"Flat low" and "Flat high" set the recognition limits for a missing ADC module: in this case\r
-the ADC will deliver a flat line around 0x800.\r
-"Bit low" is the upper limit for recognizing an ADC value as digital low bit.\r
-"Bit high" is the lower limit for recognizing an ADC value as digital high bit.\r
-\r
-This register must be initialized correctly before sending any triggers to the APVs.\r
-\r
-Recommended setting is 0xd0208878 at time of this writing, giving\r
-Flat Low = 0x780\r
-Flat High = 0x880\r
-Bit Low = 0x200\r
-Bit High = 0xd00\r
-\r
-\r
-Reset value of register is 0x00000000.\r
-\r
-#################################################################################\r
-# #\r
-# configuration register for triggers #\r
-# #\r
-#################################################################################\r
-\r
-0xb020 - 0xb020 : trigger settings\r
------------------------------------\r
-\r
-D[31:28] TRG3 number of triggers\r
-D[27:24] TRG3 delay\r
-D[23:20] TRG2 number of triggers\r
-D[19:16] TRG2 delay\r
-D[15:12] TRG1 number of triggers\r
-D[11:8] TRG1 delay\r
-D[7:4] TRG0 number of triggers\r
-D[3:0] TRG0 delay\r
-\r
-This register is 32bit wide with full read/write access. \r
-It sets up the APV readout functionality (per external trigger input)\r
-\r
-For all four trigger inputs (external and slow control) the number of APV readout \r
-triggers to be sent as well as the number of clock cycles between APV readout \r
-triggers can be set up.\r
-\r
-It is not recommended to take more than 8 APV readout triggers per external trigger.\r
-\r
-Take care: the data format may change with setting up more than one APV readout trigger.\r
-\r
-\r
-Reset value of register is 0x10101010.\r
-\r
-\r
-#################################################################################\r
-# #\r
-# configuration register for PLLs #\r
-# #\r
-#################################################################################\r
-\r
-0xb030 - 0xb030 : PLL settings\r
--------------------------------\r
-\r
-D[31] 100MHZ DLL locked 0 -> bad, 1 -> locked\r
-D[30] 40MHZ PLL locked 0 -> bad, 1 -> locked\r
-D[29] ADC1 PLL locked 0 -> bad, 1 -> locked\r
-D[28] ADC0 PLL locked 0 -> bad, 1 -> locked\r
-D[27:24] reserved\r
-D[23] reserved\r
-D[22:20] sector ID as given by backplane switch\r
-D[19] reserved\r
-D[18:16] module ID as given by backplane switch\r
-D[15:8] external trigger setup\r
--> D[15] EXT_IN[3] active\r
--> D[14] EXT_IN[2] active\r
--> D[13] EXT_IN[1] active\r
--> D[12] EXT_IN[0] active\r
--> D[11] invert external trigger 3\r
--> D[10] invert external trigger 2\r
--> D[9] invert external trigger 1\r
--> D[8] invert external trigger 0\r
-D[7] 40MHz PLL reset\r
-D[6] ADC1 PLL reset\r
-D[5] ADC0 PLL reset\r
-D[4] reserved\r
-D[3:0] 40MHz clock phase setting\r
-\r
-This register is divided into read only bits (D[31:16]) and read/write bits (D[15:0]).\r
-It configures the ADCM hardware resource: setup of FPGA internal PLLs, clock phase between\r
-ADC and APV 40MHz clock and external trigger inputs.\r
-\r
-PLLs must not be in reset during normal operation.\r
-Please note that after reset the PLLs may take some 100ms to be stable again.\r
-\r
-The clock phase shift between ADC and APV clock must be adjusted to accommodate \r
-for delays on PCB and cables. It is mandatory to set this correctly to have the\r
-ADCs sampling the analog signal returning from APVs at the right point in time.\r
-\r
-To activate external trigger inputs set the corresponding bit to 1.\r
-If connected correctly to the CTS no signal inversion is needed.\r
-\r
-Reset value of register is 0x00000000.\r
-\r
-#################################################################################\r
-# #\r
-# 1Wire master for APVs and backplane #\r
-# #\r
-#################################################################################\r
-\r
-0xc000 - 0xc03f : 1Wire master for APV and backplane\r
------------------------------------------------------\r
-\r
-Writing the offset 0xc000 with any value starts one full 1Wire action.\r
-This takes about 1.0s - there is no busy locking for reading the memory.\r
-\r
-offset 0: lower 32bit of serial number \r
-offset 1: upper 32bit of serial number\r
-offset 2: D[15] 0 -> no 1Wire found, 1 -> 1Wire found\r
- D[11:0] temperature of 1Wire IC\r
-offset 3: reserved\r
-\r
-\r
-#################################################################################\r
-# #\r
-# SPI master for FlashROM access #\r
-# #\r
-#################################################################################\r
-\r
-0xd000 - 0xd001 : SPI master for FlashROM\r
-------------------------------------------\r
-\r
-0xd000: SPI control register \r
- \r
-D[31:24] SPI command\r
-D[23:16] address byte high (A[23:16])\r
-D[15:8] address byte mid (A[15:8])\r
-D[7:0] address byte low (A[7:0])\r
-\r
-Full read/write access; writing this register starts the SPI hardware access.\r
-This register is busy locked.\r
-\r
-Reset value of register is 0x00000000.\r
-\r
-\r
-0xd001: SPI status register\r
-\r
-D[31:24] number of data words to be transfered (0x00 -> 1, 0xff -> 256)\r
-D[23:8] reserved\r
-D[7:0] debug information (state machine bits)\r
-\r
-This register is divided into read only bits (D[7:0]) and read/write bits (D[31:24]).\r
-\r
-Reset value of register is 0x00000000.\r
-\r
-\r
-0xd100 - 0xd03f : SPI data memory (FlashROM)\r
----------------------------------------------\r
-\r
-Memory bank for read / write data in SPI transfer. This memory block is not busy locked.\r
-\r
-D[7:0] first byte\r
-D[15:8] second byte\r
-D[23:16] third byte\r
-D[31:24] fourth byte\r
-....\r
-\r
-\r
-#################################################################################\r
-# #\r
-# I2C master for APV slowcontrol access #\r
-# #\r
-#################################################################################\r
-\r
-0x8040 - 0x8040 : I2C master for APV slow control\r
---------------------------------------------------\r
-\r
-This I2C master is tailor made for APV25S1 ASICs. \r
-\r
- write access \r
-D[31] I2C start bit \r
-D[30] I2C ???\r
-D[29:24] I2C speed\r
-D[23:16] I2C address\r
-D[15:8] I2C command\r
-D[7:0] I2C write data\r
-\r
- read access\r
-D[31:24] status bits \r
--> D[31] "running" or "busy" bit\r
--> D[30] "access done" bit\r
--> D[29] "e_ranak" -> I2C repeated address NAK\r
--> D[28] "e_rsf" -> error generating repeated start condition\r
--> D[27] "e_dnak" -> I2C data NAK\r
--> D[26] "e_cnak" -> I2C command NAK\r
--> D[25] "e_anak" -> I2C address NAK\r
--> D[24] "e_sf" -> error generating start condition \r
-D[23:21] reserved\r
-D[20:16] debug\r
-D[15:8] reserved\r
-D[7:0] I2C read data\r
-\r
-\r
--- /dev/null
+#-- Synplicity, Inc.
+#-- Version 9.0
+#-- Project file adcmv3.prj
+#-- Written on 2010.02.11
+
+# add_file options
+add_file -vhdl -lib work "version.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "design/adcmv3_components.vhd"
+
+# ADCMv3 design files
+add_file -vhdl -lib work "design/adcmv3.vhd"
+add_file -vhdl -lib work "design/dbg_reg.vhd"
+add_file -vhdl -lib work "design/reset_handler.vhd"
+add_file -vhdl -lib work "design/reboot_handler.vhd"
+add_file -vhdl -lib work "design/pulse_sync.vhd"
+add_file -vhdl -lib work "design/adc_ch_in.vhd"
+add_file -vhdl -lib work "design/state_sync.vhd"
+add_file -vhdl -lib work "design/apv_sync_handler.vhd"
+add_file -vhdl -lib work "design/apv_trg_handler.vhd"
+add_file -vhdl -lib work "design/eds_buffer_dpram.vhd"
+add_file -vhdl -lib work "design/eds_buf.vhd"
+add_file -vhdl -lib work "design/max_data.vhd"
+add_file -vhdl -lib work "design/real_trg_handler.vhd"
+add_file -vhdl -lib work "design/pulse_stretch.vhd"
+add_file -vhdl -lib work "design/apv_trgctrl.vhd"
+add_file -vhdl -lib work "design/adc_channel_select.vhd"
+add_file -vhdl -lib work "design/crossover.vhd"
+add_file -vhdl -lib work "design/adc_crossover.vhd"
+add_file -vhdl -lib work "design/adc_twochannels.vhd"
+add_file -vhdl -lib work "design/adc_data_handler.vhd"
+add_file -vhdl -lib work "design/frame_status_mem.vhd"
+add_file -vhdl -lib work "design/input_bram.vhd"
+add_file -vhdl -lib work "design/apv_raw_buffer.vhd"
+add_file -vhdl -lib work "design/apv_lock_sm.vhd"
+add_file -vhdl -lib work "design/apv_digital.vhd"
+add_file -vhdl -lib work "design/apv_locker.vhd"
+add_file -vhdl -lib work "design/raw_buf_stage.vhd"
+add_file -vhdl -lib work "design/decoder_8bit.vhd"
+add_file -vhdl -lib work "design/apv_pc_nc_alu.vhd"
+add_file -vhdl -lib work "design/buf_toc.vhd"
+add_file -vhdl -lib work "design/ref_row_sel.vhd"
+add_file -vhdl -lib work "design/frmctr_check.vhd"
+add_file -vhdl -lib work "design/ped_corr_ctrl.vhd"
+add_file -vhdl -lib work "design/adc_apv_map_mem.vhd"
+add_file -vhdl -lib work "design/fifo_1kx18.vhd"
+add_file -vhdl -lib work "design/fifo_2kx27.vhd"
+add_file -vhdl -lib work "design/ipu_fifo_stage.vhd"
+add_file -vhdl -lib work "design/slv_register.vhd"
+add_file -vhdl -lib work "design/adc_snoop_mem.vhd"
+add_file -vhdl -lib work "design/slv_adc_snoop.vhd"
+add_file -vhdl -lib work "design/slv_half_register.vhd"
+add_file -vhdl -lib work "design/slv_status.vhd"
+add_file -vhdl -lib work "design/slv_status_bank.vhd"
+add_file -vhdl -lib work "design/apv_adc_map_mem.vhd"
+add_file -vhdl -lib work "design/slv_register_bank.vhd"
+add_file -vhdl -lib work "design/spi_real_slim.vhd"
+add_file -vhdl -lib work "design/spi_adc_master.vhd"
+add_file -vhdl -lib work "design/slv_onewire_dpram.vhd"
+add_file -vhdl -lib work "design/onewire_master.vhd"
+add_file -vhdl -lib work "design/onewire_spare_one.vhd"
+add_file -vhdl -lib work "design/adc_onewire_map_mem.vhd"
+add_file -vhdl -lib work "design/slv_onewire_memory.vhd"
+add_file -vhdl -lib work "design/i2c_gstart.vhd"
+add_file -vhdl -lib work "design/i2c_sendb.vhd"
+add_file -vhdl -lib work "design/i2c_slim.vhd"
+add_file -vhdl -lib work "design/i2c_master.vhd"
+add_file -vhdl -lib work "design/ped_thr_true.vhd"
+add_file -vhdl -lib work "design/slv_ped_thr_mem.vhd"
+add_file -vhdl -lib work "design/slave_bus.vhd"
+add_file -vhdl -lib work "design/rich_trb.vhd"
+add_file -vhdl -lib work "design/sync_pll_40m.vhd"
+add_file -vhdl -lib work "design/dll_100m.vhd"
+add_file -vhdl -lib work "design/pll_40m.vhd"
+
+# TrbNet design files
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd"
+
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd"
+# add_file -vhdl -lib work "design/sfp_rx_handler.vhd"
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+
+# device options
+set_option -technology LATTICE-ECP2M
+set_option -part LFE2M100E
+set_option -package F900C
+set_option -speed_grade -6
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "adcmv3"
+
+# map options
+set_option -frequency 100
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 0
+# set_option -force_gsr auto
+set_option -force_gsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/adcmv3.edf"
+
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
--- /dev/null
+#!/usr/bin/perl
+###########################################
+# Script file to run the flow
+###########################################
+
+# You need the tunnels before!
+
+use Data::Dumper;
+use warnings;
+use strict;
+
+# Path settings for ispLEVER tools
+my $lattice_path = '/usr/local/opt/synplify/8/isptools';
+
+# Path settings for SynplifyPRO
+my $synplify_path = '/usr/local/opt/synplify/premier';
+# my $synplify_path = '/scratch/rich/synplify/D-2009.12';
+
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}="27000\@localhost";
+
+# Design top level entity
+my $TOPNAME="adcmv3";
+
+# FPGA chip description
+my $FAMILYNAME="LATTICEECP2M";
+my $DEVICENAME="LFE2M100E";
+my $PACKAGE="FPBGA900";
+my $SPEEDGRADE="6";
+
+# benchmarking
+my $CTIME_String = localtime(time);
+print "Script started: $CTIME_String\n";
+system("echo $CTIME_String > workdir/benchmark.txt");
+
+# cleanup in workdir
+system("rm workdir/$TOPNAME.alt");
+system("rm workdir/$TOPNAME.bgn");
+system("rm workdir/$TOPNAME.bit");
+system("rm workdir/$TOPNAME.edf");
+system("rm workdir/$TOPNAME.fse");
+system("rm workdir/$TOPNAME.mrp");
+system("rm workdir/$TOPNAME.ncd");
+system("rm workdir/$TOPNAME.ngd");
+system("rm workdir/$TOPNAME.ngo");
+system("rm workdir/$TOPNAME.ngy");
+system("rm workdir/$TOPNAME.pad");
+system("rm workdir/$TOPNAME.par");
+system("rm workdir/$TOPNAME.sr?");
+system("rm workdir/$TOPNAME.tlg");
+system("rm workdir/$TOPNAME.twr*");
+
+# Create full lpf file
+system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
+
+# Generate timestamp for slowcontrol readback
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+ constant VERSION_NUMBER_TIME : integer := $t;
+
+end package version;
+EOF
+$fh->close;
+
+# Run Synplify on the design
+system("env| grep LM_");
+my $r = "";
+my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj";
+$r=execute($c, "do_not_exit" );
+
+# Check for errors
+chdir "workdir";
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+foreach (@a)
+{
+ if(/\@E:/)
+ {
+ $c="cat $TOPNAME.srr";
+ system($c);
+ print "ERROR_ERROR_ERROR_ERROR_ERROR\n";
+ exit 129;
+ }
+}
+
+# ispLEVER design flow starts here
+# new license file must be given
+$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de";
+
+# EDIF2NGD
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+# NGDBUILD
+$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+execute($c);
+
+# MAP
+my $tpmap = $TOPNAME . "_map" ;
+$c=qq|$lattice_path/ispfpga/bin/lin/map -noinferGSR -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf" -tdm -td_pack|;
+execute($c);
+
+system("rm $TOPNAME.ncd");
+
+# MULTIPAR
+
+my $fh2 = new FileHandle(">$TOPNAME.p2t");
+die "could not open file" if (! defined $fh2);
+print $fh2 <<EOF;
+
+-w
+-i 5
+-l 5
+-n 8
+-t 1
+-s 1
+-c 1
+-e 2
+-m nodelist.txt
+-exp parCDP=1
+-exp parCDR=1
+-exp parPlcInLimit=0
+-exp parPlcInNeighborSize=1
+-exp parPathBased=ON
+-exp parHold=ON
+
+EOF
+$fh2->close;
+
+######################################################################
+# -w # overwrite files
+# -i 15 # maximum number of routing attempts
+# -l 5 # effort level (1-5)
+# -n 1 # starting cost table (n=0 loop)
+# -y # delay summary report
+# -s 12 # number of best results to save
+# -t 1 # start placement with cost table X
+# -c 1 # number of cost-based cleanup passes of the router
+# -e 2 # number of delay-based cleanup passes of the router
+# -m nodelist.txt #
+# -exp parCDP=1 #
+# -exp parCDR=1 #
+# -exp parPlcInLimit=0 #
+# -exp parPlcInNeighborSize=1 #
+# -exp parPathBased=ON #
+# -exp parHold=ON #
+# -exp parHoldLimit=10000 #
+# -exp paruseNBR=1 #
+######################################################################
+
+# real multipar
+$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+execute($c);
+
+# IOR IO Timing Report
+#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+#execute($c);
+
+# TWR Timing Report (setup)
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# TWR Timing Report (hold)
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# BitGen
+#$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+chdir "..";
+
+$CTIME_String = localtime(time);
+print "Script ended: $CTIME_String\n";
+system("echo $CTIME_String >> workdir/benchmark.txt");
+
+exit;
+
+sub execute {
+ my ($c, $op) = @_;
+ #print "option: $op \n";
+ $op = "" if(!$op);
+ print "\n\ncommand to execute: $c \n";
+ $r=system($c);
+ if($r) {
+ print "$!";
+ if($op ne "do_not_exit") {
+ exit;
+ }
+ }
+
+ return $r;
+
+}
--- /dev/null
+#!/usr/bin/perl
+###########################################
+# Script file to run the flow
+###########################################
+
+# You need the tunnels before!
+
+use Data::Dumper;
+use warnings;
+use strict;
+
+# Path settings for ispLEVER tools
+my $lattice_path = '/usr/local/opt/synplify/8/isptools';
+
+# Path settings for SynplifyPRO
+# my $synplify_path = '/usr/local/opt/synplify/premier';
+my $synplify_path = '/scratch/rich/synplify/D-2009.12';
+
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}="27000\@localhost";
+
+# Design top level entity
+my $TOPNAME="adcmv3";
+
+# FPGA chip description
+my $FAMILYNAME="LATTICEECP2M";
+my $DEVICENAME="LFE2M100E";
+my $PACKAGE="FPBGA900";
+my $SPEEDGRADE="6";
+
+# Create full lpf file
+system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
+
+# Generate timestamp for slowcontrol readback
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+ constant VERSION_NUMBER_TIME : integer := $t;
+
+end package version;
+EOF
+$fh->close;
+
+# Run Synplify on the design
+system("env| grep LM_");
+my $r = "";
+my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj";
+$r=execute($c, "do_not_exit" );
+
+# Check for errors
+chdir "workdir";
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+foreach (@a)
+{
+ if(/\@E:/)
+ {
+ $c="cat $TOPNAME.srr";
+ system($c);
+ print "ERROR_ERROR_ERROR_ERROR_ERROR\n";
+ exit 129;
+ }
+}
+
+# ispLEVER design flow starts here
+# new license file must be given
+$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de";
+
+# EDIF2NGD
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+# NGDBUILD
+$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+execute($c);
+
+# MAP
+my $tpmap = $TOPNAME . "_map" ;
+$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+execute($c);
+
+system("rm $TOPNAME.ncd");
+
+$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+execute($c);
+
+# IOR IO Timing Report
+#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+#execute($c);
+
+# TWR Timing Report (setup)
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# TWR Timing Report (hold)
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# BitGen
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|;
+execute($c);
+
+chdir "..";
+
+exit;
+
+sub execute {
+ my ($c, $op) = @_;
+ #print "option: $op \n";
+ $op = "" if(!$op);
+ print "\n\ncommand to execute: $c \n";
+ $r=system($c);
+ if($r) {
+ print "$!";
+ if($op ne "do_not_exit") {
+ exit;
+ }
+ }
+
+ return $r;
+
+}
--- /dev/null
+######################################################################\r
+# PLL 100MHz -> 40MHz\r
+######################################################################\r
+FREQUENCY NET "CLK100M_c" 100.000000 MHz ;\r
+FREQUENCY NET "sysclk_c" 100.000000 MHz ;\r
+\r
+LOCATE COMP "THE_40M_PLL/PLLDINST_0" SITE "PLL_R103C3" ;\r
+FREQUENCY NET "clk_adc" 40.000000 MHz ;\r
+FREQUENCY NET "clk_apv_c" 40.000000 MHz ;\r
+\r
+######################################################################\r
+# DLL 100MHz -> 100MHz\r
+######################################################################\r
+LOCATE COMP "THE_100M_DLL/dll_100m_0_0" SITE "DLL_R103C1" ;\r
+FREQUENCY NET "sysclk" 100.000000 MHz ;\r
+\r
+######################################################################\r
+# CTS 40MHz clock\r
+######################################################################\r
+FREQUENCY NET "cts_clk40m" 40.000000 MHz ;\r
+\r
+######################################################################\r
+# TRBnet SerDes clock constraints\r
+######################################################################\r
+FREQUENCY NET "THE_RICH_TRB/THE_MEDIA_INTERFACE/ff_txfullclk" 200.000000 MHz ;\r
+FREQUENCY NET "THE_RICH_TRB/THE_MEDIA_INTERFACE/ff_txhalfclk" 100.000000 MHz ;\r
+\r
+REGION "MEDIA_INTERFACE_REGION" "R9C100" 10 28 ;\r
+LOCATE UGROUP "THE_RICH_TRB/THE_MEDIA_INTERFACE/MEDIA_INTERFACE_group" REGION "MEDIA_INTERFACE_REGION" ;\r
+\r
+######################################################################\r
+# PLL ADC0: 40MHz\r
+######################################################################\r
+LOCATE COMP "THE_ADC0_HANDLER/THE_ADC_PLL/PLLDINST_0" SITE "SPLL_R67C1" ;\r
+\r
+PERIOD PORT "ADC0_LCLK" 4.1666 ns ;\r
+USE PRIMARY PURE NET "ADC0_LCLK_c" ;\r
+USE EDGE NET "ADC0_LCLK_c" ;\r
+\r
+# Input setup\r
+DEFINE PORT GROUP "ADC0_INPUT" "ADC0_OUT*" "ADC0_ADCLK*" ;\r
+INPUT_SETUP GROUP "ADC0_INPUT" 0.600000 ns HOLD 0.600000 ns CLKPORT "ADC0_LCLK" ;\r
+\r
+# Reconstructed clock\r
+FREQUENCY NET "THE_ADC0_HANDLER/clk40m" 40.000000 MHz ;\r
+USE PRIMARY DCS NET "THE_ADC0_HANDLER/clk40m" ;\r
+\r
+# 240MHz ADC0 regions (namely ser2par for DDR data stream)\r
+REGION "ADC0_REGION" "R59C2" 46 4 ;\r
+LOCATE UGROUP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;\r
+LOCATE UGROUP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;\r
+LOCATE UGROUP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;\r
+LOCATE UGROUP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;\r
+\r
+######################################################################\r
+# PLL ADC1: 40MHz\r
+######################################################################\r
+LOCATE COMP "THE_ADC1_HANDLER/THE_ADC_PLL/PLLDINST_0" SITE "SPLL_R49C1" ;\r
+\r
+PERIOD PORT "ADC1_LCLK" 4.1666 ns ;\r
+USE PRIMARY PURE NET "ADC1_LCLK_c" ;\r
+USE EDGE NET "ADC1_LCLK_c" ;\r
+\r
+# Input setup\r
+DEFINE PORT GROUP "ADC1_INPUT" "ADC1_OUT*" "ADC1_ADCLK*" ;\r
+INPUT_SETUP GROUP "ADC1_INPUT" 0.600000 ns HOLD 0.600000 ns CLKPORT "ADC1_LCLK" ;\r
+\r
+# Reconstructed clock\r
+FREQUENCY NET "THE_ADC1_HANDLER/clk40m" 40.000000 MHz ;\r
+USE PRIMARY DCS NET "THE_ADC1_HANDLER/clk40m" ;\r
+\r
+# 240MHz ADC1 regions (namely ser2par for DDR data stream)\r
+REGION "ADC1_REGION" "R9C2" 49 4 ;\r
+LOCATE UGROUP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;\r
+LOCATE UGROUP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;\r
+LOCATE UGROUP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;\r
+LOCATE UGROUP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;\r
+\r
+######################################################################\r
+# SerDes URC\r
+# SerDes\r
+######################################################################\r
+LOCATE COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/PCSC_INST" SITE "URPCS" ;\r
+\r
+\r
+\r
--- /dev/null
+######################################################################\r
+# PLL 100MHz -> 40MHz\r
+######################################################################\r
+FREQUENCY PORT "clk100m" 100.000000 MHz ;\r
+LOCATE COMP "THE_40M_PLL/PLLDINST_0" SITE "PLL_R103C3" ;\r
+FREQUENCY NET "clk_adc" 40.000000 MHz ;\r
+FREQUENCY NET "clk_apv" 40.000000 MHz ;\r
+\r
+######################################################################\r
+# DLL 100MHz -> 100MHz\r
+######################################################################\r
+LOCATE COMP "THE_100M_DLL/dll_100m_0_0" SITE "DLL_R103C1" ;\r
+FREQUENCY NET "sysclk" 100.000000 MHz ;\r
+\r
+######################################################################\r
+# TRBnet SerDes clock constraints\r
+######################################################################\r
+FREQUENCY NET "THE_RICH_TRB/THE_MEDIA_INTERFACE/ff_txfullclk" 200.000000 MHz ;\r
+FREQUENCY NET "THE_RICH_TRB/THE_MEDIA_INTERFACE/ff_txhalfclk" 100.000000 MHz ;\r
+\r
+REGION "MEDIA_INTERFACE_REGION" "R9C100" 10 28 ;\r
+LOCATE UGROUP "THE_RICH_TRB/THE_MEDIA_INTERFACE/MEDIA_INTERFACE_group" REGION "MEDIA_INTERFACE_REGION" ;\r
+\r
+######################################################################\r
+# PLL ADC0: 40MHz\r
+######################################################################\r
+LOCATE COMP "THE_ADC0_HANDLER/THE_ADC_PLL/PLLDINST_0" SITE "SPLL_R67C1" ;\r
+\r
+PERIOD PORT "ADC0_LCLK" 4.1666 ns ;\r
+USE PRIMARY PURE NET "ADC0_LCLK_c" ;\r
+USE EDGE NET "ADC0_LCLK_c" ;\r
+\r
+# Input setup\r
+DEFINE PORT GROUP "ADC0_INPUT" "ADC0_OUT*" "ADC0_ADCLK*" ;\r
+INPUT_SETUP GROUP "ADC0_INPUT" 0.600000 ns HOLD 0.600000 ns CLKPORT "ADC0_LCLK" ;\r
+\r
+# Reconstructed clock\r
+FREQUENCY NET "THE_ADC0_HANDLER/clk40m" 40.000000 MHz ;\r
+USE PRIMARY DCS NET "THE_ADC0_HANDLER/clk40m" ;\r
+\r
+# 240MHz ADC0 regions (namely ser2par for DDR data stream)\r
+REGION "ADC0_REGION" "R59C2" 46 4 ;\r
+LOCATE UGROUP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;\r
+LOCATE UGROUP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;\r
+LOCATE UGROUP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;\r
+LOCATE UGROUP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;\r
+\r
+######################################################################\r
+# PLL ADC1: 40MHz\r
+######################################################################\r
+LOCATE COMP "THE_ADC1_HANDLER/THE_ADC_PLL/PLLDINST_0" SITE "SPLL_R49C1" ;\r
+\r
+PERIOD PORT "ADC1_LCLK" 4.1666 ns ;\r
+USE PRIMARY PURE NET "ADC1_LCLK_c" ;\r
+USE EDGE NET "ADC1_LCLK_c" ;\r
+\r
+# Input setup\r
+DEFINE PORT GROUP "ADC1_INPUT" "ADC1_OUT*" "ADC1_ADCLK*" ;\r
+INPUT_SETUP GROUP "ADC1_INPUT" 0.600000 ns HOLD 0.600000 ns CLKPORT "ADC1_LCLK" ;\r
+\r
+# Reconstructed clock\r
+FREQUENCY NET "THE_ADC1_HANDLER/clk40m" 40.000000 MHz ;\r
+USE PRIMARY DCS NET "THE_ADC1_HANDLER/clk40m" ;\r
+\r
+# 240MHz ADC1 regions (namely ser2par for DDR data stream)\r
+REGION "ADC1_REGION" "R9C2" 49 4 ;\r
+LOCATE UGROUP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;\r
+LOCATE UGROUP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;\r
+LOCATE UGROUP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;\r
+LOCATE UGROUP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;\r
+\r
+######################################################################\r
+# SerDes URC\r
+# SerDes\r
+######################################################################\r
+LOCATE COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/PCSC_INST" SITE "URPCS" ;\r
+\r
+\r
+\r
--- /dev/null
+DBG_EXP_43 R26\r
+DBG_EXP_42 P25\r
+DBG_EXP_41 T27\r
+DBG_EXP_40 P26\r
+DBG_EXP_39 T26\r
+DBG_EXP_38 N25\r
+DBG_EXP_37 U26\r
+DBG_EXP_36 M25\r
+DBG_EXP_35 V25\r
+DBG_EXP_34 M26\r
+DBG_EXP_33 W25\r
+DBG_EXP_32 L25\r
+DBG_EXP_31 W26\r
+DBG_EXP_30 L26\r
+DBG_EXP_29 Y26\r
+DBG_EXP_28 K25\r
+DBG_EXP_27 Y27\r
+DBG_EXP_26 J26\r
+DBG_EXP_25 AB26\r
+DBG_EXP_24 H25\r
+DBG_EXP_23 AC27\r
+DBG_EXP_22 H26\r
+DBG_EXP_21 U25\r
+DBG_EXP_20 H24\r
+DBG_EXP_19 U28\r
+DBG_EXP_18 G26\r
+DBG_EXP_17 U27\r
+DBG_EXP_16 G25\r
+DBG_EXP_15 L27\r
+DBG_EXP_14 L28\r
+DBG_EXP_13 M28\r
+DBG_EXP_12 K24\r
+DBG_EXP_11 M27\r
+DBG_EXP_10 M30\r
+DBG_EXP_9 N26\r
+DBG_EXP_8 M29\r
+DBG_EXP_7 P27\r
+DBG_EXP_6 L30\r
+DBG_EXP_5 R28\r
+DBG_EXP_4 L29\r
+DBG_EXP_3 R27\r
+DBG_EXP_2 K30\r
+DBG_EXP_1 T28\r
+DBG_EXP_0 K29\r
+\r
+\r
+\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
\r
signal debug : std_logic_vector(15 downto 0);\r
\r
-\r
begin\r
\r
-- Reset synchronizer\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
---------------------------------------------------------------------------\r
-- Reset: we keep the FIFO in reset as long as the PLL is not locked\r
---------------------------------------------------------------------------\r
-next_reset <= reset_in or not adc_data_valid_in;\r
+next_reset <= RESET_IN or not ADC_DATA_VALID_IN;\r
\r
THE_RESET_STATE_SYNC: state_sync\r
port map(\r
STATE_A_IN => next_reset,\r
- CLK_B_IN => clk_apv_in,\r
+ CLK_B_IN => CLK_APV_IN,\r
RESET_B_IN => '0',\r
STATE_B_OUT => reset\r
);\r
---------------------------------------------------------------------------\r
-- Crossover fifo for ADC\r
---------------------------------------------------------------------------\r
-next_fifo_wr_ena <= adc_ce_in and adc_data_valid_in;\r
+next_fifo_wr_ena <= adc_ce_in and ADC_DATA_VALID_IN;\r
next_fifo_rd_ena <= '1' when ( fifo_rd_level > b"0_0101" ) else '0';\r
\r
-SYNC_WRCLK_PROC: process( adc_clk_in )\r
+SYNC_WRCLK_PROC: process( ADC_CLK_IN )\r
begin\r
- if( rising_edge(adc_clk_in) ) then\r
+ if( rising_edge(ADC_CLK_IN) ) then\r
fifo_wr_ena <= next_fifo_wr_ena;\r
end if;\r
end process SYNC_WRCLK_PROC;\r
\r
-SYNC_RDCLK_PROC: process( clk_apv_in )\r
+SYNC_RDCLK_PROC: process( CLK_APV_IN )\r
begin\r
- if( rising_edge(clk_apv_in) ) then\r
+ if( rising_edge(CLK_APV_IN) ) then\r
fifo_rd_ena <= next_fifo_rd_ena;\r
apv_data_valid <= apv_data_valid(1 downto 0) & fifo_rd_ena;\r
end if;\r
\r
THE_CROSSOVER: crossover\r
port map(\r
- DATA(95 downto 84) => adc_data_7_in,\r
- DATA(83 downto 72) => adc_data_6_in,\r
- DATA(71 downto 60) => adc_data_5_in,\r
- DATA(59 downto 48) => adc_data_4_in,\r
- DATA(47 downto 36) => adc_data_3_in,\r
- DATA(35 downto 24) => adc_data_2_in,\r
- DATA(23 downto 12) => adc_data_1_in,\r
- DATA(11 downto 0) => adc_data_0_in,\r
- WRCLOCK => adc_clk_in,\r
- RDCLOCK => clk_apv_in,\r
+ DATA(95 downto 84) => ADC_DATA_7_IN,\r
+ DATA(83 downto 72) => ADC_DATA_6_IN,\r
+ DATA(71 downto 60) => ADC_DATA_5_IN,\r
+ DATA(59 downto 48) => ADC_DATA_4_IN,\r
+ DATA(47 downto 36) => ADC_DATA_3_IN,\r
+ DATA(35 downto 24) => ADC_DATA_2_IN,\r
+ DATA(23 downto 12) => ADC_DATA_1_IN,\r
+ DATA(11 downto 0) => ADC_DATA_0_IN,\r
+ WRCLOCK => ADC_CLK_IN,\r
+ RDCLOCK => CLK_APV_IN,\r
WREN => fifo_wr_ena,\r
RDEN => fifo_rd_ena,\r
RESET => reset, -- this is an async clear input!\r
RPRESET => '0', -- not needed, as OR'ed with RESET\r
- Q(95 downto 84) => apv_data_7_out,\r
- Q(83 downto 72) => apv_data_6_out,\r
- Q(71 downto 60) => apv_data_5_out,\r
- Q(59 downto 48) => apv_data_4_out,\r
- Q(47 downto 36) => apv_data_3_out,\r
- Q(35 downto 24) => apv_data_2_out,\r
- Q(23 downto 12) => apv_data_1_out,\r
- Q(11 downto 0) => apv_data_0_out,\r
+ Q(95 downto 84) => APV_DATA_7_OUT,\r
+ Q(83 downto 72) => APV_DATA_6_OUT,\r
+ Q(71 downto 60) => APV_DATA_5_OUT,\r
+ Q(59 downto 48) => APV_DATA_4_OUT,\r
+ Q(47 downto 36) => APV_DATA_3_OUT,\r
+ Q(35 downto 24) => APV_DATA_2_OUT,\r
+ Q(23 downto 12) => APV_DATA_1_OUT,\r
+ Q(11 downto 0) => APV_DATA_0_OUT,\r
WCNT => fifo_wr_level,\r
RCNT => fifo_rd_level,\r
EMPTY => open,\r
---------------------------------------------------------------------------\r
-- Output signals\r
---------------------------------------------------------------------------\r
-level_rd_out <= fifo_rd_level;\r
-level_wr_out <= fifo_wr_level;\r
-apv_data_valid_out <= apv_data_valid(2);\r
+LEVEL_RD_OUT <= fifo_rd_level;\r
+LEVEL_WR_OUT <= fifo_wr_level;\r
+APV_DATA_VALID_OUT <= apv_data_valid(2);\r
\r
\r
---------------------------------------------------------------------------\r
-- DEBUG signals\r
---------------------------------------------------------------------------\r
-debug_out <= debug;\r
+DEBUG_OUT <= debug;\r
\r
\r
end behavioral;\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
\r
-entity adc_data_handler_new is\r
+entity adc_data_handler is\r
port(\r
RESET_IN : in std_logic;\r
ADC_LCLK_IN : in std_logic; -- LCLK from ADC\r
ADC_DATA0_OUT : out std_logic_vector(11 downto 0);\r
ADC_CE_OUT : out std_logic;\r
ADC_VALID_OUT : out std_logic;\r
+ ADC_SWAP_OUT : out std_logic;\r
DEBUG_OUT : out std_logic_vector(15 downto 0)\r
);\r
end;\r
\r
-architecture behavioral of adc_data_handler_new is\r
+architecture behavioral of adc_data_handler is\r
\r
-- Placer Directives\r
attribute HGROUP : string;\r
signal next_recstore : std_logic;\r
signal recstore : std_logic_vector(3 downto 0);\r
\r
+--NEW\r
+signal realswap : std_logic_vector(3 downto 0);\r
+signal next_recswap : std_logic;\r
+signal recswap : std_logic_vector(3 downto 0);\r
+\r
signal reset : std_logic; -- synchronized to 240MHz local clock\r
\r
signal input_delay : std_logic_vector(3 downto 0);\r
\r
-signal bitcounter : std_logic_vector(2 downto 0);\r
-signal synccounter : std_logic_vector(2 downto 0);\r
-signal next_ce_inc : std_logic;\r
-signal ce_inc : std_logic;\r
-signal next_ce_dec : std_logic;\r
-signal ce_dec : std_logic;\r
+signal bitcounter : unsigned(2 downto 0);\r
+\r
+signal synccounter : unsigned(2 downto 0);\r
+signal next_sync_inc : std_logic;\r
+signal sync_inc : std_logic;\r
+signal next_sync_dec : std_logic;\r
+signal sync_dec : std_logic;\r
signal next_sync_low : std_logic;\r
signal sync_low : std_logic;\r
signal next_sync_high : std_logic;\r
signal sync_high : std_logic;\r
\r
+signal swapcounter : unsigned(2 downto 0);\r
+signal next_swap_inc : std_logic;\r
+signal swap_inc : std_logic;\r
+signal next_swap_dec : std_logic;\r
+signal swap_dec : std_logic;\r
+signal next_swap_low : std_logic;\r
+signal swap_low : std_logic;\r
+signal next_swap_high : std_logic;\r
+signal swap_high : std_logic;\r
+\r
signal debug : std_logic_vector(15 downto 0);\r
\r
begin\r
\r
-- input delay for IDDR, 50ps / unit\r
-input_delay <= pll_ctrl_in;\r
+input_delay <= PLL_CTRL_IN;\r
\r
-- Reset synchronizer\r
THE_RESET_SYNC: state_sync\r
port map(\r
- STATE_A_IN => reset_in,\r
- CLK_B_IN => adc_lclk_in,\r
+ STATE_A_IN => RESET_IN,\r
+ CLK_B_IN => ADC_LCLK_IN,\r
RESET_B_IN => '0',\r
STATE_B_OUT => reset\r
);\r
\r
-- We have to reconstruct the ADC word clock (ADCLK).\r
-- Mind the vector!\r
-adc_adclk_vec(0) <= adc_adclk_in;\r
+adc_adclk_vec(0) <= ADC_ADCLK_IN;\r
\r
THE_ADC_ADCLK_IN: adc_ch_in\r
port map(\r
DEL => input_delay,\r
- ECLK => adc_lclk_in,\r
- SCLK => adc_lclk_in,\r
+ ECLK => ADC_LCLK_IN,\r
+ SCLK => ADC_LCLK_IN,\r
RST => '0',\r
DATA => adc_adclk_vec,\r
Q => adc_adclk\r
THE_DIN_0: adc_ch_in\r
port map(\r
DEL => input_delay,\r
- ECLK => adc_lclk_in,\r
- SCLK => adc_lclk_in,\r
+ ECLK => ADC_LCLK_IN,\r
+ SCLK => ADC_LCLK_IN,\r
RST => '0',\r
- DATA => adc_chnl_in(0 downto 0),\r
+ DATA => ADC_CHNL_IN(0 downto 0),\r
Q => adc_ch_0_mux\r
);\r
THE_DIN_1: adc_ch_in\r
port map(\r
DEL => input_delay,\r
- ECLK => adc_lclk_in,\r
- SCLK => adc_lclk_in,\r
+ ECLK => ADC_LCLK_IN,\r
+ SCLK => ADC_LCLK_IN,\r
RST => '0',\r
- DATA => adc_chnl_in(1 downto 1),\r
+ DATA => ADC_CHNL_IN(1 downto 1),\r
Q => adc_ch_1_mux\r
);\r
THE_ADC_0_1_CH: adc_twochannels\r
port map(\r
- CLK_IN => adc_lclk_in,\r
+ CLK_IN => ADC_LCLK_IN,\r
RESET_IN => reset,\r
CLOCK_IN => adc_adclk,\r
DATA_0_IN => adc_ch_0_mux,\r
DATA_0_OUT => last_adc_0_ch,\r
DATA_1_OUT => last_adc_1_ch,\r
STORE_OUT => realstore(0),\r
- SWAP_OUT => open,\r
+ SWAP_OUT => realswap(0), --open,\r
CLOCK_OUT => open,\r
DEBUG_OUT => open\r
);\r
THE_DIN_2: adc_ch_in\r
port map(\r
DEL => input_delay,\r
- ECLK => adc_lclk_in,\r
- SCLK => adc_lclk_in,\r
+ ECLK => ADC_LCLK_IN,\r
+ SCLK => ADC_LCLK_IN,\r
RST => '0',\r
- DATA => adc_chnl_in(2 downto 2),\r
+ DATA => ADC_CHNL_IN(2 downto 2),\r
Q => adc_ch_2_mux\r
);\r
THE_DIN_3: adc_ch_in\r
port map(\r
DEL => input_delay,\r
- ECLK => adc_lclk_in,\r
- SCLK => adc_lclk_in,\r
+ ECLK => ADC_LCLK_IN,\r
+ SCLK => ADC_LCLK_IN,\r
RST => '0',\r
- DATA => adc_chnl_in(3 downto 3),\r
+ DATA => ADC_CHNL_IN(3 downto 3),\r
Q => adc_ch_3_mux\r
);\r
THE_ADC_2_3_CH: adc_twochannels\r
port map(\r
- CLK_IN => adc_lclk_in,\r
+ CLK_IN => ADC_LCLK_IN,\r
RESET_IN => reset,\r
CLOCK_IN => adc_adclk,\r
DATA_0_IN => adc_ch_2_mux,\r
DATA_0_OUT => last_adc_2_ch,\r
DATA_1_OUT => last_adc_3_ch,\r
STORE_OUT => realstore(1),\r
- SWAP_OUT => open,\r
+ SWAP_OUT => realswap(1), --open,\r
CLOCK_OUT => open,\r
DEBUG_OUT => open\r
);\r
THE_DIN_4: adc_ch_in\r
port map(\r
DEL => input_delay,\r
- ECLK => adc_lclk_in,\r
- SCLK => adc_lclk_in,\r
+ ECLK => ADC_LCLK_IN,\r
+ SCLK => ADC_LCLK_IN,\r
RST => '0',\r
- DATA => adc_chnl_in(4 downto 4),\r
+ DATA => ADC_CHNL_IN(4 downto 4),\r
Q => adc_ch_4_mux\r
);\r
THE_DIN_5: adc_ch_in\r
port map(\r
DEL => input_delay,\r
- ECLK => adc_lclk_in,\r
- SCLK => adc_lclk_in,\r
+ ECLK => ADC_LCLK_IN,\r
+ SCLK => ADC_LCLK_IN,\r
RST => '0',\r
- DATA => adc_chnl_in(5 downto 5),\r
+ DATA => ADC_CHNL_IN(5 downto 5),\r
Q => adc_ch_5_mux\r
);\r
THE_ADC_4_5_CH: adc_twochannels\r
port map(\r
- CLK_IN => adc_lclk_in,\r
+ CLK_IN => ADC_LCLK_IN,\r
RESET_IN => reset,\r
CLOCK_IN => adc_adclk,\r
DATA_0_IN => adc_ch_4_mux,\r
DATA_0_OUT => last_adc_4_ch,\r
DATA_1_OUT => last_adc_5_ch,\r
STORE_OUT => realstore(2),\r
- SWAP_OUT => open,\r
+ SWAP_OUT => realswap(2), --open,\r
CLOCK_OUT => open,\r
DEBUG_OUT => open\r
);\r
THE_DIN_6: adc_ch_in\r
port map(\r
DEL => input_delay,\r
- ECLK => adc_lclk_in,\r
- SCLK => adc_lclk_in,\r
+ ECLK => ADC_LCLK_IN,\r
+ SCLK => ADC_LCLK_IN,\r
RST => '0',\r
- DATA => adc_chnl_in(6 downto 6),\r
+ DATA => ADC_CHNL_IN(6 downto 6),\r
Q => adc_ch_6_mux\r
);\r
THE_DIN_7: adc_ch_in\r
port map(\r
DEL => input_delay,\r
- ECLK => adc_lclk_in,\r
- SCLK => adc_lclk_in,\r
+ ECLK => ADC_LCLK_IN,\r
+ SCLK => ADC_LCLK_IN,\r
RST => '0',\r
- DATA => adc_chnl_in(7 downto 7),\r
+ DATA => ADC_CHNL_IN(7 downto 7),\r
Q => adc_ch_7_mux\r
);\r
THE_ADC_6_7_CH: adc_twochannels\r
port map(\r
- CLK_IN => adc_lclk_in,\r
+ CLK_IN => ADC_LCLK_IN,\r
RESET_IN => reset,\r
CLOCK_IN => adc_adclk,\r
DATA_0_IN => adc_ch_6_mux,\r
DATA_0_OUT => last_adc_6_ch,\r
DATA_1_OUT => last_adc_7_ch,\r
STORE_OUT => realstore(3),\r
- SWAP_OUT => open,\r
+ SWAP_OUT => realswap(3), --open,\r
CLOCK_OUT => open,\r
DEBUG_OUT => open\r
);\r
-- Clock reconstruction (will only work if all four units work in perfect alignment)\r
next_recstore <= '1' when ( realstore = b"1111" ) else '0';\r
\r
+-- swap indicator for data reconstruction\r
+next_recswap <= '1' when ( realswap = b"1111" ) else '0';\r
+\r
-- Synchronising stage\r
THE_SYNC_PROC: process( adc_lclk_in )\r
begin\r
if( rising_edge(adc_lclk_in) ) then\r
recstore(3 downto 0) <= recstore(2 downto 0) & next_recstore;\r
+ recswap(3 downto 0) <= recswap(2 downto 0) & next_recswap;\r
sync_low <= next_sync_low;\r
sync_high <= next_sync_high;\r
- ce_inc <= next_ce_inc;\r
- ce_dec <= next_ce_dec;\r
+ sync_inc <= next_sync_inc;\r
+ sync_dec <= next_sync_dec;\r
+ swap_low <= next_swap_low;\r
+ swap_high <= next_swap_high;\r
+ swap_inc <= next_swap_inc;\r
+ swap_dec <= next_swap_dec;\r
end if;\r
end process THE_SYNC_PROC;\r
\r
-THE_BIT_COUNTER: process( adc_lclk_in )\r
+-- Bit counter for reconstructed data\r
+THE_BIT_COUNTER: process( ADC_LCLK_IN )\r
begin\r
- if( rising_edge(adc_lclk_in) ) then\r
+ if( rising_edge(ADC_LCLK_IN) ) then\r
if( recstore(0) = '1' ) then\r
bitcounter <= (others => '0');\r
else\r
end if;\r
end process THE_BIT_COUNTER;\r
\r
+-- Inhibits for the sync counter: only [7:0] are allowed as values\r
next_sync_low <= '1' when (synccounter = b"000") else '0';\r
next_sync_high <= '1' when (synccounter = b"111") else '0';\r
\r
-next_ce_inc <= '1' when ( (bitcounter = b"101") and (recstore(0) = '1') and (sync_high = '0') ) else '0';\r
-next_ce_dec <= '1' when ( (bitcounter = b"101") and (recstore(0) = '0') and (sync_low = '0') ) else '0';\r
+-- up/down count enables for sync counter\r
+next_sync_inc <= '1' when ( (bitcounter = b"101") and (recstore(0) = '1') and (sync_high = '0') ) else '0';\r
+next_sync_dec <= '1' when ( (bitcounter = b"101") and (recstore(0) = '0') and (sync_low = '0') ) else '0';\r
\r
-THE_SYNC_COUNTER: process( adc_lclk_in )\r
+THE_SYNC_COUNTER: process( ADC_LCLK_IN )\r
begin\r
- if( rising_edge(adc_lclk_in) ) then\r
+ if( rising_edge(ADC_LCLK_IN) ) then\r
if( reset = '1' ) then\r
synccounter <= (others => '0');\r
- elsif( (ce_inc = '1') and (ce_dec = '0') ) then\r
+ elsif( (sync_inc = '1') and (sync_dec = '0') ) then\r
synccounter <= synccounter + 1;\r
- elsif( (ce_inc = '0') and (ce_dec = '1') ) then\r
+ elsif( (sync_inc = '0') and (sync_dec = '1') ) then\r
synccounter <= synccounter - 1;\r
end if;\r
end if;\r
end process THE_SYNC_COUNTER;\r
\r
+-- Inhibits for the swap counter: only [7:0] are allowed as values\r
+next_swap_low <= '1' when (swapcounter = b"000") else '0';\r
+next_swap_high <= '1' when (swapcounter = b"111") else '0';\r
+\r
+-- up/down count enables for sync counter\r
+next_swap_inc <= '1' when ( (bitcounter = b"101") and (recswap(0) = '1') and (swap_high = '0') ) else '0';\r
+next_swap_dec <= '1' when ( (bitcounter = b"101") and (recswap(0) = '0') and (swap_low = '0') ) else '0';\r
+\r
+THE_SWAP_COUNTER: process( ADC_LCLK_IN )\r
+begin\r
+ if( rising_edge(ADC_LCLK_IN) ) then\r
+ if( reset = '1' ) then\r
+ swapcounter <= (others => '0');\r
+ elsif( (swap_inc = '1') and (swap_dec = '0') ) then\r
+ swapcounter <= swapcounter + 1;\r
+ elsif( (swap_inc = '0') and (swap_dec = '1') ) then\r
+ swapcounter <= swapcounter - 1;\r
+ end if;\r
+ end if;\r
+end process THE_SWAP_COUNTER;\r
+\r
+-- debug signals\r
debug(15 downto 11) <= (others => '0');\r
-debug(10 downto 8) <= synccounter;\r
-debug(7) <= sync_low;\r
-debug(6) <= sync_high;\r
-debug(5) <= ce_dec;\r
-debug(4) <= ce_inc;\r
+debug(10 downto 8) <= std_logic_vector(swapcounter);\r
+debug(7) <= swap_low;\r
+debug(6) <= swap_high;\r
+debug(5) <= swap_dec;\r
+debug(4) <= swap_inc;\r
debug(3) <= '0';\r
-debug(2 downto 0) <= bitcounter;\r
+debug(2 downto 0) <= std_logic_vector(bitcounter);\r
\r
-----------------------------------------------------------------------\r
-- generate 8 ADC channel inputs and clock transfer registers\r
-----------------------------------------------------------------------\r
-THE_DATA_DELAY_PROC: process( adc_lclk_in )\r
+THE_DATA_DELAY_PROC: process( ADC_LCLK_IN )\r
begin\r
- if( rising_edge(adc_lclk_in) ) then\r
+ if( rising_edge(ADC_LCLK_IN) ) then\r
buf_adc_7_ch <= last_adc_7_ch;\r
buf_adc_6_ch <= last_adc_6_ch;\r
buf_adc_5_ch <= last_adc_5_ch;\r
\r
\r
-- output signals\r
-adc_data7_out <= buf_adc_7_ch;\r
-adc_data6_out <= buf_adc_6_ch;\r
-adc_data5_out <= buf_adc_5_ch;\r
-adc_data4_out <= buf_adc_4_ch;\r
-adc_data3_out <= buf_adc_3_ch;\r
-adc_data2_out <= buf_adc_2_ch;\r
-adc_data1_out <= buf_adc_1_ch;\r
-adc_data0_out <= buf_adc_0_ch;\r
-adc_ce_out <= recstore(3);\r
-adc_valid_out <= sync_high;\r
-\r
-debug_out(15 downto 0) <= debug;\r
+ADC_DATA7_OUT <= buf_adc_7_ch;\r
+ADC_DATA6_OUT <= buf_adc_6_ch;\r
+ADC_DATA5_OUT <= buf_adc_5_ch;\r
+ADC_DATA4_OUT <= buf_adc_4_ch;\r
+ADC_DATA3_OUT <= buf_adc_3_ch;\r
+ADC_DATA2_OUT <= buf_adc_2_ch;\r
+ADC_DATA1_OUT <= buf_adc_1_ch;\r
+ADC_DATA0_OUT <= buf_adc_0_ch;\r
+ADC_CE_OUT <= recstore(3);\r
+ADC_VALID_OUT <= sync_high;\r
+ADC_SWAP_OUT <= swap_high;\r
+\r
+DEBUG_OUT(15 downto 0) <= debug;\r
\r
end behavioral;\r
-
\ No newline at end of file
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+--use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.adcmv3_components.all;\r
+\r
+library ecp2m;\r
+use ecp2m.components.all;\r
+\r
+entity adcmv3 is\r
+port( \r
+ CLK100M : in std_logic; -- OK -- 100MHz LVDS clock \r
+ -- trigger inputs\r
+ EXT_IN : in std_logic_vector(3 downto 0); -- OK -- external triggers\r
+ -- APV stuff\r
+ APV0A_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
+ APV0B_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
+ APV0A_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
+ APV0B_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
+ APV0_RST : out std_logic; -- OK -- APV bank 0: reset signal, low active\r
+ APV0_SDA : inout std_logic; -- OK -- APV bank 0: I2C bus SDA\r
+ APV0_SCL : inout std_logic; -- OK -- APV bank 0: I2C bus SCL\r
+ ENA_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
+ APV1A_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
+ APV1B_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
+ APV1A_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
+ APV1B_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
+ APV1_RST : out std_logic; -- OK -- APV bank 1: reset signal, low active\r
+ APV1_SDA : inout std_logic; -- OK -- APV bank 1: I2C bus SDA\r
+ APV1_SCL : inout std_logic; -- OK -- APV bank 1: I2C bus SCL\r
+ ENB_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
+ -- ADC0 stuff\r
+ ADC0_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
+ ADC0_RST : out std_logic; -- OK -- ADC reset signal\r
+ ADC0_PD : out std_logic; -- OK -- ADC powerdown signal\r
+ ADC0_CS : out std_logic; -- OK -- ADC /CS signal\r
+ ADC0_SDI : out std_logic; -- OK -- ADC serial data in\r
+ ADC0_SCK : out std_logic; -- OK -- ADC serial clock\r
+ ADC0_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
+ ADC0_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
+ ADC0_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
+ -- ADC1 stuff\r
+ ADC1_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
+ ADC1_RST : out std_logic; -- OK -- ADC reset signal\r
+ ADC1_PD : out std_logic; -- OK -- ADC powerdown signal\r
+ ADC1_CS : out std_logic; -- OK -- ADC /CS signal\r
+ ADC1_SDI : out std_logic; -- OK -- ADC serial data in\r
+ ADC1_SCK : out std_logic; -- OK -- ADC serial clock\r
+ ADC1_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
+ ADC1_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
+ ADC1_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
+ -- uC connections\r
+ UC_RESET : in std_logic; -- OK -- uC reset, high active\r
+ UC_REBOOT : out std_logic; -- OK -- was UC_FPGA(3), requests FPGA reboot\r
+ -- SerDes pins \r
+ HDINN2 : in std_logic; -- highspeed INPUT\r
+ HDINP2 : in std_logic; --\r
+ HDOUTN2 : out std_logic; -- highspeed OUTPUT\r
+ HDOUTP2 : out std_logic; -- \r
+ SD_PRESENT : in std_logic; -- OK -- Present signal from SFP\r
+ SD_LOS : in std_logic; -- OK -- Loss Of Signal from SFP\r
+ SD_TXDIS : out std_logic; -- OK -- SFP transmitter disable\r
+ ADCM_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on ADCM\r
+ -- Backplane sense wires\r
+ BP_MODULE : in std_logic_vector(3 downto 0); -- OK -- module number input from backplane\r
+ BP_SECTOR : in std_logic_vector(3 downto 0); -- OK -- sector number input from backplane\r
+ BP_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on backplane \r
+ BP_LED : out std_logic; -- OK -- backplane LED \r
+ -- LEDs\r
+ FPGA_LED : out std_logic_vector(6 downto 3); -- OK -- general purpose LEDS\r
+ FPGA_LED_RXD : out std_logic; -- OK -- FPGA_LED(2)\r
+ FPGA_LED_TXD : out std_logic; -- OK -- FPGA_LED(1)\r
+ FPGA_LED_LINK : out std_logic; -- OK -- FPGA_LED(0)\r
+ FPGA_LED_PLL : out std_logic; -- OK -- PLL locked \r
+ FPGA_LED_ADC : out std_logic_vector(1 downto 0); -- OK -- ADCx OK LED \r
+ -- 1Wire chips on APV FEs\r
+ APV0_1W : inout std_logic_vector(7 downto 0);\r
+ APV1_1W : inout std_logic_vector(7 downto 0);\r
+ -- SPI FlashROM connections\r
+ U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM\r
+ U_SPI_SCK : out std_logic; -- OK -- clock\r
+ U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM\r
+ U_SPI_SDO : in std_logic -- OK -- connects to SO on the FlashROM\r
+ -- Debug connections\r
+-- DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header\r
+);\r
+end;\r
+\r
+architecture adcmv3 of adcmv3 is\r
+\r
+-- Signals\r
+-- Clock related signals\r
+signal clk100m_locked : std_logic; -- not needed at the moment\r
+signal sysclk : std_logic; -- clean 100MHz for distribution\r
+\r
+signal adc0_ce : std_logic;\r
+signal adc0_valid : std_logic;\r
+signal adc0_swap : std_logic;\r
+signal adc0_reset : std_logic;\r
+signal adc0_powerdown : std_logic;\r
+signal adc1_ce : std_logic;\r
+signal adc1_valid : std_logic;\r
+signal adc1_swap : std_logic;\r
+signal adc1_reset : std_logic;\r
+signal adc1_powerdown : std_logic;\r
+\r
+signal clk_adc : std_logic; -- 40MHz for ADC operation\r
+signal clk_apv : std_logic; -- 40MHz for APV operation (phase shiftable!)\r
+signal clk40m_locked : std_logic;\r
+signal clk40m_reset : std_logic;\r
+\r
+signal async_reset : std_logic;\r
+\r
+-- APV related signals\r
+signal apv_sda_out : std_logic; -- APV SDA\r
+signal apv_sda_in : std_logic;\r
+signal apv_scl_out : std_logic; -- APV SCL\r
+signal apv_scl_in : std_logic;\r
+signal apv_trg : std_logic; -- real APV trigger signal\r
+signal apv_sync : std_logic; -- artificial signal\r
+signal apv_frame_reqd : std_logic; -- one 100MHz pulse per requested frame\r
+signal apv0_reset : std_logic;\r
+signal apv1_reset : std_logic;\r
+signal frontend_reset : std_logic;\r
+signal apv_reset : std_logic;\r
+signal adc_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8]\r
+signal lvds_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8]\r
+\r
+-- Control signals\r
+signal ctrl_pll : std_logic_vector(15 downto 0); -- PLL control register\r
+signal status_pll : std_logic_vector(15 downto 0); -- PLL status register\r
+signal ctrl_trg : std_logic_vector(31 downto 0); -- TRG control register\r
+signal ctrl_lvl : std_logic_vector(31 downto 0); -- LVL control register\r
+ \r
+signal ctrl_bitlow : std_logic_vector(11 downto 0); -- BIT_LOW setting for APV digital header\r
+signal ctrl_bithigh : std_logic_vector(11 downto 0); -- BIT_HIGH setting for APV digital header\r
+signal ctrl_flatlow : std_logic_vector(11 downto 0); -- FLAT_LOW setting\r
+signal ctrl_flathigh : std_logic_vector(11 downto 0); -- FLAT_HIGH setting\r
+\r
+signal maximum_trg : std_logic_vector(3 downto 0);\r
+\r
+signal raw_buf_full : std_logic;\r
+signal eds_buf_full : std_logic;\r
+signal eds_buf_level : std_logic_vector(4 downto 0);\r
+\r
+-- regIO data bus\r
+signal regio_addr : std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);\r
+signal regio_read_enable : std_logic;\r
+signal regio_write_enable : std_logic;\r
+signal regio_data_wr : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
+signal regio_data_rd : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
+signal regio_dataready : std_logic;\r
+signal regio_no_more_data : std_logic;\r
+signal regio_write_ack : std_logic;\r
+signal regio_unknown_addr : std_logic;\r
+signal regio_timeout : std_logic;\r
+\r
+-- common status / control registers from RegIO\r
+signal common_stat_reg : std_logic_vector(8*32-1 downto 0);\r
+signal common_ctrl_reg : std_logic_vector(3*32-1 downto 0);\r
+\r
+-- user defined "quick'n'dirty" registers\r
+signal simple_status : std_logic_vector(127 downto 0);\r
+signal simple_control : std_logic_vector(63 downto 0);\r
+\r
+-- debug signals\r
+signal test_reg : std_logic_vector(31 downto 0);\r
+signal trgctrl_debug : std_logic_vector(63 downto 0);\r
+signal raw_buf_debug : std_logic_vector(63 downto 0);\r
+--signal trbrich_debug : std_logic_vector(63 downto 0);\r
+--signal slave_debug : std_logic_vector(63 downto 0);\r
+--signal fifo_debug : std_logic_vector(63 downto 0);\r
+\r
+-- EDS / BUFFER signals (raw buf -> ped corr)\r
+signal eds_data : std_logic_vector(39 downto 0);\r
+signal eds_avail : std_logic;\r
+signal eds_done : std_logic;\r
+signal buf_addr : std_logic_vector(6 downto 0);\r
+signal buf_done : std_logic;\r
+signal buf_tick : std_logic_vector(15 downto 0);\r
+signal buf_start : std_logic_vector(15 downto 0);\r
+signal buf_ready : std_logic_vector(15 downto 0); -- just for debugging!\r
+\r
+type reg_38bit_t is array (0 to 15) of std_logic_vector(37 downto 0);\r
+signal buf_data : reg_38bit_t;\r
+\r
+signal thr_addr : std_logic_vector(6 downto 0);\r
+type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
+signal thr_data : reg_18bit_t;\r
+signal ped_data : reg_18bit_t;\r
+\r
+-- FIFO / DHDR signals (ped corr -> ipu stage)\r
+signal dhdr_data : std_logic_vector(31 downto 0);\r
+signal dhdr_length : std_logic_vector(15 downto 0);\r
+signal dhdr_store : std_logic;\r
+signal dhdr_buf_full : std_logic;\r
+\r
+signal fifo_start : std_logic;\r
+signal fifo_done : std_logic;\r
+signal fifo_we : std_logic_vector(15 downto 0);\r
+signal fifo_space_req : std_logic_vector(11 downto 0);\r
+type reg_40bit_t is array (0 to 15) of std_logic_vector(39 downto 0);\r
+signal fifo_data : reg_40bit_t;\r
+type reg_32bit_t is array (0 to 15) of std_logic_vector(31 downto 0);\r
+signal fifo_status : reg_32bit_t;\r
+\r
+signal ipu_handler_status : std_logic_vector(31 downto 0);\r
+signal lvl1_release_status : std_logic_vector(31 downto 0);\r
+\r
+-- APV control / status signals\r
+type reg_16bit_t is array (0 to 15) of std_logic_vector(15 downto 0);\r
+signal adc_ctrl_reg : reg_16bit_t;\r
+signal adc_stat_reg : reg_16bit_t;\r
+signal raw_buf_dbg : reg_16bit_t;\r
+\r
+--signal debug : std_logic_vector(42 downto 0);\r
+--signal debug_q : std_logic_vector(42 downto 0);\r
+--signal debug_qq : std_logic_vector(42 downto 0);\r
+--signal debug_clk : std_logic;\r
+ \r
+-- LVL1 application interface\r
+signal lvl1_trg_type : std_logic_vector(3 downto 0);\r
+signal lvl1_trg_received : std_logic;\r
+signal lvl1_trg_number : std_logic_vector(15 downto 0);\r
+signal lvl1_trg_code : std_logic_vector(7 downto 0);\r
+signal lvl1_trg_information : std_logic_vector(23 downto 0);\r
+signal lvl1_error_pattern : std_logic_vector(31 downto 0);\r
+signal lvl1_trg_release : std_logic;\r
+signal lvl1_trg_missing : std_logic;\r
+signal lvl1_int_trg_number : std_logic_vector(15 downto 0);\r
+signal lvl1_int_trg_update : std_logic;\r
+signal timing_trg_found : std_logic;\r
+signal timing_trg_too_long : std_logic;\r
+\r
+-- IPU application interface\r
+signal ipu_number : std_logic_vector(15 downto 0);\r
+signal ipu_information : std_logic_vector(7 downto 0);\r
+signal ipu_start_readout : std_logic;\r
+signal ipu_data : std_logic_vector(31 downto 0);\r
+signal ipu_dataready : std_logic;\r
+signal ipu_readout_finished : std_logic;\r
+signal ipu_read : std_logic;\r
+signal ipu_length : std_logic_vector(15 downto 0);\r
+signal ipu_error_pattern : std_logic_vector(31 downto 0);\r
+signal ipu_last_num : std_logic_vector(31 downto 0);\r
+\r
+signal local_lvl1_counter : std_logic_vector(15 downto 0);\r
+signal local_lvl2_counter : std_logic_vector(15 downto 0);\r
+\r
+-- ADC signals\r
+type reg_12bit_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
+signal adc_raw_data : reg_12bit_t; -- ADC specific clock domain\r
+signal adc_data : reg_12bit_t; -- common APV clock domain\r
+\r
+signal adc1_testdata : std_logic_vector(11 downto 0);\r
+signal adc0_testdata : std_logic_vector(11 downto 0);\r
+signal adc1_select : std_logic_vector(2 downto 0);\r
+signal adc0_select : std_logic_vector(2 downto 0);\r
+\r
+-- input synchronizing\r
+signal bp_sector_q : std_logic_vector(3 downto 0);\r
+signal bp_sector_qq : std_logic_vector(3 downto 0);\r
+signal bp_module_q : std_logic_vector(3 downto 0);\r
+signal bp_module_qq : std_logic_vector(3 downto 0);\r
+\r
+signal lsm_state_bits : std_logic_vector(3 downto 0);\r
+signal reset_by_trb : std_logic;\r
+signal global_sync_reset : std_logic;\r
+\r
+signal adc0_iodelay : std_logic_vector(3 downto 0);\r
+signal adc1_iodelay : std_logic_vector(3 downto 0);\r
+\r
+signal cts_clk40m : std_logic;\r
+signal cts_clk40m_locked : std_logic;\r
+signal test_reg40m : std_logic;\r
+\r
+signal serious_error_flag : std_logic;\r
+signal error_flag : std_logic;\r
+signal warning_flag : std_logic;\r
+signal note_flag : std_logic;\r
+\r
+signal broken_buf : std_logic_vector(15 downto 0);\r
+signal next_not_configured : std_logic;\r
+signal not_configured : std_logic;\r
+\r
+signal apv_error : std_logic_vector(15 downto 0);\r
+signal next_fe_error : std_logic;\r
+signal fe_error : std_logic;\r
+\r
+signal tick_10s : std_logic;\r
+\r
+begin\r
+\r
+\r
+----------------------------------------\r
+-- Async reset assignment --\r
+----------------------------------------\r
+async_reset <= uc_reset; -- uC reset pin\r
+\r
+\r
+----------------------------------------\r
+-- Reset handler / spike surpression --\r
+----------------------------------------\r
+THE_RESET_HANDLER: reset_handler \r
+generic map (\r
+ RESET_DELAY => x"00ff"\r
+)\r
+port map (\r
+ CLEAR_IN => async_reset,\r
+ CLEAR_N_IN => '1', -- unused\r
+ CLK_IN => clk100m,\r
+ SYSCLK_IN => sysclk,\r
+ PLL_LOCKED_IN => clk100m_locked,\r
+ RESET_IN => common_ctrl_reg(3),\r
+ TRB_RESET_IN => reset_by_trb,\r
+ CLEAR_OUT => open,\r
+ RESET_OUT => global_sync_reset,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- Reboot handler (pulse triggered) --\r
+----------------------------------------\r
+THE_REBOOT_HANDLER: reboot_handler\r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ CLK_IN => sysclk,\r
+ START_IN => common_ctrl_reg(15),\r
+ REBOOT_OUT => uc_reboot,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- 100MHz PLL -> 40MHz / 100MHz --\r
+----------------------------------------\r
+-- 100MHz PLL, generating 40MHz and phase shifted 40MHz\r
+THE_40M_PLL: PLL_40M\r
+port map( \r
+ CLK => clk100m,\r
+ RESET => clk40m_reset,\r
+ DPAMODE => '1', -- dynamic control \r
+ DPHASE0 => ctrl_pll(0),\r
+ DPHASE1 => ctrl_pll(1),\r
+ DPHASE2 => ctrl_pll(2),\r
+ DPHASE3 => ctrl_pll(3),\r
+ CLKOP => clk_apv, -- fixed phase, used for logic \r
+ CLKOS => clk_adc, -- phase adjustable, for ODDRXC only\r
+ LOCK => clk40m_locked\r
+);\r
+clk40m_reset <= ctrl_pll(7);\r
+\r
+-- 100MHz DLL, used for clock injection delay removal\r
+THE_100M_DLL: dll_100m\r
+port map( \r
+ CLK => clk100m,\r
+ RESETN => '1',\r
+ ALUHOLD => '0',\r
+ CLKOP => sysclk,\r
+ CLKOS => open,\r
+ LOCK => clk100m_locked\r
+);\r
+\r
+-- 40MHz PLL, takes central clock distributed by CTS\r
+THE_SYNC_PLL: sync_pll_40m\r
+port map(\r
+ CLK => ext_in(3),\r
+ RESET => ctrl_pll(4),\r
+ CLKOP => cts_clk40m,\r
+ LOCK => cts_clk40m_locked\r
+);\r
+\r
+THE_TEST_REG: process( cts_clk40m, cts_clk40m_locked )\r
+begin\r
+ if( cts_clk40m_locked = '0' ) then\r
+ test_reg40m <= '0';\r
+ else\r
+ if( rising_edge(cts_clk40m) ) then\r
+ test_reg40m <= not test_reg40m;\r
+ end if;\r
+ end if;\r
+end process THE_TEST_REG;\r
+\r
+----------------------------------------\r
+-- TRB endpoint --\r
+----------------------------------------\r
+THE_RICH_TRB: rich_trb\r
+port map( \r
+ CLK100M_IN => clk100m, -- SerDes exclusive clock\r
+ SYSCLK_IN => sysclk, -- fabric clock\r
+ RESET_IN => global_sync_reset,\r
+ SD_RXD_P_IN => hdinp2,\r
+ SD_RXD_N_IN => hdinn2,\r
+ SD_TXD_P_OUT => hdoutp2, \r
+ SD_TXD_N_OUT => hdoutn2,\r
+ SD_PRESENT_IN => sd_present,\r
+ SD_TXDIS_OUT => sd_txdis,\r
+ SD_LOS_IN => sd_los,\r
+ ONEWIRE_INOUT => adcm_onewire,\r
+ -- common regIO status / control registers\r
+ COMMON_STAT_REG_IN => common_stat_reg,\r
+ COMMON_CTRL_REG_OUT => common_ctrl_reg,\r
+ -- status register input to regIO / control register output from regIO\r
+ CONTROL_OUT => simple_control,\r
+ STATUS_IN => simple_status,\r
+ -- LVL1 signals\r
+ LVL1_TRG_TYPE_OUT => lvl1_trg_type,\r
+ LVL1_TRG_RECEIVED_OUT => lvl1_trg_received,\r
+ LVL1_TRG_NUMBER_OUT => lvl1_trg_number,\r
+ LVL1_TRG_CODE_OUT => lvl1_trg_code,\r
+ LVL1_TRG_INFORMATION_OUT => lvl1_trg_information,\r
+ LVL1_ERROR_PATTERN_IN => lvl1_error_pattern,\r
+ LVL1_TRG_RELEASE_IN => lvl1_trg_release,\r
+ LVL1_INT_TRG_NUMBER_OUT => lvl1_int_trg_number, -- internal trigger counter\r
+ LVL1_INT_TRG_UPDATE_OUT => lvl1_int_trg_update, -- update on internal trigger counter\r
+ TIMING_TRG_FOUND_IN => timing_trg_found,\r
+ -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-)\r
+ IPU_NUMBER_OUT => ipu_number,\r
+ IPU_INFORMATION_OUT => ipu_information,\r
+ IPU_START_READOUT_OUT => ipu_start_readout,\r
+ IPU_DATA_IN => ipu_data,\r
+ IPU_DATAREADY_IN => ipu_dataready,\r
+ IPU_READOUT_FINISHED_IN => ipu_readout_finished,\r
+ IPU_READ_OUT => ipu_read,\r
+ IPU_LENGTH_IN => ipu_length,\r
+ IPU_ERROR_PATTERN_IN => ipu_error_pattern,\r
+ -- regIO bus\r
+ REGIO_ADDR_OUT => regio_addr,\r
+ REGIO_READ_ENABLE_OUT => regio_read_enable,\r
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable,\r
+ REGIO_DATA_OUT => regio_data_wr,\r
+ REGIO_DATA_IN => regio_data_rd,\r
+ REGIO_DATAREADY_IN => regio_dataready,\r
+ REGIO_NO_MORE_DATA_IN => regio_no_more_data,\r
+ REGIO_WRITE_ACK_IN => regio_write_ack,\r
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr,\r
+ REGIO_TIMEOUT_OUT => regio_timeout,\r
+ -- status LEDs\r
+ LED_LINK_STAT => fpga_led_link,\r
+ LED_LINK_TXD => fpga_led_txd,\r
+ LED_LINK_RXD => fpga_led_rxd,\r
+ LINK_BSM_OUT => lsm_state_bits, -- LinkStateMachine bits\r
+ RESET_OUT => reset_by_trb,\r
+ TICK_10S_OUT => tick_10s,\r
+ -- Debug\r
+ DEBUG => open --trbrich_debug \r
+);\r
+\r
+-- common control register bit definitions\r
+-- [31:24] ---\r
+-- [23:16] fake timing trigger\r
+-- [15] reboot FPGA\r
+-- [14:11] --- \r
+-- [10] reset sequence counter\r
+-- [9:4] ---\r
+-- [3] master reset, reset the whole endpoint\r
+-- [2] empty IPU chain, reset IPU logic\r
+-- [1] reset trigger logic\r
+-- [0] reset frontends\r
+\r
+-- LVL1 error pattern, to be sent back to CTS with each trigger\r
+lvl1_error_pattern(31 downto 24) <= (others => '0'); -- reserved\r
+lvl1_error_pattern(23) <= fe_error; -- frontend error\r
+lvl1_error_pattern(22) <= not_configured; -- not configured\r
+lvl1_error_pattern(21) <= '0'; -- buffers almost full\r
+lvl1_error_pattern(20) <= '0'; -- buffers half full\r
+lvl1_error_pattern(19 downto 18) <= (others => '0'); -- reserved\r
+lvl1_error_pattern(17) <= lvl1_trg_missing; -- missing timing trigger (done by Jan)\r
+lvl1_error_pattern(16) <= '0'; -- LVL1 tag mismatch with local counters (done by Jan)\r
+lvl1_error_pattern(15 downto 0) <= (others => '0'); -- reserved for common status bits\r
+\r
+\r
+----------------------------------------------\r
+-- mixed status and control bit definitions --\r
+----------------------------------------------\r
+\r
+-- Common status register \r
+-- CSR7: LVL1 handler statistics (2)\r
+common_stat_reg(255 downto 224) <= (others => '0');\r
+-- CSR6: LVL1 handler statistics (1)\r
+common_stat_reg(223 downto 192) <= (others => '0');\r
+-- CSR5: trigger data register\r
+common_stat_reg(191 downto 160) <= (others => '0');\r
+-- CSR4: link and reset status register\r
+common_stat_reg(159 downto 128) <= (others => '0');\r
+-- CSR3: LVL1 handler statistics (0)\r
+common_stat_reg(127 downto 96) <= (others => '0');\r
+common_stat_reg(127 downto 96) <= (others => '0');\r
+common_stat_reg(127 downto 96) <= (others => '0');\r
+-- CSR2: LVL1 handler status\r
+common_stat_reg(95 downto 91) <= (others => '0'); -- reserved\r
+common_stat_reg(90 downto 80) <= (others => '0'); -- delay between timing and LVL1 trigger\r
+common_stat_reg(79) <= '0'; -- found timing trigger\r
+common_stat_reg(78) <= '0'; -- LVL1 data valid\r
+common_stat_reg(77) <= '0'; -- multiple timing triggers found\r
+common_stat_reg(76) <= '0'; -- trigger number match\r
+common_stat_reg(75) <= '0'; -- timeout found\r
+common_stat_reg(74 downto 68) <= (others => '0'); -- reserved\r
+common_stat_reg(67 downto 64) <= (others => '0'); -- status of LVL1 handler state machine\r
+-- CSR1: LVL1 and IPU numbers\r
+common_stat_reg(63 downto 48) <= ipu_last_num(15 downto 0); -- LVL2 counter\r
+common_stat_reg(47 downto 32) <= local_lvl1_counter; -- LVL1 counter\r
+-- CSR0: basic error flags, temperature\r
+common_stat_reg(31 downto 20) <= x"000"; -- reserved for temp sensor\r
+common_stat_reg(19 downto 16) <= (others => '0'); -- reserved\r
+common_stat_reg(15) <= '0'; -- link error (code violation, NOT FOR SFPs!)\r
+common_stat_reg(14) <= '0'; -- single event upset detected (SEU logic)\r
+common_stat_reg(13) <= timing_trg_too_long; -- trigger line wrong polarity\r
+common_stat_reg(12) <= '0'; -- IPU: single broken event\r
+common_stat_reg(11) <= '0'; -- IPU: severe problem\r
+common_stat_reg(10) <= '0'; -- IPU: partially not found\r
+common_stat_reg(9) <= ipu_error_pattern(20); -- IPU: not found\r
+common_stat_reg(8) <= lvl1_trg_missing; -- LVL1: timing trigger missing\r
+common_stat_reg(7) <= fe_error; -- LVL1: frontend error\r
+common_stat_reg(6) <= not_configured; -- LVL1: not configured\r
+common_stat_reg(5) <= '0'; -- LVL2 counter mismatch (not implemented)\r
+common_stat_reg(4) <= '0'; -- LVL1 trigger counter mismatch (reserved)\r
+common_stat_reg(3) <= note_flag; -- note flag\r
+common_stat_reg(2) <= warning_flag; -- warning flag\r
+common_stat_reg(1) <= error_flag; -- error flag\r
+common_stat_reg(0) <= serious_error_flag; -- serious error flag \r
+\r
+serious_error_flag <= lvl1_trg_missing or fe_error or not_configured;\r
+error_flag <= ipu_error_pattern(20);\r
+warning_flag <= '0';\r
+note_flag <= '0';\r
+\r
+-- Control register bit padding\r
+ctrl_bithigh <= ctrl_lvl(31 downto 24) & x"0";\r
+ctrl_bitlow <= ctrl_lvl(23 downto 16) & x"0";\r
+ctrl_flathigh <= ctrl_lvl(15 downto 8) & x"0";\r
+ctrl_flatlow <= ctrl_lvl(7 downto 0) & x"0";\r
+\r
+-- LVDS driver enable\r
+ena_lvds(0) <= adc_on(4) or lvds_on(4); \r
+ena_lvds(1) <= adc_on(3) or lvds_on(3);\r
+ena_lvds(2) <= adc_on(5) or lvds_on(5);\r
+ena_lvds(3) <= adc_on(2) or lvds_on(2);\r
+ena_lvds(4) <= adc_on(6) or lvds_on(6);\r
+ena_lvds(5) <= adc_on(1) or lvds_on(1);\r
+ena_lvds(6) <= adc_on(7) or lvds_on(7);\r
+ena_lvds(7) <= adc_on(0) or lvds_on(0);\r
+ \r
+enb_lvds(0) <= adc_on(13) or lvds_on(13);\r
+enb_lvds(1) <= adc_on(10) or lvds_on(10);\r
+enb_lvds(2) <= adc_on(12) or lvds_on(12);\r
+enb_lvds(3) <= adc_on(11) or lvds_on(11);\r
+enb_lvds(4) <= adc_on(15) or lvds_on(15);\r
+enb_lvds(5) <= adc_on(8) or lvds_on(8);\r
+enb_lvds(6) <= adc_on(14) or lvds_on(14);\r
+enb_lvds(7) <= adc_on(9) or lvds_on(9);\r
+\r
+bp_led <= cts_clk40m_locked; -- LED is against GND!\r
+\r
+\r
+----------------------------------------\r
+-- internal slave bus -> slow control --\r
+----------------------------------------\r
+THE_SLAVE_BUS: slave_bus\r
+port map( \r
+ CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ -- RegIO signals\r
+ REGIO_ADDR_IN => regio_addr,\r
+ REGIO_DATA_IN => regio_data_wr,\r
+ REGIO_DATA_OUT => regio_data_rd,\r
+ REGIO_READ_ENABLE_IN => regio_read_enable,\r
+ REGIO_WRITE_ENABLE_IN => regio_write_enable,\r
+ REGIO_TIMEOUT_IN => regio_timeout,\r
+ REGIO_DATAREADY_OUT => regio_dataready,\r
+ REGIO_WRITE_ACK_OUT => regio_write_ack,\r
+ REGIO_NO_MORE_DATA_OUT => regio_no_more_data,\r
+ REGIO_UNKNOWN_ADDR_OUT => regio_unknown_addr,\r
+ -- I2C connections\r
+ SDA_IN => apv_sda_in,\r
+ SDA_OUT => apv_sda_out,\r
+ SCL_IN => apv_scl_in,\r
+ SCL_OUT => apv_scl_out,\r
+ -- 1Wire connections\r
+ ONEWIRE_START_IN => '0', -- not used yet\r
+ ONEWIRE_INOUT(15 downto 8) => apv1_1w(7 downto 0),\r
+ ONEWIRE_INOUT(7 downto 0) => apv0_1w(7 downto 0),\r
+ BP_ONEWIRE_INOUT => bp_onewire,\r
+ -- SPI connections\r
+ SPI_CS_OUT => u_spi_cs,\r
+ SPI_SCK_OUT => u_spi_sck,\r
+ SPI_SDI_IN => u_spi_sdo,\r
+ SPI_SDO_OUT => u_spi_sdi,\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC0_CS_OUT => adc0_cs,\r
+ SPI_ADC0_SCK_OUT => adc0_sck,\r
+ SPI_ADC0_SDO_OUT => adc0_sdi,\r
+ ADC0_PLL_LOCKED_IN => adc0_valid,\r
+ ADC0_PD_OUT => adc0_powerdown,\r
+ ADC0_RST_OUT => adc0_reset,\r
+ ADC0_DEL_OUT => adc0_iodelay,\r
+ ADC0_CLK_IN => clk_apv,\r
+ ADC0_DATA_IN => adc0_testdata,\r
+ ADC0_SEL_OUT => adc0_select,\r
+ APV0_RST_OUT => apv0_reset,\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC1_CS_OUT => adc1_cs,\r
+ SPI_ADC1_SCK_OUT => adc1_sck,\r
+ SPI_ADC1_SDO_OUT => adc1_sdi,\r
+ ADC1_PLL_LOCKED_IN => adc1_valid,\r
+ ADC1_PD_OUT => adc1_powerdown,\r
+ ADC1_RST_OUT => adc1_reset,\r
+ ADC1_DEL_OUT => adc1_iodelay,\r
+ ADC1_CLK_IN => clk_apv,\r
+ ADC1_DATA_IN => adc1_testdata,\r
+ ADC1_SEL_OUT => adc1_select,\r
+ APV1_RST_OUT => apv1_reset,\r
+ -- backplane identifier\r
+ BACKPLANE_IN => bp_module_qq(2 downto 0),\r
+ -- pedestal interface\r
+ PED_ADDR_IN => buf_addr,\r
+ PED_DATA_0_OUT => ped_data(0),\r
+ PED_DATA_1_OUT => ped_data(1),\r
+ PED_DATA_2_OUT => ped_data(2),\r
+ PED_DATA_3_OUT => ped_data(3),\r
+ PED_DATA_4_OUT => ped_data(4),\r
+ PED_DATA_5_OUT => ped_data(5),\r
+ PED_DATA_6_OUT => ped_data(6),\r
+ PED_DATA_7_OUT => ped_data(7),\r
+ PED_DATA_8_OUT => ped_data(8),\r
+ PED_DATA_9_OUT => ped_data(9),\r
+ PED_DATA_10_OUT => ped_data(10),\r
+ PED_DATA_11_OUT => ped_data(11),\r
+ PED_DATA_12_OUT => ped_data(12),\r
+ PED_DATA_13_OUT => ped_data(13),\r
+ PED_DATA_14_OUT => ped_data(14),\r
+ PED_DATA_15_OUT => ped_data(15),\r
+ -- threshold interface\r
+ THR_ADDR_IN => thr_addr,\r
+ THR_DATA_0_OUT => thr_data(0),\r
+ THR_DATA_1_OUT => thr_data(1),\r
+ THR_DATA_2_OUT => thr_data(2),\r
+ THR_DATA_3_OUT => thr_data(3),\r
+ THR_DATA_4_OUT => thr_data(4),\r
+ THR_DATA_5_OUT => thr_data(5),\r
+ THR_DATA_6_OUT => thr_data(6),\r
+ THR_DATA_7_OUT => thr_data(7),\r
+ THR_DATA_8_OUT => thr_data(8),\r
+ THR_DATA_9_OUT => thr_data(9),\r
+ THR_DATA_10_OUT => thr_data(10),\r
+ THR_DATA_11_OUT => thr_data(11),\r
+ THR_DATA_12_OUT => thr_data(12),\r
+ THR_DATA_13_OUT => thr_data(13),\r
+ THR_DATA_14_OUT => thr_data(14),\r
+ THR_DATA_15_OUT => thr_data(15),\r
+ -- APV control / status\r
+ CTRL_0_OUT => adc_ctrl_reg(0),\r
+ CTRL_1_OUT => adc_ctrl_reg(1),\r
+ CTRL_2_OUT => adc_ctrl_reg(2),\r
+ CTRL_3_OUT => adc_ctrl_reg(3),\r
+ CTRL_4_OUT => adc_ctrl_reg(4),\r
+ CTRL_5_OUT => adc_ctrl_reg(5),\r
+ CTRL_6_OUT => adc_ctrl_reg(6),\r
+ CTRL_7_OUT => adc_ctrl_reg(7),\r
+ CTRL_8_OUT => adc_ctrl_reg(8),\r
+ CTRL_9_OUT => adc_ctrl_reg(9),\r
+ CTRL_10_OUT => adc_ctrl_reg(10),\r
+ CTRL_11_OUT => adc_ctrl_reg(11),\r
+ CTRL_12_OUT => adc_ctrl_reg(12),\r
+ CTRL_13_OUT => adc_ctrl_reg(13),\r
+ CTRL_14_OUT => adc_ctrl_reg(14),\r
+ CTRL_15_OUT => adc_ctrl_reg(15),\r
+ STAT_0_IN => adc_stat_reg(0),\r
+ STAT_1_IN => adc_stat_reg(1),\r
+ STAT_2_IN => adc_stat_reg(2),\r
+ STAT_3_IN => adc_stat_reg(3),\r
+ STAT_4_IN => adc_stat_reg(4),\r
+ STAT_5_IN => adc_stat_reg(5),\r
+ STAT_6_IN => adc_stat_reg(6),\r
+ STAT_7_IN => adc_stat_reg(7),\r
+ STAT_8_IN => adc_stat_reg(8),\r
+ STAT_9_IN => adc_stat_reg(9),\r
+ STAT_10_IN => adc_stat_reg(10),\r
+ STAT_11_IN => adc_stat_reg(11),\r
+ STAT_12_IN => adc_stat_reg(12),\r
+ STAT_13_IN => adc_stat_reg(13),\r
+ STAT_14_IN => adc_stat_reg(14),\r
+ STAT_15_IN => adc_stat_reg(15),\r
+ -- FIFO status\r
+ FIFO_STATUS_0_IN => fifo_status(0),\r
+ FIFO_STATUS_1_IN => fifo_status(1),\r
+ FIFO_STATUS_2_IN => fifo_status(2),\r
+ FIFO_STATUS_3_IN => fifo_status(3),\r
+ FIFO_STATUS_4_IN => fifo_status(4),\r
+ FIFO_STATUS_5_IN => fifo_status(5),\r
+ FIFO_STATUS_6_IN => fifo_status(6),\r
+ FIFO_STATUS_7_IN => fifo_status(7),\r
+ FIFO_STATUS_8_IN => fifo_status(8),\r
+ FIFO_STATUS_9_IN => fifo_status(9),\r
+ FIFO_STATUS_10_IN => fifo_status(10),\r
+ FIFO_STATUS_11_IN => fifo_status(11),\r
+ FIFO_STATUS_12_IN => fifo_status(12),\r
+ FIFO_STATUS_13_IN => fifo_status(13),\r
+ FIFO_STATUS_14_IN => fifo_status(14),\r
+ FIFO_STATUS_15_IN => fifo_status(15),\r
+ IPU_STATUS_IN => ipu_handler_status,\r
+ RELEASE_STATUS_IN => lvl1_release_status,\r
+ -- some control signals\r
+ CTRL_LVL_OUT => ctrl_lvl,\r
+ CTRL_TRG_OUT => ctrl_trg,\r
+ CTRL_PLL_OUT => ctrl_pll,\r
+ STATUS_PLL_IN => status_pll,\r
+ -- temporary stuff \r
+ TEST_REG_IN => test_reg, -- short cut \r
+ TEST_REG_OUT => test_reg,\r
+ -- Debug \r
+ DEBUG_OUT => open, --slave_debug,\r
+ STAT => open\r
+); \r
+\r
+-- PLL status register \r
+status_pll(15) <= clk100m_locked;\r
+status_pll(14) <= clk40m_locked;\r
+status_pll(13) <= adc1_valid;\r
+status_pll(12) <= adc0_valid;\r
+status_pll(11) <= adc1_swap;\r
+status_pll(10) <= adc0_swap;\r
+status_pll(9) <= test_reg40m; --'0';\r
+status_pll(8) <= cts_clk40m_locked;\r
+status_pll(7) <= '0'; -- make it human readable\r
+status_pll(6 downto 4) <= bp_sector_qq(2 downto 0); -- given by backplane DIP switch, for readback only\r
+status_pll(3) <= '0'; -- make it human readable\r
+status_pll(2 downto 0) <= bp_module_qq(2 downto 0); -- given by backplane DIP switch, for readback only\r
+\r
+-- Common status register, do not use.\r
+-- 0x83\r
+--simple_status(127 downto 112) <= (others => '0');\r
+--simple_status(111 downto 96) <= trgctrl_debug(47 downto 32);\r
+simple_status(127 downto 96) <= trgctrl_debug(63 downto 32);\r
+-- 0x82\r
+simple_status(95 downto 64) <= trgctrl_debug(31 downto 0);\r
+-- 0x81\r
+simple_status(63 downto 32) <= (others => '0');\r
+-- 0x80\r
+simple_status(31 downto 16) <= local_lvl2_counter;\r
+simple_status(15 downto 0) <= local_lvl1_counter;\r
+\r
+-- all APVs are reset together, including the common FE reset\r
+THE_APV_PULSE_STRETCH: pulse_stretch\r
+port map(\r
+ CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ START_IN => common_ctrl_reg(0),\r
+ PULSE_OUT => frontend_reset,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+apv_reset <= apv0_reset or apv1_reset or frontend_reset;\r
+\r
+-- APV status registers\r
+-- "ADC on" bits\r
+-- "LVDS ON" bits \r
+GEN_ADC_LVDS_ON: for i in 0 to 15 generate\r
+ adc_on(i) <= adc_ctrl_reg(i)(0);\r
+ lvds_on(i) <= adc_ctrl_reg(i)(1);\r
+-- adc_stat_reg(i) <= raw_buf_dbg(i);\r
+ adc_stat_reg(i) <= buf_data(i)(37 downto 30) & raw_buf_debug(i*4+3 downto i*4+0) & std_logic_vector(to_unsigned(i,4));\r
+ broken_buf(i) <= buf_data(i)(36); -- BUF_BROKEN bit\r
+ apv_error(i) <= buf_data(i)(26); -- APV error frame bit\r
+end generate GEN_ADC_LVDS_ON;\r
+\r
+next_not_configured <= '1' when (broken_buf /= x"0000") else '0';\r
+next_fe_error <= '1' when (apv_error /= x"0000") else '0';\r
+\r
+----------------------------------------\r
+-- IPU endpoint for data transport --\r
+----------------------------------------\r
+THE_IPU_STAGE: ipu_fifo_stage \r
+port map( \r
+ CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ IPU_RESET_IN => common_ctrl_reg(2),\r
+ -- Slow control signals \r
+ SECTOR_IN => bp_sector_qq(2 downto 0), \r
+ MODULE_IN => bp_module_qq(2 downto 0), \r
+ -- IPU channel connections \r
+ IPU_NUMBER_IN => ipu_number,\r
+ IPU_INFORMATION_IN => ipu_information,\r
+ IPU_START_READOUT_IN => ipu_start_readout,\r
+ IPU_DATA_OUT => ipu_data,\r
+ IPU_DATAREADY_OUT => ipu_dataready,\r
+ IPU_READOUT_FINISHED_OUT => ipu_readout_finished,\r
+ IPU_READ_IN => ipu_read,\r
+ IPU_LENGTH_OUT => ipu_length,\r
+ IPU_ERROR_PATTERN_OUT => ipu_error_pattern,\r
+ IPU_LAST_NUM_OUT => ipu_last_num,\r
+ LVL2_COUNTER_OUT => local_lvl2_counter,\r
+ -- DHDR buffer input \r
+ DHDR_DATA_IN => dhdr_data,\r
+ DHDR_LENGTH_IN => dhdr_length,\r
+ DHDR_STORE_IN => dhdr_store,\r
+ DHDR_BUF_FULL_OUT => dhdr_buf_full,\r
+ -- processed data input\r
+ FIFO_SPACE_REQ_IN => fifo_space_req,\r
+ FIFO_START_IN => fifo_start,\r
+ FIFO_0_DATA_IN => fifo_data(0),\r
+ FIFO_1_DATA_IN => fifo_data(1),\r
+ FIFO_2_DATA_IN => fifo_data(2),\r
+ FIFO_3_DATA_IN => fifo_data(3),\r
+ FIFO_4_DATA_IN => fifo_data(4),\r
+ FIFO_5_DATA_IN => fifo_data(5),\r
+ FIFO_6_DATA_IN => fifo_data(6),\r
+ FIFO_7_DATA_IN => fifo_data(7),\r
+ FIFO_8_DATA_IN => fifo_data(8),\r
+ FIFO_9_DATA_IN => fifo_data(9),\r
+ FIFO_10_DATA_IN => fifo_data(10),\r
+ FIFO_11_DATA_IN => fifo_data(11),\r
+ FIFO_12_DATA_IN => fifo_data(12),\r
+ FIFO_13_DATA_IN => fifo_data(13),\r
+ FIFO_14_DATA_IN => fifo_data(14),\r
+ FIFO_15_DATA_IN => fifo_data(15),\r
+ FIFO_WE_IN => fifo_we,\r
+ FIFO_DONE_IN => fifo_done,\r
+ FIFO_0_STATUS_OUT => fifo_status(0),\r
+ FIFO_1_STATUS_OUT => fifo_status(1),\r
+ FIFO_2_STATUS_OUT => fifo_status(2),\r
+ FIFO_3_STATUS_OUT => fifo_status(3),\r
+ FIFO_4_STATUS_OUT => fifo_status(4),\r
+ FIFO_5_STATUS_OUT => fifo_status(5),\r
+ FIFO_6_STATUS_OUT => fifo_status(6),\r
+ FIFO_7_STATUS_OUT => fifo_status(7),\r
+ FIFO_8_STATUS_OUT => fifo_status(8),\r
+ FIFO_9_STATUS_OUT => fifo_status(9),\r
+ FIFO_10_STATUS_OUT => fifo_status(10),\r
+ FIFO_11_STATUS_OUT => fifo_status(11),\r
+ FIFO_12_STATUS_OUT => fifo_status(12),\r
+ FIFO_13_STATUS_OUT => fifo_status(13),\r
+ FIFO_14_STATUS_OUT => fifo_status(14),\r
+ FIFO_15_STATUS_OUT => fifo_status(15),\r
+ IPU_STATUS_OUT => ipu_handler_status,\r
+ RELEASE_STATUS_OUT => lvl1_release_status,\r
+ -- Debug signals\r
+ DBG_BSM_OUT => open,\r
+ DBG_OUT => open --fifo_debug\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- Data processing unit --\r
+----------------------------------------\r
+THE_PED_CORR_STAGE: ped_corr_ctrl\r
+port map( \r
+ CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ VERBOSE_IN => common_ctrl_reg(94), -- CCR2-30\r
+ EDS_DATA_IN => eds_data,\r
+ EDS_AVAIL_IN => eds_avail,\r
+ EDS_DONE_OUT => eds_done,\r
+ -- DHDR information -- to next stage\r
+ DHDR_DATA_OUT => dhdr_data,\r
+ DHDR_LENGTH_OUT => dhdr_length,\r
+ DHDR_STORE_OUT => dhdr_store,\r
+ DHDR_BUF_FULL_IN => dhdr_buf_full,\r
+ FIFO_SPACE_REQ_OUT => fifo_space_req, \r
+ -- data buffers -- from raw_buf_stage\r
+ BUF_ADDR_OUT => buf_addr,\r
+ BUF_DONE_OUT => buf_done,\r
+ BUF_TICK_IN => buf_tick,\r
+ BUF_START_IN => buf_start,\r
+ -- raw data\r
+ BUF_0_DATA_IN => buf_data(0),\r
+ BUF_1_DATA_IN => buf_data(1),\r
+ BUF_2_DATA_IN => buf_data(2),\r
+ BUF_3_DATA_IN => buf_data(3),\r
+ BUF_4_DATA_IN => buf_data(4),\r
+ BUF_5_DATA_IN => buf_data(5),\r
+ BUF_6_DATA_IN => buf_data(6),\r
+ BUF_7_DATA_IN => buf_data(7),\r
+ BUF_8_DATA_IN => buf_data(8),\r
+ BUF_9_DATA_IN => buf_data(9),\r
+ BUF_10_DATA_IN => buf_data(10),\r
+ BUF_11_DATA_IN => buf_data(11),\r
+ BUF_12_DATA_IN => buf_data(12),\r
+ BUF_13_DATA_IN => buf_data(13),\r
+ BUF_14_DATA_IN => buf_data(14),\r
+ BUF_15_DATA_IN => buf_data(15),\r
+ -- Pedestal data \r
+ PED_ADDR_OUT => open, -- BUGBUGBUG\r
+ PED_0_DATA_IN => ped_data(0),\r
+ PED_1_DATA_IN => ped_data(1),\r
+ PED_2_DATA_IN => ped_data(2),\r
+ PED_3_DATA_IN => ped_data(3),\r
+ PED_4_DATA_IN => ped_data(4),\r
+ PED_5_DATA_IN => ped_data(5),\r
+ PED_6_DATA_IN => ped_data(6),\r
+ PED_7_DATA_IN => ped_data(7),\r
+ PED_8_DATA_IN => ped_data(8),\r
+ PED_9_DATA_IN => ped_data(9),\r
+ PED_10_DATA_IN => ped_data(10),\r
+ PED_11_DATA_IN => ped_data(11),\r
+ PED_12_DATA_IN => ped_data(12),\r
+ PED_13_DATA_IN => ped_data(13),\r
+ PED_14_DATA_IN => ped_data(14),\r
+ PED_15_DATA_IN => ped_data(15),\r
+ -- Threshold data\r
+ THR_ADDR_OUT => thr_addr,\r
+ THR_0_DATA_IN => thr_data(0),\r
+ THR_1_DATA_IN => thr_data(1),\r
+ THR_2_DATA_IN => thr_data(2),\r
+ THR_3_DATA_IN => thr_data(3),\r
+ THR_4_DATA_IN => thr_data(4),\r
+ THR_5_DATA_IN => thr_data(5),\r
+ THR_6_DATA_IN => thr_data(6),\r
+ THR_7_DATA_IN => thr_data(7),\r
+ THR_8_DATA_IN => thr_data(8),\r
+ THR_9_DATA_IN => thr_data(9),\r
+ THR_10_DATA_IN => thr_data(10),\r
+ THR_11_DATA_IN => thr_data(11),\r
+ THR_12_DATA_IN => thr_data(12),\r
+ THR_13_DATA_IN => thr_data(13),\r
+ THR_14_DATA_IN => thr_data(14),\r
+ THR_15_DATA_IN => thr_data(15),\r
+ -- processed data\r
+ FIFO_START_OUT => fifo_start,\r
+ FIFO_0_DATA_OUT => fifo_data(0),\r
+ FIFO_1_DATA_OUT => fifo_data(1),\r
+ FIFO_2_DATA_OUT => fifo_data(2),\r
+ FIFO_3_DATA_OUT => fifo_data(3),\r
+ FIFO_4_DATA_OUT => fifo_data(4),\r
+ FIFO_5_DATA_OUT => fifo_data(5),\r
+ FIFO_6_DATA_OUT => fifo_data(6),\r
+ FIFO_7_DATA_OUT => fifo_data(7),\r
+ FIFO_8_DATA_OUT => fifo_data(8),\r
+ FIFO_9_DATA_OUT => fifo_data(9),\r
+ FIFO_10_DATA_OUT => fifo_data(10),\r
+ FIFO_11_DATA_OUT => fifo_data(11),\r
+ FIFO_12_DATA_OUT => fifo_data(12),\r
+ FIFO_13_DATA_OUT => fifo_data(13),\r
+ FIFO_14_DATA_OUT => fifo_data(14),\r
+ FIFO_15_DATA_OUT => fifo_data(15),\r
+ FIFO_WE_OUT => fifo_we,\r
+ FIFO_DONE_OUT => fifo_done,\r
+ -- Debug signals\r
+ DBG_BSM_OUT => open,\r
+ DBG_OUT => open\r
+);\r
+\r
+\r
+------------------------------------------\r
+-- Raw data processing and storage unit --\r
+------------------------------------------\r
+THE_RAW_BUF_STAGE: raw_buf_stage\r
+port map( \r
+ CLK_IN => sysclk,\r
+ CLK_APV_IN => clk_apv,\r
+ RESET_IN => reset_by_trb,\r
+ -- trigger related signals\r
+ APV_RESET_IN => apv_reset, -- (100MHz clock)\r
+ APV_SYNC_IN => apv_sync, -- (40MHz APV clock)\r
+ APV_FRAME_REQD_IN => apv_frame_reqd, -- (100MHz clock)\r
+ -- ADC0 signals\r
+ ADC0_VALID_IN => adc0_valid,\r
+ ADC0_0_DATA_IN => adc_data(0),\r
+ ADC0_1_DATA_IN => adc_data(1),\r
+ ADC0_2_DATA_IN => adc_data(2),\r
+ ADC0_3_DATA_IN => adc_data(3),\r
+ ADC0_4_DATA_IN => adc_data(4),\r
+ ADC0_5_DATA_IN => adc_data(5),\r
+ ADC0_6_DATA_IN => adc_data(6),\r
+ ADC0_7_DATA_IN => adc_data(7),\r
+ -- ADC1 signals\r
+ ADC1_VALID_IN => adc1_valid,\r
+ ADC1_0_DATA_IN => adc_data(8),\r
+ ADC1_1_DATA_IN => adc_data(9),\r
+ ADC1_2_DATA_IN => adc_data(10),\r
+ ADC1_3_DATA_IN => adc_data(11),\r
+ ADC1_4_DATA_IN => adc_data(12),\r
+ ADC1_5_DATA_IN => adc_data(13),\r
+ ADC1_6_DATA_IN => adc_data(14),\r
+ ADC1_7_DATA_IN => adc_data(15),\r
+ -- Slow control registers\r
+ MAX_TRG_NUM_IN => maximum_trg, -- automatically determined\r
+ BIT_LOW_IN => ctrl_bitlow, -- from slow control\r
+ BIT_HIGH_IN => ctrl_bithigh, -- from slow control\r
+ FL_LOW_IN => ctrl_flatlow, -- from slow control\r
+ FL_HIGH_IN => ctrl_flathigh, -- from slow control\r
+ APV_ON_IN => adc_on,\r
+ -- 100MHZ synchronous interface\r
+ -- APV raw buffers\r
+ BUF_FULL_OUT => raw_buf_full, -- NEW NEW NEW\r
+ BUF_ADDR_IN => buf_addr, -- from ped_corr_ctrl\r
+ BUF_DONE_IN => buf_done, -- from ped_corr_ctrl\r
+ BUF_TICK_OUT => buf_tick,\r
+ BUF_START_OUT => buf_start,\r
+ BUF_READY_OUT => buf_ready,\r
+ BUF_0_DATA_OUT => buf_data(0), -- to ped_corr_ctrl \r
+ BUF_1_DATA_OUT => buf_data(1), -- to ped_corr_ctrl\r
+ BUF_2_DATA_OUT => buf_data(2), -- to ped_corr_ctrl\r
+ BUF_3_DATA_OUT => buf_data(3), -- to ped_corr_ctrl\r
+ BUF_4_DATA_OUT => buf_data(4), -- to ped_corr_ctrl\r
+ BUF_5_DATA_OUT => buf_data(5), -- to ped_corr_ctrl\r
+ BUF_6_DATA_OUT => buf_data(6), -- to ped_corr_ctrl\r
+ BUF_7_DATA_OUT => buf_data(7), -- to ped_corr_ctrl\r
+ BUF_8_DATA_OUT => buf_data(8), -- to ped_corr_ctrl\r
+ BUF_9_DATA_OUT => buf_data(9), -- to ped_corr_ctrl\r
+ BUF_10_DATA_OUT => buf_data(10), -- to ped_corr_ctrl\r
+ BUF_11_DATA_OUT => buf_data(11), -- to ped_corr_ctrl\r
+ BUF_12_DATA_OUT => buf_data(12), -- to ped_corr_ctrl\r
+ BUF_13_DATA_OUT => buf_data(13), -- to ped_corr_ctrl\r
+ BUF_14_DATA_OUT => buf_data(14), -- to ped_corr_ctrl\r
+ BUF_15_DATA_OUT => buf_data(15), -- to ped_corr_ctrl\r
+ -- Debug signals SPECIAL\r
+ DBG_0_OUT => raw_buf_dbg(0),\r
+ DBG_1_OUT => raw_buf_dbg(1),\r
+ DBG_2_OUT => raw_buf_dbg(2),\r
+ DBG_3_OUT => raw_buf_dbg(3),\r
+ DBG_4_OUT => raw_buf_dbg(4),\r
+ DBG_5_OUT => raw_buf_dbg(5),\r
+ DBG_6_OUT => raw_buf_dbg(6),\r
+ DBG_7_OUT => raw_buf_dbg(7),\r
+ DBG_8_OUT => raw_buf_dbg(8),\r
+ DBG_9_OUT => raw_buf_dbg(9),\r
+ DBG_10_OUT => raw_buf_dbg(10),\r
+ DBG_11_OUT => raw_buf_dbg(11),\r
+ DBG_12_OUT => raw_buf_dbg(12),\r
+ DBG_13_OUT => raw_buf_dbg(13),\r
+ DBG_14_OUT => raw_buf_dbg(14),\r
+ DBG_15_OUT => raw_buf_dbg(15),\r
+ -- Debug signals\r
+ DEBUG_OUT => raw_buf_debug --open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- ADC1 data handler --\r
+----------------------------------------\r
+THE_ADC1_HANDLER: adc_data_handler \r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ ADC_LCLK_IN => adc1_lclk,\r
+ ADC_ADCLK_IN => adc1_adclk,\r
+ ADC_CHNL_IN => adc1_out,\r
+ PLL_CTRL_IN => adc1_iodelay,\r
+ ADC_DATA7_OUT => adc_raw_data(15),\r
+ ADC_DATA6_OUT => adc_raw_data(14),\r
+ ADC_DATA5_OUT => adc_raw_data(13),\r
+ ADC_DATA4_OUT => adc_raw_data(12),\r
+ ADC_DATA3_OUT => adc_raw_data(11),\r
+ ADC_DATA2_OUT => adc_raw_data(10),\r
+ ADC_DATA1_OUT => adc_raw_data(9),\r
+ ADC_DATA0_OUT => adc_raw_data(8),\r
+ ADC_CE_OUT => adc1_ce,\r
+ ADC_VALID_OUT => adc1_valid,\r
+ ADC_SWAP_OUT => adc1_swap,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- ADC1 clock domain crossover --\r
+----------------------------------------\r
+THE_ADC1_CROSSOVER: adc_crossover\r
+port map( \r
+ CLK_APV_IN => clk_apv,\r
+ RESET_IN => global_sync_reset,\r
+ -- ADC clock domain signals\r
+ ADC_CLK_IN => adc1_lclk,\r
+ ADC_CE_IN => adc1_ce,\r
+ ADC_DATA_VALID_IN => adc1_valid,\r
+ ADC_DATA_7_IN => adc_raw_data(15),\r
+ ADC_DATA_6_IN => adc_raw_data(14),\r
+ ADC_DATA_5_IN => adc_raw_data(13),\r
+ ADC_DATA_4_IN => adc_raw_data(12),\r
+ ADC_DATA_3_IN => adc_raw_data(11),\r
+ ADC_DATA_2_IN => adc_raw_data(10),\r
+ ADC_DATA_1_IN => adc_raw_data(9),\r
+ ADC_DATA_0_IN => adc_raw_data(8),\r
+ LEVEL_WR_OUT => open,\r
+ -- APV clock domain signals\r
+ APV_DATA_7_OUT => adc_data(15),\r
+ APV_DATA_6_OUT => adc_data(14),\r
+ APV_DATA_5_OUT => adc_data(13),\r
+ APV_DATA_4_OUT => adc_data(12),\r
+ APV_DATA_3_OUT => adc_data(11),\r
+ APV_DATA_2_OUT => adc_data(10),\r
+ APV_DATA_1_OUT => adc_data(9),\r
+ APV_DATA_0_OUT => adc_data(8),\r
+ APV_DATA_VALID_OUT => open,\r
+ LEVEL_RD_OUT => open,\r
+ -- Debug signals\r
+ DEBUG_OUT => open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- ADC1 test data multiplexer --\r
+----------------------------------------\r
+THE_ADC_1_SELECT: adc_channel_select\r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ ADC_CLK_IN => clk_apv,\r
+ ADC_SEL_IN => adc1_select,\r
+ ADC_7_IN => adc_data(15),\r
+ ADC_6_IN => adc_data(14),\r
+ ADC_5_IN => adc_data(13),\r
+ ADC_4_IN => adc_data(12),\r
+ ADC_3_IN => adc_data(11),\r
+ ADC_2_IN => adc_data(10),\r
+ ADC_1_IN => adc_data(9),\r
+ ADC_0_IN => adc_data(8),\r
+ ADC_CH_OUT => adc1_testdata,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- ADC0 data handler --\r
+----------------------------------------\r
+THE_ADC0_HANDLER: adc_data_handler \r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ ADC_LCLK_IN => adc0_lclk,\r
+ ADC_ADCLK_IN => adc0_adclk,\r
+ ADC_CHNL_IN => adc0_out,\r
+ PLL_CTRL_IN => adc0_iodelay,\r
+ ADC_DATA7_OUT => adc_raw_data(7),\r
+ ADC_DATA6_OUT => adc_raw_data(6),\r
+ ADC_DATA5_OUT => adc_raw_data(5),\r
+ ADC_DATA4_OUT => adc_raw_data(4),\r
+ ADC_DATA3_OUT => adc_raw_data(3),\r
+ ADC_DATA2_OUT => adc_raw_data(2),\r
+ ADC_DATA1_OUT => adc_raw_data(1),\r
+ ADC_DATA0_OUT => adc_raw_data(0),\r
+ ADC_CE_OUT => adc0_ce,\r
+ ADC_VALID_OUT => adc0_valid,\r
+ ADC_SWAP_OUT => adc0_swap,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- ADC0 clock domain crossover --\r
+----------------------------------------\r
+THE_ADC0_CROSSOVER: adc_crossover\r
+port map( \r
+ CLK_APV_IN => clk_apv,\r
+ RESET_IN => global_sync_reset,\r
+ -- ADC clock domain signals\r
+ ADC_CLK_IN => adc0_lclk,\r
+ ADC_CE_IN => adc0_ce,\r
+ ADC_DATA_VALID_IN => adc0_valid,\r
+ ADC_DATA_7_IN => adc_raw_data(7),\r
+ ADC_DATA_6_IN => adc_raw_data(6),\r
+ ADC_DATA_5_IN => adc_raw_data(5),\r
+ ADC_DATA_4_IN => adc_raw_data(4),\r
+ ADC_DATA_3_IN => adc_raw_data(3),\r
+ ADC_DATA_2_IN => adc_raw_data(2),\r
+ ADC_DATA_1_IN => adc_raw_data(1),\r
+ ADC_DATA_0_IN => adc_raw_data(0),\r
+ LEVEL_WR_OUT => open,\r
+ -- APV clock domain signals\r
+ APV_DATA_7_OUT => adc_data(7),\r
+ APV_DATA_6_OUT => adc_data(6),\r
+ APV_DATA_5_OUT => adc_data(5),\r
+ APV_DATA_4_OUT => adc_data(4),\r
+ APV_DATA_3_OUT => adc_data(3),\r
+ APV_DATA_2_OUT => adc_data(2),\r
+ APV_DATA_1_OUT => adc_data(1),\r
+ APV_DATA_0_OUT => adc_data(0),\r
+ APV_DATA_VALID_OUT => open,\r
+ LEVEL_RD_OUT => open,\r
+ -- Debug signals\r
+ DEBUG_OUT => open\r
+);\r
+\r
+ \r
+----------------------------------------\r
+-- ADC0 test data multiplexer --\r
+----------------------------------------\r
+THE_ADC_0_SELECT: adc_channel_select\r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ ADC_CLK_IN => clk_apv,\r
+ ADC_SEL_IN => adc0_select,\r
+ ADC_7_IN => adc_data(7),\r
+ ADC_6_IN => adc_data(6),\r
+ ADC_5_IN => adc_data(5),\r
+ ADC_4_IN => adc_data(4),\r
+ ADC_3_IN => adc_data(3),\r
+ ADC_2_IN => adc_data(2),\r
+ ADC_1_IN => adc_data(1),\r
+ ADC_0_IN => adc_data(0),\r
+ ADC_CH_OUT => adc0_testdata,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- Trigger handler (APV specific) --\r
+----------------------------------------\r
+THE_APV_TRGCTRL: apv_trgctrl\r
+port map( \r
+ CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ CLK_APV_IN => clk_apv,\r
+ -- Triggers\r
+ SYNC_TRG_IN => common_ctrl_reg(31), -- slow control pulse\r
+ TIME_TRG_IN => ext_in, -- external trigger inputs\r
+ TRB_TRG_IN => common_ctrl_reg(19 downto 16), -- slow control triggers\r
+ STILL_BUSY_IN => raw_buf_full, -- if no more frames are free in first stage buffer we must cease triggers.\r
+ TRG_FOUND_OUT => timing_trg_found, -- to TRB LVL1 endpoint\r
+ TRG_TOO_LONG_OUT => timing_trg_too_long, -- only for TRG0 channel\r
+ SECTOR_IN => bp_sector_qq(2 downto 0), \r
+ -- slow control settings\r
+ TRG_MAX_OUT => maximum_trg,\r
+ TRG_3_TODO_IN => ctrl_trg(31 downto 28), -- from slow control\r
+ TRG_3_DELAY_IN => ctrl_trg(27 downto 24), -- from slow control\r
+ TRG_2_TODO_IN => ctrl_trg(23 downto 20), -- from slow control\r
+ TRG_2_DELAY_IN => ctrl_trg(19 downto 16), -- from slow control\r
+ TRG_1_TODO_IN => ctrl_trg(15 downto 12), -- from slow control\r
+ TRG_1_DELAY_IN => ctrl_trg(11 downto 8), -- from slow control\r
+ TRG_0_TODO_IN => ctrl_trg(7 downto 4), -- from slow control\r
+ TRG_0_DELAY_IN => ctrl_trg(3 downto 0), -- from slow control\r
+ TRG_SETUP_IN => ctrl_pll(15 downto 8), -- from slow control\r
+ -- TRB LVL1 signals\r
+ TRB_TTAG_IN => lvl1_trg_number, -- from TRB LVL1 endpoint\r
+ TRB_TRND_IN => lvl1_trg_code, -- from TRB LVL1 endpoint\r
+ TRB_TTYPE_IN => lvl1_trg_type, -- from TRB LVL1 endpoint\r
+ TRB_TINFO_IN => lvl1_trg_information, -- from TRB LVL1 endpoint\r
+ TRB_TRGRCVD_IN => lvl1_trg_received, -- from TRB LVL1 endpoint\r
+ TRB_MISSING_OUT => lvl1_trg_missing, -- missing timing trigger\r
+ TRB_RELEASE_OUT => lvl1_trg_release, -- to TRB LVL1 endpoint\r
+ TRB_COUNTER_OUT => local_lvl1_counter, -- own trigger counter\r
+ TRB_COUNTER_IN => lvl1_int_trg_number, -- official TRB trigger counter\r
+ TRB_LD_COUNTER_IN => lvl1_int_trg_update, -- load TRB counter value\r
+ -- EDS signals\r
+ EDS_DATA_OUT => eds_data, -- to ped_corr_stage\r
+ EDS_AVAIL_OUT => eds_avail, -- to ped_corr_stage\r
+ EDS_DONE_IN => eds_done, -- from ped_corr_stage\r
+ EDS_FULL_OUT => eds_buf_full,\r
+ EDS_LEVEL_OUT => eds_buf_level,\r
+ FRM_REQD_OUT => apv_frame_reqd, -- to raw_buf_stage (100MHz clock)\r
+ -- APV signals \r
+ APV_TRG_OUT => apv_trg, -- to APV frontends (40MHz APV clock)\r
+ APV_SYNC_OUT => apv_sync, -- to raw_buf_stage (40MHz APV clock)\r
+ DEBUG_OUT => trgctrl_debug\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- ADC signals --\r
+----------------------------------------\r
+adc1_rst <= adc1_reset;\r
+adc1_pd <= adc1_powerdown;\r
+\r
+THE_ADC1CLK_OUT: ODDRXC\r
+port map( \r
+ DA => '1',\r
+ DB => '0',\r
+ CLK => clk_adc,\r
+ RST => '0',\r
+ Q => adc1_clk\r
+);\r
+\r
+adc0_rst <= adc0_reset;\r
+adc0_pd <= adc0_powerdown;\r
+\r
+THE_ADC0CLK_OUT: ODDRXC\r
+port map( \r
+ DA => '1',\r
+ DB => '0',\r
+ CLK => clk_adc,\r
+ RST => '0',\r
+ Q => adc0_clk\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- APV signals --\r
+----------------------------------------\r
+-- SDA line output\r
+apv0_sda <= '0' when (apv_sda_out = '0') else 'Z';\r
+apv1_sda <= '0' when (apv_sda_out = '0') else 'Z';\r
+-- SDA line input (wired OR negative logic)\r
+apv_sda_in <= apv0_sda and apv1_sda;\r
+\r
+-- SCL line output\r
+apv0_scl <= '0' when (apv_scl_out = '0') else 'Z';\r
+apv1_scl <= '0' when (apv_scl_out = '0') else 'Z';\r
+-- SCL line input (wired OR negative logic)\r
+apv_scl_in <= apv0_scl and apv1_scl;\r
+\r
+-- Reset signal with correct polarity\r
+apv0_rst <= not apv_reset;\r
+apv1_rst <= not apv_reset;\r
+\r
+-- CLK and TRG signal\r
+-- CLK is shifted to meet timing constraints of APV\r
+THE_APV0ACLK_OUT: ODDRXC\r
+port map( \r
+ DA => '0', \r
+ DB => '1', \r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0a_clk\r
+);\r
+\r
+THE_APV0BCLK_OUT: ODDRXC\r
+port map( \r
+ DA => '0',\r
+ DB => '1',\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0b_clk\r
+);\r
+\r
+THE_APV1ACLK_OUT: ODDRXC\r
+port map( \r
+ DA => '0',\r
+ DB => '1',\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1a_clk\r
+);\r
+\r
+THE_APV1BCLK_OUT: ODDRXC\r
+port map( \r
+ DA => '0',\r
+ DB => '1',\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1b_clk\r
+);\r
+\r
+THE_APV0ATRG_OUT: ODDRXC\r
+port map( \r
+ DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0a_trg\r
+);\r
+THE_APV0BTRG_OUT: ODDRXC\r
+port map( \r
+ DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0b_trg\r
+);\r
+THE_APV1ATRG_OUT: ODDRXC\r
+port map( \r
+ DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1a_trg\r
+);\r
+THE_APV1BTRG_OUT: ODDRXC\r
+port map( \r
+ DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1b_trg\r
+);\r
+\r
+\r
+----------------------------------------\r
+-- DIP switch input registers --\r
+----------------------------------------\r
+-- switch "OFF" => '1', switch "ON" => '0'; so invert it\r
+THE_SYNC_PROC: process( sysclk )\r
+begin\r
+ if( rising_edge(sysclk) ) then\r
+ bp_module_qq <= bp_module_q;\r
+ bp_module_q <= not bp_module;\r
+ bp_sector_qq <= bp_sector_q;\r
+ bp_sector_q <= not bp_sector;\r
+ not_configured <= next_not_configured; -- status bit\r
+ fe_error <= next_fe_error; -- status bit\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+\r
+----------------------------------------\r
+-- LED drivers --\r
+----------------------------------------\r
+fpga_led_adc(1) <= not adc1_valid; \r
+fpga_led_adc(0) <= not adc0_valid;\r
+fpga_led(6) <= not lsm_state_bits(0); -- LED "0"\r
+fpga_led(5) <= not lsm_state_bits(1); -- LED "1"\r
+fpga_led(4) <= not lsm_state_bits(2); -- LED "2"\r
+fpga_led(3) <= not lsm_state_bits(3); -- LED "3"\r
+fpga_led_pll <= not clk40m_locked;\r
+\r
+\r
+----------------------------------------\r
+-- FPGA debug header driver --\r
+----------------------------------------\r
+\r
+-- NOT USED, USE EPIC EDITOR INSTEAD!\r
+\r
+------------------------------------------------------------------\r
+-- ORIGINAL STUFF\r
+------------------------------------------------------------------\r
+--debug(42 downto 39) <= (others => '0'); \r
+---- IPU signals\r
+--debug(38 downto 35) <= ipu_number(3 downto 0);\r
+--debug(34) <= ipu_start_readout;\r
+--debug(33) <= ipu_dataready;\r
+--debug(32) <= ipu_read;\r
+--debug(31) <= ipu_readout_finished;\r
+---- FIFO signals\r
+--debug(30) <= fifo_start; -- ped_corr_ctrl -> ipu_stage => data procession starts (unused in ipu_stage)\r
+--debug(29) <= fifo_we(0); -- ped_corr_ctrl -> ipu_stage => transfer processed data into data FIFO (0)\r
+--debug(28) <= fifo_done; -- ped_corr_ctrl -> ipu_stage => store length count data in small FIFOs\r
+--debug(27) <= dhdr_store; -- ped_corr_ctrl -> ipu_stage => store DHDR information for IPU\r
+--debug(26) <= dhdr_buf_full; -- ipu_stage ->\r
+---- EventDataSheet / buffer signals\r
+--debug(25) <= buf_done; -- ped_corr_ctrl -> raw_buf_stage => raw data has been processed\r
+--debug(24) <= buf_tick(0); -- raw_buf_stage -> ped_corr_ctrl => synced tickmarks\r
+--debug(23) <= buf_ready(0); -- raw_buf_stage => adc_last\r
+--debug(22) <= buf_start(0); -- raw_buf_stage -> ped_corr_ctrl => adc_start\r
+--debug(21 downto 17) <= buf_data(0)(34 downto 30);\r
+--debug(16) <= raw_buf_full; -- raw_buf_stage -> apv_trgctrl => at least one raw buffer is full\r
+--debug(15) <= eds_done; -- ped_corr_ctrl -> apv_trgctrl => EDS data has been transfered, release buffer entry\r
+--debug(14) <= eds_avail; -- apv_trgctrl -> ped_corr_ctrl => at least one EDS is available\r
+--debug(13) <= eds_buf_full; -- apv_trgctrl => EDS buffer is full\r
+--debug(12 downto 8) <= eds_buf_level; \r
+---- timing trigger signals\r
+--debug(7) <= timing_trg_found; -- apv_trgctrl -> endpoint => timing trigger has arrived\r
+--debug(6) <= lvl1_trg_received; -- endpoint -> apv_trgctrl => LVL1 trigger packet has arrived\r
+--debug(5) <= lvl1_trg_missing; -- apv_trgctrl -> endpoint => two consecutive timing triggers found\r
+--debug(4) <= lvl1_trg_release; -- apv_trgctrl -> endpoint => release LVL1 busy \r
+--debug(3 downto 0) <= lvl1_trg_number(3 downto 0);\r
+\r
+\r
+----------------------------------------\r
+-- "unused" pins --\r
+----------------------------------------\r
+\r
+end adcmv3;\r
library ieee;\r
use ieee.std_logic_1164.all;\r
use IEEE.numeric_std.ALL;\r
-use IEEE.std_logic_UNSIGNED.ALL;\r
+--use IEEE.numeric_std.ALL;\r
+--use IEEE.std_logic_UNSIGNED.ALL;\r
\r
---library work;\r
---use work.trb_net_std.all;\r
\r
package adcmv3_components is\r
\r
-component raw_buf_stage_new is\r
+component dbg_reg is\r
+generic(\r
+ WIDTH : integer := 1\r
+);\r
+port(\r
+ DEBUG_IN : in std_logic_vector(WIDTH-1 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(WIDTH-1 downto 0)\r
+);\r
+end component dbg_reg;\r
+\r
+component reset_handler is\r
+generic(\r
+ RESET_DELAY : std_logic_vector(15 downto 0) := x"1fff"\r
+);\r
+port( \r
+ CLEAR_IN : in std_logic; -- reset input (high active, async)\r
+ CLEAR_N_IN : in std_logic; -- reset input (low active, async)\r
+ CLK_IN : in std_logic; -- raw master clock, NOT from PLL/DLL!\r
+ SYSCLK_IN : in std_logic; -- PLL/DLL remastered clock\r
+ PLL_LOCKED_IN : in std_logic; -- master PLL lock signal (async)\r
+ RESET_IN : in std_logic; -- general reset signal (SYSCLK)\r
+ TRB_RESET_IN : in std_logic; -- TRBnet reset signal (SYSCLK)\r
+ CLEAR_OUT : out std_logic; -- async reset out, USE WITH CARE!\r
+ RESET_OUT : out std_logic; -- synchronous reset out (SYSCLK)\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component reset_handler;\r
+\r
+component sync_pll_40m is\r
+port(\r
+ CLK : in std_logic; \r
+ RESET : in std_logic; \r
+ CLKOP : out std_logic; \r
+ LOCK : out std_logic\r
+);\r
+end component sync_pll_40m;\r
+\r
+component raw_buf_stage is\r
port(\r
CLK_IN : in std_logic; -- 100MHz local clock\r
CLK_APV_IN : in std_logic; -- 40MHz APV clock\r
BUF_13_DATA_OUT : out std_logic_vector(37 downto 0);\r
BUF_14_DATA_OUT : out std_logic_vector(37 downto 0);\r
BUF_15_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ -- DEBUG SPECIAL\r
+ DBG_0_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_1_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_2_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_3_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_4_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_5_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_6_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_7_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_8_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_9_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_10_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_11_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_12_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_13_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_14_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_15_OUT : out std_logic_vector(15 downto 0);\r
-- Debug signals\r
DEBUG_OUT : out std_logic_vector(63 downto 0)\r
);\r
-end component raw_buf_stage_new;\r
+end component raw_buf_stage;\r
\r
-component adc_data_handler_new is\r
+component adc_data_handler is\r
port(\r
- RESET_IN : in std_logic;\r
- ADC_LCLK_IN : in std_logic; -- LCLK from ADC\r
- ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC\r
- ADC_CHNL_IN : in std_logic_vector(7 downto 0);\r
- PLL_CTRL_IN : in std_logic_vector(3 downto 0);\r
- ADC_DATA7_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA6_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA5_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA4_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA3_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA2_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA1_OUT : out std_logic_vector(11 downto 0);\r
- ADC_DATA0_OUT : out std_logic_vector(11 downto 0);\r
- ADC_CE_OUT : out std_logic;\r
- ADC_VALID_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
-);\r
-end component adc_data_handler_new;\r
+ RESET_IN : in std_logic;\r
+ ADC_LCLK_IN : in std_logic; -- LCLK from ADC\r
+ ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC\r
+ ADC_CHNL_IN : in std_logic_vector(7 downto 0);\r
+ PLL_CTRL_IN : in std_logic_vector(3 downto 0);\r
+ ADC_DATA7_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA6_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA5_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA4_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA3_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA2_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA1_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA0_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_CE_OUT : out std_logic;\r
+ ADC_VALID_OUT : out std_logic;\r
+ ADC_SWAP_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end component adc_data_handler;\r
\r
component adc_crossover is\r
port(\r
);\r
end component max_data;\r
\r
-component comp4bit is\r
-port(\r
- DATAA : in std_logic_vector(3 downto 0);\r
- DATAB : in std_logic_vector(3 downto 0);\r
- AGTB : out std_logic\r
-);\r
-end component comp4bit;\r
-\r
component slv_register_bank is\r
generic(\r
RESET_VALUE : std_logic_vector(15 downto 0) := x"0001"\r
);\r
end component slv_register_bank;\r
\r
+component slv_status is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ STATUS_IN : in std_logic_vector(31 downto 0)\r
+);\r
+end component slv_status;\r
+\r
+component slv_status_bank is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(3 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ STAT_0_IN : in std_logic_vector(31 downto 0);\r
+ STAT_1_IN : in std_logic_vector(31 downto 0);\r
+ STAT_2_IN : in std_logic_vector(31 downto 0);\r
+ STAT_3_IN : in std_logic_vector(31 downto 0);\r
+ STAT_4_IN : in std_logic_vector(31 downto 0);\r
+ STAT_5_IN : in std_logic_vector(31 downto 0);\r
+ STAT_6_IN : in std_logic_vector(31 downto 0);\r
+ STAT_7_IN : in std_logic_vector(31 downto 0);\r
+ STAT_8_IN : in std_logic_vector(31 downto 0);\r
+ STAT_9_IN : in std_logic_vector(31 downto 0);\r
+ STAT_10_IN : in std_logic_vector(31 downto 0);\r
+ STAT_11_IN : in std_logic_vector(31 downto 0);\r
+ STAT_12_IN : in std_logic_vector(31 downto 0);\r
+ STAT_13_IN : in std_logic_vector(31 downto 0);\r
+ STAT_14_IN : in std_logic_vector(31 downto 0);\r
+ STAT_15_IN : in std_logic_vector(31 downto 0)\r
+);\r
+end component slv_status_bank;\r
+\r
component pulse_stretch is\r
port(\r
CLK_IN : in std_logic;\r
);\r
end component slv_ped_thr_mem;\r
\r
-component reset_handler is\r
-port( \r
- CLEAR_IN : in std_logic; -- async reset from outside, if available (otherwise '0')\r
- RESET_IN : in std_logic; -- for testing, if not needed, set to '0'\r
- CLK_IN : in std_logic;\r
- TRB_RESET_IN : in std_logic;\r
- RESET_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
-);\r
-end component reset_handler;\r
-\r
component pll_40m is\r
port( \r
CLK : in std_logic;\r
ONEWIRE_INOUT : inout std_logic;\r
-- common regIO status / control registers\r
-- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI\r
- COMMON_STAT_REG_IN : in std_logic_vector(2*32-1 downto 0); -- common status register, bit definitions like in WIKI\r
+ COMMON_STAT_REG_IN : in std_logic_vector(8*32-1 downto 0); -- common status register, bit definitions like in WIKI\r
-- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI\r
- COMMON_CTRL_REG_OUT : out std_logic_vector(2*32-1 downto 0); -- common control register, bit definitions like in WIKI\r
+ COMMON_CTRL_REG_OUT : out std_logic_vector(3*32-1 downto 0); -- common control register, bit definitions like in WIKI\r
-- status register input to regIO / control register output from regIO\r
CONTROL_OUT : out std_logic_vector(63 downto 0);\r
STATUS_IN : in std_logic_vector(127 downto 0);\r
LED_LINK_RXD : out std_logic;\r
LINK_BSM_OUT : out std_logic_vector(3 downto 0);\r
RESET_OUT : out std_logic;\r
+ TICK_10S_OUT : out std_logic;\r
-- Debug\r
DEBUG : out std_logic_vector(63 downto 0)\r
);\r
STAT_13_IN : in std_logic_vector(15 downto 0);\r
STAT_14_IN : in std_logic_vector(15 downto 0);\r
STAT_15_IN : in std_logic_vector(15 downto 0);\r
+ -- FIFO status\r
+ FIFO_STATUS_0_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_1_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_2_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_3_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_4_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_5_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_6_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_7_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_8_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_9_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_10_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_11_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_12_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_13_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_14_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_15_IN : in std_logic_vector(31 downto 0);\r
+ IPU_STATUS_IN : in std_logic_vector(31 downto 0);\r
+ RELEASE_STATUS_IN : in std_logic_vector(31 downto 0);\r
-- some control signals\r
CTRL_LVL_OUT : out std_logic_vector(31 downto 0);\r
CTRL_TRG_OUT : out std_logic_vector(31 downto 0);\r
);\r
end component slave_bus;\r
\r
-component oddrxc is\r
-port( \r
- DA : in std_logic;\r
- DB : in std_logic;\r
- CLK : in std_logic;\r
- RST : in std_logic;\r
- Q : out std_logic\r
-);\r
-end component oddrxc;\r
\r
component apv_trgctrl is\r
port( \r
TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow\r
TRG_FOUND_OUT : out std_logic; -- trigger found\r
+ TRG_TOO_LONG_OUT : out std_logic; -- only for TRG0 channel\r
SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number\r
-- slow control settings\r
TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event\r
CLK_IN : in std_logic; -- 100MHz local clock\r
RESET_IN : in std_logic; -- synchronous reset\r
-- Slow control registers\r
+ VERBOSE_IN : in std_logic; -- add debug words for each APV\r
-- EDS buffer -- back to previous source stage\r
EDS_DATA_IN : in std_logic_vector(39 downto 0);\r
EDS_AVAIL_IN : in std_logic;\r
port( \r
CLK_IN : in std_logic; -- 100MHz local clock\r
RESET_IN : in std_logic; -- synchronous reset\r
+ IPU_RESET_IN : in std_logic; -- requested by TRBnet standard\r
-- Slow control signals\r
SECTOR_IN : in std_logic_vector(2 downto 0);\r
MODULE_IN : in std_logic_vector(2 downto 0);\r
IPU_READ_IN : in std_logic; -- read strobe, low every second cycle\r
IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
+ IPU_LAST_NUM_OUT : out std_logic_vector(31 downto 0); -- last number received / readout\r
LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter\r
-- DHDR buffer input\r
DHDR_DATA_IN : in std_logic_vector(31 downto 0);\r
FIFO_15_DATA_IN : in std_logic_vector(39 downto 0);\r
FIFO_WE_IN : in std_logic_vector(15 downto 0);\r
FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs\r
+ -- data buffer status\r
+ FIFO_0_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_1_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_2_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_3_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_4_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_5_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_6_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_7_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_8_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_9_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_10_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_11_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_12_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_13_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_14_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_15_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ IPU_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ RELEASE_STATUS_OUT : out std_logic_vector(31 downto 0);\r
-- Debug signals\r
DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
DBG_OUT : out std_logic_vector(63 downto 0)\r
TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint\r
+ TRG_TOO_LONG_OUT : out std_logic; -- only for TRG0 channel\r
SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number\r
TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag\r
TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number\r
\r
component fifo_1kx18 is\r
port(\r
- DATA : in std_logic_vector(17 downto 0); \r
- CLOCK : in std_logic; \r
- WREN : in std_logic; \r
- RDEN : in std_logic; \r
- RESET : in std_logic; \r
- Q : out std_logic_vector(17 downto 0); \r
- WCNT : out std_logic_vector(10 downto 0); \r
- EMPTY : out std_logic; \r
- FULL : out std_logic\r
+ DATA : in std_logic_vector(17 downto 0); \r
+ CLOCK : in std_logic; \r
+ WREN : in std_logic; \r
+ RDEN : in std_logic; \r
+ RESET : in std_logic; \r
+ Q : out std_logic_vector(17 downto 0); \r
+ WCNT : out std_logic_vector(10 downto 0); \r
+ EMPTY : out std_logic; \r
+ ALMOSTFULL : out std_logic;\r
+ FULL : out std_logic\r
);\r
end component fifo_1kx18;\r
\r
);\r
end component decoder_8bit;\r
\r
-component adder_5bit is\r
-port( \r
- DATAA : in std_logic_vector(4 downto 0);\r
- DATAB : in std_logic_vector(4 downto 0);\r
- CLOCK : in std_logic;\r
- RESET : in std_logic;\r
- CLOCKEN : in std_logic;\r
- RESULT : out std_logic_vector(4 downto 0)\r
-);\r
-end component adder_5bit;\r
-\r
-component adder_16bit is\r
-port( \r
- DATAA : in std_logic_vector(15 downto 0);\r
- DATAB : in std_logic_vector(15 downto 0);\r
- CLOCK : in std_logic;\r
- RESET : in std_logic;\r
- CLOCKEN : in std_logic;\r
- RESULT : out std_logic_vector(15 downto 0)\r
-);\r
-end component adder_16bit;\r
-\r
-component suber_12bit is\r
-port( \r
- DATAA : in std_logic_vector(11 downto 0);\r
- DATAB : in std_logic_vector(11 downto 0);\r
- CLOCK : in std_logic;\r
- RESET : in std_logic;\r
- CLOCKEN : in std_logic;\r
- RESULT : out std_logic_vector(11 downto 0)\r
-);\r
-end component suber_12bit;\r
-\r
-component comp_12bit is\r
-port(\r
- DATAA : in std_logic_vector(11 downto 0); \r
- DATAB : in std_logic_vector(11 downto 0); \r
- CLOCK : in std_logic; \r
- CLOCKEN : in std_logic; \r
- ACLR : in std_logic; \r
- AGTB : out std_logic\r
-);\r
-end component comp_12bit;\r
-\r
component buf_toc is\r
port( \r
CLK_IN : in std_logic;\r
CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number\r
LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
+ EDS_DATA_IN : in std_logic_vector(39 downto 0); -- DEBUG !!!\r
BUF_GOOD_IN : in std_logic;\r
BUF_BAD_IN : in std_logic;\r
BUF_IGNORE_IN : in std_logic;\r
DO_HEADER_IN : in std_logic;\r
DO_ERROR_IN : in std_logic;\r
SUPPRESS_IN : in std_logic;\r
+ VERBOSE_IN : in std_logic;\r
EVT_TYPE_IN : in std_logic_vector(2 downto 0);\r
RAW_ADDR_IN : in std_logic_vector(6 downto 0);\r
RAW_DATA_IN : in std_logic_vector(37 downto 0);\r
);\r
end component apv_pc_nc_alu;\r
\r
-component comp14bit is\r
-port( \r
- DATAA : in std_logic_vector(13 downto 0);\r
- DATAB : in std_logic_vector(13 downto 0);\r
- CLOCK : in std_logic;\r
- CLOCKEN : in std_logic;\r
- ACLR : in std_logic;\r
- AGEB : out std_logic\r
-); \r
-end component comp14bit;\r
-\r
component input_bram is\r
port( \r
WRADDRESS : in std_logic_vector(10 downto 0);\r
);\r
end component frame_status_mem;\r
\r
-component adder_6bit is\r
-port( \r
- DATAA : in std_logic_vector(5 downto 0);\r
- DATAB : in std_logic_vector(5 downto 0);\r
- CLOCK : in std_logic;\r
- RESET : in std_logic;\r
- CLOCKEN : in std_logic;\r
- RESULT : out std_logic_vector(5 downto 0)\r
-);\r
-end component adder_6bit;\r
-\r
component apv_lock_sm is\r
port( \r
CLK_APV_IN : in std_logic;\r
end package;\r
\r
-- Down in the Dumps...\r
-\r
---component fifo_16x11 is\r
---port( \r
--- DATA : in std_logic_vector(10 downto 0);\r
--- CLOCK : in std_logic;\r
--- WREN : in std_logic;\r
--- RDEN : in std_logic;\r
--- RESET : in std_logic;\r
--- Q : out std_logic_vector(10 downto 0);\r
--- WCNT : out std_logic_vector(4 downto 0);\r
--- EMPTY : out std_logic;\r
--- FULL : out std_logic\r
---);\r
---end component fifo_16x11;\r
-\r
---component dhdr_buf is\r
---port( \r
--- CLK_IN : in std_logic; -- 100MHz master clock\r
--- RESET_IN : in std_logic;\r
--- -- DHDR information block\r
--- DHDR_DATA_IN : in std_logic_vector(47 downto 0); -- EDS data input\r
--- DHDR_WE_IN : in std_logic; -- EDS write enable\r
--- DHDR_DONE_IN : in std_logic; -- release EDS\r
--- DHDR_DATA_OUT : out std_logic_vector(47 downto 0);\r
--- DHDR_AVAILABLE_OUT : out std_logic;\r
--- -- trigger busy information\r
--- BUF_FULL_OUT : out std_logic;\r
--- BUF_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
--- -- Debug signals\r
--- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
---);\r
---end component dhdr_buf;\r
-\r
---component dhdr_buffer_dpram is\r
---port( \r
--- WRADDRESS : in std_logic_vector(3 downto 0);\r
--- DATA : in std_logic_vector(47 downto 0);\r
--- WRCLOCK : in std_logic;\r
--- WE : in std_logic;\r
--- WRCLOCKEN : in std_logic;\r
--- RDADDRESS : in std_logic_vector(3 downto 0);\r
--- RDCLOCK : in std_logic;\r
--- RDCLOCKEN : in std_logic;\r
--- RESET : in std_logic;\r
--- Q : out std_logic_vector(47 downto 0)\r
---);\r
---end component;\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
+--use ieee.std_logic_unsigned.all;\r
\r
library work;\r
use work.trb_net_std.all;\r
use work.adcmv3_components.all;\r
\r
+library ecp2m;\r
+use ecp2m.components.all;\r
+\r
entity adcmv3 is\r
-port( CLK100M : in std_logic; -- OK -- 100MHz LVDS clock \r
- -- trigger inputs\r
- EXT_IN : in std_logic_vector(3 downto 0); -- OK -- external triggers\r
- -- APV stuff\r
- APV0A_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
- APV0B_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
- APV0A_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
- APV0B_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
- APV0_RST : out std_logic; -- OK -- APV bank 0: reset signal, low active\r
- APV0_SDA : inout std_logic; -- OK -- APV bank 0: I2C bus SDA\r
- APV0_SCL : inout std_logic; -- OK -- APV bank 0: I2C bus SCL\r
- ENA_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
- APV1A_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
- APV1B_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
- APV1A_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
- APV1B_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
- APV1_RST : out std_logic; -- OK -- APV bank 1: reset signal, low active\r
- APV1_SDA : inout std_logic; -- OK -- APV bank 1: I2C bus SDA\r
- APV1_SCL : inout std_logic; -- OK -- APV bank 1: I2C bus SCL\r
- ENB_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
- -- ADC0 stuff\r
- ADC0_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
- ADC0_RST : out std_logic; -- OK -- ADC reset signal\r
- ADC0_PD : out std_logic; -- OK -- ADC powerdown signal\r
- ADC0_CS : out std_logic; -- OK -- ADC /CS signal\r
- ADC0_SDI : out std_logic; -- OK -- ADC serial data in\r
- ADC0_SCK : out std_logic; -- OK -- ADC serial clock\r
- ADC0_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
- ADC0_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
- ADC0_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
- -- ADC1 stuff\r
- ADC1_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
- ADC1_RST : out std_logic; -- OK -- ADC reset signal\r
- ADC1_PD : out std_logic; -- OK -- ADC powerdown signal\r
- ADC1_CS : out std_logic; -- OK -- ADC /CS signal\r
- ADC1_SDI : out std_logic; -- OK -- ADC serial data in\r
- ADC1_SCK : out std_logic; -- OK -- ADC serial clock\r
- ADC1_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
- ADC1_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
- ADC1_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
- -- uC connections\r
- UC_RESET : in std_logic; -- OK -- uC reset, high active\r
- UC_REBOOT : out std_logic; -- OK -- was UC_FPGA(3), requests FPGA reboot\r
- -- SerDes pins \r
- HDINN2 : in std_logic; -- highspeed INPUT\r
- HDINP2 : in std_logic; --\r
- HDOUTN2 : out std_logic; -- highspeed OUTPUT\r
- HDOUTP2 : out std_logic; -- \r
- SD_PRESENT : in std_logic; -- OK -- Present signal from SFP\r
- SD_LOS : in std_logic; -- OK -- Loss Of Signal from SFP\r
- SD_TXDIS : out std_logic; -- OK -- SFP transmitter disable\r
- ADCM_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on ADCM\r
- -- Backplane sense wires\r
- BP_MODULE : in std_logic_vector(3 downto 0); -- OK -- module number input from backplane\r
- BP_SECTOR : in std_logic_vector(3 downto 0); -- OK -- sector number input from backplane\r
- BP_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on backplane \r
- BP_LED : out std_logic; -- OK -- backplane LED \r
- -- LEDs\r
- FPGA_LED : out std_logic_vector(6 downto 3); -- OK -- general purpose LEDS\r
- FPGA_LED_RXD : out std_logic; -- OK -- FPGA_LED(2)\r
- FPGA_LED_TXD : out std_logic; -- OK -- FPGA_LED(1)\r
- FPGA_LED_LINK : out std_logic; -- OK -- FPGA_LED(0)\r
- FPGA_LED_PLL : out std_logic; -- OK -- PLL locked \r
- FPGA_LED_ADC : out std_logic_vector(1 downto 0); -- OK -- ADCx OK LED \r
- -- 1Wire chips on APV FEs\r
- APV0_1W : inout std_logic_vector(7 downto 0);\r
- APV1_1W : inout std_logic_vector(7 downto 0);\r
- -- SPI FlashROM connections\r
- U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM\r
- U_SPI_SCK : out std_logic; -- OK -- clock\r
- U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM\r
- U_SPI_SDO : in std_logic; -- OK -- connects to SO on the FlashROM\r
- -- Debug connections\r
- DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header\r
+port( \r
+ CLK100M : in std_logic; -- OK -- 100MHz LVDS clock \r
+ -- trigger inputs\r
+ EXT_IN : in std_logic_vector(3 downto 0); -- OK -- external triggers\r
+ -- APV stuff\r
+ APV0A_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
+ APV0B_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
+ APV0A_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
+ APV0B_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
+ APV0_RST : out std_logic; -- OK -- APV bank 0: reset signal, low active\r
+ APV0_SDA : inout std_logic; -- OK -- APV bank 0: I2C bus SDA\r
+ APV0_SCL : inout std_logic; -- OK -- APV bank 0: I2C bus SCL\r
+ ENA_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
+ APV1A_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
+ APV1B_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
+ APV1A_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
+ APV1B_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
+ APV1_RST : out std_logic; -- OK -- APV bank 1: reset signal, low active\r
+ APV1_SDA : inout std_logic; -- OK -- APV bank 1: I2C bus SDA\r
+ APV1_SCL : inout std_logic; -- OK -- APV bank 1: I2C bus SCL\r
+ ENB_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
+ -- ADC0 stuff\r
+ ADC0_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
+ ADC0_RST : out std_logic; -- OK -- ADC reset signal\r
+ ADC0_PD : out std_logic; -- OK -- ADC powerdown signal\r
+ ADC0_CS : out std_logic; -- OK -- ADC /CS signal\r
+ ADC0_SDI : out std_logic; -- OK -- ADC serial data in\r
+ ADC0_SCK : out std_logic; -- OK -- ADC serial clock\r
+ ADC0_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
+ ADC0_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
+ ADC0_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
+ -- ADC1 stuff\r
+ ADC1_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
+ ADC1_RST : out std_logic; -- OK -- ADC reset signal\r
+ ADC1_PD : out std_logic; -- OK -- ADC powerdown signal\r
+ ADC1_CS : out std_logic; -- OK -- ADC /CS signal\r
+ ADC1_SDI : out std_logic; -- OK -- ADC serial data in\r
+ ADC1_SCK : out std_logic; -- OK -- ADC serial clock\r
+ ADC1_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
+ ADC1_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
+ ADC1_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
+ -- uC connections\r
+ UC_RESET : in std_logic; -- OK -- uC reset, high active\r
+ UC_REBOOT : out std_logic; -- OK -- was UC_FPGA(3), requests FPGA reboot\r
+ -- SerDes pins \r
+ HDINN2 : in std_logic; -- highspeed INPUT\r
+ HDINP2 : in std_logic; --\r
+ HDOUTN2 : out std_logic; -- highspeed OUTPUT\r
+ HDOUTP2 : out std_logic; -- \r
+ SD_PRESENT : in std_logic; -- OK -- Present signal from SFP\r
+ SD_LOS : in std_logic; -- OK -- Loss Of Signal from SFP\r
+ SD_TXDIS : out std_logic; -- OK -- SFP transmitter disable\r
+ ADCM_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on ADCM\r
+ -- Backplane sense wires\r
+ BP_MODULE : in std_logic_vector(3 downto 0); -- OK -- module number input from backplane\r
+ BP_SECTOR : in std_logic_vector(3 downto 0); -- OK -- sector number input from backplane\r
+ BP_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on backplane \r
+ BP_LED : out std_logic; -- OK -- backplane LED \r
+ -- LEDs\r
+ FPGA_LED : out std_logic_vector(6 downto 3); -- OK -- general purpose LEDS\r
+ FPGA_LED_RXD : out std_logic; -- OK -- FPGA_LED(2)\r
+ FPGA_LED_TXD : out std_logic; -- OK -- FPGA_LED(1)\r
+ FPGA_LED_LINK : out std_logic; -- OK -- FPGA_LED(0)\r
+ FPGA_LED_PLL : out std_logic; -- OK -- PLL locked \r
+ FPGA_LED_ADC : out std_logic_vector(1 downto 0); -- OK -- ADCx OK LED \r
+ -- 1Wire chips on APV FEs\r
+ APV0_1W : inout std_logic_vector(7 downto 0);\r
+ APV1_1W : inout std_logic_vector(7 downto 0);\r
+ -- SPI FlashROM connections\r
+ U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM\r
+ U_SPI_SCK : out std_logic; -- OK -- clock\r
+ U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM\r
+ U_SPI_SDO : in std_logic -- OK -- connects to SO on the FlashROM\r
+ -- Debug connections\r
+-- DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header\r
);\r
end;\r
\r
\r
signal adc0_ce : std_logic;\r
signal adc0_valid : std_logic;\r
+signal adc0_swap : std_logic;\r
signal adc0_reset : std_logic;\r
signal adc0_powerdown : std_logic;\r
signal adc1_ce : std_logic;\r
signal adc1_valid : std_logic;\r
+signal adc1_swap : std_logic;\r
signal adc1_reset : std_logic;\r
signal adc1_powerdown : std_logic;\r
\r
signal apv_frame_reqd : std_logic; -- one 100MHz pulse per requested frame\r
signal apv0_reset : std_logic;\r
signal apv1_reset : std_logic;\r
+signal frontend_reset : std_logic;\r
signal apv_reset : std_logic;\r
signal adc_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8]\r
signal lvds_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8]\r
signal fifo_space_req : std_logic_vector(11 downto 0);\r
type reg_40bit_t is array (0 to 15) of std_logic_vector(39 downto 0);\r
signal fifo_data : reg_40bit_t;\r
+type reg_32bit_t is array (0 to 15) of std_logic_vector(31 downto 0);\r
+signal fifo_status : reg_32bit_t;\r
+\r
+signal ipu_handler_status : std_logic_vector(31 downto 0);\r
+signal lvl1_release_status : std_logic_vector(31 downto 0);\r
\r
-- APV control / status signals\r
type reg_16bit_t is array (0 to 15) of std_logic_vector(15 downto 0);\r
signal ipu_read : std_logic;\r
signal ipu_length : std_logic_vector(15 downto 0);\r
signal ipu_error_pattern : std_logic_vector(31 downto 0);\r
+signal ipu_last_num : std_logic_vector(31 downto 0);\r
\r
signal local_lvl1_counter : std_logic_vector(15 downto 0);\r
signal local_lvl2_counter : std_logic_vector(15 downto 0);\r
signal adc0_iodelay : std_logic_vector(3 downto 0);\r
signal adc1_iodelay : std_logic_vector(3 downto 0);\r
\r
- \r
+signal cts_clk40m : std_logic;\r
+signal cts_clk40m_locked : std_logic;\r
+signal test_reg40m : std_logic;\r
+\r
+signal serious_error_flag : std_logic;\r
+signal error_flag : std_logic;\r
+signal warning_flag : std_logic;\r
+signal note_flag : std_logic;\r
+\r
+signal broken_buf : std_logic_vector(15 downto 0);\r
+signal next_not_configured : std_logic;\r
+signal not_configured : std_logic;\r
+\r
+signal apv_error : std_logic_vector(15 downto 0);\r
+signal next_fe_error : std_logic;\r
+signal fe_error : std_logic;\r
+\r
+signal test_data_in : unsigned(17 downto 0);\r
+signal test_data_out : std_logic_vector(17 downto 0);\r
+signal test_data_wren : std_logic;\r
+signal test_data_rden : std_logic;\r
+signal test_data_empty : std_logic;\r
+signal test_data_full : std_logic;\r
+\r
+component lattice_ecp2m_fifo_16bit_dualport is\r
+port(\r
+ Data: in std_logic_vector(17 downto 0); \r
+ WrClock: in std_logic; \r
+ RdClock: in std_logic; \r
+ WrEn: in std_logic; \r
+ RdEn: in std_logic; \r
+ Reset: in std_logic; \r
+ RPReset: in std_logic; \r
+ Q: out std_logic_vector(17 downto 0); \r
+ Empty: out std_logic; \r
+ Full: out std_logic\r
+);\r
+end component lattice_ecp2m_fifo_16bit_dualport;\r
+\r
+begin\r
+\r
+\r
+----------------------------------------\r
+-- TEST TEST TEST TEST TEST\r
+----------------------------------------\r
+THE_TEST_COUNTER: process( sysclk )\r
begin\r
+ if( rising_edge(sysclk) ) then\r
+ if( global_sync_reset = '1' ) then\r
+ test_data_in <= (others => '0');\r
+ else\r
+ test_data_in <= test_data_in + 1;\r
+ end if;\r
+ end if;\r
+end process THE_TEST_COUNTER;\r
+\r
+THE_TEST_FIFO: lattice_ecp2m_fifo_16bit_dualport\r
+port map(\r
+ Data => std_logic_vector(test_data_in),\r
+ WrClock => sysclk,\r
+ RdClock => sysclk, \r
+ WrEn => test_data_wren, \r
+ RdEn => test_data_rden, \r
+ Reset => global_sync_reset, \r
+ RPReset => '0', \r
+ Q => test_data_out, \r
+ Empty => test_data_empty, \r
+ Full => test_data_full\r
+);\r
+\r
+test_data_rden <= not test_data_empty;\r
+test_data_wren <= std_logic(test_data_in(3));\r
+\r
+\r
+simple_status(63 downto 54) <= (others => '0');\r
+simple_status(53) <= test_data_wren;\r
+simple_status(52) <= test_data_rden;\r
+simple_status(51) <= test_data_full;\r
+simple_status(50) <= test_data_empty;\r
+simple_status(49 downto 32) <= test_data_out;\r
+----------------------------------------\r
+-- TEST TEST TEST TEST TEST\r
+----------------------------------------\r
\r
----------------------------------------\r
-- Async reset assignment --\r
----------------------------------------\r
---async_reset <= '0'; -- no async reset\r
async_reset <= uc_reset; -- uC reset pin\r
\r
\r
----------------------------------------\r
-- Reset handler / spike surpression --\r
----------------------------------------\r
-THE_RESET_HANDLER: reset_handler\r
-port map( \r
+THE_RESET_HANDLER: reset_handler \r
+generic map (\r
+ RESET_DELAY => x"00ff"\r
+)\r
+port map (\r
CLEAR_IN => async_reset,\r
- RESET_IN => '0',\r
- CLK_IN => sysclk,\r
+ CLEAR_N_IN => '1', -- unused\r
+ CLK_IN => clk100m,\r
+ SYSCLK_IN => sysclk,\r
+ PLL_LOCKED_IN => clk100m_locked,\r
+ RESET_IN => common_ctrl_reg(3),\r
TRB_RESET_IN => reset_by_trb,\r
+ CLEAR_OUT => open,\r
RESET_OUT => global_sync_reset,\r
DEBUG_OUT => open\r
);\r
\r
\r
+----------------------------------------\r
+-- Reboot handler (pulse triggered) --\r
+----------------------------------------\r
+THE_REBOOT_HANDLER: reboot_handler\r
+port map( \r
+ RESET_IN => reset_by_trb,\r
+ CLK_IN => sysclk,\r
+ START_IN => common_ctrl_reg(15),\r
+ REBOOT_OUT => uc_reboot,\r
+ DEBUG_OUT => open\r
+);\r
+\r
+\r
----------------------------------------\r
-- 100MHz PLL -> 40MHz / 100MHz --\r
----------------------------------------\r
LOCK => clk100m_locked\r
);\r
\r
+-- 40MHz PLL, takes central clock distributed by CTS\r
+THE_SYNC_PLL: sync_pll_40m\r
+port map(\r
+ CLK => ext_in(3),\r
+ RESET => ctrl_pll(4),\r
+ CLKOP => cts_clk40m,\r
+ LOCK => cts_clk40m_locked\r
+);\r
+\r
+THE_TEST_REG: process( cts_clk40m, cts_clk40m_locked )\r
+begin\r
+ if( cts_clk40m_locked = '0' ) then\r
+ test_reg40m <= '0';\r
+ else\r
+ if( rising_edge(cts_clk40m) ) then\r
+ test_reg40m <= not test_reg40m;\r
+ end if;\r
+ end if;\r
+end process THE_TEST_REG;\r
\r
----------------------------------------\r
-- TRB endpoint --\r
-- [0] reset frontends\r
\r
-- LVL1 error pattern, to be sent back to CTS with each trigger\r
-lvl1_error_pattern(31 downto 23) <= (others => '0');\r
-lvl1_error_pattern(22) <= '0'; -- not configured\r
-lvl1_error_pattern(21) <= '0'; -- buffers almost full\r
-lvl1_error_pattern(20) <= '0'; -- buffers half full\r
-lvl1_error_pattern(19 downto 18) <= (others => '0');\r
-lvl1_error_pattern(17) <= '0'; -- missing timing trigger (done by Jan)\r
-lvl1_error_pattern(16) <= '0'; -- LVL1 tag mismatch with local counters (done by Jan)\r
-lvl1_error_pattern(15 downto 0) <= (others => '0'); \r
-\r
-\r
-------------------------------------------------------------------\r
--- DEBUG DEBUG DEBUG\r
-------------------------------------------------------------------\r
-debug_clk <= sysclk;\r
-\r
---debug(42 downto 0) <= (others => '0');\r
-\r
-debug(42 downto 39) <= (others => '0'); \r
--- IPU signals\r
-debug(38 downto 35) <= ipu_number(3 downto 0);\r
-debug(34) <= ipu_start_readout;\r
-debug(33) <= ipu_dataready;\r
-debug(32) <= ipu_read;\r
-debug(31) <= ipu_readout_finished;\r
--- FIFO signals\r
-debug(30) <= fifo_start; -- ped_corr_ctrl -> ipu_stage => data procession starts (unused in ipu_stage)\r
-debug(29) <= fifo_we(0); -- ped_corr_ctrl -> ipu_stage => transfer processed data into data FIFO (0)\r
-debug(28) <= fifo_done; -- ped_corr_ctrl -> ipu_stage => store length count data in small FIFOs\r
-debug(27) <= dhdr_store; -- ped_corr_ctrl -> ipu_stage => store DHDR information for IPU\r
-debug(26) <= dhdr_buf_full; -- ipu_stage ->\r
--- EventDataSheet / buffer signals\r
-debug(25) <= buf_done; -- ped_corr_ctrl -> raw_buf_stage => raw data has been processed\r
-debug(24) <= buf_tick(0); -- raw_buf_stage -> ped_corr_ctrl => synced tickmarks\r
-debug(23) <= buf_ready(0); -- raw_buf_stage => adc_last\r
-debug(22) <= buf_start(0); -- raw_buf_stage -> ped_corr_ctrl => adc_start\r
-debug(21 downto 17) <= buf_data(0)(34 downto 30);\r
-debug(16) <= raw_buf_full; -- raw_buf_stage -> apv_trgctrl => at least one raw buffer is full\r
-debug(15) <= eds_done; -- ped_corr_ctrl -> apv_trgctrl => EDS data has been transfered, release buffer entry\r
-debug(14) <= eds_avail; -- apv_trgctrl -> ped_corr_ctrl => at least one EDS is available\r
-debug(13) <= eds_buf_full; -- apv_trgctrl => EDS buffer is full\r
-debug(12 downto 8) <= eds_buf_level; \r
--- timing trigger signals\r
-debug(7) <= timing_trg_found; -- apv_trgctrl -> endpoint => timing trigger has arrived\r
-debug(6) <= lvl1_trg_received; -- endpoint -> apv_trgctrl => LVL1 trigger packet has arrived\r
-debug(5) <= lvl1_trg_missing; -- apv_trgctrl -> endpoint => two consecutive timing triggers found\r
-debug(4) <= lvl1_trg_release; -- apv_trgctrl -> endpoint => release LVL1 busy \r
-debug(3 downto 0) <= lvl1_trg_number(3 downto 0);\r
+lvl1_error_pattern(31 downto 24) <= (others => '0'); -- reserved\r
+lvl1_error_pattern(23) <= fe_error; -- frontend error\r
+lvl1_error_pattern(22) <= not_configured; -- not configured\r
+lvl1_error_pattern(21) <= '0'; -- buffers almost full\r
+lvl1_error_pattern(20) <= '0'; -- buffers half full\r
+lvl1_error_pattern(19 downto 18) <= (others => '0'); -- reserved\r
+lvl1_error_pattern(17) <= lvl1_trg_missing; -- missing timing trigger (done by Jan)\r
+lvl1_error_pattern(16) <= '0'; -- LVL1 tag mismatch with local counters (done by Jan)\r
+lvl1_error_pattern(15 downto 0) <= (others => '0'); -- reserved for common status bits\r
\r
\r
----------------------------------------------\r
-- mixed status and control bit definitions --\r
----------------------------------------------\r
\r
--- Common status register\r
-common_stat_reg(63 downto 48) <= (others => '0'); -- LVL2 counter\r
-common_stat_reg(47 downto 32) <= (others => '0'); -- LVL1 counter (doen by Jan)\r
-common_stat_reg(31 downto 20) <= x"000"; -- reserved for temp sensor\r
-common_stat_reg(19 downto 6) <= (others => '0');\r
-common_stat_reg(5) <= '0'; -- LVL2 counter mismatch\r
-common_stat_reg(4) <= '0'; -- LVL1 counter mismatch (done by Jan)\r
-common_stat_reg(3 downto 0) <= (others => '0');\r
+-- Common status register \r
+-- CSR1\r
+common_stat_reg(63 downto 48) <= ipu_last_num(15 downto 0); -- LVL2 counter\r
+common_stat_reg(47 downto 32) <= local_lvl1_counter; -- LVL1 counter\r
+-- CSR0\r
+common_stat_reg(31 downto 20) <= x"000"; -- reserved for temp sensor\r
+common_stat_reg(19 downto 13) <= (others => '0');\r
+common_stat_reg(12) <= '0'; -- IPU: single broken event\r
+common_stat_reg(11) <= '0'; -- IPU: severe problem\r
+common_stat_reg(10) <= '0'; -- IPU: partially not found\r
+common_stat_reg(9) <= ipu_error_pattern(20); -- IPU: not found\r
+common_stat_reg(8) <= lvl1_trg_missing; -- LVL1: timing trigger missing\r
+common_stat_reg(7) <= fe_error; -- LVL1: frontend error\r
+common_stat_reg(6) <= not_configured; -- LVL1: not configured\r
+common_stat_reg(5) <= '0'; -- LVL2 counter mismatch (not implemented)\r
+common_stat_reg(4) <= '0'; -- LVL1 trigger counter mismatch (reserved)\r
+common_stat_reg(3) <= note_flag; -- note flag\r
+common_stat_reg(2) <= warning_flag; -- warning flag\r
+common_stat_reg(1) <= error_flag; -- error flag\r
+common_stat_reg(0) <= serious_error_flag; -- serious error flag\r
+\r
+serious_error_flag <= lvl1_trg_missing or fe_error or not_configured;\r
+error_flag <= ipu_error_pattern(20);\r
+warning_flag <= '0';\r
+note_flag <= '0';\r
\r
-- Control register bit padding\r
ctrl_bithigh <= ctrl_lvl(31 downto 24) & x"0";\r
enb_lvds(6) <= adc_on(14) or lvds_on(14);\r
enb_lvds(7) <= adc_on(9) or lvds_on(9);\r
\r
-bp_led <= '1'; -- LED is against GND!\r
+bp_led <= cts_clk40m_locked; -- LED is against GND!\r
\r
\r
----------------------------------------\r
STAT_13_IN => adc_stat_reg(13),\r
STAT_14_IN => adc_stat_reg(14),\r
STAT_15_IN => adc_stat_reg(15),\r
+ -- FIFO status\r
+ FIFO_STATUS_0_IN => fifo_status(0),\r
+ FIFO_STATUS_1_IN => fifo_status(1),\r
+ FIFO_STATUS_2_IN => fifo_status(2),\r
+ FIFO_STATUS_3_IN => fifo_status(3),\r
+ FIFO_STATUS_4_IN => fifo_status(4),\r
+ FIFO_STATUS_5_IN => fifo_status(5),\r
+ FIFO_STATUS_6_IN => fifo_status(6),\r
+ FIFO_STATUS_7_IN => fifo_status(7),\r
+ FIFO_STATUS_8_IN => fifo_status(8),\r
+ FIFO_STATUS_9_IN => fifo_status(9),\r
+ FIFO_STATUS_10_IN => fifo_status(10),\r
+ FIFO_STATUS_11_IN => fifo_status(11),\r
+ FIFO_STATUS_12_IN => fifo_status(12),\r
+ FIFO_STATUS_13_IN => fifo_status(13),\r
+ FIFO_STATUS_14_IN => fifo_status(14),\r
+ FIFO_STATUS_15_IN => fifo_status(15),\r
+ IPU_STATUS_IN => ipu_handler_status,\r
+ RELEASE_STATUS_IN => lvl1_release_status,\r
-- some control signals\r
CTRL_LVL_OUT => ctrl_lvl,\r
CTRL_TRG_OUT => ctrl_trg,\r
status_pll(14) <= clk40m_locked;\r
status_pll(13) <= adc1_valid;\r
status_pll(12) <= adc0_valid;\r
-status_pll(11 downto 8) <= (others => '0');\r
+status_pll(11) <= adc1_swap;\r
+status_pll(10) <= adc0_swap;\r
+status_pll(9) <= test_reg40m; --'0';\r
+status_pll(8) <= cts_clk40m_locked;\r
status_pll(7) <= '0'; -- make it human readable\r
status_pll(6 downto 4) <= bp_sector_qq(2 downto 0); -- given by backplane DIP switch, for readback only\r
status_pll(3) <= '0'; -- make it human readable\r
simple_status(127 downto 104) <= (others => '0');\r
simple_status(103 downto 96) <= trgctrl_debug(39 downto 32);\r
simple_status(95 downto 64) <= trgctrl_debug(31 downto 0);\r
-simple_status(63 downto 32) <= (others => '0');\r
+--simple_status(63 downto 32) <= (others => '0');\r
simple_status(31 downto 16) <= local_lvl2_counter;\r
simple_status(15 downto 0) <= local_lvl1_counter;\r
\r
--- all APVs are reset together\r
-apv_reset <= apv0_reset or apv1_reset;\r
+-- all APVs are reset together, including the common FE reset\r
+THE_APV_PULSE_STRETCH: pulse_stretch\r
+port map(\r
+ CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ START_IN => common_ctrl_reg(0),\r
+ PULSE_OUT => frontend_reset,\r
+ DEBUG_OUT => open\r
+);\r
\r
--- APV status registers\r
-adc_stat_reg(15) <= buf_data(15)(37 downto 30) & raw_buf_debug(63 downto 60) & x"f";\r
-adc_stat_reg(14) <= buf_data(14)(37 downto 30) & raw_buf_debug(59 downto 56) & x"e";\r
-adc_stat_reg(13) <= buf_data(13)(37 downto 30) & raw_buf_debug(55 downto 52) & x"d";\r
-adc_stat_reg(12) <= buf_data(12)(37 downto 30) & raw_buf_debug(51 downto 48) & x"c";\r
-adc_stat_reg(11) <= buf_data(11)(37 downto 30) & raw_buf_debug(47 downto 44) & x"b";\r
-adc_stat_reg(10) <= buf_data(10)(37 downto 30) & raw_buf_debug(43 downto 40) & x"a";\r
-adc_stat_reg(9) <= buf_data(9)(37 downto 30) & raw_buf_debug(39 downto 36) & x"9";\r
-adc_stat_reg(8) <= buf_data(8)(37 downto 30) & raw_buf_debug(35 downto 32) & x"8";\r
-adc_stat_reg(7) <= buf_data(7)(37 downto 30) & raw_buf_debug(31 downto 28) & x"7";\r
-adc_stat_reg(6) <= buf_data(6)(37 downto 30) & raw_buf_debug(27 downto 24) & x"6";\r
-adc_stat_reg(5) <= buf_data(5)(37 downto 30) & raw_buf_debug(23 downto 20) & x"5";\r
-adc_stat_reg(4) <= buf_data(4)(37 downto 30) & raw_buf_debug(19 downto 16) & x"4";\r
-adc_stat_reg(3) <= buf_data(3)(37 downto 30) & raw_buf_debug(15 downto 12) & x"3";\r
-adc_stat_reg(2) <= buf_data(2)(37 downto 30) & raw_buf_debug(11 downto 8) & x"2";\r
-adc_stat_reg(1) <= buf_data(1)(37 downto 30) & raw_buf_debug(7 downto 4) & x"1";\r
-adc_stat_reg(0) <= buf_data(0)(37 downto 30) & raw_buf_debug(3 downto 0) & x"0";\r
-\r
-adc_on(15) <= adc_ctrl_reg(15)(0);\r
-adc_on(14) <= adc_ctrl_reg(14)(0);\r
-adc_on(13) <= adc_ctrl_reg(13)(0);\r
-adc_on(12) <= adc_ctrl_reg(12)(0);\r
-adc_on(11) <= adc_ctrl_reg(11)(0);\r
-adc_on(10) <= adc_ctrl_reg(10)(0);\r
-adc_on(9) <= adc_ctrl_reg(9)(0);\r
-adc_on(8) <= adc_ctrl_reg(8)(0);\r
-adc_on(7) <= adc_ctrl_reg(7)(0);\r
-adc_on(6) <= adc_ctrl_reg(6)(0);\r
-adc_on(5) <= adc_ctrl_reg(5)(0);\r
-adc_on(4) <= adc_ctrl_reg(4)(0);\r
-adc_on(3) <= adc_ctrl_reg(3)(0);\r
-adc_on(2) <= adc_ctrl_reg(2)(0);\r
-adc_on(1) <= adc_ctrl_reg(1)(0);\r
-adc_on(0) <= adc_ctrl_reg(0)(0);\r
-\r
-lvds_on(15) <= adc_ctrl_reg(15)(1);\r
-lvds_on(14) <= adc_ctrl_reg(14)(1);\r
-lvds_on(13) <= adc_ctrl_reg(13)(1);\r
-lvds_on(12) <= adc_ctrl_reg(12)(1);\r
-lvds_on(11) <= adc_ctrl_reg(11)(1);\r
-lvds_on(10) <= adc_ctrl_reg(10)(1);\r
-lvds_on(9) <= adc_ctrl_reg(9)(1);\r
-lvds_on(8) <= adc_ctrl_reg(8)(1);\r
-lvds_on(7) <= adc_ctrl_reg(7)(1);\r
-lvds_on(6) <= adc_ctrl_reg(6)(1);\r
-lvds_on(5) <= adc_ctrl_reg(5)(1);\r
-lvds_on(4) <= adc_ctrl_reg(4)(1);\r
-lvds_on(3) <= adc_ctrl_reg(3)(1);\r
-lvds_on(2) <= adc_ctrl_reg(2)(1);\r
-lvds_on(1) <= adc_ctrl_reg(1)(1);\r
-lvds_on(0) <= adc_ctrl_reg(0)(1);\r
+apv_reset <= apv0_reset or apv1_reset or frontend_reset;\r
\r
+-- APV status registers\r
+-- "ADC on" bits\r
+-- "LVDS ON" bits \r
+GEN_ADC_LVDS_ON: for i in 0 to 15 generate\r
+ adc_on(i) <= adc_ctrl_reg(i)(0);\r
+ lvds_on(i) <= adc_ctrl_reg(i)(1);\r
+ adc_stat_reg(i) <= buf_data(i)(37 downto 30) & raw_buf_debug(i*4+3 downto i*4+0) & std_logic_vector(to_unsigned(i,4));\r
+ broken_buf(i) <= buf_data(i)(36); -- BUF_BROKEN bit\r
+ apv_error(i) <= buf_data(i)(26); -- APV error frame bit\r
+end generate GEN_ADC_LVDS_ON;\r
+\r
+next_not_configured <= '1' when (broken_buf /= x"0000") else '0';\r
+next_fe_error <= '1' when (apv_error /= x"0000") else '0';\r
\r
----------------------------------------\r
-- IPU endpoint for data transport --\r
IPU_READ_IN => ipu_read,\r
IPU_LENGTH_OUT => ipu_length,\r
IPU_ERROR_PATTERN_OUT => ipu_error_pattern,\r
+ IPU_LAST_NUM_OUT => ipu_last_num,\r
LVL2_COUNTER_OUT => local_lvl2_counter,\r
-- DHDR buffer input \r
DHDR_DATA_IN => dhdr_data,\r
FIFO_15_DATA_IN => fifo_data(15),\r
FIFO_WE_IN => fifo_we,\r
FIFO_DONE_IN => fifo_done,\r
+ FIFO_0_STATUS_OUT => fifo_status(0),\r
+ FIFO_1_STATUS_OUT => fifo_status(1),\r
+ FIFO_2_STATUS_OUT => fifo_status(2),\r
+ FIFO_3_STATUS_OUT => fifo_status(3),\r
+ FIFO_4_STATUS_OUT => fifo_status(4),\r
+ FIFO_5_STATUS_OUT => fifo_status(5),\r
+ FIFO_6_STATUS_OUT => fifo_status(6),\r
+ FIFO_7_STATUS_OUT => fifo_status(7),\r
+ FIFO_8_STATUS_OUT => fifo_status(8),\r
+ FIFO_9_STATUS_OUT => fifo_status(9),\r
+ FIFO_10_STATUS_OUT => fifo_status(10),\r
+ FIFO_11_STATUS_OUT => fifo_status(11),\r
+ FIFO_12_STATUS_OUT => fifo_status(12),\r
+ FIFO_13_STATUS_OUT => fifo_status(13),\r
+ FIFO_14_STATUS_OUT => fifo_status(14),\r
+ FIFO_15_STATUS_OUT => fifo_status(15),\r
+ IPU_STATUS_OUT => ipu_handler_status,\r
+ RELEASE_STATUS_OUT => lvl1_release_status,\r
-- Debug signals\r
DBG_BSM_OUT => open,\r
DBG_OUT => fifo_debug --open\r
port map( \r
CLK_IN => sysclk,\r
RESET_IN => global_sync_reset,\r
+ VERBOSE_IN => common_ctrl_reg(31), -- QUICKHACK\r
EDS_DATA_IN => eds_data,\r
EDS_AVAIL_IN => eds_avail,\r
EDS_DONE_OUT => eds_done,\r
------------------------------------------\r
-- Raw data processing and storage unit --\r
------------------------------------------\r
-THE_RAW_BUF_STAGE: raw_buf_stage_new\r
+THE_RAW_BUF_STAGE: raw_buf_stage\r
port map( \r
CLK_IN => sysclk,\r
CLK_APV_IN => clk_apv,\r
----------------------------------------\r
-- ADC1 data handler --\r
----------------------------------------\r
-THE_ADC1_HANDLER: adc_data_handler_new \r
+THE_ADC1_HANDLER: adc_data_handler \r
port map( \r
RESET_IN => reset_by_trb,\r
ADC_LCLK_IN => adc1_lclk,\r
ADC_DATA0_OUT => adc_raw_data(8),\r
ADC_CE_OUT => adc1_ce,\r
ADC_VALID_OUT => adc1_valid,\r
+ ADC_SWAP_OUT => adc1_swap,\r
DEBUG_OUT => open\r
);\r
\r
----------------------------------------\r
-- ADC0 data handler --\r
----------------------------------------\r
-THE_ADC0_HANDLER: adc_data_handler_new \r
+THE_ADC0_HANDLER: adc_data_handler \r
port map( \r
RESET_IN => reset_by_trb,\r
ADC_LCLK_IN => adc0_lclk,\r
ADC_DATA0_OUT => adc_raw_data(0),\r
ADC_CE_OUT => adc0_ce,\r
ADC_VALID_OUT => adc0_valid,\r
+ ADC_SWAP_OUT => adc0_swap,\r
DEBUG_OUT => open\r
);\r
\r
TRB_TTYPE_IN => lvl1_trg_type, -- from TRB LVL1 endpoint\r
TRB_TINFO_IN => lvl1_trg_information, -- from TRB LVL1 endpoint\r
TRB_TRGRCVD_IN => lvl1_trg_received, -- from TRB LVL1 endpoint\r
- TRB_MISSING_OUT => lvl1_trg_missing,\r
+ TRB_MISSING_OUT => lvl1_trg_missing, -- missing timing trigger\r
TRB_RELEASE_OUT => lvl1_trg_release, -- to TRB LVL1 endpoint\r
TRB_COUNTER_OUT => local_lvl1_counter, -- own trigger counter\r
TRB_COUNTER_IN => lvl1_int_trg_number, -- official TRB trigger counter\r
-- DIP switch input registers --\r
----------------------------------------\r
-- switch "OFF" => '1', switch "ON" => '0'; so invert it\r
-THE_BP_SYNC_PROC: process( sysclk )\r
+THE_SYNC_PROC: process( sysclk )\r
begin\r
if( rising_edge(sysclk) ) then\r
- bp_module_qq <= bp_module_q;\r
- bp_module_q <= not bp_module;\r
- bp_sector_qq <= bp_sector_q;\r
- bp_sector_q <= not bp_sector;\r
+ bp_module_qq <= bp_module_q;\r
+ bp_module_q <= not bp_module;\r
+ bp_sector_qq <= bp_sector_q;\r
+ bp_sector_q <= not bp_sector;\r
+ not_configured <= next_not_configured; -- status bit\r
+ fe_error <= next_fe_error; -- status bit\r
end if;\r
-end process THE_BP_SYNC_PROC;\r
-\r
-\r
-----------------------------------------\r
--- Reboot handler (pulse triggered) --\r
-----------------------------------------\r
-THE_REBOOT_HANDLER: reboot_handler\r
-port map( \r
- RESET_IN => reset_by_trb,\r
- CLK_IN => sysclk,\r
- START_IN => common_ctrl_reg(15),\r
- REBOOT_OUT => uc_reboot,\r
- DEBUG_OUT => open\r
-);\r
-\r
-\r
-----------------------------------------\r
--- FPGA debug header driver --\r
-----------------------------------------\r
-THE_DBG_CLK_OUT: ODDRXC\r
-port map( \r
- DA => '1',\r
- DB => '0',\r
- CLK => debug_clk,\r
- RST => '0',\r
- Q => dbg_exp(43)\r
-);\r
- \r
-THE_DEBUG_REG_PROC: process( debug_clk )\r
-begin\r
- if( rising_edge(debug_clk) ) then\r
- dbg_exp(42 downto 0) <= debug_qq(42 downto 0);\r
- debug_qq(42 downto 0) <= debug_q(42 downto 0);\r
- debug_q(42 downto 0) <= debug(42 downto 0);\r
- end if;\r
-end process THE_DEBUG_REG_PROC;\r
+end process THE_SYNC_PROC;\r
\r
\r
----------------------------------------\r
fpga_led_pll <= not clk40m_locked;\r
\r
\r
+----------------------------------------\r
+-- FPGA debug header driver --\r
+----------------------------------------\r
+\r
+-- NOT USED, USE EPIC EDITOR INSTEAD!\r
+\r
+------------------------------------------------------------------\r
+-- ORIGINAL STUFF\r
+------------------------------------------------------------------\r
+--debug(42 downto 39) <= (others => '0'); \r
+---- IPU signals\r
+--debug(38 downto 35) <= ipu_number(3 downto 0);\r
+--debug(34) <= ipu_start_readout;\r
+--debug(33) <= ipu_dataready;\r
+--debug(32) <= ipu_read;\r
+--debug(31) <= ipu_readout_finished;\r
+---- FIFO signals\r
+--debug(30) <= fifo_start; -- ped_corr_ctrl -> ipu_stage => data procession starts (unused in ipu_stage)\r
+--debug(29) <= fifo_we(0); -- ped_corr_ctrl -> ipu_stage => transfer processed data into data FIFO (0)\r
+--debug(28) <= fifo_done; -- ped_corr_ctrl -> ipu_stage => store length count data in small FIFOs\r
+--debug(27) <= dhdr_store; -- ped_corr_ctrl -> ipu_stage => store DHDR information for IPU\r
+--debug(26) <= dhdr_buf_full; -- ipu_stage ->\r
+---- EventDataSheet / buffer signals\r
+--debug(25) <= buf_done; -- ped_corr_ctrl -> raw_buf_stage => raw data has been processed\r
+--debug(24) <= buf_tick(0); -- raw_buf_stage -> ped_corr_ctrl => synced tickmarks\r
+--debug(23) <= buf_ready(0); -- raw_buf_stage => adc_last\r
+--debug(22) <= buf_start(0); -- raw_buf_stage -> ped_corr_ctrl => adc_start\r
+--debug(21 downto 17) <= buf_data(0)(34 downto 30);\r
+--debug(16) <= raw_buf_full; -- raw_buf_stage -> apv_trgctrl => at least one raw buffer is full\r
+--debug(15) <= eds_done; -- ped_corr_ctrl -> apv_trgctrl => EDS data has been transfered, release buffer entry\r
+--debug(14) <= eds_avail; -- apv_trgctrl -> ped_corr_ctrl => at least one EDS is available\r
+--debug(13) <= eds_buf_full; -- apv_trgctrl => EDS buffer is full\r
+--debug(12 downto 8) <= eds_buf_level; \r
+---- timing trigger signals\r
+--debug(7) <= timing_trg_found; -- apv_trgctrl -> endpoint => timing trigger has arrived\r
+--debug(6) <= lvl1_trg_received; -- endpoint -> apv_trgctrl => LVL1 trigger packet has arrived\r
+--debug(5) <= lvl1_trg_missing; -- apv_trgctrl -> endpoint => two consecutive timing triggers found\r
+--debug(4) <= lvl1_trg_release; -- apv_trgctrl -> endpoint => release LVL1 busy \r
+--debug(3 downto 0) <= lvl1_trg_number(3 downto 0);\r
+\r
+\r
----------------------------------------\r
-- "unused" pins --\r
----------------------------------------\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
\r
signal rst_pc_sm : std_logic;\r
signal rst_pc_ctr : std_logic;\r
-signal pc_ctr : std_logic_vector(5 downto 0);\r
+signal pc_ctr : unsigned(5 downto 0);\r
signal next_pc_match : std_logic;\r
signal pc_match : std_logic;\r
\r
signal rst_tc_sm : std_logic;\r
signal inc_tc_sm : std_logic;\r
-signal tc_ctr : std_logic_vector(3 downto 0);\r
+signal tc_ctr : unsigned(3 downto 0);\r
signal next_sync_timeout : std_logic;\r
signal sync_timeout : std_logic;\r
\r
signal rst_lc_sm : std_logic;\r
signal inc_lc_sm : std_logic;\r
-signal lc_ctr : std_logic_vector(3 downto 0);\r
+signal lc_ctr : unsigned(3 downto 0);\r
signal next_sync_success : std_logic;\r
signal sync_success : std_logic;\r
\r
signal delay_store : std_logic_vector(7 downto 0);\r
signal store_header : std_logic;\r
\r
-signal apv_channel : std_logic_vector(6 downto 0);\r
+signal apv_channel : unsigned(6 downto 0);\r
signal ce_chnl_ctr : std_logic;\r
signal frame_analog : std_logic;\r
signal set_frame_analog : std_logic;\r
signal next_ce_underflow : std_logic;\r
signal next_ce_overflow : std_logic;\r
\r
-signal sum_ovf : std_logic_vector(7 downto 0);\r
-signal sum_udf : std_logic_vector(7 downto 0);\r
+signal sum_ovf : unsigned(7 downto 0);\r
+signal sum_udf : unsigned(7 downto 0);\r
\r
-signal frame_ctr : std_logic_vector(3 downto 0);\r
+signal frame_ctr : unsigned(3 downto 0);\r
signal comb_ce_frame_ctr : std_logic;\r
\r
signal debug : std_logic_vector(15 downto 0);\r
apv_channel_out(2) <= apv_channel(6);\r
apv_channel_out(1) <= apv_channel(5);\r
apv_channel_out(0) <= apv_channel(4);\r
+-- DO WE NEED A CASTING HERE?\r
\r
apv_raw_out <= adc_raw_two;\r
apv_overflow_out <= apv_overflow;\r
frame_flat_out <= frame_flat;\r
frame_ovf_out <= frame_ovf;\r
frame_udf_out <= frame_udf;\r
-frame_ctr_out <= frame_ctr;\r
+frame_ctr_out <= std_logic_vector(frame_ctr);\r
frame_error_out <= frame_error;\r
frame_row_out <= frame_row;\r
\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number\r
LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
+ EDS_DATA_IN : in std_logic_vector(39 downto 0); -- DEBUG !!!\r
BUF_GOOD_IN : in std_logic; -- process buffer\r
BUF_BAD_IN : in std_logic; -- write only error header\r
BUF_IGNORE_IN : in std_logic; -- do not write anything\r
DO_HEADER_IN : in std_logic;\r
DO_ERROR_IN : in std_logic;\r
SUPPRESS_IN : in std_logic; -- suppress bit\r
+ VERBOSE_IN : in std_logic; -- add debug words for each APV\r
EVT_TYPE_IN : in std_logic_vector(2 downto 0); -- RICH data configuration bits\r
RAW_ADDR_IN : in std_logic_vector(6 downto 0);\r
RAW_DATA_IN : in std_logic_vector(37 downto 0);\r
architecture behavioral of apv_pc_nc_alu is\r
\r
-- normal signals\r
-signal raw_data_q : std_logic_vector(12 downto 0); -- input register\r
-signal ped_data_q : std_logic_vector(12 downto 0); -- input register\r
-signal ped_corr_data_q : std_logic_vector(12 downto 0); -- registered pedestal corrected value\r
-signal ped_corr_data_qq : std_logic_vector(12 downto 0); -- registered pedestal corrected value\r
-signal ped_corr_data_qqq : std_logic_vector(12 downto 0); -- registered pedestal corrected value\r
-signal loc_baseline_q : std_logic_vector(13 downto 0);\r
-signal nc_corr_data_q : std_logic_vector(13 downto 0);\r
-signal nc_corr_data_qq : std_logic_vector(13 downto 0);\r
-signal nc_corr_data_qqq : std_logic_vector(21 downto 0);\r
-signal thr_data_q : std_logic_vector(13 downto 0);\r
+signal raw_data_q : unsigned(12 downto 0); -- input register\r
+signal ped_data_q : unsigned(12 downto 0); -- input register\r
+signal ped_corr_data_q : unsigned(12 downto 0); -- registered pedestal corrected value\r
+signal ped_corr_data_qq : unsigned(12 downto 0); -- registered pedestal corrected value\r
+signal ped_corr_data_qqq : unsigned(12 downto 0); -- registered pedestal corrected value\r
+signal loc_baseline_q : unsigned(13 downto 0);\r
+signal nc_corr_data_q : unsigned(13 downto 0);\r
+signal nc_corr_data_qq : unsigned(13 downto 0);\r
+signal nc_corr_data_qqq : unsigned(21 downto 0);\r
+signal thr_data_q : unsigned(13 downto 0);\r
signal udf_int : std_logic_vector(6 downto 0);\r
signal ovf_int : std_logic_vector(6 downto 0);\r
signal frame_int : std_logic_vector(6 downto 0);\r
signal off_int : std_logic_vector(6 downto 0);\r
signal next_data_we : std_logic;\r
signal data_we : std_logic;\r
-signal adjust_data : std_logic_vector(13 downto 0);\r
+signal adjust_data : unsigned(13 downto 0);\r
\r
+signal thr_pass_comb : std_logic;\r
signal thr_pass : std_logic;\r
\r
-- data steering signals\r
signal toggle : std_logic_vector(6 downto 0);\r
\r
-- Channel counter\r
-signal channel : std_logic_vector(6 downto 0);\r
+signal channel : unsigned(6 downto 0);\r
\r
-signal count : std_logic_vector(9 downto 0);\r
+signal count : unsigned(9 downto 0);\r
\r
signal anydata : std_logic;\r
\r
THE_RAW_INPUT_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
- raw_data_q <= '1' & raw_data_in(11 downto 0);\r
+ raw_data_q <= '1' & unsigned(raw_data_in(11 downto 0));\r
end if;\r
end process THE_RAW_INPUT_PROC;\r
\r
if( (reset_in = '1') or (ped_off = '1') ) then\r
ped_data_q <= (others => '0');\r
else\r
- ped_data_q <= '0' & ped_data_in(11 downto 0);\r
+ ped_data_q <= '0' & unsigned(ped_data_in(11 downto 0));\r
end if;\r
end if;\r
end process THE_PED_INPUT_PROC;\r
thr_data_q(12) <= '0' when (evt_type_in = "111") else '1';\r
\r
-- Threshold comparison\r
-THE_THR_COMP: comp14bit\r
-port map(\r
- DATAA => nc_corr_data_q,\r
- DATAB => thr_data_q,\r
- CLOCK => clk_in,\r
- CLOCKEN => '1',\r
- ACLR => reset_in,\r
- AGEB => thr_pass\r
-);\r
+thr_pass_comb <= '1' when ( nc_corr_data_q >= thr_data_q ) else '0';\r
+THE_THR_COMP: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ thr_pass <= thr_pass_comb;\r
+ end if;\r
+end process THE_THR_COMP;\r
\r
-- in raw modes, we must shift back to "normal" nominal baseline\r
THE_ADJUSTMENT_PROC: process( clk_in )\r
if( rising_edge(clk_in) ) then\r
if( reset_in = '1' ) then\r
nc_corr_data_qqq <= (others => '0');\r
--- nc_corr_data_qq <= (others => '0');\r
thr_data_q(11 downto 0) <= (others => '0');\r
else\r
if ( (do_header_in = '0') and (do_error_in = '0') ) then\r
elsif( (do_header_in = '1') ) then\r
nc_corr_data_qqq(21) <= '1'; -- HEADER\r
nc_corr_data_qqq(20) <= buf_bad_in;\r
- nc_corr_data_qqq(19 downto 16) <= error_in;\r
- nc_corr_data_qqq(15 downto 12) <= max_frames_in;\r
- nc_corr_data_qqq(11 downto 8) <= curr_frame_in;\r
- nc_corr_data_qqq(7 downto 0) <= raw_data_in(25 downto 18);\r
+ nc_corr_data_qqq(19 downto 16) <= unsigned(ERROR_IN);\r
+ nc_corr_data_qqq(15 downto 12) <= unsigned(MAX_FRAMES_IN);\r
+ nc_corr_data_qqq(11 downto 8) <= unsigned(CURR_FRAME_IN);\r
+ nc_corr_data_qqq(7 downto 0) <= unsigned(RAW_DATA_IN(25 downto 18));\r
elsif( (do_error_in = '1') ) then\r
nc_corr_data_qqq(21) <= '1'; -- HEADER\r
nc_corr_data_qqq(20) <= raw_data_in(26); -- error\r
- nc_corr_data_qqq(19 downto 16) <= eds_frm_ctr_in; -- EDS start frame\r
- nc_corr_data_qqq(15 downto 12) <= loc_frm_ctr_in; -- local frame counter value\r
- nc_corr_data_qqq(11 downto 8) <= raw_data_in(17 downto 14); -- frame counter\r
- nc_corr_data_qqq(7 downto 0) <= raw_data_in(25 downto 18); -- row\r
+ nc_corr_data_qqq(19 downto 16) <= unsigned(EDS_DATA_IN(11 downto 8)); -- TRG_RANDOM(3:0)\r
+ nc_corr_data_qqq(15 downto 0) <= unsigned(EDS_DATA_IN(31 downto 16)); -- TRG_TAG\r
+-- nc_corr_data_qqq(19 downto 16) <= unsigned(EDS_FRM_CTR_IN); -- EDS start frame\r
+-- nc_corr_data_qqq(15 downto 12) <= unsigned(LOC_FRM_CTR_IN); -- local frame counter value\r
+-- nc_corr_data_qqq(11 downto 8) <= unsigned(RAW_DATA_IN(17 downto 14)); -- frame counter\r
+-- nc_corr_data_qqq(7 downto 0) <= unsigned(RAW_DATA_IN(25 downto 18)); -- row\r
end if;\r
--- nc_corr_data_qq <= nc_corr_data_q;\r
- thr_data_q(11 downto 0) <= thr_data_in(11 downto 0);\r
+ thr_data_q(11 downto 0) <= unsigned(thr_data_in(11 downto 0));\r
end if;\r
end if;\r
end process THE_NC_DELAY_PROC;\r
((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "110") and (frame_int(5) = '1') and (toggle(5) = '1') and (bad_corr(5) = '0')) or\r
((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "111") and (frame_int(5) = '1') and (toggle(5) = '1') and (bad_corr(5) = '0') and (thr_pass = '1')) or\r
(((buf_good_in = '1') or (buf_bad_in = '1')) and (do_header_in = '1')) or\r
--- ((buf_bad_in = '1') and (do_error_in = '1'))\r
- ((do_error_in = '1'))\r
+ ((buf_bad_in = '1') and (do_error_in = '1')) or\r
+ ((verbose_in = '1') and (do_error_in = '1'))\r
) else '0';\r
\r
-- Channel counter for outgoing data\r
\r
-- output signals (most of them are only needed for simulation!)\r
we_out <= data_we;\r
-count_out <= count;\r
+count_out <= std_logic_vector(count);\r
anydata_out <= anydata;\r
\r
-- Real FIFO input. We use a 2kx27 FIFO, with only 22bit carrying real information.\r
fifo_data_out(24) <= bad_corr(6);\r
fifo_data_out(23) <= ovf_int(6);\r
fifo_data_out(22) <= udf_int(6);\r
-fifo_data_out(21 downto 0) <= nc_corr_data_qqq;\r
+fifo_data_out(21 downto 0) <= std_logic_vector(nc_corr_data_qqq);\r
\r
-- Debug signals\r
--debug(31 downto 16) <= (others => '0');\r
debug(15) <= thr_pass;\r
debug(14) <= '0';\r
-debug(13 downto 0) <= thr_data_q;\r
+debug(13 downto 0) <= std_logic_vector(thr_data_q);\r
\r
dbg_out <= debug;\r
\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
signal adc_last : std_logic;\r
\r
signal ce_wr_pointer : std_logic;\r
-signal wr_pointer : std_logic_vector(3 downto 0);\r
+signal wr_pointer : unsigned(3 downto 0);\r
signal ce_rd_pointer : std_logic;\r
-signal rd_pointer : std_logic_vector(3 downto 0);\r
+signal rd_pointer : unsigned(3 downto 0);\r
\r
signal buf_good_x : std_logic;\r
signal buf_good : std_logic;\r
signal buf_ignore_x : std_logic;\r
signal buf_ignore : std_logic;\r
\r
-signal buf_level : std_logic_vector(4 downto 0);\r
+signal buf_level : unsigned(4 downto 0);\r
signal buf_level_up_x : std_logic;\r
signal buf_level_down_x : std_logic;\r
\r
signal apv_locked : std_logic;\r
\r
-- from old APV_BUFHANDLER block\r
-signal apv_free_ctr : std_logic_vector(4 downto 0);\r
+signal apv_free_ctr : unsigned(4 downto 0);\r
signal apv_free_up : std_logic;\r
signal apv_free_down : std_logic;\r
-signal buf_free_ctr : std_logic_vector(4 downto 0);\r
+signal buf_free_ctr : unsigned(4 downto 0);\r
signal buf_free_up : std_logic;\r
signal buf_free_down : std_logic;\r
\r
-signal sum_apv_buf : std_logic_vector(5 downto 0);\r
-signal sum_apv : std_logic_vector(5 downto 0);\r
-signal sum_buf : std_logic_vector(5 downto 0);\r
-signal trg_limit : std_logic_vector(5 downto 0);\r
+signal sum_apv_buf : unsigned(5 downto 0);\r
+signal sum_apv : unsigned(5 downto 0);\r
+signal sum_buf : unsigned(5 downto 0);\r
+signal trg_limit : unsigned(5 downto 0);\r
\r
signal debug : std_logic_vector(15 downto 0);\r
\r
begin\r
\r
-- Debugging signals\r
-debug <= (others => '0');\r
+--debug <= (others => '0');\r
+\r
+debug(15) <= apv_or_buf_full;\r
+debug(14 downto 10) <= std_logic_vector(buf_level);\r
+debug(9 downto 5) <= std_logic_vector(buf_free_ctr);\r
+debug(4 downto 0) <= std_logic_vector(apv_free_ctr);\r
\r
-- Aliasing of status bits from APV_LOCKER (40MHz domain)\r
apv_adcok_x <= not adc_status_in(7); -- '0' = good ADC, '1' = bad ADC\r
-- Control signals for the data EBRs\r
wr_data_ena <= adc_analog_in;\r
rd_data_ena <= '1';\r
-wr_data_addr <= wr_pointer & adc_channel_in;\r
-rd_data_addr <= rd_pointer & buf_addr_in;\r
+wr_data_addr <= std_logic_vector(wr_pointer) & adc_channel_in;\r
+rd_data_addr <= std_logic_vector(rd_pointer) & buf_addr_in;\r
wr_data_d <= adc_raw_in;\r
\r
-- We have two EBRs to implement a 2kx18 ring buffer\r
-- We use a LUT based DPRAM for the 16x12b status memory\r
THE_FRAME_STATUS_MEM: frame_status_mem\r
port map(\r
- WRADDRESS => wr_pointer,\r
+ WRADDRESS => std_logic_vector(wr_pointer),\r
DATA => adc_frame_in,\r
WRCLOCK => clk_apv_in,\r
WE => ce_wr_pointer, -- we store the frame status with the last ADC word\r
WRCLOCKEN => '1',\r
- RDADDRESS => rd_pointer,\r
+ RDADDRESS => std_logic_vector(rd_pointer),\r
RDCLOCK => buf_clk_in,\r
RDCLOCKEN => '1',\r
RESET => reset_in,\r
-- - a late "FRAME_RCVD" to notify that a requested frame has been transfered\r
-- from APV to the raw buffer.\r
\r
-apv_free_down <= frm_reqd_in;\r
+apv_free_down <= (frm_reqd_in and buf_good); -- 02092010 MB\r
apv_free_up <= adc_last;\r
\r
THE_APV_FREE_COUNTER_PROC: process( buf_clk_in )\r
-- page to the buffer pool again.\r
\r
buf_free_down <= adc_start;\r
-buf_free_up <= buf_done_in;\r
+buf_free_up <= (buf_done_in and buf_good); -- 02092010 MB\r
\r
THE_BUF_FREE_COUNTER_PROC: process( buf_clk_in )\r
begin\r
sum_buf <= '0' & buf_free_ctr;\r
\r
-- Balance the frames requested from APV and already present in raw buffers\r
-THE_APV_BUF_ADDER: adder_6bit\r
-port map( DATAA => sum_apv,\r
- DATAB => sum_buf,\r
- CLOCK => buf_clk_in,\r
- RESET => buf_reset_in,\r
- CLOCKEN => '1',\r
- RESULT => sum_apv_buf\r
- );\r
+THE_APV_BUF_ADDER: process( buf_clk_in )\r
+begin\r
+ if( rising_edge(buf_clk_in) ) then\r
+ sum_apv_buf <= sum_apv + sum_buf;\r
+ end if;\r
+end process THE_APV_BUF_ADDER;\r
\r
-- We have a minimum number of buffer pages to keep:\r
-- this construct makes 16 + (max_trg_num)\r
-trg_limit <= "01" & max_trg_num_in;\r
+trg_limit <= "01" & unsigned(max_trg_num_in);\r
\r
-apv_or_buf_full_x <= '1' when (sum_apv_buf < trg_limit) else '0';\r
+apv_or_buf_full_x <= '1' when ((sum_apv_buf < trg_limit) and (buf_good = '1')) else '0'; -- 02092010 MB\r
\r
THE_SYNC_PROC: process( buf_clk_in )\r
begin\r
------------------------------------------------------------------------------------------\r
------------------------------------------------------------------------------------------\r
\r
-\r
-- Output signals\r
-buf_data_out <= rd_data_d;\r
-buf_start_out <= adc_start;\r
-buf_ready_out <= adc_last;\r
-buf_status_out <= adc_status_qq;\r
-buf_frame_out <= buf_frame;\r
+BUF_DATA_OUT <= rd_data_d;\r
+BUF_START_OUT <= adc_start;\r
+BUF_READY_OUT <= adc_last;\r
+BUF_STATUS_OUT <= adc_status_qq;\r
+BUF_FRAME_OUT <= buf_frame;\r
\r
-buf_good_out <= buf_good;\r
-buf_broken_out <= buf_broken;\r
-buf_ignore_out <= buf_ignore;\r
-buf_level_out <= buf_level;\r
-buf_full_out <= apv_or_buf_full;\r
+BUF_GOOD_OUT <= buf_good;\r
+BUF_BROKEN_OUT <= buf_broken;\r
+BUF_IGNORE_OUT <= buf_ignore;\r
+BUF_LEVEL_OUT <= std_logic_vector(buf_level);\r
+BUF_FULL_OUT <= apv_or_buf_full;\r
\r
-buf_tickmark_out <= buf_tickmark;\r
+BUF_TICKMARK_OUT <= buf_tickmark;\r
\r
-- Debug signals\r
-debug_out <= debug;\r
+DEBUG_OUT <= debug;\r
\r
end behavioral;\r
\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
-- normal signals\r
signal apv_trgstart : std_logic;\r
signal next_apv_trgstart : std_logic;\r
-signal todo_ctr : std_logic_vector(3 downto 0);\r
+signal todo_ctr : unsigned(3 downto 0);\r
signal comb_todo_done : std_logic;\r
-signal delay_ctr : std_logic_vector(3 downto 0);\r
+signal delay_ctr : unsigned(3 downto 0);\r
signal comb_delay_done : std_logic;\r
signal apv_trgsent : std_logic;\r
signal apv_trgdone : std_logic;\r
if ( reset_apv_in = '1' ) then\r
todo_ctr <= (others => '0');\r
elsif( apv_trgstart = '1' ) then\r
- todo_ctr <= apv_trg_todo_in;\r
+ todo_ctr <= unsigned(apv_trg_todo_in);\r
elsif( todo_ctr_ce = '1' ) then\r
todo_ctr <= todo_ctr - 1;\r
end if;\r
if ( reset_apv_in = '1' ) then\r
delay_ctr <= (others => '0');\r
elsif( delay_ctr_ld = '1' ) then\r
- delay_ctr <= apv_trg_delay_in;\r
+ delay_ctr <= unsigned(apv_trg_delay_in);\r
elsif( delay_ctr_ce = '1' ) then\r
delay_ctr <= delay_ctr - 1;\r
end if;\r
apv_trg_out <= apv_trg;\r
apv_trgsent_out <= apv_trgsent;\r
\r
-debug_out(15 downto 12) <= todo_ctr;\r
-debug_out(11 downto 8) <= delay_ctr;\r
+debug_out(15 downto 12) <= std_logic_vector(todo_ctr);\r
+debug_out(11 downto 8) <= std_logic_vector(delay_ctr);\r
debug_out(7) <= delay_ctr_ld;\r
debug_out(6) <= '0';\r
debug_out(5) <= comb_delay_done;\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow\r
TRG_FOUND_OUT : out std_logic;\r
+ TRG_TOO_LONG_OUT : out std_logic; -- only for TRG0 channel\r
SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number\r
-- slow control settings\r
TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event\r
---------------------------------------------------------------------------\r
-- Debug\r
---------------------------------------------------------------------------\r
-debug(63 downto 40) <= (others => '0');\r
+--debug(63 downto 0) <= (others => '0');\r
+debug(63 downto 60) <= eds_data(19 downto 16);\r
+debug(59 downto 56) <= eds_data(7 downto 4);\r
+debug(55) <= trb_missing;\r
+debug(54) <= eds_avail;\r
+debug(53) <= eds_full;\r
+debug(52 downto 48) <= eds_level;\r
+debug(47) <= busy_release;\r
+debug(46) <= '0';\r
+debug(45) <= STILL_BUSY_IN; -- raw_buf_full\r
+debug(44 downto 40) <= bsm(4 downto 0); -- real trigger states\r
debug(39 downto 0) <= test_eds_data;\r
\r
\r
---------------------------------------------------------------------------\r
THE_RESET_SYNC: state_sync\r
port map(\r
- STATE_A_IN => reset_in,\r
- CLK_B_IN => clk_apv_in,\r
+ STATE_A_IN => RESET_IN,\r
+ CLK_B_IN => CLK_APV_IN,\r
RESET_B_IN => '0',\r
STATE_B_OUT => apv_clk_rst\r
);\r
---------------------------------------------------------------------------\r
SC_TRG0_STRECH: pulse_stretch\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- START_IN => trb_trg_in(0),\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ START_IN => TRB_TRG_IN(0),\r
PULSE_OUT => sc_trg_stretch(0),\r
DEBUG_OUT => open\r
);\r
SC_TRG1_STRECH: pulse_stretch\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- START_IN => trb_trg_in(1),\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ START_IN => TRB_TRG_IN(1),\r
PULSE_OUT => sc_trg_stretch(1),\r
DEBUG_OUT => open\r
);\r
SC_TRG2_STRECH: pulse_stretch\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- START_IN => trb_trg_in(2),\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ START_IN => TRB_TRG_IN(2),\r
PULSE_OUT => sc_trg_stretch(2),\r
DEBUG_OUT => open\r
);\r
SC_TRG3_STRECH: pulse_stretch\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- START_IN => trb_trg_in(3),\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ START_IN => TRB_TRG_IN(3),\r
PULSE_OUT => sc_trg_stretch(3),\r
DEBUG_OUT => open\r
);\r
---------------------------------------------------------------------------\r
-- Busy handling\r
---------------------------------------------------------------------------\r
-THE_SYNC_PROC: process( clk_in )\r
+THE_SYNC_PROC: process( CLK_IN )\r
begin\r
- if( rising_edge(clk_in) ) then\r
- busy_release <= not still_busy_in and not eds_full;\r
+ if( rising_edge(CLK_IN) ) then\r
+ busy_release <= not STILL_BUSY_IN and not eds_full;\r
end if;\r
end process THE_SYNC_PROC;\r
\r
---------------------------------------------------------------------------\r
THE_REAL_TRG_HANDLER: real_trg_handler\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- TIME_TRG_IN => time_trg_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ TIME_TRG_IN => TIME_TRG_IN,\r
TRB_TRG_IN => sc_trg_stretch,\r
APV_TRGDONE_IN => apv_trgdone_all,\r
- TRG_3_TODO_IN => trg_3_todo_in,\r
- TRG_2_TODO_IN => trg_2_todo_in,\r
- TRG_1_TODO_IN => trg_1_todo_in,\r
- TRG_0_TODO_IN => trg_0_todo_in,\r
- TRG_SETUP_IN => trg_setup_in,\r
+ TRG_3_TODO_IN => TRG_3_TODO_IN,\r
+ TRG_2_TODO_IN => TRG_2_TODO_IN,\r
+ TRG_1_TODO_IN => TRG_1_TODO_IN,\r
+ TRG_0_TODO_IN => TRG_0_TODO_IN,\r
+ TRG_SETUP_IN => TRG_SETUP_IN,\r
TRG_FOUND_OUT => trg_found,\r
- SECTOR_IN => sector_in,\r
- TRB_TTAG_IN => trb_ttag_in,\r
- TRB_TRND_IN => trb_trnd_in,\r
- TRB_TTYPE_IN => trb_ttype_in,\r
- TRB_TINFO_IN => trb_tinfo_in,\r
- TRB_TRGRCVD_IN => trb_trgrcvd_in,\r
+ TRG_TOO_LONG_OUT => TRG_TOO_LONG_OUT,\r
+ SECTOR_IN => SECTOR_IN,\r
+ TRB_TTAG_IN => TRB_TTAG_IN,\r
+ TRB_TRND_IN => TRB_TRND_IN,\r
+ TRB_TTYPE_IN => TRB_TTYPE_IN,\r
+ TRB_TINFO_IN => TRB_TINFO_IN,\r
+ TRB_TRGRCVD_IN => TRB_TRGRCVD_IN,\r
TRB_MISSING_OUT => trb_missing,\r
BUSY_RELEASE_IN => busy_release,\r
LVL1_COUNTER_OUT => trb_counter,\r
- LVL1_COUNTER_IN => trb_counter_in,\r
- LVL1_LD_COUNTER_IN => trb_ld_counter_in,\r
+ LVL1_COUNTER_IN => TRB_COUNTER_IN,\r
+ LVL1_LD_COUNTER_IN => TRB_LD_COUNTER_IN,\r
APV_TRGSEL_OUT => apv_trgsel,\r
APV_TRGSTART_OUT => apv_trgstart,\r
EDS_DATA_OUT => atc_eds_data,\r
-- mind the delay in this block!\r
THE_MAX_TRG: max_data\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- TODO_3_IN => trg_3_todo_in,\r
- TODO_2_IN => trg_2_todo_in,\r
- TODO_1_IN => trg_1_todo_in,\r
- TODO_0_IN => trg_0_todo_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ TODO_3_IN => TRG_3_TODO_IN,\r
+ TODO_2_IN => TRG_2_TODO_IN,\r
+ TODO_1_IN => TRG_1_TODO_IN,\r
+ TODO_0_IN => TRG_0_TODO_IN,\r
TODO_MAX_OUT => maximum_trg,\r
DEBUG_OUT => open\r
);\r
\r
-- Only for storing last EDS for debugging!\r
-THE_TEST_EDS_DATA_PROC: process( clk_in )\r
+THE_TEST_EDS_DATA_PROC: process( CLK_IN )\r
begin\r
- if( rising_edge(clk_in) ) then\r
+ if( rising_edge(CLK_IN) ) then\r
if( atc_eds_we = '1' ) then\r
test_eds_data <= atc_eds_data;\r
end if;\r
---------------------------------------------------------------------------\r
THE_EDS_BUF: eds_buf\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
EDS_DATA_IN => atc_eds_data, -- data from trigger handler\r
EDS_WE_IN => atc_eds_we, -- write enable from trigger handler\r
- EDS_DONE_IN => eds_done_in, -- release current EDS page\r
+ EDS_DONE_IN => EDS_DONE_IN, -- release current EDS page\r
EDS_DATA_OUT => eds_data, -- current EDS data out\r
EDS_AVAILABLE_OUT => eds_avail, -- current EDS is valid\r
BUF_FULL_OUT => eds_full, -- EDS buffer is full\r
---------------------------------------------------------------------------\r
THE_APV_TRG_HANDLER_3: apv_trg_handler\r
port map(\r
- CLK_APV_IN => clk_apv_in,\r
+ CLK_APV_IN => CLK_APV_IN,\r
RESET_APV_IN => apv_clk_rst,\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
APV_TRGSTART_IN => apv_trgstart,\r
APV_TRGSEL_IN => apv_trgsel(3),\r
- APV_TRG_TODO_IN => trg_3_todo_in,\r
- APV_TRG_DELAY_IN => trg_3_delay_in,\r
+ APV_TRG_TODO_IN => TRG_3_TODO_IN,\r
+ APV_TRG_DELAY_IN => TRG_3_DELAY_IN,\r
APV_TRGDONE_OUT => apv_trgdone(3),\r
APV_TRG_OUT => apv_trg(3),\r
APV_TRGSENT_OUT => apv_trgsent(3),\r
---------------------------------------------------------------------------\r
THE_APV_TRG_HANDLER_2: apv_trg_handler\r
port map(\r
- CLK_APV_IN => clk_apv_in,\r
+ CLK_APV_IN => CLK_APV_IN,\r
RESET_APV_IN => apv_clk_rst,\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
APV_TRGSTART_IN => apv_trgstart,\r
APV_TRGSEL_IN => apv_trgsel(2),\r
- APV_TRG_TODO_IN => trg_2_todo_in,\r
- APV_TRG_DELAY_IN => trg_2_delay_in,\r
+ APV_TRG_TODO_IN => TRG_2_TODO_IN,\r
+ APV_TRG_DELAY_IN => TRG_2_DELAY_IN,\r
APV_TRGDONE_OUT => apv_trgdone(2),\r
APV_TRG_OUT => apv_trg(2),\r
APV_TRGSENT_OUT => apv_trgsent(2),\r
---------------------------------------------------------------------------\r
THE_APV_TRG_HANDLER_1: apv_trg_handler\r
port map(\r
- CLK_APV_IN => clk_apv_in,\r
+ CLK_APV_IN => CLK_APV_IN,\r
RESET_APV_IN => apv_clk_rst,\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
APV_TRGSTART_IN => apv_trgstart,\r
APV_TRGSEL_IN => apv_trgsel(1),\r
- APV_TRG_TODO_IN => trg_1_todo_in,\r
- APV_TRG_DELAY_IN => trg_1_delay_in,\r
+ APV_TRG_TODO_IN => TRG_1_TODO_IN,\r
+ APV_TRG_DELAY_IN => TRG_1_DELAY_IN,\r
APV_TRGDONE_OUT => apv_trgdone(1),\r
APV_TRG_OUT => apv_trg(1),\r
APV_TRGSENT_OUT => apv_trgsent(1),\r
---------------------------------------------------------------------------\r
THE_APV_TRG_HANDLER_0: apv_trg_handler\r
port map(\r
- CLK_APV_IN => clk_apv_in,\r
+ CLK_APV_IN => CLK_APV_IN,\r
RESET_APV_IN => apv_clk_rst,\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
APV_TRGSTART_IN => apv_trgstart,\r
APV_TRGSEL_IN => apv_trgsel(0),\r
- APV_TRG_TODO_IN => trg_0_todo_in,\r
- APV_TRG_DELAY_IN => trg_0_delay_in,\r
+ APV_TRG_TODO_IN => TRG_0_TODO_IN,\r
+ APV_TRG_DELAY_IN => TRG_0_DELAY_IN,\r
APV_TRGDONE_OUT => apv_trgdone(0),\r
APV_TRG_OUT => apv_trg(0),\r
APV_TRGSENT_OUT => apv_trgsent(0),\r
---------------------------------------------------------------------------\r
THE_APV_SYNC_HANDLER: apv_sync_handler\r
port map(\r
- CLK_APV_IN => clk_apv_in,\r
+ CLK_APV_IN => CLK_APV_IN,\r
RESET_APV_IN => apv_clk_rst,\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- APV_TRGSTART_IN => sync_trg_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ APV_TRGSTART_IN => SYNC_TRG_IN,\r
APV_TRGSEL_IN => '1',\r
APV_TRGDONE_OUT => open,\r
APV_TRG_OUT => apv_sync_signal,\r
next_apv_trgdone_all <= apv_trgdone(3) or apv_trgdone(2) or apv_trgdone(1) or apv_trgdone(0);\r
next_apv_trgsent_all <= apv_trgsent(3) or apv_trgsent(2) or apv_trgsent(1) or apv_trgsent(0);\r
\r
-THE_SYNC_AVP_HOUSEKEEPING_PROC: process( clk_in )\r
+THE_SYNC_AVP_HOUSEKEEPING_PROC: process( CLK_IN )\r
begin\r
- if( rising_edge(clk_in) ) then\r
+ if( rising_edge(CLK_IN) ) then\r
apv_trgdone_all <= next_apv_trgdone_all;\r
apv_trgsent_all <= next_apv_trgsent_all;\r
end if;\r
-- we combine all four trigger sources, and the sync source\r
next_apv_trg_all <= apv_trg(3) or apv_trg(2) or apv_trg(1) or apv_trg(0) or apv_sync_signal;\r
\r
-THE_SYNC_AVP_TRG_PROC: process( clk_apv_in )\r
+THE_SYNC_AVP_TRG_PROC: process( CLK_APV_IN )\r
begin\r
- if( rising_edge(clk_apv_in) ) then\r
+ if( rising_edge(CLK_APV_IN) ) then\r
apv_trg_all <= next_apv_trg_all;\r
end if;\r
end process THE_SYNC_AVP_TRG_PROC;\r
---------------------------------------------------------------------------\r
-- output signals\r
---------------------------------------------------------------------------\r
-eds_data_out <= eds_data;\r
-eds_avail_out <= eds_avail;\r
-eds_full_out <= eds_full;\r
-eds_level_out <= eds_level;\r
-frm_reqd_out <= apv_trgsent_all;\r
-trb_release_out <= trb_release;\r
-trb_missing_out <= trb_missing;\r
-trb_counter_out <= trb_counter;\r
+EDS_DATA_OUT <= eds_data;\r
+EDS_AVAIL_OUT <= eds_avail;\r
+EDS_FULL_OUT <= eds_full;\r
+EDS_LEVEL_OUT <= eds_level;\r
+FRM_REQD_OUT <= apv_trgsent_all;\r
+TRB_RELEASE_OUT <= trb_release;\r
+TRB_MISSING_OUT <= trb_missing;\r
+TRB_COUNTER_OUT <= trb_counter;\r
\r
-apv_trg_out <= apv_trg_all;\r
-apv_sync_out <= apv_sync;\r
+APV_TRG_OUT <= apv_trg_all;\r
+APV_SYNC_OUT <= apv_sync;\r
\r
-trg_found_out <= trg_found;\r
-trg_max_out <= maximum_trg;\r
+TRG_FOUND_OUT <= trg_found;\r
+TRG_MAX_OUT <= maximum_trg;\r
\r
---------------------------------------------------------------------------\r
-- Debug signals\r
---------------------------------------------------------------------------\r
-debug_out <= debug;\r
+DEBUG_OUT <= debug;\r
\r
end behavioral;\r
\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
signal bsm_x : std_logic_vector(7 downto 0);\r
signal debug_x : std_logic_vector(15 downto 0);\r
\r
-signal buf_lvl : std_logic_vector(4 downto 0);\r
+signal buf_lvl : unsigned(4 downto 0);\r
signal buf_good : std_logic;\r
signal buf_broken : std_logic;\r
signal buf_ignore : std_logic;\r
signal next_ready : std_logic;\r
signal ready : std_logic;\r
\r
-signal frames_needed : std_logic_vector(4 downto 0);\r
+signal frames_needed : unsigned(4 downto 0);\r
\r
signal next_frames_avail : std_logic;\r
signal frames_avail : std_logic;\r
\r
-signal toc_ctr : std_logic_vector(3 downto 0);\r
+signal toc_ctr : unsigned(3 downto 0);\r
signal next_toc_rst : std_logic;\r
signal toc_rst : std_logic;\r
signal next_toc_ce : std_logic;\r
buf_good <= buf_lvl_in(7);\r
buf_broken <= buf_lvl_in(6);\r
buf_ignore <= buf_lvl_in(5);\r
-buf_lvl <= buf_lvl_in(4 downto 0);\r
+buf_lvl <= unsigned(buf_lvl_in(4 downto 0));\r
\r
-- Timeout counter\r
THE_TIMEOUT_COUNTER_PROC: process( clk_in )\r
next_toc_hit <= '1' when (toc_ctr = x"f") else '0';\r
\r
-- Check for the number of available frames\r
-frames_needed <= '0' & frames_reqd_in;\r
+frames_needed <= '0' & unsigned(frames_reqd_in);\r
next_frames_avail <= '1' when ( buf_lvl >= frames_needed ) else '0';\r
\r
-- Synchronization process\r
debug_x(6) <= gooddata;\r
debug_x(5) <= baddata;\r
debug_x(4) <= ready;\r
-debug_x(3 downto 0) <= toc_ctr;\r
+debug_x(3 downto 0) <= std_logic_vector(toc_ctr);\r
\r
dbg_out <= debug_x;\r
bsm_out <= bsm_x;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+\r
+entity dbg_reg is\r
+generic(\r
+ WIDTH : integer := 1\r
+);\r
+port(\r
+ DEBUG_IN : in std_logic_vector(WIDTH-1 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(WIDTH-1 downto 0)\r
+);\r
+end entity dbg_reg;\r
+\r
+architecture behavioral of dbg_reg is\r
+\r
+attribute syn_hier : string;\r
+attribute syn_hier of behavioral : architecture is "flatten, firm";\r
+\r
+begin\r
+\r
+-- Yes. A strange entity. But VHDL/Synplify are too stupid to make it easier.\r
+\r
+debug_out <= debug_in;\r
+\r
+end behavioral;\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
\r
-- Signals for controlling the EDS buffer memory\r
signal eds_data : std_logic_vector(39 downto 0);\r
-signal eds_rd_addr : std_logic_vector(3 downto 0);\r
-signal eds_wr_addr : std_logic_vector(3 downto 0);\r
+signal eds_rd_addr : unsigned(3 downto 0);\r
+signal eds_wr_addr : unsigned(3 downto 0);\r
signal eds_wr : std_logic;\r
signal eds_rd : std_logic;\r
-signal eds_free_ctr : std_logic_vector(4 downto 0); -- fill level counter\r
+signal eds_free_ctr : unsigned(4 downto 0); -- fill level counter\r
signal eds_free_up : std_logic;\r
signal eds_free_down : std_logic;\r
signal eds_available_x : std_logic;\r
-- A 16x40b DPRAM is used for buffering the EventDataSheets (EDS)\r
THE_EDS_BUFFER: eds_buffer_dpram\r
port map(\r
- WRADDRESS => eds_wr_addr,\r
+ WRADDRESS => std_logic_vector(eds_wr_addr),\r
DATA => eds_data_in,\r
WRCLOCK => clk_in,\r
WE => eds_we_in,\r
WRCLOCKEN => '1',\r
- RDADDRESS => eds_rd_addr,\r
+ RDADDRESS => std_logic_vector(eds_rd_addr),\r
RDCLOCK => clk_in,\r
RDCLOCKEN => '1',\r
RESET => reset_in,\r
Q => eds_data\r
);\r
\r
--- Are there any EDS to work on?\r
---eds_available_x <= '1' when (eds_wr_addr /= eds_rd_addr) else '0';\r
--- epic fail: cut'n'paste error from dhdr_buf.vhd\r
-\r
-- Debug signals\r
debug(15 downto 0) <= (others => '0');\r
\r
eds_data_out <= eds_data;\r
eds_available_out <= eds_available;\r
buf_full_out <= eds_full;\r
-buf_level_out <= eds_free_ctr;\r
+buf_level_out <= std_logic_vector(eds_free_ctr);\r
debug_out <= debug;\r
\r
end behavioral;\r
VendorName=Lattice Semiconductor Corporation\r
CoreType=LPM\r
CoreStatus=Demo\r
-CoreName=Adder\r
-CoreRevision=3.1\r
-ModuleName=adder_16bit\r
+CoreName=FIFO\r
+CoreRevision=4.8\r
+ModuleName=fifo_1kx18\r
SourceFormat=VHDL\r
ParameterFileVersion=1.0\r
-Date=03/03/2009\r
-Time=10:27:46\r
+Date=04/29/2010\r
+Time=14:49:48\r
\r
[Parameters]\r
Verilog=0\r
Expression=BusA(0 to 7)\r
Order=Big Endian [MSB:LSB]\r
IO=0\r
-InputWidth=16\r
-Representation=Unsigned\r
-UseCIport=0\r
-COport=None\r
-OutReg=1\r
-Complex=0\r
-Stage=0\r
+FIFOImp=EBR Based\r
+Depth=1024\r
+Width=18\r
+regout=0\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=1\r
+PfMode=Static - Single Threshold\r
+PfAssert=1020\r
+PfDeassert=506\r
+RDataCount=1\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 1024 -width 18 -depth 1024 -no_enable -pe -1 -pf 1020 -fill -e
+
+-- Thu Apr 29 14:49:48 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity fifo_1kx18 is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(17 downto 0);
+ WCNT: out std_logic_vector(10 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_1kx18;
+
+architecture Structure of fifo_1kx18 is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw_inv: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal co5: std_logic;
+ signal co4: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal co4_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal co0_2: std_logic;
+ signal co1_2: std_logic;
+ signal co2_2: std_logic;
+ signal co3_2: std_logic;
+ signal wren_i: std_logic;
+ signal co4_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal co5_1: std_logic;
+ signal wcount_10: std_logic;
+ signal co4_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal ircount_10: std_logic;
+ signal co5_2: std_logic;
+ signal rcount_10: std_logic;
+ signal co4_4: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal fcnt_en_inv_inv: std_logic;
+ signal cnt_con: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal cnt_con_inv: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_5: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_5: std_logic;
+ signal scuba_vhi: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_5: std_logic;
+ signal fcount_10: std_logic;
+ signal af_d: std_logic;
+ signal af_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_1kx18.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b000";
+ attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000";
+ attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_0_0 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_0_0_0 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "18";
+ attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "18";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t4: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_8: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t3: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_7: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t2: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t1: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_6: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_5: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t0: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_4: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ INV_3: INV
+ port map (A=>fcnt_en, Z=>fcnt_en_inv);
+
+ INV_2: INV
+ port map (A=>cnt_con, Z=>cnt_con_inv);
+
+ INV_1: INV
+ port map (A=>r_nw, Z=>r_nw_inv);
+
+ INV_0: INV
+ port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv);
+
+ pdp_ram_0_0_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wcount_0,
+ ADA5=>wcount_1, ADA6=>wcount_2, ADA7=>wcount_3,
+ ADA8=>wcount_4, ADA9=>wcount_5, ADA10=>wcount_6,
+ ADA11=>wcount_7, ADA12=>wcount_8, ADA13=>wcount_9,
+ CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>scuba_vlo, ADB4=>rcount_0, ADB5=>rcount_1,
+ ADB6=>rcount_2, ADB7=>rcount_3, ADB8=>rcount_4,
+ ADB9=>rcount_5, ADB10=>rcount_6, ADB11=>rcount_7,
+ ADB12=>rcount_8, ADB13=>rcount_9, CEB=>rden_i, CLKB=>Clock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2),
+ DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7),
+ DOB8=>Q(8), DOB9=>Q(9), DOB10=>Q(10), DOB11=>Q(11),
+ DOB12=>Q(12), DOB13=>Q(13), DOB14=>Q(14), DOB15=>Q(15),
+ DOB16=>Q(16), DOB17=>Q(17));
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_24: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_23: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_0);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_0);
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+
+ bdcnt_bctr_5: CB2
+ port map (CI=>co4, PC0=>fcount_10, PC1=>scuba_vlo, CON=>cnt_con,
+ CO=>co5, NC0=>ifcount_10, NC1=>open);
+
+ e_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ S1=>open);
+
+ e_cmp_0: ALEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ CI=>cmp_ci, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+ e_cmp_5: ALEB2
+ port map (A0=>fcount_10, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ S1=>open);
+
+ g_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ S1=>open);
+
+ g_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ CI=>cmp_ci_1, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
+ CI=>co3_2, GE=>co4_2);
+
+ g_cmp_5: AGEB2
+ port map (A0=>fcount_10, A1=>scuba_vlo, B0=>wren_i_inv,
+ B1=>scuba_vlo, CI=>co4_2, GE=>cmp_ge_d1_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ S1=>open);
+
+ w_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ S1=>open);
+
+ w_ctr_0: CU2
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_ctr_5: CU2
+ port map (CI=>co4_3, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5_1,
+ NC0=>iwcount_10, NC1=>open);
+
+ r_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ S1=>open);
+
+ r_ctr_0: CU2
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ r_ctr_5: CU2
+ port map (CI=>co4_4, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_2,
+ NC0=>ircount_10, NC1=>open);
+
+ af_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open,
+ S1=>open);
+
+ af_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv,
+ B1=>cnt_con, CI=>cmp_ci_2, GE=>co0_5);
+
+ af_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con_inv,
+ B1=>scuba_vhi, CI=>co0_5, GE=>co1_5);
+
+ af_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>co1_5, GE=>co2_5);
+
+ af_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>co2_5, GE=>co3_5);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ af_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>co3_5, GE=>co4_5);
+
+ af_cmp_5: AGEB2
+ port map (A0=>fcount_10, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co4_5, GE=>af_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a2: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ WCNT(10) <= fcount_10;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of fifo_1kx18 is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:ALEB2 use entity ecp2m.ALEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:CB2 use entity ecp2m.CB2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+-- Missing: FIFO buffer handling, full / empty checks\r
+\r
+entity ipu_fifo_stage is\r
+port(\r
+ CLK_IN : in std_logic; -- 100MHz local clock\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ IPU_RESET_IN : in std_logic; -- requested by TRBnet standard\r
+ -- Slow control signals\r
+ SECTOR_IN : in std_logic_vector(2 downto 0);\r
+ MODULE_IN : in std_logic_vector(2 downto 0);\r
+ -- IPU channel connections\r
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
+ IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
+ IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
+ IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
+ IPU_READ_IN : in std_logic; -- read strobe, low every second cycle\r
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
+ IPU_LAST_NUM_OUT : out std_logic_vector(31 downto 0); -- last number received / readout\r
+ LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter\r
+ -- DHDR buffer input\r
+ DHDR_DATA_IN : in std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_IN : in std_logic_vector(15 downto 0);\r
+ DHDR_STORE_IN : in std_logic;\r
+ DHDR_BUF_FULL_OUT : out std_logic;\r
+ -- processed data input\r
+ FIFO_START_IN : in std_logic;\r
+ FIFO_SPACE_REQ_IN : in std_logic_vector(11 downto 0);\r
+ FIFO_0_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_WE_IN : in std_logic_vector(15 downto 0);\r
+ FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs\r
+ -- data buffer status\r
+ FIFO_0_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_1_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_2_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_3_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_4_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_5_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_6_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_7_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_8_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_9_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_10_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_11_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_12_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_13_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_14_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_15_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ IPU_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ RELEASE_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end;\r
+\r
+architecture behavioral of ipu_fifo_stage is\r
+\r
+-- Placer Directives\r
+attribute HGROUP : string;\r
+-- for whole architecture\r
+attribute HGROUP of behavioral : architecture is "IPU_FIFO_STAGE_group";\r
+\r
+-- state machine definitions\r
+type STATES is (SLEEP,RDLF,GETFD,DELH,WHDR,GETD,WAITD,WAITDL,DEL0,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- signals\r
+signal debug : std_logic_vector(63 downto 0);\r
+signal bsm_x : std_logic_vector(7 downto 0);\r
+signal next_trgnum_match : std_logic;\r
+signal trgnum_match : std_logic;\r
+\r
+signal dhdr_fifo_in_int : std_logic_vector(47 downto 0);\r
+signal dhdr_fifo_out_int : std_logic_vector(47 downto 0);\r
+signal dhdr_avail : std_logic;\r
+signal next_todo_list : std_logic_vector(15 downto 0);\r
+signal todo_list : std_logic_vector(15 downto 0);\r
+signal next_fifo_sel : std_logic_vector(4 downto 0);\r
+signal fifo_sel : std_logic_vector(4 downto 0);\r
+signal next_sel_fifo : std_logic_vector(15 downto 0);\r
+signal sel_fifo : std_logic_vector(15 downto 0);\r
+\r
+signal comb_rd_dfifo : std_logic_vector(15 downto 0);\r
+signal comb_st_data : std_logic_vector(15 downto 0);\r
+signal comb_ack_todo : std_logic;\r
+\r
+signal ipu_out_data : std_logic_vector(31 downto 0);\r
+\r
+-- state machine signals\r
+signal next_rd_lfifo : std_logic;\r
+signal rd_lfifo : std_logic; -- read current LENGTH_FIFO information (as well as LockAtMe bit)\r
+signal next_dataready : std_logic;\r
+signal dataready : std_logic; -- data word is available\r
+signal next_set_hdr : std_logic;\r
+signal set_hdr : std_logic; -- store DHDR in output register\r
+signal next_set_data : std_logic;\r
+signal set_data : std_logic; -- store DATA from current DATA FIFO in output register\r
+signal next_ld_todo : std_logic;\r
+signal ld_todo : std_logic; -- load initial TODO list\r
+signal next_ack_todo : std_logic;\r
+signal ack_todo : std_logic; -- remove current entry from TODO list\r
+signal next_finished : std_logic;\r
+signal finished : std_logic; -- readout is finished\r
+signal next_preload : std_logic;\r
+signal preload : std_logic; -- read first data word from DATA FIFOs\r
+\r
+-- generate needs arrays...\r
+type fifo_data_t is array (0 to 15) of std_logic_vector(26 downto 0);\r
+signal fifo_in_data : fifo_data_t;\r
+signal fifo_out_data : fifo_data_t;\r
+type fifo_count_t is array (0 to 15) of std_logic_vector(10 downto 0);\r
+signal fifo_in_count : fifo_count_t;\r
+type fifo_todo_t is array (0 to 15) of unsigned(9 downto 0);\r
+signal fifo_todo : fifo_todo_t;\r
+type fifo_ldata_t is array (0 to 15) of std_logic_vector(10 downto 0);\r
+signal fifo_ldata : fifo_ldata_t;\r
+type fifo_cnt_t is array (0 to 15) of unsigned(11 downto 0);\r
+signal fifo_data_free_x : fifo_cnt_t;\r
+signal fifo_data_free : fifo_cnt_t;\r
+type fifo_wcnt_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
+signal fifo_wcnt : fifo_wcnt_t;\r
+type fifo_lunused_t is array (0 to 15) of std_logic_vector(6 downto 0);\r
+signal fifo_lunused : fifo_lunused_t;\r
+type fifo_status_t is array (0 to 15) of std_logic_vector(31 downto 0);\r
+signal fifo_status : fifo_status_t;\r
+\r
+signal ipu_status : std_logic_vector(31 downto 0);\r
+signal release_status : std_logic_vector(31 downto 0);\r
+\r
+signal dfifo_available_x : std_logic_vector(15 downto 0);\r
+signal dfifo_available : std_logic_vector(15 downto 0);\r
+signal dfifo_empty : std_logic_vector(15 downto 0);\r
+signal dfifo_full : std_logic_vector(15 downto 0);\r
+\r
+signal lfifo_empty : std_logic_vector(15 downto 0);\r
+signal lfifo_almostfull : std_logic_vector(15 downto 0);\r
+signal lfifo_full : std_logic_vector(15 downto 0);\r
+\r
+signal next_fifo_done : std_logic_vector(15 downto 0);\r
+signal fifo_done : std_logic_vector(15 downto 0);\r
+signal next_fifo_last : std_logic;\r
+signal fifo_last : std_logic;\r
+\r
+signal my_trg_number : std_logic_vector(31 downto 0); -- just for checking!\r
+\r
+signal old_apv_num : std_logic_vector(3 downto 0);\r
+signal new_apv_num : std_logic_vector(3 downto 0);\r
+\r
+signal cyclectr : unsigned(15 downto 0); -- cycle counter\r
+\r
+signal next_dhdr_buf_full : std_logic;\r
+signal dhdr_buf_full : std_logic;\r
+\r
+signal reset_all : std_logic;\r
+\r
+-- Jan Michel's status bits (faked)\r
+signal status_bits : std_logic_vector(3 downto 0);\r
+\r
+\r
+begin\r
+\r
+---------------------------------------------------------------------------\r
+-- Combine syncronous resets\r
+---------------------------------------------------------------------------\r
+reset_all <= RESET_IN or IPU_RESET_IN;\r
+\r
+---------------------------------------------------------------------------\r
+-- Statemachine\r
+---------------------------------------------------------------------------\r
+\r
+-- state registers\r
+STATE_MEM: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( reset_all = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ rd_lfifo <= '0';\r
+ dataready <= '0';\r
+ set_hdr <= '0';\r
+ set_data <= '0';\r
+ ld_todo <= '0';\r
+ ack_todo <= '0';\r
+ preload <= '0';\r
+ finished <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ rd_lfifo <= next_rd_lfifo;\r
+ dataready <= next_dataready;\r
+ set_hdr <= next_set_hdr;\r
+ set_data <= next_set_data;\r
+ ld_todo <= next_ld_todo;\r
+ ack_todo <= next_ack_todo;\r
+ preload <= next_preload;\r
+ finished <= next_finished;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- state transitions\r
+STATE_TRANSFORM: process( CURRENT_STATE, dhdr_avail, IPU_START_READOUT_IN, IPU_READ_IN, fifo_last, fifo_sel(4) )\r
+begin\r
+ NEXT_STATE <= SLEEP; -- avoid latches\r
+ next_rd_lfifo <= '0';\r
+ next_dataready <= '0';\r
+ next_set_hdr <= '0';\r
+ next_set_data <= '0';\r
+ next_ld_todo <= '0';\r
+ next_ack_todo <= '0';\r
+ next_preload <= '0';\r
+ next_finished <= '0';\r
+ \r
+ case CURRENT_STATE is\r
+ when SLEEP => if( (dhdr_avail = '1') and (IPU_START_READOUT_IN = '1') ) then\r
+ NEXT_STATE <= RDLF;\r
+ next_rd_lfifo <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RDLF => NEXT_STATE <= GETFD;\r
+ next_set_hdr <= '1';\r
+ next_ld_todo <= '1';\r
+ when GETFD => NEXT_STATE <= DELH;\r
+ next_preload <= '1';\r
+ when DELH => NEXT_STATE <= WHDR;\r
+ next_dataready <= '1';\r
+ when WHDR => if ( (IPU_READ_IN = '1') and (fifo_sel(4) = '0') ) then\r
+ NEXT_STATE <= GETD; -- there are datawords to send\r
+ next_set_data <= '1';\r
+ next_ack_todo <= '1';\r
+ elsif( (IPU_READ_IN = '1') and (fifo_sel(4) = '1') ) then\r
+ NEXT_STATE <= DONE; -- only DHDR, no data words\r
+ next_finished <= '1';\r
+ else\r
+ NEXT_STATE <= WHDR;\r
+ next_dataready <= '1';\r
+ end if;\r
+ when GETD => if( fifo_last = '1' ) then\r
+ NEXT_STATE <= DEL0;\r
+ else\r
+ NEXT_STATE <= WAITD;\r
+ next_dataready <= '1';\r
+ end if;\r
+ when WAITD => if( ipu_read_in = '1' ) then\r
+ NEXT_STATE <= GETD;\r
+ next_set_data <= '1';\r
+ else\r
+ NEXT_STATE <= WAITD;\r
+ next_dataready <= '1';\r
+ end if;\r
+ when DEL0 => NEXT_STATE <= WAITDL;\r
+ next_dataready <= '1';\r
+ when WAITDL => if ( (IPU_READ_IN = '1') and (fifo_sel(4) = '0') ) then\r
+ NEXT_STATE <= GETD;\r
+ next_set_data <= '1';\r
+ next_ack_todo <= '1';\r
+ elsif( (IPU_READ_IN = '1') and (fifo_sel(4) = '1') ) then\r
+ NEXT_STATE <= DONE;\r
+ next_finished <= '1';\r
+ else\r
+ NEXT_STATE <= WAITDL;\r
+ next_dataready <= '1';\r
+ end if;\r
+ when DONE => if( IPU_START_READOUT_IN = '0' ) then\r
+ NEXT_STATE <= SLEEP;\r
+ else\r
+ NEXT_STATE <= DONE;\r
+ end if;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process STATE_TRANSFORM;\r
+\r
+-- Handshaking to IPU data channel\r
+IPU_DATAREADY_OUT <= dataready;\r
+IPU_READOUT_FINISHED_OUT <= finished;\r
+\r
+-- length information can be simply copied\r
+IPU_LENGTH_OUT <= dhdr_fifo_out_int(47 downto 32);\r
+\r
+-- IPU error pattern\r
+IPU_ERROR_PATTERN_OUT(31 downto 24) <= (others => '0');\r
+IPU_ERROR_PATTERN_OUT(23) <= '0'; -- "single broken event"\r
+IPU_ERROR_PATTERN_OUT(23) <= '0'; -- "severe problem"\r
+IPU_ERROR_PATTERN_OUT(21) <= '0'; -- "partially not found"\r
+IPU_ERROR_PATTERN_OUT(20) <= not trgnum_match; -- "not found"\r
+IPU_ERROR_PATTERN_OUT(19 downto 0) <= (others => '0');\r
+\r
+-- state decoding (ONLY FOR DEBUGGING!)\r
+STATE_DECODE: process( CURRENT_STATE )\r
+begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm_x <= x"00";\r
+ status_bits <= x"0";\r
+ when RDLF => bsm_x <= x"11"; --x"01";\r
+ status_bits <= x"1";\r
+ when GETFD => bsm_x <= x"22"; --x"02";\r
+ status_bits <= x"2";\r
+ when DELH => bsm_x <= x"33"; --x"03";\r
+ status_bits <= x"3";\r
+ when WHDR => bsm_x <= x"f4"; --x"04";\r
+ status_bits <= x"3";\r
+ when GETD => bsm_x <= x"e5"; --x"05";\r
+ status_bits <= x"4";\r
+ when WAITD => bsm_x <= x"d6"; --x"06";\r
+ status_bits <= x"4";\r
+ when WAITDL => bsm_x <= x"c7"; --x"07";\r
+ status_bits <= x"4";\r
+ when DEL0 => bsm_x <= x"b8"; --x"08";\r
+ status_bits <= x"4";\r
+ when DONE => bsm_x <= x"a9"; --x"09";\r
+ status_bits <= x"5";\r
+ when others => bsm_x <= x"ff";\r
+ status_bits <= x"f";\r
+ end case;\r
+end process STATE_DECODE;\r
+\r
+---------------------------------------------------------------------------\r
+-- Aliasing the data streams\r
+---------------------------------------------------------------------------\r
+fifo_in_data(0) <= FIFO_0_DATA_IN(26 downto 0); fifo_in_count(0) <= FIFO_0_DATA_IN(37 downto 27);\r
+fifo_in_data(1) <= FIFO_1_DATA_IN(26 downto 0); fifo_in_count(1) <= FIFO_1_DATA_IN(37 downto 27);\r
+fifo_in_data(2) <= FIFO_2_DATA_IN(26 downto 0); fifo_in_count(2) <= FIFO_2_DATA_IN(37 downto 27);\r
+fifo_in_data(3) <= FIFO_3_DATA_IN(26 downto 0); fifo_in_count(3) <= FIFO_3_DATA_IN(37 downto 27);\r
+fifo_in_data(4) <= FIFO_4_DATA_IN(26 downto 0); fifo_in_count(4) <= FIFO_4_DATA_IN(37 downto 27);\r
+fifo_in_data(5) <= FIFO_5_DATA_IN(26 downto 0); fifo_in_count(5) <= FIFO_5_DATA_IN(37 downto 27);\r
+fifo_in_data(6) <= FIFO_6_DATA_IN(26 downto 0); fifo_in_count(6) <= FIFO_6_DATA_IN(37 downto 27);\r
+fifo_in_data(7) <= FIFO_7_DATA_IN(26 downto 0); fifo_in_count(7) <= FIFO_7_DATA_IN(37 downto 27);\r
+fifo_in_data(8) <= FIFO_8_DATA_IN(26 downto 0); fifo_in_count(8) <= FIFO_8_DATA_IN(37 downto 27);\r
+fifo_in_data(9) <= FIFO_9_DATA_IN(26 downto 0); fifo_in_count(9) <= FIFO_9_DATA_IN(37 downto 27);\r
+fifo_in_data(10) <= FIFO_10_DATA_IN(26 downto 0); fifo_in_count(10) <= FIFO_10_DATA_IN(37 downto 27);\r
+fifo_in_data(11) <= FIFO_11_DATA_IN(26 downto 0); fifo_in_count(11) <= FIFO_11_DATA_IN(37 downto 27);\r
+fifo_in_data(12) <= FIFO_12_DATA_IN(26 downto 0); fifo_in_count(12) <= FIFO_12_DATA_IN(37 downto 27);\r
+fifo_in_data(13) <= FIFO_13_DATA_IN(26 downto 0); fifo_in_count(13) <= FIFO_13_DATA_IN(37 downto 27);\r
+fifo_in_data(14) <= FIFO_14_DATA_IN(26 downto 0); fifo_in_count(14) <= FIFO_14_DATA_IN(37 downto 27);\r
+fifo_in_data(15) <= FIFO_15_DATA_IN(26 downto 0); fifo_in_count(15) <= FIFO_15_DATA_IN(37 downto 27);\r
+\r
+---------------------------------------------------------------------------\r
+-- DATA and LENGTH FIFO for the APV data streams\r
+---------------------------------------------------------------------------\r
+\r
+-- We also store the DHDR inside the LFIFOs. They are big enough and have unused bits like hell.\r
+dhdr_fifo_in_int <= DHDR_LENGTH_IN & DHDR_DATA_IN;\r
+\r
+GEN_FIFO: for i in 0 to 15 generate\r
+ THE_DFIFO: fifo_2kx27\r
+ port map(\r
+ DATA => fifo_in_data(i),\r
+ CLOCK => CLK_IN,\r
+ WREN => FIFO_WE_IN(i),\r
+ RDEN => comb_rd_dfifo(i),\r
+ RESET => reset_all,\r
+ Q => fifo_out_data(i),\r
+ WCNT => fifo_wcnt(i),\r
+ EMPTY => dfifo_empty(i),\r
+ FULL => dfifo_full(i)\r
+ );\r
+\r
+ -- Combinatorial read pulse for FIFOs\r
+ comb_rd_dfifo(i) <= (not fifo_done(i) and sel_fifo(i) and IPU_READ_IN and dataready) or (preload and fifo_ldata(i)(10));\r
+\r
+ -- Combinatorial store pulse for data (last data word need to be transfered also!)\r
+ comb_st_data(i) <= (sel_fifo(i) and IPU_READ_IN and dataready);\r
+\r
+ -- getting the number of free entries in the data fifo by subtracting [size] - [used entries]\r
+ fifo_data_free_x(i) <= x"800" - unsigned(fifo_wcnt(i));\r
+\r
+ -- check if next event will still fit into data FIFO\r
+ dfifo_available_x(i) <= '1' when (fifo_data_free(i) > unsigned(FIFO_SPACE_REQ_IN)) else '0';\r
+\r
+ THE_SMALL_SYNCER: process( clk_in)\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ fifo_data_free(i) <= fifo_data_free_x(i);\r
+ dfifo_available(i) <= dfifo_available_x(i);\r
+ end if;\r
+ end process THE_SMALL_SYNCER; \r
+\r
+ -- length fifo - stores the number of words to fetch from dfifo\r
+ THE_LFIFO: fifo_1kx18\r
+ port map(\r
+ DATA(17 downto 15) => dhdr_fifo_in_int(i*3 + 2 downto i*3),\r
+ DATA(14 downto 11) => b"0000", -- free for other stuff!\r
+ DATA(10 downto 0) => fifo_in_count(i),\r
+ CLOCK => CLK_IN,\r
+ WREN => FIFO_DONE_IN,\r
+ RDEN => rd_lfifo,\r
+ RESET => reset_all,\r
+ Q(17 downto 11) => fifo_lunused(i), -- will be portions of DHDR\r
+ Q(10 downto 0) => fifo_ldata(i),\r
+ WCNT => open, -- BUG\r
+ EMPTY => lfifo_empty(i), -- BUG\r
+ ALMOSTFULL => lfifo_almostfull(i), -- BUG\r
+ FULL => lfifo_full(i) -- BUG\r
+ );\r
+ next_todo_list(i) <= fifo_ldata(i)(10);\r
+\r
+ -- reassamble the DHDR information \r
+ dhdr_fifo_out_int(i*3 + 2 downto i*3) <= fifo_lunused(i)(6 downto 4);\r
+ \r
+ -- TODO counter for all FIFOs\r
+ THE_TODO_CTR_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( (reset_all = '1') or (rd_lfifo = '1') ) then\r
+ fifo_todo(i) <= (others => '0');\r
+ elsif( ld_todo = '1' ) then\r
+ fifo_todo(i) <= unsigned(fifo_ldata(i)(9 downto 0));\r
+ elsif( comb_rd_dfifo(i) = '1' ) then\r
+ fifo_todo(i) <= fifo_todo(i) - 1;\r
+ end if;\r
+ end if;\r
+ end process THE_TODO_CTR_PROC;\r
+\r
+ next_fifo_done(i) <= '1' when ( fifo_todo(i) = b"00_0000_0000" ) else '0';\r
+\r
+ -- FIFO status bits, compatible with Jans data handler\r
+ fifo_status(i)(31 downto 28) <= (others => '0'); -- reserved\r
+ fifo_status(i)(27) <= '0'; --fifo_done_in; -- length FIFO write strobe (not implemented)\r
+ fifo_status(i)(26) <= lfifo_full(i); -- length FIFO full. This is an error flag.\r
+ fifo_status(i)(25) <= lfifo_almostfull(i); -- length FIFO almost full\r
+ fifo_status(i)(24) <= lfifo_empty(i); -- length FIFO empty\r
+ fifo_status(i)(23) <= '0'; -- reserved\r
+ fifo_status(i)(22) <= '0'; -- buffer state machine waiting for busy release\r
+ fifo_status(i)(21) <= '0'; -- buffer state machine busy waiting for data\r
+ fifo_status(i)(20) <= '0'; -- buffer state machine idle\r
+ fifo_status(i)(19) <= '0'; --FIFO_WE_IN(i); -- FIFO write strobe (not implemented)\r
+ fifo_status(i)(18) <= dfifo_full(i); -- FIFO full. This is an error flag.\r
+ fifo_status(i)(17) <= not dfifo_available(i); -- FIFO almost full\r
+ fifo_status(i)(16) <= dfifo_empty(i); -- FIFO empty\r
+ fifo_status(i)(15 downto 0) <= b"0000" & fifo_wcnt(i); -- current fill level of FIFO\r
+\r
+end generate GEN_FIFO;\r
+\r
+comb_ack_todo <= fifo_last and set_data;\r
+\r
+next_dhdr_buf_full <= '1' when (lfifo_almostfull(0) = '1') or\r
+ (dfifo_available /= b"1111_1111_1111_1111")\r
+ else '0';\r
+dhdr_avail <= not lfifo_empty(0); -- FAKE\r
+\r
+-- compare incoming trigger number with stored DHDR information\r
+next_trgnum_match <= '1' when ( IPU_NUMBER_IN = dhdr_fifo_out_int(15 downto 0) ) else '0';\r
+\r
+THE_TRGNUM_MATCH_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( reset_all = '1' ) then\r
+ trgnum_match <= '0';\r
+ my_trg_number <= (others => '0');\r
+ elsif( set_hdr = '1' ) then\r
+ trgnum_match <= next_trgnum_match;\r
+ my_trg_number <= IPU_NUMBER_IN & dhdr_fifo_out_int(15 downto 0);\r
+ end if;\r
+ end if;\r
+end process THE_TRGNUM_MATCH_PROC;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- priority encoding is used to select the next buffer for readout\r
+---------------------------------------------------------------------------\r
+THE_PRI_ENCODER_PROC: process( todo_list, fifo_done )\r
+begin\r
+ if ( todo_list(15 downto 15) = "1" ) then\r
+ next_fifo_sel <= "01111"; next_sel_fifo <= b"1000_0000_0000_0000"; next_fifo_last <= fifo_done(15);\r
+ elsif( todo_list(15 downto 14) = "01" ) then\r
+ next_fifo_sel <= "01110"; next_sel_fifo <= b"0100_0000_0000_0000"; next_fifo_last <= fifo_done(14);\r
+ elsif( todo_list(15 downto 13) = "001" ) then\r
+ next_fifo_sel <= "01101"; next_sel_fifo <= b"0010_0000_0000_0000"; next_fifo_last <= fifo_done(13);\r
+ elsif( todo_list(15 downto 12) = "0001" ) then\r
+ next_fifo_sel <= "01100"; next_sel_fifo <= b"0001_0000_0000_0000"; next_fifo_last <= fifo_done(12);\r
+ elsif( todo_list(15 downto 11) = "00001" ) then\r
+ next_fifo_sel <= "01011"; next_sel_fifo <= b"0000_1000_0000_0000"; next_fifo_last <= fifo_done(11);\r
+ elsif( todo_list(15 downto 10) = "000001" ) then\r
+ next_fifo_sel <= "01010"; next_sel_fifo <= b"0000_0100_0000_0000"; next_fifo_last <= fifo_done(10);\r
+ elsif( todo_list(15 downto 9) = "0000001" ) then\r
+ next_fifo_sel <= "01001"; next_sel_fifo <= b"0000_0010_0000_0000"; next_fifo_last <= fifo_done(9);\r
+ elsif( todo_list(15 downto 8) = "00000001" ) then\r
+ next_fifo_sel <= "01000"; next_sel_fifo <= b"0000_0001_0000_0000"; next_fifo_last <= fifo_done(8);\r
+ elsif( todo_list(15 downto 7) = "000000001" ) then\r
+ next_fifo_sel <= "00111"; next_sel_fifo <= b"0000_0000_1000_0000"; next_fifo_last <= fifo_done(7);\r
+ elsif( todo_list(15 downto 6) = "0000000001" ) then\r
+ next_fifo_sel <= "00110"; next_sel_fifo <= b"0000_0000_0100_0000"; next_fifo_last <= fifo_done(6);\r
+ elsif( todo_list(15 downto 5) = "00000000001" ) then\r
+ next_fifo_sel <= "00101"; next_sel_fifo <= b"0000_0000_0010_0000"; next_fifo_last <= fifo_done(5);\r
+ elsif( todo_list(15 downto 4) = "000000000001" ) then\r
+ next_fifo_sel <= "00100"; next_sel_fifo <= b"0000_0000_0001_0000"; next_fifo_last <= fifo_done(4);\r
+ elsif( todo_list(15 downto 3) = "0000000000001" ) then\r
+ next_fifo_sel <= "00011"; next_sel_fifo <= b"0000_0000_0000_1000"; next_fifo_last <= fifo_done(3);\r
+ elsif( todo_list(15 downto 2) = "00000000000001" ) then\r
+ next_fifo_sel <= "00010"; next_sel_fifo <= b"0000_0000_0000_0100"; next_fifo_last <= fifo_done(2);\r
+ elsif( todo_list(15 downto 1) = "000000000000001" ) then\r
+ next_fifo_sel <= "00001"; next_sel_fifo <= b"0000_0000_0000_0010"; next_fifo_last <= fifo_done(1);\r
+ elsif( todo_list(15 downto 0) = "0000000000000001" ) then\r
+ next_fifo_sel <= "00000"; next_sel_fifo <= b"0000_0000_0000_0001"; next_fifo_last <= fifo_done(0);\r
+ else\r
+ next_fifo_sel <= "10000"; next_sel_fifo <= b"0000_0000_0000_0000"; next_fifo_last <= '0';\r
+ end if;\r
+end process THE_PRI_ENCODER_PROC;\r
+\r
+-- We need to clear single bits during readout here!!!\r
+THE_TODO_LIST_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( reset_all = '1' ) then\r
+ todo_list <= (others => '0');\r
+ elsif( ld_todo = '1' ) then\r
+ todo_list <= next_todo_list; -- store initial todo list\r
+ elsif( comb_ack_todo = '1' ) then\r
+ todo_list <= todo_list and not sel_fifo; -- does this work?!?\r
+ end if;\r
+ end if;\r
+end process THE_TODO_LIST_PROC;\r
+\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- synchronizing process\r
+---------------------------------------------------------------------------\r
+THE_SYNC_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ fifo_sel <= next_fifo_sel;\r
+ sel_fifo <= next_sel_fifo;\r
+ fifo_done <= next_fifo_done;\r
+ fifo_last <= next_fifo_last;\r
+ dhdr_buf_full <= next_dhdr_buf_full;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- backplane wise APV mapping\r
+---------------------------------------------------------------------------\r
+old_apv_num <= fifo_sel(3 downto 0);\r
+\r
+THE_ADC_APV_MAP_MEM: adc_apv_map_mem\r
+port map( ADDRESS(6 downto 4) => MODULE_IN(2 downto 0),\r
+ ADDRESS(3 downto 0) => old_apv_num,\r
+ Q => new_apv_num\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Data multiplexer\r
+---------------------------------------------------------------------------\r
+THE_DATA_MUX_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( set_hdr = '1' ) then\r
+ ipu_out_data <= dhdr_fifo_out_int(31 downto 0);\r
+ elsif( comb_st_data(0) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(0)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(0)(20 downto 0);\r
+ elsif( comb_st_data(1) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(1)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(1)(20 downto 0);\r
+ elsif( comb_st_data(2) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(2)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(2)(20 downto 0);\r
+ elsif( comb_st_data(3) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(3)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(3)(20 downto 0);\r
+ elsif( comb_st_data(4) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(4)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(4)(20 downto 0);\r
+ elsif( comb_st_data(5) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(5)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(5)(20 downto 0);\r
+ elsif( comb_st_data(6) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(6)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(6)(20 downto 0);\r
+ elsif( comb_st_data(7) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(7)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(7)(20 downto 0);\r
+ elsif( comb_st_data(8) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(8)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(8)(20 downto 0);\r
+ elsif( comb_st_data(9) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(9)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(9)(20 downto 0);\r
+ elsif( comb_st_data(10) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(10)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(10)(20 downto 0);\r
+ elsif( comb_st_data(11) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(11)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(11)(20 downto 0);\r
+ elsif( comb_st_data(12) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(12)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(12)(20 downto 0);\r
+ elsif( comb_st_data(13) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(13)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(13)(20 downto 0);\r
+ elsif( comb_st_data(14) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(14)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(14)(20 downto 0);\r
+ elsif( comb_st_data(15) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(15)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(15)(20 downto 0);\r
+ end if;\r
+ end if;\r
+end process THE_DATA_MUX_PROC;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- IPU cycle counter... just to be sure\r
+---------------------------------------------------------------------------\r
+THE_CYCLE_COUNTER_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( reset_all = '1' ) then\r
+ cyclectr <= (others => '0');\r
+ elsif( finished = '1' ) then\r
+ cyclectr <= cyclectr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_CYCLE_COUNTER_PROC;\r
+\r
+-- IPU handler status\r
+ipu_status(31 downto 16) <= (others => '0'); -- reserved\r
+ipu_status(15) <= '0'; -- error flag: endpoint not configured\r
+ipu_status(14) <= '0'; -- error flag: synchronisation\r
+ipu_status(13) <= '0'; -- error flag: event has missing data\r
+ipu_status(12) <= not trgnum_match; -- error flag: event not found\r
+ipu_status(11 downto 4) <= (others => '0'); -- reserved\r
+ipu_status(3 downto 0) <= status_bits; -- IPU transfer status \r
+\r
+-- LVL1 and IPU channel release status\r
+release_status(31 downto 16) <= fifo_done;\r
+release_status(15 downto 0) <= (others => '0'); -- BUG\r
+\r
+---------------------------------------------------------------------------\r
+-- Output signals\r
+---------------------------------------------------------------------------\r
+IPU_DATA_OUT <= ipu_out_data;\r
+LVL2_COUNTER_OUT <= std_logic_vector(cyclectr);\r
+IPU_LAST_NUM_OUT <= my_trg_number;\r
+DHDR_BUF_FULL_OUT <= dhdr_buf_full;\r
+\r
+FIFO_0_STATUS_OUT <= fifo_status(0);\r
+FIFO_1_STATUS_OUT <= fifo_status(1);\r
+FIFO_2_STATUS_OUT <= fifo_status(2);\r
+FIFO_3_STATUS_OUT <= fifo_status(3);\r
+FIFO_4_STATUS_OUT <= fifo_status(4);\r
+FIFO_5_STATUS_OUT <= fifo_status(5);\r
+FIFO_6_STATUS_OUT <= fifo_status(6);\r
+FIFO_7_STATUS_OUT <= fifo_status(7);\r
+FIFO_8_STATUS_OUT <= fifo_status(8);\r
+FIFO_9_STATUS_OUT <= fifo_status(9);\r
+FIFO_10_STATUS_OUT <= fifo_status(10);\r
+FIFO_11_STATUS_OUT <= fifo_status(11);\r
+FIFO_12_STATUS_OUT <= fifo_status(12);\r
+FIFO_13_STATUS_OUT <= fifo_status(13);\r
+FIFO_14_STATUS_OUT <= fifo_status(14);\r
+FIFO_15_STATUS_OUT <= fifo_status(15);\r
+IPU_STATUS_OUT <= ipu_status;\r
+RELEASE_STATUS_OUT <= release_status;\r
+\r
+---------------------------------------------------------------------------\r
+-- debug information\r
+---------------------------------------------------------------------------\r
+debug(63 downto 48) <= todo_list;\r
+debug(47 downto 25) <= (others => '0');\r
+debug(24 downto 20) <= fifo_sel;\r
+debug(19 downto 17) <= (others => '0');\r
+debug(16) <= fifo_last;\r
+debug(15 downto 0) <= fifo_done;\r
+\r
+---------------------------------------------------------------------------\r
+-- DEBUG signals\r
+---------------------------------------------------------------------------\r
+DBG_BSM_OUT <= bsm_x;\r
+DBG_OUT <= debug;\r
+\r
+end behavioral;\r
+\r
+\r
+\r
+\r
+\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
IPU_READ_IN : in std_logic; -- read strobe, low every second cycle\r
IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
+ IPU_LAST_NUM_OUT : out std_logic_vector(31 downto 0); -- last number received / readout\r
LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter\r
-- DHDR buffer input\r
DHDR_DATA_IN : in std_logic_vector(31 downto 0);\r
FIFO_15_DATA_IN : in std_logic_vector(39 downto 0);\r
FIFO_WE_IN : in std_logic_vector(15 downto 0);\r
FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs\r
+ -- data buffer status\r
+ FIFO_0_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_1_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_2_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_3_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_4_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_5_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_6_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_7_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_8_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_9_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_10_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_11_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_12_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_13_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_14_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ FIFO_15_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ IPU_STATUS_OUT : out std_logic_vector(31 downto 0);\r
+ RELEASE_STATUS_OUT : out std_logic_vector(31 downto 0);\r
-- Debug signals\r
DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
DBG_OUT : out std_logic_vector(63 downto 0)\r
signal fifo_out_data : fifo_data_t;\r
type fifo_count_t is array (0 to 15) of std_logic_vector(10 downto 0);\r
signal fifo_in_count : fifo_count_t;\r
-type fifo_todo_t is array (0 to 15) of std_logic_vector(9 downto 0);\r
+type fifo_todo_t is array (0 to 15) of unsigned(9 downto 0);\r
signal fifo_todo : fifo_todo_t;\r
type fifo_ldata_t is array (0 to 15) of std_logic_vector(10 downto 0);\r
signal fifo_ldata : fifo_ldata_t;\r
signal fifo_data_free : fifo_wcnt_t;\r
type fifo_lunused_t is array (0 to 15) of std_logic_vector(6 downto 0);\r
signal fifo_lunused : fifo_lunused_t;\r
+type fifo_status_t is array (0 to 15) of std_logic_vector(31 downto 0);\r
+signal fifo_status : fifo_status_t;\r
+\r
+signal ipu_status : std_logic_vector(31 downto 0);\r
+signal release_status : std_logic_vector(31 downto 0);\r
\r
signal dfifo_available : std_logic_vector(15 downto 0);\r
+signal dfifo_empty : std_logic_vector(15 downto 0);\r
+signal dfifo_full : std_logic_vector(15 downto 0);\r
\r
signal lfifo_empty : std_logic_vector(15 downto 0);\r
+signal lfifo_almostfull : std_logic_vector(15 downto 0);\r
signal lfifo_full : std_logic_vector(15 downto 0);\r
\r
signal next_fifo_done : std_logic_vector(15 downto 0);\r
signal old_apv_num : std_logic_vector(3 downto 0);\r
signal new_apv_num : std_logic_vector(3 downto 0);\r
\r
-signal cyclectr : std_logic_vector(15 downto 0); -- cycle counter\r
+signal cyclectr : unsigned(15 downto 0); -- cycle counter\r
\r
signal next_dhdr_buf_full : std_logic;\r
signal dhdr_buf_full : std_logic;\r
\r
+-- Jan Michel's status bits (faked)\r
+signal status_bits : std_logic_vector(3 downto 0);\r
+\r
begin\r
---------------------------------------------------------------------------\r
-- Statemachine\r
next_ack_todo <= '0';\r
next_preload <= '0';\r
next_finished <= '0';\r
+ \r
case CURRENT_STATE is\r
when SLEEP => if( (dhdr_avail = '1') and (ipu_start_readout_in = '1') ) then\r
NEXT_STATE <= RDLF;\r
next_rd_lfifo <= '1';\r
else\r
- NEXT_STATE <= SLEEP;\r
+ NEXT_STATE <= SLEEP;\r
end if;\r
when RDLF => NEXT_STATE <= GETFD;\r
next_set_hdr <= '1';\r
-- length information can be simply copied\r
ipu_length_out <= dhdr_fifo_out(47 downto 32);\r
\r
--- IPU error pattern: [24] => trigger tag mismatch\r
+-- IPU error pattern\r
ipu_error_pattern_out(31 downto 24) <= (others => '0');\r
ipu_error_pattern_out(23) <= '0'; -- "single broken event"\r
ipu_error_pattern_out(23) <= '0'; -- "severe problem"\r
STATE_DECODE: process( CURRENT_STATE )\r
begin\r
case CURRENT_STATE is\r
- when SLEEP => bsm_x <= x"00";\r
- when RDLF => bsm_x <= x"01";\r
- when GETFD => bsm_x <= x"02";\r
- when DELH => bsm_x <= x"03";\r
- when WHDR => bsm_x <= x"04";\r
- when GETD => bsm_x <= x"05";\r
- when WAITD => bsm_x <= x"06";\r
- when WAITDL => bsm_x <= x"07";\r
- when DEL0 => bsm_x <= x"08";\r
- when DONE => bsm_x <= x"09";\r
- when others => bsm_x <= x"ff";\r
+ when SLEEP => bsm_x <= x"00";\r
+ status_bits <= x"0";\r
+ when RDLF => bsm_x <= x"01";\r
+ status_bits <= x"1";\r
+ when GETFD => bsm_x <= x"02";\r
+ status_bits <= x"2";\r
+ when DELH => bsm_x <= x"03";\r
+ status_bits <= x"3";\r
+ when WHDR => bsm_x <= x"04";\r
+ status_bits <= x"3";\r
+ when GETD => bsm_x <= x"05";\r
+ status_bits <= x"4";\r
+ when WAITD => bsm_x <= x"06";\r
+ status_bits <= x"4";\r
+ when WAITDL => bsm_x <= x"07";\r
+ status_bits <= x"4";\r
+ when DEL0 => bsm_x <= x"08";\r
+ status_bits <= x"4";\r
+ when DONE => bsm_x <= x"09";\r
+ status_bits <= x"5";\r
+ when others => bsm_x <= x"ff";\r
+ status_bits <= x"f";\r
end case;\r
end process STATE_DECODE;\r
\r
RESET => reset_in,\r
Q => fifo_out_data(i), -- BUG\r
WCNT => fifo_wcnt(i), -- BUG\r
- EMPTY => open, -- BUG\r
- FULL => open -- BUG\r
+ EMPTY => dfifo_empty(i), -- BUG\r
+ FULL => dfifo_full(i) -- BUG\r
);\r
\r
-- Combinatorial read pulse for FIFOs\r
Q(17 downto 11) => fifo_lunused(i), -- will be portions of DHDR\r
Q(10 downto 0) => fifo_ldata(i),\r
WCNT => open, -- BUG\r
- EMPTY => lfifo_empty(i), -- open -- BUG\r
- FULL => lfifo_full(i) --open -- BUG\r
+ EMPTY => lfifo_empty(i), -- BUG\r
+ ALMOSTFULL => lfifo_almostfull(i), -- BUG\r
+ FULL => lfifo_full(i) -- BUG\r
);\r
next_todo_list(i) <= fifo_ldata(i)(10);\r
\r
if( (reset_in = '1') or (rd_lfifo = '1') ) then\r
fifo_todo(i) <= (others => '0');\r
elsif( ld_todo = '1' ) then\r
- fifo_todo(i) <= fifo_ldata(i)(9 downto 0);\r
+ fifo_todo(i) <= unsigned(fifo_ldata(i)(9 downto 0));\r
elsif( comb_rd_dfifo(i) = '1' ) then\r
fifo_todo(i) <= fifo_todo(i) - 1;\r
end if;\r
\r
next_fifo_done(i) <= '1' when ( fifo_todo(i) = b"00_0000_0000" ) else '0';\r
\r
+ -- FIFO status bits, compatible with Jans data handler\r
+ fifo_status(i)(31 downto 28) <= (others => '0'); -- reserved\r
+ fifo_status(i)(27) <= '0'; --fifo_done_in; -- length FIFO write strobe (not implemented)\r
+ fifo_status(i)(26) <= lfifo_full(i); -- length FIFO full. This is an error flag.\r
+ fifo_status(i)(25) <= lfifo_almostfull(i); -- length FIFO almost full\r
+ fifo_status(i)(24) <= lfifo_empty(i); -- length FIFO empty\r
+ fifo_status(i)(23) <= '0'; -- reserved\r
+ fifo_status(i)(22) <= '0'; -- buffer state machine waiting for busy release\r
+ fifo_status(i)(21) <= '0'; -- buffer state machine busy waiting for data\r
+ fifo_status(i)(20) <= '0'; -- buffer state machine idle\r
+ fifo_status(i)(19) <= '0'; --fifo_we_in(i); -- FIFO write strobe (not implemented)\r
+ fifo_status(i)(18) <= dfifo_full(i); -- FIFO full. This is an error flag.\r
+ fifo_status(i)(17) <= not dfifo_available(i); -- FIFO almost full\r
+ fifo_status(i)(16) <= dfifo_empty(i); -- FIFO empty\r
+ fifo_status(i)(15 downto 0) <= b"0000" & fifo_wcnt(i); -- current fill level of FIFO\r
+\r
end generate GEN_FIFO;\r
\r
comb_ack_todo <= fifo_last and set_data;\r
\r
-next_dhdr_buf_full <= '1' when (lfifo_full(0) = '1') or\r
+next_dhdr_buf_full <= '1' when (lfifo_almostfull(0) = '1') or\r
(dfifo_available /= b"1111_1111_1111_1111")\r
else '0';\r
dhdr_avail <= not lfifo_empty(0); -- FAKE\r
end if;\r
end process THE_CYCLE_COUNTER_PROC;\r
\r
+-- IPU handler status\r
+ipu_status(31 downto 16) <= (others => '0'); -- reserved\r
+ipu_status(15) <= '0'; -- error flag: endpoint not configured\r
+ipu_status(14) <= '0'; -- error flag: synchronisation\r
+ipu_status(13) <= '0'; -- error flag: event has missing data\r
+ipu_status(12) <= not trgnum_match; -- error flag: event not found\r
+ipu_status(11 downto 4) <= (others => '0'); -- reserved\r
+ipu_status(3 downto 0) <= status_bits; -- IPU transfer status \r
+\r
+-- LVL1 and IPU channel release status\r
+release_status(31 downto 16) <= fifo_done;\r
+release_status(15 downto 0) <= (others => '0'); -- BUG\r
+\r
+---------------------------------------------------------------------------\r
+-- Output signals\r
+---------------------------------------------------------------------------\r
+IPU_DATA_OUT <= ipu_out_data;\r
+LVL2_COUNTER_OUT <= std_logic_vector(cyclectr);\r
+IPU_LAST_NUM_OUT <= my_trg_number;\r
+DHDR_BUF_FULL_OUT <= dhdr_buf_full;\r
+\r
+FIFO_0_STATUS_OUT <= fifo_status(0);\r
+FIFO_1_STATUS_OUT <= fifo_status(1);\r
+FIFO_2_STATUS_OUT <= fifo_status(2);\r
+FIFO_3_STATUS_OUT <= fifo_status(3);\r
+FIFO_4_STATUS_OUT <= fifo_status(4);\r
+FIFO_5_STATUS_OUT <= fifo_status(5);\r
+FIFO_6_STATUS_OUT <= fifo_status(6);\r
+FIFO_7_STATUS_OUT <= fifo_status(7);\r
+FIFO_8_STATUS_OUT <= fifo_status(8);\r
+FIFO_9_STATUS_OUT <= fifo_status(9);\r
+FIFO_10_STATUS_OUT <= fifo_status(10);\r
+FIFO_11_STATUS_OUT <= fifo_status(11);\r
+FIFO_12_STATUS_OUT <= fifo_status(12);\r
+FIFO_13_STATUS_OUT <= fifo_status(13);\r
+FIFO_14_STATUS_OUT <= fifo_status(14);\r
+FIFO_15_STATUS_OUT <= fifo_status(15);\r
+IPU_STATUS_OUT <= ipu_status;\r
+RELEASE_STATUS_OUT <= release_status;\r
+\r
---------------------------------------------------------------------------\r
-- debug information\r
---------------------------------------------------------------------------\r
debug(16) <= fifo_last;\r
debug(15 downto 0) <= fifo_done;\r
\r
----------------------------------------------------------------------------\r
--- Output signals\r
----------------------------------------------------------------------------\r
-ipu_data_out <= ipu_out_data;\r
-lvl2_counter_out <= cyclectr;\r
-dhdr_buf_full_out <= dhdr_buf_full;\r
-\r
---------------------------------------------------------------------------\r
-- DEBUG signals\r
---------------------------------------------------------------------------\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
\r
-- FIRST COMPARATOR STEP\r
-- compare MAX_3 against MAX_2, store the bigger one\r
-THE_COMP_3_2: comp4bit\r
-port map(\r
- DATAA => todo_3_in,\r
- DATAB => todo_2_in,\r
- AGTB => comb_3_gt_2\r
-);\r
+comb_3_gt_2 <= '1' when (todo_3_in > todo_2_in) else '0';\r
\r
THE_3_2_STORE_PROC: process( clk_in )\r
begin\r
\r
\r
-- compare MAX_2 against MAX_1, store the bigger one\r
-THE_COMP_2_1: comp4bit\r
-port map(\r
- DATAA => todo_2_in,\r
- DATAB => todo_1_in,\r
- AGTB => comb_2_gt_1\r
-);\r
+comb_2_gt_1 <= '1' when (todo_2_in > todo_1_in) else '0';\r
\r
THE_2_1_STORE_PROC: process( clk_in )\r
begin\r
end process THE_2_1_STORE_PROC;\r
\r
-- compare MAX_1 against MAX_0, store the bigger one\r
-THE_COMP_1_0: comp4bit\r
-port map(\r
- DATAA => todo_1_in,\r
- DATAB => todo_0_in,\r
- AGTB => comb_1_gt_0\r
-);\r
+comb_1_gt_0 <= '1' when (todo_1_in > todo_0_in) else '0';\r
\r
THE_1_0_STORE_PROC: process( clk_in )\r
begin\r
\r
-- SECOND COMPARATOR STEP\r
-- compare MAX_32 against MAX_21, store the bigger one\r
-THE_COMP_32_21: comp4bit\r
-port map(\r
- DATAA => max_32_data,\r
- DATAB => max_21_data,\r
- AGTB => comb_32_gt_21\r
-);\r
+comb_32_gt_21 <= '1' when (max_32_data > max_21_data) else '0';\r
\r
THE_32_21_STORE_PROC: process( clk_in )\r
begin\r
end process THE_32_21_STORE_PROC;\r
\r
-- compare MAX_21 against MAX_10, store the bigger one\r
-THE_COMP_21_10: comp4bit\r
-port map(\r
- DATAA => max_21_data,\r
- DATAB => max_10_data,\r
- AGTB => comb_21_gt_10\r
-);\r
+comb_21_gt_10 <= '1' when (max_21_data > max_10_data) else '0';\r
\r
THE_21_10_STORE_PROC: process( clk_in )\r
begin\r
end process THE_21_10_STORE_PROC;\r
\r
-- FINAL COMPARATOR STEP\r
-THE_COMP_FINAL: comp4bit\r
-port map(\r
- DATAA => max_321_data,\r
- DATAB => max_210_data,\r
- AGTB => comb_final\r
-);\r
+comb_final <= '1' when (max_321_data > max_210_data) else '0';\r
\r
THE_FINAL_STORE_PROC: process( clk_in )\r
begin\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
CLK_IN : in std_logic; -- 100MHz local clock\r
RESET_IN : in std_logic; -- synchronous reset\r
-- Slow control registers\r
+ VERBOSE_IN : in std_logic; -- add debug words for each APV\r
-- EDS buffer -- back to previous source stage\r
EDS_DATA_IN : in std_logic_vector(39 downto 0);\r
EDS_AVAIL_IN : in std_logic;\r
signal buf_ready : std_logic_vector(15 downto 0);\r
\r
-- local frame counter\r
-signal to_do_ctr : std_logic_vector(3 downto 0);\r
-signal done_ctr : std_logic_vector(3 downto 0);\r
-signal loc_frm_ctr : std_logic_vector(3 downto 0);\r
+signal to_do_ctr : unsigned(3 downto 0);\r
+signal done_ctr : unsigned(3 downto 0);\r
+signal loc_frm_ctr : unsigned(3 downto 0);\r
signal next_ld_frm_ctr : std_logic;\r
signal ld_frm_ctr : std_logic; -- load frame counter with EDS start value\r
signal next_ce_frm_ctr : std_logic;\r
signal frame_busy : std_logic; -- from ALU\r
\r
-- Buffer read address counter, control signals\r
-signal buf_addr : std_logic_vector(5 downto 0); -- buffer / pedestal read address\r
+signal buf_addr : unsigned(5 downto 0); -- buffer / pedestal read address\r
signal buf_half : std_logic;\r
signal next_buf_addr_ce : std_logic;\r
signal buf_addr_ce : std_logic;\r
\r
-- for summing up\r
signal next_small_0_sum : std_logic_vector(4 downto 0);\r
-signal small_0_sum : std_logic_vector(4 downto 0);\r
+signal small_0_sum : unsigned(4 downto 0);\r
signal next_small_1_sum : std_logic_vector(4 downto 0);\r
-signal small_1_sum : std_logic_vector(4 downto 0);\r
-signal small_sum : std_logic_vector(15 downto 0);\r
-signal total_sum : std_logic_vector(15 downto 0);\r
+signal small_1_sum : unsigned(4 downto 0);\r
+signal small_sum : unsigned(15 downto 0);\r
+signal total_sum : unsigned(15 downto 0);\r
signal reset_sum : std_logic;\r
\r
signal next_max_num_words : std_logic_vector(11 downto 0);\r
-- - number of debug words per APV frame => by design\r
next_max_num_words(11) <= '0';\r
\r
-THE_DECIDER_PROC: process( eds_data_in(35 downto 32), eds_data_in(2 downto 0) )\r
+--THE_DECIDER_PROC: process( EDS_DATA_IN(35 downto 32), EDS_DATA_IN(2 downto 0) )\r
+THE_DECIDER_PROC: process( EDS_DATA_IN(35 downto 32) )\r
begin\r
case eds_data_in(2 downto 0) is\r
- when b"000" => next_max_num_words(10 downto 6) <= eds_data_in(35 downto 32) & '0'; -- 128 - RAW128\r
- when b"001" => next_max_num_words(10 downto 6) <= eds_data_in(35 downto 32) & '0'; -- 128 - PED128\r
- when b"010" => next_max_num_words(10 downto 6) <= eds_data_in(35 downto 32) & '0'; -- 128 - PED128THR\r
- when b"011" => next_max_num_words(10 downto 6) <= '0' & eds_data_in(35 downto 32); -- 64 - RAW64\r
- when b"100" => next_max_num_words(10 downto 6) <= eds_data_in(35 downto 32) & '0'; -- 128 - NC64PED64\r
- when b"101" => next_max_num_words(10 downto 6) <= '0' & eds_data_in(35 downto 32); -- 64 - NC64\r
- when b"110" => next_max_num_words(10 downto 6) <= '0' & eds_data_in(35 downto 32); -- 64 - NC64GOOD\r
- when b"111" => next_max_num_words(10 downto 6) <= '0' & eds_data_in(35 downto 32); -- 64 - NC64THR\r
+ when b"000" => next_max_num_words(10 downto 6) <= EDS_DATA_IN(35 downto 32) & '0'; -- 128 - RAW128\r
+ when b"001" => next_max_num_words(10 downto 6) <= EDS_DATA_IN(35 downto 32) & '0'; -- 128 - PED128\r
+ when b"010" => next_max_num_words(10 downto 6) <= EDS_DATA_IN(35 downto 32) & '0'; -- 128 - PED128THR\r
+ when b"011" => next_max_num_words(10 downto 6) <= '0' & EDS_DATA_IN(35 downto 32); -- 64 - RAW64\r
+ when b"100" => next_max_num_words(10 downto 6) <= EDS_DATA_IN(35 downto 32) & '0'; -- 128 - NC64PED64\r
+ when b"101" => next_max_num_words(10 downto 6) <= '0' & EDS_DATA_IN(35 downto 32); -- 64 - NC64\r
+ when b"110" => next_max_num_words(10 downto 6) <= '0' & EDS_DATA_IN(35 downto 32); -- 64 - NC64GOOD\r
+ when b"111" => next_max_num_words(10 downto 6) <= '0' & EDS_DATA_IN(35 downto 32); -- 64 - NC64THR\r
when others => next_max_num_words(10 downto 6) <= (others => '0');\r
end case;\r
end process THE_DECIDER_PROC;\r
\r
next_max_num_words(5) <= '0';\r
-next_max_num_words(4 downto 1) <= eds_data_in(35 downto 32);\r
+next_max_num_words(4 downto 1) <= EDS_DATA_IN(35 downto 32);\r
next_max_num_words(0) <= '0';\r
\r
---------------------------------------------------------------------------\r
-- Aliasing the data streams\r
---------------------------------------------------------------------------\r
-raw_data(0) <= buf_0_data_in;\r
-raw_data(1) <= buf_1_data_in;\r
-raw_data(2) <= buf_2_data_in;\r
-raw_data(3) <= buf_3_data_in;\r
-raw_data(4) <= buf_4_data_in;\r
-raw_data(5) <= buf_5_data_in;\r
-raw_data(6) <= buf_6_data_in;\r
-raw_data(7) <= buf_7_data_in;\r
-raw_data(8) <= buf_8_data_in;\r
-raw_data(9) <= buf_9_data_in;\r
-raw_data(10) <= buf_10_data_in;\r
-raw_data(11) <= buf_11_data_in;\r
-raw_data(12) <= buf_12_data_in;\r
-raw_data(13) <= buf_13_data_in;\r
-raw_data(14) <= buf_14_data_in;\r
-raw_data(15) <= buf_15_data_in;\r
-\r
-ped_data(0) <= ped_0_data_in;\r
-ped_data(1) <= ped_1_data_in;\r
-ped_data(2) <= ped_2_data_in;\r
-ped_data(3) <= ped_3_data_in;\r
-ped_data(4) <= ped_4_data_in;\r
-ped_data(5) <= ped_5_data_in;\r
-ped_data(6) <= ped_6_data_in;\r
-ped_data(7) <= ped_7_data_in;\r
-ped_data(8) <= ped_8_data_in;\r
-ped_data(9) <= ped_9_data_in;\r
-ped_data(10) <= ped_10_data_in;\r
-ped_data(11) <= ped_11_data_in;\r
-ped_data(12) <= ped_12_data_in;\r
-ped_data(13) <= ped_13_data_in;\r
-ped_data(14) <= ped_14_data_in;\r
-ped_data(15) <= ped_15_data_in;\r
-\r
-thr_data(0) <= thr_0_data_in;\r
-thr_data(1) <= thr_1_data_in;\r
-thr_data(2) <= thr_2_data_in;\r
-thr_data(3) <= thr_3_data_in;\r
-thr_data(4) <= thr_4_data_in;\r
-thr_data(5) <= thr_5_data_in;\r
-thr_data(6) <= thr_6_data_in;\r
-thr_data(7) <= thr_7_data_in;\r
-thr_data(8) <= thr_8_data_in;\r
-thr_data(9) <= thr_9_data_in;\r
-thr_data(10) <= thr_10_data_in;\r
-thr_data(11) <= thr_11_data_in;\r
-thr_data(12) <= thr_12_data_in;\r
-thr_data(13) <= thr_13_data_in;\r
-thr_data(14) <= thr_14_data_in;\r
-thr_data(15) <= thr_15_data_in;\r
+raw_data(0) <= BUF_0_DATA_IN;\r
+raw_data(1) <= BUF_1_DATA_IN;\r
+raw_data(2) <= BUF_2_DATA_IN;\r
+raw_data(3) <= BUF_3_DATA_IN;\r
+raw_data(4) <= BUF_4_DATA_IN;\r
+raw_data(5) <= BUF_5_DATA_IN;\r
+raw_data(6) <= BUF_6_DATA_IN;\r
+raw_data(7) <= BUF_7_DATA_IN;\r
+raw_data(8) <= BUF_8_DATA_IN;\r
+raw_data(9) <= BUF_9_DATA_IN;\r
+raw_data(10) <= BUF_10_DATA_IN;\r
+raw_data(11) <= BUF_11_DATA_IN;\r
+raw_data(12) <= BUF_12_DATA_IN;\r
+raw_data(13) <= BUF_13_DATA_IN;\r
+raw_data(14) <= BUF_14_DATA_IN;\r
+raw_data(15) <= BUF_15_DATA_IN;\r
+\r
+ped_data(0) <= PED_0_DATA_IN;\r
+ped_data(1) <= PED_1_DATA_IN;\r
+ped_data(2) <= PED_2_DATA_IN;\r
+ped_data(3) <= PED_3_DATA_IN;\r
+ped_data(4) <= PED_4_DATA_IN;\r
+ped_data(5) <= PED_5_DATA_IN;\r
+ped_data(6) <= PED_6_DATA_IN;\r
+ped_data(7) <= PED_7_DATA_IN;\r
+ped_data(8) <= PED_8_DATA_IN;\r
+ped_data(9) <= PED_9_DATA_IN;\r
+ped_data(10) <= PED_10_DATA_IN;\r
+ped_data(11) <= PED_11_DATA_IN;\r
+ped_data(12) <= PED_12_DATA_IN;\r
+ped_data(13) <= PED_13_DATA_IN;\r
+ped_data(14) <= PED_14_DATA_IN;\r
+ped_data(15) <= PED_15_DATA_IN;\r
+\r
+thr_data(0) <= THR_0_DATA_IN;\r
+thr_data(1) <= THR_1_DATA_IN;\r
+thr_data(2) <= THR_2_DATA_IN;\r
+thr_data(3) <= THR_3_DATA_IN;\r
+thr_data(4) <= THR_4_DATA_IN;\r
+thr_data(5) <= THR_5_DATA_IN;\r
+thr_data(6) <= THR_6_DATA_IN;\r
+thr_data(7) <= THR_7_DATA_IN;\r
+thr_data(8) <= THR_8_DATA_IN;\r
+thr_data(9) <= THR_9_DATA_IN;\r
+thr_data(10) <= THR_10_DATA_IN;\r
+thr_data(11) <= THR_11_DATA_IN;\r
+thr_data(12) <= THR_12_DATA_IN;\r
+thr_data(13) <= THR_13_DATA_IN;\r
+thr_data(14) <= THR_14_DATA_IN;\r
+thr_data(15) <= THR_15_DATA_IN;\r
\r
\r
---------------------------------------------------------------------------\r
---------------------------------------------------------------------------\r
THE_FRMCTR_CHECK: frmctr_check\r
port map(\r
- CLK_IN => clk_in,\r
+ CLK_IN => CLK_IN,\r
GOODDATA_IN => buf_gooddata,\r
- FRAMECOUNTER_IN => loc_frm_ctr,\r
+ FRAMECOUNTER_IN => std_logic_vector(loc_frm_ctr),\r
FRM_NR_0_IN => raw_data(0)(17 downto 14),\r
FRM_NR_1_IN => raw_data(1)(17 downto 14),\r
FRM_NR_2_IN => raw_data(2)(17 downto 14),\r
---------------------------------------------------------------------------\r
THE_REF_ROW_SEL: ref_row_sel\r
port map(\r
- CLK_IN => clk_in,\r
+ CLK_IN => CLK_IN,\r
READY_IN => buf_ready,\r
GOODDATA_IN => buf_gooddata,\r
FRAME_0_IN => raw_data(0)(29 downto 18),\r
---------------------------------------------------------------------------\r
\r
-- state registers\r
-STATE_MEM: process( clk_in )\r
+STATE_MEM: process( CLK_IN )\r
begin\r
- if( rising_edge(clk_in) ) then\r
- if( reset_in = '1' ) then\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
CURRENT_STATE <= SLEEP;\r
wait_frames <= '0';\r
ld_frm_ctr <= '0';\r
errors(0) <= frame_apv_error;\r
\r
-- state transitions\r
-STATE_TRANSFORM: process( CURRENT_STATE, eds_avail_in, dhdr_buf_full_in, last_frame, multi_frame, frame_busy,\r
+STATE_TRANSFORM: process( CURRENT_STATE, EDS_AVAIL_IN, DHDR_BUF_FULL_IN, last_frame, multi_frame, frame_busy,\r
buffers_ready, buffers_valid, frame_ctr_error, frame_row_error, frame_apv_error,\r
buf_addr_done, buf_half )\r
begin\r
case CURRENT_STATE is\r
-- BUG: we need to delay this by some clock cycles to be sure that enough space is available in IPU stage.\r
-- calculation of max_num_words takes some time.\r
- when SLEEP => if( (eds_avail_in = '1') and (dhdr_buf_full_in = '0') ) then\r
+ when SLEEP => if( (EDS_AVAIL_IN = '1') and (DHDR_BUF_FULL_IN = '0') ) then\r
NEXT_STATE <= LOADFC;\r
next_ld_frm_ctr <= '1';\r
else\r
---------------------------------------------------------------------------\r
-- Buffer address counter, fetches raw data and pedestal values from EBRs\r
---------------------------------------------------------------------------\r
-THE_BUF_ADDR_COUNTER_PROC: process( clk_in )\r
+THE_BUF_ADDR_COUNTER_PROC: process( CLK_IN )\r
begin\r
- if( rising_edge(clk_in) ) then\r
- if ( (buf_addr_rst = '1') or (reset_in = '1') ) then\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( (buf_addr_rst = '1') or (RESET_IN = '1') ) then\r
buf_addr <= (others => '0');\r
elsif( buf_addr_ce = '1' ) then\r
buf_addr <= buf_addr + 1;\r
\r
next_buf_addr_done <= '1' when ( buf_addr = "111110" ) else '0';\r
\r
-THE_HALF_PROC: process( clk_in )\r
+THE_HALF_PROC: process( CLK_IN )\r
begin\r
- if( rising_edge(clk_in) ) then\r
- if ( (ld_frm_ctr = '1') or (reset_in = '1') ) then\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( (ld_frm_ctr = '1') or (RESET_IN = '1') ) then\r
buf_half <= '0';\r
elsif( (buf_addr_done = '1') and (buf_half = '0') ) then\r
buf_half <= '1';\r
end if;\r
end process THE_HALF_PROC;\r
\r
-raw_addr <= buf_half & buf_addr;\r
+raw_addr <= buf_half & std_logic_vector(buf_addr);\r
\r
---------------------------------------------------------------------------\r
-- local frame counter, loaded / counted by SM for checking\r
---------------------------------------------------------------------------\r
-THE_LOC_FRAME_COUNTER_PROC: process( clk_in )\r
+THE_LOC_FRAME_COUNTER_PROC: process( CLK_IN )\r
begin\r
- if( rising_edge(clk_in) ) then\r
- if ( reset_in = '1' ) then\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( RESET_IN = '1' ) then\r
loc_frm_ctr <= (others => '0');\r
to_do_ctr <= (others => '0');\r
done_ctr <= (others => '0');\r
elsif( ld_frm_ctr = '1' ) then\r
- loc_frm_ctr <= eds_data_in(39 downto 36);\r
- to_do_ctr <= eds_data_in(35 downto 32);\r
+ loc_frm_ctr <= unsigned(EDS_DATA_IN(39 downto 36));\r
+ to_do_ctr <= unsigned(EDS_DATA_IN(35 downto 32));\r
done_ctr <= (others => '0');\r
elsif( ce_frm_ctr = '1' ) then\r
loc_frm_ctr <= loc_frm_ctr + 1; -- local frame counter\r
next_cleaned_up <= '1' when ( done_ctr = x"0" ) else '0';\r
\r
-- insert administration words if more than one frame is requested (MULTIFRAME)\r
-next_multi_frame <= '1' when ( eds_data_in(35 downto 32) > x"1" ) else '0';\r
+next_multi_frame <= '1' when ( EDS_DATA_IN(35 downto 32) > x"1" ) else '0';\r
\r
---------------------------------------------------------------------------\r
-- synchronizing process\r
---------------------------------------------------------------------------\r
-THE_SYNC_PROC: process( clk_in )\r
+THE_SYNC_PROC: process( CLK_IN )\r
begin\r
- if( rising_edge(clk_in) ) then\r
+ if( rising_edge(CLK_IN) ) then\r
last_frame <= next_last_frame;\r
multi_frame <= next_multi_frame;\r
cleaned_up <= next_cleaned_up;\r
buf_addr_done <= next_buf_addr_done;\r
buf_frame_valid <= frame_valid;\r
- small_0_sum <= next_small_0_sum;\r
- small_1_sum <= next_small_1_sum;\r
+ small_0_sum <= unsigned(next_small_0_sum);\r
+ small_1_sum <= unsigned(next_small_1_sum);\r
max_num_words <= next_max_num_words;\r
thr_addr_qqq <= thr_addr_qq;\r
thr_addr_qq <= thr_addr_q;\r
GEN_TOC: for i in 0 to 15 generate\r
THE_BUF_TOC: buf_toc\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
- BUF_TICK_IN => buf_tick_in(i),\r
- BUF_START_IN => buf_start_in(i),\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ BUF_TICK_IN => BUF_TICK_IN(i),\r
+ BUF_START_IN => BUF_START_IN(i),\r
WAITFRAME_IN => wait_frames,\r
- FRAMES_REQD_IN => eds_data_in(35 downto 32), -- always the same\r
+ FRAMES_REQD_IN => EDS_DATA_IN(35 downto 32), -- always the same\r
BUF_LVL_IN => raw_data(i)(37 downto 30),\r
GOODDATA_OUT => buf_gooddata(i),\r
BADDATA_OUT => buf_baddata(i),\r
GEN_ALU: for i in 0 to 15 generate\r
THE_ALU: apv_pc_nc_alu\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
START_IN => ld_frm_ctr,\r
- MAX_FRAMES_IN => eds_data_in(35 downto 32),\r
- CURR_FRAME_IN => done_ctr,\r
- LOC_FRM_CTR_IN => loc_frm_ctr, -- DEBUG\r
- EDS_FRM_CTR_IN => eds_data_in(39 downto 36), -- DEBUG\r
+ MAX_FRAMES_IN => EDS_DATA_IN(35 downto 32),\r
+ CURR_FRAME_IN => std_logic_vector(done_ctr),\r
+ LOC_FRM_CTR_IN => std_logic_vector(loc_frm_ctr),\r
+ EDS_FRM_CTR_IN => EDS_DATA_IN(39 downto 36),\r
+ EDS_DATA_IN => EDS_DATA_IN, -- DEBUG\r
BUF_GOOD_IN => buf_gooddata(i),\r
BUF_BAD_IN => buf_baddata(i),\r
BUF_IGNORE_IN => buf_nodata(i),\r
ERROR_IN => errors,\r
DO_HEADER_IN => do_hdr,\r
DO_ERROR_IN => do_error,\r
- SUPPRESS_IN => eds_data_in(3), -- suppress bit\r
- EVT_TYPE_IN => eds_data_in(2 downto 0), -- RICH data configuration bits\r
+ SUPPRESS_IN => EDS_DATA_IN(3), -- suppress bit\r
+ VERBOSE_IN => VERBOSE_IN, -- add debug words\r
+ EVT_TYPE_IN => EDS_DATA_IN(2 downto 0), -- RICH data configuration bits\r
RAW_ADDR_IN => buf_raw_addr, -- delayed by one cycle\r
RAW_DATA_IN => raw_data(i),\r
PED_DATA_IN => ped_data(i),\r
\r
reset_sum <= reset_in or ld_frm_ctr;\r
\r
-THE_FIRST_ADDER: adder_5bit\r
-port map(\r
- DATAA => small_0_sum,\r
- DATAB => small_1_sum,\r
- CLOCK => clk_in,\r
- RESET => reset_sum, -- BUG\r
- CLOCKEN => '1',\r
- RESULT => small_sum(4 downto 0)\r
-);\r
+THE_FIRST_ADDER: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( reset_sum = '1' ) then\r
+ small_sum(4 downto 0) <= (others => '0');\r
+ else\r
+ small_sum(4 downto 0) <= small_0_sum + small_1_sum;\r
+ end if;\r
+ end if;\r
+end process THE_FIRST_ADDER;\r
small_sum(15 downto 5) <= (others => '0');\r
\r
-THE_ACCUMULATOR: adder_16bit\r
-port map(\r
- DATAA => small_sum,\r
- DATAB => total_sum,\r
- CLOCK => clk_in,\r
- RESET => reset_sum, -- BUG\r
- CLOCKEN => '1',\r
- RESULT => total_sum\r
-);\r
+THE_ACCUMULATOR: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( reset_sum = '1' ) then\r
+ total_sum <= (others => '0');\r
+ else\r
+ total_sum <= total_sum + small_sum;\r
+ end if;\r
+ end if;\r
+end process THE_ACCUMULATOR;\r
+\r
\r
\r
---------------------------------------------------------------------------\r
---------------------------------------------------------------------------\r
DHDR_DATA_OUT(31 downto 29) <= "000"; -- reserved bits\r
DHDR_DATA_OUT(28) <= '0'; -- packbit, MUST NEVER BE SET IN FEs\r
-DHDR_DATA_OUT(27 downto 24) <= eds_data_in(7 downto 4);\r
-DHDR_DATA_OUT(23 downto 16) <= eds_data_in(15 downto 8);\r
-DHDR_DATA_OUT(15 downto 0) <= eds_data_in(31 downto 16);\r
-DHDR_LENGTH_OUT <= total_sum;\r
+DHDR_DATA_OUT(27 downto 24) <= EDS_DATA_IN(7 downto 4);\r
+DHDR_DATA_OUT(23 downto 16) <= EDS_DATA_IN(15 downto 8);\r
+DHDR_DATA_OUT(15 downto 0) <= EDS_DATA_IN(31 downto 16);\r
+DHDR_LENGTH_OUT <= std_logic_vector(total_sum);\r
DHDR_STORE_OUT <= eds_wr;\r
\r
---------------------------------------------------------------------------\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
architecture behavioral of pulse_stretch is\r
\r
-- normal signals\r
-signal pulse_cnt : std_logic_vector(3 downto 0);\r
+signal pulse_cnt : unsigned(3 downto 0);\r
signal pulse_cnt_ce : std_logic;\r
signal pulse_x : std_logic;\r
signal pulse : std_logic;\r
begin\r
\r
-- Pulse length counter\r
-THE_PULSE_LENGTH_CTR: process( clk_in )\r
+THE_PULSE_LENGTH_CTR: process( CLK_IN )\r
begin\r
- if( rising_edge(clk_in) ) then\r
- if ( reset_in = '1' ) then\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( RESET_IN = '1' ) then\r
pulse_cnt <= (others => '0');\r
elsif( pulse_cnt_ce = '1' ) then\r
pulse_cnt <= pulse_cnt + 1;\r
end if;\r
end process THE_PULSE_LENGTH_CTR;\r
\r
-pulse_cnt_ce <= '1' when ( (start_in = '1') or (pulse_cnt /= x"0") ) else '0';\r
+pulse_cnt_ce <= '1' when ( (START_IN = '1') or (pulse_cnt /= x"0") ) else '0';\r
\r
pulse_x <= '1' when ( (pulse_cnt(2) = '1') or (pulse_cnt(3) = '1') ) else '0';\r
\r
-- Syanchronize it\r
-THE_SYNC_PROC: process( clk_in )\r
+THE_SYNC_PROC: process( CLK_IN )\r
begin\r
- if( rising_edge(clk_in) ) then\r
- if( reset_in = '1' ) then\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
pulse <= '0';\r
else\r
pulse <= pulse_x;\r
\r
\r
-- output signals\r
-pulse_out <= pulse;\r
-debug_out(15 downto 4) <= (others => '0');\r
-debug_out(3 downto 0) <= pulse_cnt;\r
+PULSE_OUT <= pulse;\r
+DEBUG_OUT(15 downto 4) <= (others => '0');\r
+DEBUG_OUT(3 downto 0) <= std_logic_vector(pulse_cnt);\r
\r
end behavioral;\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
begin\r
\r
-- toggle flip flop in clock domain A\r
-THE_TOGGLE_FF_PROC: process( clk_a_in )\r
+THE_TOGGLE_FF_PROC: process( CLK_A_IN )\r
begin\r
- if( rising_edge(clk_a_in) ) then\r
- if ( reset_a_in = '1' ) then\r
+ if( rising_edge(CLK_A_IN) ) then\r
+ if ( RESET_A_IN = '1' ) then\r
toggle_ff <= '0';\r
- elsif( pulse_a_in = '1' ) then\r
+ elsif( PULSE_A_IN = '1' ) then\r
toggle_ff <= not toggle_ff;\r
end if;\r
end if;\r
end process THE_TOGGLE_FF_PROC;\r
\r
-- synchronizing stage for clock domain B\r
-THE_SYNC_STAGE_PROC: process( clk_b_in )\r
+THE_SYNC_STAGE_PROC: process( CLK_B_IN )\r
begin\r
- if( rising_edge(clk_b_in) ) then\r
- if( reset_b_in = '1' ) then\r
+ if( rising_edge(CLK_B_IN) ) then\r
+ if( RESET_B_IN = '1' ) then\r
sync_q <= '0'; sync_qq <= '0'; sync_qqq <= '0';\r
else\r
sync_qqq <= sync_qq;\r
end process THE_SYNC_STAGE_PROC;\r
\r
-- output pulse registering\r
-THE_OUTPUT_PULSE_PROC: process( clk_b_in )\r
+THE_OUTPUT_PULSE_PROC: process( CLK_B_IN )\r
begin\r
- if( rising_edge(clk_b_in) ) then\r
- if( reset_b_in = '1' ) then\r
+ if( rising_edge(CLK_B_IN) ) then\r
+ if( RESET_B_IN = '1' ) then\r
pulse_b <= '0';\r
else\r
pulse_b <= sync_qqq xor sync_qq;\r
end process THE_OUTPUT_PULSE_PROC;\r
\r
-- output signals\r
-pulse_b_out <= pulse_b;\r
+PULSE_B_OUT <= pulse_b;\r
\r
end behavioral;\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
\r
-entity raw_buf_stage_new is\r
+entity raw_buf_stage is\r
port(\r
CLK_IN : in std_logic; -- 100MHz local clock\r
CLK_APV_IN : in std_logic; -- 40MHz APV clock\r
BUF_13_DATA_OUT : out std_logic_vector(37 downto 0);\r
BUF_14_DATA_OUT : out std_logic_vector(37 downto 0);\r
BUF_15_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ -- DEBUG SPECIAL\r
+ DBG_0_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_1_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_2_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_3_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_4_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_5_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_6_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_7_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_8_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_9_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_10_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_11_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_12_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_13_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_14_OUT : out std_logic_vector(15 downto 0);\r
+ DBG_15_OUT : out std_logic_vector(15 downto 0);\r
-- Debug signals\r
DEBUG_OUT : out std_logic_vector(63 downto 0)\r
);\r
end;\r
\r
-architecture behavioral of raw_buf_stage_new is\r
+architecture behavioral of raw_buf_stage is\r
\r
-- Reset signals, combinatorial and registered\r
signal next_reset_all : std_logic;\r
type buf_level_t is array (0 to 15) of std_logic_vector(7 downto 0);\r
signal buf_level : buf_level_t;\r
\r
+type buf_dbg_t is array (0 to 15) of std_logic_vector(15 downto 0);\r
+signal buf_dbg : buf_dbg_t;\r
+\r
signal buf_tick : std_logic_vector(15 downto 0);\r
signal buf_start : std_logic_vector(15 downto 0);\r
signal buf_ready : std_logic_vector(15 downto 0);\r
---------------------------------------------------------------------------\r
-- Reset handling\r
---------------------------------------------------------------------------\r
-next_reset_all <= (reset_in or apv_reset_in); -- 40MHz clock domain\r
-next_reset <= (reset_in or apv_reset_in); -- 100MHz clock domain\r
+next_reset_all <= (RESET_IN or APV_RESET_IN); -- 40MHz clock domain\r
+next_reset <= (RESET_IN or APV_RESET_IN); -- 100MHz clock domain\r
\r
THE_RESET_SYNC: state_sync\r
port map(\r
STATE_A_IN => next_reset_all,\r
- CLK_B_IN => clk_apv_in,\r
+ CLK_B_IN => CLK_APV_IN,\r
RESET_B_IN => '0',\r
STATE_B_OUT => reset_all\r
);\r
---------------------------------------------------------------------------\r
next_raw_buf_full <= '1' when ( buf_full /= x"0000" ) else '0';\r
\r
-THE_SYNC_PROC: process( clk_in )\r
+THE_SYNC_PROC: process( CLK_IN )\r
begin\r
- if( rising_edge(clk_in) ) then\r
+ if( rising_edge(CLK_IN) ) then\r
raw_buf_full <= next_raw_buf_full;\r
reset <= next_reset_all;\r
end if;\r
---------------------------------------------------------------------------\r
\r
-- Aliasing the inputs for the generator\r
-adc_data(7) <= adc0_7_data_in;\r
-adc_data(6) <= adc0_6_data_in;\r
-adc_data(5) <= adc0_5_data_in;\r
-adc_data(4) <= adc0_4_data_in;\r
-adc_data(3) <= adc0_3_data_in;\r
-adc_data(2) <= adc0_2_data_in;\r
-adc_data(1) <= adc0_1_data_in;\r
-adc_data(0) <= adc0_0_data_in;\r
+adc_data(7) <= ADC0_7_DATA_IN;\r
+adc_data(6) <= ADC0_6_DATA_IN;\r
+adc_data(5) <= ADC0_5_DATA_IN;\r
+adc_data(4) <= ADC0_4_DATA_IN;\r
+adc_data(3) <= ADC0_3_DATA_IN;\r
+adc_data(2) <= ADC0_2_DATA_IN;\r
+adc_data(1) <= ADC0_1_DATA_IN;\r
+adc_data(0) <= ADC0_0_DATA_IN;\r
\r
-- generate 8 identical blocks, one per APV connected to ADC0\r
GEN_ADC0: for i in 0 to 7 generate\r
-- APV locker, handles synchronisation and all the other stuff\r
THE_APV_LOCKER: apv_locker\r
port map(\r
- CLK_APV_IN => clk_apv_in,\r
+ CLK_APV_IN => CLK_APV_IN,\r
RESET_IN => reset_all,\r
- SYNC_IN => apv_sync_in,\r
+ SYNC_IN => APV_SYNC_IN,\r
ADC_RAW_IN => adc_data(i),\r
- ADC_VALID_IN => adc0_valid_in,\r
- APV_ON_IN => apv_on_in(i),\r
- BIT_LOW_IN => bit_low_in,\r
- BIT_HIGH_IN => bit_high_in,\r
- FL_LOW_IN => fl_low_in,\r
- FL_HIGH_IN => fl_high_in,\r
+ ADC_VALID_IN => ADC0_VALID_IN,\r
+ APV_ON_IN => APV_ON_IN(i),\r
+ BIT_LOW_IN => BIT_LOW_IN,\r
+ BIT_HIGH_IN => BIT_HIGH_IN,\r
+ FL_LOW_IN => FL_LOW_IN,\r
+ FL_HIGH_IN => FL_HIGH_IN,\r
STATUS_IGNORE_OUT => apv_status(i)(1),\r
STATUS_UNKNOWN_OUT => apv_status(i)(6),\r
STATUS_BADADC_OUT => apv_status(i)(7),\r
-- raw buffer, stores frame data, all outputs are 100MHz synchronized\r
THE_APV_RAW_BUFFER: apv_raw_buffer\r
port map(\r
- CLK_APV_IN => clk_apv_in,\r
+ CLK_APV_IN => CLK_APV_IN,\r
RESET_IN => reset_all,\r
- FRM_REQD_IN => apv_frame_reqd_in,\r
- MAX_TRG_NUM_IN => max_trg_num_in,\r
+ FRM_REQD_IN => APV_FRAME_REQD_IN,\r
+ MAX_TRG_NUM_IN => MAX_TRG_NUM_IN,\r
ADC_ANALOG_IN => apv_analog(i),\r
ADC_START_IN => apv_start(i),\r
ADC_LAST_IN => apv_last(i),\r
ADC_RAW_IN => apv_data(i),\r
ADC_STATUS_IN => apv_status(i),\r
ADC_FRAME_IN => apv_frame(i),\r
- BUF_CLK_IN => clk_in,\r
+ BUF_CLK_IN => CLK_IN,\r
BUF_RESET_IN => reset,\r
BUF_START_OUT => buf_start(i),\r
BUF_READY_OUT => buf_ready(i),\r
BUF_LEVEL_OUT => buf_level(i)(4 downto 0),\r
BUF_TICKMARK_OUT => buf_tick(i),\r
BUF_FULL_OUT => buf_full(i),\r
- DEBUG_OUT => open\r
+ DEBUG_OUT => buf_dbg(i) --open\r
);\r
\r
end generate GEN_ADC0;\r
---------------------------------------------------------------------------\r
\r
-- Aliasing the inputs for the generator\r
-adc_data(15) <= adc1_7_data_in;\r
-adc_data(14) <= adc1_6_data_in;\r
-adc_data(13) <= adc1_5_data_in;\r
-adc_data(12) <= adc1_4_data_in;\r
-adc_data(11) <= adc1_3_data_in;\r
-adc_data(10) <= adc1_2_data_in;\r
-adc_data(9) <= adc1_1_data_in;\r
-adc_data(8) <= adc1_0_data_in;\r
+adc_data(15) <= ADC1_7_DATA_IN;\r
+adc_data(14) <= ADC1_6_DATA_IN;\r
+adc_data(13) <= ADC1_5_DATA_IN;\r
+adc_data(12) <= ADC1_4_DATA_IN;\r
+adc_data(11) <= ADC1_3_DATA_IN;\r
+adc_data(10) <= ADC1_2_DATA_IN;\r
+adc_data(9) <= ADC1_1_DATA_IN;\r
+adc_data(8) <= ADC1_0_DATA_IN;\r
\r
-- generate 8 identical blocks, one per APV connected to ADC1\r
GEN_ADC1: for i in 8 to 15 generate\r
-- APV locker, handles synchronisation and all the other stuff\r
THE_APV_LOCKER: apv_locker\r
port map(\r
- CLK_APV_IN => clk_apv_in,\r
+ CLK_APV_IN => CLK_APV_IN,\r
RESET_IN => reset_all,\r
- SYNC_IN => apv_sync_in,\r
+ SYNC_IN => APV_SYNC_IN,\r
ADC_RAW_IN => adc_data(i),\r
- ADC_VALID_IN => adc1_valid_in,\r
+ ADC_VALID_IN => ADC1_VALID_IN,\r
APV_ON_IN => apv_on_in(i),\r
- BIT_LOW_IN => bit_low_in,\r
- BIT_HIGH_IN => bit_high_in,\r
- FL_LOW_IN => fl_low_in,\r
- FL_HIGH_IN => fl_high_in,\r
+ BIT_LOW_IN => BIT_LOW_IN,\r
+ BIT_HIGH_IN => BIT_HIGH_IN,\r
+ FL_LOW_IN => FL_LOW_IN,\r
+ FL_HIGH_IN => FL_HIGH_IN,\r
STATUS_IGNORE_OUT => apv_status(i)(1),\r
STATUS_UNKNOWN_OUT => apv_status(i)(6),\r
STATUS_BADADC_OUT => apv_status(i)(7),\r
-- raw buffer, stores frame data, all outputs are 100MHz synchronized\r
THE_APV_RAW_BUFFER: apv_raw_buffer\r
port map(\r
- CLK_APV_IN => clk_apv_in,\r
+ CLK_APV_IN => CLK_APV_IN,\r
RESET_IN => reset_all,\r
- FRM_REQD_IN => apv_frame_reqd_in,\r
- MAX_TRG_NUM_IN => max_trg_num_in,\r
+ FRM_REQD_IN => APV_FRAME_REQD_IN,\r
+ MAX_TRG_NUM_IN => MAX_TRG_NUM_IN,\r
ADC_ANALOG_IN => apv_analog(i),\r
ADC_START_IN => apv_start(i),\r
ADC_LAST_IN => apv_last(i),\r
ADC_RAW_IN => apv_data(i),\r
ADC_STATUS_IN => apv_status(i),\r
ADC_FRAME_IN => apv_frame(i),\r
- BUF_CLK_IN => clk_in,\r
+ BUF_CLK_IN => CLK_IN,\r
BUF_RESET_IN => reset,\r
BUF_START_OUT => buf_start(i),\r
BUF_READY_OUT => buf_ready(i),\r
BUF_LEVEL_OUT => buf_level(i)(4 downto 0),\r
BUF_TICKMARK_OUT => buf_tick(i),\r
BUF_FULL_OUT => buf_full(i),\r
- DEBUG_OUT => open\r
+ DEBUG_OUT => buf_dbg(i) --open\r
);\r
\r
end generate GEN_ADC1;\r
-- Output signals\r
---------------------------------------------------------------------------\r
\r
-buf_full_out <= raw_buf_full;\r
-buf_tick_out <= buf_tick; -- needed for TOCs\r
-buf_start_out <= buf_start; -- needed for TOCs\r
-buf_ready_out <= buf_ready; -- debug signal\r
+BUF_FULL_OUT <= raw_buf_full;\r
+BUF_TICK_OUT <= buf_tick; -- needed for TOCs\r
+BUF_START_OUT <= buf_start; -- needed for TOCs\r
+BUF_READY_OUT <= buf_ready; -- debug signal\r
\r
-- Alias the outputs from generator\r
-buf_0_data_out(17 downto 0) <= buf_data(0);\r
-buf_0_data_out(29 downto 18) <= buf_frame(0);\r
-buf_0_data_out(37 downto 30) <= buf_level(0);\r
-buf_1_data_out(17 downto 0) <= buf_data(1);\r
-buf_1_data_out(29 downto 18) <= buf_frame(1);\r
-buf_1_data_out(37 downto 30) <= buf_level(1);\r
-buf_2_data_out(17 downto 0) <= buf_data(2);\r
-buf_2_data_out(29 downto 18) <= buf_frame(2);\r
-buf_2_data_out(37 downto 30) <= buf_level(2);\r
-buf_3_data_out(17 downto 0) <= buf_data(3);\r
-buf_3_data_out(29 downto 18) <= buf_frame(3);\r
-buf_3_data_out(37 downto 30) <= buf_level(3);\r
-buf_4_data_out(17 downto 0) <= buf_data(4);\r
-buf_4_data_out(29 downto 18) <= buf_frame(4);\r
-buf_4_data_out(37 downto 30) <= buf_level(4);\r
-buf_5_data_out(17 downto 0) <= buf_data(5);\r
-buf_5_data_out(29 downto 18) <= buf_frame(5);\r
-buf_5_data_out(37 downto 30) <= buf_level(5);\r
-buf_6_data_out(17 downto 0) <= buf_data(6);\r
-buf_6_data_out(29 downto 18) <= buf_frame(6);\r
-buf_6_data_out(37 downto 30) <= buf_level(6);\r
-buf_7_data_out(17 downto 0) <= buf_data(7);\r
-buf_7_data_out(29 downto 18) <= buf_frame(7);\r
-buf_7_data_out(37 downto 30) <= buf_level(7);\r
-buf_8_data_out(17 downto 0) <= buf_data(8);\r
-buf_8_data_out(29 downto 18) <= buf_frame(8);\r
-buf_8_data_out(37 downto 30) <= buf_level(8);\r
-buf_9_data_out(17 downto 0) <= buf_data(9);\r
-buf_9_data_out(29 downto 18) <= buf_frame(9);\r
-buf_9_data_out(37 downto 30) <= buf_level(9);\r
-buf_10_data_out(17 downto 0) <= buf_data(10);\r
-buf_10_data_out(29 downto 18) <= buf_frame(10);\r
-buf_10_data_out(37 downto 30) <= buf_level(10);\r
-buf_11_data_out(17 downto 0) <= buf_data(11);\r
-buf_11_data_out(29 downto 18) <= buf_frame(11);\r
-buf_11_data_out(37 downto 30) <= buf_level(11);\r
-buf_12_data_out(17 downto 0) <= buf_data(12);\r
-buf_12_data_out(29 downto 18) <= buf_frame(12);\r
-buf_12_data_out(37 downto 30) <= buf_level(12);\r
-buf_13_data_out(17 downto 0) <= buf_data(13);\r
-buf_13_data_out(29 downto 18) <= buf_frame(13);\r
-buf_13_data_out(37 downto 30) <= buf_level(13);\r
-buf_14_data_out(17 downto 0) <= buf_data(14);\r
-buf_14_data_out(29 downto 18) <= buf_frame(14);\r
-buf_14_data_out(37 downto 30) <= buf_level(14);\r
-buf_15_data_out(17 downto 0) <= buf_data(15);\r
-buf_15_data_out(29 downto 18) <= buf_frame(15);\r
-buf_15_data_out(37 downto 30) <= buf_level(15);\r
+BUF_0_DATA_OUT(17 downto 0) <= buf_data(0);\r
+BUF_0_DATA_OUT(29 downto 18) <= buf_frame(0);\r
+BUF_0_DATA_OUT(37 downto 30) <= buf_level(0);\r
+BUF_1_DATA_OUT(17 downto 0) <= buf_data(1);\r
+BUF_1_DATA_OUT(29 downto 18) <= buf_frame(1);\r
+BUF_1_DATA_OUT(37 downto 30) <= buf_level(1);\r
+BUF_2_DATA_OUT(17 downto 0) <= buf_data(2);\r
+BUF_2_DATA_OUT(29 downto 18) <= buf_frame(2);\r
+BUF_2_DATA_OUT(37 downto 30) <= buf_level(2);\r
+BUF_3_DATA_OUT(17 downto 0) <= buf_data(3);\r
+BUF_3_DATA_OUT(29 downto 18) <= buf_frame(3);\r
+BUF_3_DATA_OUT(37 downto 30) <= buf_level(3);\r
+BUF_4_DATA_OUT(17 downto 0) <= buf_data(4);\r
+BUF_4_DATA_OUT(29 downto 18) <= buf_frame(4);\r
+BUF_4_DATA_OUT(37 downto 30) <= buf_level(4);\r
+BUF_5_DATA_OUT(17 downto 0) <= buf_data(5);\r
+BUF_5_DATA_OUT(29 downto 18) <= buf_frame(5);\r
+BUF_5_DATA_OUT(37 downto 30) <= buf_level(5);\r
+BUF_6_DATA_OUT(17 downto 0) <= buf_data(6);\r
+BUF_6_DATA_OUT(29 downto 18) <= buf_frame(6);\r
+BUF_6_DATA_OUT(37 downto 30) <= buf_level(6);\r
+BUF_7_DATA_OUT(17 downto 0) <= buf_data(7);\r
+BUF_7_DATA_OUT(29 downto 18) <= buf_frame(7);\r
+BUF_7_DATA_OUT(37 downto 30) <= buf_level(7);\r
+BUF_8_DATA_OUT(17 downto 0) <= buf_data(8);\r
+BUF_8_DATA_OUT(29 downto 18) <= buf_frame(8);\r
+BUF_8_DATA_OUT(37 downto 30) <= buf_level(8);\r
+BUF_9_DATA_OUT(17 downto 0) <= buf_data(9);\r
+BUF_9_DATA_OUT(29 downto 18) <= buf_frame(9);\r
+BUF_9_DATA_OUT(37 downto 30) <= buf_level(9);\r
+BUF_10_DATA_OUT(17 downto 0) <= buf_data(10);\r
+BUF_10_DATA_OUT(29 downto 18) <= buf_frame(10);\r
+BUF_10_DATA_OUT(37 downto 30) <= buf_level(10);\r
+BUF_11_DATA_OUT(17 downto 0) <= buf_data(11);\r
+BUF_11_DATA_OUT(29 downto 18) <= buf_frame(11);\r
+BUF_11_DATA_OUT(37 downto 30) <= buf_level(11);\r
+BUF_12_DATA_OUT(17 downto 0) <= buf_data(12);\r
+BUF_12_DATA_OUT(29 downto 18) <= buf_frame(12);\r
+BUF_12_DATA_OUT(37 downto 30) <= buf_level(12);\r
+BUF_13_DATA_OUT(17 downto 0) <= buf_data(13);\r
+BUF_13_DATA_OUT(29 downto 18) <= buf_frame(13);\r
+BUF_13_DATA_OUT(37 downto 30) <= buf_level(13);\r
+BUF_14_DATA_OUT(17 downto 0) <= buf_data(14);\r
+BUF_14_DATA_OUT(29 downto 18) <= buf_frame(14);\r
+BUF_14_DATA_OUT(37 downto 30) <= buf_level(14);\r
+BUF_15_DATA_OUT(17 downto 0) <= buf_data(15);\r
+BUF_15_DATA_OUT(29 downto 18) <= buf_frame(15);\r
+BUF_15_DATA_OUT(37 downto 30) <= buf_level(15);\r
\r
---------------------------------------------------------------------------\r
-- DEBUG signals\r
---------------------------------------------------------------------------\r
-debug_out <= debug;\r
+DBG_0_OUT <= buf_dbg(0);\r
+DBG_1_OUT <= buf_dbg(1);\r
+DBG_2_OUT <= buf_dbg(2);\r
+DBG_3_OUT <= buf_dbg(3);\r
+DBG_4_OUT <= buf_dbg(4);\r
+DBG_5_OUT <= buf_dbg(5);\r
+DBG_6_OUT <= buf_dbg(6);\r
+DBG_7_OUT <= buf_dbg(7);\r
+DBG_8_OUT <= buf_dbg(8);\r
+DBG_9_OUT <= buf_dbg(9);\r
+DBG_10_OUT <= buf_dbg(10);\r
+DBG_11_OUT <= buf_dbg(11);\r
+DBG_12_OUT <= buf_dbg(12);\r
+DBG_13_OUT <= buf_dbg(13);\r
+DBG_14_OUT <= buf_dbg(14);\r
+DBG_15_OUT <= buf_dbg(15);\r
+\r
+DEBUG_OUT <= debug;\r
\r
end behavioral;\r
\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+-- Comment: better than the first version, but still a lot of optimization possible.\r
+\r
+-- (1) no more compare tags here. some steps in the FSM can be taken out.\r
+-- (2) no more rst_lvl1_counter signal anymore in the CCR. to be replaced!\r
+\r
+entity real_trg_handler is\r
+port(\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
+ TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
+ APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse)\r
+ TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
+ TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
+ TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
+ TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
+ TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
+ TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint\r
+ TRG_TOO_LONG_OUT : out std_logic; -- only for TRG0 channel\r
+ SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number\r
+ -- TRB LVL1 channel signals\r
+ TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag\r
+ TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number\r
+ TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 4bit trigger type\r
+ TRB_TINFO_IN : in std_logic_vector(23 downto 0); -- LVL1 24bit trigger information\r
+ TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB\r
+ TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger\r
+ LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_COUNTER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_LD_COUNTER_IN : in std_logic;\r
+ BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator\r
+ --\r
+ APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine\r
+ APV_TRGSTART_OUT : out std_logic; -- start an APV trigger state machine\r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data\r
+ EDS_WE_OUT : out std_logic; -- EDS write enable (general interface)\r
+ EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level\r
+ EDS_READY_OUT : out std_logic; -- APV trigger sequence done\r
+ DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end;\r
+\r
+architecture behavioral of real_trg_handler is\r
+\r
+-- state machine signals\r
+type STATES is (SLEEP, STORE, START, COUNT, RELAX, CHECK, WAPV, WLVL1, TRBS,\r
+ WEDS, WDEL0, WDEL1, WBUSY, DONE, CNTEVT, BADTRG, TTLTRG);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+-- normal signals\r
+signal trg_comb : std_logic_vector(3 downto 0); -- TRB or hardware inputs\r
+signal trg_q : std_logic_vector(3 downto 0);\r
+signal trg_qq : std_logic_vector(3 downto 0);\r
+signal trg_qqq : std_logic_vector(3 downto 0);\r
+signal trg_qqqq : std_logic_vector(3 downto 0);\r
+signal trg_edge : std_logic_vector(3 downto 0);\r
+signal decoded_trg : std_logic_vector(3 downto 0);\r
+signal todo_start : std_logic_vector(3 downto 0);\r
+signal trg_found : std_logic;\r
+\r
+signal evtctr : unsigned(15 downto 0); -- event counter\r
+signal ce_evtctr : std_logic;\r
+signal next_ce_evtctr : std_logic;\r
+signal frmctr : unsigned(3 downto 0); -- frame counter\r
+signal ce_frmctr : std_logic;\r
+signal next_ce_frmctr : std_logic;\r
+signal todo_ctr : unsigned(3 downto 0);\r
+signal next_todo_done : std_logic;\r
+signal todo_done : std_logic;\r
+signal next_apv_trgstart : std_logic;\r
+signal apv_trgstart : std_logic;\r
+signal eds_data : std_logic_vector(39 downto 0);\r
+signal eds_start : std_logic;\r
+signal next_eds_start : std_logic;\r
+signal eds_we : std_logic;\r
+signal next_eds_we : std_logic;\r
+signal next_eds_ready : std_logic;\r
+signal eds_ready : std_logic; -- end signal, release busy by sending TERM and clean up misc stuff\r
+signal apv_trg_finished : std_logic;\r
+signal next_accept : std_logic; -- we can accept a trigger\r
+signal accept : std_logic;\r
+signal next_missed_trg : std_logic;\r
+signal missed_trg : std_logic;\r
+signal missing_trg : std_logic;\r
+signal next_rst_status : std_logic;\r
+signal rst_status : std_logic;\r
+\r
+signal time_trg : std_logic_vector(3 downto 0);\r
+\r
+-- Information to be collected for the EDS\r
+signal trg_dectrg_reg : std_logic_vector(3 downto 0); -- priority encoded timing trigger (4bit)\r
+signal trg_frmctr_reg : std_logic_vector(3 downto 0); -- frame counter start value (4bit)\r
+signal trg_frmnum_reg : std_logic_vector(3 downto 0); -- number of frames in this event (4bit)\r
+\r
+signal next_store_local : std_logic;\r
+signal store_local : std_logic;\r
+signal next_rst_local : std_logic;\r
+signal rst_local : std_logic;\r
+\r
+signal time_trg_on : std_logic_vector(3 downto 0);\r
+signal time_trg_inv : std_logic_vector(3 downto 0);\r
+\r
+signal big_event_comb : std_logic;\r
+signal tag_sector_match_comb : std_logic;\r
+signal suppress_data_comb : std_logic;\r
+\r
+signal trg_len_ctr : unsigned(8 downto 0); -- 9bit = 5.12us max\r
+signal trg_len_rst : std_logic; \r
+signal trg_len_ce : std_logic; \r
+signal trg_len_done : std_logic;\r
+signal trg_too_long : std_logic;\r
+\r
+signal bsm_x : std_logic_vector(7 downto 0);\r
+\r
+begin\r
+\r
+-- Aliasing the control bits\r
+time_trg_on(3) <= TRG_SETUP_IN(7);\r
+time_trg_inv(3) <= TRG_SETUP_IN(3);\r
+time_trg_on(2) <= TRG_SETUP_IN(6);\r
+time_trg_inv(2) <= TRG_SETUP_IN(2);\r
+time_trg_on(1) <= TRG_SETUP_IN(5);\r
+time_trg_inv(1) <= TRG_SETUP_IN(1);\r
+time_trg_on(0) <= TRG_SETUP_IN(4);\r
+time_trg_inv(0) <= TRG_SETUP_IN(0);\r
+\r
+------------------------------------------------------------\r
+-- Synchronize the external trigger inputs\r
+------------------------------------------------------------\r
+THE_TIME_TRG_3_SYNC: state_sync\r
+port map(\r
+ STATE_A_IN => TIME_TRG_IN(3),\r
+ CLK_B_IN => CLK_IN,\r
+ RESET_B_IN => RESET_IN,\r
+ STATE_B_OUT => time_trg(3)\r
+);\r
+THE_TIME_TRG_2_SYNC: state_sync\r
+port map(\r
+ STATE_A_IN => TIME_TRG_IN(2),\r
+ CLK_B_IN => CLK_IN,\r
+ RESET_B_IN => RESET_IN,\r
+ STATE_B_OUT => time_trg(2)\r
+);\r
+THE_TIME_TRG_1_SYNC: state_sync\r
+port map(\r
+ STATE_A_IN => TIME_TRG_IN(1),\r
+ CLK_B_IN => CLK_IN,\r
+ RESET_B_IN => RESET_IN,\r
+ STATE_B_OUT => time_trg(1)\r
+);\r
+THE_TIME_TRG_0_SYNC: state_sync\r
+port map(\r
+ STATE_A_IN => TIME_TRG_IN(0),\r
+ CLK_B_IN => CLK_IN,\r
+ RESET_B_IN => RESET_IN,\r
+ STATE_B_OUT => time_trg(0)\r
+);\r
+\r
+------------------------------------------------------------\r
+-- For all four possible hardware triggers we combine hardware and TRB inputs\r
+-- TRB slow control trigger inputs are already synchronized to SYSCLK.\r
+------------------------------------------------------------\r
+trg_comb(3) <= ((time_trg(3) xor time_trg_inv(3)) and time_trg_on(3)) or TRB_TRG_IN(3);\r
+trg_comb(2) <= ((time_trg(2) xor time_trg_inv(2)) and time_trg_on(2)) or TRB_TRG_IN(2);\r
+trg_comb(1) <= ((time_trg(1) xor time_trg_inv(1)) and time_trg_on(1)) or TRB_TRG_IN(1);\r
+trg_comb(0) <= ((time_trg(0) xor time_trg_inv(0)) and time_trg_on(0)) or TRB_TRG_IN(0);\r
+\r
+--------------------------------------------------------------------------------------------------\r
+-- trigger length surveillance\r
+--------------------------------------------------------------------------------------------------\r
+THE_TRG_LENGTH_CTR_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( (RESET_IN = '1') or (trg_len_rst = '1') ) then\r
+ trg_len_ctr <= (others => '0');\r
+ elsif( trg_len_ce = '1' ) then\r
+ trg_len_ctr <= trg_len_ctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_TRG_LENGTH_CTR_PROC;\r
+\r
+-- Count whenever trigger signal is high\r
+trg_len_ce <= trg_qqqq(0);\r
+-- Reset counter with each rising edge\r
+trg_len_rst <= trg_edge(0);\r
+-- Overflow of counter marks trigger length > 5us\r
+trg_len_done <= '1' when (trg_len_ctr = b"1_1111_1111") else '0';\r
+\r
+THE_TRG_TOO_LONG_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( (RESET_IN = '1') or (trg_len_rst = '1') ) then\r
+ trg_too_long <= '0';\r
+ elsif( trg_len_done = '1' ) then\r
+ trg_too_long <= '1';\r
+ end if;\r
+ end if;\r
+end process THE_TRG_TOO_LONG_PROC;\r
+\r
+--------------------------------------------------------------------------------------------------\r
+--------------------------------------------------------------------------------------------------\r
+\r
+------------------------------------------------------------\r
+-- Now we shift the synced signals into shift registers with four FF in a row.\r
+-- This gives us a 16bit pattern in total to decide which trigger input was active.\r
+------------------------------------------------------------\r
+THE_TRG_LENGTH_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ trg_qqqq <= (others => '0');\r
+ trg_qqq <= (others => '0');\r
+ trg_qq <= (others => '0');\r
+ trg_q <= (others => '0');\r
+ else\r
+ trg_qqqq <= trg_qqq;\r
+ trg_qqq <= trg_qq;\r
+ trg_qq <= trg_q;\r
+ trg_q <= trg_comb;\r
+ end if;\r
+ end if;\r
+end process THE_TRG_LENGTH_PROC;\r
+\r
+------------------------------------------------------------\r
+-- Check for rising edges in the signals, with a long steady state signal following.\r
+-- We accept only signals of three clock cycles minimum length (as sent by the TRB_TRG).\r
+------------------------------------------------------------\r
+THE_RISING_EDGES_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ trg_edge <= (others => '0');\r
+ else\r
+ trg_edge(3) <= not trg_qqqq(3) and trg_qqq(3) and trg_qq(3) and trg_q(3);\r
+ trg_edge(2) <= not trg_qqqq(2) and trg_qqq(2) and trg_qq(2) and trg_q(2);\r
+ trg_edge(1) <= not trg_qqqq(1) and trg_qqq(1) and trg_qq(1) and trg_q(1);\r
+ trg_edge(0) <= not trg_qqqq(0) and trg_qqq(0) and trg_qq(0) and trg_q(0);\r
+ end if;\r
+ end if;\r
+end process THE_RISING_EDGES_PROC;\r
+\r
+-- Now we are almost done.\r
+-- The detected edges are priorized.\r
+THE_TRG_PRIORITY_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ decoded_trg <= (others => '0');\r
+ todo_start <= (others => '0');\r
+ trg_found <= '0';\r
+ else\r
+ if( trg_edge(3) = '1' ) then\r
+ decoded_trg <= "1000";\r
+ todo_start <= TRG_3_TODO_IN;\r
+ trg_found <= '1';\r
+ elsif( trg_edge(3 downto 2) = "01" ) then\r
+ decoded_trg <= "0100";\r
+ todo_start <= TRG_2_TODO_IN;\r
+ trg_found <= '1';\r
+ elsif( trg_edge(3 downto 1) = "001" ) then\r
+ decoded_trg <= "0010";\r
+ todo_start <= TRG_1_TODO_IN;\r
+ trg_found <= '1';\r
+ elsif( trg_edge(3 downto 0) = "0001" ) then\r
+ decoded_trg <= "0001";\r
+ todo_start <= TRG_0_TODO_IN;\r
+ trg_found <= '1';\r
+ else\r
+ -- case of "timingtriggerless trigger"?\r
+ decoded_trg <= "0000";\r
+ todo_start <= "0000";\r
+ trg_found <= '0';\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process THE_TRG_PRIORITY_PROC;\r
+\r
+-- We need to store some information for the EDS... from local counters\r
+-- NB: after one cycle this information set is reset to zero!\r
+-- needed for missing timing trigger handling.\r
+THE_LOCALSTORE_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( (RESET_IN = '1') or (rst_local = '1') ) then\r
+ trg_frmctr_reg <= (others => '0');\r
+ trg_frmnum_reg <= (others => '0');\r
+ trg_dectrg_reg <= (others => '0');\r
+ elsif( (accept = '1') and (trg_found = '1') ) then -- the clock cycle before local_store pulse\r
+ trg_frmctr_reg <= std_logic_vector(frmctr);\r
+ trg_frmnum_reg <= todo_start;\r
+ trg_dectrg_reg <= decoded_trg;\r
+ end if;\r
+ end if;\r
+end process THE_LOCALSTORE_PROC;\r
+\r
+-- The ToDo counter: is loaded with the number of APV triggers, and counts down.\r
+THE_TODO_COUNTER_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( RESET_IN = '1' ) then\r
+ todo_ctr <= (others => '0');\r
+ elsif( store_local = '1' ) then\r
+ todo_ctr <= unsigned(trg_frmnum_reg);\r
+ elsif( ce_frmctr = '1' ) then\r
+ todo_ctr <= todo_ctr - 1;\r
+ end if;\r
+ end if;\r
+end process THE_TODO_COUNTER_PROC;\r
+next_todo_done <= '1' when (todo_ctr = x"0") else '0';\r
+\r
+THE_TRG_SYNC_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ todo_done <= '0';\r
+ else\r
+ todo_done <= next_todo_done;\r
+ end if;\r
+ end if;\r
+end process THE_TRG_SYNC_PROC;\r
+\r
+-- We store the end pulse from the APV trigger handler, as we need to wait for\r
+-- LVL1 in any case before we can take care of this signal.\r
+THE_TRGDONE_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ apv_trg_finished <= '0';\r
+ elsif( APV_TRGDONE_IN = '1' ) then\r
+ apv_trg_finished <= '1';\r
+ elsif( eds_ready = '1' ) then\r
+ apv_trg_finished <= '0';\r
+ end if;\r
+ end if;\r
+end process THE_TRGDONE_PROC;\r
+\r
+-- A statemachine handles all actions for filling out the trigger information sheet\r
+-- state registers\r
+STATE_MEM: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ ce_evtctr <= '0';\r
+ ce_frmctr <= '0';\r
+ eds_ready <= '0';\r
+ eds_we <= '0';\r
+ eds_start <= '0';\r
+ rst_local <= '0';\r
+ store_local <= '0';\r
+ apv_trgstart <= '0';\r
+ accept <= '1';\r
+ missed_trg <= '0';\r
+ rst_status <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ ce_evtctr <= next_ce_evtctr;\r
+ ce_frmctr <= next_ce_frmctr;\r
+ eds_ready <= next_eds_ready;\r
+ eds_we <= next_eds_we;\r
+ eds_start <= next_eds_start;\r
+ rst_local <= next_rst_local;\r
+ store_local <= next_store_local;\r
+ apv_trgstart <= next_apv_trgstart;\r
+ accept <= next_accept;\r
+ missed_trg <= next_missed_trg;\r
+ rst_status <= next_rst_status;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- state transitions\r
+STATE_TRANSFORM: process( CURRENT_STATE, trg_found, todo_done, TRB_TRGRCVD_IN, apv_trg_finished, \r
+ BUSY_RELEASE_IN, TRB_TTYPE_IN(3), TRB_TINFO_IN(7) )\r
+begin\r
+ NEXT_STATE <= SLEEP; -- avoid latches\r
+ next_ce_evtctr <= '0';\r
+ next_ce_frmctr <= '0';\r
+ next_eds_ready <= '0';\r
+ next_eds_we <= '0';\r
+ next_eds_start <= '0';\r
+ next_rst_local <= '0';\r
+ next_store_local <= '0';\r
+ next_apv_trgstart <= '0';\r
+ next_accept <= '0';\r
+ next_missed_trg <= '0';\r
+ next_rst_status <= '0';\r
+ case CURRENT_STATE is\r
+ -- not good. if no timing trigger was received but a trb trigger arrives, we must do something!\r
+ when SLEEP => if ( trg_found = '1' ) then\r
+ -- normal way: timing trigger found\r
+ NEXT_STATE <= STORE;\r
+ next_store_local <= '1';\r
+ next_eds_start <= '1';\r
+ elsif( (trg_found = '0') and (TRB_TRGRCVD_IN = '1') and (TRB_TTYPE_IN(3) = '1') and (TRB_TINFO_IN(7) = '1') ) then\r
+ NEXT_STATE <= TTLTRG;\r
+ elsif( (trg_found = '0') and (TRB_TRGRCVD_IN = '1') and ((TRB_TTYPE_IN(3) = '0') or (TRB_TINFO_IN(7) = '0')) ) then\r
+ NEXT_STATE <= BADTRG;\r
+ next_missed_trg <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ next_accept <= '1';\r
+ end if;\r
+ when TTLTRG => NEXT_STATE <= TRBS;\r
+ when BADTRG => NEXT_STATE <= TRBS;\r
+ when STORE => NEXT_STATE <= START;\r
+ next_apv_trgstart <= '1';\r
+ when START => NEXT_STATE <= CHECK;\r
+ when CHECK => if( todo_done = '1' ) then\r
+ NEXT_STATE <= WAPV;\r
+ else\r
+ NEXT_STATE <= COUNT;\r
+ next_ce_frmctr <= '1';\r
+ end if;\r
+ when COUNT => NEXT_STATE <= RELAX;\r
+ when RELAX => NEXT_STATE <= CHECK;\r
+ when WAPV => if( apv_trg_finished = '1' ) then\r
+ NEXT_STATE <= WLVL1;\r
+ else\r
+ NEXT_STATE <= WAPV;\r
+ end if;\r
+ when WLVL1 => if( TRB_TRGRCVD_IN = '1' ) then\r
+ NEXT_STATE <= TRBS;\r
+ else\r
+ NEXT_STATE <= WLVL1;\r
+ end if;\r
+ when TRBS => NEXT_STATE <= WEDS;\r
+ next_eds_we <= '1';\r
+ next_rst_local <= '1';\r
+ when WEDS => NEXT_STATE <= CNTEVT;\r
+ next_ce_evtctr <= '1';\r
+ when CNTEVT => NEXT_STATE <= WDEL0;\r
+ when WDEL0 => NEXT_STATE <= WDEL1;\r
+ when WDEL1 => NEXT_STATE <= WBUSY;\r
+ when WBUSY => if( BUSY_RELEASE_IN = '1' ) then\r
+ NEXT_STATE <= DONE;\r
+ next_eds_ready <= '1';\r
+ else\r
+ NEXT_STATE <= WBUSY;\r
+ end if;\r
+ when DONE => if( TRB_TRGRCVD_IN = '0' ) then -- mind the state synchronizer delay!!!\r
+ NEXT_STATE <= SLEEP;\r
+ next_accept <= '1';\r
+ next_rst_status <= '1';\r
+ else\r
+ NEXT_STATE <= DONE;\r
+ end if;\r
+ when others => NEXT_STATE <= SLEEP;\r
+ next_accept <= '1';\r
+ end case;\r
+end process STATE_TRANSFORM;\r
+\r
+-- state decoding\r
+STATE_DECODE: process( CURRENT_STATE )\r
+begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm_x <= x"00";\r
+ when STORE => bsm_x <= x"01";\r
+ when START => bsm_x <= x"02";\r
+ when CHECK => bsm_x <= x"03";\r
+ when COUNT => bsm_x <= x"04";\r
+ when RELAX => bsm_x <= x"14";\r
+ when WAPV => bsm_x <= x"05";\r
+ when WLVL1 => bsm_x <= x"06";\r
+ when TRBS => bsm_x <= x"07";\r
+ when WEDS => bsm_x <= x"0b";\r
+ when WDEL0 => bsm_x <= x"0c";\r
+ when WDEL1 => bsm_x <= x"0d";\r
+ when WBUSY => bsm_x <= x"0e";\r
+ when DONE => bsm_x <= x"0f";\r
+ when CNTEVT => bsm_x <= x"10";\r
+ when BADTRG => bsm_x <= x"11";\r
+ when TTLTRG => bsm_x <= x"12";\r
+ when others => bsm_x <= x"ff";\r
+ end case;\r
+end process STATE_DECODE;\r
+\r
+\r
+-- The event counter: is incremented with each accepted trigger\r
+THE_EVENT_COUNTER_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( RESET_IN = '1' ) then\r
+ evtctr <= (others => '0');\r
+ elsif( LVL1_LD_COUNTER_IN = '1' ) then\r
+ evtctr <= unsigned(LVL1_COUNTER_IN); -- update with value from TRBnet counter\r
+ elsif( ce_evtctr = '1' ) then\r
+ evtctr <= evtctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_EVENT_COUNTER_PROC;\r
+\r
+-- The frame counter: is incremented with each 1-0-0 trigger sent to APV\r
+THE_FRAME_COUNTER_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ frmctr <= (others => '0');\r
+ elsif( ce_frmctr = '1' ) then\r
+ frmctr <= frmctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_FRAME_COUNTER_PROC;\r
+\r
+-- If a timing trigger was missing, we simply ignore this LVL1 trigger\r
+THE_MISSED_TRG_REG: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( (RESET_IN = '1') or (rst_status = '1') ) then\r
+ missing_trg <= '0';\r
+ elsif( missed_trg = '1' ) then\r
+ missing_trg <= '1';\r
+ end if;\r
+ end if;\r
+end process THE_MISSED_TRG_REG;\r
+\r
+-- Now for something completely different: as we have two sectors connected\r
+-- to one GbE hub in the final setup, we must do a trick to stay below 64kB \r
+-- subevent size.\r
+-- So in all cases where 128 channels per event are requested, only those ADCM\r
+-- will produce data where the last bit of sector number and trigger number matches.\r
+-- I.e.: odd sectors fire on odd trigger numbers, even sectors on even trigger numbers.\r
+\r
+-- potentially dangerous (aka big) event\r
+big_event_comb <= '1' when (TRB_TINFO_IN(10 downto 8) = b"000") or -- RAW128\r
+ (TRB_TINFO_IN(10 downto 8) = b"001") or -- PED128\r
+ (TRB_TINFO_IN(10 downto 8) = b"010") or -- PED128THR\r
+ (TRB_TINFO_IN(10 downto 8) = b"100") -- NC64PED64\r
+ else '0';\r
+\r
+-- sector number matches trigger number\r
+tag_sector_match_comb <= '1' when ( SECTOR_IN(0) = TRB_TTAG_IN(0) ) else '0';\r
+\r
+-- when to drop data\r
+suppress_data_comb <= (big_event_comb and not tag_sector_match_comb) or TRB_TINFO_IN(0);\r
+\r
+-- EDS bits:\r
+eds_data(39 downto 36) <= trg_frmctr_reg;\r
+eds_data(35 downto 32) <= trg_frmnum_reg;\r
+eds_data(31 downto 16) <= TRB_TTAG_IN;\r
+eds_data(15 downto 8) <= TRB_TRND_IN;\r
+eds_data(7 downto 4) <= TRB_TTYPE_IN;\r
+eds_data(3) <= suppress_data_comb; --trb_tinfo_in(0); -- suppress output bit\r
+eds_data(2 downto 0) <= TRB_TINFO_IN(10 downto 8); -- RICH data configuration bits\r
+\r
+-- output signals\r
+APV_TRGSTART_OUT <= apv_trgstart;\r
+APV_TRGSEL_OUT <= trg_dectrg_reg;\r
+\r
+EDS_DATA_OUT <= eds_data;\r
+EDS_START_OUT <= eds_start;\r
+EDS_WE_OUT <= eds_we;\r
+EDS_READY_OUT <= eds_ready;\r
+TRB_MISSING_OUT <= missing_trg;\r
+LVL1_COUNTER_OUT <= std_logic_vector(evtctr);\r
+TRG_FOUND_OUT <= trg_comb(0); --trg_found; -- ugly bug fix for new handler_lvl1.vhd\r
+TRG_TOO_LONG_OUT <= trg_too_long;\r
+\r
+-- Debug signals\r
+BSM_OUT <= bsm_x;\r
+\r
+DEBUG_OUT(63 downto 32) <= (others => '0');\r
+DEBUG_OUT(31 downto 24) <= std_logic_vector(evtctr(7 downto 0));\r
+DEBUG_OUT(23 downto 16) <= TRB_TTAG_IN(7 downto 0);\r
+DEBUG_OUT(15) <= ce_evtctr;\r
+DEBUG_OUT(14) <= '0';\r
+DEBUG_OUT(13) <= missing_trg;\r
+DEBUG_OUT(12) <= accept;\r
+DEBUG_OUT(11) <= '0';\r
+DEBUG_OUT(10) <= '0';\r
+DEBUG_OUT(9) <= TRB_TRGRCVD_IN;\r
+DEBUG_OUT(8) <= trg_found;\r
+DEBUG_OUT(7 downto 0) <= bsm_x;\r
+\r
+DBG_FRMCTR_OUT <= std_logic_vector(frmctr);\r
+\r
+end behavioral;\r
+\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
signal todo_start : std_logic_vector(3 downto 0);\r
signal trg_found : std_logic;\r
\r
-signal evtctr : std_logic_vector(15 downto 0); -- event counter\r
+signal evtctr : unsigned(15 downto 0); -- event counter\r
signal ce_evtctr : std_logic;\r
signal next_ce_evtctr : std_logic;\r
-signal frmctr : std_logic_vector(3 downto 0); -- frame counter\r
+signal frmctr : unsigned(3 downto 0); -- frame counter\r
signal ce_frmctr : std_logic;\r
signal next_ce_frmctr : std_logic;\r
-signal todo_ctr : std_logic_vector(3 downto 0);\r
+signal todo_ctr : unsigned(3 downto 0);\r
signal next_todo_done : std_logic;\r
signal todo_done : std_logic;\r
signal next_apv_trgstart : std_logic;\r
\r
------------------------------------------------------------\r
-- Synchronize the external trigger inputs\r
+------------------------------------------------------------\r
THE_TIME_TRG_3_SYNC: state_sync\r
port map(\r
STATE_A_IN => time_trg_in(3),\r
RESET_B_IN => reset_in,\r
STATE_B_OUT => time_trg(0)\r
);\r
-------------------------------------------------------------\r
\r
+------------------------------------------------------------\r
-- For all four possible hardware triggers we combine hardware and TRB inputs\r
-- TRB slow control trigger inputs are already synchronized to SYSCLK.\r
---trg_comb <= time_trg or trb_trg_in;\r
-\r
+------------------------------------------------------------\r
trg_comb(3) <= ((time_trg(3) xor time_trg_inv(3)) and time_trg_on(3)) or trb_trg_in(3);\r
trg_comb(2) <= ((time_trg(2) xor time_trg_inv(2)) and time_trg_on(2)) or trb_trg_in(2);\r
trg_comb(1) <= ((time_trg(1) xor time_trg_inv(1)) and time_trg_on(1)) or trb_trg_in(1);\r
trg_comb(0) <= ((time_trg(0) xor time_trg_inv(0)) and time_trg_on(0)) or trb_trg_in(0);\r
\r
+------------------------------------------------------------\r
-- Now we shift the synced signals into shift registers with four FF in a row.\r
-- This gives us a 16bit pattern in total to decide which trigger input was active.\r
+------------------------------------------------------------\r
THE_TRG_LENGTH_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
end if;\r
end process THE_TRG_LENGTH_PROC;\r
\r
+------------------------------------------------------------\r
-- Check for rising edges in the signals, with a long steady state signal following.\r
-- We accept only signals of three clock cycles minimum length (as sent by the TRB_TRG).\r
+------------------------------------------------------------\r
THE_RISING_EDGES_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
trg_frmnum_reg <= (others => '0');\r
trg_dectrg_reg <= (others => '0');\r
elsif( (accept = '1') and (trg_found = '1') ) then -- the clock cycle before local_store pulse\r
- trg_frmctr_reg <= frmctr;\r
+ trg_frmctr_reg <= std_logic_vector(frmctr);\r
trg_frmnum_reg <= todo_start;\r
trg_dectrg_reg <= decoded_trg;\r
end if;\r
if ( reset_in = '1' ) then\r
todo_ctr <= (others => '0');\r
elsif( store_local = '1' ) then\r
- todo_ctr <= trg_frmnum_reg;\r
+ todo_ctr <= unsigned(trg_frmnum_reg);\r
elsif( ce_frmctr = '1' ) then\r
todo_ctr <= todo_ctr - 1;\r
end if;\r
end process THE_TODO_COUNTER_PROC;\r
next_todo_done <= '1' when (todo_ctr = x"0") else '0';\r
\r
-\r
--------------------------------------------------\r
--------------------------------------------------\r
--------------------------------------------------\r
-\r
THE_TRG_SYNC_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
if( reset_in = '1' ) then\r
- todo_done <= '0';\r
+ todo_done <= '0';\r
else\r
- todo_done <= next_todo_done;\r
+ todo_done <= next_todo_done;\r
end if;\r
end if;\r
end process THE_TRG_SYNC_PROC;\r
if ( reset_in = '1' ) then\r
evtctr <= (others => '0');\r
elsif( lvl1_ld_counter_in = '1' ) then\r
- evtctr <= lvl1_counter_in; -- update with value from TRBnet counter\r
+ evtctr <= unsigned(lvl1_counter_in); -- update with value from TRBnet counter\r
elsif( ce_evtctr = '1' ) then\r
evtctr <= evtctr + 1;\r
end if;\r
eds_we_out <= eds_we;\r
eds_ready_out <= eds_ready;\r
trb_missing_out <= missing_trg;\r
-lvl1_counter_out <= evtctr;\r
+lvl1_counter_out <= std_logic_vector(evtctr);\r
trg_found_out <= trg_found;\r
\r
-- Debug signals\r
bsm_out <= bsm_x;\r
\r
debug_out(63 downto 32) <= (others => '0');\r
-debug_out(31 downto 24) <= evtctr(7 downto 0);\r
+debug_out(31 downto 24) <= std_logic_vector(evtctr(7 downto 0));\r
debug_out(23 downto 16) <= trb_ttag_in(7 downto 0);\r
debug_out(15) <= ce_evtctr;\r
debug_out(14) <= '0';\r
debug_out(8) <= trg_found;\r
debug_out(7 downto 0) <= bsm_x;\r
\r
-dbg_frmctr_out <= frmctr;\r
+dbg_frmctr_out <= std_logic_vector(frmctr);\r
\r
end behavioral;\r
\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
architecture behavioral of reboot_handler is\r
\r
-- normal signals\r
-signal reboot_counter : std_logic_vector(15 downto 0);\r
+signal reboot_counter : unsigned(15 downto 0);\r
signal reboot_ce : std_logic;\r
signal reboot_x : std_logic;\r
signal reboot : std_logic;\r
begin\r
\r
-- Latch the start pulse\r
-THE_START_PULSE: process( clk_in )\r
+THE_START_PULSE: process( CLK_IN )\r
begin\r
- if( rising_edge(clk_in) ) then\r
- if ( reset_in = '1' ) then\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( RESET_IN = '1' ) then\r
reboot_ce <= '0';\r
- elsif( start_in = '1' ) then\r
+ elsif( START_IN = '1' ) then\r
reboot_ce <= '1';\r
end if;\r
end if;\r
end process THE_START_PULSE;\r
\r
-- Reboot counter\r
-THE_REBOOT_COUNTER: process( clk_in )\r
+THE_REBOOT_COUNTER: process( CLK_IN )\r
begin\r
- if( rising_edge(clk_in) ) then\r
- if ( reset_in = '1' ) then\r
+ if( rising_edge(CLK_IN) ) then\r
+ if ( RESET_IN = '1' ) then\r
reboot_counter <= (others => '0');\r
reboot <= '0';\r
elsif( reboot_ce = '1' ) then\r
reboot_x <= reboot_counter(15) and reboot_counter(14) and reboot_counter(13);\r
\r
-- output signals\r
-reboot_out <= reboot;\r
+REBOOT_OUT <= reboot;\r
\r
-debug_out(15 downto 0) <= reboot_counter;\r
+DEBUG_OUT(15 downto 0) <= std_logic_vector(reboot_counter);\r
\r
end behavioral;\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
--- /dev/null
+library ieee; \r
+use ieee.std_logic_1164.all; \r
+use ieee.numeric_std.all; \r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+--library ecp2m;\r
+--use ecp2m.components.all;\r
+\r
+entity reset_handler is\r
+generic(\r
+ RESET_DELAY : std_logic_vector(15 downto 0) := x"1fff"\r
+);\r
+port( \r
+ CLEAR_IN : in std_logic; -- reset input (high active, async)\r
+ CLEAR_N_IN : in std_logic; -- reset input (low active, async)\r
+ CLK_IN : in std_logic; -- raw master clock, NOT from PLL/DLL!\r
+ SYSCLK_IN : in std_logic; -- PLL/DLL remastered clock\r
+ PLL_LOCKED_IN : in std_logic; -- master PLL lock signal (async)\r
+ RESET_IN : in std_logic; -- general reset signal (SYSCLK)\r
+ TRB_RESET_IN : in std_logic; -- TRBnet reset signal (SYSCLK)\r
+ CLEAR_OUT : out std_logic; -- async reset out, USE WITH CARE!\r
+ RESET_OUT : out std_logic; -- synchronous reset out (SYSCLK)\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end;\r
+\r
+-- This reset handler tries to generate a stable synchronous reset\r
+-- for FPGA fabric. It waits for the system clock PLL to lock, reacts\r
+-- on two external asynchronous resets, and also allows to reset the\r
+-- FPGA by sending a synchronous TRBnet reset pulse.\r
+-- It is not recommended to reset the system clock PLL/DLL with\r
+-- any of the reset signals generated here. It may deadlock.\r
+\r
+architecture behavioral of reset_handler is\r
+\r
+-- normal signals\r
+signal async_sampler : std_logic_vector(7 downto 0); -- input shift register\r
+signal comb_async_pulse : std_logic;\r
+signal async_pulse : std_logic;\r
+signal reset_cnt : unsigned(15 downto 0) := x"0000";\r
+signal debug : std_logic_vector(15 downto 0);\r
+signal reset : std_logic; -- DO NOT USE THIS SIGNAL!\r
+\r
+signal reset_buffer : std_logic; -- DO NOT USE THIS SIGNAL!\r
+signal trb_reset_buffer : std_logic; -- DO NOT USE THIS SIGNAL!\r
+signal reset_pulse : std_logic_vector(1 downto 0) := b"00";\r
+signal trb_reset_pulse : std_logic_vector(1 downto 0) := b"00"; \r
+signal comb_async_rst : std_logic;\r
+signal final_reset : std_logic_vector(1 downto 0) := b"11"; -- DO NOT USE THIS SIGNAL!\r
+\r
+attribute syn_preserve : boolean;\r
+attribute syn_preserve of async_sampler : signal is true;\r
+attribute syn_preserve of async_pulse : signal is true;\r
+attribute syn_preserve of reset : signal is true;\r
+attribute syn_preserve of reset_cnt : signal is true;\r
+attribute syn_preserve of comb_async_rst : signal is true;\r
+ \r
+begin \r
+\r
+----------------------------------------------------------------\r
+-- Combine all async reset sources: CLR, /CLR, PLL_LOCK\r
+----------------------------------------------------------------\r
+comb_async_rst <= not CLEAR_IN and CLEAR_N_IN and PLL_LOCKED_IN;\r
+\r
+----------------------------------------------------------------\r
+-- sample the async reset line and react only on a long pulse\r
+----------------------------------------------------------------\r
+THE_ASYNC_SAMPLER_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ async_sampler(7 downto 0) <= async_sampler(6 downto 0) & comb_async_rst;\r
+ async_pulse <= comb_async_pulse;\r
+ end if;\r
+end process THE_ASYNC_SAMPLER_PROC;\r
+\r
+-- first two registers are clock domain transfer registers!\r
+comb_async_pulse <= '1' when ( async_sampler(7 downto 2) = b"0000_00" ) else '0';\r
+\r
+----------------------------------------------------------------\r
+-- Sync the signals from SYSCLK to raw clock domain and back\r
+----------------------------------------------------------------\r
+THE_SYNC_PROC: process( SYSCLK_IN ) \r
+begin\r
+ if( rising_edge(SYSCLK_IN) ) then\r
+ reset_buffer <= RESET_IN; -- not really needed, but relaxes timing\r
+ trb_reset_buffer <= TRB_RESET_IN; -- not really needed, but relaxes timing\r
+ final_reset <= final_reset(0) & reset;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+THE_CROSSING_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ reset_pulse <= reset_pulse(0) & reset_buffer;\r
+ trb_reset_pulse <= trb_reset_pulse(0) & trb_reset_buffer;\r
+ end if;\r
+end process THE_CROSSING_PROC;\r
+\r
+----------------------------------------------------------------\r
+-- one global reset counter\r
+----------------------------------------------------------------\r
+THE_GLOBAL_RESET_PROC: process( CLK_IN )\r
+begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( (async_pulse = '1') or (reset_pulse(1) = '1') or (trb_reset_pulse(1) = '1') ) then\r
+ reset_cnt <= (others => '0');\r
+ reset <= '1';\r
+ else\r
+ reset_cnt <= reset_cnt + 1;\r
+ reset <= '1';\r
+ if( reset_cnt = unsigned(RESET_DELAY) ) then\r
+ reset <= '0';\r
+ reset_cnt <= unsigned(RESET_DELAY);\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process THE_GLOBAL_RESET_PROC;\r
+\r
+\r
+----------------------------------------------------------------\r
+-- Debug signals\r
+----------------------------------------------------------------\r
+debug(15) <= reset;\r
+debug(14) <= '0';\r
+debug(13 downto 12) <= final_reset;\r
+debug(11 downto 0) <= std_logic_vector(reset_cnt(11 downto 0));\r
+--debug(15) <= comb_async_pulse;\r
+--debug(14 downto 8) <= (others => '0');\r
+--debug(7 downto 0) <= async_sampler;\r
+\r
+----------------------------------------------------------------\r
+-- Output signals\r
+----------------------------------------------------------------\r
+DEBUG_OUT <= debug;\r
+CLEAR_OUT <= not comb_async_rst;\r
+RESET_OUT <= final_reset(1);\r
+\r
+end behavioral; \r
LED_LINK_RXD : out std_logic;
LINK_BSM_OUT : out std_logic_vector(3 downto 0);
RESET_OUT : out std_logic;
+ TICK_10S_OUT : out std_logic;
-- Debug
DEBUG : out std_logic_vector(63 downto 0)
);
-- Signals
signal clk_en : std_logic;
-signal med_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0);
-signal med_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-signal med_dataready_in : std_logic;
-signal med_read_out : std_logic;
-signal med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
-signal med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-signal med_dataready_out : std_logic;
-signal med_read_in : std_logic;
+signal med_data_in_int : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+signal med_packet_num_in_int : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+signal med_dataready_in_int : std_logic;
+signal med_read_out_int : std_logic;
+signal med_data_out_int : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+signal med_packet_num_out_int : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+signal med_dataready_out_int : std_logic;
+signal med_read_in_int : std_logic;
signal med_stat_debug : std_logic_vector(63 downto 0);
signal med_ctrl_op : std_logic_vector(15 downto 0);
signal med_stat_op : std_logic_vector(15 downto 0);
signal stat_debug_1 : std_logic_vector(31 downto 0);
-begin
-
---#######################################################################
+signal tick_1ms : std_logic;
+signal counter_10s : unsigned(13 downto 0);
+signal next_rst_counter_10s : std_logic;
+signal rst_counter_10s : std_logic;
+signal ce_counter_10s : std_logic;
+signal next_tick_10s : std_logic;
+signal tick_10s : std_logic;
---#######################################################################
+begin
-- Debug
debug <= debug_x;
-- Clock assignment. We don't use CLK_EN really in our designs.
clk_en <= '1';
--------------------------------------------------------------
+------------------------------------------------------------------------------------
-- Serdes
--------------------------------------------------------------
+------------------------------------------------------------------------------------
THE_MEDIA_INTERFACE : trb_net16_med_ecp_sfp_gbe
generic map(
SERDES_NUM => 2
)
port map(
- CLK => clk100m_in,
- SYSCLK => sysclk_in,
- RESET => reset_in,
+ CLK => CLK100M_IN,
+ SYSCLK => SYSCLK_IN,
+ RESET => RESET_IN,
CLEAR => '0',
CLK_EN => clk_en,
--Internal Connection
- MED_DATA_IN => med_data_out,
- MED_PACKET_NUM_IN => med_packet_num_out,
- MED_DATAREADY_IN => med_dataready_out,
- MED_READ_OUT => med_read_in,
- MED_DATA_OUT => med_data_in,
- MED_PACKET_NUM_OUT => med_packet_num_in,
- MED_DATAREADY_OUT => med_dataready_in,
- MED_READ_IN => med_read_out,
+ MED_DATA_IN => med_data_out_int,
+ MED_PACKET_NUM_IN => med_packet_num_out_int,
+ MED_DATAREADY_IN => med_dataready_out_int,
+ MED_READ_OUT => med_read_in_int,
+ MED_DATA_OUT => med_data_in_int,
+ MED_PACKET_NUM_OUT => med_packet_num_in_int,
+ MED_DATAREADY_OUT => med_dataready_in_int,
+ MED_READ_IN => med_read_out_int,
REFCLK2CORE_OUT => open,
--SFP Connection
- SD_RXD_P_IN => sd_rxd_p_in,
- SD_RXD_N_IN => sd_rxd_n_in,
- SD_TXD_P_OUT => sd_txd_p_out,
- SD_TXD_N_OUT => sd_txd_n_out,
+ SD_RXD_P_IN => SD_RXD_P_IN,
+ SD_RXD_N_IN => SD_RXD_N_IN,
+ SD_TXD_P_OUT => SD_TXD_P_OUT,
+ SD_TXD_N_OUT => SD_TXD_N_OUT,
SD_REFCLK_P_IN => '1',
SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => sd_present_in,
- SD_LOS_IN => sd_los_in,
- SD_TXDIS_OUT => sd_txdis_out,
+ SD_PRSNT_N_IN => SD_PRESENT_IN,
+ SD_LOS_IN => SD_LOS_IN,
+ SD_TXDIS_OUT => SD_TXDIS_OUT,
-- Status and control port
STAT_OP => med_stat_op,
CTRL_OP => med_ctrl_op, -- input
CTRL_DEBUG => (others => '0')
);
---debug_x <= med_stat_debug;
+------------------------------------------------------------------------------------
+-- Debug signals
+------------------------------------------------------------------------------------
+debug_x(63 downto 47) <= med_stat_debug(63 downto 47);
+debug_x(46 downto 42) <= (others => '0');
+debug_x(41) <= med_read_out_int; -- MED_READ_IN
+debug_x(40) <= med_dataready_in_int; -- MED_DATAREADY_OUT
+debug_x(39 downto 37) <= med_packet_num_in_int; -- MED_PACKET_NUM_OUT
+debug_x(36 downto 21) <= med_data_in_int; -- MED_DATA_OUT
+debug_x(20) <= med_read_in_int; -- MED_READ_OUT
+debug_x(19) <= med_dataready_out_int; -- MED_DATAREADY_IN
+debug_x(18 downto 16) <= med_packet_num_out_int; -- MED_PACKET_NUM_IN
+--debug_x(15 downto 0) <= med_data_out; -- MED_DATA_IN
+debug_x(15 downto 7) <= (others => '0');
+debug_x(6 downto 0) <= med_stat_debug(30 downto 24);
-debug_x(63 downto 42) <= (others => '0');
-debug_x(41) <= med_read_out; -- MED_READ_IN
-debug_x(40) <= med_dataready_in; -- MED_DATAREADY_OUT
-debug_x(39 downto 37) <= med_packet_num_in; -- MED_PACKET_NUM_OUT
-debug_x(36 downto 21) <= med_data_in; -- MED_DATA_OUT
-debug_x(20) <= med_read_in; -- MED_READ_OUT
-debug_x(19) <= med_dataready_out; -- MED_DATAREADY_IN
-debug_x(18 downto 16) <= med_packet_num_out; -- MED_PACKET_NUM_IN
-debug_x(15 downto 0) <= med_data_out; -- MED_DATA_IN
-
- ------------------------------------------------------------
+------------------------------------------------------------------------------------
-- Full featured HADES endpoint
--------------------------------------------------------------
+------------------------------------------------------------------------------------
THE_UNIFIED_ENDPOINT: trb_net16_endpoint_hades_full
generic map(
USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
REGIO_INIT_UNIQUE_ID => x"dead_beef_affe_d00f",
REGIO_INIT_BOARD_INFO => x"5aa5_3cc3",
REGIO_INIT_ENDPOINT_ID => x"0001",
- REGIO_COMPILE_TIME => VERSION_NUMBER_TIME,
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
REGIO_COMPILE_VERSION => x"0003",
REGIO_HARDWARE_VERSION => x"3300_0000", -- ADCMv3 signature
REGIO_USE_1WIRE_INTERFACE => c_YES,
+ TIMING_TRIGGER_RAW => c_YES,
CLOCK_FREQUENCY => 100
)
port map(
- CLK => sysclk_in,
- RESET => reset_in,
+ CLK => SYSCLK_IN,
+ RESET => RESET_IN,
CLK_EN => clk_en,
-- Media direction port
- MED_DATAREADY_OUT => med_dataready_out,
- MED_DATA_OUT => med_data_out,
- MED_PACKET_NUM_OUT => med_packet_num_out,
- MED_READ_IN => med_read_in,
- MED_DATAREADY_IN => med_dataready_in,
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out,
+ MED_DATAREADY_OUT => med_dataready_out_int,
+ MED_DATA_OUT => med_data_out_int,
+ MED_PACKET_NUM_OUT => med_packet_num_out_int,
+ MED_READ_IN => med_read_in_int,
+ MED_DATAREADY_IN => med_dataready_in_int,
+ MED_DATA_IN => med_data_in_int,
+ MED_PACKET_NUM_IN => med_packet_num_in_int,
+ MED_READ_OUT => med_read_out_int,
MED_STAT_OP_IN => med_stat_op,
MED_CTRL_OP_OUT => med_ctrl_op,
-- LVL1 trigger APL
- LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received
- LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received
- LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
- LVL1_TRG_DATA_VALID_OUT => lvl1_trg_received_out,
- TRG_TIMING_TRG_RECEIVED_IN => timing_trg_found_in,
- LVL1_TRG_TYPE_OUT => lvl1_trg_type_out,
- LVL1_TRG_NUMBER_OUT => lvl1_trg_number_out,
- LVL1_TRG_CODE_OUT => lvl1_trg_code_out,
- LVL1_TRG_INFORMATION_OUT => lvl1_trg_information_out,
- LVL1_ERROR_PATTERN_IN => lvl1_error_pattern_in,
- LVL1_TRG_RELEASE_IN => lvl1_trg_release_in,
+ LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received
+ LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received
+ LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
+ LVL1_TRG_DATA_VALID_OUT => LVL1_TRG_RECEIVED_OUT,
+ TRG_TIMING_TRG_RECEIVED_IN => TIMING_TRG_FOUND_IN,
+ LVL1_TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT,
+ LVL1_TRG_NUMBER_OUT => LVL1_TRG_NUMBER_OUT,
+ LVL1_TRG_CODE_OUT => LVL1_TRG_CODE_OUT,
+ LVL1_TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT,
+ LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN,
+ LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN,
LVL1_INT_TRG_NUMBER_OUT => open, -- internal trigger number from LVL1 endpoint
-- IPU Port
- IPU_NUMBER_OUT => ipu_number_out,
+ IPU_NUMBER_OUT => IPU_NUMBER_OUT,
IPU_READOUT_TYPE_OUT => open, -- 4bit readout type
- IPU_INFORMATION_OUT => ipu_information_out,
- IPU_START_READOUT_OUT => ipu_start_readout_out,
- IPU_DATA_IN => ipu_data_in,
- IPU_DATAREADY_IN => ipu_dataready_in,
- IPU_READOUT_FINISHED_IN => ipu_readout_finished_in,
- IPU_READ_OUT => ipu_read_out,
- IPU_LENGTH_IN => ipu_length_in,
- IPU_ERROR_PATTERN_IN => ipu_error_pattern_in,
+ IPU_INFORMATION_OUT => IPU_INFORMATION_OUT,
+ IPU_START_READOUT_OUT => IPU_START_READOUT_OUT,
+ IPU_DATA_IN => IPU_DATA_IN,
+ IPU_DATAREADY_IN => IPU_DATAREADY_IN,
+ IPU_READOUT_FINISHED_IN => IPU_READOUT_FINISHED_IN,
+ IPU_READ_OUT => IPU_READ_OUT,
+ IPU_LENGTH_IN => IPU_LENGTH_IN,
+ IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN,
-- Slow Control Data Port
REGIO_COMMON_STAT_REG_IN => common_stat_reg,
REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg,
STAT_REG_STROBE => open,
CTRL_REG_STROBE => open,
--following ports only used when using internal data port
- REGIO_ADDR_OUT => regio_addr_out,
- REGIO_READ_ENABLE_OUT => regio_read_enable_out,
- REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,
- REGIO_DATA_OUT => regio_data_out,
- REGIO_DATA_IN => regio_data_in,
- REGIO_DATAREADY_IN => regio_dataready_in,
- REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,
- REGIO_WRITE_ACK_IN => regio_write_ack_in,
- REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- REGIO_TIMEOUT_OUT => regio_timeout_out,
+ REGIO_ADDR_OUT => REGIO_ADDR_OUT,
+ REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT,
+ REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT,
+ REGIO_DATA_OUT => REGIO_DATA_OUT,
+ REGIO_DATA_IN => REGIO_DATA_IN,
+ REGIO_DATAREADY_IN => REGIO_DATAREADY_IN,
+ REGIO_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN,
+ REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN,
+ REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN,
+ REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT,
--IDRAM is used if no 1-wire interface, onewire used otherwise
REGIO_IDRAM_DATA_IN => x"0000", -- not used
REGIO_IDRAM_DATA_OUT => open, -- not used
REGIO_IDRAM_ADDR_IN => "000", -- not used
REGIO_IDRAM_WR_IN => '0', -- not used
- REGIO_ONEWIRE_INOUT => onewire_inout,
+ REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT,
REGIO_ONEWIRE_MONITOR_IN => '1', -- not used
REGIO_ONEWIRE_MONITOR_OUT => open, -- not used
- -- New stuff?!?
+ -- New stuff
GLOBAL_TIME_OUT => open,
LOCAL_TIME_OUT => open,
TIME_SINCE_LAST_TRG_OUT => open,
- TIMER_TICKS_OUT => open,
+ TIMER_TICKS_OUT(1) => tick_1ms, -- ms ticks
+ TIMER_TICKS_OUT(0) => open, -- us ticks
-- Status and debug
STAT_DEBUG_IPU => open,
STAT_DEBUG_1 => stat_debug_1, --open,
STAT_ADDR_DEBUG => open
);
+------------------------------------------------------------------------------------
+-- 10s counter
+------------------------------------------------------------------------------------
+THE_TEN_SEC_CTR_PROC: process( SYSCLK_IN )
+begin
+ if( rising_edge(SYSCLK_IN) ) then
+ if ( rst_counter_10s = '1' ) then
+ counter_10s <= (others => '0');
+ elsif( ce_counter_10s = '1' ) then
+ counter_10s <= counter_10s + 1;
+ end if;
+ rst_counter_10s <= next_rst_counter_10s;
+ tick_10s <= next_tick_10s;
+ end if;
+end process THE_TEN_SEC_CTR_PROC;
+
+ce_counter_10s <= tick_1ms;
+
+next_rst_counter_10s <= '1' when (((counter_10s = 9765) and (ce_counter_10s = '1')) or (RESET_IN = '1')) else '0';
+
+next_tick_10s <= rst_counter_10s;
+
+------------------------------------------------------------------------------------
-- Control register assignment
+------------------------------------------------------------------------------------
-- Common status register
-common_stat_reg(COMMON_STAT_REG'left downto 32) <= common_stat_reg_in(63 downto 32); --(others => '0');
-common_stat_reg(31 downto 20) <= (others => '0'); -- already taken by TEMP of 1WID
-common_stat_reg(19 downto 0) <= common_stat_reg_in(19 downto 0); --(others => '0');
+common_stat_reg(127 downto 64) <= COMMON_STAT_REG_IN(127 downto 64); -- reserved
+common_stat_reg(63 downto 32) <= COMMON_STAT_REG_IN(63 downto 32);
+common_stat_reg(31 downto 20) <= (others => '0'); -- already taken by TEMP of 1WID
+common_stat_reg(19 downto 0) <= COMMON_STAT_REG_IN(19 downto 0);
-- Common control register
-common_ctrl_reg_out <= common_ctrl_reg;
+COMMON_CTRL_REG_OUT <= common_ctrl_reg;
-- User status register
-regio_stat_regs <= status_in;
-control_out <= regio_ctrl_regs;
-lvl1_int_trg_update_out <= common_ctrl_reg_strobe(1);
-lvl1_int_trg_number_out <= common_ctrl_reg(47 downto 32);
+regio_stat_regs <= STATUS_IN;
+CONTROL_OUT <= regio_ctrl_regs;
+LVL1_INT_TRG_UPDATE_OUT <= common_ctrl_reg_strobe(1);
+LVL1_INT_TRG_NUMBER_OUT <= common_ctrl_reg(47 downto 32);
-- FPGA LEDs
-led_link_stat <= not med_stat_op(9); -- link status
-led_link_rxd <= not med_stat_op(10); -- not med_packet_num_in(2); -- data receive
-led_link_txd <= not med_stat_op(11); -- data transmit
-link_bsm_out <= med_stat_op(7 downto 4); -- LSM state bits
-reset_out <= med_stat_op(13); -- TRB generated reset
+LED_LINK_STAT <= not med_stat_op(9); -- link status
+LED_LINK_RXD <= not med_stat_op(10); -- not med_packet_num_in(2); -- data receive
+LED_LINK_TXD <= not med_stat_op(11); -- data transmit
+
+-- Output signals
+LINK_BSM_OUT <= med_stat_op(7 downto 4); -- LSM state bits
+RESET_OUT <= med_stat_op(13); -- TRB generated reset
end architecture;
-
\ No newline at end of file
+
--- /dev/null
+-------------------------------------------------------------------------------
+-- Single buffer with one more buffer to keep the speed of the datalink
+-- The sbuf can be connected to a combinatorial logic (as an output buffer)
+-- to provide the synchronous logic
+--
+-- 2 versions are provided
+-- VERSION=0 is the fast version, so double buffering is done
+-- VERSION=1 is half data rate: After data has been written to the sbuf,
+-- the input read signal is stalled until the buffer is empty.
+-- Maybe enough for trigger and slow control channels
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+--use work.trb_net_std.all;
+
+entity sbuf is
+generic(
+ DATA_WIDTH : integer := 18;
+ VERSION : integer := 0
+);
+port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- port to combinatorial logic
+ COMB_DATAREADY_IN : in std_logic; --comb logic provides data word
+ COMB_next_READ_OUT : out std_logic; --sbuf can read in NEXT cycle
+ COMB_READ_IN : in std_logic; --comb logic IS reading
+ -- the COMB_next_READ_OUT should be connected via comb. logic to a register
+ -- to provide COMB_READ_IN (feedback path with 1 cycle delay)
+ COMB_DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0); -- Data word
+ -- Port to synchronous output.
+ SYN_DATAREADY_OUT : out std_logic;
+ SYN_DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0); -- Data word
+ SYN_READ_IN : in std_logic;
+ -- Status and control port
+ STAT_BUFFER : out std_logic
+);
+end sbuf;
+
+architecture sbuf_arch of sbuf is
+
+signal current_b1_buffer : std_logic_vector(DATA_WIDTH-1 downto 0);
+signal next_b1_buffer : std_logic_vector(DATA_WIDTH-1 downto 0);
+signal current_b2_buffer : std_logic_vector(DATA_WIDTH-1 downto 0);
+signal next_b2_buffer : std_logic_vector(DATA_WIDTH-1 downto 0);
+signal next_next_READ_OUT : std_logic;
+signal current_next_READ_OUT : std_logic;
+signal next_SYN_DATAREADY_OUT : std_logic;
+signal current_SYN_DATAREADY_OUT : std_logic;
+
+signal move_b1_buffer : std_logic;
+signal move_b2_buffer : std_logic;
+
+type BUFFER_STATE is (BUFFER_EMPTY, BUFFER_B2_FULL, BUFFER_B1_FULL);
+signal current_buffer_state : BUFFER_STATE;
+signal next_buffer_state : BUFFER_STATE;
+signal current_buffer_state_int : std_logic_vector(1 downto 0);
+
+signal current_got_overflow : std_logic;
+signal next_got_overflow : std_logic;
+signal combined_COMB_DATAREADY_IN : std_logic;
+signal use_current_b1_buffer : std_logic;
+
+signal buf_SYN_READ_IN : std_logic;
+
+attribute syn_preserve : boolean;
+attribute syn_keep : boolean;
+attribute syn_preserve of current_SYN_DATAREADY_OUT : signal is true;
+attribute syn_keep of current_SYN_DATAREADY_OUT : signal is true;
+attribute syn_preserve of current_next_READ_OUT : signal is true;
+attribute syn_keep of current_next_READ_OUT : signal is true;
+attribute syn_preserve of combined_COMB_DATAREADY_IN : signal is true;
+attribute syn_keep of combined_COMB_DATAREADY_IN : signal is true;
+attribute syn_preserve of buf_SYN_READ_IN : signal is true;
+attribute syn_keep of buf_SYN_READ_IN : signal is true;
+
+attribute syn_hier : string;
+attribute syn_hier of sbuf_arch : architecture is "flatten, firm";
+
+
+begin
+
+buf_SYN_READ_IN <= SYN_READ_IN;
+
+SYN_DATA_OUT <= current_b2_buffer;
+SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT;
+STAT_BUFFER <= current_got_overflow;
+
+combined_COMB_DATAREADY_IN <= (COMB_DATAREADY_IN and COMB_READ_IN);
+
+THE_MUX_PROC: process (use_current_b1_buffer, COMB_DATA_IN, current_b1_buffer)
+begin
+ if( use_current_b1_buffer = '1' ) then
+ next_b2_buffer <= current_b1_buffer;
+ else
+ next_b2_buffer <= COMB_DATA_IN;
+ end if;
+end process;
+
+
+THE_COMB_PROC: process (current_buffer_state, COMB_DATA_IN, combined_comb_dataready_in,
+ current_SYN_DATAREADY_OUT, current_got_overflow, buf_syn_read_in)
+begin
+ next_buffer_state <= current_buffer_state;
+ next_next_READ_OUT <= '1';
+ next_b1_buffer <= COMB_DATA_IN;
+ move_b1_buffer <= '0';
+ use_current_b1_buffer <= '0'; --by default COMB_DATA_IN;
+ move_b2_buffer <= '0';
+ next_SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT;
+ next_got_overflow <= current_got_overflow;
+
+ if ( current_buffer_state = BUFFER_EMPTY ) then
+ current_buffer_state_int <= "00";
+ if( combined_COMB_DATAREADY_IN = '1' ) then
+ -- COMB logic is writing into the sbuf
+ next_buffer_state <= BUFFER_B2_FULL;
+ move_b2_buffer <= '1';
+ next_SYN_DATAREADY_OUT <= '1';
+ end if;
+ elsif( current_buffer_state = BUFFER_B2_FULL ) then
+ current_buffer_state_int <= "01";
+ if ( (combined_COMB_DATAREADY_IN = '1') and (buf_SYN_READ_IN = '1') ) then
+ -- COMB logic is writing into the sbuf
+ -- at the same time syn port is reading
+ move_b2_buffer <= '1';
+ next_SYN_DATAREADY_OUT <= '1';
+ elsif( (combined_COMB_DATAREADY_IN = '1') and (buf_SYN_READ_IN = '0') ) then
+ -- ONLY COMB logic is writing into the sbuf
+ -- this is the case when we should use the additional
+ -- buffer
+ next_buffer_state <= BUFFER_B1_FULL;
+ next_next_READ_OUT <= '0'; --PLEASE stop writing
+ move_b1_buffer <= '1';
+ next_SYN_DATAREADY_OUT <= '1';
+ elsif( (combined_COMB_DATAREADY_IN = '0') and (buf_SYN_READ_IN = '1') ) then
+ next_buffer_state <= BUFFER_EMPTY;
+ next_SYN_DATAREADY_OUT <= '0';
+ else
+ next_next_READ_OUT <= '0';
+ next_SYN_DATAREADY_OUT <= '1';
+ end if;
+ elsif( current_buffer_state = BUFFER_B1_FULL ) then
+ current_buffer_state_int <= "10";
+ next_SYN_DATAREADY_OUT <= '1';
+ next_next_READ_OUT <= '0';
+ if ( (combined_COMB_DATAREADY_IN = '1') and (buf_SYN_READ_IN = '1') ) then
+ -- COMB logic is writing into the sbuf
+ -- at the same time syn port is reading
+ use_current_b1_buffer <= '1';
+ move_b1_buffer <= '1';
+ move_b2_buffer <= '1';
+ elsif( (combined_COMB_DATAREADY_IN = '1') and (buf_SYN_READ_IN = '0') ) then
+ -- ONLY COMB logic is writing into the sbuf FATAL ERROR
+ next_got_overflow <= '1';
+ elsif( (combined_COMB_DATAREADY_IN = '0') and (buf_SYN_READ_IN = '1') ) then
+ next_buffer_state <= BUFFER_B2_FULL;
+ next_next_READ_OUT <= '1'; --?
+ use_current_b1_buffer <= '1';
+ move_b1_buffer <= '1';
+ move_b2_buffer <= '1';
+ end if;
+ end if;
+end process THE_COMB_PROC;
+
+-- the next lines are an emergency stop
+-- unfortuanally unregistered
+-- this is needed because the final READ_OUT has
+-- to be known 2 clk cycles in advance, which is
+-- almost impossible taking into account that
+-- the SYN reader may release the RD signal at any point
+-- if this is the case, BREAK
+--combined_COMB_DATAREADY_IN = '0' and SYN_READ_IN = '1'
+THE_EM_STOP_PROC: process(current_next_READ_OUT,
+ current_buffer_state, current_SYN_DATAREADY_OUT, buf_SYN_READ_IN)
+begin
+ if current_SYN_DATAREADY_OUT = '1' and buf_SYN_READ_IN = '0' and current_buffer_state = BUFFER_B2_FULL then
+ COMB_next_READ_OUT <= '0';
+ elsif current_SYN_DATAREADY_OUT = '1' and buf_SYN_READ_IN = '1' and current_buffer_state = BUFFER_B1_FULL then
+ COMB_next_READ_OUT <= '1';
+ else
+ COMB_next_READ_OUT <= current_next_READ_OUT;
+ end if;
+end process THE_EM_STOP_PROC;
+
+THE_REG_PROC: process(CLK)
+begin
+ if( rising_edge(CLK) ) then
+ if ( RESET = '1' ) then
+ current_buffer_state <= BUFFER_EMPTY;
+ current_got_overflow <= '0';
+ current_SYN_DATAREADY_OUT <= '0';
+ current_next_READ_OUT <= '0';
+ elsif( CLK_EN = '1' ) then
+ current_buffer_state <= next_buffer_state;
+ current_got_overflow <= next_got_overflow;
+ current_SYN_DATAREADY_OUT <= next_SYN_DATAREADY_OUT;
+ current_next_READ_OUT <= next_next_READ_OUT;
+ end if;
+ end if;
+end process THE_REG_PROC;
+
+THE_REG2_PROC: process(CLK)
+begin
+ if( rising_edge(CLK) ) then
+ if( move_b1_buffer = '1' ) then
+ current_b1_buffer <= next_b1_buffer;
+ end if;
+ end if;
+end process THE_REG2_PROC;
+
+THE_REG3_PROC: process(CLK)
+begin
+ if( rising_edge(CLK) ) then
+ if( move_b2_buffer = '1' ) then
+ current_b2_buffer <= next_b2_buffer;
+ end if;
+ end if;
+end process THE_REG3_PROC;
+
+end sbuf_arch;
\ No newline at end of file
--- /dev/null
+-- Handler for incoming data stream from SFP
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+entity sfp_rx_handler is
+port(
+ SYSCLK : in std_logic; -- fabric clock
+ RESET_IN : in std_logic; -- synchronous reset
+ --Internal Connection
+ MED_DATA_OUT : out std_logic_vector(15 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ MED_DATAREADY_OUT : out std_logic;
+ MED_READ_IN : in std_logic;
+ -- Reset stuff
+ SEND_RESET_WORDS_OUT : out std_logic;
+ MAKE_TRBNET_RESET_OUT : out std_logic;
+ --SFP Connection
+ SD_RX_DATA_IN : in std_logic_vector(15 downto 0); -- byte swapped data from
+ SD_RX_K_IN : in std_logic_vector(1 downto 0);
+ SD_RX_ALLOW_IN : in std_logic;
+ SD_LINK_OK_IN : in std_logic; -- link OK signal from SerDes
+ SD_SWAP_BYTES_IN : in std_logic; -- swap bytes signal from LSM
+ -- Status and control port
+ TOC_CTR_OUT : out std_logic_vector(9 downto 0);
+ BSM_OUT : out std_logic_vector(3 downto 0);
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+);
+end entity sfp_rx_handler;
+
+architecture Behavioural of sfp_rx_handler is
+
+-- Components
+component fifo_18x16_media_interface is
+port(
+ Data : in std_logic_vector(17 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(17 downto 0);
+ WCNT : out std_logic_vector(4 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic
+);
+end component fifo_18x16_media_interface;
+
+-- Signals
+type STATES is (IDLE, PWAIT, PRH0, PRD0, PRD1, PRD2, PRD3, PTIME, PKILL);
+signal CURRENT_STATE, NEXT_STATE: STATES;
+signal bsm_x : std_logic_vector(3 downto 0);
+
+signal p_wait_x : std_logic; -- at least one data word is in FIFO
+signal p_avail_x : std_logic; -- at least five data words are in FIFO
+signal p_really_x : std_logic; -- at least six data words are in FIFO
+signal p_time_x : std_logic;
+
+signal rx_rden_x : std_logic;
+signal rx_rden : std_logic;
+signal toc_ce_x : std_logic;
+signal toc_ce : std_logic;
+signal toc_rst_x : std_logic;
+signal toc_rst : std_logic;
+signal fatal_toc_x : std_logic;
+signal fatal_toc : std_logic;
+
+signal rx_pnen : std_logic;
+
+signal toc_ctr : unsigned(9 downto 0);
+
+signal fifo_rx_rd_en : std_logic;
+signal fifo_rx_wr_en : std_logic;
+signal fifo_rx_reset : std_logic;
+signal fifo_rx_din : std_logic_vector(17 downto 0);
+signal fifo_rx_dout : std_logic_vector(17 downto 0);
+signal fifo_rx_full : std_logic;
+signal fifo_rx_empty : std_logic;
+signal fifo_rx_aempty : std_logic;
+signal fifo_rx_afull : std_logic;
+signal fifo_rx_wcnt : std_logic_vector(4 downto 0);
+
+signal rx_counter : unsigned(2 downto 0);
+
+signal last_rx : std_logic_vector(8 downto 0);
+
+signal med_dataready : std_logic;
+signal med_data : std_logic_vector(15 downto 0);
+signal med_packet_num : std_logic_vector(2 downto 0);
+
+signal reset_word_cnt : unsigned(4 downto 0);
+signal make_trbnet_reset : std_logic;
+signal send_reset_words : std_logic;
+
+signal debug : std_logic_vector(15 downto 0);
+
+begin
+
+-------------------------------------------------------------------------
+-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
+-------------------------------------------------------------------------
+THE_BYTE_SWAP_PROC: process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ last_rx <= SD_RX_K_IN(1) & SD_RX_DATA_IN(15 downto 8);
+ if( sd_swap_bytes_in = '0' ) then
+ fifo_rx_din <= SD_RX_K_IN(1) & SD_RX_K_IN(0) & SD_RX_DATA_IN(15 downto 8) & SD_RX_DATA_IN(7 downto 0);
+ fifo_rx_wr_en <= not SD_RX_K_IN(0) and SD_RX_ALLOW_IN and SD_LINK_OK_IN;
+ else
+ fifo_rx_din <= SD_RX_K_IN(0) & last_rx(8) & SD_RX_DATA_IN(7 downto 0) & last_rx(7 downto 0);
+ fifo_rx_wr_en <= not last_rx(8) and SD_RX_ALLOW_IN and SD_LINK_OK_IN;
+ end if;
+ end if;
+end process THE_BYTE_SWAP_PROC;
+
+-------------------------------------------------------------------------
+-- We must also take care of the reset K sequences here
+-------------------------------------------------------------------------
+THE_CNT_RESET_PROC : process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ if( RESET_IN = '1' ) then
+ send_reset_words <= '0';
+ make_trbnet_reset <= '0';
+ reset_word_cnt <= (others => '0');
+ else
+ send_reset_words <= '0';
+ make_trbnet_reset <= '0';
+ if( fifo_rx_din = "11" & x"fefe" ) then
+ if( reset_word_cnt(4) = '0' ) then
+ reset_word_cnt <= reset_word_cnt + 1;
+ else
+ send_reset_words <= '1';
+ end if;
+ else
+ reset_word_cnt <= (others => '0');
+ make_trbnet_reset <= std_logic(reset_word_cnt(4));
+ end if;
+ end if;
+ end if;
+end process;
+
+fifo_rx_reset <= RESET_IN or fatal_toc;
+fifo_rx_rd_en <= rx_rden;
+
+-------------------------------------------------------------------------
+-- RX Fifo & Data output
+-------------------------------------------------------------------------
+THE_FIFO_SFP_TO_FPGA: fifo_18x16_media_interface
+port map(
+ Data => fifo_rx_din, -- byte swap process
+ Clock => SYSCLK,
+ WrEn => fifo_rx_wr_en, -- byte swap process
+ RdEn => fifo_rx_rd_en,
+ Reset => fifo_rx_reset,
+ Q => fifo_rx_dout,
+ WCNT => fifo_rx_wcnt,
+ Empty => fifo_rx_empty, -- can be ignored, as we monitor p_wait_x and p_avail_x
+ Full => fifo_rx_full, -- should be monitored!
+ AlmostEmpty => fifo_rx_aempty
+);
+
+
+p_wait_x <= '1' when (fifo_rx_wcnt /= b"00000") else '0';
+
+p_avail_x <= '1' when (fifo_rx_wcnt > b"00100") else '0';
+
+p_really_x <= '1' when (fifo_rx_wcnt > b"00101") else '0';
+
+p_time_x <= '1' when (toc_ctr = b"11_1111_1111") else '0';
+
+-------------------------------------------------------------------------
+-- State machine
+-------------------------------------------------------------------------
+-- state registers
+STATE_MEM: process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ if( RESET_IN = '1' ) then
+ CURRENT_STATE <= IDLE;
+ rx_rden <= '0';
+ toc_ce <= '0';
+ toc_rst <= '0';
+ fatal_toc <= '0';
+ else
+ CURRENT_STATE <= NEXT_STATE;
+ rx_rden <= rx_rden_x;
+ toc_ce <= toc_ce_x;
+ toc_rst <= toc_rst_x;
+ fatal_toc <= fatal_toc_x;
+ end if;
+ end if;
+end process STATE_MEM;
+
+-- state transitions
+STATE_TRANSFORM: process( CURRENT_STATE, p_wait_x, p_avail_x, p_time_x, p_really_x, MED_READ_IN )
+begin
+ NEXT_STATE <= IDLE; -- avoid latches
+ rx_rden_x <= '0';
+ toc_ce_x <= '0';
+ toc_rst_x <= '0';
+ fatal_toc_x <= '0';
+ case CURRENT_STATE is
+ when IDLE => bsm_x <= x"0";
+ if( p_wait_x = '1' ) then
+ NEXT_STATE <= PWAIT;
+ toc_ce_x <= '1';
+ else
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ end if;
+ when PWAIT => bsm_x <= x"1";
+ if ( (p_avail_x = '0') and (p_wait_x = '0') ) then
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ elsif( (p_avail_x = '1') and (MED_READ_IN = '1') ) then
+ NEXT_STATE <= PRH0;
+ rx_rden_x <= '1';
+ toc_rst_x <= '1';
+ elsif( (p_avail_x = '0') and (p_time_x = '1') ) then
+ NEXT_STATE <= PTIME;
+ toc_rst_x <= '1';
+ else
+ NEXT_STATE <= PWAIT;
+ toc_ce_x <= '1';
+ end if;
+ when PRH0 => bsm_x <= x"2";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD0;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRH0;
+ end if;
+ when PRD0 => bsm_x <= x"3";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD1;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD0;
+ end if;
+ when PRD1 => bsm_x <= x"4";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD2;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD1;
+ end if;
+ when PRD2 => bsm_x <= x"5";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD3;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD2;
+ end if;
+ when PRD3 => bsm_x <= x"6";
+ if ( (p_avail_x = '0') and (p_wait_x = '0') ) then
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ elsif( (p_avail_x = '0') and (p_wait_x = '1') ) then
+ NEXT_STATE <= PWAIT;
+ toc_ce_x <= '1';
+ elsif( (p_really_x = '1') and (MED_READ_IN = '1') ) then
+ NEXT_STATE <= PRH0;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD3;
+ end if;
+ when PTIME => bsm_x <= x"8";
+ NEXT_STATE <= PKILL;
+ fatal_toc_x <= '1';
+ when PKILL => bsm_x <= x"9";
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ when others => bsm_x <= x"f";
+ NEXT_STATE <= IDLE;
+ end case;
+end process STATE_TRANSFORM;
+
+-------------------------------------------------------------------------
+-- Timeout counter for incoming packet words
+-------------------------------------------------------------------------
+THE_TOC_CTR_PROC: process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ if ( (RESET_IN = '1') or (toc_rst = '1') ) then
+ toc_ctr <= (others => '0');
+ elsif( toc_ce = '1' ) then
+ toc_ctr <= toc_ctr + 1;
+ end if;
+ end if;
+end process THE_TOC_CTR_PROC;
+
+-------------------------------------------------------------------------
+-- Signal sync
+-------------------------------------------------------------------------
+THE_SYNC_PROC: process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ if( RESET_IN = '1' ) then
+ med_dataready <= '0';
+ rx_pnen <= '0';
+ else
+ med_dataready <= rx_pnen;
+ med_data <= fifo_rx_dout(15 downto 0);
+ med_packet_num <= std_logic_vector(rx_counter);
+ rx_pnen <= rx_rden;
+ end if;
+ end if;
+end process THE_SYNC_PROC;
+
+
+-------------------------------------------------------------------------
+-- RX packet counter
+-------------------------------------------------------------------------
+THE_RX_PACKETS_PROC: process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ if( RESET_IN = '1' ) then
+ rx_counter <= b"100";
+ else
+ if( rx_pnen = '1' ) then
+ if( rx_counter = b"100" ) then
+ rx_counter <= (others => '0');
+ else
+ rx_counter <= rx_counter + 1;
+ end if;
+ end if;
+ end if;
+ end if;
+end process THE_RX_PACKETS_PROC;
+
+
+-------------------------------------------------------------------------
+-- Debug
+-------------------------------------------------------------------------
+debug(15) <= '0';
+debug(14) <= '0';
+debug(13) <= '0';
+debug(12) <= '0';
+debug(11) <= p_time_x;
+debug(10) <= p_really_x;
+debug(9) <= p_avail_x;
+debug(8) <= p_wait_x;
+debug(7 downto 5) <= (others => '0');
+debug(4 downto 0) <= fifo_rx_wcnt;
+
+-------------------------------------------------------------------------
+-- Outputs
+-------------------------------------------------------------------------
+MAKE_TRBNET_RESET_OUT <= make_trbnet_reset;
+SEND_RESET_WORDS_OUT <= send_reset_words;
+
+MED_DATA_OUT <= med_data;
+MED_DATAREADY_OUT <= med_dataready;
+MED_PACKET_NUM_OUT <= med_packet_num;
+
+TOC_CTR_OUT <= std_logic_vector(toc_ctr);
+BSM_OUT <= bsm_x;
+
+DEBUG_OUT <= debug;
+
+end architecture;
\ No newline at end of file
--- /dev/null
+-- Handler for incoming data stream from SFP
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+entity sfp_rx_handler is
+port(
+ SYSCLK : in std_logic; -- fabric clock
+ RESET_IN : in std_logic; -- synchronous reset
+ --Internal Connection
+ MED_DATA_OUT : out std_logic_vector(15 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ MED_DATAREADY_OUT : out std_logic;
+ MED_READ_IN : in std_logic;
+ -- Reset stuff
+ SEND_RESET_WORDS_OUT : out std_logic;
+ MAKE_TRBNET_RESET_OUT : out std_logic;
+ --SFP Connection
+ SD_RX_DATA_IN : in std_logic_vector(15 downto 0); -- byte swapped data from
+ SD_RX_K_IN : in std_logic_vector(1 downto 0);
+ SD_RX_ALLOW_IN : in std_logic;
+ SD_LINK_OK_IN : in std_logic; -- link OK signal from SerDes
+ SD_SWAP_BYTES_IN : in std_logic; -- swap bytes signal from LSM
+ -- Status and control port
+ TOC_CTR_OUT : out std_logic_vector(9 downto 0);
+ BSM_OUT : out std_logic_vector(3 downto 0);
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+);
+end entity sfp_rx_handler;
+
+architecture Behavioural of sfp_rx_handler is
+
+-- Components
+component fifo_18x16_media_interface is
+port(
+ Data : in std_logic_vector(17 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(17 downto 0);
+ WCNT : out std_logic_vector(4 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic
+);
+end component fifo_18x16_media_interface;
+
+component fifo_18x16_media_interface_mb is
+port(
+ Data : in std_logic_vector(17 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ AmEmptySetThresh : in std_logic_vector(3 downto 0);
+ AmEmptyClrThresh : in std_logic_vector(3 downto 0);
+ AmFullSetThresh : in std_logic_vector(3 downto 0);
+ AmFullClrThresh : in std_logic_vector(3 downto 0);
+ Q : out std_logic_vector(17 downto 0);
+ WCNT : out std_logic_vector(4 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ AlmostFull : out std_logic
+);
+end component fifo_18x16_media_interface_mb;
+
+-- Signals
+type STATES is (IDLE, PWAIT, PRH0, PRD0, PRD1, PRD2, PRD3, PTIME, PKILL);
+signal CURRENT_STATE, NEXT_STATE: STATES;
+signal bsm_x : std_logic_vector(3 downto 0);
+
+signal p_wait_x : std_logic;
+signal p_avail_x : std_logic;
+signal p_time_x : std_logic;
+
+signal rx_rden_x : std_logic;
+signal rx_rden : std_logic;
+signal toc_ce_x : std_logic;
+signal toc_ce : std_logic;
+signal toc_rst_x : std_logic;
+signal toc_rst : std_logic;
+signal fatal_toc_x : std_logic;
+signal fatal_toc : std_logic;
+
+signal rx_pnen : std_logic;
+
+signal toc_ctr : unsigned(9 downto 0);
+
+signal fifo_rx_rd_en : std_logic;
+signal fifo_rx_wr_en : std_logic;
+signal fifo_rx_reset : std_logic;
+signal fifo_rx_din : std_logic_vector(17 downto 0);
+signal fifo_rx_dout : std_logic_vector(17 downto 0);
+signal fifo_rx_full : std_logic;
+signal fifo_rx_empty : std_logic;
+signal fifo_rx_aempty : std_logic;
+signal fifo_rx_afull : std_logic;
+signal fifo_rx_wcnt : std_logic_vector(4 downto 0);
+
+signal rx_counter : unsigned(2 downto 0);
+
+signal last_rx : std_logic_vector(8 downto 0);
+
+signal med_dataready : std_logic;
+signal med_data : std_logic_vector(15 downto 0);
+signal med_packet_num : std_logic_vector(2 downto 0);
+
+signal reset_word_cnt : unsigned(4 downto 0);
+signal make_trbnet_reset : std_logic;
+signal send_reset_words : std_logic;
+
+signal debug : std_logic_vector(15 downto 0);
+
+begin
+
+-------------------------------------------------------------------------
+-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
+-------------------------------------------------------------------------
+THE_BYTE_SWAP_PROC: process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ last_rx <= SD_RX_K_IN(1) & SD_RX_DATA_IN(15 downto 8);
+ if( sd_swap_bytes_in = '0' ) then
+ fifo_rx_din <= SD_RX_K_IN(1) & SD_RX_K_IN(0) & SD_RX_DATA_IN(15 downto 8) & SD_RX_DATA_IN(7 downto 0);
+ fifo_rx_wr_en <= not SD_RX_K_IN(0) and SD_RX_ALLOW_IN and SD_LINK_OK_IN;
+ else
+ fifo_rx_din <= SD_RX_K_IN(0) & last_rx(8) & SD_RX_DATA_IN(7 downto 0) & last_rx(7 downto 0);
+ fifo_rx_wr_en <= not last_rx(8) and SD_RX_ALLOW_IN and SD_LINK_OK_IN;
+ end if;
+ end if;
+end process THE_BYTE_SWAP_PROC;
+
+-------------------------------------------------------------------------
+-- We must also take care of the reset K sequences here
+-------------------------------------------------------------------------
+THE_CNT_RESET_PROC : process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ if( RESET_IN = '1' ) then
+ send_reset_words <= '0';
+ make_trbnet_reset <= '0';
+ reset_word_cnt <= (others => '0');
+ else
+ send_reset_words <= '0';
+ make_trbnet_reset <= '0';
+ if( fifo_rx_din = "11" & x"fefe" ) then
+ if( reset_word_cnt(4) = '0' ) then
+ reset_word_cnt <= reset_word_cnt + 1;
+ else
+ send_reset_words <= '1';
+ end if;
+ else
+ reset_word_cnt <= (others => '0');
+ make_trbnet_reset <= std_logic(reset_word_cnt(4));
+ end if;
+ end if;
+ end if;
+end process;
+
+fifo_rx_reset <= RESET_IN or fatal_toc;
+fifo_rx_rd_en <= rx_rden;
+
+-------------------------------------------------------------------------
+-- RX Fifo & Data output
+-------------------------------------------------------------------------
+THE_FIFO_SFP_TO_FPGA: fifo_18x16_media_interface
+port map(
+ Data => fifo_rx_din, -- byte swap process
+ Clock => SYSCLK,
+ WrEn => fifo_rx_wr_en, -- byte swap process
+ RdEn => fifo_rx_rd_en,
+ Reset => fifo_rx_reset,
+ Q => fifo_rx_dout,
+ WCNT => fifo_rx_wcnt,
+ Empty => fifo_rx_empty, -- can be ignored, as we monitor p_wait_x and p_avail_x
+ Full => fifo_rx_full, -- should be monitored!
+ AlmostEmpty => fifo_rx_aempty
+);
+
+--THE_FIFO_SFP_TO_FPGA: fifo_18x16_media_interface_mb
+--port map(
+-- Data => fifo_rx_din,
+-- Clock => SYSCLK,
+-- WrEn => fifo_rx_wr_en,
+-- RdEn => fifo_rx_rd_en,
+-- Reset => fifo_rx_reset,
+-- AmEmptySetThresh => x"4",
+-- AmEmptyClrThresh => x"6",
+-- AmFullSetThresh => x"e",
+-- AmFullClrThresh => x"c",
+-- Q => fifo_rx_dout,
+-- WCNT => fifo_rx_wcnt,
+-- Empty => fifo_rx_empty, -- can be ignored, as we monitor p_wait_x and p_avail_x
+-- Full => fifo_rx_full, -- should be monitored!
+-- AlmostEmpty => fifo_rx_aempty,
+-- AlmostFull => fifo_rx_afull
+--);
+
+
+p_wait_x <= '1' when (fifo_rx_wcnt /= b"00000") else '0';
+
+p_avail_x <= '1' when (fifo_rx_wcnt > b"00100") else '0';
+
+p_time_x <= '1' when (toc_ctr = b"11_1111_1111") else '0';
+
+-------------------------------------------------------------------------
+-- State machine
+-------------------------------------------------------------------------
+-- state registers
+STATE_MEM: process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ if( RESET_IN = '1' ) then
+ CURRENT_STATE <= IDLE;
+ rx_rden <= '0';
+ toc_ce <= '0';
+ toc_rst <= '0';
+ fatal_toc <= '0';
+ else
+ CURRENT_STATE <= NEXT_STATE;
+ rx_rden <= rx_rden_x;
+ toc_ce <= toc_ce_x;
+ toc_rst <= toc_rst_x;
+ fatal_toc <= fatal_toc_x;
+ end if;
+ end if;
+end process STATE_MEM;
+
+-- state transitions
+STATE_TRANSFORM: process( CURRENT_STATE, p_wait_x, p_avail_x, p_time_x, fifo_rx_rd_en, MED_READ_IN )
+begin
+ NEXT_STATE <= IDLE; -- avoid latches
+ rx_rden_x <= '0';
+ toc_ce_x <= '0';
+ toc_rst_x <= '0';
+ fatal_toc_x <= '0';
+ case CURRENT_STATE is
+ when IDLE => bsm_x <= x"0";
+ if( p_wait_x = '1' ) then
+ NEXT_STATE <= PWAIT;
+ toc_ce_x <= '1';
+ else
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ end if;
+ when PWAIT => bsm_x <= x"1";
+ if ( (p_avail_x = '0') and (p_wait_x = '0') ) then
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ elsif( (p_avail_x = '1') and (MED_READ_IN = '1') ) then
+ NEXT_STATE <= PRH0;
+ rx_rden_x <= '1';
+ toc_rst_x <= '1';
+ elsif( (p_avail_x = '0') and (p_time_x = '1') ) then
+ NEXT_STATE <= PTIME;
+ toc_rst_x <= '1';
+ else
+ NEXT_STATE <= PWAIT;
+ toc_ce_x <= '1';
+ end if;
+ when PRH0 => bsm_x <= x"2";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD0;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRH0;
+ end if;
+ when PRD0 => bsm_x <= x"3";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD1;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD0;
+ end if;
+ when PRD1 => bsm_x <= x"4";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD2;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD1;
+ end if;
+ when PRD2 => bsm_x <= x"5";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD3;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD2;
+ end if;
+ when PRD3 => bsm_x <= x"6";
+ if ( (p_avail_x = '0') and (p_wait_x = '0') ) then
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ elsif( (p_avail_x = '0') and (p_wait_x = '1') ) then
+ NEXT_STATE <= PWAIT;
+ toc_ce_x <= '1';
+ elsif( (p_avail_x = '1') and (MED_READ_IN = '1') and (fifo_rx_rd_en = '0')) then
+ NEXT_STATE <= PRH0;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD3;
+ end if;
+ when PTIME => bsm_x <= x"8";
+ NEXT_STATE <= PKILL;
+ fatal_toc_x <= '1';
+ when PKILL => bsm_x <= x"9";
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ when others => bsm_x <= x"f";
+ NEXT_STATE <= IDLE;
+ end case;
+end process STATE_TRANSFORM;
+
+-------------------------------------------------------------------------
+-- Timeout counter for incoming packet words
+-------------------------------------------------------------------------
+THE_TOC_CTR_PROC: process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ if ( (RESET_IN = '1') or (toc_rst = '1') ) then
+ toc_ctr <= (others => '0');
+ elsif( toc_ce = '1' ) then
+ toc_ctr <= toc_ctr + 1;
+ end if;
+ end if;
+end process THE_TOC_CTR_PROC;
+
+-------------------------------------------------------------------------
+-- Signal sync
+-------------------------------------------------------------------------
+THE_SYNC_PROC: process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ if( RESET_IN = '1' ) then
+ med_dataready <= '0';
+ rx_pnen <= '0';
+ else
+ med_dataready <= rx_pnen;
+ med_data <= fifo_rx_dout(15 downto 0);
+ med_packet_num <= std_logic_vector(rx_counter);
+ rx_pnen <= rx_rden;
+ end if;
+ end if;
+end process THE_SYNC_PROC;
+
+
+-------------------------------------------------------------------------
+-- RX packet counter
+-------------------------------------------------------------------------
+THE_RX_PACKETS_PROC: process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ if( RESET_IN = '1' ) then
+ rx_counter <= b"100";
+ else
+ if( rx_pnen = '1' ) then
+ if( rx_counter = b"100" ) then
+ rx_counter <= (others => '0');
+ else
+ rx_counter <= rx_counter + 1;
+ end if;
+ end if;
+ end if;
+ end if;
+end process THE_RX_PACKETS_PROC;
+
+
+-------------------------------------------------------------------------
+-- Debug
+-------------------------------------------------------------------------
+debug(15) <= fifo_rx_full;
+debug(14) <= fifo_rx_afull;
+debug(13) <= fifo_rx_aempty;
+debug(12) <= fifo_rx_empty;
+debug(11) <= fifo_rx_rd_en;
+debug(10) <= p_time_x;
+debug(9) <= p_avail_x;
+debug(8) <= p_wait_x;
+debug(7 downto 5) <= (others => '0');
+debug(4 downto 0) <= fifo_rx_wcnt;
+
+-------------------------------------------------------------------------
+-- Outputs
+-------------------------------------------------------------------------
+MAKE_TRBNET_RESET_OUT <= make_trbnet_reset;
+SEND_RESET_WORDS_OUT <= send_reset_words;
+
+MED_DATA_OUT <= med_data;
+MED_DATAREADY_OUT <= med_dataready;
+MED_PACKET_NUM_OUT <= med_packet_num;
+
+TOC_CTR_OUT <= std_logic_vector(toc_ctr);
+BSM_OUT <= bsm_x;
+
+DEBUG_OUT <= debug;
+
+end architecture;
\ No newline at end of file
--- /dev/null
+-- Handler for incoming data stream from SFP
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+entity sfp_rx_handler is
+port(
+ SYSCLK : in std_logic; -- fabric clock
+ RESET_IN : in std_logic; -- synchronous reset
+ --Internal Connection
+ MED_DATA_OUT : out std_logic_vector(15 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ MED_DATAREADY_OUT : out std_logic;
+ MED_READ_IN : in std_logic;
+ -- Reset stuff
+ SEND_RESET_WORDS_OUT : out std_logic;
+ MAKE_TRBNET_RESET_OUT : out std_logic;
+ --SFP Connection
+ SD_RX_DATA_IN : in std_logic_vector(15 downto 0); -- byte swapped data from
+ SD_RX_K_IN : in std_logic_vector(1 downto 0);
+ SD_RX_ALLOW_IN : in std_logic;
+ SD_LINK_OK_IN : in std_logic; -- link OK signal from SerDes
+ SD_SWAP_BYTES_IN : in std_logic; -- swap bytes signal from LSM
+ -- Status and control port
+ TOC_CTR_OUT : out std_logic_vector(9 downto 0);
+ BSM_OUT : out std_logic_vector(3 downto 0);
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+);
+end entity sfp_rx_handler;
+
+architecture Behavioural of sfp_rx_handler is
+
+-- Components
+component fifo_18x16_media_interface is
+port(
+ Data : in std_logic_vector(17 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(17 downto 0);
+ WCNT : out std_logic_vector(4 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic
+);
+end component;
+
+-- Signals
+type STATES is (IDLE, PWAIT, PRH0, PRD0, PRD1, PRD2, PRD3, PTIME, PKILL);
+signal CURRENT_STATE, NEXT_STATE: STATES;
+signal bsm_x : std_logic_vector(3 downto 0);
+
+signal p_wait_x : std_logic;
+signal p_avail_x : std_logic;
+signal p_time_x : std_logic;
+
+signal rx_rden_x : std_logic;
+signal rx_rden : std_logic;
+signal toc_ce_x : std_logic;
+signal toc_ce : std_logic;
+signal toc_rst_x : std_logic;
+signal toc_rst : std_logic;
+signal fatal_toc_x : std_logic;
+signal fatal_toc : std_logic;
+
+signal rx_pnen : std_logic;
+
+signal toc_ctr : unsigned(9 downto 0);
+
+signal fifo_rx_rd_en : std_logic;
+signal fifo_rx_wr_en : std_logic;
+signal fifo_rx_reset : std_logic;
+signal fifo_rx_din : std_logic_vector(17 downto 0);
+signal fifo_rx_dout : std_logic_vector(17 downto 0);
+signal fifo_rx_full : std_logic;
+signal fifo_rx_empty : std_logic;
+signal fifo_rx_aempty : std_logic;
+signal fifo_rx_wcnt : std_logic_vector(4 downto 0);
+
+signal rx_counter : unsigned(2 downto 0);
+
+signal last_rx : std_logic_vector(8 downto 0);
+
+signal buf_med_dataready_out : std_logic;
+signal buf_med_data_out : std_logic_vector(15 downto 0);
+signal buf_med_packet_num_out : std_logic_vector(2 downto 0);
+
+signal reset_word_cnt : unsigned(4 downto 0);
+signal make_trbnet_reset : std_logic;
+signal send_reset_words : std_logic;
+
+signal debug : std_logic_vector(15 downto 0);
+
+begin
+
+-------------------------------------------------------------------------
+-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
+-------------------------------------------------------------------------
+THE_BYTE_SWAP_PROC: process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ last_rx <= SD_RX_K_IN(1) & SD_RX_DATA_IN(15 downto 8);
+ if( sd_swap_bytes_in = '0' ) then
+ fifo_rx_din <= SD_RX_K_IN(1) & SD_RX_K_IN(0) & SD_RX_DATA_IN(15 downto 8) & SD_RX_DATA_IN(7 downto 0);
+ fifo_rx_wr_en <= not SD_RX_K_IN(0) and SD_RX_ALLOW_IN and SD_LINK_OK_IN;
+ else
+ fifo_rx_din <= SD_RX_K_IN(0) & last_rx(8) & SD_RX_DATA_IN(7 downto 0) & last_rx(7 downto 0);
+ fifo_rx_wr_en <= not last_rx(8) and SD_RX_ALLOW_IN and SD_LINK_OK_IN;
+ end if;
+ end if;
+end process THE_BYTE_SWAP_PROC;
+
+-------------------------------------------------------------------------
+-- We must also take care of the reset K sequences here
+-------------------------------------------------------------------------
+THE_CNT_RESET_PROC : process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ if( RESET_IN = '1' ) then
+ send_reset_words <= '0';
+ make_trbnet_reset <= '0';
+ reset_word_cnt <= (others => '0');
+ else
+ send_reset_words <= '0';
+ make_trbnet_reset <= '0';
+ if( fifo_rx_din = "11" & x"fefe" ) then
+ if( reset_word_cnt(4) = '0' ) then
+ reset_word_cnt <= reset_word_cnt + 1;
+ else
+ send_reset_words <= '1';
+ end if;
+ else
+ reset_word_cnt <= (others => '0');
+ make_trbnet_reset <= std_logic(reset_word_cnt(4));
+ end if;
+ end if;
+ end if;
+end process;
+
+fifo_rx_reset <= RESET_IN or fatal_toc;
+fifo_rx_rd_en <= rx_rden;
+
+-------------------------------------------------------------------------
+-- RX Fifo & Data output
+-------------------------------------------------------------------------
+THE_FIFO_SFP_TO_FPGA: fifo_18x16_media_interface
+port map(
+ Data => fifo_rx_din, -- byte swap process
+ Clock => SYSCLK,
+ WrEn => fifo_rx_wr_en, -- byte swap process
+ RdEn => fifo_rx_rd_en,
+ Reset => fifo_rx_reset,
+ Q => fifo_rx_dout,
+ WCNT => fifo_rx_wcnt,
+ Empty => fifo_rx_empty, -- can be ignored, as we monitor p_wait_x and p_avail_x
+ Full => fifo_rx_full, -- should be monitored!
+ AlmostEmpty => fifo_rx_aempty
+);
+
+p_wait_x <= '1' when (fifo_rx_wcnt /= b"00000") else '0';
+
+p_avail_x <= '1' when (fifo_rx_wcnt > b"00100") else '0';
+
+p_time_x <= '1' when (toc_ctr = b"11_1111_1111") else '0';
+
+-------------------------------------------------------------------------
+-- State machine
+-------------------------------------------------------------------------
+-- state registers
+STATE_MEM: process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ if( RESET_IN = '1' ) then
+ CURRENT_STATE <= IDLE;
+ rx_rden <= '0';
+ toc_ce <= '0';
+ toc_rst <= '0';
+ fatal_toc <= '0';
+ else
+ CURRENT_STATE <= NEXT_STATE;
+ rx_rden <= rx_rden_x;
+ toc_ce <= toc_ce_x;
+ toc_rst <= toc_rst_x;
+ fatal_toc <= fatal_toc_x;
+ end if;
+ end if;
+end process STATE_MEM;
+
+-- state transitions
+STATE_TRANSFORM: process( CURRENT_STATE, p_wait_x, p_avail_x, p_time_x, rx_rden, MED_READ_IN )
+begin
+ NEXT_STATE <= IDLE; -- avoid latches
+ rx_rden_x <= '0';
+ toc_ce_x <= '0';
+ toc_rst_x <= '0';
+ fatal_toc_x <= '0';
+ case CURRENT_STATE is
+ when IDLE => bsm_x <= x"0";
+ if( p_wait_x = '1' ) then
+ NEXT_STATE <= PWAIT;
+ toc_ce_x <= '1';
+ else
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ end if;
+ when PWAIT => bsm_x <= x"1";
+ if ( (p_avail_x = '0') and (p_wait_x = '0') ) then
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ elsif( (p_avail_x = '1') and (MED_READ_IN = '1') ) then
+ NEXT_STATE <= PRH0;
+ rx_rden_x <= '1';
+ toc_rst_x <= '1';
+ elsif( (p_avail_x = '0') and (p_time_x = '1') ) then
+ NEXT_STATE <= PTIME;
+ toc_rst_x <= '1';
+ else
+ NEXT_STATE <= PWAIT;
+ toc_ce_x <= '1';
+ end if;
+ when PRH0 => bsm_x <= x"2";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD0;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRH0;
+ end if;
+ when PRD0 => bsm_x <= x"3";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD1;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD0;
+ end if;
+ when PRD1 => bsm_x <= x"4";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD2;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD1;
+ end if;
+ when PRD2 => bsm_x <= x"5";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD3;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD2;
+ end if;
+ when PRD3 => bsm_x <= x"6";
+ if ( (p_avail_x = '0') and (p_wait_x = '0') ) then
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ elsif( (p_avail_x = '0') and (p_wait_x = '1') ) then
+ NEXT_STATE <= PWAIT;
+ toc_ce_x <= '1';
+ elsif( (p_avail_x = '1') and (MED_READ_IN = '1') ) then
+ NEXT_STATE <= PRH0;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD3;
+ end if;
+ when PTIME => bsm_x <= x"8";
+ NEXT_STATE <= PKILL;
+ fatal_toc_x <= '1';
+ when PKILL => bsm_x <= x"9";
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ when others => bsm_x <= x"f";
+ NEXT_STATE <= IDLE;
+ end case;
+end process STATE_TRANSFORM;
+
+-------------------------------------------------------------------------
+-- Timeout counter for incoming packet words
+-------------------------------------------------------------------------
+THE_TOC_CTR_PROC: process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ if ( (RESET_IN = '1') or (toc_rst = '1') ) then
+ toc_ctr <= (others => '0');
+ elsif( toc_ce = '1' ) then
+ toc_ctr <= toc_ctr + 1;
+ end if;
+ end if;
+end process THE_TOC_CTR_PROC;
+
+
+buf_med_data_out <= fifo_rx_dout(15 downto 0);
+buf_med_dataready_out <= rx_pnen;
+buf_med_packet_num_out <= std_logic_vector(rx_counter);
+
+-------------------------------------------------------------------------
+-- Signal sync
+-------------------------------------------------------------------------
+THE_SYNC_PROC: process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ if( RESET_IN = '1' ) then
+ med_dataready_out <= '0';
+ rx_pnen <= '0';
+ else
+ med_dataready_out <= buf_med_dataready_out;
+ med_data_out <= buf_med_data_out;
+ med_packet_num_out <= buf_med_packet_num_out;
+ rx_pnen <= rx_rden;
+ end if;
+ end if;
+end process THE_SYNC_PROC;
+
+
+-------------------------------------------------------------------------
+-- RX packet counter
+-------------------------------------------------------------------------
+THE_RX_PACKETS_PROC: process( SYSCLK )
+begin
+ if( rising_edge(SYSCLK) ) then
+ if( RESET_IN = '1' ) then
+ rx_counter <= b"100";
+ else
+ if( rx_pnen = '1' ) then
+ if( rx_counter = b"100" ) then
+ rx_counter <= (others => '0');
+ else
+ rx_counter <= rx_counter + 1;
+ end if;
+ end if;
+ end if;
+ end if;
+end process THE_RX_PACKETS_PROC;
+
+
+-------------------------------------------------------------------------
+-- Debug
+-------------------------------------------------------------------------
+debug(15) <= fifo_rx_wr_en;
+debug(14) <= toc_rst;
+debug(13) <= toc_ce;
+debug(12) <= rx_pnen;
+debug(11) <= rx_rden;
+debug(10) <= p_time_x;
+debug(9) <= p_avail_x;
+debug(8) <= p_wait_x;
+debug(7 downto 5) <= (others => '0');
+debug(4 downto 0) <= fifo_rx_wcnt;
+
+-------------------------------------------------------------------------
+-- Outputs
+-------------------------------------------------------------------------
+DEBUG_OUT <= debug;
+
+MAKE_TRBNET_RESET_OUT <= make_trbnet_reset;
+SEND_RESET_WORDS_OUT <= send_reset_words;
+
+TOC_CTR_OUT <= std_logic_vector(toc_ctr);
+BSM_OUT <= bsm_x;
+
+end architecture;
\ No newline at end of file
STAT_13_IN : in std_logic_vector(15 downto 0);\r
STAT_14_IN : in std_logic_vector(15 downto 0);\r
STAT_15_IN : in std_logic_vector(15 downto 0);\r
+ -- FIFO status\r
+ FIFO_STATUS_0_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_1_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_2_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_3_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_4_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_5_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_6_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_7_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_8_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_9_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_10_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_11_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_12_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_13_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_14_IN : in std_logic_vector(31 downto 0);\r
+ FIFO_STATUS_15_IN : in std_logic_vector(31 downto 0);\r
+ IPU_STATUS_IN : in std_logic_vector(31 downto 0);\r
+ RELEASE_STATUS_IN : in std_logic_vector(31 downto 0);\r
-- some control signals\r
CTRL_LVL_OUT : out std_logic_vector(31 downto 0);\r
CTRL_TRG_OUT : out std_logic_vector(31 downto 0);\r
architecture Behavioral of slave_bus is\r
\r
-- Signals\r
-signal slv_read : std_logic_vector(15-1 downto 0);\r
-signal slv_write : std_logic_vector(15-1 downto 0);\r
-signal slv_busy : std_logic_vector(15-1 downto 0);\r
-signal slv_ack : std_logic_vector(15-1 downto 0);\r
-signal slv_addr : std_logic_vector(15*16-1 downto 0);\r
-signal slv_data_rd : std_logic_vector(15*32-1 downto 0);\r
-signal slv_data_wr : std_logic_vector(15*32-1 downto 0);\r
+signal slv_read : std_logic_vector(18-1 downto 0);\r
+signal slv_write : std_logic_vector(18-1 downto 0);\r
+signal slv_busy : std_logic_vector(18-1 downto 0);\r
+signal slv_ack : std_logic_vector(18-1 downto 0);\r
+signal slv_addr : std_logic_vector(18*16-1 downto 0);\r
+signal slv_data_rd : std_logic_vector(18*32-1 downto 0);\r
+signal slv_data_wr : std_logic_vector(18*32-1 downto 0);\r
\r
-- SPI controller BRAM lines\r
signal spi_bram_addr : std_logic_vector(7 downto 0);\r
-- Bus handler: acts as bridge between RegIO and the FPGA internal slave bus\r
THE_BUS_HANDLER: trb_net16_regio_bus_handler\r
generic map(\r
- PORT_NUMBER => 15,\r
+ PORT_NUMBER => 18,\r
PORT_ADDRESSES => ( 0 => x"a000", -- pedestal memories\r
1 => x"a800", -- threshold memories\r
2 => x"8040", -- I2C master\r
12 => x"f000", -- ADC 0 snooper\r
13 => x"f800", -- ADC 1 snooper\r
14 => x"8000", -- test register (busy)\r
+ 15 => x"7100", -- data buffer status registers\r
+ 16 => x"7200", -- LVL1 release status register\r
+ 17 => x"7202", -- IPU handler status register\r
others => x"0000"),\r
PORT_ADDR_MASK => ( 0 => 11, -- pedestal memories\r
1 => 11, -- threshold memories\r
12 => 10, -- ADC 0 snooper\r
13 => 10, -- ADC 1 snooper\r
14 => 0, -- test register (normal)\r
+ 15 => 4, -- FIFO status registers\r
+ 16 => 0, -- LVL1 release status register\r
+ 17 => 0, -- IPU handler status register\r
others => 0)\r
)\r
port map(\r
- CLK => clk_in,\r
- RESET => reset_in,\r
- DAT_ADDR_IN => regio_addr_in,\r
- DAT_DATA_IN => regio_data_in,\r
- DAT_DATA_OUT => regio_data_out,\r
- DAT_READ_ENABLE_IN => regio_read_enable_in,\r
- DAT_WRITE_ENABLE_IN => regio_write_enable_in,\r
- DAT_TIMEOUT_IN => regio_timeout_in,\r
- DAT_DATAREADY_OUT => regio_dataready_out,\r
- DAT_WRITE_ACK_OUT => regio_write_ack_out,\r
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_out,\r
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_out,\r
+ CLK => CLK_IN,\r
+ RESET => RESET_IN,\r
+ DAT_ADDR_IN => REGIO_ADDR_IN,\r
+ DAT_DATA_IN => REGIO_DATA_IN,\r
+ DAT_DATA_OUT => REGIO_DATA_OUT,\r
+ DAT_READ_ENABLE_IN => REGIO_READ_ENABLE_IN,\r
+ DAT_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_IN,\r
+ DAT_TIMEOUT_IN => REGIO_TIMEOUT_IN,\r
+ DAT_DATAREADY_OUT => REGIO_DATAREADY_OUT,\r
+ DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT,\r
+ DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT,\r
+ DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT,\r
-- pedestal memories\r
BUS_READ_ENABLE_OUT(0) => slv_read(0),\r
BUS_WRITE_ENABLE_OUT(0) => slv_write(0),\r
BUS_WRITE_ACK_IN(14) => slv_ack(14),\r
BUS_NO_MORE_DATA_IN(14) => slv_busy(14),\r
BUS_UNKNOWN_ADDR_IN(14) => '0',\r
+ -- data buffer status registers\r
+ BUS_READ_ENABLE_OUT(15) => slv_read(15),\r
+ BUS_WRITE_ENABLE_OUT(15) => slv_write(15),\r
+ BUS_DATA_OUT(15*32+31 downto 15*32) => slv_data_wr(15*32+31 downto 15*32),\r
+ BUS_DATA_IN(15*32+31 downto 15*32) => slv_data_rd(15*32+31 downto 15*32),\r
+ BUS_ADDR_OUT(15*16+15 downto 15*16) => slv_addr(15*16+15 downto 15*16),\r
+ BUS_TIMEOUT_OUT(15) => open,\r
+ BUS_DATAREADY_IN(15) => slv_ack(15),\r
+ BUS_WRITE_ACK_IN(15) => slv_ack(15),\r
+ BUS_NO_MORE_DATA_IN(15) => slv_busy(15),\r
+ BUS_UNKNOWN_ADDR_IN(15) => '0',\r
+ -- LVL1 release status register\r
+ BUS_READ_ENABLE_OUT(16) => slv_read(16),\r
+ BUS_WRITE_ENABLE_OUT(16) => slv_write(16),\r
+ BUS_DATA_OUT(16*32+31 downto 16*32) => slv_data_wr(16*32+31 downto 16*32),\r
+ BUS_DATA_IN(16*32+31 downto 16*32) => slv_data_rd(16*32+31 downto 16*32),\r
+ BUS_ADDR_OUT(16*16+15 downto 16*16) => slv_addr(16*16+15 downto 16*16),\r
+ BUS_TIMEOUT_OUT(16) => open,\r
+ BUS_DATAREADY_IN(16) => slv_ack(16),\r
+ BUS_WRITE_ACK_IN(16) => slv_ack(16),\r
+ BUS_NO_MORE_DATA_IN(16) => slv_busy(16),\r
+ BUS_UNKNOWN_ADDR_IN(16) => '0',\r
+ -- IPU handler status register\r
+ BUS_READ_ENABLE_OUT(17) => slv_read(17),\r
+ BUS_WRITE_ENABLE_OUT(17) => slv_write(17),\r
+ BUS_DATA_OUT(17*32+31 downto 17*32) => slv_data_wr(17*32+31 downto 17*32),\r
+ BUS_DATA_IN(17*32+31 downto 17*32) => slv_data_rd(17*32+31 downto 17*32),\r
+ BUS_ADDR_OUT(17*16+15 downto 17*16) => slv_addr(17*16+15 downto 17*16),\r
+ BUS_TIMEOUT_OUT(17) => open,\r
+ BUS_DATAREADY_IN(17) => slv_ack(17),\r
+ BUS_WRITE_ACK_IN(17) => slv_ack(17),\r
+ BUS_NO_MORE_DATA_IN(17) => slv_busy(17),\r
+ BUS_UNKNOWN_ADDR_IN(17) => '0',\r
-- debug\r
STAT_DEBUG => stat\r
);\r
------------------------------------------------------------------------------------\r
THE_PED_MEM: slv_ped_thr_mem\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
-- Slave bus\r
SLV_ADDR_IN => slv_addr(0*16+10 downto 0*16),\r
SLV_READ_IN => slv_read(0),\r
SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32),\r
SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32),\r
-- backplane identifier\r
- BACKPLANE_IN => backplane_in,\r
+ BACKPLANE_IN => BACKPLANE_IN,\r
-- I/O to the backend\r
- MEM_CLK_IN => clk_in,\r
- MEM_ADDR_IN => ped_addr_in,\r
- MEM_0_D_OUT => ped_data_0_out,\r
- MEM_1_D_OUT => ped_data_1_out,\r
- MEM_2_D_OUT => ped_data_2_out,\r
- MEM_3_D_OUT => ped_data_3_out,\r
- MEM_4_D_OUT => ped_data_4_out,\r
- MEM_5_D_OUT => ped_data_5_out,\r
- MEM_6_D_OUT => ped_data_6_out,\r
- MEM_7_D_OUT => ped_data_7_out,\r
- MEM_8_D_OUT => ped_data_8_out,\r
- MEM_9_D_OUT => ped_data_9_out,\r
- MEM_10_D_OUT => ped_data_10_out,\r
- MEM_11_D_OUT => ped_data_11_out,\r
- MEM_12_D_OUT => ped_data_12_out,\r
- MEM_13_D_OUT => ped_data_13_out,\r
- MEM_14_D_OUT => ped_data_14_out,\r
- MEM_15_D_OUT => ped_data_15_out,\r
+ MEM_CLK_IN => CLK_IN,\r
+ MEM_ADDR_IN => PED_ADDR_IN,\r
+ MEM_0_D_OUT => PED_DATA_0_OUT,\r
+ MEM_1_D_OUT => PED_DATA_1_OUT,\r
+ MEM_2_D_OUT => PED_DATA_2_OUT,\r
+ MEM_3_D_OUT => PED_DATA_3_OUT,\r
+ MEM_4_D_OUT => PED_DATA_4_OUT,\r
+ MEM_5_D_OUT => PED_DATA_5_OUT,\r
+ MEM_6_D_OUT => PED_DATA_6_OUT,\r
+ MEM_7_D_OUT => PED_DATA_7_OUT,\r
+ MEM_8_D_OUT => PED_DATA_8_OUT,\r
+ MEM_9_D_OUT => PED_DATA_9_OUT,\r
+ MEM_10_D_OUT => PED_DATA_10_OUT,\r
+ MEM_11_D_OUT => PED_DATA_11_OUT,\r
+ MEM_12_D_OUT => PED_DATA_12_OUT,\r
+ MEM_13_D_OUT => PED_DATA_13_OUT,\r
+ MEM_14_D_OUT => PED_DATA_14_OUT,\r
+ MEM_15_D_OUT => PED_DATA_15_OUT,\r
-- Status lines\r
STAT => open\r
);\r
------------------------------------------------------------------------------------\r
THE_THR_MEM: slv_ped_thr_mem\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
-- Slave bus\r
SLV_ADDR_IN => slv_addr(1*16+10 downto 1*16),\r
SLV_READ_IN => slv_read(1),\r
SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),\r
SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),\r
-- backplane identifier\r
- BACKPLANE_IN => backplane_in,\r
+ BACKPLANE_IN => BACKPLANE_IN,\r
-- I/O to the backend\r
- MEM_CLK_IN => clk_in,\r
- MEM_ADDR_IN => thr_addr_in,\r
- MEM_0_D_OUT => thr_data_0_out,\r
- MEM_1_D_OUT => thr_data_1_out,\r
- MEM_2_D_OUT => thr_data_2_out,\r
- MEM_3_D_OUT => thr_data_3_out,\r
- MEM_4_D_OUT => thr_data_4_out,\r
- MEM_5_D_OUT => thr_data_5_out,\r
- MEM_6_D_OUT => thr_data_6_out,\r
- MEM_7_D_OUT => thr_data_7_out,\r
- MEM_8_D_OUT => thr_data_8_out,\r
- MEM_9_D_OUT => thr_data_9_out,\r
- MEM_10_D_OUT => thr_data_10_out,\r
- MEM_11_D_OUT => thr_data_11_out,\r
- MEM_12_D_OUT => thr_data_12_out,\r
- MEM_13_D_OUT => thr_data_13_out,\r
- MEM_14_D_OUT => thr_data_14_out,\r
- MEM_15_D_OUT => thr_data_15_out,\r
+ MEM_CLK_IN => CLK_IN,\r
+ MEM_ADDR_IN => THR_ADDR_IN,\r
+ MEM_0_D_OUT => THR_DATA_0_OUT,\r
+ MEM_1_D_OUT => THR_DATA_1_OUT,\r
+ MEM_2_D_OUT => THR_DATA_2_OUT,\r
+ MEM_3_D_OUT => THR_DATA_3_OUT,\r
+ MEM_4_D_OUT => THR_DATA_4_OUT,\r
+ MEM_5_D_OUT => THR_DATA_5_OUT,\r
+ MEM_6_D_OUT => THR_DATA_6_OUT,\r
+ MEM_7_D_OUT => THR_DATA_7_OUT,\r
+ MEM_8_D_OUT => THR_DATA_8_OUT,\r
+ MEM_9_D_OUT => THR_DATA_9_OUT,\r
+ MEM_10_D_OUT => THR_DATA_10_OUT,\r
+ MEM_11_D_OUT => THR_DATA_11_OUT,\r
+ MEM_12_D_OUT => THR_DATA_12_OUT,\r
+ MEM_13_D_OUT => THR_DATA_13_OUT,\r
+ MEM_14_D_OUT => THR_DATA_14_OUT,\r
+ MEM_15_D_OUT => THR_DATA_15_OUT,\r
-- Status lines\r
STAT => open\r
);\r
------------------------------------------------------------------------------------\r
THE_I2C_MASTER: i2c_master\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
-- Slave bus\r
SLV_READ_IN => slv_read(2),\r
SLV_WRITE_IN => slv_write(2),\r
SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32),\r
SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),\r
-- I2C connections\r
- SDA_IN => sda_in,\r
- SDA_OUT => sda_out,\r
- SCL_IN => scl_in,\r
- SCL_OUT => scl_out,\r
+ SDA_IN => SDA_IN,\r
+ SDA_OUT => SDA_OUT,\r
+ SCL_IN => SCL_IN,\r
+ SCL_OUT => SCL_OUT,\r
-- Status lines\r
STAT => open\r
);\r
------------------------------------------------------------------------------------\r
THE_ONEWIRE_MEMORY: slv_onewire_memory\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
-- Slave bus\r
SLV_ADDR_IN => slv_addr(3*16+5 downto 3*16),\r
SLV_READ_IN => slv_read(3),\r
SLV_WRITE_IN => slv_write(3),\r
SLV_ACK_OUT => slv_ack(3),\r
- SLV_BUSY_OUT => open,\r
+ SLV_BUSY_OUT => slv_busy(3), --open,\r
SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32),\r
-- backplane identifier\r
- BACKPLANE_IN => backplane_in,\r
+ BACKPLANE_IN => BACKPLANE_IN,\r
-- 1Wire lines\r
- ONEWIRE_START_IN => onewire_start_in, -- not used yet\r
- ONEWIRE_INOUT => onewire_inout,\r
- BP_ONEWIRE_INOUT => bp_onewire_inout,\r
+ ONEWIRE_START_IN => ONEWIRE_START_IN, -- not used yet\r
+ ONEWIRE_INOUT => ONEWIRE_INOUT,\r
+ BP_ONEWIRE_INOUT => BP_ONEWIRE_INOUT,\r
-- Status lines\r
STAT => onewire_debug --open\r
);\r
-slv_busy(3) <= '0';\r
+--slv_busy(3) <= '0';\r
\r
------------------------------------------------------------------------------------\r
-- SPI master\r
------------------------------------------------------------------------------------\r
THE_SPI_MASTER: spi_master\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
-- Slave bus\r
BUS_READ_IN => slv_read(4),\r
BUS_WRITE_IN => slv_write(4),\r
------------------------------------------------------------------------------------\r
THE_SPI_MEMORY: spi_databus_memory\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
-- Slave bus\r
BUS_ADDR_IN => slv_addr(5*16+5 downto 5*16),\r
BUS_READ_IN => slv_read(5),\r
RESET_VALUE_CTRL => x"60"\r
)\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
-- Slave bus\r
SLV_READ_IN => slv_read(6),\r
SLV_WRITE_IN => slv_write(6),\r
SLV_DATA_IN => slv_data_wr(6*32+31 downto 6*32),\r
SLV_DATA_OUT => slv_data_rd(6*32+31 downto 6*32),\r
-- SPI connections\r
- SPI_CS_OUT => spi_adc0_cs_out,\r
- SPI_SDO_OUT => spi_adc0_sdo_out,\r
- SPI_SCK_OUT => spi_adc0_sck_out,\r
+ SPI_CS_OUT => SPI_ADC0_CS_OUT,\r
+ SPI_SDO_OUT => SPI_ADC0_SDO_OUT,\r
+ SPI_SCK_OUT => SPI_ADC0_SCK_OUT,\r
-- ADC connections\r
- ADC_LOCKED_IN => adc0_pll_locked_in,\r
- ADC_PD_OUT => adc0_pd_out,\r
- ADC_RST_OUT => adc0_rst_out,\r
- ADC_DEL_OUT => adc0_del_out,\r
+ ADC_LOCKED_IN => ADC0_PLL_LOCKED_IN,\r
+ ADC_PD_OUT => ADC0_PD_OUT,\r
+ ADC_RST_OUT => ADC0_RST_OUT,\r
+ ADC_DEL_OUT => ADC0_DEL_OUT,\r
-- APV connections\r
- APV_RST_OUT => apv0_rst_out,\r
+ APV_RST_OUT => APV0_RST_OUT,\r
-- Status lines\r
STAT => open\r
);\r
RESET_VALUE_CTRL => x"60"\r
)\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
-- Slave bus\r
SLV_READ_IN => slv_read(7),\r
SLV_WRITE_IN => slv_write(7),\r
SLV_BUSY_OUT => slv_busy(7),\r
SLV_ACK_OUT => slv_ack(7),\r
SLV_DATA_IN => slv_data_wr(7*32+31 downto 7*32),\r
- SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32),\r
+ SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32),\r
-- SPI connections\r
- SPI_CS_OUT => spi_adc1_cs_out,\r
- SPI_SDO_OUT => spi_adc1_sdo_out,\r
- SPI_SCK_OUT => spi_adc1_sck_out,\r
+ SPI_CS_OUT => SPI_ADC1_CS_OUT,\r
+ SPI_SDO_OUT => SPI_ADC1_SDO_OUT,\r
+ SPI_SCK_OUT => SPI_ADC1_SCK_OUT,\r
-- ADC connections\r
- ADC_LOCKED_IN => adc1_pll_locked_in,\r
- ADC_PD_OUT => adc1_pd_out,\r
- ADC_RST_OUT => adc1_rst_out,\r
- ADC_DEL_OUT => adc1_del_out,\r
+ ADC_LOCKED_IN => ADC1_PLL_LOCKED_IN,\r
+ ADC_PD_OUT => ADC1_PD_OUT,\r
+ ADC_RST_OUT => ADC1_RST_OUT,\r
+ ADC_DEL_OUT => ADC1_DEL_OUT,\r
-- APV connections\r
- APV_RST_OUT => apv1_rst_out,\r
+ APV_RST_OUT => APV1_RST_OUT,\r
-- Status lines\r
STAT => open\r
);\r
RESET_VALUE => x"0001"\r
)\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
-- Slave bus\r
SLV_ADDR_IN => slv_addr(8*16+3 downto 8*16),\r
SLV_READ_IN => slv_read(8),\r
SLV_DATA_IN => slv_data_wr(8*32+31 downto 8*32),\r
SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32),\r
-- I/O to the backend\r
- BACKPLANE_IN => backplane_in,\r
- CTRL_0_OUT => ctrl_0_out,\r
- CTRL_1_OUT => ctrl_1_out,\r
- CTRL_2_OUT => ctrl_2_out,\r
- CTRL_3_OUT => ctrl_3_out,\r
- CTRL_4_OUT => ctrl_4_out,\r
- CTRL_5_OUT => ctrl_5_out,\r
- CTRL_6_OUT => ctrl_6_out,\r
- CTRL_7_OUT => ctrl_7_out,\r
- CTRL_8_OUT => ctrl_8_out,\r
- CTRL_9_OUT => ctrl_9_out,\r
- CTRL_10_OUT => ctrl_10_out,\r
- CTRL_11_OUT => ctrl_11_out,\r
- CTRL_12_OUT => ctrl_12_out,\r
- CTRL_13_OUT => ctrl_13_out,\r
- CTRL_14_OUT => ctrl_14_out,\r
- CTRL_15_OUT => ctrl_15_out,\r
- STAT_0_IN => stat_0_in,\r
- STAT_1_IN => stat_1_in,\r
- STAT_2_IN => stat_2_in,\r
- STAT_3_IN => stat_3_in,\r
- STAT_4_IN => stat_4_in,\r
- STAT_5_IN => stat_5_in,\r
- STAT_6_IN => stat_6_in,\r
- STAT_7_IN => stat_7_in,\r
- STAT_8_IN => stat_8_in,\r
- STAT_9_IN => stat_9_in,\r
- STAT_10_IN => stat_10_in,\r
- STAT_11_IN => stat_11_in,\r
- STAT_12_IN => stat_12_in,\r
- STAT_13_IN => stat_13_in,\r
- STAT_14_IN => stat_14_in,\r
- STAT_15_IN => stat_15_in,\r
+ BACKPLANE_IN => BACKPLANE_IN,\r
+ CTRL_0_OUT => CTRL_0_OUT,\r
+ CTRL_1_OUT => CTRL_1_OUT,\r
+ CTRL_2_OUT => CTRL_2_OUT,\r
+ CTRL_3_OUT => CTRL_3_OUT,\r
+ CTRL_4_OUT => CTRL_4_OUT,\r
+ CTRL_5_OUT => CTRL_5_OUT,\r
+ CTRL_6_OUT => CTRL_6_OUT,\r
+ CTRL_7_OUT => CTRL_7_OUT,\r
+ CTRL_8_OUT => CTRL_8_OUT,\r
+ CTRL_9_OUT => CTRL_9_OUT,\r
+ CTRL_10_OUT => CTRL_10_OUT,\r
+ CTRL_11_OUT => CTRL_11_OUT,\r
+ CTRL_12_OUT => CTRL_12_OUT,\r
+ CTRL_13_OUT => CTRL_13_OUT,\r
+ CTRL_14_OUT => CTRL_14_OUT,\r
+ CTRL_15_OUT => CTRL_15_OUT,\r
+ STAT_0_IN => STAT_0_IN,\r
+ STAT_1_IN => STAT_1_IN,\r
+ STAT_2_IN => STAT_2_IN,\r
+ STAT_3_IN => STAT_3_IN,\r
+ STAT_4_IN => STAT_4_IN,\r
+ STAT_5_IN => STAT_5_IN,\r
+ STAT_6_IN => STAT_6_IN,\r
+ STAT_7_IN => STAT_7_IN,\r
+ STAT_8_IN => STAT_8_IN,\r
+ STAT_9_IN => STAT_9_IN,\r
+ STAT_10_IN => STAT_10_IN,\r
+ STAT_11_IN => STAT_11_IN,\r
+ STAT_12_IN => STAT_12_IN,\r
+ STAT_13_IN => STAT_13_IN,\r
+ STAT_14_IN => STAT_14_IN,\r
+ STAT_15_IN => STAT_15_IN,\r
-- Status lines\r
STAT => open\r
);\r
slv_busy(8) <= '0';\r
\r
+------------------------------------------------------------------------------------\r
+-- Data buffer status registers\r
+------------------------------------------------------------------------------------\r
+THE_FIFO_STATUS_BANK: slv_status_bank\r
+port map(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ -- Slave bus\r
+ SLV_ADDR_IN => slv_addr(15*16+3 downto 15*16),\r
+ SLV_READ_IN => slv_read(15),\r
+ SLV_WRITE_IN => slv_write(15),\r
+ SLV_ACK_OUT => slv_ack(15),\r
+ SLV_DATA_OUT => slv_data_rd(15*32+31 downto 15*32),\r
+ -- I/O to the backend\r
+ STAT_0_IN => FIFO_STATUS_0_IN,\r
+ STAT_1_IN => FIFO_STATUS_1_IN,\r
+ STAT_2_IN => FIFO_STATUS_2_IN,\r
+ STAT_3_IN => FIFO_STATUS_3_IN,\r
+ STAT_4_IN => FIFO_STATUS_4_IN,\r
+ STAT_5_IN => FIFO_STATUS_5_IN,\r
+ STAT_6_IN => FIFO_STATUS_6_IN,\r
+ STAT_7_IN => FIFO_STATUS_7_IN,\r
+ STAT_8_IN => FIFO_STATUS_8_IN,\r
+ STAT_9_IN => FIFO_STATUS_9_IN,\r
+ STAT_10_IN => FIFO_STATUS_10_IN,\r
+ STAT_11_IN => FIFO_STATUS_11_IN,\r
+ STAT_12_IN => FIFO_STATUS_12_IN,\r
+ STAT_13_IN => FIFO_STATUS_13_IN,\r
+ STAT_14_IN => FIFO_STATUS_14_IN,\r
+ STAT_15_IN => FIFO_STATUS_15_IN\r
+);\r
+slv_busy(15) <= '0';\r
+\r
+\r
+------------------------------------------------------------------------------------\r
+-- LVL1 release status\r
+------------------------------------------------------------------------------------\r
+THE_LVL1_RELEASE_STATUS: slv_status\r
+port map(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(16),\r
+ SLV_WRITE_IN => slv_write(16),\r
+ SLV_ACK_OUT => slv_ack(16),\r
+ SLV_DATA_OUT => slv_data_rd(16*32+31 downto 16*32),\r
+ -- I/O to the backend\r
+ STATUS_IN => RELEASE_STATUS_IN\r
+);\r
+slv_busy(16) <= '0';\r
+\r
+\r
+------------------------------------------------------------------------------------\r
+-- IPU handler status\r
+------------------------------------------------------------------------------------\r
+THE_IPU_HANDLER_STATUS: slv_status\r
+port map(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(17),\r
+ SLV_WRITE_IN => slv_write(17),\r
+ SLV_ACK_OUT => slv_ack(17),\r
+ SLV_DATA_OUT => slv_data_rd(17*32+31 downto 17*32),\r
+ -- I/O to the backend\r
+ STATUS_IN => IPU_STATUS_IN\r
+);\r
+slv_busy(17) <= '0';\r
+\r
+\r
------------------------------------------------------------------------------------\r
-- ADC level register\r
------------------------------------------------------------------------------------\r
THE_ADC_LVL_REG: slv_register\r
generic map(\r
- RESET_VALUE => x"d0_20_78_88"\r
+ RESET_VALUE => x"d0_20_88_78"\r
)\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in, -- general reset\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN, -- general reset\r
BUSY_IN => '0',\r
-- Slave bus\r
SLV_READ_IN => slv_read(9),\r
RESET_VALUE => x"10_10_10_10"\r
)\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in, -- general reset\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN, -- general reset\r
BUSY_IN => '0',\r
-- Slave bus\r
SLV_READ_IN => slv_read(10),\r
RESET_VALUE => x"00_02"\r
)\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in, -- general reset\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN, -- general reset\r
-- Slave bus\r
SLV_READ_IN => slv_read(11),\r
SLV_WRITE_IN => slv_write(11),\r
SLV_DATA_IN => slv_data_wr(11*32+31 downto 11*32),\r
SLV_DATA_OUT => slv_data_rd(11*32+31 downto 11*32),\r
-- I/O to the backend\r
- STATUS_REG_IN => status_pll_in,\r
+ STATUS_REG_IN => STATUS_PLL_IN,\r
CTRL_REG_OUT => ctrl_pll,\r
-- Status lines\r
STAT => open\r
------------------------------------------------------------------------------------\r
THE_ADC0_SNOOPER: slv_adc_snoop\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
-- Slave bus\r
SLV_ADDR_IN => slv_addr(12*16+9 downto 12*16),\r
SLV_READ_IN => slv_read(12),\r
SLV_DATA_IN => slv_data_wr(12*32+31 downto 12*32),\r
SLV_DATA_OUT => slv_data_rd(12*32+31 downto 12*32),\r
-- I/O to the backend\r
- ADC_SEL_OUT => adc0_sel_out,\r
- ADC_CLK_IN => adc0_clk_in,\r
- ADC_DATA_IN => adc0_data_in,\r
+ ADC_SEL_OUT => ADC0_SEL_OUT,\r
+ ADC_CLK_IN => ADC0_CLK_IN,\r
+ ADC_DATA_IN => ADC0_DATA_IN,\r
-- Status lines\r
STAT => open\r
);\r
------------------------------------------------------------------------------------\r
THE_ADC1_SNOOPER: slv_adc_snoop\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
-- Slave bus\r
SLV_ADDR_IN => slv_addr(13*16+9 downto 13*16),\r
SLV_READ_IN => slv_read(13),\r
SLV_DATA_IN => slv_data_wr(13*32+31 downto 13*32),\r
SLV_DATA_OUT => slv_data_rd(13*32+31 downto 13*32),\r
-- I/O to the backend\r
- ADC_SEL_OUT => adc1_sel_out,\r
- ADC_CLK_IN => adc1_clk_in,\r
- ADC_DATA_IN => adc1_data_in,\r
+ ADC_SEL_OUT => ADC1_SEL_OUT,\r
+ ADC_CLK_IN => ADC1_CLK_IN,\r
+ ADC_DATA_IN => ADC1_DATA_IN,\r
-- Status lines\r
STAT => open\r
);\r
RESET_VALUE => x"dead_beef"\r
)\r
port map(\r
- CLK_IN => clk_in,\r
- RESET_IN => reset_in, -- general reset\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN, -- general reset\r
BUSY_IN => '0',\r
-- Slave bus\r
SLV_READ_IN => slv_read(14),\r
SLV_DATA_IN => slv_data_wr(14*32+31 downto 14*32),\r
SLV_DATA_OUT => slv_data_rd(14*32+31 downto 14*32),\r
-- I/O to the backend\r
- REG_DATA_IN => test_reg_in, --x"5a3c_87e1",\r
- REG_DATA_OUT => test_reg_out,\r
+ REG_DATA_IN => TEST_REG_IN, --x"5a3c_87e1",\r
+ REG_DATA_OUT => TEST_REG_OUT,\r
-- Status lines\r
STAT => open\r
);\r
debug(42 downto 0) <= (others => '0');\r
\r
-- input signals\r
-spi_sdi <= spi_sdi_in;\r
+spi_sdi <= SPI_SDI_IN;\r
\r
-- Output signals\r
-spi_cs_out <= spi_cs;\r
-spi_sck_out <= spi_sck;\r
-spi_sdo_out <= spi_sdo;\r
+SPI_CS_OUT <= spi_cs;\r
+SPI_SCK_OUT <= spi_sck;\r
+SPI_SDO_OUT <= spi_sdo;\r
\r
-ctrl_lvl_out <= ctrl_lvl;\r
-ctrl_trg_out <= ctrl_trg;\r
-ctrl_pll_out <= ctrl_pll;\r
+CTRL_LVL_OUT <= ctrl_lvl;\r
+CTRL_TRG_OUT <= ctrl_trg;\r
+CTRL_PLL_OUT <= ctrl_pll;\r
\r
-debug_out <= debug;\r
+DEBUG_OUT <= debug;\r
\r
end Behavioral;\r
architecture Behavioral of slv_onewire_memory is\r
\r
-- Signals\r
-type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+type STATES is (SLEEP,RD_RDY,WR_RDY,WR_BSY,RD_ACK,WR_ACK,DONE);\r
signal CURRENT_STATE, NEXT_STATE: STATES;\r
\r
-- slave bus signals\r
signal slv_ack_x : std_logic;\r
signal slv_ack : std_logic;\r
+signal slv_busy_x : std_logic;\r
signal slv_busy : std_logic;\r
signal store_wr_x : std_logic;\r
signal store_wr : std_logic;\r
signal store_rd_x : std_logic;\r
signal store_rd : std_logic;\r
\r
+signal wire_busy : std_logic;\r
+\r
-- for replacing the lost FE with BP data\r
signal wr_addr_q : std_logic_vector(6 downto 0); -- some bits are masked\r
signal wr_data_q : std_logic_vector(15 downto 0);\r
\r
signal onewire_bsm : std_logic_vector(7 downto 0);\r
\r
+signal readout_start : std_logic;\r
+\r
begin\r
\r
-- Fake\r
stat(63 downto 40) <= (others => '0');\r
\r
stat(39 downto 32) <= buf_slv_data_out(7 downto 0);\r
-stat(31 downto 26) <= slv_addr_in;\r
-stat(25) <= slv_write_in;\r
-stat(24) <= slv_read_in;\r
+stat(31 downto 26) <= SLV_ADDR_IN;\r
+stat(25) <= SLV_WRITE_IN;\r
+stat(24) <= SLV_READ_IN;\r
stat(23) <= store_wr;\r
stat(22) <= store_rd;\r
stat(21) <= slv_ack;\r
-- Remap the 1Wire chips to Luigi's world\r
THE_ADC_ONEWIRE_MAP_MEM: adc_onewire_map_mem\r
port map(\r
- ADDRESS(6 downto 4) => backplane_in,\r
- ADDRESS(3 downto 0) => slv_addr_in(5 downto 2),\r
+ ADDRESS(6 downto 4) => BACKPLANE_IN,\r
+ ADDRESS(3 downto 0) => SLV_ADDR_IN(5 downto 2),\r
Q => read_address(5 downto 2)\r
);\r
-read_address(1 downto 0) <= slv_addr_in(1 downto 0);\r
+read_address(1 downto 0) <= SLV_ADDR_IN(1 downto 0);\r
\r
-- One APV FE connector is missing ("Roman's FE"), and replace the\r
-- 1Wire ID by the backplane\r
THE_ONEWIRE_SPARE_ONE: onewire_spare_one\r
port map(\r
- ADDRESS => backplane_in,\r
+ ADDRESS => BACKPLANE_IN,\r
Q => missing_one\r
);\r
\r
-- Statemachine --\r
---------------------------------------------------------\r
-- State memory process\r
-STATE_MEM: process( clk_in )\r
+STATE_MEM: process( CLK_IN )\r
begin\r
- if( rising_edge(clk_in) ) then\r
- if( reset_in = '1' ) then\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
CURRENT_STATE <= SLEEP;\r
slv_ack <= '0';\r
+ slv_busy <= '0';\r
store_wr <= '0';\r
store_rd <= '0';\r
else\r
CURRENT_STATE <= NEXT_STATE;\r
slv_ack <= slv_ack_x;\r
+ slv_busy <= slv_busy_x;\r
store_wr <= store_wr_x;\r
store_rd <= store_rd_x;\r
end if;\r
end process STATE_MEM;\r
\r
-- Transition matrix\r
-TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in )\r
+TRANSFORM: process(CURRENT_STATE, SLV_READ_IN, SLV_WRITE_IN, wire_busy )\r
begin\r
NEXT_STATE <= SLEEP;\r
slv_ack_x <= '0';\r
+ slv_busy_x <= '0';\r
store_wr_x <= '0';\r
store_rd_x <= '0';\r
case CURRENT_STATE is\r
- when SLEEP => if ( (slv_read_in = '1') ) then\r
- NEXT_STATE <= RD_RDY;\r
+ when SLEEP => if ( (SLV_READ_IN = '1') ) then\r
+ NEXT_STATE <= RD_RDY; -- read is always possible\r
store_rd_x <= '1';\r
- elsif( (slv_write_in = '1') ) then\r
- NEXT_STATE <= WR_RDY;\r
+ elsif( (wire_busy = '0') and (SLV_WRITE_IN = '1') ) then\r
+ NEXT_STATE <= WR_RDY; -- write starts accessing 1Wire, so it is protected\r
store_wr_x <= '1';\r
+ elsif( (wire_busy = '1') and (SLV_WRITE_IN = '1') ) then\r
+ NEXT_STATE <= WR_BSY; -- access in progress, don't touch\r
+ slv_busy_x <= '1';\r
else\r
NEXT_STATE <= SLEEP;\r
end if;\r
when RD_RDY => NEXT_STATE <= RD_ACK;\r
when WR_RDY => NEXT_STATE <= WR_ACK;\r
- when RD_ACK => if( slv_read_in = '0' ) then\r
+ when RD_ACK => if( SLV_READ_IN = '0' ) then\r
NEXT_STATE <= DONE;\r
slv_ack_x <= '1';\r
else\r
NEXT_STATE <= RD_ACK;\r
slv_ack_x <= '1';\r
end if;\r
- when WR_ACK => if( slv_write_in = '0' ) then\r
+ when WR_ACK => if( SLV_WRITE_IN = '0' ) then\r
NEXT_STATE <= DONE;\r
slv_ack_x <= '1';\r
else\r
NEXT_STATE <= WR_ACK;\r
slv_ack_x <= '1';\r
end if;\r
+ when WR_BSY => if( SLV_WRITE_IN = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_BSY;\r
+ slv_busy_x <= '1';\r
+ end if;\r
when DONE => NEXT_STATE <= SLEEP;\r
\r
when others => NEXT_STATE <= SLEEP;\r
end case;\r
end process TRANSFORM;\r
\r
+-- Start 1W readout, either by slow control access, or by automatic periodical signal\r
+readout_start <= store_wr or (ONEWIRE_START_IN and not wire_busy);\r
\r
---------------------------------------------------------\r
-- 1 Wire master --\r
THE_ONEWIRE_MASTER: onewire_master\r
generic map( CLK_PERIOD => 10 )\r
port map(\r
- CLK => clk_in,\r
- RESET => reset_in,\r
- READOUT_ENABLE_IN => store_wr,\r
+ CLK => CLK_IN,\r
+ RESET => RESET_IN,\r
+ READOUT_ENABLE_IN => readout_start, --store_wr,\r
-- connection to 1-wire interface (16 APV FEs)\r
- ONEWIRE => onewire_inout,\r
- BP_ONEWIRE => bp_onewire_inout,\r
+ ONEWIRE => ONEWIRE_INOUT,\r
+ BP_ONEWIRE => BP_ONEWIRE_INOUT,\r
-- connection to external DPRAM for slow control readout\r
BP_DATA_OUT => wr_bp_data,\r
DATA_OUT => wr_data,\r
ADDR_OUT => wr_addr,\r
WRITE_OUT => wr_we,\r
- BUSY_OUT => slv_busy, -- could be used...\r
+ BUSY_OUT => wire_busy, --slv_busy, -- could be used...\r
-- debug\r
BSM_OUT => onewire_bsm,\r
STAT => open\r
---------------------------------------------------------\r
-- data replacing --\r
---------------------------------------------------------\r
-THE_DATA_REPLACE_PROC: process(clk_in)\r
+THE_DATA_REPLACE_PROC: process( CLK_IN )\r
begin\r
- if( rising_edge(clk_in) ) then\r
+ if( rising_edge(CLK_IN) ) then\r
wr_addr_q <= wr_addr;\r
wr_we_q <= wr_we;\r
if( overlay = '1' ) then\r
RDADDRESS => read_address,\r
DATA => wr_data_q,\r
WE => wr_we_q,\r
- RDCLOCK => clk_in,\r
+ RDCLOCK => CLK_IN,\r
RDCLOCKEN => '1',\r
- RESET => reset_in,\r
- WRCLOCK => clk_in,\r
+ RESET => RESET_IN,\r
+ WRCLOCK => CLK_IN,\r
WRCLOCKEN => '1',\r
Q => buf_slv_data_out\r
);\r
\r
\r
-\r
-- output signals\r
-slv_data_out <= buf_slv_data_out;\r
-slv_ack_out <= slv_ack;\r
-slv_busy_out <= slv_busy;\r
+SLV_DATA_OUT <= buf_slv_data_out;\r
+SLV_ACK_OUT <= slv_ack;\r
+SLV_BUSY_OUT <= slv_busy;\r
\r
end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity slv_status is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ STATUS_IN : in std_logic_vector(31 downto 0)\r
+);\r
+end entity;\r
+\r
+architecture Behavioral of slv_status is\r
+\r
+-- Signals\r
+type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+signal slv_ack_x : std_logic;\r
+signal slv_ack : std_logic;\r
+\r
+signal rdback_data : std_logic_vector(31 downto 0);\r
+\r
+begin\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_ack <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_ack <= slv_ack_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process( CURRENT_STATE, slv_read_in, slv_write_in )\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_ack_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( slv_read_in = '1' ) then\r
+ NEXT_STATE <= RD_DEL0;\r
+ elsif( slv_write_in = '1' ) then\r
+ NEXT_STATE <= WR_DEL0;\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
+ when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
+ when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+---------------------------------------------------------\r
+-- data handling --\r
+---------------------------------------------------------\r
+rdback_data <= status_in;\r
+\r
+---------------------------------------------------------\r
+-- output signals --\r
+---------------------------------------------------------\r
+\r
+slv_ack_out <= slv_ack;\r
+slv_data_out <= rdback_data;\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity slv_status_bank is\r
+port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(3 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ STAT_0_IN : in std_logic_vector(31 downto 0);\r
+ STAT_1_IN : in std_logic_vector(31 downto 0);\r
+ STAT_2_IN : in std_logic_vector(31 downto 0);\r
+ STAT_3_IN : in std_logic_vector(31 downto 0);\r
+ STAT_4_IN : in std_logic_vector(31 downto 0);\r
+ STAT_5_IN : in std_logic_vector(31 downto 0);\r
+ STAT_6_IN : in std_logic_vector(31 downto 0);\r
+ STAT_7_IN : in std_logic_vector(31 downto 0);\r
+ STAT_8_IN : in std_logic_vector(31 downto 0);\r
+ STAT_9_IN : in std_logic_vector(31 downto 0);\r
+ STAT_10_IN : in std_logic_vector(31 downto 0);\r
+ STAT_11_IN : in std_logic_vector(31 downto 0);\r
+ STAT_12_IN : in std_logic_vector(31 downto 0);\r
+ STAT_13_IN : in std_logic_vector(31 downto 0);\r
+ STAT_14_IN : in std_logic_vector(31 downto 0);\r
+ STAT_15_IN : in std_logic_vector(31 downto 0)\r
+);\r
+end entity;\r
+\r
+architecture Behavioral of slv_status_bank is\r
+\r
+-- Signals\r
+type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+signal slv_ack_x : std_logic;\r
+signal slv_ack : std_logic;\r
+\r
+signal rdback_data : std_logic_vector(31 downto 0);\r
+\r
+begin\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_ack <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_ack <= slv_ack_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process( CURRENT_STATE, slv_read_in, slv_write_in )\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_ack_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( slv_read_in = '1' ) then\r
+ NEXT_STATE <= RD_DEL0;\r
+ elsif( slv_write_in = '1' ) then\r
+ NEXT_STATE <= WR_DEL0;\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
+ when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
+ when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+---------------------------------------------------------\r
+-- data handling --\r
+---------------------------------------------------------\r
+THE_REG_SEL_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ case slv_addr_in is\r
+ when x"0" => rdback_data <= stat_0_in; \r
+ when x"1" => rdback_data <= stat_1_in; \r
+ when x"2" => rdback_data <= stat_2_in; \r
+ when x"3" => rdback_data <= stat_3_in; \r
+ when x"4" => rdback_data <= stat_4_in; \r
+ when x"5" => rdback_data <= stat_5_in; \r
+ when x"6" => rdback_data <= stat_6_in; \r
+ when x"7" => rdback_data <= stat_7_in; \r
+ when x"8" => rdback_data <= stat_8_in; \r
+ when x"9" => rdback_data <= stat_9_in; \r
+ when x"a" => rdback_data <= stat_10_in;\r
+ when x"b" => rdback_data <= stat_11_in;\r
+ when x"c" => rdback_data <= stat_12_in;\r
+ when x"d" => rdback_data <= stat_13_in;\r
+ when x"e" => rdback_data <= stat_14_in;\r
+ when x"f" => rdback_data <= stat_15_in;\r
+ when others => rdback_data <= x"0000_0000";\r
+ end case;\r
+ end if;\r
+end process THE_REG_SEL_PROC;\r
+\r
+---------------------------------------------------------\r
+-- output signals --\r
+---------------------------------------------------------\r
+\r
+slv_ack_out <= slv_ack;\r
+slv_data_out <= rdback_data;\r
+\r
+end Behavioral;\r
library ieee;\r
use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.adcmv3_components.all;\r
architecture behavioral of state_sync is\r
\r
-- normal signals\r
-signal sync_q : std_logic;\r
-signal sync_qq : std_logic;\r
+signal sync : std_logic_vector(1 downto 0);\r
\r
begin\r
\r
-- synchronizing stage for clock domain B\r
-THE_SYNC_STAGE_PROC: process( clk_b_in )\r
+THE_SYNC_STAGE_PROC: process( CLK_B_IN )\r
begin\r
- if( rising_edge(clk_b_in) ) then\r
- if( reset_b_in = '1' ) then\r
- sync_q <= '0'; sync_qq <= '0';\r
+ if( rising_edge(CLK_B_IN) ) then\r
+ if( RESET_B_IN = '1' ) then\r
+ sync <= (others => '0');\r
else\r
- sync_qq <= sync_q;\r
- sync_q <= state_a_in;\r
+ sync <= sync(0) & STATE_A_IN;\r
end if;\r
end if;\r
end process THE_SYNC_STAGE_PROC;\r
\r
-- output signals\r
-state_b_out <= sync_qq;\r
+STATE_B_OUT <= sync(1);\r
\r
end behavioral;\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=PLL\r
+CoreRevision=5.1\r
+ModuleName=sync_pll_40m\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=04/28/2010\r
+Time=15:46:16\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=None\r
+Order=None\r
+IO=0\r
+Type=ehxpllb\r
+mode=normal\r
+IFrq=40\r
+OFrq=40.000000\r
+KFrq=\r
+U_OFrq=40\r
+U_KFrq=50\r
+OP_Tol=0.0\r
+OK_Tol=0.0\r
+Div=1\r
+Mult=1\r
+Post=32\r
+SecD=2\r
+fb_mode=Internal\r
+PhaseDuty=Static\r
+DelayControl=AUTO_NO_DELAY\r
+External=DISABLED\r
+PCDR=1\r
+ClkOPBp=0\r
+EnCLKOS=0\r
+ClkOSBp=0\r
+Phase=0.0\r
+Duty=8\r
+DPD=50% Duty\r
+EnCLKOK=0\r
+ClkOKBp=0\r
+ClkRst=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 5.1
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n sync_pll_40m -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 40 -phase_cntl STATIC -fclkop 40 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode INTERNAL -extcap DISABLED -noclkos -noclkok -use_rst -e
+
+-- Wed Apr 28 15:46:17 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity sync_pll_40m is
+ port (
+ CLK: in std_logic;
+ RESET: in std_logic;
+ CLKOP: out std_logic;
+ LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of sync_pll_40m : entity is true;
+end sync_pll_40m;
+
+architecture Structure of sync_pll_40m is
+
+ -- internal signal declarations
+ signal CLKOP_t: std_logic;
+ signal CLKFB_t: std_logic;
+ signal scuba_vlo: std_logic;
+ signal CLK_t: std_logic;
+
+ -- local component declarations
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component EPLLD
+ -- synopsys translate_off
+ generic (PLLCAP : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ DUTY : in Integer; PHASEADJ : in String;
+ PHASE_CNTL : in String; CLKOK_DIV : in Integer;
+ CLKFB_DIV : in Integer; CLKOP_DIV : in Integer;
+ CLKI_DIV : in Integer);
+ -- synopsys translate_on
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; DPAMODE: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic;
+ CLKOK: out std_logic; LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ attribute PLLCAP : string;
+ attribute PLLTYPE : string;
+ attribute CLKOK_BYPASS : string;
+ attribute FREQUENCY_PIN_CLKOK : string;
+ attribute CLKOK_DIV : string;
+ attribute CLKOS_BYPASS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute CLKOP_BYPASS : string;
+ attribute PHASE_CNTL : string;
+ attribute FDEL : string;
+ attribute DUTY : string;
+ attribute PHASEADJ : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute CLKOP_DIV : string;
+ attribute CLKFB_DIV : string;
+ attribute CLKI_DIV : string;
+ attribute FIN : string;
+ attribute PLLCAP of PLLDInst_0 : label is "DISABLED";
+ attribute PLLTYPE of PLLDInst_0 : label is "AUTO";
+ attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED";
+ attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "50.000000";
+ attribute CLKOK_DIV of PLLDInst_0 : label is "2";
+ attribute CLKOS_BYPASS of PLLDInst_0 : label is "DISABLED";
+ attribute FREQUENCY_PIN_CLKOP of PLLDInst_0 : label is "40.000000";
+ attribute CLKOP_BYPASS of PLLDInst_0 : label is "DISABLED";
+ attribute PHASE_CNTL of PLLDInst_0 : label is "STATIC";
+ attribute FDEL of PLLDInst_0 : label is "0";
+ attribute DUTY of PLLDInst_0 : label is "8";
+ attribute PHASEADJ of PLLDInst_0 : label is "0.0";
+ attribute FREQUENCY_PIN_CLKI of PLLDInst_0 : label is "40.000000";
+ attribute CLKOP_DIV of PLLDInst_0 : label is "32";
+ attribute CLKFB_DIV of PLLDInst_0 : label is "1";
+ attribute CLKI_DIV of PLLDInst_0 : label is "1";
+ attribute FIN of PLLDInst_0 : label is "40.000000";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLDInst_0: EPLLD
+ -- synopsys translate_off
+ generic map (PLLCAP=> "DISABLED", CLKOK_BYPASS=> "DISABLED",
+ CLKOK_DIV=> 2, CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ PHASE_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOP_DIV=> 32,
+ CLKFB_DIV=> 1, CLKI_DIV=> 1)
+ -- synopsys translate_on
+ port map (CLKI=>CLK_t, CLKFB=>CLKFB_t, RST=>RESET,
+ RSTK=>scuba_vlo, DPAMODE=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open,
+ LOCK=>LOCK, CLKINTFB=>CLKFB_t);
+
+ CLKOP <= CLKOP_t;
+ CLK_t <= CLK;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of sync_pll_40m is
+ for Structure
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:EPLLD use entity ecp2m.EPLLD(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT count_unit\r
+ PORT(\r
+ CLOCK : IN std_logic;\r
+ RESET : IN std_logic;\r
+ NCS_IN : IN std_logic;\r
+ MOSI_IN : IN std_logic;\r
+ SCK_IN : IN std_logic;\r
+ COUNT_IN : IN std_logic_vector(7 downto 0); \r
+ MISO_OUT : OUT std_logic;\r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLOCK : std_logic;\r
+ SIGNAL RESET : std_logic;\r
+ SIGNAL NCS_IN : std_logic;\r
+ SIGNAL MOSI_IN : std_logic;\r
+ SIGNAL MISO_OUT : std_logic;\r
+ SIGNAL SCK_IN : std_logic;\r
+ SIGNAL COUNT_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: count_unit PORT MAP(\r
+ CLOCK => CLOCK,\r
+ RESET => RESET,\r
+ NCS_IN => NCS_IN,\r
+ MOSI_IN => MOSI_IN,\r
+ MISO_OUT => MISO_OUT,\r
+ SCK_IN => SCK_IN,\r
+ COUNT_IN => COUNT_IN,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+-- Clock generation\r
+THE_CLOCK_GEN: process\r
+begin\r
+ CLOCK <= '1'; wait for 5.0 ns;\r
+ CLOCK <= '0'; wait for 5.0 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+-- The testbench\r
+THE_TESTBENCH: process\r
+variable databyte : std_logic_vector(7 downto 0) := x"00";\r
+begin\r
+ \r
+ -- Setup signals\r
+ reset <= '0';\r
+ ncs_in <= '1';\r
+ sck_in <= '0';\r
+ mosi_in <= '0';\r
+ data_in <= x"dead_beef";\r
+ -- Reset the whole stuff\r
+ wait until rising_edge(clock);\r
+ reset <= '1';\r
+ wait until rising_edge(clock);\r
+ reset <= '0';\r
+ wait for 900 ns;\r
+\r
+ -- Tests may start now\r
+\r
+ ------------------------------------------------------\r
+ -- INIT\r
+ ncs_in <= '0';\r
+ -- COMMAND_START\r
+ databyte := x"ff";\r
+ for I in 7 downto 0 loop\r
+ wait for 100 ns;\r
+ mosi_in <= databyte(I);\r
+ wait for 100 ns;\r
+ sck_in <= '1';\r
+ wait for 200 ns;\r
+ sck_in <= '0';\r
+ end loop;\r
+ wait for 200 ns;\r
+ -- COMMAND_END\r
+ ncs_in <= '1';\r
+ wait for 2 us;\r
+ ------------------------------------------------------\r
+\r
+ \r
+\r
+ \r
+ -- Stay a while... stay forever!!! Muahahah!!!\r
+ wait;\r
+end process THE_TESTBENCH;\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT count_unit\r
+ PORT(\r
+ CLOCK : IN std_logic;\r
+ RESET : IN std_logic;\r
+ NCS_IN : IN std_logic;\r
+ MOSI_IN : IN std_logic;\r
+ SCK_IN : IN std_logic;\r
+ COUNT_IN : IN std_logic_vector(7 downto 0); \r
+ MISO_OUT : OUT std_logic;\r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLOCK : std_logic;\r
+ SIGNAL RESET : std_logic;\r
+ SIGNAL NCS_IN : std_logic;\r
+ SIGNAL MOSI_IN : std_logic;\r
+ SIGNAL MISO_OUT : std_logic;\r
+ SIGNAL SCK_IN : std_logic;\r
+ SIGNAL COUNT_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: count_unit PORT MAP(\r
+ CLOCK => CLOCK,\r
+ RESET => RESET,\r
+ NCS_IN => NCS_IN,\r
+ MOSI_IN => MOSI_IN,\r
+ MISO_OUT => MISO_OUT,\r
+ SCK_IN => SCK_IN,\r
+ COUNT_IN => COUNT_IN,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+-- Clock generation\r
+THE_CLOCK_GEN: process\r
+begin\r
+ CLOCK <= '1'; wait for 5.0 ns;\r
+ CLOCK <= '0'; wait for 5.0 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+-- The testbench\r
+THE_TESTBENCH: process\r
+variable databyte : std_logic_vector(7 downto 0) := x"00";\r
+begin\r
+ \r
+ -- Setup signals\r
+ reset <= '0';\r
+ ncs_in <= '1';\r
+ sck_in <= '0';\r
+ mosi_in <= '0';\r
+ data_in <= x"dead_beef";\r
+ -- Reset the whole stuff\r
+ wait until rising_edge(clock);\r
+ reset <= '1';\r
+ wait until rising_edge(clock);\r
+ reset <= '0';\r
+ wait for 900 ns;\r
+\r
+ -- Tests may start now\r
+\r
+ ------------------------------------------------------\r
+ -- INIT\r
+ ncs_in <= '0';\r
+ -- COMMAND_START\r
+ databyte := x"ff";\r
+ for I in 7 downto 0 loop\r
+ wait for 100 ns;\r
+ mosi_in <= databyte(I);\r
+ wait for 100 ns;\r
+ sck_in <= '1';\r
+ wait for 200 ns;\r
+ sck_in <= '0';\r
+ end loop;\r
+ wait for 200 ns;\r
+ -- COMMAND_END\r
+ ncs_in <= '1';\r
+ wait for 2 us;\r
+ ------------------------------------------------------\r
+\r
+ \r
+\r
+ \r
+ -- Stay a while... stay forever!!! Muahahah!!!\r
+ wait;\r
+end process THE_TESTBENCH;\r
+END;\r
+\r
+END;\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.8\r
+ModuleName=test_fifo2\r
+SourceFormat=Schematic/VHDL\r
+ParameterFileVersion=1.0\r
+Date=05/20/2010\r
+Time=14:41:10\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=1024\r
+Width=18\r
+regout=0\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=0\r
+PfMode=Static - Dual Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=0\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 1024 -width 18 -depth 1024 -no_enable -pe -1 -pf -1 -e
+
+-- Thu May 20 14:41:10 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity test_fifo2 is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(17 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end test_fifo2;
+
+architecture Structure of test_fifo2 is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal rden_i_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal co5: std_logic;
+ signal cnt_con: std_logic;
+ signal co4: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal co4_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal wren_i: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_10: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal co5_1: std_logic;
+ signal wcount_10: std_logic;
+ signal co4_3: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal ircount_10: std_logic;
+ signal co5_2: std_logic;
+ signal rcount_10: std_logic;
+ signal scuba_vlo: std_logic;
+ signal co4_4: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "test_fifo2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b000";
+ attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000";
+ attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_0_0 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_0_0_0 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "18";
+ attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "18";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t3: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_3: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t2: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_2: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ AND2_t1: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t0: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_1: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ pdp_ram_0_0_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wcount_0,
+ ADA5=>wcount_1, ADA6=>wcount_2, ADA7=>wcount_3,
+ ADA8=>wcount_4, ADA9=>wcount_5, ADA10=>wcount_6,
+ ADA11=>wcount_7, ADA12=>wcount_8, ADA13=>wcount_9,
+ CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>scuba_vlo, ADB4=>rcount_0, ADB5=>rcount_1,
+ ADB6=>rcount_2, ADB7=>rcount_3, ADB8=>rcount_4,
+ ADB9=>rcount_5, ADB10=>rcount_6, ADB11=>rcount_7,
+ ADB12=>rcount_8, ADB13=>rcount_9, CEB=>rden_i, CLKB=>Clock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2),
+ DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7),
+ DOB8=>Q(8), DOB9=>Q(9), DOB10=>Q(10), DOB11=>Q(11),
+ DOB12=>Q(12), DOB13=>Q(13), DOB14=>Q(14), DOB15=>Q(15),
+ DOB16=>Q(16), DOB17=>Q(17));
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_23: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_0);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_0);
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ bdcnt_bctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+
+ bdcnt_bctr_5: CB2
+ port map (CI=>co4, PC0=>fcount_10, PC1=>scuba_vlo, CON=>cnt_con,
+ CO=>co5, NC0=>ifcount_10, NC1=>open);
+
+ e_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ S1=>open);
+
+ e_cmp_0: ALEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ CI=>cmp_ci, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+ e_cmp_5: ALEB2
+ port map (A0=>fcount_10, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ S1=>open);
+
+ g_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ S1=>open);
+
+ g_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ CI=>cmp_ci_1, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
+ CI=>co3_2, GE=>co4_2);
+
+ g_cmp_5: AGEB2
+ port map (A0=>fcount_10, A1=>scuba_vlo, B0=>wren_i_inv,
+ B1=>scuba_vlo, CI=>co4_2, GE=>cmp_ge_d1_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ S1=>open);
+
+ w_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ S1=>open);
+
+ w_ctr_0: CU2
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_ctr_5: CU2
+ port map (CI=>co4_3, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5_1,
+ NC0=>iwcount_10, NC1=>open);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ S1=>open);
+
+ r_ctr_0: CU2
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ r_ctr_5: CU2
+ port map (CI=>co4_4, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_2,
+ NC0=>ircount_10, NC1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of test_fifo2 is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:ALEB2 use entity ecp2m.ALEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:CB2 use entity ecp2m.CB2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- Playground for media interface RX packet stuff
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+entity test_media is
+port(
+ SYSCLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ --Internal Connection
+ MED_DATA_OUT : out std_logic_vector(15 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ MED_DATAREADY_OUT : out std_logic;
+ MED_READ_IN : in std_logic;
+ --SFP Connection
+ SD_RX_DATA_IN : in std_logic_vector(15 downto 0);
+ SD_RX_K_IN : in std_logic_vector(1 downto 0);
+ -- Status and control port
+ TOC_CTR_OUT : out std_logic_vector(9 downto 0);
+ BSM_OUT : out std_logic_vector(3 downto 0);
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+);
+end entity test_media;
+
+architecture Behavioural of test_media is
+
+-- Components
+component fifo_18x16_media_interface is
+port(
+ Data : in std_logic_vector(17 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(17 downto 0);
+ WCNT : out std_logic_vector(4 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic
+);
+end component;
+
+-- Signals
+type STATES is (IDLE, PWAIT, PRH0, PRD0, PRD1, PRD2, PRD3, PTIME, PKILL);
+signal CURRENT_STATE, NEXT_STATE: STATES;
+signal bsm_x : std_logic_vector(3 downto 0);
+
+signal p_wait_x : std_logic;
+signal p_avail_x : std_logic;
+signal p_time_x : std_logic;
+
+signal rx_rden_x : std_logic;
+signal rx_rden : std_logic;
+signal toc_ce_x : std_logic;
+signal toc_ce : std_logic;
+signal toc_rst_x : std_logic;
+signal toc_rst : std_logic;
+signal fatal_toc_x : std_logic;
+signal fatal_toc : std_logic;
+
+signal rx_pnen : std_logic;
+
+signal toc_ctr : unsigned(9 downto 0);
+
+signal fifo_rx_rd_en : std_logic;
+signal fifo_rx_wr_en : std_logic;
+signal fifo_rx_reset : std_logic;
+signal fifo_rx_din : std_logic_vector(17 downto 0);
+signal fifo_rx_dout : std_logic_vector(17 downto 0);
+signal fifo_rx_full : std_logic;
+signal fifo_rx_empty : std_logic;
+signal fifo_rx_aempty : std_logic;
+signal fifo_rx_wcnt : std_logic_vector(4 downto 0);
+
+signal rx_counter : unsigned(2 downto 0);
+
+signal buf_med_dataready_out : std_logic;
+signal buf_med_data_out : std_logic_vector(15 downto 0);
+signal buf_med_packet_num_out : std_logic_vector(2 downto 0);
+signal last_rx : std_logic_vector(8 downto 0);
+signal last_fifo_rx_empty : std_logic;
+
+signal debug : std_logic_vector(15 downto 0);
+
+begin
+
+fifo_rx_din(17 downto 16) <= sd_rx_k_in;
+fifo_rx_din(15 downto 0) <= sd_rx_data_in;
+
+fifo_rx_reset <= reset or fatal_toc;
+fifo_rx_rd_en <= rx_rden;
+fifo_rx_wr_en <= '1' when (sd_rx_k_in = b"00") else '0'; -- accept only data
+
+-------------------------------------------------------------------------
+-- RX Fifo & Data output
+-------------------------------------------------------------------------
+THE_FIFO_SFP_TO_FPGA: fifo_18x16_media_interface
+port map(
+ Data => fifo_rx_din,
+ Clock => sysclk,
+ WrEn => fifo_rx_wr_en,
+ RdEn => fifo_rx_rd_en,
+ Reset => fifo_rx_reset,
+ Q => fifo_rx_dout,
+ WCNT => fifo_rx_wcnt,
+ Empty => fifo_rx_empty,
+ Full => fifo_rx_full,
+ AlmostEmpty => fifo_rx_aempty
+);
+
+p_wait_x <= '1' when (fifo_rx_wcnt /= b"00000") else '0';
+
+p_avail_x <= '1' when (fifo_rx_wcnt > b"00100") else '0';
+
+p_time_x <= '1' when (toc_ctr = b"11_1111_1111") else '0';
+
+-------------------------------------------------------------------------
+-- State machine
+-------------------------------------------------------------------------
+-- state registers
+STATE_MEM: process( sysclk )
+begin
+ if( rising_edge(sysclk) ) then
+ if( reset = '1' ) then
+ CURRENT_STATE <= IDLE;
+ rx_rden <= '0';
+ toc_ce <= '0';
+ toc_rst <= '0';
+ fatal_toc <= '0';
+ else
+ CURRENT_STATE <= NEXT_STATE;
+ rx_rden <= rx_rden_x;
+ toc_ce <= toc_ce_x;
+ toc_rst <= toc_rst_x;
+ fatal_toc <= fatal_toc_x;
+ end if;
+ end if;
+end process STATE_MEM;
+
+-- state transitions
+STATE_TRANSFORM: process( CURRENT_STATE, p_wait_x, p_avail_x, p_time_x, rx_rden, MED_READ_IN )
+begin
+ NEXT_STATE <= IDLE; -- avoid latches
+ rx_rden_x <= '0';
+ toc_ce_x <= '0';
+ toc_rst_x <= '0';
+ fatal_toc_x <= '0';
+ case CURRENT_STATE is
+ when IDLE => bsm_x <= x"0";
+ if( p_wait_x = '1' ) then
+ NEXT_STATE <= PWAIT;
+ toc_ce_x <= '1';
+ else
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ end if;
+ when PWAIT => bsm_x <= x"1";
+ if ( (p_avail_x = '0') and (p_wait_x = '0') ) then
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ elsif( (p_avail_x = '1') and (MED_READ_IN = '1') ) then
+ NEXT_STATE <= PRH0;
+ rx_rden_x <= '1';
+ toc_rst_x <= '1';
+ elsif( (p_avail_x = '0') and (p_time_x = '1') ) then
+ NEXT_STATE <= PTIME;
+ toc_rst_x <= '1';
+ else
+ NEXT_STATE <= PWAIT;
+ toc_ce_x <= '1';
+ end if;
+ when PRH0 => bsm_x <= x"2";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD0;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRH0;
+ end if;
+ when PRD0 => bsm_x <= x"3";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD1;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD0;
+ end if;
+ when PRD1 => bsm_x <= x"4";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD2;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD1;
+ end if;
+ when PRD2 => bsm_x <= x"5";
+ if( MED_READ_IN = '1' ) then
+ NEXT_STATE <= PRD3;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD2;
+ end if;
+ when PRD3 => bsm_x <= x"6";
+ if ( (p_avail_x = '0') and (p_wait_x = '0') ) then
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ elsif( (p_avail_x = '0') and (p_wait_x = '1') ) then
+ NEXT_STATE <= PWAIT;
+ toc_ce_x <= '1';
+ elsif( (p_avail_x = '1') and (MED_READ_IN = '1') ) then
+ NEXT_STATE <= PRH0;
+ rx_rden_x <= '1';
+ else
+ NEXT_STATE <= PRD3;
+ end if;
+ when PTIME => bsm_x <= x"8";
+ NEXT_STATE <= PKILL;
+ fatal_toc_x <= '1';
+ when PKILL => bsm_x <= x"9";
+ NEXT_STATE <= IDLE;
+ toc_rst_x <= '1';
+ when others => bsm_x <= x"f";
+ NEXT_STATE <= IDLE;
+ end case;
+end process STATE_TRANSFORM;
+
+-------------------------------------------------------------------------
+-- Timeout counter for incoming packet words
+-------------------------------------------------------------------------
+THE_TOC_CTR_PROC: process( sysclk )
+begin
+ if( rising_edge(sysclk) ) then
+ if ( (reset = '1') or (toc_rst = '1') ) then
+ toc_ctr <= (others => '0');
+ elsif( toc_ce = '1' ) then
+ toc_ctr <= toc_ctr + 1;
+ end if;
+ end if;
+end process THE_TOC_CTR_PROC;
+
+
+buf_med_data_out <= fifo_rx_dout(15 downto 0);
+buf_med_dataready_out <= rx_pnen;
+buf_med_packet_num_out <= std_logic_vector(rx_counter);
+
+-------------------------------------------------------------------------
+-- Signal sync
+-------------------------------------------------------------------------
+THE_SYNC_PROC: process( sysclk )
+begin
+ if( rising_edge(sysclk) ) then
+ if( reset = '1' ) then
+ med_dataready_out <= '0';
+ rx_pnen <= '0';
+ else
+ med_dataready_out <= buf_med_dataready_out;
+ med_data_out <= buf_med_data_out;
+ med_packet_num_out <= buf_med_packet_num_out;
+ rx_pnen <= rx_rden;
+ end if;
+ end if;
+end process THE_SYNC_PROC;
+
+
+-------------------------------------------------------------------------
+-- RX packet counter
+-------------------------------------------------------------------------
+THE_RX_PACKETS_PROC: process( sysclk )
+begin
+ if( rising_edge(sysclk) ) then
+ last_fifo_rx_empty <= fifo_rx_empty;
+ if( reset = '1' ) then
+ rx_counter <= b"100";
+ else
+ if( rx_pnen = '1' ) then
+ if( rx_counter = b"100" ) then
+ rx_counter <= (others => '0');
+ else
+ rx_counter <= rx_counter + 1;
+ end if;
+ end if;
+ end if;
+ end if;
+end process THE_RX_PACKETS_PROC;
+
+
+-------------------------------------------------------------------------
+-- Debug
+-------------------------------------------------------------------------
+debug(15) <= fatal_toc;
+debug(14) <= toc_rst;
+debug(13) <= toc_ce;
+debug(12) <= rx_pnen;
+debug(11) <= rx_rden;
+debug(10) <= p_time_x;
+debug(9) <= p_avail_x;
+debug(8) <= p_wait_x;
+debug(7 downto 5) <= (others => '0');
+debug(4 downto 0) <= fifo_rx_wcnt;
+
+-------------------------------------------------------------------------
+-- Outputs
+-------------------------------------------------------------------------
+debug_out <= debug;
+
+toc_ctr_out <= std_logic_vector(toc_ctr);
+bsm_out <= bsm_x;
+
+end architecture;
\ No newline at end of file
--- /dev/null
+List of features to be included in TRBnet compliant endpoints
+=============================================================
+
+(1) Functions
+ - Common Control Register 0
+ - General Reset bits (Bits 3,2,1)
+ * Bit 3: general reset (user, implemented)
+ * Bit 2: IPU logic reset (user)
+ - Bit 1: trigger logic reset (user)
+ * Reset frontends (Bit 0, if possible) (user, implemented, also on legacy registers)
+ * Reboot FPGA (Bit 15, if possible) (user, implemented)
+ * Faked timing trigger (Bit 16) (user, 19-16 implemented)
+ * correct generics for endpoint
+ * hardware ID (user, implemented)
+ * broadcast mask (user, implemented)
+ * compile time / design version (user, implemented)
+ - correct error flags in LVL1 error pattern
+ - buffer half full (endpoint_full_handler or user)
+ - almost full (endpoint_full_handler or user)
+ - counter mismatch (endpoint_full_handler or user)
+ X timing trigger missing (endpoint)
+ * not configured (user)
+ * frontend error (user)
+ * LVL1 trigger information
+ * suppress output (Bit 0) (endpoint_full_handler or user, implemented)
+ * detector specific bits (if applicable)(user, implemented)
+ - IPU error pattern
+ * event not found (Bit 20) (user, implemented)
+ - event data missing (Bit 21) (user)
+ - severe problems, buffer under-/overflow (Bit 22) (user)
+ X Ethernet link broken (Bit 24) (Ethernet interface)
+ X SubEvent buffer full (Bit 25) (Ethernet interface)
+ - correct LVL1 trigger handler, detect missing timing triggers etc.
+ (endpoint_full_handler or user)
+
+(2) Status information
+ * buffer fill levels for IPU/LVL1 (as described in registers 0x7100 - 0x710F, 0x7110, 0x7200, 0x7202)
+ (state machine bits in these registers are not mandatory, but recommended)
+ (endpoint_full_handler or user, state machine bits missing)
+ - Common Status Register 0
+ - error / warning flags (Bits 3 - 0) (user)
+ * serious error (Bit 0) (user)
+ * error (Bit 1) (user)
+ - warning (Bit 2) (user)
+ - note (Bit 3) (user)
+ X LVL1 / IPU counter mismatch (Bits 5 - 4) (endpoint)
+ * frontend errors (Bits 7 - 6) (user, implemented)
+ * missing timing trigger (Bit 8) (endpoint_full_handler or user, implemented)
+ - IPU errors (Bit 12 - 9) (user)
+ * event not found (Bit 9) (user, implemented)
+ - partially not found (Bit 10) (user)
+ - severe problem (Bit 11) (user)
+ - last event broken (Bit 12) (user)
+ - Common Status Register 1 :
+ * IPU counter / IPU last event (depending on implementation)
+ (endpoint_full_handler or user)
+ - LVL1 counter / LVL1 last event (depending on implementation)
+ (endpoint_full_handler or user)
+
+(3) Others
+ - Full documentation of all registers available (user)
+ - Full documentation of data format (user)
+
+(4) Optional but Recommended
+ - Status registers with
+ - state machine states (user)
+ - fifo fill level & flags (user)
+ - flags representing status of operation (user)
+
+
+
+Notes:
+ "(endpoint_full_handler or user)" : The user has to set these bits if the endpoint_full_handler is not used
+ "(endpoint)" : The endpoint cares about this bit
+ "(user)" : The user has to set these bits in any case
+ "(Ethernet interface)" : Has to be generated in SubEventBuilder / Ethernet interface
\ No newline at end of file
--- /dev/null
+ADCM_I2C
+========
+
+Offset in ADCM module: 0x8040
+
+Read register: get status of I2C master / readback of values in case of I2C read
+
+Write register: setup / start the I2C master
+
+Access handling: the I2C master implements a TRB busy handling.
+
+Write bit definition
+====================
+
+D[31] I2C_GO 0 => don't do anything on I2C, 1 => start I2C access
+D[30] I2C_ACTION 0 => write byte, 1 => read byte
+D[29:24] I2C_SPEED set to all '1'
+D[23:16] I2C_ADDRESS address of I2C chip
+D[15:8] I2C_CMD command byte for access
+D[7:0] I2C_DATA data to be written
+
+
+Read bit definition
+===================
+
+D[31:24] I2C_DATA result of I2C read operation
+D[23:21] reserved reserved
+D[20:16] I2C_STATUS
+ D[20] ERROR_RSTART generation of repeated START condition failed
+ D[19] ERROR_DATACK no acknowledge for data byte
+ D[18] ERROR_CMDACK no acknowledge for command byte
+ D[17] ERROR_ADDACK no acknowledge for address byte
+ D[16] ERROR_START generation of START condition failed
+D[15:0] reserved reserved
+
+
+
+Argument:
+
+./trb_i2c w 0xaaaa 0xbb 0xcc 0xdd
+
+ TRB CHIP CMD DATA
+
+./trb_i2c r 0xaaaa 0xbb 0xcc
+
+ TRB CHIP CMD
+
+Ablauf:
+
+Beispiel: schreibe Latency-Register mit 0x0a
+
+# latency register (0x04) to 0x0a
+./trbcmd w 0x42 0x8040 0xbf3f0405
+./trbcmd w 0x42 0x8040 0x3f3f0000
+
+ACHTUNG: Beginn des Zugriffs, wenn I2C_GO auf '1' gesetzt wird. Dieses Bit bleibt nach dem
+erfolgten Zugriff auf '1' und muss danach von Hand auf '0' gesetzt werden, ehe ein neuer
+Zugriff gestartet werden kann.
--- /dev/null
+. adcmv3 ..\design\adcmv3.vhd i:\vhdl_pro\comp_adcmv3\design\adcmv3.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.IOBUF.THE_IBUF.THE_FIFO.fifo lattice_ecp2m_fifo_18x1k ..\..\trbnet\lattice\ecp2m\lattice_ecp2m_fifo_18x1k.lpc i:\vhdl_pro\trbnet\lattice\ecp2m\lattice_ecp2m_fifo_18x1k.lpc\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.IOBUF.THE_IBUF.SBUF_INIT.sbuf trb_net_sbuf6 ..\..\trbnet\trb_net_sbuf6.vhd i:\vhdl_pro\trbnet\trb_net_sbuf6.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.regIO trb_net16_regIO ..\..\trbnet\trb_net16_regIO.vhd i:\vhdl_pro\trbnet\trb_net16_regIO.vhd\r
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SERDES serdes_gbe_2 ..\..\trbnet\media_interfaces\ecp2m_sfp\serdes_gbe_2.lpc i:\vhdl_pro\trbnet\media_interfaces\ecp2m_sfp\serdes_gbe_2.lpc\r
+THE_APV_PULSE_STRETCH pulse_stretch ..\design\pulse_stretch.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_stretch.vhd\r
+THE_SLAVE_BUS.THE_ADC1_SNOOPER.THE_RST_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_SLAVE_BUS.THE_ADC0_SNOOPER.THE_RST_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_LSM trb_net16_lsm_sfp ..\..\trbnet\media_interfaces\trb_net16_lsm_sfp.vhd i:\vhdl_pro\trbnet\media_interfaces\trb_net16_lsm_sfp.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.regIO.pattern_gen_inst trb_net_pattern_gen ..\..\trbnet\trb_net_pattern_gen.vhd i:\vhdl_pro\trbnet\trb_net_pattern_gen.vhd\r
+THE_IPU_STAGE.THE_DFIFO fifo_2kx27 ..\design\fifo_2kx27.lpc i:\vhdl_pro\comp_adcmv3\design\fifo_2kx27.lpc\r
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_FPGA_TO_SFP.FIFO_DP_BRAM lattice_ecp2m_fifo_16bit_dualport ..\..\trbnet\lattice\ecp2m\lattice_ecp2m_fifo_16bit_dualport.lpc i:\vhdl_pro\trbnet\lattice\ecp2m\lattice_ecp2m_fifo_16bit_dualport.lpc\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.IOBUF.THE_IBUF.SBUF_REPLY.sbuf trb_net_sbuf6 ..\..\trbnet\trb_net_sbuf6.vhd i:\vhdl_pro\trbnet\trb_net_sbuf6.vhd\r
+THE_IPU_STAGE.THE_LFIFO fifo_1kx18 ..\design\fifo_1kx18.lpc i:\vhdl_pro\comp_adcmv3\design\fifo_1kx18.lpc\r
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_SFP_TO_FPGA.FIFO_DP_BRAM lattice_ecp2m_fifo_16bit_dualport ..\..\trbnet\lattice\ecp2m\lattice_ecp2m_fifo_16bit_dualport.lpc i:\vhdl_pro\trbnet\lattice\ecp2m\lattice_ecp2m_fifo_16bit_dualport.lpc\r
+THE_SLAVE_BUS.THE_PED_MEM.THE_APV_ADC_MAP_MEM apv_adc_map_mem ..\design\apv_adc_map_mem.lpc i:\vhdl_pro\comp_adcmv3\design\apv_adc_map_mem.lpc\r
+THE_SLAVE_BUS.THE_ADC1_SNOOPER.THE_RESET_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_SLAVE_BUS.THE_ADC0_SNOOPER.THE_RESET_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_SLAVE_BUS.THE_THR_MEM.THE_APV_ADC_MAP_MEM apv_adc_map_mem ..\design\apv_adc_map_mem.lpc i:\vhdl_pro\comp_adcmv3\design\apv_adc_map_mem.lpc\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.termbuf trb_net16_term_buf ..\..\trbnet\trb_net16_term_buf.vhd i:\vhdl_pro\trbnet\trb_net16_term_buf.vhd\r
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_RX_K_SYNC signal_sync ..\..\trbnet\basics\signal_sync.vhd i:\vhdl_pro\trbnet\basics\signal_sync.vhd\r
+THE_ADC0_HANDLER.THE_DIN_3 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_ADC0_HANDLER.THE_DIN_4 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_ADC0_HANDLER.THE_DIN_5 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_ADC0_HANDLER.THE_DIN_6 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_ADC0_HANDLER.THE_DIN_7 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_ADC0_HANDLER.THE_DIN_0 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_ADC0_HANDLER.THE_DIN_1 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_ADC0_HANDLER.THE_DIN_2 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_ADC1_HANDLER.THE_DIN_3 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_ADC1_HANDLER.THE_DIN_4 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.DAT_PASSIVE_API.FIFO_TO_APL.fifo lattice_ecp2m_fifo_18x1k ..\..\trbnet\lattice\ecp2m\lattice_ecp2m_fifo_18x1k.lpc i:\vhdl_pro\trbnet\lattice\ecp2m\lattice_ecp2m_fifo_18x1k.lpc\r
+THE_SLAVE_BUS.THE_PED_MEM slv_ped_thr_mem ..\design\slv_ped_thr_mem.vhd i:\vhdl_pro\comp_adcmv3\design\slv_ped_thr_mem.vhd\r
+THE_ADC1_HANDLER.THE_DIN_5 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_ADC1_HANDLER.THE_DIN_6 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_SLAVE_BUS.THE_SPI_MEMORY.THE_BUS_SPI_DPRAM spi_dpram_32_to_8 ..\..\trbnet\lattice\ecp2m\spi_dpram_32_to_8.lpc i:\vhdl_pro\trbnet\lattice\ecp2m\spi_dpram_32_to_8.lpc\r
+THE_ADC1_HANDLER.THE_DIN_7 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_ADC1_HANDLER.THE_DIN_0 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_ADC1_HANDLER.THE_DIN_1 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_ADC1_HANDLER.THE_DIN_2 adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_PED_CORR_STAGE.THE_ALU apv_pc_nc_alu ..\design\apv_pc_nc_alu.vhd i:\vhdl_pro\comp_adcmv3\design\apv_pc_nc_alu.vhd\r
+THE_RAW_BUF_STAGE.THE_APV_LOCKER.THE_APV_DIGITAL apv_digital ..\design\apv_digital.vhd i:\vhdl_pro\comp_adcmv3\design\apv_digital.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.DAT_PASSIVE_API.FIFO_TO_INT.fifo lattice_ecp2m_fifo_18x1k ..\..\trbnet\lattice\ecp2m\lattice_ecp2m_fifo_18x1k.lpc i:\vhdl_pro\trbnet\lattice\ecp2m\lattice_ecp2m_fifo_18x1k.lpc\r
+THE_SLAVE_BUS.THE_THR_MEM slv_ped_thr_mem ..\design\slv_ped_thr_mem.vhd i:\vhdl_pro\comp_adcmv3\design\slv_ped_thr_mem.vhd\r
+THE_RAW_BUF_STAGE.THE_APV_LOCKER.THE_APV_LOCK_SM apv_lock_sm ..\design\apv_lock_sm.vhd i:\vhdl_pro\comp_adcmv3\design\apv_lock_sm.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.THE_LVL1_HANDLER.THE_PULSE_STRETCH pulse_stretch ..\design\pulse_stretch.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_stretch.vhd\r
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_RX_K_DELAY signal_sync ..\..\trbnet\basics\signal_sync.vhd i:\vhdl_pro\trbnet\basics\signal_sync.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.DAT_PASSIVE_API.SBUF_TO_APL.sbuf trb_net_sbuf6 ..\..\trbnet\trb_net_sbuf6.vhd i:\vhdl_pro\trbnet\trb_net_sbuf6.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.IOBUF.INITOBUF trb_net16_obuf_nodata ..\..\trbnet\trb_net16_obuf_nodata.vhd i:\vhdl_pro\trbnet\trb_net16_obuf_nodata.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.IOBUF.THE_IBUF trb_net16_ibuf ..\..\trbnet\trb_net16_ibuf.vhd i:\vhdl_pro\trbnet\trb_net16_ibuf.vhd\r
+THE_SLAVE_BUS.THE_I2C_MASTER i2c_master ..\design\i2c_master.vhd i:\vhdl_pro\comp_adcmv3\design\i2c_master.vhd\r
+THE_ADC_0_SELECT.THE_SEL0_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_ADC_0_SELECT.THE_SEL1_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_ADC_0_SELECT.THE_SEL2_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_ADC_1_SELECT.THE_SEL0_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_ADC_1_SELECT.THE_SEL1_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_ADC_1_SELECT.THE_SEL2_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_SLAVE_BUS.THE_ADC1_SNOOPER.THE_ADC0_SNOOP_MEM adc_snoop_mem ..\design\adc_snoop_mem.lpc i:\vhdl_pro\comp_adcmv3\design\adc_snoop_mem.lpc\r
+THE_SLAVE_BUS.THE_ADC0_SNOOPER.THE_ADC0_SNOOP_MEM adc_snoop_mem ..\design\adc_snoop_mem.lpc i:\vhdl_pro\comp_adcmv3\design\adc_snoop_mem.lpc\r
+THE_SLAVE_BUS.THE_SPI_MASTER spi_master ..\..\trbnet\special\spi_master.vhd i:\vhdl_pro\trbnet\special\spi_master.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER trb_net_priority_arbiter ..\..\trbnet\trb_net_priority_arbiter.vhd i:\vhdl_pro\trbnet\trb_net_priority_arbiter.vhd\r
+THE_APV_TRGCTRL.THE_EDS_BUF eds_buf ..\design\eds_buf.vhd i:\vhdl_pro\comp_adcmv3\design\eds_buf.vhd\r
+THE_SLAVE_BUS.THE_SPI_MEMORY spi_databus_memory ..\..\trbnet\special\spi_databus_memory.vhd i:\vhdl_pro\trbnet\special\spi_databus_memory.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.THE_LVL1_HANDLER.THE_TIMING_TRG_SYNC signal_sync ..\..\trbnet\basics\signal_sync.vhd i:\vhdl_pro\trbnet\basics\signal_sync.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.THE_SBUF trb_net16_sbuf ..\..\trbnet\trb_net16_sbuf.vhd i:\vhdl_pro\trbnet\trb_net16_sbuf.vhd\r
+THE_APV_TRGCTRL.THE_MAX_TRG max_data ..\design\max_data.vhd i:\vhdl_pro\comp_adcmv3\design\max_data.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.MUX_SBUF trb_net16_sbuf ..\..\trbnet\trb_net16_sbuf.vhd i:\vhdl_pro\trbnet\trb_net16_sbuf.vhd\r
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_RX_DATA_DELAY signal_sync ..\..\trbnet\basics\signal_sync.vhd i:\vhdl_pro\trbnet\basics\signal_sync.vhd\r
+THE_RAW_BUF_STAGE.THE_APV_LOCKER.THE_APVON_SYNCER state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_RX_ALLOW_SYNC signal_sync ..\..\trbnet\basics\signal_sync.vhd i:\vhdl_pro\trbnet\basics\signal_sync.vhd\r
+THE_SLAVE_BUS.THE_ADC_LVL_REG slv_register ..\design\slv_register.vhd i:\vhdl_pro\comp_adcmv3\design\slv_register.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.DAT_PASSIVE_API trb_net16_api_base ..\..\trbnet\trb_net16_api_base.vhd i:\vhdl_pro\trbnet\trb_net16_api_base.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.IOBUF.REPLYOBUF trb_net16_obuf_nodata ..\..\trbnet\trb_net16_obuf_nodata.vhd i:\vhdl_pro\trbnet\trb_net16_obuf_nodata.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.THE_LVL1_HANDLER handler_lvl1 ..\..\trbnet\special\handler_lvl1.vhd i:\vhdl_pro\trbnet\special\handler_lvl1.vhd\r
+THE_SLAVE_BUS.THE_ADC1_SNOOPER slv_adc_snoop ..\design\slv_adc_snoop.vhd i:\vhdl_pro\comp_adcmv3\design\slv_adc_snoop.vhd\r
+THE_SLAVE_BUS.THE_ADC0_SNOOPER slv_adc_snoop ..\design\slv_adc_snoop.vhd i:\vhdl_pro\comp_adcmv3\design\slv_adc_snoop.vhd\r
+THE_SLAVE_BUS.THE_BUS_HANDLER trb_net16_regio_bus_handler ..\..\trbnet\trb_net16_regio_bus_handler.vhd i:\vhdl_pro\trbnet\trb_net16_regio_bus_handler.vhd\r
+THE_SLAVE_BUS.THE_TRG_CTRL_REG slv_register ..\design\slv_register.vhd i:\vhdl_pro\comp_adcmv3\design\slv_register.vhd\r
+THE_SLAVE_BUS.THE_PLL_CTRL_REG slv_half_register ..\design\slv_half_register.vhd i:\vhdl_pro\comp_adcmv3\design\slv_half_register.vhd\r
+THE_APV_TRGCTRL.SC_TRG0_STRECH pulse_stretch ..\design\pulse_stretch.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_stretch.vhd\r
+THE_APV_TRGCTRL.SC_TRG1_STRECH pulse_stretch ..\design\pulse_stretch.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_stretch.vhd\r
+THE_ADC_0_SELECT.THE_RESET_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_ADC_1_SELECT.THE_RESET_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_APV_TRGCTRL.SC_TRG2_STRECH pulse_stretch ..\design\pulse_stretch.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_stretch.vhd\r
+THE_APV_TRGCTRL.SC_TRG3_STRECH pulse_stretch ..\design\pulse_stretch.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_stretch.vhd\r
+THE_PED_CORR_STAGE.THE_BUF_TOC buf_toc ..\design\buf_toc.vhd i:\vhdl_pro\comp_adcmv3\design\buf_toc.vhd\r
+THE_RAW_BUF_STAGE.THE_APV_RAW_BUFFER.THE_APV_ON_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_APV_TRGCTRL.THE_RESET_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_RAW_BUF_STAGE.THE_APV_RAW_BUFFER.THE_INPUT_BRAM input_bram ..\design\input_bram.lpc i:\vhdl_pro\comp_adcmv3\design\input_bram.lpc\r
+THE_SLAVE_BUS.THE_ONEWIRE_MEMORY.THE_ONEWIRE_MASTER onewire_master ..\design\onewire_master.vhd i:\vhdl_pro\comp_adcmv3\design\onewire_master.vhd\r
+THE_ADC0_HANDLER.THE_RESET_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_ADC1_HANDLER.THE_RESET_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_SLAVE_BUS.THE_SPI_ADC1_MASTER.THE_SPI_REAL_SLIM spi_real_slim ..\design\spi_real_slim.vhd i:\vhdl_pro\comp_adcmv3\design\spi_real_slim.vhd\r
+THE_SLAVE_BUS.THE_SPI_ADC0_MASTER.THE_SPI_REAL_SLIM spi_real_slim ..\design\spi_real_slim.vhd i:\vhdl_pro\comp_adcmv3\design\spi_real_slim.vhd\r
+THE_RAW_BUF_STAGE.THE_APV_LOCKER apv_locker ..\design\apv_locker.vhd i:\vhdl_pro\comp_adcmv3\design\apv_locker.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.ENC3 trb_net_priority_encoder ..\..\trbnet\trb_net_priority_encoder.vhd i:\vhdl_pro\trbnet\trb_net_priority_encoder.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.ENC2 trb_net_priority_encoder ..\..\trbnet\trb_net_priority_encoder.vhd i:\vhdl_pro\trbnet\trb_net_priority_encoder.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.ARBITER.ENC1 trb_net_priority_encoder ..\..\trbnet\trb_net_priority_encoder.vhd i:\vhdl_pro\trbnet\trb_net_priority_encoder.vhd\r
+THE_SLAVE_BUS.THE_ONEWIRE_MEMORY slv_onewire_memory ..\design\slv_onewire_memory.vhd i:\vhdl_pro\comp_adcmv3\design\slv_onewire_memory.vhd\r
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_SFP_STATUS_SYNC signal_sync ..\..\trbnet\basics\signal_sync.vhd i:\vhdl_pro\trbnet\basics\signal_sync.vhd\r
+THE_RICH_TRB.THE_MEDIA_INTERFACE trb_net16_med_ecp_sfp_gbe ..\..\trbnet\media_interfaces\trb_net16_med_ecp_sfp_gbe.vhd i:\vhdl_pro\trbnet\media_interfaces\trb_net16_med_ecp_sfp_gbe.vhd\r
+THE_ADC0_CROSSOVER.THE_CROSSOVER crossover ..\design\crossover.lpc i:\vhdl_pro\comp_adcmv3\design\crossover.lpc\r
+THE_ADC0_HANDLER.THE_ADC_2_3_CH adc_twochannels ..\design\adc_twochannels.vhd i:\vhdl_pro\comp_adcmv3\design\adc_twochannels.vhd\r
+THE_100M_DLL dll_100m ..\design\dll_100m.lpc i:\vhdl_pro\comp_adcmv3\design\dll_100m.lpc\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.regIO.the_addresses.THE_STAT_RAM ram_16x16_dp ..\..\trbnet\basics\ram_16x16_dp.vhd i:\vhdl_pro\trbnet\basics\ram_16x16_dp.vhd\r
+THE_SLAVE_BUS.THE_GOOD_TEST_REG slv_register ..\design\slv_register.vhd i:\vhdl_pro\comp_adcmv3\design\slv_register.vhd\r
+THE_ADC0_HANDLER.THE_ADC_0_1_CH adc_twochannels ..\design\adc_twochannels.vhd i:\vhdl_pro\comp_adcmv3\design\adc_twochannels.vhd\r
+THE_PED_CORR_STAGE.THE_DECODER_0 decoder_8bit ..\design\decoder_8bit.lpc i:\vhdl_pro\comp_adcmv3\design\decoder_8bit.lpc\r
+THE_PED_CORR_STAGE.THE_DECODER_1 decoder_8bit ..\design\decoder_8bit.lpc i:\vhdl_pro\comp_adcmv3\design\decoder_8bit.lpc\r
+THE_ADC0_HANDLER.THE_ADC_4_5_CH adc_twochannels ..\design\adc_twochannels.vhd i:\vhdl_pro\comp_adcmv3\design\adc_twochannels.vhd\r
+THE_ADC0_HANDLER.THE_ADC_6_7_CH adc_twochannels ..\design\adc_twochannels.vhd i:\vhdl_pro\comp_adcmv3\design\adc_twochannels.vhd\r
+THE_ADC1_HANDLER.THE_ADC_2_3_CH adc_twochannels ..\design\adc_twochannels.vhd i:\vhdl_pro\comp_adcmv3\design\adc_twochannels.vhd\r
+THE_ADC1_HANDLER.THE_ADC_0_1_CH adc_twochannels ..\design\adc_twochannels.vhd i:\vhdl_pro\comp_adcmv3\design\adc_twochannels.vhd\r
+THE_ADC1_HANDLER.THE_ADC_4_5_CH adc_twochannels ..\design\adc_twochannels.vhd i:\vhdl_pro\comp_adcmv3\design\adc_twochannels.vhd\r
+THE_ADC1_HANDLER.THE_ADC_6_7_CH adc_twochannels ..\design\adc_twochannels.vhd i:\vhdl_pro\comp_adcmv3\design\adc_twochannels.vhd\r
+THE_ADC1_CROSSOVER.THE_CROSSOVER crossover ..\design\crossover.lpc i:\vhdl_pro\comp_adcmv3\design\crossover.lpc\r
+THE_RAW_BUF_STAGE.THE_RESET_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_40M_PLL pll_40m ..\design\pll_40m.lpc i:\vhdl_pro\comp_adcmv3\design\pll_40m.lpc\r
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_FPGA_TO_SFP trb_net_fifo_16bit_bram_dualport ..\..\trbnet\lattice\ecp2m\trb_net_fifo_16bit_bram_dualport.vhd i:\vhdl_pro\trbnet\lattice\ecp2m\trb_net_fifo_16bit_bram_dualport.vhd\r
+THE_RICH_TRB.THE_MEDIA_INTERFACE.THE_FIFO_SFP_TO_FPGA trb_net_fifo_16bit_bram_dualport ..\..\trbnet\lattice\ecp2m\trb_net_fifo_16bit_bram_dualport.vhd i:\vhdl_pro\trbnet\lattice\ecp2m\trb_net_fifo_16bit_bram_dualport.vhd\r
+THE_SLAVE_BUS.THE_ONEWIRE_MEMORY.THE_SLV_ONEWIRE_DPRAM slv_onewire_dpram ..\design\slv_onewire_dpram.lpc i:\vhdl_pro\comp_adcmv3\design\slv_onewire_dpram.lpc\r
+THE_SLAVE_BUS.THE_I2C_MASTER.THE_I2C_SLIM.THE_I2C_SENDB i2c_sendb ..\design\i2c_sendb.vhd i:\vhdl_pro\comp_adcmv3\design\i2c_sendb.vhd\r
+THE_IPU_STAGE.THE_ADC_APV_MAP_MEM adc_apv_map_mem ..\design\adc_apv_map_mem.lpc i:\vhdl_pro\comp_adcmv3\design\adc_apv_map_mem.lpc\r
+THE_ADC0_HANDLER.THE_ADC_ADCLK_IN adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_ADC1_HANDLER.THE_ADC_ADCLK_IN adc_ch_in ..\design\adc_ch_in.lpc i:\vhdl_pro\comp_adcmv3\design\adc_ch_in.lpc\r
+THE_RICH_TRB rich_trb ..\design\rich_trb.vhd i:\vhdl_pro\comp_adcmv3\design\rich_trb.vhd\r
+THE_SLAVE_BUS.THE_I2C_MASTER.THE_I2C_SLIM.THE_I2C_GSTART i2c_gstart ..\design\i2c_gstart.vhd i:\vhdl_pro\comp_adcmv3\design\i2c_gstart.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.DAT_PASSIVE_API.SBUF trb_net16_sbuf ..\..\trbnet\trb_net16_sbuf.vhd i:\vhdl_pro\trbnet\trb_net16_sbuf.vhd\r
+THE_RAW_BUF_STAGE.THE_APV_RAW_BUFFER.THE_TICKMARK_SYNCER pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_SYNC_PLL sync_pll_40m ..\design\sync_pll_40m.lpc i:\vhdl_pro\comp_adcmv3\design\sync_pll_40m.lpc\r
+THE_SLAVE_BUS.THE_SPI_ADC1_MASTER spi_adc_master ..\design\spi_adc_master.vhd i:\vhdl_pro\comp_adcmv3\design\spi_adc_master.vhd\r
+THE_SLAVE_BUS.THE_SPI_ADC0_MASTER spi_adc_master ..\design\spi_adc_master.vhd i:\vhdl_pro\comp_adcmv3\design\spi_adc_master.vhd\r
+THE_SLAVE_BUS.THE_ONEWIRE_MEMORY.THE_ONEWIRE_SPARE_ONE onewire_spare_one ..\design\onewire_spare_one.lpc i:\vhdl_pro\comp_adcmv3\design\onewire_spare_one.lpc\r
+THE_SLAVE_BUS.THE_FIFO_STATUS_BANK slv_status_bank ..\design\slv_status_bank.vhd i:\vhdl_pro\comp_adcmv3\design\slv_status_bank.vhd\r
+THE_RAW_BUF_STAGE.THE_APV_RAW_BUFFER.THE_ADC_LAST_SYNCER pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.THE_TIME_TRG_0_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.THE_TIME_TRG_1_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.THE_TIME_TRG_2_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER.THE_TIME_TRG_3_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_SLAVE_BUS slave_bus ..\design\slave_bus.vhd i:\vhdl_pro\comp_adcmv3\design\slave_bus.vhd\r
+THE_PED_CORR_STAGE.THE_REF_ROW_SEL ref_row_sel ..\design\ref_row_sel.vhd i:\vhdl_pro\comp_adcmv3\design\ref_row_sel.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT trb_net16_endpoint_hades_full ..\..\trbnet\trb_net16_endpoint_hades_full.vhd i:\vhdl_pro\trbnet\trb_net16_endpoint_hades_full.vhd\r
+THE_RAW_BUF_STAGE.THE_APV_RAW_BUFFER.THE_APV_LOCKED_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.THE_SBUF.sbuf trb_net_sbuf6 ..\..\trbnet\trb_net_sbuf6.vhd i:\vhdl_pro\trbnet\trb_net_sbuf6.vhd\r
+THE_SLAVE_BUS.THE_SLV_REGISTER_BANK.THE_APV_ADC_MAP_MEM apv_adc_map_mem ..\design\apv_adc_map_mem.lpc i:\vhdl_pro\comp_adcmv3\design\apv_adc_map_mem.lpc\r
+THE_IPU_STAGE ipu_fifo_stage ..\design\ipu_fifo_stage.vhd i:\vhdl_pro\comp_adcmv3\design\ipu_fifo_stage.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.regIO.board_rom rom_16x8 ..\..\trbnet\basics\rom_16x8.vhd i:\vhdl_pro\trbnet\basics\rom_16x8.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.IOBUF.THE_IBUF.THE_CRC trb_net_CRC ..\..\trbnet\trb_net_CRC.vhd i:\vhdl_pro\trbnet\trb_net_CRC.vhd\r
+THE_APV_TRGCTRL.THE_APV_SYNC_HANDLER.THE_APVTRGDONE_SYNC pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_RAW_BUF_STAGE.THE_APV_RAW_BUFFER.THE_APV_ADCOK_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX.MUX_SBUF.sbuf trb_net_sbuf6 ..\..\trbnet\trb_net_sbuf6.vhd i:\vhdl_pro\trbnet\trb_net_sbuf6.vhd\r
+THE_SLAVE_BUS.THE_ONEWIRE_MEMORY.THE_ADC_ONEWIRE_MAP_MEM adc_onewire_map_mem ..\design\adc_onewire_map_mem.lpc i:\vhdl_pro\comp_adcmv3\design\adc_onewire_map_mem.lpc\r
+THE_RAW_BUF_STAGE.THE_APV_RAW_BUFFER apv_raw_buffer ..\design\apv_raw_buffer.vhd i:\vhdl_pro\comp_adcmv3\design\apv_raw_buffer.vhd\r
+THE_PED_CORR_STAGE.THE_FRMCTR_CHECK frmctr_check ..\design\frmctr_check.vhd i:\vhdl_pro\comp_adcmv3\design\frmctr_check.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.the_ipudata_apl trb_net16_ipudata ..\..\trbnet\trb_net16_ipudata.vhd i:\vhdl_pro\trbnet\trb_net16_ipudata.vhd\r
+THE_ADC_0_SELECT adc_channel_select ..\design\adc_channel_select.vhd i:\vhdl_pro\comp_adcmv3\design\adc_channel_select.vhd\r
+THE_ADC_1_SELECT adc_channel_select ..\design\adc_channel_select.vhd i:\vhdl_pro\comp_adcmv3\design\adc_channel_select.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.IOBUF.THE_IBUF.SBUF_INIT trb_net16_sbuf ..\..\trbnet\trb_net16_sbuf.vhd i:\vhdl_pro\trbnet\trb_net16_sbuf.vhd\r
+THE_SLAVE_BUS.THE_IPU_HANDLER_STATUS slv_status ..\design\slv_status.vhd i:\vhdl_pro\comp_adcmv3\design\slv_status.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.the_trigger_apl trb_net16_trigger ..\..\trbnet\trb_net16_trigger.vhd i:\vhdl_pro\trbnet\trb_net16_trigger.vhd\r
+THE_APV_TRGCTRL.THE_APV_SYNC_HANDLER apv_sync_handler ..\design\apv_sync_handler.vhd i:\vhdl_pro\comp_adcmv3\design\apv_sync_handler.vhd\r
+THE_SLAVE_BUS.THE_SLV_REGISTER_BANK slv_register_bank ..\design\slv_register_bank.vhd i:\vhdl_pro\comp_adcmv3\design\slv_register_bank.vhd\r
+THE_ADC0_HANDLER adc_data_handler ..\design\adc_data_handler.vhd i:\vhdl_pro\comp_adcmv3\design\adc_data_handler.vhd\r
+THE_ADC1_HANDLER adc_data_handler ..\design\adc_data_handler.vhd i:\vhdl_pro\comp_adcmv3\design\adc_data_handler.vhd\r
+THE_APV_TRGCTRL.THE_REAL_TRG_HANDLER real_trg_handler ..\design\real_trg_handler.vhd i:\vhdl_pro\comp_adcmv3\design\real_trg_handler.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.IOBUF.THE_IBUF.THE_FIFO trb_net16_fifo ..\..\trbnet\lattice\ecp2m\trb_net16_fifo_arch.vhd i:\vhdl_pro\trbnet\lattice\ecp2m\trb_net16_fifo_arch.vhd\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_0.THE_APVTRGSTART_SYNC pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_1.THE_APVTRGSTART_SYNC pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_2.THE_APVTRGSTART_SYNC pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_3.THE_APVTRGSTART_SYNC pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_0.THE_APVTRGDONE_SYNC pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_1.THE_APVTRGDONE_SYNC pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_APV_TRGCTRL apv_trgctrl ..\design\apv_trgctrl.vhd i:\vhdl_pro\comp_adcmv3\design\apv_trgctrl.vhd\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_2.THE_APVTRGDONE_SYNC pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_3.THE_APVTRGDONE_SYNC pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_RAW_BUF_STAGE.THE_APV_RAW_BUFFER.THE_FRAME_STATUS_MEM frame_status_mem ..\design\frame_status_mem.lpc i:\vhdl_pro\comp_adcmv3\design\frame_status_mem.lpc\r
+THE_RAW_BUF_STAGE.THE_APV_RAW_BUFFER.THE_ADC_START_SYNCER pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_SLAVE_BUS.THE_PED_MEM.THE_PED_MEM ped_thr_true ..\design\ped_thr_true.lpc i:\vhdl_pro\comp_adcmv3\design\ped_thr_true.lpc\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_0.THE_APVTRGSENT_SYNC pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_1.THE_APVTRGSENT_SYNC pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_0 apv_trg_handler ..\design\apv_trg_handler.vhd i:\vhdl_pro\comp_adcmv3\design\apv_trg_handler.vhd\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_1 apv_trg_handler ..\design\apv_trg_handler.vhd i:\vhdl_pro\comp_adcmv3\design\apv_trg_handler.vhd\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_2 apv_trg_handler ..\design\apv_trg_handler.vhd i:\vhdl_pro\comp_adcmv3\design\apv_trg_handler.vhd\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_2.THE_APVTRGSENT_SYNC pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_3 apv_trg_handler ..\design\apv_trg_handler.vhd i:\vhdl_pro\comp_adcmv3\design\apv_trg_handler.vhd\r
+THE_APV_TRGCTRL.THE_APV_TRG_HANDLER_3.THE_APVTRGSENT_SYNC pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_APV_TRGCTRL.THE_APV_SYNC_HANDLER.THE_APVTRGSTART_SYNC pulse_sync ..\design\pulse_sync.vhd i:\vhdl_pro\comp_adcmv3\design\pulse_sync.vhd\r
+THE_SLAVE_BUS.THE_THR_MEM.THE_PED_MEM ped_thr_true ..\design\ped_thr_true.lpc i:\vhdl_pro\comp_adcmv3\design\ped_thr_true.lpc\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.onewire_interface trb_net_onewire ..\..\trbnet\trb_net_onewire.vhd i:\vhdl_pro\trbnet\trb_net_onewire.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.IOBUF.THE_IBUF.SBUF_REPLY trb_net16_sbuf ..\..\trbnet\trb_net16_sbuf.vhd i:\vhdl_pro\trbnet\trb_net16_sbuf.vhd\r
+THE_RAW_BUF_STAGE raw_buf_stage ..\design\raw_buf_stage.vhd i:\vhdl_pro\comp_adcmv3\design\raw_buf_stage.vhd\r
+THE_REBOOT_HANDLER reboot_handler ..\design\reboot_handler.vhd i:\vhdl_pro\comp_adcmv3\design\reboot_handler.vhd\r
+THE_SLAVE_BUS.THE_LVL1_RELEASE_STATUS slv_status ..\design\slv_status.vhd i:\vhdl_pro\comp_adcmv3\design\slv_status.vhd\r
+THE_ADC0_CROSSOVER adc_crossover ..\design\adc_crossover.vhd i:\vhdl_pro\comp_adcmv3\design\adc_crossover.vhd\r
+THE_ADC1_CROSSOVER adc_crossover ..\design\adc_crossover.vhd i:\vhdl_pro\comp_adcmv3\design\adc_crossover.vhd\r
+THE_PED_CORR_STAGE ped_corr_ctrl ..\design\ped_corr_ctrl.vhd i:\vhdl_pro\comp_adcmv3\design\ped_corr_ctrl.vhd\r
+THE_RESET_HANDLER reset_handler ..\design\reset_handler.vhd i:\vhdl_pro\comp_adcmv3\design\reset_handler.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.IOBUF trb_net16_iobuf ..\..\trbnet\trb_net16_iobuf.vhd i:\vhdl_pro\trbnet\trb_net16_iobuf.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.DAT_PASSIVE_API.SBUF.sbuf trb_net_sbuf6 ..\..\trbnet\trb_net_sbuf6.vhd i:\vhdl_pro\trbnet\trb_net_sbuf6.vhd\r
+THE_SLAVE_BUS.THE_I2C_MASTER.THE_I2C_SLIM i2c_slim ..\design\i2c_slim.vhd i:\vhdl_pro\comp_adcmv3\design\i2c_slim.vhd\r
+THE_ADC0_CROSSOVER.THE_RESET_STATE_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_ADC1_CROSSOVER.THE_RESET_STATE_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.MPLEX trb_net16_io_multiplexer ..\..\trbnet\trb_net16_io_multiplexer.vhd i:\vhdl_pro\trbnet\trb_net16_io_multiplexer.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.regIO.the_addresses trb_net16_addresses ..\..\trbnet\trb_net16_addresses.vhd i:\vhdl_pro\trbnet\trb_net16_addresses.vhd\r
+THE_SLAVE_BUS.THE_ADC1_SNOOPER.THE_CE_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_SLAVE_BUS.THE_ADC0_SNOOPER.THE_CE_SYNC state_sync ..\design\state_sync.vhd i:\vhdl_pro\comp_adcmv3\design\state_sync.vhd\r
+THE_APV_TRGCTRL.THE_EDS_BUF.THE_EDS_BUFFER eds_buffer_dpram ..\design\eds_buffer_dpram.lpc i:\vhdl_pro\comp_adcmv3\design\eds_buffer_dpram.lpc\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.DAT_PASSIVE_API.FIFO_TO_APL trb_net16_fifo ..\..\trbnet\lattice\ecp2m\trb_net16_fifo_arch.vhd i:\vhdl_pro\trbnet\lattice\ecp2m\trb_net16_fifo_arch.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.DAT_PASSIVE_API.FIFO_TO_INT trb_net16_fifo ..\..\trbnet\lattice\ecp2m\trb_net16_fifo_arch.vhd i:\vhdl_pro\trbnet\lattice\ecp2m\trb_net16_fifo_arch.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.DAT_PASSIVE_API.SBUF_TO_APL trb_net16_sbuf ..\..\trbnet\trb_net16_sbuf.vhd i:\vhdl_pro\trbnet\trb_net16_sbuf.vhd\r
+THE_RICH_TRB.THE_UNIFIED_ENDPOINT.DAT_PASSIVE_API.SBUF_TO_APL2 trb_net_sbuf ..\..\trbnet\trb_net_sbuf.vhd i:\vhdl_pro\trbnet\trb_net_sbuf.vhd\r
+THE_SLAVE_BUS.THE_SPI_MASTER.THE_SPI_SLIM spi_slim ..\..\trbnet\special\spi_slim.vhd i:\vhdl_pro\trbnet\special\spi_slim.vhd\r
+[VHDL_Package] ../../trbnet/trb_net_components.vhd ..\..\trbnet\trb_net_components.vhd i:\vhdl_pro\trbnet\trb_net_components.vhd\r
+[VHDL_Package] ../version.vhd ..\version.vhd i:\vhdl_pro\comp_adcmv3\version.vhd\r
+[VHDL_Package] ../design/adcmv3_components.vhd ..\design\adcmv3_components.vhd i:\vhdl_pro\comp_adcmv3\design\adcmv3_components.vhd\r
+[VHDL_Package] ../../trbnet/trb_net_std.vhd ..\..\trbnet\trb_net_std.vhd i:\vhdl_pro\trbnet\trb_net_std.vhd\r
+[VHDL_Package] ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ..\..\trbnet\lattice\ecp2m\lattice_ecp2m_fifo.vhd i:\vhdl_pro\trbnet\lattice\ecp2m\lattice_ecp2m_fifo.vhd\r
--- /dev/null
+\r
+[Device]\r
+Family = ep5m00;\r
+PartNumber = LFE2M100E-6F900C;\r
+Package = FPBGA900;\r
+PartType = LFE2M100E;\r
+Speed = -6;\r
+Operating_condition = COM;\r
+Status = Production;\r
+\r
+[Revision]\r
+Parent = ep5m00.lci;\r
+DATE = 2002;\r
+TIME = 0:00:00;\r
+Source_Format = Pure_VHDL;\r
+Synthesis = Synplify;\r
+\r
+[Ignore Assignments]\r
+\r
+[Clear Assignments]\r
+\r
+[Backannotate Assignments]\r
+\r
+[Global Constraints]\r
+\r
+[Location Assignments]\r
+layer = OFF;\r
+\r
+[Group Assignments]\r
+layer = OFF;\r
+\r
+[Resource Reservations]\r
+layer = OFF;\r
+\r
+[Fitter Report Format]\r
+\r
+[Power]\r
+\r
+[Source Constraint Option]\r
+\r
+[Fast Bypass]\r
+\r
+[OSM Bypass]\r
+\r
+[Input Registers]\r
+\r
+[Netlist/Delay Format]\r
+\r
+[IO Types]\r
+layer = OFF;\r
+\r
+[Pullup]\r
+\r
+[Slewrate]\r
+\r
+[Region]\r
+\r
+[Timing Constraints]\r
+\r
+[HSI Attributes]\r
+\r
+[Input Delay]\r
+\r
+[TRACE MAP]\r
+Logic_Delay = 0;\r
+\r
+[global constraints list]\r
+\r
+[Global Constraints Process Update]\r
+\r
+[LOCATION ASSIGNMENTS LIST]\r
+\r
+[RESOURCE RESERVATIONS LIST]\r
+\r
+[Pin attributes list]\r
+\r
+[Timing Analyzer]\r
+\r
+[PLL Assignments]\r
+\r
+[Explorer Results]\r
+\r
+[Explorer User Settings]\r
+\r
+[Explorer Run Settings]\r
--- /dev/null
+\r
+[Device]\r
+Family = ep5m00;\r
+PartNumber = LFE2M100E-6F900C;\r
+Package = FPBGA900;\r
+PartType = LFE2M100E;\r
+Speed = -6;\r
+Operating_condition = COM;\r
+Status = Production;\r
+\r
+[Revision]\r
+Parent = ep5m00.lci;\r
+DATE = 2002;\r
+TIME = 0:00:00;\r
+Source_Format = Pure_VHDL;\r
+Synthesis = Synplify;\r
+\r
+[Ignore Assignments]\r
+\r
+[Clear Assignments]\r
+\r
+[Backannotate Assignments]\r
+\r
+[Global Constraints]\r
+\r
+[Location Assignments]\r
+layer = OFF;\r
+\r
+[Group Assignments]\r
+layer = OFF;\r
+\r
+[Resource Reservations]\r
+layer = OFF;\r
+\r
+[Fitter Report Format]\r
+\r
+[Power]\r
+\r
+[Source Constraint Option]\r
+\r
+[Fast Bypass]\r
+\r
+[OSM Bypass]\r
+\r
+[Input Registers]\r
+\r
+[Netlist/Delay Format]\r
+\r
+[IO Types]\r
+layer = OFF;\r
+\r
+[Pullup]\r
+\r
+[Slewrate]\r
+\r
+[Region]\r
+\r
+[Timing Constraints]\r
+\r
+[HSI Attributes]\r
+\r
+[Input Delay]\r
+\r
+[TRACE MAP]\r
+Logic_Delay = 0;\r
+\r
+[global constraints list]\r
+\r
+[Global Constraints Process Update]\r
+\r
+[LOCATION ASSIGNMENTS LIST]\r
+\r
+[RESOURCE RESERVATIONS LIST]\r
+\r
+[Pin attributes list]\r
+\r
+[Timing Analyzer]\r
+\r
+[PLL Assignments]\r
+\r
+[Explorer Results]\r
+\r
+[Explorer User Settings]\r
+\r
+[Explorer Run Settings]\r
--- /dev/null
+COMMERCIAL;\r
+BLOCK RESETPATHS;\r
+BLOCK ASYNCPATHS;\r
--- /dev/null
+-v 1\r
+-gt\r
+-mapchkpnt 0\r
--- /dev/null
+<SYNPROJ_Revision_Control>
+<RevisionControl_Info/>
+</SYNPROJ_Revision_Control>
--- /dev/null
+STYFILENAME=adcmv3.sty\r
+PROJECT=adcmv3\r
+ENTRY=Pure VHDL\r
+WORKING_PATH=i:/vhdl_pro/comp_adcmv3/lever\r
+MODULE=adcmv3\r
+TOP_FILE=../design/adcmv3.vhd\r
+EDF_FILE_LIST=../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/test_media.vhd ../design/sbuf.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd\r
+VHDL_FILE_LIST=../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/test_media.vhd ../design/sbuf.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd\r
+VERILOG_FILE_LIST=../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/test_media.vhd ../design/sbuf.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd\r
+DEVICEPART=LFE2M100E-6F900C\r
--- /dev/null
+[STRATEGY-LIST]\r
+Normal=True, 1276853141\r
+[synthesis-type]\r
+tool=Synplify\r
--- /dev/null
+JDF B\r
+// Created by Version 8.001 \r
+PROJECT adcmv3\r
+DESIGN adcmv3 Normal\r
+DEVKIT LFE2M100E-6F900C\r
+ENTRY Pure VHDL\r
+MODULE ..\..\trbnet\trb_net_components.vhd\r
+MODSTYLE ../../trbnet/trb_net_components.vhd Normal\r
+MODULE ..\version.vhd\r
+MODSTYLE ../version.vhd Normal\r
+MODULE ..\design\adcmv3_components.vhd\r
+MODSTYLE ../design/adcmv3_components.vhd Normal\r
+MODULE ..\..\trbnet\trb_net_std.vhd\r
+MODSTYLE ../../trbnet/trb_net_std.vhd Normal\r
+MODULE ..\..\trbnet\lattice\ecp2m\lattice_ecp2m_fifo.vhd\r
+MODSTYLE ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd Normal\r
+MODULE ..\design\dbg_reg.vhd\r
+MODSTYLE dbg_reg Normal\r
+MODULE ..\design\pulse_sync.vhd\r
+MODSTYLE pulse_sync Normal\r
+STIMULUS pulse_sync ..\sim\tb_pulse_sync.vhd\r
+MODULE ..\design\apv_sync_handler.vhd\r
+MODSTYLE apv_sync_handler Normal\r
+MODULE ..\design\apv_trg_handler.vhd\r
+MODSTYLE apv_trg_handler Normal\r
+MODULE ..\design\eds_buffer_dpram.lpc\r
+MODSTYLE eds_buffer_dpram Normal\r
+MODULE ..\design\eds_buf.vhd\r
+MODSTYLE eds_buf Normal\r
+MODULE ..\design\max_data.vhd\r
+MODSTYLE max_data Normal\r
+STIMULUS max_data ..\sim\tb_max_data.vhd\r
+MODULE ..\design\state_sync.vhd\r
+MODSTYLE state_sync Normal\r
+MODULE ..\design\real_trg_handler.vhd\r
+MODSTYLE real_trg_handler Normal\r
+STIMULUS real_trg_handler ..\sim\tb_real_trg_handler.vhd\r
+MODULE ..\design\pulse_stretch.vhd\r
+MODSTYLE pulse_stretch Normal\r
+STIMULUS pulse_stretch ..\sim\tb_pulse_stretch.vhd\r
+MODULE ..\design\apv_trgctrl.vhd\r
+MODSTYLE apv_trgctrl Normal\r
+STIMULUS apv_trgctrl ..\sim\tb_apv_trgctrl.vhd\r
+MODULE ..\design\adc_channel_select.vhd\r
+MODSTYLE adc_channel_select Normal\r
+MODULE ..\design\crossover.lpc\r
+MODSTYLE crossover Normal\r
+STIMULUS crossover ..\sim\tb_crossover.vhd\r
+MODULE ..\design\adc_crossover.vhd\r
+MODSTYLE adc_crossover Normal\r
+STIMULUS adc_crossover ..\sim\tb_adc_crossover.vhd\r
+MODULE ..\design\adc_twochannels.vhd\r
+MODSTYLE adc_twochannels Normal\r
+MODULE ..\design\adc_ch_in.lpc\r
+MODSTYLE adc_ch_in Normal\r
+MODULE ..\design\adc_data_handler.vhd\r
+MODSTYLE adc_data_handler Normal\r
+STIMULUS adc_data_handler ..\sim\tb_adc_handler.vhd\r
+MODULE ..\design\frame_status_mem.lpc\r
+MODSTYLE frame_status_mem Normal\r
+MODULE ..\design\input_bram.lpc\r
+MODSTYLE input_bram Normal\r
+MODULE ..\design\apv_raw_buffer.vhd\r
+MODSTYLE apv_raw_buffer Normal\r
+MODULE ..\design\apv_lock_sm.vhd\r
+MODSTYLE apv_lock_sm Normal\r
+MODULE ..\design\apv_digital.vhd\r
+MODSTYLE apv_digital Normal\r
+MODULE ..\design\apv_locker.vhd\r
+MODSTYLE apv_locker Normal\r
+STIMULUS apv_locker ..\sim\tb_apv_locker.vhd\r
+MODULE ..\design\raw_buf_stage.vhd\r
+MODSTYLE raw_buf_stage Normal\r
+MODULE ..\design\decoder_8bit.lpc\r
+MODSTYLE decoder_8bit Normal\r
+MODULE ..\design\apv_pc_nc_alu.vhd\r
+MODSTYLE apv_pc_nc_alu Normal\r
+STIMULUS apv_pc_nc_alu ..\sim\tb_apv_pc_nc_alu.vhd\r
+MODULE ..\design\buf_toc.vhd\r
+MODSTYLE buf_toc Normal\r
+MODULE ..\design\ref_row_sel.vhd\r
+MODSTYLE ref_row_sel Normal\r
+MODULE ..\design\frmctr_check.vhd\r
+MODSTYLE frmctr_check Normal\r
+MODULE ..\design\ped_corr_ctrl.vhd\r
+MODSTYLE ped_corr_ctrl Normal\r
+STIMULUS ped_corr_ctrl ..\sim\tb_ped_corr_ctrl.vhd\r
+MODULE ..\design\adc_apv_map_mem.lpc\r
+MODSTYLE adc_apv_map_mem Normal\r
+MODULE ..\design\fifo_1kx18.lpc\r
+MODSTYLE fifo_1kx18 Normal\r
+MODULE ..\design\fifo_2kx27.lpc\r
+MODSTYLE fifo_2kx27 Normal\r
+MODULE ..\design\ipu_fifo_stage.vhd\r
+MODSTYLE ipu_fifo_stage Normal\r
+STIMULUS ipu_fifo_stage ..\sim\tb_ipu_fifo_stage.vhd\r
+MODULE ..\design\slv_register.vhd\r
+MODSTYLE slv_register Normal\r
+MODULE ..\design\adc_snoop_mem.lpc\r
+MODSTYLE adc_snoop_mem Normal\r
+MODULE ..\design\slv_adc_snoop.vhd\r
+MODSTYLE slv_adc_snoop Normal\r
+STIMULUS slv_adc_snoop ..\sim\tb_slv_adc_snoop.vhd\r
+MODULE ..\design\slv_half_register.vhd\r
+MODSTYLE slv_half_register Normal\r
+MODULE ..\design\slv_status.vhd\r
+MODSTYLE slv_status Normal\r
+MODULE ..\design\slv_status_bank.vhd\r
+MODSTYLE slv_status_bank Normal\r
+MODULE ..\design\apv_adc_map_mem.lpc\r
+MODSTYLE apv_adc_map_mem Normal\r
+MODULE ..\design\slv_register_bank.vhd\r
+MODSTYLE slv_register_bank Normal\r
+STIMULUS slv_register_bank ..\sim\tb_slv_register_bank.vhd\r
+MODULE ..\design\spi_real_slim.vhd\r
+MODSTYLE spi_real_slim Normal\r
+STIMULUS spi_real_slim ..\sim\tb_spi_real_slim.vhd\r
+MODULE ..\design\spi_adc_master.vhd\r
+MODSTYLE spi_adc_master Normal\r
+MODULE ..\..\trbnet\lattice\ecp2m\spi_dpram_32_to_8.lpc\r
+MODSTYLE spi_dpram_32_to_8 Normal\r
+MODULE ..\..\trbnet\special\spi_databus_memory.vhd\r
+MODSTYLE spi_databus_memory Normal\r
+MODULE ..\..\trbnet\special\spi_slim.vhd\r
+MODSTYLE spi_slim Normal\r
+MODULE ..\..\trbnet\special\spi_master.vhd\r
+MODSTYLE spi_master Normal\r
+STIMULUS spi_master ..\sim\tb_spi_master.vhd\r
+MODULE ..\design\slv_onewire_dpram.lpc\r
+MODSTYLE slv_onewire_dpram Normal\r
+MODULE ..\design\onewire_master.vhd\r
+MODSTYLE onewire_master Normal\r
+STIMULUS onewire_master ..\sim\tb_onewire_master.vhd\r
+MODULE ..\design\onewire_spare_one.lpc\r
+MODSTYLE onewire_spare_one Normal\r
+MODULE ..\design\adc_onewire_map_mem.lpc\r
+MODSTYLE adc_onewire_map_mem Normal\r
+MODULE ..\design\slv_onewire_memory.vhd\r
+MODSTYLE slv_onewire_memory Normal\r
+STIMULUS slv_onewire_memory ..\sim\tb_slv_onewire_memory.vhd\r
+MODULE ..\design\i2c_gstart.vhd\r
+MODSTYLE i2c_gstart Normal\r
+MODULE ..\design\i2c_sendb.vhd\r
+MODSTYLE i2c_sendb Normal\r
+MODULE ..\design\i2c_slim.vhd\r
+MODSTYLE i2c_slim Normal\r
+MODULE ..\design\i2c_master.vhd\r
+MODSTYLE i2c_master Normal\r
+MODULE ..\design\ped_thr_true.lpc\r
+MODSTYLE ped_thr_true Normal\r
+MODULE ..\design\slv_ped_thr_mem.vhd\r
+MODSTYLE slv_ped_thr_mem Normal\r
+STIMULUS slv_ped_thr_mem ..\sim\tb_slv_ped_thr_mem.vhd\r
+MODULE ..\..\trbnet\trb_net16_regio_bus_handler.vhd\r
+MODSTYLE trb_net16_regio_bus_handler Normal\r
+MODULE ..\design\slave_bus.vhd\r
+MODSTYLE slave_bus Normal\r
+MODULE ..\..\trbnet\basics\signal_sync.vhd\r
+MODSTYLE signal_sync Normal\r
+MODULE ..\..\trbnet\special\handler_lvl1.vhd\r
+MODSTYLE handler_lvl1 Normal\r
+MODULE ..\..\trbnet\trb_net_sbuf.vhd\r
+MODSTYLE trb_net_sbuf Normal\r
+MODULE ..\..\trbnet\trb_net_sbuf5.vhd\r
+MODSTYLE trb_net_sbuf5 Normal\r
+MODULE ..\..\trbnet\trb_net_sbuf6.vhd\r
+MODSTYLE trb_net_sbuf6 Normal\r
+MODULE ..\..\trbnet\trb_net16_sbuf.vhd\r
+MODSTYLE trb_net16_sbuf Normal\r
+MODULE ..\..\trbnet\trb_net_priority_encoder.vhd\r
+MODSTYLE trb_net_priority_encoder Normal\r
+MODULE ..\..\trbnet\trb_net_priority_arbiter.vhd\r
+MODSTYLE trb_net_priority_arbiter Normal\r
+MODULE ..\..\trbnet\trb_net16_io_multiplexer.vhd\r
+MODSTYLE trb_net16_io_multiplexer Normal\r
+MODULE ..\..\trbnet\trb_net_onewire.vhd\r
+MODSTYLE trb_net_onewire Normal\r
+MODULE ..\..\trbnet\basics\rom_16x8.vhd\r
+MODSTYLE rom_16x8 Normal\r
+MODULE ..\..\trbnet\basics\ram_16x16_dp.vhd\r
+MODSTYLE ram_16x16_dp Normal\r
+MODULE ..\..\trbnet\trb_net16_addresses.vhd\r
+MODSTYLE trb_net16_addresses Normal\r
+MODULE ..\..\trbnet\trb_net_pattern_gen.vhd\r
+MODSTYLE trb_net_pattern_gen Normal\r
+MODULE ..\..\trbnet\trb_net16_regIO.vhd\r
+MODSTYLE trb_net16_regio Normal\r
+MODULE ..\..\trbnet\lattice\ecp2m\lattice_ecp2m_fifo_18x1k.lpc\r
+MODSTYLE lattice_ecp2m_fifo_18x1k Normal\r
+MODULE ..\..\trbnet\lattice\ecp2m\trb_net16_fifo_arch.vhd\r
+MODSTYLE trb_net16_fifo Normal\r
+MODULE ..\..\trbnet\trb_net16_api_base.vhd\r
+MODSTYLE trb_net16_api_base Normal\r
+MODULE ..\..\trbnet\trb_net_CRC.vhd\r
+MODSTYLE trb_net_crc Normal\r
+MODULE ..\..\trbnet\trb_net16_obuf.vhd\r
+MODSTYLE trb_net16_obuf Normal\r
+MODULE ..\..\trbnet\trb_net16_obuf_nodata.vhd\r
+MODSTYLE trb_net16_obuf_nodata Normal\r
+MODULE ..\..\trbnet\trb_net16_ibuf.vhd\r
+MODSTYLE trb_net16_ibuf Normal\r
+MODULE ..\..\trbnet\trb_net16_iobuf.vhd\r
+MODSTYLE trb_net16_iobuf Normal\r
+MODULE ..\..\trbnet\trb_net16_term_buf.vhd\r
+MODSTYLE trb_net16_term_buf Normal\r
+MODULE ..\..\trbnet\trb_net16_ipudata.vhd\r
+MODSTYLE trb_net16_ipudata Normal\r
+MODULE ..\..\trbnet\trb_net16_trigger.vhd\r
+MODSTYLE trb_net16_trigger Normal\r
+MODULE ..\..\trbnet\trb_net16_endpoint_hades_full.vhd\r
+MODSTYLE trb_net16_endpoint_hades_full Normal\r
+MODULE ..\..\trbnet\lattice\ecp2m\lattice_ecp2m_fifo_16bit_dualport.lpc\r
+MODSTYLE lattice_ecp2m_fifo_16bit_dualport Normal\r
+MODULE ..\..\trbnet\lattice\ecp2m\trb_net_fifo_16bit_bram_dualport.vhd\r
+MODSTYLE trb_net_fifo_16bit_bram_dualport Normal\r
+MODULE ..\..\trbnet\media_interfaces\ecp2m_sfp\serdes_gbe_2.lpc\r
+MODSTYLE serdes_gbe_2 Normal\r
+MODULE ..\..\trbnet\media_interfaces\trb_net16_lsm_sfp.vhd\r
+MODSTYLE trb_net16_lsm_sfp Normal\r
+MODULE ..\..\trbnet\media_interfaces\trb_net16_med_ecp_sfp_gbe.vhd\r
+MODSTYLE trb_net16_med_ecp_sfp_gbe Normal\r
+MODULE ..\design\rich_trb.vhd\r
+MODSTYLE rich_trb Normal\r
+MODULE ..\design\sync_pll_40m.lpc\r
+MODSTYLE sync_pll_40m Normal\r
+MODULE ..\design\dll_100m.lpc\r
+MODSTYLE dll_100m Normal\r
+MODULE ..\design\pll_40m.lpc\r
+MODSTYLE pll_40m Normal\r
+MODULE ..\design\reboot_handler.vhd\r
+MODSTYLE reboot_handler Normal\r
+STIMULUS reboot_handler ..\sim\tb_reboot_handler.vhd\r
+MODULE ..\design\reset_handler.vhd\r
+MODSTYLE reset_handler Normal\r
+MODULE ..\design\adcmv3.vhd\r
+MODSTYLE adcmv3 Normal\r
+SYNTHESIS_TOOL Synplify\r
+SIMULATOR_TOOL ActiveHDL\r
+AUTO_READ_DESIGN TRUE\r
+TOPMODULE adcmv3\r
--- /dev/null
+JDF B\r
+// Created by Version 8.001 \r
+PROJECT adcmv3\r
+DESIGN adcmv3 Normal\r
+DEVKIT LFE2M100E-6F900C\r
+ENTRY Pure VHDL\r
+MODULE ..\..\trbnet\trb_net_sbuf5.vhd\r
+MODULE ..\..\trbnet\trb_net_components.vhd\r
+MODSTYLE ../../trbnet/trb_net_components.vhd Normal\r
+MODULE ..\version.vhd\r
+MODSTYLE ../version.vhd Normal\r
+MODULE ..\design\adcmv3_components.vhd\r
+MODSTYLE ../design/adcmv3_components.vhd Normal\r
+MODULE ..\..\trbnet\trb_net_std.vhd\r
+MODSTYLE ../../trbnet/trb_net_std.vhd Normal\r
+MODULE ..\..\trbnet\lattice\ecp2m\lattice_ecp2m_fifo.vhd\r
+MODSTYLE ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd Normal\r
+MODULE ..\design\dbg_reg.vhd\r
+MODSTYLE dbg_reg Normal\r
+MODULE ..\design\pulse_sync.vhd\r
+MODSTYLE pulse_sync Normal\r
+STIMULUS pulse_sync ..\sim\tb_pulse_sync.vhd\r
+MODULE ..\design\apv_sync_handler.vhd\r
+MODSTYLE apv_sync_handler Normal\r
+MODULE ..\design\apv_trg_handler.vhd\r
+MODSTYLE apv_trg_handler Normal\r
+MODULE ..\design\eds_buffer_dpram.lpc\r
+MODSTYLE eds_buffer_dpram Normal\r
+MODULE ..\design\eds_buf.vhd\r
+MODSTYLE eds_buf Normal\r
+MODULE ..\design\max_data.vhd\r
+MODSTYLE max_data Normal\r
+STIMULUS max_data ..\sim\tb_max_data.vhd\r
+MODULE ..\design\state_sync.vhd\r
+MODSTYLE state_sync Normal\r
+MODULE ..\design\real_trg_handler.vhd\r
+MODSTYLE real_trg_handler Normal\r
+STIMULUS real_trg_handler ..\sim\tb_real_trg_handler.vhd\r
+MODULE ..\design\pulse_stretch.vhd\r
+MODSTYLE pulse_stretch Normal\r
+STIMULUS pulse_stretch ..\sim\tb_pulse_stretch.vhd\r
+MODULE ..\design\apv_trgctrl.vhd\r
+MODSTYLE apv_trgctrl Normal\r
+STIMULUS apv_trgctrl ..\sim\tb_apv_trgctrl.vhd\r
+MODULE ..\design\adc_channel_select.vhd\r
+MODSTYLE adc_channel_select Normal\r
+MODULE ..\design\crossover.lpc\r
+MODSTYLE crossover Normal\r
+STIMULUS crossover ..\sim\tb_crossover.vhd\r
+MODULE ..\design\adc_crossover.vhd\r
+MODSTYLE adc_crossover Normal\r
+STIMULUS adc_crossover ..\sim\tb_adc_crossover.vhd\r
+MODULE ..\design\adc_twochannels.vhd\r
+MODSTYLE adc_twochannels Normal\r
+MODULE ..\design\adc_ch_in.lpc\r
+MODSTYLE adc_ch_in Normal\r
+MODULE ..\design\adc_data_handler.vhd\r
+MODSTYLE adc_data_handler Normal\r
+STIMULUS adc_data_handler ..\sim\tb_adc_handler.vhd\r
+MODULE ..\design\frame_status_mem.lpc\r
+MODSTYLE frame_status_mem Normal\r
+MODULE ..\design\input_bram.lpc\r
+MODSTYLE input_bram Normal\r
+MODULE ..\design\apv_raw_buffer.vhd\r
+MODSTYLE apv_raw_buffer Normal\r
+MODULE ..\design\apv_lock_sm.vhd\r
+MODSTYLE apv_lock_sm Normal\r
+MODULE ..\design\apv_digital.vhd\r
+MODSTYLE apv_digital Normal\r
+MODULE ..\design\apv_locker.vhd\r
+MODSTYLE apv_locker Normal\r
+STIMULUS apv_locker ..\sim\tb_apv_locker.vhd\r
+MODULE ..\design\raw_buf_stage.vhd\r
+MODSTYLE raw_buf_stage Normal\r
+MODULE ..\design\decoder_8bit.lpc\r
+MODSTYLE decoder_8bit Normal\r
+MODULE ..\design\apv_pc_nc_alu.vhd\r
+MODSTYLE apv_pc_nc_alu Normal\r
+STIMULUS apv_pc_nc_alu ..\sim\tb_apv_pc_nc_alu.vhd\r
+MODULE ..\design\buf_toc.vhd\r
+MODSTYLE buf_toc Normal\r
+MODULE ..\design\ref_row_sel.vhd\r
+MODSTYLE ref_row_sel Normal\r
+MODULE ..\design\frmctr_check.vhd\r
+MODSTYLE frmctr_check Normal\r
+MODULE ..\design\ped_corr_ctrl.vhd\r
+MODSTYLE ped_corr_ctrl Normal\r
+STIMULUS ped_corr_ctrl ..\sim\tb_ped_corr_ctrl.vhd\r
+MODULE ..\design\adc_apv_map_mem.lpc\r
+MODSTYLE adc_apv_map_mem Normal\r
+MODULE ..\design\fifo_1kx18.lpc\r
+MODSTYLE fifo_1kx18 Normal\r
+MODULE ..\design\fifo_2kx27.lpc\r
+MODSTYLE fifo_2kx27 Normal\r
+MODULE ..\design\ipu_fifo_stage.vhd\r
+MODSTYLE ipu_fifo_stage Normal\r
+STIMULUS ipu_fifo_stage ..\sim\tb_ipu_fifo_stage.vhd\r
+MODULE ..\design\slv_register.vhd\r
+MODSTYLE slv_register Normal\r
+MODULE ..\design\adc_snoop_mem.lpc\r
+MODSTYLE adc_snoop_mem Normal\r
+MODULE ..\design\slv_adc_snoop.vhd\r
+MODSTYLE slv_adc_snoop Normal\r
+STIMULUS slv_adc_snoop ..\sim\tb_slv_adc_snoop.vhd\r
+MODULE ..\design\slv_half_register.vhd\r
+MODSTYLE slv_half_register Normal\r
+MODULE ..\design\slv_status.vhd\r
+MODSTYLE slv_status Normal\r
+MODULE ..\design\slv_status_bank.vhd\r
+MODSTYLE slv_status_bank Normal\r
+MODULE ..\design\apv_adc_map_mem.lpc\r
+MODSTYLE apv_adc_map_mem Normal\r
+MODULE ..\design\slv_register_bank.vhd\r
+MODSTYLE slv_register_bank Normal\r
+STIMULUS slv_register_bank ..\sim\tb_slv_register_bank.vhd\r
+MODULE ..\design\spi_real_slim.vhd\r
+MODSTYLE spi_real_slim Normal\r
+STIMULUS spi_real_slim ..\sim\tb_spi_real_slim.vhd\r
+MODULE ..\design\spi_adc_master.vhd\r
+MODSTYLE spi_adc_master Normal\r
+MODULE ..\..\trbnet\lattice\ecp2m\spi_dpram_32_to_8.lpc\r
+MODSTYLE spi_dpram_32_to_8 Normal\r
+MODULE ..\..\trbnet\special\spi_databus_memory.vhd\r
+MODSTYLE spi_databus_memory Normal\r
+MODULE ..\..\trbnet\special\spi_slim.vhd\r
+MODSTYLE spi_slim Normal\r
+MODULE ..\..\trbnet\special\spi_master.vhd\r
+MODSTYLE spi_master Normal\r
+STIMULUS spi_master ..\sim\tb_spi_master.vhd\r
+MODULE ..\design\slv_onewire_dpram.lpc\r
+MODSTYLE slv_onewire_dpram Normal\r
+MODULE ..\design\onewire_master.vhd\r
+MODSTYLE onewire_master Normal\r
+STIMULUS onewire_master ..\sim\tb_onewire_master.vhd\r
+MODULE ..\design\onewire_spare_one.lpc\r
+MODSTYLE onewire_spare_one Normal\r
+MODULE ..\design\adc_onewire_map_mem.lpc\r
+MODSTYLE adc_onewire_map_mem Normal\r
+MODULE ..\design\slv_onewire_memory.vhd\r
+MODSTYLE slv_onewire_memory Normal\r
+STIMULUS slv_onewire_memory ..\sim\tb_slv_onewire_memory.vhd\r
+MODULE ..\design\i2c_gstart.vhd\r
+MODSTYLE i2c_gstart Normal\r
+MODULE ..\design\i2c_sendb.vhd\r
+MODSTYLE i2c_sendb Normal\r
+MODULE ..\design\i2c_slim.vhd\r
+MODSTYLE i2c_slim Normal\r
+MODULE ..\design\i2c_master.vhd\r
+MODSTYLE i2c_master Normal\r
+MODULE ..\design\ped_thr_true.lpc\r
+MODSTYLE ped_thr_true Normal\r
+MODULE ..\design\slv_ped_thr_mem.vhd\r
+MODSTYLE slv_ped_thr_mem Normal\r
+STIMULUS slv_ped_thr_mem ..\sim\tb_slv_ped_thr_mem.vhd\r
+MODULE ..\..\trbnet\trb_net16_regio_bus_handler.vhd\r
+MODSTYLE trb_net16_regio_bus_handler Normal\r
+MODULE ..\design\slave_bus.vhd\r
+MODSTYLE slave_bus Normal\r
+MODULE ..\..\trbnet\trb_net_sbuf.vhd\r
+MODSTYLE trb_net_sbuf Normal\r
+MODULE ..\..\trbnet\trb_net16_sbuf.vhd\r
+MODSTYLE trb_net16_sbuf Normal\r
+MODULE ..\..\trbnet\trb_net_priority_encoder.vhd\r
+MODSTYLE trb_net_priority_encoder Normal\r
+MODULE ..\..\trbnet\trb_net_priority_arbiter.vhd\r
+MODSTYLE trb_net_priority_arbiter Normal\r
+MODULE ..\..\trbnet\trb_net16_io_multiplexer.vhd\r
+MODSTYLE trb_net16_io_multiplexer Normal\r
+MODULE ..\..\trbnet\trb_net_onewire.vhd\r
+MODSTYLE trb_net_onewire Normal\r
+MODULE ..\..\trbnet\basics\rom_16x8.vhd\r
+MODSTYLE rom_16x8 Normal\r
+MODULE ..\..\trbnet\basics\ram_16x16_dp.vhd\r
+MODSTYLE ram_16x16_dp Normal\r
+MODULE ..\..\trbnet\trb_net16_addresses.vhd\r
+MODSTYLE trb_net16_addresses Normal\r
+MODULE ..\..\trbnet\trb_net_pattern_gen.vhd\r
+MODSTYLE trb_net_pattern_gen Normal\r
+MODULE ..\..\trbnet\trb_net16_regIO.vhd\r
+MODSTYLE trb_net16_regio Normal\r
+MODULE ..\..\trbnet\lattice\ecp2m\lattice_ecp2m_fifo_18x1k.lpc\r
+MODSTYLE lattice_ecp2m_fifo_18x1k Normal\r
+MODULE ..\..\trbnet\lattice\ecp2m\trb_net16_fifo_arch.vhd\r
+MODSTYLE trb_net16_fifo Normal\r
+MODULE ..\..\trbnet\trb_net16_api_base.vhd\r
+MODSTYLE trb_net16_api_base Normal\r
+MODULE ..\..\trbnet\trb_net_CRC.vhd\r
+MODSTYLE trb_net_crc Normal\r
+MODULE ..\..\trbnet\trb_net16_obuf.vhd\r
+MODSTYLE trb_net16_obuf Normal\r
+MODULE ..\..\trbnet\trb_net16_obuf_nodata.vhd\r
+MODSTYLE trb_net16_obuf_nodata Normal\r
+MODULE ..\..\trbnet\trb_net16_ibuf.vhd\r
+MODSTYLE trb_net16_ibuf Normal\r
+MODULE ..\..\trbnet\trb_net16_iobuf.vhd\r
+MODSTYLE trb_net16_iobuf Normal\r
+MODULE ..\..\trbnet\trb_net16_term_buf.vhd\r
+MODSTYLE trb_net16_term_buf Normal\r
+MODULE ..\..\trbnet\trb_net16_ipudata.vhd\r
+MODSTYLE trb_net16_ipudata Normal\r
+MODULE ..\..\trbnet\trb_net16_trigger.vhd\r
+MODSTYLE trb_net16_trigger Normal\r
+MODULE ..\..\trbnet\trb_net16_endpoint_hades_full.vhd\r
+MODSTYLE trb_net16_endpoint_hades_full Normal\r
+MODULE ..\..\trbnet\lattice\ecp2m\lattice_ecp2m_fifo_16bit_dualport.lpc\r
+MODSTYLE lattice_ecp2m_fifo_16bit_dualport Normal\r
+MODULE ..\..\trbnet\lattice\ecp2m\trb_net_fifo_16bit_bram_dualport.vhd\r
+MODSTYLE trb_net_fifo_16bit_bram_dualport Normal\r
+MODULE ..\..\trbnet\media_interfaces\ecp2m_sfp\serdes_gbe_2.lpc\r
+MODSTYLE serdes_gbe_2 Normal\r
+MODULE ..\..\trbnet\media_interfaces\trb_net16_lsm_sfp.vhd\r
+MODSTYLE trb_net16_lsm_sfp Normal\r
+MODULE ..\..\trbnet\basics\signal_sync.vhd\r
+MODSTYLE signal_sync Normal\r
+MODULE ..\..\trbnet\media_interfaces\trb_net16_med_ecp_sfp_gbe.vhd\r
+MODSTYLE trb_net16_med_ecp_sfp_gbe Normal\r
+MODULE ..\design\rich_trb.vhd\r
+MODSTYLE rich_trb Normal\r
+MODULE ..\design\sync_pll_40m.lpc\r
+MODSTYLE sync_pll_40m Normal\r
+MODULE ..\design\dll_100m.lpc\r
+MODSTYLE dll_100m Normal\r
+MODULE ..\design\pll_40m.lpc\r
+MODSTYLE pll_40m Normal\r
+MODULE ..\design\reboot_handler.vhd\r
+MODSTYLE reboot_handler Normal\r
+STIMULUS reboot_handler ..\sim\tb_reboot_handler.vhd\r
+MODULE ..\design\reset_handler.vhd\r
+MODSTYLE reset_handler Normal\r
+MODULE ..\design\adcmv3.vhd\r
+MODSTYLE adcmv3 Normal\r
+SYNTHESIS_TOOL Synplify\r
+SIMULATOR_TOOL ActiveHDL\r
+AUTO_READ_DESIGN TRUE\r
+TOPMODULE adcmv3\r
--- /dev/null
+\r
+########## Tcl recorder starts at 05/21/10 17:22:04 ##########\r
+\r
+set version "8.0"\r
+set proj_dir "I:/VHDL_Pro/comp_adcmv3/lever"\r
+cd $proj_dir\r
+\r
+# Get directory paths\r
+set pver $version\r
+regsub -all {\.} $pver {_} pver\r
+set lscfile "lsc_"\r
+append lscfile $pver ".ini"\r
+set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]\r
+set lsvini_path [file join $lsvini_dir $lscfile]\r
+if {[catch {set fid [open $lsvini_path]} msg]} {\r
+ puts "File Open Error: $lsvini_path"\r
+ return false\r
+} else {set data [read $fid]; close $fid }\r
+foreach line [split $data '\n'] { \r
+ set lline [string tolower $line]\r
+ set lline [string trim $lline]\r
+ if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}\r
+ if {$path && [regexp {^\[} $lline]} {set path 0; break}\r
+ if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}\r
+ if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line; continue}\r
+ if {$path && [regexp {^fpgabinpath} $lline]} {set fpga_bin $line}}\r
+\r
+set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]\r
+regsub -all "\"" $cpld_bin "" cpld_bin\r
+set cpld_bin [file join $cpld_bin]\r
+set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]\r
+regsub -all "\"" $install_dir "" install_dir\r
+set install_dir [file join $install_dir]\r
+set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]\r
+regsub -all "\"" $fpga_dir "" fpga_dir\r
+set fpga_dir [file join $fpga_dir]\r
+set fpga_bin [string range $fpga_bin [expr [string first "=" $fpga_bin]+1] end]\r
+regsub -all "\"" $fpga_bin "" fpga_bin\r
+set fpga_bin [file join $fpga_bin]\r
+\r
+if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {\r
+ set env(PATH) "$fpga_bin;$env(PATH)" }\r
+\r
+if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {\r
+ set env(PATH) "$cpld_bin;$env(PATH)" }\r
+\r
+lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]\r
+package require runcmd\r
+\r
+# Commands to make the Process: \r
+# Hierarchy\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/eds_buffer_dpram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/crossover.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_ch_in.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/frame_status_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/input_bram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adder_16bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adder_5bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/decoder_8bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/comp14bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_apv_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/fifo_1kx18.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/comp_12bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/suber_12bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/fifo_2kx27.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_snoop_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/apv_adc_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/slv_onewire_dpram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/onewire_spare_one.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_onewire_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/ped_thr_true.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/sync_pll_40m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/dll_100m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/pll_40m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 05/21/10 17:22:04 ###########\r
+\r
+\r
+########## Tcl recorder starts at 05/21/10 17:31:15 ##########\r
+\r
+# Commands to make the Process: \r
+# Hierarchy\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/eds_buffer_dpram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/crossover.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_ch_in.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/frame_status_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/input_bram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adder_16bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adder_5bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/decoder_8bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_apv_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/fifo_1kx18.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/comp_12bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/suber_12bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/fifo_2kx27.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_snoop_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/apv_adc_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/slv_onewire_dpram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/onewire_spare_one.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_onewire_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/ped_thr_true.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/sync_pll_40m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/dll_100m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/pll_40m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 05/21/10 17:31:15 ###########\r
+\r
+\r
+########## Tcl recorder starts at 05/21/10 17:37:32 ##########\r
+\r
+# Commands to make the Process: \r
+# Hierarchy\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/eds_buffer_dpram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/crossover.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_ch_in.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/frame_status_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/input_bram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/decoder_8bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_apv_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/fifo_1kx18.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/comp_12bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/suber_12bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/fifo_2kx27.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_snoop_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/apv_adc_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/slv_onewire_dpram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/onewire_spare_one.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_onewire_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/ped_thr_true.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/sync_pll_40m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/dll_100m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/pll_40m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 05/21/10 17:37:32 ###########\r
+\r
+\r
+########## Tcl recorder starts at 05/25/10 10:19:28 ##########\r
+\r
+# Commands to make the Process: \r
+# Hierarchy\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/eds_buffer_dpram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/crossover.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_ch_in.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/frame_status_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/input_bram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/decoder_8bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_apv_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/fifo_1kx18.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/comp_12bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/fifo_2kx27.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_snoop_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/apv_adc_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/slv_onewire_dpram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/onewire_spare_one.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_onewire_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/ped_thr_true.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/sync_pll_40m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/dll_100m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/pll_40m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 05/25/10 10:19:29 ###########\r
+\r
+\r
+########## Tcl recorder starts at 05/28/10 11:55:33 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_ped_corr_ctrl_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_ped_corr_ctrl.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_ped_corr_ctrl.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd\r
+#vcomSrc ../sim/tb_ped_corr_ctrl.vhd\r
+#stimulus vhdl ped_corr_ctrl ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_ped_corr_ctrl.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_ped_corr_ctrl_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_ped_corr_ctrl.rsp tb_ped_corr_ctrl.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_ped_corr_ctrl_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_ped_corr_ctrl_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_ped_corr_ctrl_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_ped_corr_ctrl_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_ped_corr_ctrl.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_ped_corr_ctrl_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 05/28/10 11:55:33 ###########\r
+\r
+\r
+########## Tcl recorder starts at 05/28/10 11:58:26 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_ped_corr_ctrl_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_ped_corr_ctrl.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_ped_corr_ctrl.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd\r
+#vcomSrc ../sim/tb_ped_corr_ctrl.vhd\r
+#stimulus vhdl ped_corr_ctrl ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_ped_corr_ctrl.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_ped_corr_ctrl_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_ped_corr_ctrl.rsp tb_ped_corr_ctrl.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_ped_corr_ctrl_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_ped_corr_ctrl_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_ped_corr_ctrl_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_ped_corr_ctrl_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_ped_corr_ctrl.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_ped_corr_ctrl_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 05/28/10 11:58:26 ###########\r
+\r
+\r
+########## Tcl recorder starts at 05/28/10 13:29:22 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_ped_corr_ctrl_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_ped_corr_ctrl.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_ped_corr_ctrl.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd\r
+#vcomSrc ../sim/tb_ped_corr_ctrl.vhd\r
+#stimulus vhdl ped_corr_ctrl ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_ped_corr_ctrl.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_ped_corr_ctrl_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_ped_corr_ctrl.rsp tb_ped_corr_ctrl.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_ped_corr_ctrl_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_ped_corr_ctrl_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_ped_corr_ctrl_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_ped_corr_ctrl_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_ped_corr_ctrl.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_ped_corr_ctrl_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 05/28/10 13:29:22 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 10:48:46 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Test Bench Template\r
+if [catch {open fifo_18x16_media_interface.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file fifo_18x16_media_interface.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/hdl2jhd\" -tfi -proj \"adcmv3\" -mod fifo_18x16_media_interface -out \"fifo_18x16_media_interface\" -tpl \"$install_dir/ispcpld/generic/vhdl/tstbch_f.tft\" -ext vht -pf \"$install_dir/ispcpld/../cae_library/synthesis/verilog/ecp2m.v\" -setting adcmv3.sty -lst fifo_18x16_media_interface.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+file delete fifo_18x16_media_interface.rsp\r
+\r
+########## Tcl recorder end at 06/07/10 10:48:46 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 10:52:57 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_media_fifo_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_media_fifo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd\r
+#vcomSrc ../sim/tb_media_fifo.vhd\r
+#stimulus vhdl fifo_18x16_media_interface ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_media_fifo.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_media_fifo_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_media_fifo.rsp tb_media_fifo.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_media_fifo_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_media_fifo_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_media_fifo.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_media_fifo_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 10:52:57 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 10:54:27 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_media_fifo_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_media_fifo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd\r
+#vcomSrc ../sim/tb_media_fifo.vhd\r
+#stimulus vhdl fifo_18x16_media_interface ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_media_fifo.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_media_fifo_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_media_fifo.rsp tb_media_fifo.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_media_fifo_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_media_fifo_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_media_fifo.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_media_fifo_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 10:54:27 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 11:31:12 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Test Bench Template\r
+if [catch {open test_media.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file test_media.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/hdl2jhd\" -tfi -proj \"adcmv3\" -mod test_media -out \"test_media\" -tpl \"$install_dir/ispcpld/generic/vhdl/tstbch_f.tft\" -ext vht -pf \"$install_dir/ispcpld/../cae_library/synthesis/verilog/ecp2m.v\" -setting adcmv3.sty -lst test_media.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+file delete test_media.rsp\r
+\r
+########## Tcl recorder end at 06/07/10 11:31:13 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 11:36:47 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_test_media_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd\r
+#vcomSrc ../sim/tb_test_media.vhd\r
+#stimulus vhdl test_media ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_test_media.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_test_media_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_test_media.rsp tb_test_media.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 11:36:47 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 11:42:10 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_test_media_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd\r
+#vcomSrc ../sim/tb_test_media.vhd\r
+#stimulus vhdl test_media ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_test_media.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_test_media_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_test_media.rsp tb_test_media.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 11:42:10 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 11:43:08 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_test_media_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd\r
+#vcomSrc ../sim/tb_test_media.vhd\r
+#stimulus vhdl test_media ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_test_media.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_test_media_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_test_media.rsp tb_test_media.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 11:43:08 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 11:57:50 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 11:57:50 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 12:01:06 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 12:01:06 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 14:11:22 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 14:11:22 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 14:12:22 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 14:12:22 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 14:47:55 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 14:47:55 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 14:49:00 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 14:49:00 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 14:49:55 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_test_media_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd\r
+#vcomSrc ../sim/tb_test_media.vhd\r
+#stimulus vhdl test_media ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_test_media.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_test_media_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_test_media.rsp tb_test_media.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 14:49:55 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 14:53:08 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 14:53:08 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 14:57:01 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 14:57:01 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 14:59:11 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 14:59:11 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 15:01:50 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_test_media_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd\r
+#vcomSrc ../sim/tb_test_media.vhd\r
+#stimulus vhdl test_media ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_test_media.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_test_media_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_test_media.rsp tb_test_media.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 15:01:50 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 15:03:39 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_test_media_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd\r
+#vcomSrc ../sim/tb_test_media.vhd\r
+#stimulus vhdl test_media ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_test_media.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_test_media_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_test_media.rsp tb_test_media.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 15:03:39 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 15:07:56 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_test_media_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd\r
+#vcomSrc ../sim/tb_test_media.vhd\r
+#stimulus vhdl test_media ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_test_media.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_test_media_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_test_media.rsp tb_test_media.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 15:07:56 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 15:08:58 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_test_media_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd\r
+#vcomSrc ../sim/tb_test_media.vhd\r
+#stimulus vhdl test_media ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_test_media.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_test_media_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_test_media.rsp tb_test_media.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 15:08:58 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 18:02:18 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 18:02:18 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 18:06:19 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_test_media_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd\r
+#vcomSrc ../sim/tb_test_media.vhd\r
+#stimulus vhdl test_media ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_test_media.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_test_media_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_test_media.rsp tb_test_media.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 18:06:19 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 18:08:37 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 18:08:37 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 18:09:36 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_test_media_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd\r
+#vcomSrc ../sim/tb_test_media.vhd\r
+#stimulus vhdl test_media ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_test_media.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_test_media_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_test_media.rsp tb_test_media.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 18:09:36 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 18:14:09 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 18:14:09 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/07/10 18:14:47 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_test_media_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_test_media_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_test_media_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_test_media_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/07/10 18:14:47 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/08/10 09:36:34 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_sfp_rx_handler.rsp tb_sfp_rx_handler.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/08/10 09:36:34 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/08/10 09:38:46 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/08/10 09:38:46 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/08/10 09:40:06 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_sfp_rx_handler.rsp tb_sfp_rx_handler.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/08/10 09:40:06 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/08/10 09:42:24 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_sfp_rx_handler.rsp tb_sfp_rx_handler.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/08/10 09:42:24 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/08/10 10:08:42 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_sfp_rx_handler.rsp tb_sfp_rx_handler.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/08/10 10:08:42 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/08/10 10:09:45 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_sfp_rx_handler.rsp tb_sfp_rx_handler.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/08/10 10:09:45 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/08/10 10:10:29 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_sfp_rx_handler.rsp tb_sfp_rx_handler.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/08/10 10:10:29 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/08/10 10:14:02 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_sfp_rx_handler.rsp tb_sfp_rx_handler.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/08/10 10:14:02 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/08/10 10:28:05 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/08/10 10:28:05 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/08/10 10:28:39 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_sfp_rx_handler.rsp tb_sfp_rx_handler.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/08/10 10:28:39 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/08/10 11:37:30 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_sfp_rx_handler.rsp tb_sfp_rx_handler.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/08/10 11:37:30 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/08/10 11:38:22 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/08/10 11:38:22 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/08/10 11:40:56 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_sfp_rx_handler.rsp tb_sfp_rx_handler.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/08/10 11:40:56 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/08/10 11:41:44 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_sfp_rx_handler.rsp tb_sfp_rx_handler.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/08/10 11:41:44 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/09/10 18:03:16 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../design/sfp_rx_handler.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_sfp_rx_handler.rsp tb_sfp_rx_handler.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/09/10 18:03:16 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/10/10 09:22:23 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_media_fifo_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_media_fifo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd\r
+#vcomSrc ../sim/tb_media_fifo.vhd\r
+#stimulus vhdl fifo_18x16_media_interface ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../design/sfp_rx_handler.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_media_fifo.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_media_fifo_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_media_fifo.rsp tb_media_fifo.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_media_fifo_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_media_fifo_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_media_fifo.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_media_fifo_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/10/10 09:22:23 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/10/10 09:27:29 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_media_fifo_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_media_fifo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd\r
+#vcomSrc ../sim/tb_media_fifo.vhd\r
+#stimulus vhdl fifo_18x16_media_interface ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../design/sfp_rx_handler.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_media_fifo.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_media_fifo_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_media_fifo.rsp tb_media_fifo.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_media_fifo_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_media_fifo_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_media_fifo.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_media_fifo_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/10/10 09:27:29 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/10/10 09:33:43 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_media_fifo_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_media_fifo_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_media_fifo.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_media_fifo_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/10/10 09:33:43 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/10/10 09:40:48 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Test Bench Template\r
+if [catch {open fifo_18x16_media_interface_mb.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file fifo_18x16_media_interface_mb.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface_mb.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../design/sfp_rx_handler.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/hdl2jhd\" -tfi -proj \"adcmv3\" -mod fifo_18x16_media_interface_mb -out \"fifo_18x16_media_interface_mb\" -tpl \"$install_dir/ispcpld/generic/vhdl/tstbch_f.tft\" -ext vht -pf \"$install_dir/ispcpld/../cae_library/synthesis/verilog/ecp2m.v\" -setting adcmv3.sty -lst fifo_18x16_media_interface_mb.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+file delete fifo_18x16_media_interface_mb.rsp\r
+\r
+########## Tcl recorder end at 06/10/10 09:40:48 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/10/10 09:44:15 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_media_fifo_mb_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_media_fifo_mb.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_mb.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface_mb.vhd\r
+#vcomSrc ../sim/tb_media_fifo_mb.vhd\r
+#stimulus vhdl fifo_18x16_media_interface_mb ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface_mb.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../design/sfp_rx_handler.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_media_fifo_mb.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_media_fifo_mb_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_media_fifo_mb.rsp tb_media_fifo_mb.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_media_fifo_mb_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_mb_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_media_fifo_mb_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_mb_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_media_fifo_mb.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_media_fifo_mb_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/10/10 09:44:15 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/10/10 09:44:58 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_media_fifo_mb_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_media_fifo_mb.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_mb.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface_mb.vhd\r
+#vcomSrc ../sim/tb_media_fifo_mb.vhd\r
+#stimulus vhdl fifo_18x16_media_interface_mb ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface_mb.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../design/sfp_rx_handler.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_media_fifo_mb.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_media_fifo_mb_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_media_fifo_mb.rsp tb_media_fifo_mb.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_media_fifo_mb_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_mb_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_media_fifo_mb_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_media_fifo_mb_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_media_fifo_mb.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_media_fifo_mb_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/10/10 09:44:58 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/10/10 09:55:24 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface_mb.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface_mb.vhd ../design/sfp_rx_handler.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_sfp_rx_handler.rsp tb_sfp_rx_handler.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/10/10 09:55:24 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/10/10 10:00:26 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface_mb.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface_mb.vhd ../design/sfp_rx_handler.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_sfp_rx_handler.rsp tb_sfp_rx_handler.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/10/10 10:00:26 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/10/10 10:02:43 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/10/10 10:02:43 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/10/10 10:13:05 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/10/10 10:13:05 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/10/10 10:16:12 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/10/10 10:16:12 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/10/10 10:24:23 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/10/10 10:24:23 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/10/10 10:28:14 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/10/10 10:28:14 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/10/10 10:32:02 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface_mb.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../design/sfp_rx_handler.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_sfp_rx_handler.rsp tb_sfp_rx_handler.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/10/10 10:32:02 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/10/10 10:33:25 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_sfp_rx_handler_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_sfp_rx_handler_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_sfp_rx_handler_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_sfp_rx_handler_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/10/10 10:33:25 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/18/10 10:30:59 ##########\r
+\r
+# Commands to make the Process: \r
+# Synplify Synthesize VHDL File\r
+if [catch {open adcmv3.rvp w} rspFile] {\r
+ puts stderr "Cannot create response file adcmv3.rvp: $rspFile"\r
+} else {\r
+ puts $rspFile "STYFILENAME=adcmv3.sty\r
+PROJECT=adcmv3\r
+ENTRY=Pure VHDL\r
+WORKING_PATH=$proj_dir\r
+MODULE=adcmv3\r
+TOP_FILE=../design/adcmv3.vhd\r
+EDF_FILE_LIST=../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/test_media.vhd ../design/sbuf.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd\r
+VHDL_FILE_LIST=../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/test_media.vhd ../design/sbuf.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd\r
+VERILOG_FILE_LIST=../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/test_media.vhd ../design/sbuf.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd\r
+DEVICEPART=LFE2M100E-6F900C\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open sbuf.cmd w} rspFile] {\r
+ puts stderr "Cannot create response file sbuf.cmd: $rspFile"\r
+} else {\r
+ puts $rspFile "STYFILENAME: adcmv3.sty\r
+PROJECT: sbuf\r
+WORKING_PATH: \"$proj_dir\"\r
+MODULE: work.sbuf\r
+VHDL_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/vhdl/ecp2m.vhd\" ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/test_media.vhd ../design/sbuf.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd\r
+OUTPUT_FILE_NAME: sbuf\r
+SUFFIX_NAME: edi\r
+WRITE_PRF: false\r
+FREQUENCY: 200\r
+FANOUT_LIMIT: 100\r
+DISABLE_IO_INSERTION: false\r
+FORCE_GSR: false\r
+SPEED_GRADE: -6\r
+SYMBOLIC_FSM_COMPILER: true\r
+NUM_CRITICAL_PATHS: 3\r
+AUTO_CONSTRAIN_IO: true\r
+NUM_STARTEND_POINTS: 0\r
+COMPILER_COMPATIBLE: true\r
+RETIMING: none\r
+RESOURCE_SHARING: true\r
+DEFAULT_ENUM_ENCODING: default\r
+fixgatedclocks: 3\r
+fixgeneratedclocks: 3\r
+Vlog_std_v2001: V2001\r
+DUP: false\r
+ARRANGE_VHDL_FILES: true\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/Synpwrap\" -dyn -e sbuf -target LATTICE-ecp2m -part LFE2M100E -pro -oem"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/18/10 10:30:59 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/18/10 11:24:37 ##########\r
+\r
+# Commands to make the Process: \r
+# Hierarchy\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/eds_buffer_dpram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/crossover.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_ch_in.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/frame_status_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/input_bram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/decoder_8bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_apv_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/fifo_1kx18.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/fifo_2kx27.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_snoop_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/apv_adc_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/slv_onewire_dpram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/onewire_spare_one.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_onewire_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/ped_thr_true.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/sync_pll_40m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/dll_100m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/pll_40m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/18/10 11:24:37 ###########\r
+\r
+\r
+########## Tcl recorder starts at 06/18/10 11:27:54 ##########\r
+\r
+# Commands to make the Process: \r
+# Hierarchy\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/eds_buffer_dpram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/crossover.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_ch_in.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/frame_status_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/input_bram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/decoder_8bit.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_apv_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/fifo_1kx18.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/fifo_2kx27.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_snoop_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/apv_adc_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/slv_onewire_dpram.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/onewire_spare_one.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/adc_onewire_map_mem.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/ped_thr_true.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/sync_pll_40m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/dll_100m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$cpld_bin/lpc2jhd\" ../design/pll_40m.lpc -family LatticeECP2M"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 06/18/10 11:27:54 ###########\r
+\r
+\r
+########## Tcl recorder starts at 09/01/10 12:32:35 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_apv_trgctrl_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_apv_trgctrl.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_apv_trgctrl.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd\r
+#vcomSrc ../sim/tb_apv_trgctrl.vhd\r
+#stimulus vhdl apv_trgctrl ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../../trbnet/basics/signal_sync.vhd ../design/pulse_stretch.vhd ../../trbnet/special/handler_lvl1.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_apv_trgctrl.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_apv_trgctrl_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_apv_trgctrl.rsp tb_apv_trgctrl.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_apv_trgctrl_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_apv_trgctrl_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_apv_trgctrl_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_apv_trgctrl_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_apv_trgctrl.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_apv_trgctrl_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 09/01/10 12:32:35 ###########\r
+\r
+\r
+########## Tcl recorder starts at 09/01/10 12:35:20 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_apv_trgctrl_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_apv_trgctrl.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_apv_trgctrl.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd\r
+#vcomSrc ../sim/tb_apv_trgctrl.vhd\r
+#stimulus vhdl apv_trgctrl ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../../trbnet/basics/signal_sync.vhd ../design/pulse_stretch.vhd ../../trbnet/special/handler_lvl1.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_apv_trgctrl.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_apv_trgctrl_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_apv_trgctrl.rsp tb_apv_trgctrl.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_apv_trgctrl_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_apv_trgctrl_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_apv_trgctrl_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_apv_trgctrl_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_apv_trgctrl.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_apv_trgctrl_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 09/01/10 12:35:20 ###########\r
+\r
+\r
+########## Tcl recorder starts at 09/01/10 12:47:48 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_apv_trgctrl_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_apv_trgctrl.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_apv_trgctrl.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd\r
+#vcomSrc ../sim/tb_apv_trgctrl.vhd\r
+#stimulus vhdl apv_trgctrl ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../../trbnet/basics/signal_sync.vhd ../design/pulse_stretch.vhd ../../trbnet/special/handler_lvl1.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_apv_trgctrl.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_apv_trgctrl_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_apv_trgctrl.rsp tb_apv_trgctrl.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_apv_trgctrl_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_apv_trgctrl_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_apv_trgctrl_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_apv_trgctrl_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_apv_trgctrl.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_apv_trgctrl_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 09/01/10 12:47:48 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 16:33:36 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_spi_master_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd\r
+#vcomSrc ../sim/tb_spi_master.vhd\r
+#stimulus vhdl spi_master ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/special/handler_lvl1.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net_sbuf5.vhd ../../trbnet/trb_net_sbuf6.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_spi_master.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_spi_master_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_spi_master.rsp tb_spi_master.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 16:33:36 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 16:37:11 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_spi_master_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd\r
+#vcomSrc ../sim/tb_spi_master.vhd\r
+#stimulus vhdl spi_master ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/special/handler_lvl1.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net_sbuf5.vhd ../../trbnet/trb_net_sbuf6.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_spi_master.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_spi_master_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_spi_master.rsp tb_spi_master.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 16:37:11 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 16:39:49 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_spi_master_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd\r
+#vcomSrc ../sim/tb_spi_master.vhd\r
+#stimulus vhdl spi_master ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/special/handler_lvl1.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net_sbuf5.vhd ../../trbnet/trb_net_sbuf6.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_spi_master.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_spi_master_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_spi_master.rsp tb_spi_master.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 16:39:49 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 16:41:09 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_spi_master_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd\r
+#vcomSrc ../sim/tb_spi_master.vhd\r
+#stimulus vhdl spi_master ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/special/handler_lvl1.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net_sbuf5.vhd ../../trbnet/trb_net_sbuf6.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_spi_master.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_spi_master_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_spi_master.rsp tb_spi_master.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 16:41:09 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 16:42:55 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_spi_master_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd\r
+#vcomSrc ../sim/tb_spi_master.vhd\r
+#stimulus vhdl spi_master ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/special/handler_lvl1.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net_sbuf5.vhd ../../trbnet/trb_net_sbuf6.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_spi_master.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_spi_master_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_spi_master.rsp tb_spi_master.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 16:42:55 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 16:48:54 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_spi_master_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd\r
+#vcomSrc ../sim/tb_spi_master.vhd\r
+#stimulus vhdl spi_master ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/special/handler_lvl1.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net_sbuf5.vhd ../../trbnet/trb_net_sbuf6.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_spi_master.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_spi_master_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_spi_master.rsp tb_spi_master.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 16:48:54 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 16:50:36 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_spi_master_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd\r
+#vcomSrc ../sim/tb_spi_master.vhd\r
+#stimulus vhdl spi_master ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/special/handler_lvl1.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net_sbuf5.vhd ../../trbnet/trb_net_sbuf6.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_spi_master.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_spi_master_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_spi_master.rsp tb_spi_master.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 16:50:36 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 16:52:02 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_spi_master_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd\r
+#vcomSrc ../sim/tb_spi_master.vhd\r
+#stimulus vhdl spi_master ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/special/handler_lvl1.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net_sbuf5.vhd ../../trbnet/trb_net_sbuf6.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_spi_master.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_spi_master_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_spi_master.rsp tb_spi_master.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 16:52:02 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 16:56:58 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_spi_master_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd\r
+#vcomSrc ../sim/tb_spi_master.vhd\r
+#stimulus vhdl spi_master ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/special/handler_lvl1.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net_sbuf5.vhd ../../trbnet/trb_net_sbuf6.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_spi_master.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_spi_master_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_spi_master.rsp tb_spi_master.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 16:56:58 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 16:58:08 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_spi_master_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd\r
+#vcomSrc ../sim/tb_spi_master.vhd\r
+#stimulus vhdl spi_master ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/special/handler_lvl1.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net_sbuf5.vhd ../../trbnet/trb_net_sbuf6.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_spi_master.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_spi_master_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_spi_master.rsp tb_spi_master.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 16:58:08 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 16:59:40 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_spi_master_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd\r
+#vcomSrc ../sim/tb_spi_master.vhd\r
+#stimulus vhdl spi_master ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/special/handler_lvl1.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net_sbuf5.vhd ../../trbnet/trb_net_sbuf6.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_spi_master.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_spi_master_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_spi_master.rsp tb_spi_master.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 16:59:40 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 17:01:11 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_spi_master_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd\r
+#vcomSrc ../sim/tb_spi_master.vhd\r
+#stimulus vhdl spi_master ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/special/handler_lvl1.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net_sbuf5.vhd ../../trbnet/trb_net_sbuf6.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_spi_master.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_spi_master_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_spi_master.rsp tb_spi_master.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 17:01:11 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 17:16:37 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 17:16:37 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 17:18:13 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 17:18:13 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 17:19:11 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 17:19:11 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 17:23:40 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 17:23:40 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 17:27:39 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 17:27:39 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 17:28:28 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 17:28:28 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 17:36:55 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 17:36:55 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 17:39:21 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 17:39:21 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 17:45:45 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 17:45:45 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 17:48:26 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 17:48:26 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 17:49:27 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open udo.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file udo.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-- ispLEVER VHDL Functional Simulation Template: tb_spi_master_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {$cpld_bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd\r
+#vcomSrc ../sim/tb_spi_master.vhd\r
+#stimulus vhdl spi_master ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/special/handler_lvl1.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net_sbuf5.vhd ../../trbnet/trb_net_sbuf6.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_spi_master.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_spi_master_vhdf.udo %<StimModule>%\r
+#insert # End\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/chipsim\" tb_spi_master.rsp tb_spi_master.fado udo.rsp"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 17:49:27 ###########\r
+\r
+\r
+########## Tcl recorder starts at 02/03/11 17:50:29 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 02/03/11 17:50:29 ###########\r
+\r
+\r
+########## Tcl recorder starts at 10/12/11 10:42:41 ##########\r
+\r
+# Commands to make the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+# - none -\r
+# Application to view the Process: \r
+# VHDL Functional Simulation With Aldec Active-HDL\r
+if [catch {open tb_spi_master_activehdl2.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl2.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open tb_spi_master_activehdl.do w} rspFile] {\r
+ puts stderr "Cannot create response file tb_spi_master_activehdl.do: $rspFile"\r
+} else {\r
+ puts $rspFile "setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$install_dir/active-hdl/bin/avhdl\" -do \"tb_spi_master_activehdl.do\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 10/12/11 10:42:41 ###########\r
+\r
--- /dev/null
+[Tcl]\r
+Start = Yes;\r
+Process = YES;\r
+Append = YES;\r
+TclFilename = adcmv3.tcl;\r
--- /dev/null
+\r
+-- VHDL Test Bench Created from source file fifo_18x16_media_interface.vhd -- Mon Jun 07 10:48:50 2010\r
+\r
+--\r
+-- Notes: \r
+-- 1) This testbench template has been automatically generated using types\r
+-- std_logic and std_logic_vector for the ports of the unit under test.\r
+-- Lattice recommends that these types always be used for the top-level\r
+-- I/O of a design in order to guarantee that the testbench will bind\r
+-- correctly to the timing (post-route) simulation model.\r
+-- 2) To use this template as your testbench, change the filename to any\r
+-- name of your choice with the extension .vhd, and use the "source->import"\r
+-- menu in the ispLEVER Project Navigator to import the testbench.\r
+-- Then edit the user defined section below, adding code to generate the \r
+-- stimulus for your design.\r
+-- 3) VHDL simulations will produce errors if there are Lattice FPGA library \r
+-- elements in your design that require the instantiation of GSR, PUR, and\r
+-- TSALL and they are not present in the testbench. For more information see\r
+-- the How To section of online help. \r
+--\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT fifo_18x16_media_interface\r
+ PORT(\r
+ Data : IN std_logic_vector(17 downto 0);\r
+ Clock : IN std_logic;\r
+ WrEn : IN std_logic;\r
+ RdEn : IN std_logic;\r
+ Reset : IN std_logic; \r
+ Q : OUT std_logic_vector(17 downto 0);\r
+ WCNT : OUT std_logic_vector(4 downto 0);\r
+ Empty : OUT std_logic;\r
+ Full : OUT std_logic;\r
+ AlmostEmpty : OUT std_logic\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL Data : std_logic_vector(17 downto 0);\r
+ SIGNAL Clock : std_logic;\r
+ SIGNAL WrEn : std_logic;\r
+ SIGNAL RdEn : std_logic;\r
+ SIGNAL Reset : std_logic;\r
+ SIGNAL Q : std_logic_vector(17 downto 0);\r
+ SIGNAL WCNT : std_logic_vector(4 downto 0);\r
+ SIGNAL Empty : std_logic;\r
+ SIGNAL Full : std_logic;\r
+ SIGNAL AlmostEmpty : std_logic;\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: fifo_18x16_media_interface PORT MAP(\r
+ Data => Data,\r
+ Clock => Clock,\r
+ WrEn => WrEn,\r
+ RdEn => RdEn,\r
+ Reset => Reset,\r
+ Q => Q,\r
+ WCNT => WCNT,\r
+ Empty => Empty,\r
+ Full => Full,\r
+ AlmostEmpty => AlmostEmpty\r
+ );\r
+\r
+\r
+-- *** Test Bench - User Defined Section ***\r
+ tb : PROCESS\r
+ BEGIN\r
+ wait; -- will wait forever\r
+ END PROCESS;\r
+-- *** End Test Bench - User Defined Section ***\r
+\r
+END;\r
--- /dev/null
+\r
+-- VHDL Test Bench Created from source file fifo_18x16_media_interface_mb.vhd -- Thu Jun 10 09:40:51 2010\r
+\r
+--\r
+-- Notes: \r
+-- 1) This testbench template has been automatically generated using types\r
+-- std_logic and std_logic_vector for the ports of the unit under test.\r
+-- Lattice recommends that these types always be used for the top-level\r
+-- I/O of a design in order to guarantee that the testbench will bind\r
+-- correctly to the timing (post-route) simulation model.\r
+-- 2) To use this template as your testbench, change the filename to any\r
+-- name of your choice with the extension .vhd, and use the "source->import"\r
+-- menu in the ispLEVER Project Navigator to import the testbench.\r
+-- Then edit the user defined section below, adding code to generate the \r
+-- stimulus for your design.\r
+-- 3) VHDL simulations will produce errors if there are Lattice FPGA library \r
+-- elements in your design that require the instantiation of GSR, PUR, and\r
+-- TSALL and they are not present in the testbench. For more information see\r
+-- the How To section of online help. \r
+--\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT fifo_18x16_media_interface_mb\r
+ PORT(\r
+ Data : IN std_logic_vector(17 downto 0);\r
+ Clock : IN std_logic;\r
+ WrEn : IN std_logic;\r
+ RdEn : IN std_logic;\r
+ Reset : IN std_logic;\r
+ AmEmptySetThresh : IN std_logic_vector(3 downto 0);\r
+ AmEmptyClrThresh : IN std_logic_vector(3 downto 0);\r
+ AmFullSetThresh : IN std_logic_vector(3 downto 0);\r
+ AmFullClrThresh : IN std_logic_vector(3 downto 0); \r
+ Q : OUT std_logic_vector(17 downto 0);\r
+ WCNT : OUT std_logic_vector(4 downto 0);\r
+ Empty : OUT std_logic;\r
+ Full : OUT std_logic;\r
+ AlmostEmpty : OUT std_logic;\r
+ AlmostFull : OUT std_logic\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL Data : std_logic_vector(17 downto 0);\r
+ SIGNAL Clock : std_logic;\r
+ SIGNAL WrEn : std_logic;\r
+ SIGNAL RdEn : std_logic;\r
+ SIGNAL Reset : std_logic;\r
+ SIGNAL AmEmptySetThresh : std_logic_vector(3 downto 0);\r
+ SIGNAL AmEmptyClrThresh : std_logic_vector(3 downto 0);\r
+ SIGNAL AmFullSetThresh : std_logic_vector(3 downto 0);\r
+ SIGNAL AmFullClrThresh : std_logic_vector(3 downto 0);\r
+ SIGNAL Q : std_logic_vector(17 downto 0);\r
+ SIGNAL WCNT : std_logic_vector(4 downto 0);\r
+ SIGNAL Empty : std_logic;\r
+ SIGNAL Full : std_logic;\r
+ SIGNAL AlmostEmpty : std_logic;\r
+ SIGNAL AlmostFull : std_logic;\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: fifo_18x16_media_interface_mb PORT MAP(\r
+ Data => Data,\r
+ Clock => Clock,\r
+ WrEn => WrEn,\r
+ RdEn => RdEn,\r
+ Reset => Reset,\r
+ AmEmptySetThresh => AmEmptySetThresh,\r
+ AmEmptyClrThresh => AmEmptyClrThresh,\r
+ AmFullSetThresh => AmFullSetThresh,\r
+ AmFullClrThresh => AmFullClrThresh,\r
+ Q => Q,\r
+ WCNT => WCNT,\r
+ Empty => Empty,\r
+ Full => Full,\r
+ AlmostEmpty => AlmostEmpty,\r
+ AlmostFull => AlmostFull\r
+ );\r
+\r
+\r
+-- *** Test Bench - User Defined Section ***\r
+ tb : PROCESS\r
+ BEGIN\r
+ wait; -- will wait forever\r
+ END PROCESS;\r
+-- *** End Test Bench - User Defined Section ***\r
+\r
+END;\r
--- /dev/null
+REGIONSTART\r
+ADC1_REGION 244 62 105\r
+ADC0_REGION 24 112 247\r
+MEDIA_INTERFACE_REGION 255 5 21\r
+REGIONEND\r
+MODULESTART\r
+MODULEEND\r
+GROUPSTART\r
+THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/TRMBUF_group 31 3 232\r
+THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 18 30 234\r
+THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 72 239 143\r
+THE_IPU_STAGE/IPU_FIFO_STAGE_group 14 244 80\r
+THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 206 156 22\r
+THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 158 12 244\r
+THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 207 244 144\r
+THE_SLAVE_BUS/THE_SPI_MEMORY/SPI_group 239 12 62\r
+THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_group 67 247 139\r
+THE_ADC0_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group 153 213 239\r
+THE_ADC1_HANDLER/ADC_DATA_HANDLER_group 83 221 103\r
+THE_ADC1_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group 97 255 105\r
+THE_SLAVE_BUS/THE_BUS_HANDLER/Bus_handler_group 6 224 71\r
+THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group 28 219 174\r
+THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group 32 211 80\r
+THE_RICH_TRB/RICH_TRB_group 244 18 77\r
+THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 2 215 232\r
+THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 89 244 53\r
+THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group 68 64 242\r
+THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group 107 216 48\r
+THE_ADC0_HANDLER/ADC_DATA_HANDLER_group 176 211 153\r
+THE_ADC0_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group 44 224 126\r
+THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 97 205 219\r
+THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 229 192 255\r
+THE_ADC1_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group 131 239 87\r
+THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 212 159 212\r
+THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/API_group 150 245 69\r
+THE_SLAVE_BUS/THE_SPI_MASTER/SPI_group 36 242 13\r
+THE_APV_TRGCTRL/APV_TRG_CTRL_group 239 139 31\r
+THE_ADC0_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group 211 114 157\r
+THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 211 79 74\r
+THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 50 34 244\r
+THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group 18 204 50\r
+THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group 204 125 73\r
+THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group 244 79 20\r
+THE_ADC1_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group 45 237 142\r
+THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 44 83 232\r
+THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 120 129 219\r
+THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group 64 224 54\r
+THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 114 230 29\r
+THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/APV_RAW_BUF_group 252 217 29\r
+THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/RegIO_group 9 244 37\r
+THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/HUBLOGIC_group 93 234 203\r
+THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/API_group 19 13 252\r
+THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group 50 59 221\r
+THE_ADC0_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group 178 234 201\r
+THE_RICH_TRB/THE_MEDIA_INTERFACE/media_interface_group 246 34 145\r
+THE_ADC1_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group 191 20 214\r
+GROUPEND\r
--- /dev/null
+#-- Synplicity, Inc.\r
+#-- Version C-2009.03L-1\r
+#-- Project file I:\vhdl_pro\comp_adcmv3\lever\run_options.txt\r
+#-- Written on Fri Jun 18 10:31:11 2010\r
+\r
+\r
+#project files\r
+add_file -vhdl -lib work "X:/Programme/ispTOOLS_80/ispcpld/../cae_library/synthesis/vhdl/ecp2m.vhd"\r
+add_file -vhdl -lib work "../version.vhd"\r
+add_file -vhdl -lib work "../design/adcmv3_components.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"\r
+add_file -vhdl -lib work "../design/test_media.vhd"\r
+add_file -vhdl -lib work "../design/sbuf.vhd"\r
+add_file -vhdl -lib work "../design/sfp_rx_handler.vhd"\r
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"\r
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd"\r
+add_file -vhdl -lib work "../design/pulse_sync.vhd"\r
+add_file -vhdl -lib work "../design/apv_sync_handler.vhd"\r
+add_file -vhdl -lib work "../design/apv_trg_handler.vhd"\r
+add_file -vhdl -lib work "../design/eds_buffer_dpram.vhd"\r
+add_file -vhdl -lib work "../design/eds_buf.vhd"\r
+add_file -vhdl -lib work "../design/max_data.vhd"\r
+add_file -vhdl -lib work "../design/state_sync.vhd"\r
+add_file -vhdl -lib work "../design/real_trg_handler.vhd"\r
+add_file -vhdl -lib work "../design/pulse_stretch.vhd"\r
+add_file -vhdl -lib work "../design/apv_trgctrl.vhd"\r
+add_file -vhdl -lib work "../design/adc_channel_select.vhd"\r
+add_file -vhdl -lib work "../design/crossover.vhd"\r
+add_file -vhdl -lib work "../design/adc_crossover.vhd"\r
+add_file -vhdl -lib work "../design/adc_twochannels.vhd"\r
+add_file -vhdl -lib work "../design/adc_ch_in.vhd"\r
+add_file -vhdl -lib work "../design/adc_data_handler.vhd"\r
+add_file -vhdl -lib work "../design/frame_status_mem.vhd"\r
+add_file -vhdl -lib work "../design/input_bram.vhd"\r
+add_file -vhdl -lib work "../design/apv_raw_buffer.vhd"\r
+add_file -vhdl -lib work "../design/apv_lock_sm.vhd"\r
+add_file -vhdl -lib work "../design/apv_digital.vhd"\r
+add_file -vhdl -lib work "../design/apv_locker.vhd"\r
+add_file -vhdl -lib work "../design/raw_buf_stage.vhd"\r
+add_file -vhdl -lib work "../design/decoder_8bit.vhd"\r
+add_file -vhdl -lib work "../design/apv_pc_nc_alu.vhd"\r
+add_file -vhdl -lib work "../design/buf_toc.vhd"\r
+add_file -vhdl -lib work "../design/ref_row_sel.vhd"\r
+add_file -vhdl -lib work "../design/frmctr_check.vhd"\r
+add_file -vhdl -lib work "../design/ped_corr_ctrl.vhd"\r
+add_file -vhdl -lib work "../design/adc_apv_map_mem.vhd"\r
+add_file -vhdl -lib work "../design/fifo_1kx18.vhd"\r
+add_file -vhdl -lib work "../design/fifo_2kx27.vhd"\r
+add_file -vhdl -lib work "../design/ipu_fifo_stage.vhd"\r
+add_file -vhdl -lib work "../design/slv_register.vhd"\r
+add_file -vhdl -lib work "../design/adc_snoop_mem.vhd"\r
+add_file -vhdl -lib work "../design/slv_adc_snoop.vhd"\r
+add_file -vhdl -lib work "../design/slv_half_register.vhd"\r
+add_file -vhdl -lib work "../design/slv_status.vhd"\r
+add_file -vhdl -lib work "../design/slv_status_bank.vhd"\r
+add_file -vhdl -lib work "../design/apv_adc_map_mem.vhd"\r
+add_file -vhdl -lib work "../design/slv_register_bank.vhd"\r
+add_file -vhdl -lib work "../design/spi_real_slim.vhd"\r
+add_file -vhdl -lib work "../design/spi_adc_master.vhd"\r
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd"\r
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"\r
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"\r
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"\r
+add_file -vhdl -lib work "../design/slv_onewire_dpram.vhd"\r
+add_file -vhdl -lib work "../design/onewire_master.vhd"\r
+add_file -vhdl -lib work "../design/onewire_spare_one.vhd"\r
+add_file -vhdl -lib work "../design/adc_onewire_map_mem.vhd"\r
+add_file -vhdl -lib work "../design/slv_onewire_memory.vhd"\r
+add_file -vhdl -lib work "../design/i2c_gstart.vhd"\r
+add_file -vhdl -lib work "../design/i2c_sendb.vhd"\r
+add_file -vhdl -lib work "../design/i2c_slim.vhd"\r
+add_file -vhdl -lib work "../design/i2c_master.vhd"\r
+add_file -vhdl -lib work "../design/ped_thr_true.vhd"\r
+add_file -vhdl -lib work "../design/slv_ped_thr_mem.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"\r
+add_file -vhdl -lib work "../design/slave_bus.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"\r
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"\r
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"\r
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"\r
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"\r
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"\r
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd"\r
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd"\r
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"\r
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd"\r
+add_file -vhdl -lib work "../design/rich_trb.vhd"\r
+add_file -vhdl -lib work "../design/sync_pll_40m.vhd"\r
+add_file -vhdl -lib work "../design/dll_100m.vhd"\r
+add_file -vhdl -lib work "../design/pll_40m.vhd"\r
+add_file -vhdl -lib work "../design/reboot_handler.vhd"\r
+add_file -vhdl -lib work "../design/reset_handler.vhd"\r
+add_file -vhdl -lib work "../design/adcmv3.vhd"\r
+\r
+\r
+#implementation: "lever"\r
+impl -add lever -type fpga\r
+\r
+#device options\r
+set_option -technology LATTICE-ecp2m\r
+set_option -part LFE2M100E\r
+set_option -package F900C\r
+set_option -speed_grade -6\r
+set_option -part_companion ""\r
+\r
+#compilation/mapping options\r
+set_option -top_module "sbuf"\r
+\r
+# sequential_optimization_options\r
+set_option -symbolic_fsm_compiler 1\r
+\r
+# Compiler Options\r
+set_option -compiler_compatible 1\r
+set_option -resource_sharing 1\r
+\r
+# mapper_options\r
+set_option -frequency 200\r
+set_option -auto_constrain_io 1\r
+set_option -write_verilog 1\r
+set_option -write_vhdl 1\r
+\r
+# Lattice XP\r
+set_option -maxfan 100\r
+set_option -disable_io_insertion 0\r
+set_option -retiming 0\r
+set_option -pipe 0\r
+set_option -forcegsr false\r
+set_option -fixgatedclocks 3\r
+set_option -fixgeneratedclocks 3\r
+set_option -update_models_cp 1\r
+\r
+#automatic place and route (vendor) options\r
+set_option -write_apr_constraint 0\r
+\r
+#set result format/file last\r
+project -result_file "./sbuf.edi"\r
+\r
+#set log file \r
+set_option log_file "I:/vhdl_pro/comp_adcmv3/lever/sbuf.srf" \r
+\r
+#\r
+#implementation attributes\r
+\r
+set_option -vlog_std v2001\r
+set_option -num_critical_paths 3\r
+set_option -num_startend_points 0\r
+impl -active "lever"\r
--- /dev/null
+STYFILENAME: adcmv3.sty\r
+PROJECT: sbuf\r
+WORKING_PATH: "i:/vhdl_pro/comp_adcmv3/lever"\r
+MODULE: work.sbuf\r
+VHDL_FILE_LIST: "X:/Programme/ispTOOLS_80/ispcpld/../cae_library/synthesis/vhdl/ecp2m.vhd" ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/test_media.vhd ../design/sbuf.vhd ../design/sfp_rx_handler.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd\r
+OUTPUT_FILE_NAME: sbuf\r
+SUFFIX_NAME: edi\r
+WRITE_PRF: false\r
+FREQUENCY: 200\r
+FANOUT_LIMIT: 100\r
+DISABLE_IO_INSERTION: false\r
+FORCE_GSR: false\r
+SPEED_GRADE: -6\r
+SYMBOLIC_FSM_COMPILER: true\r
+NUM_CRITICAL_PATHS: 3\r
+AUTO_CONSTRAIN_IO: true\r
+NUM_STARTEND_POINTS: 0\r
+COMPILER_COMPATIBLE: true\r
+RETIMING: none\r
+RESOURCE_SHARING: true\r
+DEFAULT_ENUM_ENCODING: default\r
+fixgatedclocks: 3\r
+fixgeneratedclocks: 3\r
+Vlog_std_v2001: V2001\r
+DUP: false\r
+ARRANGE_VHDL_FILES: true\r
--- /dev/null
+(edif sbuf\r
+ (edifVersion 2 0 0)\r
+ (edifLevel 0)\r
+ (keywordMap (keywordLevel 0))\r
+ (status\r
+ (written\r
+ (timeStamp 2010 6 18 10 31 23)\r
+ (author "Synplicity, Inc.")\r
+ (program "Synplify Pro" (version "C-2009.03L-1, mapper map400lat, Build 146R"))\r
+ )\r
+ )\r
+ (library LUCENT\r
+ (edifLevel 0)\r
+ (technology (numberDefinition ))\r
+ (cell OB (cellType GENERIC)\r
+ (view PRIM (viewType NETLIST)\r
+ (interface\r
+ (port I (direction INPUT))\r
+ (port O (direction OUTPUT))\r
+ )\r
+ )\r
+ )\r
+ (cell IB (cellType GENERIC)\r
+ (view PRIM (viewType NETLIST)\r
+ (interface\r
+ (port I (direction INPUT))\r
+ (port O (direction OUTPUT))\r
+ )\r
+ )\r
+ )\r
+ (cell FD1S3IX (cellType GENERIC)\r
+ (view PRIM (viewType NETLIST)\r
+ (interface\r
+ (port D (direction INPUT))\r
+ (port CK (direction INPUT))\r
+ (port CD (direction INPUT))\r
+ (port Q (direction OUTPUT))\r
+ )\r
+ )\r
+ )\r
+ (cell FD1P3IX (cellType GENERIC)\r
+ (view PRIM (viewType NETLIST)\r
+ (interface\r
+ (port D (direction INPUT))\r
+ (port SP (direction INPUT))\r
+ (port CK (direction INPUT))\r
+ (port CD (direction INPUT))\r
+ (port Q (direction OUTPUT))\r
+ )\r
+ )\r
+ )\r
+ (cell OFS1P3DX (cellType GENERIC)\r
+ (view PRIM (viewType NETLIST)\r
+ (interface\r
+ (port D (direction INPUT))\r
+ (port SP (direction INPUT))\r
+ (port SCLK (direction INPUT))\r
+ (port CD (direction INPUT))\r
+ (port Q (direction OUTPUT))\r
+ )\r
+ )\r
+ )\r
+ (cell FD1P3AX (cellType GENERIC)\r
+ (view PRIM (viewType NETLIST)\r
+ (interface\r
+ (port D (direction INPUT))\r
+ (port SP (direction INPUT))\r
+ (port CK (direction INPUT))\r
+ (port Q (direction OUTPUT))\r
+ )\r
+ )\r
+ )\r
+ (cell ORCALUT4 (cellType GENERIC)\r
+ (view PRIM (viewType NETLIST)\r
+ (interface\r
+ (port A (direction INPUT))\r
+ (port B (direction INPUT))\r
+ (port C (direction INPUT))\r
+ (port D (direction INPUT))\r
+ (port Z (direction OUTPUT))\r
+ )\r
+ )\r
+ )\r
+ (cell PUR (cellType GENERIC)\r
+ (view PRIM (viewType NETLIST)\r
+ (interface\r
+ (port PUR (direction INPUT))\r
+ )\r
+ )\r
+ )\r
+ (cell GSR (cellType GENERIC)\r
+ (view PRIM (viewType NETLIST)\r
+ (interface\r
+ (port GSR (direction INPUT))\r
+ )\r
+ )\r
+ )\r
+ (cell VHI (cellType GENERIC)\r
+ (view PRIM (viewType NETLIST)\r
+ (interface\r
+ (port Z (direction OUTPUT))\r
+ )\r
+ )\r
+ )\r
+ (cell VLO (cellType GENERIC)\r
+ (view PRIM (viewType NETLIST)\r
+ (interface\r
+ (port Z (direction OUTPUT))\r
+ )\r
+ )\r
+ )\r
+ )\r
+ (library work\r
+ (edifLevel 0)\r
+ (technology (numberDefinition ))\r
+ (cell sbuf (cellType GENERIC)\r
+ (view sbuf_arch (viewType NETLIST)\r
+ (interface\r
+ (port CLK (direction INPUT)\r
+ )\r
+ (port RESET (direction INPUT))\r
+ (port CLK_EN (direction INPUT))\r
+ (port COMB_DATAREADY_IN (direction INPUT))\r
+ (port COMB_next_READ_OUT (direction OUTPUT))\r
+ (port COMB_READ_IN (direction INPUT))\r
+ (port (array (rename comb_data_in "COMB_DATA_IN(17:0)") 18) (direction INPUT))\r
+ (port SYN_DATAREADY_OUT (direction OUTPUT))\r
+ (port (array (rename syn_data_out "SYN_DATA_OUT(17:0)") 18) (direction OUTPUT))\r
+ (port SYN_READ_IN (direction INPUT))\r
+ (port STAT_BUFFER (direction OUTPUT))\r
+ )\r
+ (contents\r
+ (instance PUR_INST (viewRef PRIM (cellRef PUR (libraryRef LUCENT)))\r
+ )\r
+ (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))\r
+ )\r
+ (instance VCC_0 (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) )\r
+ (instance GND_0 (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) )\r
+ (instance current_got_overflow_fb (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(B+A)"))\r
+ )\r
+ (instance current_b2_buffer_0io_0 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_1 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_2 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_3 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_4 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_5 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_6 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_7 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_8 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_9 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_10 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_11 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_12 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_13 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_14 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_15 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_16 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b2_buffer_0io_17 (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_next_READ_OUT (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_got_overflow (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_buffer_state_0 (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_buffer_state_fast_1 (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_buffer_state_1 (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_0 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_1 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_3 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_4 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_5 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_6 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_7 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_8 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_9 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_10 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_11 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_12 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_13 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_14 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_15 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_16 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_b1_buffer_17 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))\r
+ )\r
+ (instance current_SYN_DATAREADY_OUT (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))\r
+ )\r
+ (instance STAT_BUFFER_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_READ_IN_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_17 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_16 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_15 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_14 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_13 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_12 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_11 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_10 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_9 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_8 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_7 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_6 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_5 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_4 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_3 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_2 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_1 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATA_OUT_pad_0 (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance SYN_DATAREADY_OUT_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_17 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_16 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_15 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_14 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_13 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_12 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_11 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_10 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_9 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_8 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_7 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_6 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_5 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_4 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_3 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_2 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_1 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_DATA_IN_pad_0 (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_READ_IN_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance COMB_next_READ_OUT_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )\r
+ (instance COMB_DATAREADY_IN_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance CLK_EN_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance RESET_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance CLK_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )\r
+ (instance combined_COMB_DATAREADY_IN_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(B A)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_9 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_12 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_13 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_14 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_15 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_16 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance current_b2_buffer_0io_RNO_17 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C A+C B)"))\r
+ )\r
+ (instance move_b1_buffer_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!D (C (B !A))+D (C+A))"))\r
+ )\r
+ (instance un1_current_buffer_state46_2_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(D (C (!B A)))"))\r
+ )\r
+ (instance move_b2_buffer_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!D (!C B+C (B A))+D A)"))\r
+ )\r
+ (instance current_buffer_state_ns_1_0__m7_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!D (C (B !A))+D (!C (B+!A)))"))\r
+ )\r
+ (instance current_buffer_state_ns_1_0__N_6_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!D (!C B+C (!B !A+B A))+D (C+(!B A)))"))\r
+ )\r
+ (instance current_next_READ_OUT_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!D (C !A)+D (!C (B+!A)+C !A))"))\r
+ )\r
+ (instance current_next_READ_OUT_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C (!B A)+C (!B+!A))"))\r
+ )\r
+ (instance current_buffer_state_ns_1_0__m7_0_fast (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!D (C (B !A))+D (!C (B+!A)))"))\r
+ )\r
+ (instance COMB_next_READ_OUT_pad_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!C (!B+!A)+C !A)"))\r
+ )\r
+ (instance COMB_next_READ_OUT_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!D (B !A)+D (!C+(B+A)))"))\r
+ )\r
+ (instance current_SYN_DATAREADY_OUT_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!D (!C !B+C A))"))\r
+ )\r
+ (instance current_SYN_DATAREADY_OUT_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))\r
+ (property lut_function (string "(!D (!C (!B A)+C A)+D (C+(!B+!A)))"))\r
+ )\r
+ (net current_next_READ_OUT_1 (joined\r
+ (portRef D (instanceRef COMB_next_READ_OUT_pad_RNO))\r
+ (portRef C (instanceRef COMB_next_READ_OUT_pad_RNO_0))\r
+ (portRef C (instanceRef current_next_READ_OUT_RNO))\r
+ (portRef Q (instanceRef current_next_READ_OUT))\r
+ )\r
+ )\r
+ (net buf_SYN_READ_IN (joined\r
+ (portRef A (instanceRef current_SYN_DATAREADY_OUT_RNO_0))\r
+ (portRef B (instanceRef COMB_next_READ_OUT_pad_RNO))\r
+ (portRef A (instanceRef current_buffer_state_ns_1_0__m7_0_fast))\r
+ (portRef A (instanceRef current_next_READ_OUT_RNO_0))\r
+ (portRef A (instanceRef current_buffer_state_ns_1_0__N_6_i))\r
+ (portRef A (instanceRef current_buffer_state_ns_1_0__m7_0))\r
+ (portRef A (instanceRef move_b2_buffer_i))\r
+ (portRef B (instanceRef un1_current_buffer_state46_2_0_a3))\r
+ (portRef A (instanceRef move_b1_buffer_i))\r
+ (portRef O (instanceRef SYN_READ_IN_pad))\r
+ )\r
+ )\r
+ (net combined_COMB_DATAREADY_IN (joined\r
+ (portRef C (instanceRef current_SYN_DATAREADY_OUT_RNO))\r
+ (portRef B (instanceRef current_buffer_state_ns_1_0__m7_0_fast))\r
+ (portRef B (instanceRef current_next_READ_OUT_RNO_0))\r
+ (portRef B (instanceRef current_buffer_state_ns_1_0__N_6_i))\r
+ (portRef B (instanceRef current_buffer_state_ns_1_0__m7_0))\r
+ (portRef B (instanceRef move_b2_buffer_i))\r
+ (portRef C (instanceRef un1_current_buffer_state46_2_0_a3))\r
+ (portRef B (instanceRef move_b1_buffer_i))\r
+ (portRef Z (instanceRef combined_COMB_DATAREADY_IN_1))\r
+ )\r
+ )\r
+ (net current_b1_buffer_0 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_0))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_0))\r
+ ))\r
+ (net current_b1_buffer_1 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_1))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_1))\r
+ ))\r
+ (net current_b1_buffer_2 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_2))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_2))\r
+ ))\r
+ (net current_b1_buffer_3 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_3))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_3))\r
+ ))\r
+ (net current_b1_buffer_4 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_4))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_4))\r
+ ))\r
+ (net current_b1_buffer_5 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_5))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_5))\r
+ ))\r
+ (net current_b1_buffer_6 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_6))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_6))\r
+ ))\r
+ (net current_b1_buffer_7 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_7))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_7))\r
+ ))\r
+ (net current_b1_buffer_8 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_8))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_8))\r
+ ))\r
+ (net current_b1_buffer_9 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_9))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_9))\r
+ ))\r
+ (net current_b1_buffer_10 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_10))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_10))\r
+ ))\r
+ (net current_b1_buffer_11 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_11))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_11))\r
+ ))\r
+ (net current_b1_buffer_12 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_12))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_12))\r
+ ))\r
+ (net current_b1_buffer_13 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_13))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_13))\r
+ ))\r
+ (net current_b1_buffer_14 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_14))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_14))\r
+ ))\r
+ (net current_b1_buffer_15 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_15))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_15))\r
+ ))\r
+ (net current_b1_buffer_16 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_16))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_16))\r
+ ))\r
+ (net current_b1_buffer_17 (joined\r
+ (portRef Q (instanceRef current_b1_buffer_17))\r
+ (portRef B (instanceRef current_b2_buffer_0io_RNO_17))\r
+ ))\r
+ (net current_buffer_state_0 (joined\r
+ (portRef Q (instanceRef current_buffer_state_0))\r
+ (portRef C (instanceRef current_SYN_DATAREADY_OUT_RNO_0))\r
+ (portRef C (instanceRef COMB_next_READ_OUT_pad_RNO))\r
+ (portRef C (instanceRef current_buffer_state_ns_1_0__m7_0_fast))\r
+ (portRef C (instanceRef current_next_READ_OUT_RNO_0))\r
+ (portRef C (instanceRef current_buffer_state_ns_1_0__N_6_i))\r
+ (portRef C (instanceRef current_buffer_state_ns_1_0__m7_0))\r
+ (portRef C (instanceRef move_b2_buffer_i))\r
+ (portRef C (instanceRef move_b1_buffer_i))\r
+ ))\r
+ (net current_buffer_state_1 (joined\r
+ (portRef Q (instanceRef current_buffer_state_1))\r
+ (portRef D (instanceRef current_SYN_DATAREADY_OUT_RNO_0))\r
+ (portRef D (instanceRef current_next_READ_OUT_RNO_0))\r
+ (portRef D (instanceRef current_buffer_state_ns_1_0__N_6_i))\r
+ (portRef D (instanceRef current_buffer_state_ns_1_0__m7_0))\r
+ (portRef D (instanceRef move_b2_buffer_i))\r
+ (portRef D (instanceRef un1_current_buffer_state46_2_0_a3))\r
+ (portRef D (instanceRef move_b1_buffer_i))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_17))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_16))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_15))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_14))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_13))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_12))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_11))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_10))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_9))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_8))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_7))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_6))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_5))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_4))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_3))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_2))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_1))\r
+ (portRef C (instanceRef current_b2_buffer_0io_RNO_0))\r
+ ))\r
+ (net un1_current_buffer_state46_2_0_a3 (joined\r
+ (portRef Z (instanceRef un1_current_buffer_state46_2_0_a3))\r
+ (portRef A (instanceRef current_got_overflow_fb))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_0 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_0))\r
+ (portRef D (instanceRef current_b2_buffer_0io_0))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_1 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_1))\r
+ (portRef D (instanceRef current_b2_buffer_0io_1))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_2 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_2))\r
+ (portRef D (instanceRef current_b2_buffer_0io_2))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_3 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_3))\r
+ (portRef D (instanceRef current_b2_buffer_0io_3))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_4 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_4))\r
+ (portRef D (instanceRef current_b2_buffer_0io_4))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_5 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_5))\r
+ (portRef D (instanceRef current_b2_buffer_0io_5))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_6 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_6))\r
+ (portRef D (instanceRef current_b2_buffer_0io_6))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_7 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_7))\r
+ (portRef D (instanceRef current_b2_buffer_0io_7))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_8 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_8))\r
+ (portRef D (instanceRef current_b2_buffer_0io_8))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_9 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_9))\r
+ (portRef D (instanceRef current_b2_buffer_0io_9))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_10 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_10))\r
+ (portRef D (instanceRef current_b2_buffer_0io_10))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_11 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_11))\r
+ (portRef D (instanceRef current_b2_buffer_0io_11))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_12 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_12))\r
+ (portRef D (instanceRef current_b2_buffer_0io_12))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_13 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_13))\r
+ (portRef D (instanceRef current_b2_buffer_0io_13))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_14 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_14))\r
+ (portRef D (instanceRef current_b2_buffer_0io_14))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_15 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_15))\r
+ (portRef D (instanceRef current_b2_buffer_0io_15))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_16 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_16))\r
+ (portRef D (instanceRef current_b2_buffer_0io_16))\r
+ ))\r
+ (net current_b2_buffer_0io_RNO_17 (joined\r
+ (portRef Z (instanceRef current_b2_buffer_0io_RNO_17))\r
+ (portRef D (instanceRef current_b2_buffer_0io_17))\r
+ ))\r
+ (net move_b1_buffer (joined\r
+ (portRef Z (instanceRef move_b1_buffer_i))\r
+ (portRef SP (instanceRef current_b1_buffer_17))\r
+ (portRef SP (instanceRef current_b1_buffer_16))\r
+ (portRef SP (instanceRef current_b1_buffer_15))\r
+ (portRef SP (instanceRef current_b1_buffer_14))\r
+ (portRef SP (instanceRef current_b1_buffer_13))\r
+ (portRef SP (instanceRef current_b1_buffer_12))\r
+ (portRef SP (instanceRef current_b1_buffer_11))\r
+ (portRef SP (instanceRef current_b1_buffer_10))\r
+ (portRef SP (instanceRef current_b1_buffer_9))\r
+ (portRef SP (instanceRef current_b1_buffer_8))\r
+ (portRef SP (instanceRef current_b1_buffer_7))\r
+ (portRef SP (instanceRef current_b1_buffer_6))\r
+ (portRef SP (instanceRef current_b1_buffer_5))\r
+ (portRef SP (instanceRef current_b1_buffer_4))\r
+ (portRef SP (instanceRef current_b1_buffer_3))\r
+ (portRef SP (instanceRef current_b1_buffer_2))\r
+ (portRef SP (instanceRef current_b1_buffer_1))\r
+ (portRef SP (instanceRef current_b1_buffer_0))\r
+ ))\r
+ (net move_b2_buffer (joined\r
+ (portRef Z (instanceRef move_b2_buffer_i))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_17))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_16))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_15))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_14))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_13))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_12))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_11))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_10))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_9))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_8))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_7))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_6))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_5))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_4))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_3))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_2))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_1))\r
+ (portRef SP (instanceRef current_b2_buffer_0io_0))\r
+ ))\r
+ (net current_buffer_state_ns_1 (joined\r
+ (portRef Z (instanceRef current_buffer_state_ns_1_0__m7_0))\r
+ (portRef D (instanceRef current_buffer_state_1))\r
+ ))\r
+ (net current_buffer_state_ns_1_0__N_6_i (joined\r
+ (portRef Z (instanceRef current_buffer_state_ns_1_0__N_6_i))\r
+ (portRef D (instanceRef current_buffer_state_0))\r
+ ))\r
+ (net N_313_i (joined\r
+ (portRef Z (instanceRef current_SYN_DATAREADY_OUT_RNO))\r
+ (portRef D (instanceRef current_SYN_DATAREADY_OUT))\r
+ ))\r
+ (net N_311_i (joined\r
+ (portRef Z (instanceRef current_next_READ_OUT_RNO))\r
+ (portRef D (instanceRef current_next_READ_OUT))\r
+ ))\r
+ (net N_311_i_1 (joined\r
+ (portRef Z (instanceRef current_next_READ_OUT_RNO_0))\r
+ (portRef B (instanceRef current_next_READ_OUT_RNO))\r
+ ))\r
+ (net current_buffer_state_fast_1 (joined\r
+ (portRef Q (instanceRef current_buffer_state_fast_1))\r
+ (portRef B (instanceRef COMB_next_READ_OUT_pad_RNO_0))\r
+ (portRef D (instanceRef current_buffer_state_ns_1_0__m7_0_fast))\r
+ ))\r
+ (net current_buffer_state_ns_fast_1 (joined\r
+ (portRef Z (instanceRef current_buffer_state_ns_1_0__m7_0_fast))\r
+ (portRef D (instanceRef current_buffer_state_fast_1))\r
+ ))\r
+ (net G_4_i_m2_1 (joined\r
+ (portRef Z (instanceRef COMB_next_READ_OUT_pad_RNO_0))\r
+ (portRef A (instanceRef COMB_next_READ_OUT_pad_RNO))\r
+ ))\r
+ (net N_313_i_1_0 (joined\r
+ (portRef Z (instanceRef current_SYN_DATAREADY_OUT_RNO_0))\r
+ (portRef B (instanceRef current_SYN_DATAREADY_OUT_RNO))\r
+ ))\r
+ (net GND (joined\r
+ (portRef Z (instanceRef GND_0))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_17))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_16))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_15))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_14))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_13))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_12))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_11))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_10))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_9))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_8))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_7))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_6))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_5))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_4))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_3))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_2))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_1))\r
+ (portRef CD (instanceRef current_b2_buffer_0io_0))\r
+ ))\r
+ (net VCC (joined\r
+ (portRef Z (instanceRef VCC_0))\r
+ (portRef GSR (instanceRef GSR_INST))\r
+ (portRef PUR (instanceRef PUR_INST))\r
+ ))\r
+ (net CLK_c (joined\r
+ (portRef O (instanceRef CLK_pad))\r
+ (portRef CK (instanceRef current_SYN_DATAREADY_OUT))\r
+ (portRef CK (instanceRef current_b1_buffer_17))\r
+ (portRef CK (instanceRef current_b1_buffer_16))\r
+ (portRef CK (instanceRef current_b1_buffer_15))\r
+ (portRef CK (instanceRef current_b1_buffer_14))\r
+ (portRef CK (instanceRef current_b1_buffer_13))\r
+ (portRef CK (instanceRef current_b1_buffer_12))\r
+ (portRef CK (instanceRef current_b1_buffer_11))\r
+ (portRef CK (instanceRef current_b1_buffer_10))\r
+ (portRef CK (instanceRef current_b1_buffer_9))\r
+ (portRef CK (instanceRef current_b1_buffer_8))\r
+ (portRef CK (instanceRef current_b1_buffer_7))\r
+ (portRef CK (instanceRef current_b1_buffer_6))\r
+ (portRef CK (instanceRef current_b1_buffer_5))\r
+ (portRef CK (instanceRef current_b1_buffer_4))\r
+ (portRef CK (instanceRef current_b1_buffer_3))\r
+ (portRef CK (instanceRef current_b1_buffer_2))\r
+ (portRef CK (instanceRef current_b1_buffer_1))\r
+ (portRef CK (instanceRef current_b1_buffer_0))\r
+ (portRef CK (instanceRef current_buffer_state_1))\r
+ (portRef CK (instanceRef current_buffer_state_fast_1))\r
+ (portRef CK (instanceRef current_buffer_state_0))\r
+ (portRef CK (instanceRef current_got_overflow))\r
+ (portRef CK (instanceRef current_next_READ_OUT))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_17))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_16))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_15))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_14))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_13))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_12))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_11))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_10))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_9))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_8))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_7))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_6))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_5))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_4))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_3))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_2))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_1))\r
+ (portRef SCLK (instanceRef current_b2_buffer_0io_0))\r
+ ))\r
+ (net CLK (joined\r
+ (portRef CLK)\r
+ (portRef I (instanceRef CLK_pad))\r
+ ))\r
+ (net RESET_c (joined\r
+ (portRef O (instanceRef RESET_pad))\r
+ (portRef CD (instanceRef current_SYN_DATAREADY_OUT))\r
+ (portRef CD (instanceRef current_buffer_state_1))\r
+ (portRef CD (instanceRef current_buffer_state_fast_1))\r
+ (portRef CD (instanceRef current_buffer_state_0))\r
+ (portRef CD (instanceRef current_got_overflow))\r
+ (portRef CD (instanceRef current_next_READ_OUT))\r
+ ))\r
+ (net RESET (joined\r
+ (portRef RESET)\r
+ (portRef I (instanceRef RESET_pad))\r
+ ))\r
+ (net CLK_EN_c (joined\r
+ (portRef O (instanceRef CLK_EN_pad))\r
+ (portRef A (instanceRef current_SYN_DATAREADY_OUT_RNO))\r
+ (portRef A (instanceRef current_next_READ_OUT_RNO))\r
+ (portRef A (instanceRef un1_current_buffer_state46_2_0_a3))\r
+ (portRef SP (instanceRef current_buffer_state_1))\r
+ (portRef SP (instanceRef current_buffer_state_fast_1))\r
+ (portRef SP (instanceRef current_buffer_state_0))\r
+ ))\r
+ (net CLK_EN (joined\r
+ (portRef CLK_EN)\r
+ (portRef I (instanceRef CLK_EN_pad))\r
+ ))\r
+ (net COMB_DATAREADY_IN_c (joined\r
+ (portRef O (instanceRef COMB_DATAREADY_IN_pad))\r
+ (portRef A (instanceRef combined_COMB_DATAREADY_IN_1))\r
+ ))\r
+ (net COMB_DATAREADY_IN (joined\r
+ (portRef COMB_DATAREADY_IN)\r
+ (portRef I (instanceRef COMB_DATAREADY_IN_pad))\r
+ ))\r
+ (net COMB_next_READ_OUT_c (joined\r
+ (portRef Z (instanceRef COMB_next_READ_OUT_pad_RNO))\r
+ (portRef I (instanceRef COMB_next_READ_OUT_pad))\r
+ ))\r
+ (net COMB_next_READ_OUT (joined\r
+ (portRef O (instanceRef COMB_next_READ_OUT_pad))\r
+ (portRef COMB_next_READ_OUT)\r
+ ))\r
+ (net COMB_READ_IN_c (joined\r
+ (portRef O (instanceRef COMB_READ_IN_pad))\r
+ (portRef B (instanceRef combined_COMB_DATAREADY_IN_1))\r
+ ))\r
+ (net COMB_READ_IN (joined\r
+ (portRef COMB_READ_IN)\r
+ (portRef I (instanceRef COMB_READ_IN_pad))\r
+ ))\r
+ (net COMB_DATA_IN_c_0 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_0))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_0))\r
+ (portRef D (instanceRef current_b1_buffer_0))\r
+ ))\r
+ (net COMB_DATA_IN_0 (joined\r
+ (portRef (member comb_data_in 17))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_0))\r
+ ))\r
+ (net COMB_DATA_IN_c_1 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_1))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_1))\r
+ (portRef D (instanceRef current_b1_buffer_1))\r
+ ))\r
+ (net COMB_DATA_IN_1 (joined\r
+ (portRef (member comb_data_in 16))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_1))\r
+ ))\r
+ (net COMB_DATA_IN_c_2 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_2))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_2))\r
+ (portRef D (instanceRef current_b1_buffer_2))\r
+ ))\r
+ (net COMB_DATA_IN_2 (joined\r
+ (portRef (member comb_data_in 15))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_2))\r
+ ))\r
+ (net COMB_DATA_IN_c_3 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_3))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_3))\r
+ (portRef D (instanceRef current_b1_buffer_3))\r
+ ))\r
+ (net COMB_DATA_IN_3 (joined\r
+ (portRef (member comb_data_in 14))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_3))\r
+ ))\r
+ (net COMB_DATA_IN_c_4 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_4))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_4))\r
+ (portRef D (instanceRef current_b1_buffer_4))\r
+ ))\r
+ (net COMB_DATA_IN_4 (joined\r
+ (portRef (member comb_data_in 13))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_4))\r
+ ))\r
+ (net COMB_DATA_IN_c_5 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_5))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_5))\r
+ (portRef D (instanceRef current_b1_buffer_5))\r
+ ))\r
+ (net COMB_DATA_IN_5 (joined\r
+ (portRef (member comb_data_in 12))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_5))\r
+ ))\r
+ (net COMB_DATA_IN_c_6 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_6))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_6))\r
+ (portRef D (instanceRef current_b1_buffer_6))\r
+ ))\r
+ (net COMB_DATA_IN_6 (joined\r
+ (portRef (member comb_data_in 11))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_6))\r
+ ))\r
+ (net COMB_DATA_IN_c_7 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_7))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_7))\r
+ (portRef D (instanceRef current_b1_buffer_7))\r
+ ))\r
+ (net COMB_DATA_IN_7 (joined\r
+ (portRef (member comb_data_in 10))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_7))\r
+ ))\r
+ (net COMB_DATA_IN_c_8 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_8))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_8))\r
+ (portRef D (instanceRef current_b1_buffer_8))\r
+ ))\r
+ (net COMB_DATA_IN_8 (joined\r
+ (portRef (member comb_data_in 9))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_8))\r
+ ))\r
+ (net COMB_DATA_IN_c_9 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_9))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_9))\r
+ (portRef D (instanceRef current_b1_buffer_9))\r
+ ))\r
+ (net COMB_DATA_IN_9 (joined\r
+ (portRef (member comb_data_in 8))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_9))\r
+ ))\r
+ (net COMB_DATA_IN_c_10 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_10))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_10))\r
+ (portRef D (instanceRef current_b1_buffer_10))\r
+ ))\r
+ (net COMB_DATA_IN_10 (joined\r
+ (portRef (member comb_data_in 7))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_10))\r
+ ))\r
+ (net COMB_DATA_IN_c_11 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_11))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_11))\r
+ (portRef D (instanceRef current_b1_buffer_11))\r
+ ))\r
+ (net COMB_DATA_IN_11 (joined\r
+ (portRef (member comb_data_in 6))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_11))\r
+ ))\r
+ (net COMB_DATA_IN_c_12 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_12))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_12))\r
+ (portRef D (instanceRef current_b1_buffer_12))\r
+ ))\r
+ (net COMB_DATA_IN_12 (joined\r
+ (portRef (member comb_data_in 5))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_12))\r
+ ))\r
+ (net COMB_DATA_IN_c_13 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_13))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_13))\r
+ (portRef D (instanceRef current_b1_buffer_13))\r
+ ))\r
+ (net COMB_DATA_IN_13 (joined\r
+ (portRef (member comb_data_in 4))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_13))\r
+ ))\r
+ (net COMB_DATA_IN_c_14 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_14))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_14))\r
+ (portRef D (instanceRef current_b1_buffer_14))\r
+ ))\r
+ (net COMB_DATA_IN_14 (joined\r
+ (portRef (member comb_data_in 3))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_14))\r
+ ))\r
+ (net COMB_DATA_IN_c_15 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_15))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_15))\r
+ (portRef D (instanceRef current_b1_buffer_15))\r
+ ))\r
+ (net COMB_DATA_IN_15 (joined\r
+ (portRef (member comb_data_in 2))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_15))\r
+ ))\r
+ (net COMB_DATA_IN_c_16 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_16))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_16))\r
+ (portRef D (instanceRef current_b1_buffer_16))\r
+ ))\r
+ (net COMB_DATA_IN_16 (joined\r
+ (portRef (member comb_data_in 1))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_16))\r
+ ))\r
+ (net COMB_DATA_IN_c_17 (joined\r
+ (portRef O (instanceRef COMB_DATA_IN_pad_17))\r
+ (portRef A (instanceRef current_b2_buffer_0io_RNO_17))\r
+ (portRef D (instanceRef current_b1_buffer_17))\r
+ ))\r
+ (net COMB_DATA_IN_17 (joined\r
+ (portRef (member comb_data_in 0))\r
+ (portRef I (instanceRef COMB_DATA_IN_pad_17))\r
+ ))\r
+ (net current_SYN_DATAREADY_OUT_1 (joined\r
+ (portRef D (instanceRef current_SYN_DATAREADY_OUT_RNO))\r
+ (portRef B (instanceRef current_SYN_DATAREADY_OUT_RNO_0))\r
+ (portRef A (instanceRef COMB_next_READ_OUT_pad_RNO_0))\r
+ (portRef I (instanceRef SYN_DATAREADY_OUT_pad))\r
+ (portRef Q (instanceRef current_SYN_DATAREADY_OUT))\r
+ )\r
+ )\r
+ (net SYN_DATAREADY_OUT (joined\r
+ (portRef O (instanceRef SYN_DATAREADY_OUT_pad))\r
+ (portRef SYN_DATAREADY_OUT)\r
+ ))\r
+ (net SYN_DATA_OUT_c_0 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_0))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_0))\r
+ ))\r
+ (net SYN_DATA_OUT_0 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_0))\r
+ (portRef (member syn_data_out 17))\r
+ ))\r
+ (net SYN_DATA_OUT_c_1 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_1))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_1))\r
+ ))\r
+ (net SYN_DATA_OUT_1 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_1))\r
+ (portRef (member syn_data_out 16))\r
+ ))\r
+ (net SYN_DATA_OUT_c_2 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_2))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_2))\r
+ ))\r
+ (net SYN_DATA_OUT_2 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_2))\r
+ (portRef (member syn_data_out 15))\r
+ ))\r
+ (net SYN_DATA_OUT_c_3 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_3))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_3))\r
+ ))\r
+ (net SYN_DATA_OUT_3 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_3))\r
+ (portRef (member syn_data_out 14))\r
+ ))\r
+ (net SYN_DATA_OUT_c_4 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_4))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_4))\r
+ ))\r
+ (net SYN_DATA_OUT_4 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_4))\r
+ (portRef (member syn_data_out 13))\r
+ ))\r
+ (net SYN_DATA_OUT_c_5 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_5))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_5))\r
+ ))\r
+ (net SYN_DATA_OUT_5 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_5))\r
+ (portRef (member syn_data_out 12))\r
+ ))\r
+ (net SYN_DATA_OUT_c_6 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_6))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_6))\r
+ ))\r
+ (net SYN_DATA_OUT_6 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_6))\r
+ (portRef (member syn_data_out 11))\r
+ ))\r
+ (net SYN_DATA_OUT_c_7 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_7))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_7))\r
+ ))\r
+ (net SYN_DATA_OUT_7 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_7))\r
+ (portRef (member syn_data_out 10))\r
+ ))\r
+ (net SYN_DATA_OUT_c_8 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_8))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_8))\r
+ ))\r
+ (net SYN_DATA_OUT_8 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_8))\r
+ (portRef (member syn_data_out 9))\r
+ ))\r
+ (net SYN_DATA_OUT_c_9 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_9))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_9))\r
+ ))\r
+ (net SYN_DATA_OUT_9 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_9))\r
+ (portRef (member syn_data_out 8))\r
+ ))\r
+ (net SYN_DATA_OUT_c_10 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_10))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_10))\r
+ ))\r
+ (net SYN_DATA_OUT_10 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_10))\r
+ (portRef (member syn_data_out 7))\r
+ ))\r
+ (net SYN_DATA_OUT_c_11 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_11))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_11))\r
+ ))\r
+ (net SYN_DATA_OUT_11 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_11))\r
+ (portRef (member syn_data_out 6))\r
+ ))\r
+ (net SYN_DATA_OUT_c_12 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_12))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_12))\r
+ ))\r
+ (net SYN_DATA_OUT_12 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_12))\r
+ (portRef (member syn_data_out 5))\r
+ ))\r
+ (net SYN_DATA_OUT_c_13 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_13))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_13))\r
+ ))\r
+ (net SYN_DATA_OUT_13 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_13))\r
+ (portRef (member syn_data_out 4))\r
+ ))\r
+ (net SYN_DATA_OUT_c_14 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_14))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_14))\r
+ ))\r
+ (net SYN_DATA_OUT_14 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_14))\r
+ (portRef (member syn_data_out 3))\r
+ ))\r
+ (net SYN_DATA_OUT_c_15 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_15))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_15))\r
+ ))\r
+ (net SYN_DATA_OUT_15 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_15))\r
+ (portRef (member syn_data_out 2))\r
+ ))\r
+ (net SYN_DATA_OUT_c_16 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_16))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_16))\r
+ ))\r
+ (net SYN_DATA_OUT_16 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_16))\r
+ (portRef (member syn_data_out 1))\r
+ ))\r
+ (net SYN_DATA_OUT_c_17 (joined\r
+ (portRef Q (instanceRef current_b2_buffer_0io_17))\r
+ (portRef I (instanceRef SYN_DATA_OUT_pad_17))\r
+ ))\r
+ (net SYN_DATA_OUT_17 (joined\r
+ (portRef O (instanceRef SYN_DATA_OUT_pad_17))\r
+ (portRef (member syn_data_out 0))\r
+ ))\r
+ (net SYN_READ_IN (joined\r
+ (portRef SYN_READ_IN)\r
+ (portRef I (instanceRef SYN_READ_IN_pad))\r
+ ))\r
+ (net STAT_BUFFER_c (joined\r
+ (portRef Q (instanceRef current_got_overflow))\r
+ (portRef I (instanceRef STAT_BUFFER_pad))\r
+ (portRef B (instanceRef current_got_overflow_fb))\r
+ ))\r
+ (net STAT_BUFFER (joined\r
+ (portRef O (instanceRef STAT_BUFFER_pad))\r
+ (portRef STAT_BUFFER)\r
+ ))\r
+ (net fb (joined\r
+ (portRef Z (instanceRef current_got_overflow_fb))\r
+ (portRef D (instanceRef current_got_overflow))\r
+ ))\r
+ )\r
+ )\r
+ )\r
+ )\r
+ (design sbuf (cellRef sbuf (libraryRef work))\r
+ (property PART (string "lfe2m100e-6") ))\r
+)\r
--- /dev/null
+\r
+fsm_encoding {1019511951} sequential\r
+\r
+fsm_state_encoding {1019511951} buffer_empty {00}\r
+\r
+fsm_state_encoding {1019511951} buffer_b2_full {01}\r
+\r
+fsm_state_encoding {1019511951} buffer_b1_full {10}\r
+\r
+fsm_registers {1019511951} {current_buffer_state[1]} {current_buffer_state[0]} \r
--- /dev/null
+#Build: Synplify Pro for Lattice C-2009.03L-1, Build 085R, May 27 2009\r
+#install: X:\Programme\ispTOOLS_80\synpbase\r
+#OS: Windows XP 5.1\r
+#Hostname: ESME\r
+\r
+#Implementation: lever\r
+\r
+#Fri Jun 18 10:31:11 2010\r
+\r
+$ Start of Compile\r
+#Fri Jun 18 10:31:11 2010\r
+\r
+Synopsys VHDL Compiler, version comp350rcp1, Build 105R, built Jul 22 2009\r
+Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved\r
+\r
+@N: CD720 :"X:\Programme\ispTOOLS_80\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns\r
+@N:"I:\vhdl_pro\comp_adcmv3\design\sbuf.vhd":21:7:21:10|Top entity is set to sbuf.\r
+VHDL syntax check successful!\r
+@N: CD630 :"I:\vhdl_pro\comp_adcmv3\design\sbuf.vhd":21:7:21:10|Synthesizing work.sbuf.sbuf_arch \r
+@N: CD233 :"I:\vhdl_pro\comp_adcmv3\design\sbuf.vhd":61:18:61:19|Using sequential encoding for type buffer_state\r
+Post processing for work.sbuf.sbuf_arch\r
+@N: CL201 :"I:\vhdl_pro\comp_adcmv3\design\sbuf.vhd":195:1:195:2|Trying to extract state machine for register current_buffer_state\r
+Extracted state machine for register current_buffer_state\r
+State machine has 3 reachable states with original encodings of:\r
+ 00\r
+ 01\r
+ 10\r
+@END\r
+Process took 0h:00m:07s realtime, 0h:00m:02s cputime\r
+# Fri Jun 18 10:31:19 2010\r
+\r
+###########################################################]\r
+Synopsys Generic Technology Mapper, Version map400lat, Build 146R, Built Sep 10 2009 10:27:59\r
+Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved\r
+Product Version C-2009.03L-1\r
+@N: MF249 |Running in 32-bit mode.\r
+@N: MF257 |Gated clock conversion enabled \r
+@N|Running in logic synthesis mode without enhanced optimization\r
+\r
+Dissolving instances under view:work.sbuf(sbuf_arch) (flattening)\r
+\r
+Available hyper_sources - for debug and ip models\r
+ None Found\r
+\r
+Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 104MB)\r
+\r
+Encoding state machine work.sbuf(sbuf_arch)-current_buffer_state[0:2]\r
+original code -> new code\r
+ 00 -> 00\r
+ 01 -> 01\r
+ 10 -> 10\r
+Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 104MB)\r
+\r
+\r
+\r
+#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[\r
+\r
+======================================================================================\r
+ Instance:Pin Generated Clock Optimization Status\r
+======================================================================================\r
+\r
+\r
+##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]\r
+\r
+Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 104MB)\r
+\r
+\r
+Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 104MB)\r
+\r
+Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 104MB)\r
+\r
+Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 104MB)\r
+\r
+Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 104MB)\r
+\r
+Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 104MB)\r
+\r
+Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 104MB)\r
+\r
+Pass CPU time Worst Slack Luts / Registers\r
+------------------------------------------------------------\r
+Pass CPU time Worst Slack Luts / Registers\r
+------------------------------------------------------------\r
+ 1 0h:00m:00s -0.79ns 31 / 41\r
+ 2 0h:00m:00s -0.79ns 31 / 41\r
+ 3 0h:00m:00s -0.79ns 31 / 41\r
+------------------------------------------------------------\r
+\r
+Timing driven replication report\r
+@N: FX271 :"i:\vhdl_pro\comp_adcmv3\design\sbuf.vhd":195:1:195:2|Instance "current_buffer_state[1]" with 26 loads has been replicated 1 time(s) to improve timing \r
+Added 1 Registers via timing driven replication\r
+Added 1 LUTs via timing driven replication\r
+\r
+\r
+Net buffering Report for view:work.sbuf(sbuf_arch):\r
+No nets needed buffering.\r
+\r
+Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 104MB)\r
+\r
+Found clock sbuf|CLK with period 5.00ns \r
+\r
+\r
+##### START OF TIMING REPORT #####[\r
+# Timing Report written on Fri Jun 18 10:31:22 2010\r
+#\r
+\r
+\r
+Top view: sbuf\r
+Requested Frequency: 200.0 MHz\r
+Wire load mode: top\r
+Paths requested: 3\r
+Constraint File(s): \r
+@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..\r
+\r
+\r
+Performance Summary \r
+*******************\r
+\r
+\r
+Worst slack in design: -0.271\r
+\r
+ Requested Estimated Requested Estimated Clock Clock \r
+Starting Clock Frequency Frequency Period Period Slack Type Group \r
+----------------------------------------------------------------------------------------------------------------------\r
+sbuf|CLK 200.0 MHz 189.7 MHz 5.000 5.271 -0.271 inferred Inferred_clkgroup_0\r
+System 200.0 MHz 201.6 MHz 5.000 4.959 0.041 system default_clkgroup \r
+======================================================================================================================\r
+\r
+\r
+\r
+\r
+\r
+Clock Relationships\r
+*******************\r
+\r
+Clocks | rise to rise | fall to fall | rise to fall | fall to rise \r
+-----------------------------------------------------------------------------------------------------------\r
+Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack\r
+-----------------------------------------------------------------------------------------------------------\r
+sbuf|CLK sbuf|CLK | 5.000 -0.271 | No paths - | No paths - | No paths - \r
+===========================================================================================================\r
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.\r
+ 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.\r
+\r
+\r
+\r
+Interface Information \r
+*********************\r
+\r
+\r
+\r
+Input Ports: \r
+\r
+Port Starting User Arrival Required \r
+Name Reference Constraint Time Time Slack\r
+ Clock \r
+---------------------------------------------------------------------------------------\r
+CLK NA NA NA NA NA \r
+CLK_EN System (rising) NA 0.000 1.759 \r
+COMB_DATAREADY_IN System (rising) NA 0.000 1.224 \r
+COMB_DATA_IN[0] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[1] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[2] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[3] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[4] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[5] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[6] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[7] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[8] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[9] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[10] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[11] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[12] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[13] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[14] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[15] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[16] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[17] System (rising) NA 0.000 2.660 \r
+COMB_READ_IN System (rising) NA 0.000 1.224 \r
+RESET System (rising) NA 0.000 3.005 \r
+SYN_READ_IN System (rising) NA 0.000 0.041 \r
+=======================================================================================\r
+\r
+\r
+Output Ports: \r
+\r
+Port Starting User Arrival Required \r
+Name Reference Constraint Time Time Slack\r
+ Clock \r
+------------------------------------------------------------------------------------------\r
+COMB_next_READ_OUT sbuf|CLK (rising) NA 5.271 5.000 \r
+STAT_BUFFER sbuf|CLK (rising) NA 3.762 5.000 \r
+SYN_DATAREADY_OUT sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[0] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[1] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[2] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[3] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[4] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[5] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[6] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[7] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[8] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[9] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[10] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[11] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[12] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[13] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[14] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[15] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[16] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[17] sbuf|CLK (rising) NA 3.722 5.000 \r
+==========================================================================================\r
+\r
+\r
+##### END OF TIMING REPORT #####]\r
+\r
+---------------------------------------\r
+Resource Usage Report\r
+Part: lfe2m100e-6\r
+\r
+Register bits: 42 of 95000 (0%)\r
+PIC Latch: 0\r
+I/O cells: 45\r
+\r
+\r
+Details:\r
+FD1P3AX: 18\r
+FD1P3IX: 3\r
+FD1S3IX: 3\r
+GSR: 1\r
+IB: 24\r
+OB: 21\r
+OFS1P3DX: 18\r
+ORCALUT4: 32\r
+PUR: 1\r
+VHI: 1\r
+VLO: 1\r
+Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 104MB peak: 104MB)\r
+\r
+Writing Analyst data base I:\vhdl_pro\comp_adcmv3\lever\sbuf.srm\r
+@N: MF203 |Set autoconstraint_io \r
+Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 104MB peak: 104MB)\r
+\r
+Writing EDIF Netlist and constraint files\r
+C-2009.03L-1\r
+Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 108MB)\r
+\r
+Writing Verilog Simulation files\r
+Finished Writing Verilog Simulation files (Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 108MB)\r
+\r
+Writing VHDL Simulation files\r
+Finished Writing VHDL Simulation files (Time elapsed 0h:00m:02s; Memory used current: 107MB peak: 108MB)\r
+\r
+Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:02s; Memory used current: 107MB peak: 108MB)\r
+\r
+@N: MF276 |Gated clock conversion enabled, but no gated clocks found in design \r
+Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:02s; Memory used current: 107MB peak: 108MB)\r
+\r
+Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:02s; Memory used current: 107MB peak: 108MB)\r
+\r
+@N: MF333 |Generated clock conversion enabled, but no generated clocks found in design \r
+Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:02s; Memory used current: 107MB peak: 108MB)\r
+\r
+\r
+\r
+##### START OF TIMING REPORT #####[\r
+# Timing Report written on Fri Jun 18 10:31:24 2010\r
+#\r
+\r
+\r
+Top view: sbuf\r
+Requested Frequency: 200.0 MHz\r
+Wire load mode: top\r
+Paths requested: 3\r
+Constraint File(s): \r
+@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..\r
+\r
+\r
+Performance Summary \r
+*******************\r
+\r
+\r
+Worst slack in design: -0.271\r
+\r
+ Requested Estimated Requested Estimated Clock Clock \r
+Starting Clock Frequency Frequency Period Period Slack Type Group \r
+----------------------------------------------------------------------------------------------------------------------\r
+sbuf|CLK 200.0 MHz 189.7 MHz 5.000 5.271 -0.271 inferred Inferred_clkgroup_0\r
+System 200.0 MHz 201.6 MHz 5.000 4.959 0.041 system default_clkgroup \r
+======================================================================================================================\r
+\r
+\r
+\r
+\r
+\r
+Clock Relationships\r
+*******************\r
+\r
+Clocks | rise to rise | fall to fall | rise to fall | fall to rise \r
+-----------------------------------------------------------------------------------------------------------\r
+Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack\r
+-----------------------------------------------------------------------------------------------------------\r
+sbuf|CLK sbuf|CLK | 5.000 -0.271 | No paths - | No paths - | No paths - \r
+===========================================================================================================\r
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.\r
+ 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.\r
+\r
+\r
+\r
+Interface Information \r
+*********************\r
+\r
+\r
+\r
+Input Ports: \r
+\r
+Port Starting User Arrival Required \r
+Name Reference Constraint Time Time Slack\r
+ Clock \r
+---------------------------------------------------------------------------------------\r
+CLK NA NA NA NA NA \r
+CLK_EN System (rising) NA 0.000 1.759 \r
+COMB_DATAREADY_IN System (rising) NA 0.000 1.224 \r
+COMB_DATA_IN[0] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[1] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[2] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[3] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[4] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[5] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[6] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[7] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[8] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[9] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[10] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[11] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[12] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[13] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[14] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[15] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[16] System (rising) NA 0.000 2.660 \r
+COMB_DATA_IN[17] System (rising) NA 0.000 2.660 \r
+COMB_READ_IN System (rising) NA 0.000 1.224 \r
+RESET System (rising) NA 0.000 3.005 \r
+SYN_READ_IN System (rising) NA 0.000 0.041 \r
+=======================================================================================\r
+\r
+\r
+Output Ports: \r
+\r
+Port Starting User Arrival Required \r
+Name Reference Constraint Time Time Slack\r
+ Clock \r
+------------------------------------------------------------------------------------------\r
+COMB_next_READ_OUT sbuf|CLK (rising) NA 5.271 5.000 \r
+STAT_BUFFER sbuf|CLK (rising) NA 3.762 5.000 \r
+SYN_DATAREADY_OUT sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[0] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[1] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[2] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[3] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[4] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[5] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[6] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[7] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[8] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[9] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[10] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[11] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[12] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[13] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[14] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[15] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[16] sbuf|CLK (rising) NA 3.722 5.000 \r
+SYN_DATA_OUT[17] sbuf|CLK (rising) NA 3.722 5.000 \r
+==========================================================================================\r
+\r
+\r
+##### END OF TIMING REPORT #####]\r
+\r
+Mapper successful!\r
+Process took 0h:00m:03s realtime, 0h:00m:02s cputime\r
+# Fri Jun 18 10:31:24 2010\r
+\r
+###########################################################]\r
--- /dev/null
+project -fileorder "X:/Programme/ispTOOLS_80/ispcpld/../cae_library/synthesis/vhdl/ecp2m.vhd" "I:/vhdl_pro/comp_adcmv3/version.vhd" "I:/vhdl_pro/comp_adcmv3/design/adcmv3_components.vhd" "I:/vhdl_pro/trbnet/trb_net_std.vhd" "I:/vhdl_pro/comp_adcmv3/design/test_media.vhd" "I:/vhdl_pro/comp_adcmv3/design/sbuf.vhd" "I:/vhdl_pro/comp_adcmv3/design/sfp_rx_handler.vhd" "I:/vhdl_pro/trbnet/basics/signal_sync.vhd" "I:/vhdl_pro/trbnet/trb_net_components.vhd" "I:/vhdl_pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd" "I:/vhdl_pro/comp_adcmv3/design/pulse_sync.vhd" "I:/vhdl_pro/comp_adcmv3/design/apv_sync_handler.vhd" "I:/vhdl_pro/comp_adcmv3/design/apv_trg_handler.vhd" "I:/vhdl_pro/comp_adcmv3/design/eds_buffer_dpram.vhd" "I:/vhdl_pro/comp_adcmv3/design/eds_buf.vhd" "I:/vhdl_pro/comp_adcmv3/design/max_data.vhd" "I:/vhdl_pro/comp_adcmv3/design/state_sync.vhd" "I:/vhdl_pro/comp_adcmv3/design/real_trg_handler.vhd" "I:/vhdl_pro/comp_adcmv3/design/pulse_stretch.vhd" "I:/vhdl_pro/comp_adcmv3/design/apv_trgctrl.vhd" "I:/vhdl_pro/comp_adcmv3/design/adc_channel_select.vhd" "I:/vhdl_pro/comp_adcmv3/design/crossover.vhd" "I:/vhdl_pro/comp_adcmv3/design/adc_crossover.vhd" "I:/vhdl_pro/comp_adcmv3/design/adc_twochannels.vhd" "I:/vhdl_pro/comp_adcmv3/design/adc_ch_in.vhd" "I:/vhdl_pro/comp_adcmv3/design/adc_data_handler.vhd" "I:/vhdl_pro/comp_adcmv3/design/frame_status_mem.vhd" "I:/vhdl_pro/comp_adcmv3/design/input_bram.vhd" "I:/vhdl_pro/comp_adcmv3/design/apv_raw_buffer.vhd" "I:/vhdl_pro/comp_adcmv3/design/apv_lock_sm.vhd" "I:/vhdl_pro/comp_adcmv3/design/apv_digital.vhd" "I:/vhdl_pro/comp_adcmv3/design/apv_locker.vhd" "I:/vhdl_pro/comp_adcmv3/design/raw_buf_stage.vhd" "I:/vhdl_pro/comp_adcmv3/design/decoder_8bit.vhd" "I:/vhdl_pro/comp_adcmv3/design/apv_pc_nc_alu.vhd" "I:/vhdl_pro/comp_adcmv3/design/buf_toc.vhd" "I:/vhdl_pro/comp_adcmv3/design/ref_row_sel.vhd" "I:/vhdl_pro/comp_adcmv3/design/frmctr_check.vhd" "I:/vhdl_pro/comp_adcmv3/design/ped_corr_ctrl.vhd" "I:/vhdl_pro/comp_adcmv3/design/adc_apv_map_mem.vhd" "I:/vhdl_pro/comp_adcmv3/design/fifo_1kx18.vhd" "I:/vhdl_pro/comp_adcmv3/design/fifo_2kx27.vhd" "I:/vhdl_pro/comp_adcmv3/design/ipu_fifo_stage.vhd" "I:/vhdl_pro/comp_adcmv3/design/slv_register.vhd" "I:/vhdl_pro/comp_adcmv3/design/adc_snoop_mem.vhd" "I:/vhdl_pro/comp_adcmv3/design/slv_adc_snoop.vhd" "I:/vhdl_pro/comp_adcmv3/design/slv_half_register.vhd" "I:/vhdl_pro/comp_adcmv3/design/slv_status.vhd" "I:/vhdl_pro/comp_adcmv3/design/slv_status_bank.vhd" "I:/vhdl_pro/comp_adcmv3/design/apv_adc_map_mem.vhd" "I:/vhdl_pro/comp_adcmv3/design/slv_register_bank.vhd" "I:/vhdl_pro/comp_adcmv3/design/spi_real_slim.vhd" "I:/vhdl_pro/comp_adcmv3/design/spi_adc_master.vhd" "I:/vhdl_pro/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd" "I:/vhdl_pro/trbnet/special/spi_databus_memory.vhd" "I:/vhdl_pro/trbnet/special/spi_slim.vhd" "I:/vhdl_pro/trbnet/special/spi_master.vhd" "I:/vhdl_pro/comp_adcmv3/design/slv_onewire_dpram.vhd" "I:/vhdl_pro/comp_adcmv3/design/onewire_master.vhd" "I:/vhdl_pro/comp_adcmv3/design/onewire_spare_one.vhd" "I:/vhdl_pro/comp_adcmv3/design/adc_onewire_map_mem.vhd" "I:/vhdl_pro/comp_adcmv3/design/slv_onewire_memory.vhd" "I:/vhdl_pro/comp_adcmv3/design/i2c_gstart.vhd" "I:/vhdl_pro/comp_adcmv3/design/i2c_sendb.vhd" "I:/vhdl_pro/comp_adcmv3/design/i2c_slim.vhd" "I:/vhdl_pro/comp_adcmv3/design/i2c_master.vhd" "I:/vhdl_pro/comp_adcmv3/design/ped_thr_true.vhd" "I:/vhdl_pro/comp_adcmv3/design/slv_ped_thr_mem.vhd" "I:/vhdl_pro/trbnet/trb_net16_regio_bus_handler.vhd" "I:/vhdl_pro/comp_adcmv3/design/slave_bus.vhd" "I:/vhdl_pro/trbnet/trb_net_sbuf.vhd" "I:/vhdl_pro/trbnet/trb_net16_sbuf.vhd" "I:/vhdl_pro/trbnet/trb_net_priority_encoder.vhd" "I:/vhdl_pro/trbnet/trb_net_priority_arbiter.vhd" "I:/vhdl_pro/trbnet/trb_net16_io_multiplexer.vhd" "I:/vhdl_pro/trbnet/trb_net_onewire.vhd" "I:/vhdl_pro/trbnet/basics/rom_16x8.vhd" "I:/vhdl_pro/trbnet/basics/ram_16x16_dp.vhd" "I:/vhdl_pro/trbnet/trb_net16_addresses.vhd" "I:/vhdl_pro/trbnet/trb_net_pattern_gen.vhd" "I:/vhdl_pro/trbnet/trb_net16_regIO.vhd" "I:/vhdl_pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd" "I:/vhdl_pro/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd" "I:/vhdl_pro/trbnet/trb_net16_api_base.vhd" "I:/vhdl_pro/trbnet/trb_net_CRC.vhd" "I:/vhdl_pro/trbnet/trb_net16_obuf.vhd" "I:/vhdl_pro/trbnet/trb_net16_obuf_nodata.vhd" "I:/vhdl_pro/trbnet/trb_net16_ibuf.vhd" "I:/vhdl_pro/trbnet/trb_net16_iobuf.vhd" "I:/vhdl_pro/trbnet/trb_net16_term_buf.vhd" "I:/vhdl_pro/trbnet/trb_net16_ipudata.vhd" "I:/vhdl_pro/trbnet/trb_net16_trigger.vhd" "I:/vhdl_pro/trbnet/trb_net16_endpoint_hades_full.vhd" "I:/vhdl_pro/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd" "I:/vhdl_pro/trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd" "I:/vhdl_pro/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd" "I:/vhdl_pro/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" "I:/vhdl_pro/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd" "I:/vhdl_pro/comp_adcmv3/design/rich_trb.vhd" "I:/vhdl_pro/comp_adcmv3/design/sync_pll_40m.vhd" "I:/vhdl_pro/comp_adcmv3/design/dll_100m.vhd" "I:/vhdl_pro/comp_adcmv3/design/pll_40m.vhd" "I:/vhdl_pro/comp_adcmv3/design/reboot_handler.vhd" "I:/vhdl_pro/comp_adcmv3/design/reset_handler.vhd" "I:/vhdl_pro/comp_adcmv3/design/adcmv3.vhd"
\ No newline at end of file
--- /dev/null
+@P: Worst Slack : -0.271\r
+@P: sbuf|CLK - Estimated Frequency : 189.7 MHz\r
+@P: sbuf|CLK - Requested Frequency : 200.0 MHz\r
+@P: sbuf|CLK - Estimated Period : 5.271\r
+@P: sbuf|CLK - Requested Period : 5.000\r
+@P: sbuf|CLK - Slack : -0.271\r
+@P: System - Estimated Frequency : 201.6 MHz\r
+@P: System - Requested Frequency : 200.0 MHz\r
+@P: System - Estimated Period : 4.959\r
+@P: System - Requested Period : 5.000\r
+@P: System - Slack : 0.041\r
+@P: Worst Slack : -0.271\r
+@P: sbuf|CLK - Estimated Frequency : 189.7 MHz\r
+@P: sbuf|CLK - Requested Frequency : 200.0 MHz\r
+@P: sbuf|CLK - Estimated Period : 5.271\r
+@P: sbuf|CLK - Requested Period : 5.000\r
+@P: sbuf|CLK - Slack : -0.271\r
+@P: System - Estimated Frequency : 201.6 MHz\r
+@P: System - Requested Frequency : 200.0 MHz\r
+@P: System - Estimated Period : 4.959\r
+@P: System - Requested Period : 5.000\r
+@P: System - Slack : 0.041\r
+@P: CPU Time : 0h:00m:02s\r
--- /dev/null
+#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {X:/Programme/ispTOOLS_80/ispcpld/bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd\r
+#vcomSrc ../sim/tb_apv_trgctrl.vhd\r
+#stimulus vhdl apv_trgctrl ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../../trbnet/basics/signal_sync.vhd ../design/pulse_stretch.vhd ../../trbnet/special/handler_lvl1.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_apv_trgctrl.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_apv_trgctrl_vhdf.udo %<StimModule>%\r
+#insert # End\r
--- /dev/null
+setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_apv_trgctrl.fado\r
--- /dev/null
+setenv SIM_WORKING_FOLDER .\r
--- /dev/null
+-- ispLEVER VHDL Functional Simulation Template: tb_apv_trgctrl_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
--- /dev/null
+#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {X:/Programme/ispTOOLS_80/ispcpld/bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd\r
+#vcomSrc ../sim/tb_media_fifo.vhd\r
+#stimulus vhdl fifo_18x16_media_interface ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../design/sfp_rx_handler.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_media_fifo.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_media_fifo_vhdf.udo %<StimModule>%\r
+#insert # End\r
--- /dev/null
+setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_media_fifo.fado\r
--- /dev/null
+setenv SIM_WORKING_FOLDER .\r
--- /dev/null
+#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {X:/Programme/ispTOOLS_80/ispcpld/bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface_mb.vhd\r
+#vcomSrc ../sim/tb_media_fifo_mb.vhd\r
+#stimulus vhdl fifo_18x16_media_interface_mb ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface_mb.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../design/sfp_rx_handler.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_media_fifo_mb.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_media_fifo_mb_vhdf.udo %<StimModule>%\r
+#insert # End\r
--- /dev/null
+setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_media_fifo_mb.fado\r
--- /dev/null
+setenv SIM_WORKING_FOLDER .\r
--- /dev/null
+-- ispLEVER VHDL Functional Simulation Template: tb_media_fifo_mb_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
--- /dev/null
+-- ispLEVER VHDL Functional Simulation Template: tb_media_fifo_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
--- /dev/null
+#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {X:/Programme/ispTOOLS_80/ispcpld/bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd\r
+#vcomSrc ../sim/tb_ped_corr_ctrl.vhd\r
+#stimulus vhdl ped_corr_ctrl ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_ped_corr_ctrl.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_ped_corr_ctrl_vhdf.udo %<StimModule>%\r
+#insert # End\r
--- /dev/null
+setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_ped_corr_ctrl.fado\r
--- /dev/null
+setenv SIM_WORKING_FOLDER .\r
--- /dev/null
+-- ispLEVER VHDL Functional Simulation Template: tb_ped_corr_ctrl_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
--- /dev/null
+#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {X:/Programme/ispTOOLS_80/ispcpld/bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/sfp_rx_handler.vhd\r
+#vcomSrc ../sim/tb_sfp_rx_handler.vhd\r
+#stimulus vhdl sfp_rx_handler ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface_mb.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../design/sfp_rx_handler.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_sfp_rx_handler.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_sfp_rx_handler_vhdf.udo %<StimModule>%\r
+#insert # End\r
--- /dev/null
+setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_sfp_rx_handler.fado\r
--- /dev/null
+setenv SIM_WORKING_FOLDER .\r
--- /dev/null
+-- ispLEVER VHDL Functional Simulation Template: tb_sfp_rx_handler_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
--- /dev/null
+# NOTE: Do not edit this file.\r
+# Auto generated by VHDL Functional Simulation Models\r
+#\r
+design create work .\r
+design open work\r
+adel -all\r
+source {X:/Programme/ispTOOLS_80/ispcpld/bin/chipsim_cmd.tcl}\r
+set sty_file adcmv3.sty \r
+if {![info exists HasProc(LS_Vcom)]} { source {chipsim_cmd.tcl} }\r
+set vcom_opt ""\r
+set src_files {../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd} \r
+LS_Vcom sty_file src_files vcom_opt\r
+if {![info exists HasProc(LS_Vcom)]} { source {chipsim_cmd.tcl} }\r
+set vcom_opt ""\r
+set src_files {../sim/tb_spi_master.vhd} \r
+LS_Vcom sty_file src_files vcom_opt\r
+vsim testbench -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+do tb_spi_master_vhdf.udo testbench\r
+# End\r
--- /dev/null
+#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {X:/Programme/ispTOOLS_80/ispcpld/bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd\r
+#vcomSrc ../sim/tb_spi_master.vhd\r
+#stimulus vhdl spi_master ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../design/dbg_reg.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/special/handler_lvl1.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net_sbuf5.vhd ../../trbnet/trb_net_sbuf6.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_spi_master.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_spi_master_vhdf.udo %<StimModule>%\r
+#insert # End\r
--- /dev/null
+setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_spi_master.fado\r
--- /dev/null
+setenv SIM_WORKING_FOLDER .\r
--- /dev/null
+-- ispLEVER VHDL Functional Simulation Template: tb_spi_master_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
--- /dev/null
+#insert # NOTE: Do not edit this file.\r
+#insert # Auto generated by VHDL Functional Simulation Models\r
+#insert #\r
+#insert design create work .\r
+#insert design open work\r
+#insert adel -all\r
+#path\r
+#do \r
+#insert source {X:/Programme/ispTOOLS_80/ispcpld/bin/chipsim_cmd.tcl}\r
+#prjInfo adcmv3.sty\r
+#vcomSrc ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd\r
+#vcomSrc ../sim/tb_test_media.vhd\r
+#stimulus vhdl test_media ../../trbnet/trb_net_components.vhd ../version.vhd ../design/adcmv3_components.vhd ../../trbnet/trb_net_std.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd ../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd ../design/test_media.vhd ../design/pulse_sync.vhd ../design/apv_sync_handler.vhd ../design/apv_trg_handler.vhd ../design/eds_buffer_dpram.vhd ../design/eds_buf.vhd ../design/max_data.vhd ../design/state_sync.vhd ../design/real_trg_handler.vhd ../design/pulse_stretch.vhd ../design/apv_trgctrl.vhd ../design/adc_channel_select.vhd ../design/crossover.vhd ../design/adc_crossover.vhd ../design/adc_twochannels.vhd ../design/adc_ch_in.vhd ../design/adc_data_handler.vhd ../design/frame_status_mem.vhd ../design/input_bram.vhd ../design/apv_raw_buffer.vhd ../design/apv_lock_sm.vhd ../design/apv_digital.vhd ../design/apv_locker.vhd ../design/raw_buf_stage.vhd ../design/decoder_8bit.vhd ../design/apv_pc_nc_alu.vhd ../design/buf_toc.vhd ../design/ref_row_sel.vhd ../design/frmctr_check.vhd ../design/ped_corr_ctrl.vhd ../design/adc_apv_map_mem.vhd ../design/fifo_1kx18.vhd ../design/fifo_2kx27.vhd ../design/ipu_fifo_stage.vhd ../design/slv_register.vhd ../design/adc_snoop_mem.vhd ../design/slv_adc_snoop.vhd ../design/slv_half_register.vhd ../design/slv_status.vhd ../design/slv_status_bank.vhd ../design/apv_adc_map_mem.vhd ../design/slv_register_bank.vhd ../design/spi_real_slim.vhd ../design/spi_adc_master.vhd ../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd ../../trbnet/special/spi_databus_memory.vhd ../../trbnet/special/spi_slim.vhd ../../trbnet/special/spi_master.vhd ../design/slv_onewire_dpram.vhd ../design/onewire_master.vhd ../design/onewire_spare_one.vhd ../design/adc_onewire_map_mem.vhd ../design/slv_onewire_memory.vhd ../design/i2c_gstart.vhd ../design/i2c_sendb.vhd ../design/i2c_slim.vhd ../design/i2c_master.vhd ../design/ped_thr_true.vhd ../design/slv_ped_thr_mem.vhd ../../trbnet/trb_net16_regio_bus_handler.vhd ../design/slave_bus.vhd ../../trbnet/trb_net_sbuf.vhd ../../trbnet/trb_net16_sbuf.vhd ../../trbnet/trb_net_priority_encoder.vhd ../../trbnet/trb_net_priority_arbiter.vhd ../../trbnet/trb_net16_io_multiplexer.vhd ../../trbnet/trb_net_onewire.vhd ../../trbnet/basics/rom_16x8.vhd ../../trbnet/basics/ram_16x16_dp.vhd ../../trbnet/trb_net16_addresses.vhd ../../trbnet/trb_net_pattern_gen.vhd ../../trbnet/trb_net16_regIO.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd ../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd ../../trbnet/trb_net16_api_base.vhd ../../trbnet/trb_net_CRC.vhd ../../trbnet/trb_net16_obuf.vhd ../../trbnet/trb_net16_obuf_nodata.vhd ../../trbnet/trb_net16_ibuf.vhd ../../trbnet/trb_net16_iobuf.vhd ../../trbnet/trb_net16_term_buf.vhd ../../trbnet/trb_net16_ipudata.vhd ../../trbnet/trb_net16_trigger.vhd ../../trbnet/trb_net16_endpoint_hades_full.vhd ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd ../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd ../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd ../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd ../../trbnet/basics/signal_sync.vhd ../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd ../design/rich_trb.vhd ../design/sync_pll_40m.vhd ../design/dll_100m.vhd ../design/pll_40m.vhd ../design/reboot_handler.vhd ../design/reset_handler.vhd ../design/adcmv3.vhd ../sim/tb_test_media.vhd\r
+#insert vsim %<StimModule>% -PL pmi_work -L ovi_ecp2m -L pcsc_work\r
+#youdo tb_test_media_vhdf.udo %<StimModule>%\r
+#insert # End\r
--- /dev/null
+setenv SIM_WORKING_FOLDER .\r
+do -tcl tb_test_media.fado\r
--- /dev/null
+setenv SIM_WORKING_FOLDER .\r
--- /dev/null
+-- ispLEVER VHDL Functional Simulation Template: tb_test_media_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
--- /dev/null
+\r
+-- VHDL Test Bench Created from source file test_media.vhd -- Mon Jun 07 11:31:16 2010\r
+\r
+--\r
+-- Notes: \r
+-- 1) This testbench template has been automatically generated using types\r
+-- std_logic and std_logic_vector for the ports of the unit under test.\r
+-- Lattice recommends that these types always be used for the top-level\r
+-- I/O of a design in order to guarantee that the testbench will bind\r
+-- correctly to the timing (post-route) simulation model.\r
+-- 2) To use this template as your testbench, change the filename to any\r
+-- name of your choice with the extension .vhd, and use the "source->import"\r
+-- menu in the ispLEVER Project Navigator to import the testbench.\r
+-- Then edit the user defined section below, adding code to generate the \r
+-- stimulus for your design.\r
+-- 3) VHDL simulations will produce errors if there are Lattice FPGA library \r
+-- elements in your design that require the instantiation of GSR, PUR, and\r
+-- TSALL and they are not present in the testbench. For more information see\r
+-- the How To section of online help. \r
+--\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT test_media\r
+ PORT(\r
+ SYSCLK : IN std_logic;\r
+ RESET : IN std_logic;\r
+ CLEAR : IN std_logic;\r
+ MED_READ_IN : IN std_logic;\r
+ SD_RX_DATA_IN : IN std_logic_vector(15 downto 0);\r
+ SD_RX_K_IN : IN std_logic_vector(1 downto 0); \r
+ MED_DATA_OUT : OUT std_logic_vector(15 downto 0);\r
+ MED_PACKET_NUM_OUT : OUT std_logic_vector(2 downto 0);\r
+ MED_DATAREADY_OUT : OUT std_logic;\r
+ DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL SYSCLK : std_logic;\r
+ SIGNAL RESET : std_logic;\r
+ SIGNAL CLEAR : std_logic;\r
+ SIGNAL MED_DATA_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL MED_PACKET_NUM_OUT : std_logic_vector(2 downto 0);\r
+ SIGNAL MED_DATAREADY_OUT : std_logic;\r
+ SIGNAL MED_READ_IN : std_logic;\r
+ SIGNAL SD_RX_DATA_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL SD_RX_K_IN : std_logic_vector(1 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: test_media PORT MAP(\r
+ SYSCLK => SYSCLK,\r
+ RESET => RESET,\r
+ CLEAR => CLEAR,\r
+ MED_DATA_OUT => MED_DATA_OUT,\r
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,\r
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,\r
+ MED_READ_IN => MED_READ_IN,\r
+ SD_RX_DATA_IN => SD_RX_DATA_IN,\r
+ SD_RX_K_IN => SD_RX_K_IN,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+\r
+-- *** Test Bench - User Defined Section ***\r
+ tb : PROCESS\r
+ BEGIN\r
+ wait; -- will wait forever\r
+ END PROCESS;\r
+-- *** End Test Bench - User Defined Section ***\r
+\r
+END;\r
--- /dev/null
+-- ispLEVER VHDL Functional Simulation Template: tb_spi_master_vhdf.udo.\r
+-- You may edit this file to control your simulation.\r
+-- You may specify your design unit.\r
+-- You may specify your waveforms.\r
+add wave *\r
+-- You may specify your simulation run time.\r
+run 1000 ns\r
--- /dev/null
+#-- Lattice Semiconductor Corporation Ltd.\r
+#-- Synplify OEM project file i:/vhdl_pro/comp_adcmv3/lever\work.sbuf.prj\r
+#-- Written on Fri Jun 18 10:31:00 2010\r
+\r
+\r
+#device options\r
+set_option -technology LATTICE-ecp2m\r
+set_option -part LFE2M100E\r
+set_option -speed_grade -6\r
+\r
+#compilation/mapping options\r
+set_option -default_enum_encoding default\r
+set_option -symbolic_fsm_compiler true\r
+set_option -resource_sharing true\r
+\r
+#use verilog 2001 standard option\r
+set_option -vlog_std v2001\r
+\r
+#map options\r
+set_option -frequency 200\r
+set_option -fanout_limit 100\r
+set_option -auto_constrain_io true\r
+set_option -disable_io_insertion false\r
+set_option -retiming false\r
+set_option -pipe false\r
+set_option -force_gsr false\r
+set_option -compiler_compatible true\r
+set_option -dup false\r
+\r
+#simulation options\r
+set_option -write_verilog true\r
+set_option -write_vhdl true\r
+\r
+#timing analysis options\r
+set_option -num_critical_paths 3\r
+set_option -num_startend_points 0\r
+\r
+#automatic place and route (vendor) options\r
+set_option -write_apr_constraint 0\r
+\r
+#synplifyPro options.\r
+set_option -fixgatedclocks 3\r
+\r
+#synplifyPro options.\r
+set_option -fixgeneratedclocks 3\r
+\r
+#-- add_file options\r
+add_file -vhdl -lib work "X:/Programme/ispTOOLS_80/ispcpld/../cae_library/synthesis/vhdl/ecp2m.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"\r
+add_file -vhdl -lib work "../version.vhd"\r
+add_file -vhdl -lib work "../design/adcmv3_components.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"\r
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd"\r
+add_file -vhdl -lib work "../design/test_media.vhd"\r
+add_file -vhdl -lib work "../design/sbuf.vhd"\r
+add_file -vhdl -lib work "../design/sfp_rx_handler.vhd"\r
+add_file -vhdl -lib work "../design/pulse_sync.vhd"\r
+add_file -vhdl -lib work "../design/apv_sync_handler.vhd"\r
+add_file -vhdl -lib work "../design/apv_trg_handler.vhd"\r
+add_file -vhdl -lib work "../design/eds_buffer_dpram.vhd"\r
+add_file -vhdl -lib work "../design/eds_buf.vhd"\r
+add_file -vhdl -lib work "../design/max_data.vhd"\r
+add_file -vhdl -lib work "../design/state_sync.vhd"\r
+add_file -vhdl -lib work "../design/real_trg_handler.vhd"\r
+add_file -vhdl -lib work "../design/pulse_stretch.vhd"\r
+add_file -vhdl -lib work "../design/apv_trgctrl.vhd"\r
+add_file -vhdl -lib work "../design/adc_channel_select.vhd"\r
+add_file -vhdl -lib work "../design/crossover.vhd"\r
+add_file -vhdl -lib work "../design/adc_crossover.vhd"\r
+add_file -vhdl -lib work "../design/adc_twochannels.vhd"\r
+add_file -vhdl -lib work "../design/adc_ch_in.vhd"\r
+add_file -vhdl -lib work "../design/adc_data_handler.vhd"\r
+add_file -vhdl -lib work "../design/frame_status_mem.vhd"\r
+add_file -vhdl -lib work "../design/input_bram.vhd"\r
+add_file -vhdl -lib work "../design/apv_raw_buffer.vhd"\r
+add_file -vhdl -lib work "../design/apv_lock_sm.vhd"\r
+add_file -vhdl -lib work "../design/apv_digital.vhd"\r
+add_file -vhdl -lib work "../design/apv_locker.vhd"\r
+add_file -vhdl -lib work "../design/raw_buf_stage.vhd"\r
+add_file -vhdl -lib work "../design/decoder_8bit.vhd"\r
+add_file -vhdl -lib work "../design/apv_pc_nc_alu.vhd"\r
+add_file -vhdl -lib work "../design/buf_toc.vhd"\r
+add_file -vhdl -lib work "../design/ref_row_sel.vhd"\r
+add_file -vhdl -lib work "../design/frmctr_check.vhd"\r
+add_file -vhdl -lib work "../design/ped_corr_ctrl.vhd"\r
+add_file -vhdl -lib work "../design/adc_apv_map_mem.vhd"\r
+add_file -vhdl -lib work "../design/fifo_1kx18.vhd"\r
+add_file -vhdl -lib work "../design/fifo_2kx27.vhd"\r
+add_file -vhdl -lib work "../design/ipu_fifo_stage.vhd"\r
+add_file -vhdl -lib work "../design/slv_register.vhd"\r
+add_file -vhdl -lib work "../design/adc_snoop_mem.vhd"\r
+add_file -vhdl -lib work "../design/slv_adc_snoop.vhd"\r
+add_file -vhdl -lib work "../design/slv_half_register.vhd"\r
+add_file -vhdl -lib work "../design/slv_status.vhd"\r
+add_file -vhdl -lib work "../design/slv_status_bank.vhd"\r
+add_file -vhdl -lib work "../design/apv_adc_map_mem.vhd"\r
+add_file -vhdl -lib work "../design/slv_register_bank.vhd"\r
+add_file -vhdl -lib work "../design/spi_real_slim.vhd"\r
+add_file -vhdl -lib work "../design/spi_adc_master.vhd"\r
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd"\r
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"\r
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"\r
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"\r
+add_file -vhdl -lib work "../design/slv_onewire_dpram.vhd"\r
+add_file -vhdl -lib work "../design/onewire_master.vhd"\r
+add_file -vhdl -lib work "../design/onewire_spare_one.vhd"\r
+add_file -vhdl -lib work "../design/adc_onewire_map_mem.vhd"\r
+add_file -vhdl -lib work "../design/slv_onewire_memory.vhd"\r
+add_file -vhdl -lib work "../design/i2c_gstart.vhd"\r
+add_file -vhdl -lib work "../design/i2c_sendb.vhd"\r
+add_file -vhdl -lib work "../design/i2c_slim.vhd"\r
+add_file -vhdl -lib work "../design/i2c_master.vhd"\r
+add_file -vhdl -lib work "../design/ped_thr_true.vhd"\r
+add_file -vhdl -lib work "../design/slv_ped_thr_mem.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"\r
+add_file -vhdl -lib work "../design/slave_bus.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"\r
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"\r
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"\r
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"\r
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"\r
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"\r
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"\r
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd"\r
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd"\r
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"\r
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"\r
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd"\r
+add_file -vhdl -lib work "../design/rich_trb.vhd"\r
+add_file -vhdl -lib work "../design/sync_pll_40m.vhd"\r
+add_file -vhdl -lib work "../design/dll_100m.vhd"\r
+add_file -vhdl -lib work "../design/pll_40m.vhd"\r
+add_file -vhdl -lib work "../design/reboot_handler.vhd"\r
+add_file -vhdl -lib work "../design/reset_handler.vhd"\r
+add_file -vhdl -lib work "../design/adcmv3.vhd"\r
+\r
+#-- top module name\r
+set_option -top_module sbuf\r
+\r
+#-- set result format/file last\r
+project -result_file "sbuf.edi"\r
+\r
+#-- error message log file\r
+project -log_file sbuf.srf\r
+\r
+#-- run Synplify with 'arrange VHDL file'\r
+project -run hdl_info_gen -fileorder\r
+project -run\r
--- /dev/null
+V 000026 55 490 0 version
+(_unit VHDL (version 0 9 )\r
+ (_version v63)\r
+ (_time 1318408979777 2011.10.12 10:42:59)\r
+ (_source (\./../../version.vhd\))\r
+ (_use (std(standard))(ieee(std_logic_1164))(ieee(std_logic_arith))(ieee(STD_LOGIC_UNSIGNED))(ieee(NUMERIC_STD)))\r
+ (_parameters dbg)\r
+ (_code ede2edbebcbbbbfaeeb9f4b7ea)\r
+ (_object\r
+ (_constant (_internal VERSION_NUMBER_TIME ~extSTD.STANDARD.INTEGER 0 11 (_entity ((i 1287565126)))))\r
+ (_type (_external ~extSTD.STANDARD.INTEGER (std STANDARD INTEGER)))\r
+ )\r
+)\r
+V 000038 55 94116 0 adcmv3_components
+(_unit VHDL (adcmv3_components 0 8 )\r
+ (_version v63)\r
+ (_time 1318408980308 2011.10.12 10:43:00)\r
+ (_source (\./../../design/adcmv3_components.vhd\))\r
+ (_use (std(standard))(ieee(std_logic_1164))(ieee(NUMERIC_STD)))\r
+ (_parameters dbg)\r
+ (_code 000e08060457571654015704135907)\r
+ (_object\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15 0 22 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~154 0 34 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15 0 58 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~156 0 59 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~158 0 60 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1510 0 61 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1512 0 62 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1514 0 63 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1516 0 64 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1518 0 65 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1520 0 68 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1522 0 69 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1524 0 70 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1526 0 71 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1528 0 72 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1530 0 73 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1532 0 74 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1534 0 75 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15 0 77 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1536 0 78 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1538 0 79 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1540 0 80 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1542 0 81 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1544 0 82 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~15 0 86 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1546 0 88 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1548 0 89 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1550 0 90 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15 0 91 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~1552 0 92 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~1554 0 93 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~1556 0 94 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~1558 0 95 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~1560 0 96 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~1562 0 97 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~1564 0 98 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~1566 0 99 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~1568 0 100 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~1570 0 101 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~1572 0 102 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~1574 0 103 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~1576 0 104 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~1578 0 105 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~1580 0 106 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1582 0 108 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1584 0 109 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1586 0 110 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1588 0 111 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1590 0 112 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1592 0 113 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1594 0 114 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1596 0 115 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1598 0 116 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15100 0 117 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15102 0 118 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15104 0 119 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15106 0 120 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15108 0 121 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15110 0 122 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15112 0 123 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15 0 125 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15 0 134 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15114 0 135 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15116 0 136 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15118 0 137 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15120 0 138 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15122 0 139 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15124 0 140 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15126 0 141 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15128 0 142 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15130 0 143 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15132 0 147 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15134 0 159 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15136 0 160 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15138 0 161 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15140 0 162 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15142 0 163 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15144 0 164 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15146 0 165 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15148 0 166 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4~downto~0}~15 0 167 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 4)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15150 0 169 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15152 0 170 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15154 0 171 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15156 0 172 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15158 0 173 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15160 0 174 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15162 0 175 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15164 0 176 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4~downto~0}~15166 0 178 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 4)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15 0 180 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{95~downto~0}~15 0 186 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 95)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{95~downto~0}~15168 0 193 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 95)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4~downto~0}~15170 0 194 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 4)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4~downto~0}~15172 0 195 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 4)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{9~downto~0}~15 0 206 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 9)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15174 0 210 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15176 0 211 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15 0 213 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15178 0 215 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15180 0 217 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{9~downto~0}~15182 0 229 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 9)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{9~downto~0}~15184 0 231 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 9)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15186 0 240 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15188 0 241 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15190 0 247 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15192 0 248 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~15194 0 254 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15196 0 255 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15198 0 263 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15200 0 264 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15202 0 265 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15204 0 266 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15206 0 267 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15208 0 268 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15210 0 269 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15212 0 270 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15214 0 271 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15216 0 272 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15218 0 273 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{9~downto~0}~15220 0 282 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 9)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15222 0 286 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15224 0 287 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15226 0 289 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15228 0 291 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15230 0 293 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{9~downto~0}~15232 0 299 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 9)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{9~downto~0}~15234 0 300 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 9)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15236 0 301 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15238 0 308 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15240 0 316 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15242 0 317 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15244 0 318 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15246 0 319 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15248 0 320 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15250 0 321 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15252 0 327 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15254 0 333 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15256 0 337 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15258 0 338 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15260 0 340 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15262 0 341 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15264 0 342 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15266 0 343 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15268 0 344 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15270 0 345 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15272 0 346 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15274 0 347 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15276 0 348 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15278 0 349 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15280 0 350 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15282 0 351 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15284 0 352 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15286 0 353 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15288 0 354 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15290 0 355 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15292 0 356 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15294 0 357 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15296 0 358 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15298 0 359 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15300 0 360 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15302 0 361 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15304 0 362 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15306 0 363 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15308 0 364 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15310 0 365 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15312 0 366 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15314 0 367 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15316 0 368 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15318 0 369 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15320 0 370 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15322 0 371 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15324 0 372 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15326 0 374 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15328 0 386 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15330 0 388 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15332 0 397 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15334 0 401 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15336 0 403 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15338 0 404 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15340 0 405 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15342 0 406 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15344 0 407 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15346 0 408 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15348 0 409 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15350 0 410 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15352 0 411 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15354 0 412 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15356 0 413 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15358 0 414 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15360 0 415 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15362 0 416 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15364 0 417 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15366 0 418 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15368 0 428 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~15370 0 434 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15372 0 435 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~15374 0 441 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15376 0 442 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15 0 448 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15378 0 449 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~15380 0 450 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~15382 0 451 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15384 0 460 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15386 0 461 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{10~downto~0}~15 0 470 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 10)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15388 0 474 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15390 0 475 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15392 0 477 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~15394 0 480 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15396 0 481 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15398 0 482 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15400 0 483 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15402 0 484 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15404 0 485 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15406 0 486 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15408 0 487 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15410 0 488 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15412 0 489 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15414 0 490 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15416 0 491 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15418 0 492 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15420 0 493 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15422 0 494 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15424 0 495 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15426 0 496 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15428 0 498 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{8*32-1~downto~0}~15 0 563 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 255)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3*32-1~downto~0}~15 0 565 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 95)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15430 0 567 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{127~downto~0}~15 0 568 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 127)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15432 0 570 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15434 0 572 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15436 0 573 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{23~downto~0}~15 0 574 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 23)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15438 0 575 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15440 0 577 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15442 0 581 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15444 0 582 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15446 0 584 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15448 0 588 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15450 0 589 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{16-1~downto~0}~15 0 592 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{32-1~downto~0}~15 0 596 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{32-1~downto~0}~15452 0 598 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15454 0 608 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15456 0 612 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15458 0 621 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15460 0 622 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15462 0 623 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15464 0 638 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15466 0 652 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15468 0 654 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15470 0 655 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15472 0 664 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15474 0 666 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15476 0 667 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15478 0 670 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~15480 0 672 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15482 0 673 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15484 0 674 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15486 0 675 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15488 0 676 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15490 0 677 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15492 0 678 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15494 0 679 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15496 0 680 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15498 0 681 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15500 0 682 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15502 0 683 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15504 0 684 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15506 0 685 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15508 0 686 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15510 0 687 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15512 0 688 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~15514 0 690 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15516 0 691 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15518 0 692 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15520 0 693 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15522 0 694 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15524 0 695 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15526 0 696 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15528 0 697 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15530 0 698 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15532 0 699 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15534 0 700 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15536 0 701 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15538 0 702 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15540 0 703 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15542 0 704 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15544 0 705 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15546 0 706 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15548 0 708 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15550 0 709 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15552 0 710 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15554 0 711 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15556 0 712 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15558 0 713 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15560 0 714 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15562 0 715 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15564 0 716 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15566 0 717 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15568 0 718 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15570 0 719 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15572 0 720 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15574 0 721 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15576 0 722 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15578 0 723 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15580 0 724 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15582 0 725 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15584 0 726 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15586 0 727 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15588 0 728 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15590 0 729 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15592 0 730 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15594 0 731 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15596 0 732 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15598 0 733 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15600 0 734 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15602 0 735 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15604 0 736 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15606 0 737 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15608 0 738 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15610 0 739 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15612 0 741 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15614 0 742 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15616 0 743 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15618 0 744 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15620 0 745 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15622 0 746 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15624 0 747 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15626 0 748 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15628 0 749 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15630 0 750 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15632 0 751 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15634 0 752 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15636 0 753 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15638 0 754 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15640 0 755 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15642 0 756 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15644 0 757 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15646 0 758 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15648 0 760 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15650 0 761 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15652 0 762 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15654 0 763 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15656 0 765 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15658 0 766 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15660 0 768 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15662 0 769 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15664 0 781 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15666 0 782 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15668 0 786 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15670 0 788 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15672 0 789 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15674 0 790 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15676 0 791 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15678 0 792 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15680 0 793 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15682 0 794 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15684 0 795 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15686 0 796 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15688 0 797 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15690 0 799 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15692 0 800 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15694 0 801 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{23~downto~0}~15696 0 802 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 23)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15698 0 806 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15700 0 807 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15 0 810 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4~downto~0}~15702 0 814 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 4)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15704 0 819 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15706 0 830 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15708 0 834 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15710 0 835 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15712 0 838 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~15714 0 840 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15716 0 842 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15718 0 843 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15720 0 845 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15722 0 846 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15724 0 847 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15726 0 848 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15728 0 849 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15730 0 850 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15732 0 851 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15734 0 852 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15736 0 853 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15738 0 854 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15740 0 855 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15742 0 856 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15744 0 857 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15746 0 858 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15748 0 859 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~15750 0 860 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~15752 0 862 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15754 0 863 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15756 0 864 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15758 0 865 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15760 0 866 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15762 0 867 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15764 0 868 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15766 0 869 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15768 0 870 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15770 0 871 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15772 0 872 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15774 0 873 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15776 0 874 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15778 0 875 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15780 0 876 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15782 0 877 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15784 0 878 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~15786 0 880 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15788 0 881 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15790 0 882 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15792 0 883 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15794 0 884 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15796 0 885 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15798 0 886 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15800 0 887 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15802 0 888 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15804 0 889 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15806 0 890 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15808 0 891 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15810 0 892 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15812 0 893 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15814 0 894 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15816 0 895 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15818 0 896 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15820 0 899 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15822 0 900 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15824 0 901 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15826 0 902 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15828 0 903 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15830 0 904 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15832 0 905 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15834 0 906 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15836 0 907 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15838 0 908 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15840 0 909 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15842 0 910 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15844 0 911 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15846 0 912 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15848 0 913 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15850 0 914 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15852 0 915 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15854 0 918 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15856 0 919 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15858 0 929 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15860 0 930 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15862 0 932 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15864 0 933 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15866 0 935 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15868 0 939 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15870 0 940 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15872 0 941 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15874 0 942 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15876 0 944 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15878 0 945 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15880 0 949 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15882 0 951 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15884 0 952 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15886 0 953 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15888 0 954 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15890 0 955 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15892 0 956 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15894 0 957 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15896 0 958 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15898 0 959 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15900 0 960 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15902 0 961 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15904 0 962 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15906 0 963 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15908 0 964 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15910 0 965 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~15912 0 966 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15914 0 967 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15916 0 970 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15918 0 971 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15920 0 972 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15922 0 973 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15924 0 974 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15926 0 975 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15928 0 976 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15930 0 977 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15932 0 978 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15934 0 979 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15936 0 980 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15938 0 981 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15940 0 982 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15942 0 983 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15944 0 984 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15946 0 985 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15948 0 986 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15950 0 987 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15952 0 989 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15954 0 990 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15956 0 999 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15958 0 1000 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15960 0 1001 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15962 0 1003 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15964 0 1004 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15966 0 1006 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15968 0 1010 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15970 0 1011 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15972 0 1015 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15974 0 1016 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15976 0 1017 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15978 0 1018 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15980 0 1020 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15982 0 1021 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15984 0 1031 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15986 0 1039 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15988 0 1040 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15990 0 1042 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15992 0 1043 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15994 0 1044 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15996 0 1045 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15998 0 1046 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~151000 0 1049 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151002 0 1050 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151004 0 1051 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151006 0 1052 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{23~downto~0}~151008 0 1053 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 23)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151010 0 1056 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151012 0 1057 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151014 0 1060 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~151016 0 1062 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151018 0 1066 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151020 0 1067 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151022 0 1068 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151024 0 1080 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151026 0 1081 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151028 0 1085 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151030 0 1086 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151032 0 1101 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151034 0 1102 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~151036 0 1111 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~151038 0 1114 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4~downto~0}~151040 0 1118 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 4)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151042 0 1120 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151044 0 1135 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{0~downto~0}~15 0 1139 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 0)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~15 0 1140 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~151046 0 1148 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~151048 0 1149 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~151050 0 1150 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151052 0 1151 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151054 0 1152 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151056 0 1156 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151058 0 1164 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151060 0 1168 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151062 0 1169 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151064 0 1170 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151066 0 1171 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151068 0 1180 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151070 0 1185 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~151072 0 1186 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151074 0 1189 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151076 0 1193 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151078 0 1202 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~151080 0 1206 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~151082 0 1207 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151084 0 1208 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151086 0 1209 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~151088 0 1214 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~151090 0 1216 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151092 0 1217 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151094 0 1218 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4~downto~0}~151096 0 1222 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 4)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151098 0 1225 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151100 0 1256 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151102 0 1265 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151104 0 1266 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151106 0 1268 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151108 0 1269 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151110 0 1271 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151112 0 1284 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151114 0 1285 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151116 0 1292 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{5~downto~0}~15 0 1301 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 5)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151118 0 1306 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~151120 0 1308 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151122 0 1311 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151124 0 1314 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151126 0 1325 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151128 0 1332 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151130 0 1333 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151132 0 1339 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151134 0 1349 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151136 0 1350 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151138 0 1359 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151140 0 1363 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{5~downto~0}~151142 0 1374 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 5)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151144 0 1375 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151146 0 1376 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151148 0 1377 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151150 0 1378 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151152 0 1379 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151154 0 1387 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151156 0 1397 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151158 0 1406 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151160 0 1415 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{8~downto~0}~15 0 1416 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 8)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{8~downto~0}~151162 0 1417 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 8)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151164 0 1426 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151166 0 1439 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151168 0 1442 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151170 0 1443 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~151172 0 1444 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151174 0 1448 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151176 0 1449 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~151178 0 1455 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{5~downto~0}~151180 0 1456 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 5)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151182 0 1457 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151184 0 1464 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{26~downto~0}~15 0 1470 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 26)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{26~downto~0}~151186 0 1475 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 26)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151188 0 1476 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~151190 0 1484 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~151192 0 1489 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{10~downto~0}~151194 0 1490 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 10)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151196 0 1499 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151198 0 1500 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151200 0 1511 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151202 0 1512 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151204 0 1517 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151206 0 1518 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151208 0 1525 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151210 0 1526 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151212 0 1527 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151214 0 1528 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151216 0 1529 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151218 0 1530 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151220 0 1531 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151222 0 1532 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151224 0 1533 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151226 0 1534 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151228 0 1535 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151230 0 1536 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151232 0 1537 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151234 0 1538 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151236 0 1539 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151238 0 1540 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151240 0 1541 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151242 0 1542 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151244 0 1547 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151246 0 1548 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151248 0 1549 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151250 0 1556 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151252 0 1557 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151254 0 1558 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151256 0 1559 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151258 0 1560 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151260 0 1561 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151262 0 1562 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151264 0 1563 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151266 0 1564 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151268 0 1565 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151270 0 1566 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151272 0 1567 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151274 0 1568 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151276 0 1569 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151278 0 1570 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151280 0 1571 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151282 0 1572 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151284 0 1573 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151286 0 1575 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151288 0 1584 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151290 0 1585 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151292 0 1586 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151294 0 1587 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~151296 0 1588 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151298 0 1592 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~151300 0 1597 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{6~downto~0}~151302 0 1598 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 6)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{37~downto~0}~151304 0 1599 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 37)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~151306 0 1600 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~151308 0 1601 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{26~downto~0}~151310 0 1603 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 26)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{9~downto~0}~151312 0 1605 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 9)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151314 0 1607 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{10~downto~0}~151316 0 1613 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 10)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{10~downto~0}~151318 0 1614 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 10)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~151320 0 1615 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~151322 0 1622 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151324 0 1628 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151326 0 1629 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151328 0 1633 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151330 0 1637 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151332 0 1664 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151334 0 1665 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151336 0 1673 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151338 0 1674 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151340 0 1675 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151342 0 1676 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151344 0 1677 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151346 0 1678 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151348 0 1679 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151350 0 1690 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~151352 0 1691 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151354 0 1695 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{39~downto~0}~151356 0 1699 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 39)(i 0))))))\r
+ (_subprogram\r
+ (_external resolved (ieee std_logic_1164 15))\r
+ )\r
+ (_type (_external ~extSTD.STANDARD.INTEGER (std STANDARD INTEGER)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_ULOGIC (ieee std_logic_1164 STD_ULOGIC)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC (ieee std_logic_1164 STD_LOGIC)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC_VECTOR (ieee std_logic_1164 STD_LOGIC_VECTOR)))\r
+ )\r
+)\r
+I 000032 55 16782 0 trb_net_std
+(_unit VHDL (trb_net_std 0 7 (trb_net_std 0 180 ))\r
+ (_version v63)\r
+ (_time 1318408980838 2011.10.12 10:43:00)\r
+ (_source (\./../../../trbnet/trb_net_std.vhd\))\r
+ (_use (std(standard))(ieee(std_logic_1164))(ieee(std_logic_arith))(ieee(STD_LOGIC_UNSIGNED)))\r
+ (_parameters dbg)\r
+ (_code 131c45151244450645144412064846)\r
+ (_entity\r
+ (_time 1318408980823)\r
+ (_use (std(standard))(ieee(std_logic_1164))(ieee(std_logic_arith))(ieee(STD_LOGIC_UNSIGNED)))\r
+ )\r
+ (_object\r
+ (_type (_internal channel_config_t 0 9 (_array ~extSTD.STANDARD.INTEGER ((_to (i 0)(i 3))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15 0 10 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal array_32_t 0 10 (_array ~STD_LOGIC_VECTOR{31~downto~0}~15 ((_uto (i -2147483648)(i 2147483647))))))\r
+ (_type (_internal multiplexer_config_t 0 11 (_array ~extSTD.STANDARD.INTEGER ((_to (i 0)(i 7))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15 0 14 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal TRIG_PHYS ~STD_LOGIC_VECTOR{3~downto~0}~15 0 14 (_entity (_string \"0001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~152 0 15 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal TRIG_MDC_CAL ~STD_LOGIC_VECTOR{3~downto~0}~152 0 15 (_entity (_string \"1001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~154 0 16 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal TRIG_SHW_CAL ~STD_LOGIC_VECTOR{3~downto~0}~154 0 16 (_entity (_string \"1010"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~156 0 17 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal TRIG_SHW_PED ~STD_LOGIC_VECTOR{3~downto~0}~156 0 17 (_entity (_string \"1011"\))))\r
+ (_type (_internal ~INTEGER~range~0~to~15~15 0 19 (_scalar (_to (i 0)(i 15)))))\r
+ (_constant (_internal TRIG_SUPPRESS_BIT ~INTEGER~range~0~to~15~15 0 19 (_entity ((i 0)))))\r
+ (_constant (_internal c_DATA_WIDTH ~extSTD.STANDARD.INTEGER 0 26 (_entity ((i 16)))))\r
+ (_constant (_internal c_NUM_WIDTH ~extSTD.STANDARD.INTEGER 0 27 (_entity ((i 3)))))\r
+ (_constant (_internal c_MUX_WIDTH ~extSTD.STANDARD.INTEGER 0 28 (_entity ((i 3)))))\r
+ (_constant (_internal c_TRG_LVL1_CHANNEL ~extSTD.STANDARD.INTEGER 0 32 (_entity ((i 0)))))\r
+ (_constant (_internal c_DATA_CHANNEL ~extSTD.STANDARD.INTEGER 0 33 (_entity ((i 1)))))\r
+ (_constant (_internal c_IPU_CHANNEL ~extSTD.STANDARD.INTEGER 0 34 (_entity ((i 1)))))\r
+ (_constant (_internal c_UNUSED_CHANNEL ~extSTD.STANDARD.INTEGER 0 35 (_entity ((i 2)))))\r
+ (_constant (_internal c_SLOW_CTRL_CHANNEL ~extSTD.STANDARD.INTEGER 0 36 (_entity ((i 3)))))\r
+ (_constant (_internal c_API_ACTIVE ~extSTD.STANDARD.INTEGER 0 39 (_entity ((i 1)))))\r
+ (_constant (_internal c_API_PASSIVE ~extSTD.STANDARD.INTEGER 0 40 (_entity ((i 0)))))\r
+ (_constant (_internal c_SBUF_FULL ~extSTD.STANDARD.INTEGER 0 43 (_entity ((i 0)))))\r
+ (_constant (_internal c_SBUF_FAST ~extSTD.STANDARD.INTEGER 0 44 (_entity ((i 0)))))\r
+ (_constant (_internal c_SBUF_HALF ~extSTD.STANDARD.INTEGER 0 45 (_entity ((i 1)))))\r
+ (_constant (_internal c_SBUF_SLOW ~extSTD.STANDARD.INTEGER 0 46 (_entity ((i 1)))))\r
+ (_constant (_internal c_SECURE_MODE ~extSTD.STANDARD.INTEGER 0 47 (_entity ((i 1)))))\r
+ (_constant (_internal c_NON_SECURE_MODE ~extSTD.STANDARD.INTEGER 0 48 (_entity ((i 0)))))\r
+ (_constant (_internal c_FIFO_NONE ~extSTD.STANDARD.INTEGER 0 51 (_entity ((i 0)))))\r
+ (_constant (_internal c_FIFO_2PCK ~extSTD.STANDARD.INTEGER 0 52 (_entity ((i 1)))))\r
+ (_constant (_internal c_FIFO_SMALL ~extSTD.STANDARD.INTEGER 0 53 (_entity ((i 1)))))\r
+ (_constant (_internal c_FIFO_4PCK ~extSTD.STANDARD.INTEGER 0 54 (_entity ((i 2)))))\r
+ (_constant (_internal c_FIFO_MEDIUM ~extSTD.STANDARD.INTEGER 0 55 (_entity ((i 2)))))\r
+ (_constant (_internal c_FIFO_8PCK ~extSTD.STANDARD.INTEGER 0 56 (_entity ((i 3)))))\r
+ (_constant (_internal c_FIFO_BIG ~extSTD.STANDARD.INTEGER 0 57 (_entity ((i 3)))))\r
+ (_constant (_internal c_FIFO_BRAM ~extSTD.STANDARD.INTEGER 0 58 (_entity ((i 6)))))\r
+ (_constant (_internal c_FIFO_BIGGEST ~extSTD.STANDARD.INTEGER 0 59 (_entity ((i 6)))))\r
+ (_constant (_internal c_FIFO_INFTY ~extSTD.STANDARD.INTEGER 0 60 (_entity ((i 7)))))\r
+ (_constant (_internal c_YES ~extSTD.STANDARD.INTEGER 0 63 (_entity ((i 1)))))\r
+ (_constant (_internal c_NO ~extSTD.STANDARD.INTEGER 0 64 (_entity ((i 0)))))\r
+ (_constant (_internal c_MONITOR ~extSTD.STANDARD.INTEGER 0 65 (_entity ((i 2)))))\r
+ (_constant (_internal std_SBUF_VERSION ~extSTD.STANDARD.INTEGER 0 69 (_entity ((i 0)))))\r
+ (_constant (_internal std_IBUF_SECURE_MODE ~extSTD.STANDARD.INTEGER 0 70 (_entity ((i 1)))))\r
+ (_constant (_internal std_USE_ACKNOWLEDGE ~extSTD.STANDARD.INTEGER 0 71 (_entity ((i 1)))))\r
+ (_constant (_internal std_USE_REPLY_CHANNEL ~extSTD.STANDARD.INTEGER 0 72 (_entity ((i 1)))))\r
+ (_constant (_internal std_FIFO_DEPTH ~extSTD.STANDARD.INTEGER 0 73 (_entity ((i 6)))))\r
+ (_constant (_internal std_DATA_COUNT_WIDTH ~extSTD.STANDARD.INTEGER 0 74 (_entity ((i 7)))))\r
+ (_constant (_internal std_TERM_SECURE_MODE ~extSTD.STANDARD.INTEGER 0 75 (_entity ((i 1)))))\r
+ (_constant (_internal std_MUX_SECURE_MODE ~extSTD.STANDARD.INTEGER 0 76 (_entity ((i 0)))))\r
+ (_constant (_internal std_FORCE_REPLY ~extSTD.STANDARD.INTEGER 0 77 (_entity ((i 1)))))\r
+ (_constant (_internal cfg_USE_CHECKSUM channel_config_t 0 78 (_entity (((i 0))((i 1))((i 0))((i 1))))))\r
+ (_constant (_internal cfg_USE_ACKNOWLEDGE channel_config_t 0 79 (_entity (((i 1))((i 1))((i 0))((i 1))))))\r
+ (_constant (_internal cfg_FORCE_REPLY channel_config_t 0 80 (_entity (((i 1))((i 1))((i 1))((i 1))))))\r
+ (_constant (_internal cfg_USE_REPLY_CHANNEL channel_config_t 0 81 (_entity (((i 1))((i 1))((i 1))((i 1))))))\r
+ (_constant (_internal c_MAX_IDLE_TIME_PER_PACKET ~extSTD.STANDARD.INTEGER 0 82 (_entity ((i 24)))))\r
+ (_constant (_internal std_multipexer_config multiplexer_config_t 0 83 (_entity ((_others(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15 0 86 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal TYPE_DAT ~STD_LOGIC_VECTOR{2~downto~0}~15 0 86 (_entity (_string \"000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~158 0 87 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal TYPE_HDR ~STD_LOGIC_VECTOR{2~downto~0}~158 0 87 (_entity (_string \"001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1510 0 88 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal TYPE_EOB ~STD_LOGIC_VECTOR{2~downto~0}~1510 0 88 (_entity (_string \"010"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1512 0 89 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal TYPE_TRM ~STD_LOGIC_VECTOR{2~downto~0}~1512 0 89 (_entity (_string \"011"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1514 0 90 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal TYPE_ACK ~STD_LOGIC_VECTOR{2~downto~0}~1514 0 90 (_entity (_string \"101"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1516 0 91 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal TYPE_ILLEGAL ~STD_LOGIC_VECTOR{2~downto~0}~1516 0 91 (_entity (_string \"111"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1518 0 94 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal ERROR_OK ~STD_LOGIC_VECTOR{2~downto~0}~1518 0 94 (_entity (_string \"000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1520 0 95 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal ERROR_ENCOD ~STD_LOGIC_VECTOR{2~downto~0}~1520 0 95 (_entity (_string \"001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1522 0 96 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal ERROR_RECOV ~STD_LOGIC_VECTOR{2~downto~0}~1522 0 96 (_entity (_string \"010"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1524 0 97 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal ERROR_FATAL ~STD_LOGIC_VECTOR{2~downto~0}~1524 0 97 (_entity (_string \"011"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1526 0 98 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal ERROR_WAIT ~STD_LOGIC_VECTOR{2~downto~0}~1526 0 98 (_entity (_string \"110"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1528 0 99 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal ERROR_NC ~STD_LOGIC_VECTOR{2~downto~0}~1528 0 99 (_entity (_string \"111"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15 0 103 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_constant (_internal ILLEGAL_ADDRESS ~STD_LOGIC_VECTOR{15~downto~0}~15 0 103 (_entity (_string \"0000000000000000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1530 0 104 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_constant (_internal BROADCAST_ADDRESS ~STD_LOGIC_VECTOR{15~downto~0}~1530 0 104 (_entity (_string \"1111111111111111"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1532 0 107 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_constant (_internal LINK_STARTUP_WORD ~STD_LOGIC_VECTOR{15~downto~0}~1532 0 107 (_entity (_string \"1110000100010000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1534 0 108 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_constant (_internal SET_ADDRESS ~STD_LOGIC_VECTOR{15~downto~0}~1534 0 108 (_entity (_string \"0101111010101101"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1536 0 109 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_constant (_internal ACK_ADDRESS ~STD_LOGIC_VECTOR{15~downto~0}~1536 0 109 (_entity (_string \"1010110010101101"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1538 0 110 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_constant (_internal READ_ID ~STD_LOGIC_VECTOR{15~downto~0}~1538 0 110 (_entity (_string \"0101111000011101"\))))\r
+ (_constant (_internal std_COMSTATREG ~extSTD.STANDARD.INTEGER 0 114 (_entity ((i 8)))))\r
+ (_constant (_internal std_COMCTRLREG ~extSTD.STANDARD.INTEGER 0 115 (_entity ((i 3)))))\r
+ (_constant (_internal std_COMneededwidth ~extSTD.STANDARD.INTEGER 0 117 (_entity ((i 3)))))\r
+ (_constant (_internal c_REGIO_ADDRESS_WIDTH ~extSTD.STANDARD.INTEGER 0 118 (_entity ((i 16)))))\r
+ (_constant (_internal c_REGIO_REGISTER_WIDTH ~extSTD.STANDARD.INTEGER 0 119 (_entity ((i 32)))))\r
+ (_constant (_internal c_REGIO_REG_WIDTH ~extSTD.STANDARD.INTEGER 0 120 (_entity ((i 32)))))\r
+ (_constant (_internal c_regio_timeout_bit ~extSTD.STANDARD.INTEGER 0 121 (_entity ((i 5)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~1540 0 124 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal c_network_control_type ~STD_LOGIC_VECTOR{3~downto~0}~1540 0 124 (_entity (_string \"1111"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~1542 0 125 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal c_read_register_type ~STD_LOGIC_VECTOR{3~downto~0}~1542 0 125 (_entity (_string \"1000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~1544 0 126 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal c_write_register_type ~STD_LOGIC_VECTOR{3~downto~0}~1544 0 126 (_entity (_string \"1001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~1546 0 127 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal c_read_multiple_type ~STD_LOGIC_VECTOR{3~downto~0}~1546 0 127 (_entity (_string \"1010"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~1548 0 128 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal c_write_multiple_type ~STD_LOGIC_VECTOR{3~downto~0}~1548 0 128 (_entity (_string \"1011"\))))\r
+ (_constant (_internal c_BUS_HANDLER_MAX_PORTS ~extSTD.STANDARD.INTEGER 0 130 (_entity ((i 64)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1550 0 131 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal c_BUS_HANDLER_ADDR_t 0 131 (_array ~STD_LOGIC_VECTOR{15~downto~0}~1550 ((_to (i 0)(i 64))))))\r
+ (_type (_internal ~INTEGER~range~0~to~16~15 0 132 (_scalar (_to (i 0)(i 16)))))\r
+ (_type (_internal c_BUS_HANDLER_WIDTH_t 0 132 (_array ~INTEGER~range~0~to~16~15 ((_to (i 0)(i 64))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1553 0 136 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_H0 ~STD_LOGIC_VECTOR{2~downto~0}~1553 0 136 (_entity (_string \"100"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1555 0 137 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F0 ~STD_LOGIC_VECTOR{2~downto~0}~1555 0 137 (_entity (_string \"000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1557 0 138 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F1 ~STD_LOGIC_VECTOR{2~downto~0}~1557 0 138 (_entity (_string \"001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1559 0 139 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F2 ~STD_LOGIC_VECTOR{2~downto~0}~1559 0 139 (_entity (_string \"010"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1561 0 140 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F3 ~STD_LOGIC_VECTOR{2~downto~0}~1561 0 140 (_entity (_string \"011"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1563 0 142 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_H0_next ~STD_LOGIC_VECTOR{2~downto~0}~1563 0 142 (_entity (_string \"011"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1565 0 143 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F0_next ~STD_LOGIC_VECTOR{2~downto~0}~1565 0 143 (_entity (_string \"100"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1567 0 144 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F1_next ~STD_LOGIC_VECTOR{2~downto~0}~1567 0 144 (_entity (_string \"000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1569 0 145 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F2_next ~STD_LOGIC_VECTOR{2~downto~0}~1569 0 145 (_entity (_string \"001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1571 0 146 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F3_next ~STD_LOGIC_VECTOR{2~downto~0}~1571 0 146 (_entity (_string \"010"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1573 0 148 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_max_word_number ~STD_LOGIC_VECTOR{2~downto~0}~1573 0 148 (_entity (_string \"100"\))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~16 0 242 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{27~downto~0}~16 0 243 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 27)(i 0))))))\r
+ (_subprogram\r
+ (_internal and_all 0 0 155 (_entity (_function (_range(_to 0 2147483647 )))))\r
+ (_internal or_all 1 0 157 (_entity (_function (_range(_to 0 2147483647 )))))\r
+ (_internal all_zero 2 0 159 (_entity (_function (_range(_to 0 2147483647 )))))\r
+ (_internal xor_all 3 0 161 (_entity (_function (_range(_to 0 2147483647 )))))\r
+ (_internal get_bit_position 4 0 164 (_entity (_function (_range(_to 0 2147483647 )))))\r
+ (_internal is_time_reached 5 0 167 (_entity (_function )))\r
+ (_internal MAX 6 0 170 (_entity (_function )))\r
+ (_internal Log2 7 0 173 (_entity (_function )))\r
+ (_internal count_ones 8 0 174 (_entity (_function (_range(_to 0 2147483647 )))))\r
+ (_external resolved (ieee std_logic_1164 15))\r
+ )\r
+ (_type (_external ~extSTD.STANDARD.INTEGER (std STANDARD INTEGER)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_ULOGIC (ieee std_logic_1164 STD_ULOGIC)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC (ieee std_logic_1164 STD_LOGIC)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC_VECTOR (ieee std_logic_1164 STD_LOGIC_VECTOR)))\r
+ )\r
+ (_model . trb_net_std 9 -1\r
+ )\r
+)\r
+V 000038 55 8110 0 lattice_ecp2m_fifo
+(_unit VHDL (lattice_ecp2m_fifo 0 8 )\r
+ (_version v63)\r
+ (_time 1318408981496 2011.10.12 10:43:01)\r
+ (_source (\./../../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd\))\r
+ (_use (.(trb_net_std))(std(standard))(ieee(std_logic_1164))(ieee(NUMERIC_STD)))\r
+ (_parameters dbg)\r
+ (_code a4aaa3f3a1f2f4b3a0a3aca7b7fef0)\r
+ (_object\r
+ (_type (_internal ~INTEGER~range~1~to~64~15 0 12 (_scalar (_to (i 1)(i 64)))))\r
+ (_type (_internal ~INTEGER~range~1~to~16~15 0 13 (_scalar (_to (i 1)(i 16)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~15 0 32 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15 0 37 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~154 0 38 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{8~downto~0}~15 0 39 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 8)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~156 0 50 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{8~downto~0}~158 0 55 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 8)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~1510 0 56 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{9~downto~0}~15 0 57 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 9)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~1512 0 68 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{9~downto~0}~1514 0 73 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 9)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~1516 0 74 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{10~downto~0}~15 0 75 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 10)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~1518 0 86 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{10~downto~0}~1520 0 91 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 10)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~1522 0 92 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15 0 93 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~1524 0 104 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1526 0 109 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~1528 0 110 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{12~downto~0}~15 0 111 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 12)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~1530 0 122 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{12~downto~0}~1532 0 127 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 12)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~1534 0 128 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{13~downto~0}~15 0 129 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 13)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~1536 0 140 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{13~downto~0}~1538 0 145 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 13)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~1540 0 146 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{14~downto~0}~15 0 147 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 14)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~1542 0 157 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{14~downto~0}~1544 0 162 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 14)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~1546 0 163 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{14~downto~0}~1548 0 164 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 14)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15 0 174 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1550 0 179 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~1552 0 180 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{8~downto~0}~1554 0 181 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 8)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~1556 0 192 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{8~downto~0}~1558 0 197 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 8)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~1560 0 198 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{9~downto~0}~1562 0 199 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 9)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~1564 0 210 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{9~downto~0}~1566 0 215 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 9)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~1568 0 216 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{10~downto~0}~1570 0 217 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 10)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~1572 0 228 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{10~downto~0}~1574 0 233 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 10)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~1576 0 234 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~1578 0 235 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~1580 0 246 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~1582 0 251 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4~downto~0}~15 0 252 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 4)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{18~downto~0}~15 0 261 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 18)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15 0 266 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~1584 0 267 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{18~downto~0}~1586 0 268 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 18)(i 0))))))\r
+ (_subprogram\r
+ (_external resolved (ieee std_logic_1164 15))\r
+ )\r
+ (_type (_external ~extSTD.STANDARD.INTEGER (std STANDARD INTEGER)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_ULOGIC (ieee std_logic_1164 STD_ULOGIC)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC (ieee std_logic_1164 STD_LOGIC)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC_VECTOR (ieee std_logic_1164 STD_LOGIC_VECTOR)))\r
+ )\r
+)\r
+V 000040 55 116833 0 trb_net_components
+(_unit VHDL (trb_net_components 0 8 )\r
+ (_version v63)\r
+ (_time 1318408982244 2011.10.12 10:43:02)\r
+ (_source (\./../../../trbnet/trb_net_components.vhd\))\r
+ (_use (.(trb_net_std))(std(standard))(ieee(std_logic_1164))(ieee(NUMERIC_STD))(ieee(STD_LOGIC_UNSIGNED)))\r
+ (_parameters dbg)\r
+ (_code 929c969c92c5c487c4c7c5c587c9c7)\r
+ (_object\r
+ (_type (_internal ~INTEGER~range~0~to~3~15 0 18 (_scalar (_to (i 0)(i 3)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15 0 19 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151 0 20 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15 0 29 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15 0 30 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~153 0 33 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~155 0 34 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15 0 49 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~157 0 50 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15 0 51 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~159 0 52 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{5~downto~0}~15 0 74 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 5)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15 0 77 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~1511 0 78 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~1513 0 85 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1515 0 96 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~1517 0 97 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~1519 0 98 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1521 0 99 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~1523 0 105 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~1525 0 106 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1527 0 109 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1529 0 110 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15 0 111 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~1531 0 113 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~1533 0 114 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1535 0 120 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1537 0 121 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~1538 0 132 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~6~15 0 133 (_scalar (_to (i 0)(i 6)))))\r
+ (_type (_internal ~INTEGER~range~1~to~6~15 0 134 (_scalar (_to (i 1)(i 6)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~1539 0 135 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~1540 0 136 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~1541 0 137 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~1542 0 138 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~1543 0 139 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~1544 0 140 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1546 0 141 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15 0 142 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1548 0 143 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~1550 0 153 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~1552 0 154 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15 0 158 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~1554 0 159 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1556 0 161 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~1558 0 163 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~1560 0 164 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1562 0 165 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1564 0 170 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1566 0 171 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1568 0 172 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{10~downto~0}~15 0 173 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 10)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~1570 0 180 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~1572 0 181 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~1574 0 184 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~1576 0 185 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~1578 0 188 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~1580 0 189 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~1582 0 192 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~1584 0 193 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~1586 0 197 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~1588 0 198 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~1590 0 213 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~1592 0 215 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~1594 0 218 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~1596 0 220 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~1598 0 223 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15100 0 225 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15102 0 228 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15104 0 230 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15106 0 234 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15108 0 235 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15110 0 236 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15112 0 237 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15114 0 242 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15116 0 246 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15118 0 247 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15120 0 250 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15122 0 253 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15124 0 256 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{16*3-1~downto~0}~15 0 273 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 47)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3*3-1~downto~0}~15 0 274 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 8)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3-1~downto~0}~15 0 275 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3-1~downto~0}~15126 0 276 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3-1~downto~0}~15128 0 277 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3*4-1~downto~0}~15 0 278 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{32*3-1~downto~0}~15 0 279 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 95)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3-1~downto~0}~15130 0 280 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{16*3-1~downto~0}~15132 0 281 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 47)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{16*3-1~downto~0}~15134 0 282 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 47)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3*3-1~downto~0}~15136 0 283 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 8)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3*3-1~downto~0}~15138 0 284 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 8)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3-1~downto~0}~15140 0 285 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3-1~downto~0}~15142 0 286 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3-1~downto~0}~15144 0 287 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{8*3-1~downto~0}~15 0 288 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 23)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11*3-1~downto~0}~15 0 289 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 32)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15146 0 292 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15148 0 293 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15150 0 294 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15152 0 295 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15154 0 302 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15156 0 307 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15158 0 308 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15160 0 321 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15162 0 322 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15164 0 323 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15166 0 324 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15168 0 332 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15170 0 333 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15172 0 337 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15174 0 338 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15176 0 341 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15178 0 343 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15180 0 344 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15182 0 345 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~1~to~4~15 0 352 (_scalar (_to (i 1)(i 4)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15184 0 353 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15186 0 360 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15188 0 361 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15190 0 362 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15192 0 363 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15208 0 388 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15210 0 392 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{8~downto~0}~15 0 396 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 8)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{12~downto~0}~15 0 397 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 12)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{8~downto~0}~15212 0 398 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 8)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15214 0 401 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15216 0 406 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15218 0 410 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15220 0 419 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15222 0 420 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15224 0 431 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15226 0 432 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~15 0 440 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{0~downto~0}~15 0 441 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 0)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15228 0 474 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~15230 0 475 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15232 0 477 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~15234 0 478 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~7~15 0 498 (_scalar (_to (i 0)(i 7)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15236 0 504 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15238 0 505 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15240 0 506 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15241 0 507 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~6~15242 0 508 (_scalar (_to (i 0)(i 6)))))\r
+ (_type (_internal ~INTEGER~range~0~to~6~15243 0 509 (_scalar (_to (i 0)(i 6)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{4}*32-1~downto~0}~15 0 511 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 511)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{4}-1~downto~0}~15 0 513 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{4}*32-1~downto~0}~15245 0 515 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 511)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15246 0 516 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15248 0 517 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15250 0 518 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15252 0 519 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15254 0 520 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15256 0 521 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15258 0 522 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15260 0 523 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~c_NO~to~c_YES~15 0 525 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~1~to~200~15 0 526 (_scalar (_to (i 1)(i 200)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15262 0 537 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15264 0 538 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15266 0 541 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15268 0 542 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15270 0 544 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15272 0 545 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15274 0 555 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15276 0 556 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15278 0 557 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{23~downto~0}~15 0 558 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 23)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15280 0 560 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15282 0 562 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15284 0 571 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15286 0 572 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15288 0 573 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15290 0 577 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15292 0 583 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15294 0 584 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{std_COMSTATREG*32-1~downto~0}~15 0 588 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 255)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{std_COMCTRLREG*32-1~downto~0}~15 0 589 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 95)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{std_COMSTATREG-1~downto~0}~15 0 592 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{std_COMCTRLREG-1~downto~0}~15 0 593 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{16-1~downto~0}~15 0 597 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{32-1~downto~0}~15 0 600 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{32-1~downto~0}~15296 0 601 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15298 0 608 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15300 0 609 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15302 0 610 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15304 0 615 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15306 0 617 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15308 0 618 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15310 0 619 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~15312 0 620 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15314 0 622 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15316 0 623 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15318 0 624 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15320 0 625 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15322 0 626 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4*32-1~downto~0}~15 0 627 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 127)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15324 0 628 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15326 0 629 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15328 0 630 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15330 0 641 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15332 0 642 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15334 0 643 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~6~15335 0 644 (_scalar (_to (i 0)(i 6)))))\r
+ (_type (_internal ~INTEGER~range~0~to~6~15336 0 645 (_scalar (_to (i 0)(i 6)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{16*32-1~downto~0}~15 0 646 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 511)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15338 0 647 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15340 0 648 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15342 0 649 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15344 0 650 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15346 0 651 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15348 0 652 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~c_NO~to~c_YES~15349 0 654 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15350 0 655 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~1~to~200~15351 0 656 (_scalar (_to (i 1)(i 200)))))\r
+ (_type (_internal ~INTEGER~range~1~to~16~15 0 658 (_scalar (_to (i 1)(i 16)))))\r
+ (_type (_internal ~INTEGER~range~9~to~14~15 0 659 (_scalar (_to (i 9)(i 14)))))\r
+ (_type (_internal ~INTEGER~range~1~to~32~15 0 660 (_scalar (_to (i 1)(i 32)))))\r
+ (_type (_internal ~INTEGER~range~0~to~2**14-2~15 0 661 (_scalar (_to (i 0)(i 16382)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15352 0 662 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~9~to~14~15353 0 663 (_scalar (_to (i 9)(i 14)))))\r
+ (_type (_internal ~INTEGER~range~2**8~to~2**14-2~15 0 664 (_scalar (_to (i 256)(i 16382)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15355 0 675 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15357 0 676 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15359 0 679 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15361 0 680 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15363 0 682 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15365 0 683 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15367 0 693 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15369 0 694 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15371 0 695 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{23~downto~0}~15373 0 696 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 23)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15375 0 697 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{std_COMSTATREG*32-1~downto~0}~15385 0 716 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 255)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{std_COMCTRLREG*32-1~downto~0}~15387 0 717 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 95)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{std_COMSTATREG-1~downto~0}~15389 0 718 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{std_COMCTRLREG-1~downto~0}~15391 0 719 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{16-1~downto~0}~15397 0 726 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{32-1~downto~0}~15399 0 727 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{32-1~downto~0}~15401 0 731 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15403 0 741 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15405 0 744 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15407 0 745 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15409 0 746 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~15411 0 747 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15413 0 750 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15415 0 751 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15417 0 752 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15419 0 753 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15421 0 754 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15423 0 755 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4*32-1~downto~0}~15425 0 756 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 127)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15427 0 757 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15429 0 758 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15431 0 759 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15433 0 774 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15435 0 775 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~6~15436 0 776 (_scalar (_to (i 0)(i 6)))))\r
+ (_type (_internal ~INTEGER~range~0~to~6~15437 0 777 (_scalar (_to (i 0)(i 6)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{4}*32-1~downto~0}~15439 0 779 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 511)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{4}-1~downto~0}~15441 0 781 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{4}*32-1~downto~0}~15443 0 783 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 511)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15444 0 784 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15446 0 785 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15448 0 786 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15450 0 787 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15452 0 788 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15454 0 789 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15456 0 790 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15458 0 791 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~c_NO~to~c_YES~15459 0 793 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~1~to~200~15460 0 794 (_scalar (_to (i 1)(i 200)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15462 0 803 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15464 0 804 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15466 0 808 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15468 0 809 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15470 0 812 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15472 0 813 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15474 0 817 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15476 0 818 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{23~downto~0}~15478 0 819 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 23)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15480 0 820 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15482 0 821 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15484 0 826 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15486 0 827 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15488 0 828 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15490 0 829 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15492 0 831 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15494 0 834 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{std_COMSTATREG*32-1~downto~0}~15496 0 838 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 255)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{std_COMCTRLREG*32-1~downto~0}~15498 0 839 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 95)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{std_COMSTATREG-1~downto~0}~15504 0 842 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{std_COMCTRLREG-1~downto~0}~15506 0 843 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{16-1~downto~0}~15512 0 847 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{32-1~downto~0}~15514 0 850 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{32-1~downto~0}~15516 0 851 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15518 0 860 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15520 0 862 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15522 0 863 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15524 0 864 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~15526 0 865 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15528 0 866 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15530 0 867 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15 0 884 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15532 0 885 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15534 0 888 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15536 0 889 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15538 0 893 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15540 0 899 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15541 0 912 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15542 0 913 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15544 0 920 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~15546 0 921 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15548 0 923 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~15550 0 924 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{10~downto~0}~15552 0 926 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 10)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15554 0 945 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15556 0 946 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15558 0 949 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15560 0 963 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{17~downto~0}~15562 0 970 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 17)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~1~to~16~15563 0 1059 (_scalar (_to (i 1)(i 16)))))\r
+ (_type (_internal ~INTEGER~range~9~to~14~15564 0 1060 (_scalar (_to (i 9)(i 14)))))\r
+ (_type (_internal ~INTEGER~range~1~to~32~15565 0 1061 (_scalar (_to (i 1)(i 32)))))\r
+ (_type (_internal ~INTEGER~range~0~to~2**14-1~15 0 1062 (_scalar (_to (i 0)(i 16383)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15566 0 1063 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~9~to~14~15567 0 1064 (_scalar (_to (i 9)(i 14)))))\r
+ (_type (_internal ~INTEGER~range~2**8~to~2**14-1~15 0 1065 (_scalar (_to (i 256)(i 16383)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15569 0 1074 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{23~downto~0}~15571 0 1075 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 23)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15573 0 1076 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15575 0 1077 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15577 0 1078 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15593 0 1094 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15597 0 1101 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15599 0 1104 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~1~to~7~15 0 1115 (_scalar (_to (i 1)(i 7)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15611 0 1127 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15613 0 1132 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15615 0 1133 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15617 0 1134 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15619 0 1136 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15621 0 1140 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15623 0 1141 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15625 0 1144 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15626 0 1153 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15628 0 1164 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15630 0 1165 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15632 0 1166 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{23~downto~0}~15634 0 1167 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 23)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15636 0 1168 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15638 0 1171 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15640 0 1173 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15642 0 1181 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15644 0 1187 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15646 0 1191 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15648 0 1194 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15650 0 1196 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~1~to~16~15651 0 1206 (_scalar (_to (i 1)(i 16)))))\r
+ (_type (_internal ~INTEGER~range~9~to~14~15652 0 1207 (_scalar (_to (i 9)(i 14)))))\r
+ (_type (_internal ~INTEGER~range~1~to~32~15653 0 1208 (_scalar (_to (i 1)(i 32)))))\r
+ (_type (_internal ~INTEGER~range~0~to~2**14-1~15654 0 1209 (_scalar (_to (i 0)(i 16383)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15655 0 1210 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~9~to~14~15656 0 1211 (_scalar (_to (i 9)(i 14)))))\r
+ (_type (_internal ~INTEGER~range~2**8~to~2**14-1~15657 0 1212 (_scalar (_to (i 256)(i 16383)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15659 0 1222 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15661 0 1225 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15663 0 1226 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15665 0 1227 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{23~downto~0}~15667 0 1228 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 23)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15669 0 1229 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15671 0 1233 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15673 0 1234 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15675 0 1235 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15677 0 1237 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15679 0 1241 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15681 0 1242 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{127~downto~0}~15 0 1257 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 127)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15697 0 1259 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~15699 0 1260 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15701 0 1261 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4~downto~0}~15 0 1262 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 4)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15703 0 1268 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15705 0 1269 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~7~15706 0 1282 (_scalar (_to (i 0)(i 7)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15707 0 1283 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15708 0 1284 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15709 0 1285 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15710 0 1286 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15711 0 1287 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15712 0 1288 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15714 0 1297 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15716 0 1298 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15718 0 1300 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15720 0 1302 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15722 0 1303 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15724 0 1306 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15726 0 1307 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15728 0 1310 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15730 0 1312 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15732 0 1313 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15734 0 1314 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15736 0 1315 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~15 0 1326 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{35~downto~0}~15738 0 1331 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 35)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~6~15739 0 1362 (_scalar (_to (i 0)(i 6)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15740 0 1363 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15741 0 1364 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~6~15742 0 1365 (_scalar (_to (i 0)(i 6)))))\r
+ (_type (_internal ~INTEGER~range~2~to~7~15 0 1366 (_scalar (_to (i 2)(i 7)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15743 0 1367 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15744 0 1368 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15745 0 1369 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15746 0 1370 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15747 0 1371 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15748 0 1372 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15749 0 1373 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15751 0 1382 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15753 0 1383 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15755 0 1386 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15757 0 1387 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15759 0 1390 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15761 0 1391 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15763 0 1393 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15765 0 1396 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15767 0 1397 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15769 0 1400 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15771 0 1401 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15773 0 1404 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15775 0 1405 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15777 0 1408 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15779 0 1409 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15781 0 1412 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15783 0 1413 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15785 0 1414 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15787 0 1415 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15789 0 1416 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15791 0 1417 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15793 0 1418 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15795 0 1419 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~15797 0 1420 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15799 0 1421 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15801 0 1441 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15803 0 1442 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15805 0 1445 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15807 0 1446 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{c_MUX_WIDTH-1}*c_DATA_WIDTH-1~downto~0}~15 0 1449 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{c_MUX_WIDTH-1}*c_NUM_WIDTH-1~downto~0}~15 0 1450 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{c_MUX_WIDTH-1}-1~downto~0}~15 0 1451 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{c_MUX_WIDTH-1}-1~downto~0}~15809 0 1452 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**c_MUX_WIDTH-1~downto~0}~15 0 1453 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH*{2**c_MUX_WIDTH}-1~downto~0}~15 0 1454 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 127)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH*{2**c_MUX_WIDTH}-1~downto~0}~15 0 1455 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 23)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**c_MUX_WIDTH-1~downto~0}~15811 0 1456 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15813 0 1458 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15815 0 1459 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~c_NO~to~c_YES~15816 0 1469 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15818 0 1477 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15820 0 1478 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15822 0 1482 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15824 0 1483 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15826 0 1486 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15828 0 1487 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15830 0 1488 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15832 0 1493 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15834 0 1494 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15836 0 1495 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15838 0 1498 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15840 0 1499 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15842 0 1500 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15844 0 1501 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15846 0 1505 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15848 0 1511 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15850 0 1512 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15852 0 1514 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15853 0 1520 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15854 0 1521 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15856 0 1530 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15858 0 1531 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15860 0 1534 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15862 0 1536 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15864 0 1537 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15866 0 1543 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15868 0 1548 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15870 0 1549 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15872 0 1552 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15874 0 1553 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15876 0 1554 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15878 0 1562 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15880 0 1563 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15882 0 1564 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15884 0 1565 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15886 0 1567 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15888 0 1571 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15890 0 1572 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15892 0 1574 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15894 0 1577 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15896 0 1590 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15898 0 1602 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15900 0 1603 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15902 0 1604 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15904 0 1606 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15906 0 1607 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15908 0 1609 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15910 0 1613 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15912 0 1614 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15914 0 1618 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15916 0 1619 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15918 0 1620 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15920 0 1621 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15922 0 1623 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15924 0 1624 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~15926 0 1648 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~15928 0 1649 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15930 0 1657 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15932 0 1658 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15934 0 1659 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~1~to~10~15 0 1672 (_scalar (_to (i 1)(i 10)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15936 0 1681 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15938 0 1682 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15940 0 1686 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15942 0 1687 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15944 0 1691 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~15946 0 1693 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~15948 0 1694 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~15950 0 1696 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15952 0 1699 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15954 0 1700 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15956 0 1702 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15958 0 1703 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15960 0 1722 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15962 0 1723 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~15964 0 1726 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~15966 0 1727 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15968 0 1739 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15970 0 1740 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{127~downto~0}~15972 0 1741 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 127)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~15974 0 1742 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15976 0 1743 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~15977 0 1756 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH*4-1~downto~0}~15 0 1765 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH*4-1~downto~0}~15 0 1766 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15979 0 1767 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15981 0 1768 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH*4-1~downto~0}~15983 0 1769 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH*4-1~downto~0}~15985 0 1770 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15987 0 1771 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15989 0 1772 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15991 0 1774 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15993 0 1775 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15995 0 1776 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15997 0 1777 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15999 0 1778 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151001 0 1780 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151003 0 1781 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{127~downto~0}~151005 0 1782 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 127)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{255~downto~0}~15 0 1783 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 255)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151007 0 1784 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151008 0 1794 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH*4-1~downto~0}~151010 0 1804 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH*4-1~downto~0}~151012 0 1805 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151014 0 1806 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151016 0 1807 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH*4-1~downto~0}~151018 0 1808 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH*4-1~downto~0}~151020 0 1809 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151022 0 1810 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151024 0 1811 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151026 0 1814 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151028 0 1815 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151030 0 1816 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151032 0 1817 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151034 0 1818 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151036 0 1821 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151038 0 1822 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{511~downto~0}~15 0 1823 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 511)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{255~downto~0}~151040 0 1824 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 255)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151042 0 1825 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~3~151043 0 1835 (_scalar (_to (i 0)(i 3)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151044 0 1836 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151046 0 1845 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151048 0 1846 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151050 0 1849 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151052 0 1850 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151054 0 1865 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151056 0 1866 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151058 0 1867 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151060 0 1868 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~3~151061 0 1878 (_scalar (_to (i 0)(i 3)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151062 0 1879 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151063 0 1880 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151065 0 1889 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151067 0 1890 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151069 0 1893 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151071 0 1894 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151073 0 1909 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151075 0 1910 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151077 0 1911 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151079 0 1912 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151080 0 1921 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4*c_DATA_WIDTH-1~downto~0}~15 0 1931 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4*c_NUM_WIDTH-1~downto~0}~15 0 1932 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151082 0 1933 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151084 0 1934 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4*c_DATA_WIDTH-1~downto~0}~151086 0 1935 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4*c_NUM_WIDTH-1~downto~0}~151088 0 1936 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151090 0 1937 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151092 0 1938 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151094 0 1941 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151096 0 1942 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151098 0 1943 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151100 0 1944 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151102 0 1947 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151104 0 1948 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151106 0 1949 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4*16-1~downto~0}~15 0 1951 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4*16-1~downto~0}~151108 0 1952 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151110 0 1953 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151112 0 1954 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151113 0 1962 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4*c_DATA_WIDTH-1~downto~0}~151115 0 1972 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4*c_NUM_WIDTH-1~downto~0}~151117 0 1973 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151119 0 1974 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151121 0 1975 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4*c_DATA_WIDTH-1~downto~0}~151123 0 1976 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4*c_NUM_WIDTH-1~downto~0}~151125 0 1977 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151127 0 1978 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151129 0 1979 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151131 0 1982 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151133 0 1983 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151135 0 1984 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151137 0 1985 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151139 0 1988 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151141 0 1989 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151143 0 1990 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4*16-1~downto~0}~151145 0 1992 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4*16-1~downto~0}~151147 0 1993 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151149 0 1994 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151151 0 1995 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151153 0 2010 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151155 0 2011 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151157 0 2014 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151159 0 2015 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151161 0 2019 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151163 0 2022 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151165 0 2026 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151167 0 2027 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151169 0 2028 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151171 0 2045 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151173 0 2046 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151175 0 2049 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151177 0 2050 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151179 0 2054 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151181 0 2058 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151183 0 2063 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151185 0 2064 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151187 0 2065 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151189 0 2081 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151191 0 2085 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151193 0 2092 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151195 0 2093 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151197 0 2096 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151199 0 2097 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151201 0 2098 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{100~downto~0}~15 0 2099 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 100)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151203 0 2100 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151205 0 2101 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151206 0 2112 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151208 0 2123 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~151210 0 2124 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~15 0 2126 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151212 0 2127 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151214 0 2142 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~151216 0 2143 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{11~downto~0}~151218 0 2145 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 11)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151220 0 2146 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151221 0 2158 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151222 0 2159 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~6~151223 0 2160 (_scalar (_to (i 0)(i 6)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151225 0 2169 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151227 0 2170 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151229 0 2174 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151231 0 2175 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151233 0 2178 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151235 0 2179 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151237 0 2180 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151239 0 2181 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1~downto~0}~151241 0 2182 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 1)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151243 0 2201 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151245 0 2202 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151247 0 2205 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151249 0 2206 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151251 0 2207 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{9~downto~0}~15 0 2308 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 9)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~6~151272 0 2366 (_scalar (_to (i 0)(i 6)))))\r
+ (_type (_internal ~INTEGER~range~0~to~6~151273 0 2367 (_scalar (_to (i 0)(i 6)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{4}*32-1~downto~0}~151275 0 2369 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 511)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{4}-1~downto~0}~151277 0 2371 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{4}*32-1~downto~0}~151279 0 2373 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 511)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151280 0 2374 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151282 0 2375 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151284 0 2376 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151286 0 2377 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151288 0 2378 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151290 0 2379 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151292 0 2380 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151294 0 2381 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~1~to~200~151295 0 2382 (_scalar (_to (i 1)(i 200)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151297 0 2390 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151299 0 2391 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151301 0 2395 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151303 0 2396 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151305 0 2399 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151307 0 2400 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~151309 0 2401 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151311 0 2406 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151313 0 2409 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151315 0 2410 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~151317 0 2411 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151319 0 2415 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151321 0 2417 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151323 0 2418 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151325 0 2419 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{std_COMSTATREG*c_REGIO_REG_WIDTH-1~downto~0}~15 0 2424 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 255)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{std_COMCTRLREG*c_REGIO_REG_WIDTH-1~downto~0}~15 0 2425 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 95)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{{std_COMSTATREG}-1~downto~0}~15 0 2429 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{{std_COMCTRLREG}-1~downto~0}~15 0 2430 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_REGIO_ADDRESS_WIDTH-1~downto~0}~15 0 2434 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_REGIO_REG_WIDTH-1~downto~0}~15 0 2437 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_REGIO_REG_WIDTH-1~downto~0}~151327 0 2438 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151329 0 2446 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151331 0 2447 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~1~to~c_BUS_HANDLER_MAX_PORTS~15 0 2457 (_scalar (_to (i 1)(i 64)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151333 0 2464 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151335 0 2465 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151337 0 2466 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151351 0 2487 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151353 0 2496 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151355 0 2508 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151357 0 2516 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151359 0 2517 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151361 0 2518 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151363 0 2519 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151365 0 2520 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151367 0 2521 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151369 0 2522 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151371 0 2523 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~151373 0 2527 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151375 0 2528 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151377 0 2540 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151379 0 2547 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~151381 0 2550 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151383 0 2553 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151385 0 2556 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151387 0 2564 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{95~downto~0}~15 0 2565 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 95)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151389 0 2585 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151391 0 2586 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151393 0 2589 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151395 0 2590 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151397 0 2593 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151401 0 2619 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{18~downto~0}~15 0 2697 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 18)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{18~downto~0}~151415 0 2700 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 18)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151417 0 2703 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151419 0 2704 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4~downto~0}~151421 0 2705 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 4)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{18~downto~0}~151423 0 2719 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 18)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{18~downto~0}~151425 0 2722 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 18)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151427 0 2725 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151429 0 2726 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4~downto~0}~151431 0 2727 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 4)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151433 0 2738 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151435 0 2743 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151437 0 2744 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151439 0 2747 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151441 0 2748 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151443 0 2750 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151445 0 2758 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151447 0 2769 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151449 0 2770 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151451 0 2772 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151453 0 2773 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151455 0 2775 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{5~downto~0}~151457 0 2786 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 5)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151459 0 2790 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151461 0 2791 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151463 0 2793 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151465 0 2794 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151467 0 2795 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{63~downto~0}~151469 0 2798 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151471 0 2805 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151473 0 2806 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{5~downto~0}~151475 0 2807 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 5)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151477 0 2808 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151479 0 2817 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151481 0 2818 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151483 0 2829 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151485 0 2830 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151487 0 2831 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151489 0 2832 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151491 0 2833 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151493 0 2834 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151495 0 2836 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151497 0 2838 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151499 0 2846 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151501 0 2847 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{0~downto~0}~151503 0 2864 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 0)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151505 0 2865 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151507 0 2866 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151509 0 2873 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151511 0 2874 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151513 0 2875 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151515 0 2878 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151520 0 2909 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151521 0 2911 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151523 0 2922 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151525 0 2923 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151527 0 2927 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151529 0 2928 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151531 0 2930 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151533 0 2945 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151535 0 2946 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151537 0 2949 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151539 0 2950 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151541 0 2953 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151543 0 2954 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151544 0 2965 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151545 0 2966 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151547 0 2975 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151549 0 2976 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~151551 0 2978 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151553 0 2981 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151555 0 2982 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~151557 0 2984 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151559 0 2986 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151560 0 2995 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~151561 0 2997 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151563 0 3008 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151565 0 3009 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH-1~downto~0}~151567 0 3013 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH-1~downto~0}~151569 0 3014 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~151571 0 3018 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151573 0 3019 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151575 0 3020 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{23~downto~0}~151577 0 3021 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 23)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151579 0 3024 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151581 0 3037 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~151583 0 3038 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151585 0 3042 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151587 0 3046 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~151589 0 3049 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151591 0 3054 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151593 0 3055 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH*2**{c_MUX_WIDTH}-1~downto~0}~15 0 3086 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 127)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH*2**{c_MUX_WIDTH}-1~downto~0}~15 0 3087 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 23)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{c_MUX_WIDTH}-1~downto~0}~15 0 3088 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{c_MUX_WIDTH}-1~downto~0}~151595 0 3089 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{c_MUX_WIDTH}-1~downto~0}~151597 0 3090 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{4*2**{c_MUX_WIDTH}-1~downto~0}~15 0 3091 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{32*2**{c_MUX_WIDTH}-1~downto~0}~15 0 3092 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 255)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{c_MUX_WIDTH}-1~downto~0}~151599 0 3093 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{16*2**{c_MUX_WIDTH}-1~downto~0}~15 0 3094 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 127)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_DATA_WIDTH*2**{c_MUX_WIDTH}-1~downto~0}~151601 0 3095 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 127)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{c_NUM_WIDTH*2**{c_MUX_WIDTH}-1~downto~0}~151603 0 3096 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 23)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3*2**{c_MUX_WIDTH}-1~downto~0}~15 0 3097 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 23)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{c_MUX_WIDTH}-1~downto~0}~151605 0 3098 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{c_MUX_WIDTH}-1~downto~0}~151607 0 3099 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2**{c_MUX_WIDTH}-1~downto~0}~151609 0 3100 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{8*2**{c_MUX_WIDTH}-1~downto~0}~15 0 3101 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 63)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151611 0 3104 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151613 0 3105 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~151615 0 3107 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151617 0 3108 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~151619 0 3109 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_subprogram\r
+ (_external resolved (ieee std_logic_1164 15))\r
+ )\r
+ (_type (_external ~extSTD.STANDARD.INTEGER (std STANDARD INTEGER)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_ULOGIC (ieee std_logic_1164 STD_ULOGIC)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC (ieee std_logic_1164 STD_LOGIC)))\r
+ (_variable (_external work.trb_net_std.c_DATA_WIDTH(. trb_net_std c_DATA_WIDTH)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC_VECTOR (ieee std_logic_1164 STD_LOGIC_VECTOR)))\r
+ (_variable (_external work.trb_net_std.c_NUM_WIDTH(. trb_net_std c_NUM_WIDTH)))\r
+ (_type (_external ~extwork.trb_net_std.channel_config_t (. trb_net_std channel_config_t)))\r
+ (_variable (_external work.trb_net_std.c_NO(. trb_net_std c_NO)))\r
+ (_variable (_external work.trb_net_std.c_YES(. trb_net_std c_YES)))\r
+ (_variable (_external work.trb_net_std.std_COMSTATREG(. trb_net_std std_COMSTATREG)))\r
+ (_variable (_external work.trb_net_std.std_COMCTRLREG(. trb_net_std std_COMCTRLREG)))\r
+ (_type (_external ~extwork.trb_net_std.multiplexer_config_t (. trb_net_std multiplexer_config_t)))\r
+ (_variable (_external work.trb_net_std.c_MUX_WIDTH(. trb_net_std c_MUX_WIDTH)))\r
+ (_variable (_external work.trb_net_std.c_REGIO_REG_WIDTH(. trb_net_std c_REGIO_REG_WIDTH)))\r
+ (_variable (_external work.trb_net_std.c_REGIO_ADDRESS_WIDTH(. trb_net_std c_REGIO_ADDRESS_WIDTH)))\r
+ (_variable (_external work.trb_net_std.c_BUS_HANDLER_MAX_PORTS(. trb_net_std c_BUS_HANDLER_MAX_PORTS)))\r
+ (_type (_external ~extwork.trb_net_std.~STD_LOGIC_VECTOR{15~downto~0}~1550 (. trb_net_std ~STD_LOGIC_VECTOR{15~downto~0}~1550)))\r
+ (_type (_external ~extwork.trb_net_std.c_BUS_HANDLER_ADDR_t (. trb_net_std c_BUS_HANDLER_ADDR_t)))\r
+ (_type (_external ~extwork.trb_net_std.~INTEGER~range~0~to~16~15 (. trb_net_std ~INTEGER~range~0~to~16~15)))\r
+ (_type (_external ~extwork.trb_net_std.c_BUS_HANDLER_WIDTH_t (. trb_net_std c_BUS_HANDLER_WIDTH_t)))\r
+ )\r
+)\r
+V 000032 55 16782 0 trb_net_std
+(_unit VHDL (trb_net_std 0 7 (trb_net_std 0 180 ))\r
+ (_version v63)\r
+ (_time 1318408983822 2011.10.12 10:43:03)\r
+ (_source (\./../../../trbnet/trb_net_std.vhd\))\r
+ (_use (std(standard))(ieee(std_logic_1164))(ieee(std_logic_arith))(ieee(STD_LOGIC_UNSIGNED)))\r
+ (_parameters dbg)\r
+ (_code bcb2bee9edebeaa9eabbebbda9e7e9)\r
+ (_entity\r
+ (_time 1318408980822)\r
+ (_use (std(standard))(ieee(std_logic_1164))(ieee(std_logic_arith))(ieee(STD_LOGIC_UNSIGNED)))\r
+ )\r
+ (_object\r
+ (_type (_internal channel_config_t 0 9 (_array ~extSTD.STANDARD.INTEGER ((_to (i 0)(i 3))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~15 0 10 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal array_32_t 0 10 (_array ~STD_LOGIC_VECTOR{31~downto~0}~15 ((_uto (i -2147483648)(i 2147483647))))))\r
+ (_type (_internal multiplexer_config_t 0 11 (_array ~extSTD.STANDARD.INTEGER ((_to (i 0)(i 7))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~15 0 14 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal TRIG_PHYS ~STD_LOGIC_VECTOR{3~downto~0}~15 0 14 (_entity (_string \"0001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~152 0 15 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal TRIG_MDC_CAL ~STD_LOGIC_VECTOR{3~downto~0}~152 0 15 (_entity (_string \"1001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~154 0 16 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal TRIG_SHW_CAL ~STD_LOGIC_VECTOR{3~downto~0}~154 0 16 (_entity (_string \"1010"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~156 0 17 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal TRIG_SHW_PED ~STD_LOGIC_VECTOR{3~downto~0}~156 0 17 (_entity (_string \"1011"\))))\r
+ (_type (_internal ~INTEGER~range~0~to~15~15 0 19 (_scalar (_to (i 0)(i 15)))))\r
+ (_constant (_internal TRIG_SUPPRESS_BIT ~INTEGER~range~0~to~15~15 0 19 (_entity ((i 0)))))\r
+ (_constant (_internal c_DATA_WIDTH ~extSTD.STANDARD.INTEGER 0 26 (_entity ((i 16)))))\r
+ (_constant (_internal c_NUM_WIDTH ~extSTD.STANDARD.INTEGER 0 27 (_entity ((i 3)))))\r
+ (_constant (_internal c_MUX_WIDTH ~extSTD.STANDARD.INTEGER 0 28 (_entity ((i 3)))))\r
+ (_constant (_internal c_TRG_LVL1_CHANNEL ~extSTD.STANDARD.INTEGER 0 32 (_entity ((i 0)))))\r
+ (_constant (_internal c_DATA_CHANNEL ~extSTD.STANDARD.INTEGER 0 33 (_entity ((i 1)))))\r
+ (_constant (_internal c_IPU_CHANNEL ~extSTD.STANDARD.INTEGER 0 34 (_entity ((i 1)))))\r
+ (_constant (_internal c_UNUSED_CHANNEL ~extSTD.STANDARD.INTEGER 0 35 (_entity ((i 2)))))\r
+ (_constant (_internal c_SLOW_CTRL_CHANNEL ~extSTD.STANDARD.INTEGER 0 36 (_entity ((i 3)))))\r
+ (_constant (_internal c_API_ACTIVE ~extSTD.STANDARD.INTEGER 0 39 (_entity ((i 1)))))\r
+ (_constant (_internal c_API_PASSIVE ~extSTD.STANDARD.INTEGER 0 40 (_entity ((i 0)))))\r
+ (_constant (_internal c_SBUF_FULL ~extSTD.STANDARD.INTEGER 0 43 (_entity ((i 0)))))\r
+ (_constant (_internal c_SBUF_FAST ~extSTD.STANDARD.INTEGER 0 44 (_entity ((i 0)))))\r
+ (_constant (_internal c_SBUF_HALF ~extSTD.STANDARD.INTEGER 0 45 (_entity ((i 1)))))\r
+ (_constant (_internal c_SBUF_SLOW ~extSTD.STANDARD.INTEGER 0 46 (_entity ((i 1)))))\r
+ (_constant (_internal c_SECURE_MODE ~extSTD.STANDARD.INTEGER 0 47 (_entity ((i 1)))))\r
+ (_constant (_internal c_NON_SECURE_MODE ~extSTD.STANDARD.INTEGER 0 48 (_entity ((i 0)))))\r
+ (_constant (_internal c_FIFO_NONE ~extSTD.STANDARD.INTEGER 0 51 (_entity ((i 0)))))\r
+ (_constant (_internal c_FIFO_2PCK ~extSTD.STANDARD.INTEGER 0 52 (_entity ((i 1)))))\r
+ (_constant (_internal c_FIFO_SMALL ~extSTD.STANDARD.INTEGER 0 53 (_entity ((i 1)))))\r
+ (_constant (_internal c_FIFO_4PCK ~extSTD.STANDARD.INTEGER 0 54 (_entity ((i 2)))))\r
+ (_constant (_internal c_FIFO_MEDIUM ~extSTD.STANDARD.INTEGER 0 55 (_entity ((i 2)))))\r
+ (_constant (_internal c_FIFO_8PCK ~extSTD.STANDARD.INTEGER 0 56 (_entity ((i 3)))))\r
+ (_constant (_internal c_FIFO_BIG ~extSTD.STANDARD.INTEGER 0 57 (_entity ((i 3)))))\r
+ (_constant (_internal c_FIFO_BRAM ~extSTD.STANDARD.INTEGER 0 58 (_entity ((i 6)))))\r
+ (_constant (_internal c_FIFO_BIGGEST ~extSTD.STANDARD.INTEGER 0 59 (_entity ((i 6)))))\r
+ (_constant (_internal c_FIFO_INFTY ~extSTD.STANDARD.INTEGER 0 60 (_entity ((i 7)))))\r
+ (_constant (_internal c_YES ~extSTD.STANDARD.INTEGER 0 63 (_entity ((i 1)))))\r
+ (_constant (_internal c_NO ~extSTD.STANDARD.INTEGER 0 64 (_entity ((i 0)))))\r
+ (_constant (_internal c_MONITOR ~extSTD.STANDARD.INTEGER 0 65 (_entity ((i 2)))))\r
+ (_constant (_internal std_SBUF_VERSION ~extSTD.STANDARD.INTEGER 0 69 (_entity ((i 0)))))\r
+ (_constant (_internal std_IBUF_SECURE_MODE ~extSTD.STANDARD.INTEGER 0 70 (_entity ((i 1)))))\r
+ (_constant (_internal std_USE_ACKNOWLEDGE ~extSTD.STANDARD.INTEGER 0 71 (_entity ((i 1)))))\r
+ (_constant (_internal std_USE_REPLY_CHANNEL ~extSTD.STANDARD.INTEGER 0 72 (_entity ((i 1)))))\r
+ (_constant (_internal std_FIFO_DEPTH ~extSTD.STANDARD.INTEGER 0 73 (_entity ((i 6)))))\r
+ (_constant (_internal std_DATA_COUNT_WIDTH ~extSTD.STANDARD.INTEGER 0 74 (_entity ((i 7)))))\r
+ (_constant (_internal std_TERM_SECURE_MODE ~extSTD.STANDARD.INTEGER 0 75 (_entity ((i 1)))))\r
+ (_constant (_internal std_MUX_SECURE_MODE ~extSTD.STANDARD.INTEGER 0 76 (_entity ((i 0)))))\r
+ (_constant (_internal std_FORCE_REPLY ~extSTD.STANDARD.INTEGER 0 77 (_entity ((i 1)))))\r
+ (_constant (_internal cfg_USE_CHECKSUM channel_config_t 0 78 (_entity (((i 0))((i 1))((i 0))((i 1))))))\r
+ (_constant (_internal cfg_USE_ACKNOWLEDGE channel_config_t 0 79 (_entity (((i 1))((i 1))((i 0))((i 1))))))\r
+ (_constant (_internal cfg_FORCE_REPLY channel_config_t 0 80 (_entity (((i 1))((i 1))((i 1))((i 1))))))\r
+ (_constant (_internal cfg_USE_REPLY_CHANNEL channel_config_t 0 81 (_entity (((i 1))((i 1))((i 1))((i 1))))))\r
+ (_constant (_internal c_MAX_IDLE_TIME_PER_PACKET ~extSTD.STANDARD.INTEGER 0 82 (_entity ((i 24)))))\r
+ (_constant (_internal std_multipexer_config multiplexer_config_t 0 83 (_entity ((_others(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~15 0 86 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal TYPE_DAT ~STD_LOGIC_VECTOR{2~downto~0}~15 0 86 (_entity (_string \"000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~158 0 87 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal TYPE_HDR ~STD_LOGIC_VECTOR{2~downto~0}~158 0 87 (_entity (_string \"001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1510 0 88 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal TYPE_EOB ~STD_LOGIC_VECTOR{2~downto~0}~1510 0 88 (_entity (_string \"010"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1512 0 89 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal TYPE_TRM ~STD_LOGIC_VECTOR{2~downto~0}~1512 0 89 (_entity (_string \"011"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1514 0 90 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal TYPE_ACK ~STD_LOGIC_VECTOR{2~downto~0}~1514 0 90 (_entity (_string \"101"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1516 0 91 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal TYPE_ILLEGAL ~STD_LOGIC_VECTOR{2~downto~0}~1516 0 91 (_entity (_string \"111"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1518 0 94 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal ERROR_OK ~STD_LOGIC_VECTOR{2~downto~0}~1518 0 94 (_entity (_string \"000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1520 0 95 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal ERROR_ENCOD ~STD_LOGIC_VECTOR{2~downto~0}~1520 0 95 (_entity (_string \"001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1522 0 96 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal ERROR_RECOV ~STD_LOGIC_VECTOR{2~downto~0}~1522 0 96 (_entity (_string \"010"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1524 0 97 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal ERROR_FATAL ~STD_LOGIC_VECTOR{2~downto~0}~1524 0 97 (_entity (_string \"011"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1526 0 98 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal ERROR_WAIT ~STD_LOGIC_VECTOR{2~downto~0}~1526 0 98 (_entity (_string \"110"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1528 0 99 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal ERROR_NC ~STD_LOGIC_VECTOR{2~downto~0}~1528 0 99 (_entity (_string \"111"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~15 0 103 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_constant (_internal ILLEGAL_ADDRESS ~STD_LOGIC_VECTOR{15~downto~0}~15 0 103 (_entity (_string \"0000000000000000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1530 0 104 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_constant (_internal BROADCAST_ADDRESS ~STD_LOGIC_VECTOR{15~downto~0}~1530 0 104 (_entity (_string \"1111111111111111"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1532 0 107 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_constant (_internal LINK_STARTUP_WORD ~STD_LOGIC_VECTOR{15~downto~0}~1532 0 107 (_entity (_string \"1110000100010000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1534 0 108 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_constant (_internal SET_ADDRESS ~STD_LOGIC_VECTOR{15~downto~0}~1534 0 108 (_entity (_string \"0101111010101101"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1536 0 109 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_constant (_internal ACK_ADDRESS ~STD_LOGIC_VECTOR{15~downto~0}~1536 0 109 (_entity (_string \"1010110010101101"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1538 0 110 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_constant (_internal READ_ID ~STD_LOGIC_VECTOR{15~downto~0}~1538 0 110 (_entity (_string \"0101111000011101"\))))\r
+ (_constant (_internal std_COMSTATREG ~extSTD.STANDARD.INTEGER 0 114 (_entity ((i 8)))))\r
+ (_constant (_internal std_COMCTRLREG ~extSTD.STANDARD.INTEGER 0 115 (_entity ((i 3)))))\r
+ (_constant (_internal std_COMneededwidth ~extSTD.STANDARD.INTEGER 0 117 (_entity ((i 3)))))\r
+ (_constant (_internal c_REGIO_ADDRESS_WIDTH ~extSTD.STANDARD.INTEGER 0 118 (_entity ((i 16)))))\r
+ (_constant (_internal c_REGIO_REGISTER_WIDTH ~extSTD.STANDARD.INTEGER 0 119 (_entity ((i 32)))))\r
+ (_constant (_internal c_REGIO_REG_WIDTH ~extSTD.STANDARD.INTEGER 0 120 (_entity ((i 32)))))\r
+ (_constant (_internal c_regio_timeout_bit ~extSTD.STANDARD.INTEGER 0 121 (_entity ((i 5)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~1540 0 124 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal c_network_control_type ~STD_LOGIC_VECTOR{3~downto~0}~1540 0 124 (_entity (_string \"1111"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~1542 0 125 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal c_read_register_type ~STD_LOGIC_VECTOR{3~downto~0}~1542 0 125 (_entity (_string \"1000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~1544 0 126 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal c_write_register_type ~STD_LOGIC_VECTOR{3~downto~0}~1544 0 126 (_entity (_string \"1001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~1546 0 127 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal c_read_multiple_type ~STD_LOGIC_VECTOR{3~downto~0}~1546 0 127 (_entity (_string \"1010"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~1548 0 128 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_constant (_internal c_write_multiple_type ~STD_LOGIC_VECTOR{3~downto~0}~1548 0 128 (_entity (_string \"1011"\))))\r
+ (_constant (_internal c_BUS_HANDLER_MAX_PORTS ~extSTD.STANDARD.INTEGER 0 130 (_entity ((i 64)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{15~downto~0}~1550 0 131 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 15)(i 0))))))\r
+ (_type (_internal c_BUS_HANDLER_ADDR_t 0 131 (_array ~STD_LOGIC_VECTOR{15~downto~0}~1550 ((_to (i 0)(i 64))))))\r
+ (_type (_internal ~INTEGER~range~0~to~16~15 0 132 (_scalar (_to (i 0)(i 16)))))\r
+ (_type (_internal c_BUS_HANDLER_WIDTH_t 0 132 (_array ~INTEGER~range~0~to~16~15 ((_to (i 0)(i 64))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1553 0 136 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_H0 ~STD_LOGIC_VECTOR{2~downto~0}~1553 0 136 (_entity (_string \"100"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1555 0 137 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F0 ~STD_LOGIC_VECTOR{2~downto~0}~1555 0 137 (_entity (_string \"000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1557 0 138 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F1 ~STD_LOGIC_VECTOR{2~downto~0}~1557 0 138 (_entity (_string \"001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1559 0 139 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F2 ~STD_LOGIC_VECTOR{2~downto~0}~1559 0 139 (_entity (_string \"010"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1561 0 140 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F3 ~STD_LOGIC_VECTOR{2~downto~0}~1561 0 140 (_entity (_string \"011"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1563 0 142 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_H0_next ~STD_LOGIC_VECTOR{2~downto~0}~1563 0 142 (_entity (_string \"011"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1565 0 143 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F0_next ~STD_LOGIC_VECTOR{2~downto~0}~1565 0 143 (_entity (_string \"100"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1567 0 144 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F1_next ~STD_LOGIC_VECTOR{2~downto~0}~1567 0 144 (_entity (_string \"000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1569 0 145 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F2_next ~STD_LOGIC_VECTOR{2~downto~0}~1569 0 145 (_entity (_string \"001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1571 0 146 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_F3_next ~STD_LOGIC_VECTOR{2~downto~0}~1571 0 146 (_entity (_string \"010"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~1573 0 148 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_constant (_internal c_max_word_number ~STD_LOGIC_VECTOR{2~downto~0}~1573 0 148 (_entity (_string \"100"\))))\r
+ (_type (_internal ~INTEGER~range~0~to~1~16 0 242 (_scalar (_to (i 0)(i 1)))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{27~downto~0}~16 0 243 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 27)(i 0))))))\r
+ (_subprogram\r
+ (_internal and_all 0 0 155 (_entity (_function (_range(_to 0 2147483647 )))))\r
+ (_internal or_all 1 0 157 (_entity (_function (_range(_to 0 2147483647 )))))\r
+ (_internal all_zero 2 0 159 (_entity (_function (_range(_to 0 2147483647 )))))\r
+ (_internal xor_all 3 0 161 (_entity (_function (_range(_to 0 2147483647 )))))\r
+ (_internal get_bit_position 4 0 164 (_entity (_function (_range(_to 0 2147483647 )))))\r
+ (_internal is_time_reached 5 0 167 (_entity (_function )))\r
+ (_internal MAX 6 0 170 (_entity (_function )))\r
+ (_internal Log2 7 0 173 (_entity (_function )))\r
+ (_internal count_ones 8 0 174 (_entity (_function (_range(_to 0 2147483647 )))))\r
+ (_external resolved (ieee std_logic_1164 15))\r
+ )\r
+ (_type (_external ~extSTD.STANDARD.INTEGER (std STANDARD INTEGER)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_ULOGIC (ieee std_logic_1164 STD_ULOGIC)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC (ieee std_logic_1164 STD_LOGIC)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC_VECTOR (ieee std_logic_1164 STD_LOGIC_VECTOR)))\r
+ )\r
+ (_model . trb_net_std 9 -1\r
+ )\r
+)\r
+V 000051 55 21700 1318408985041 Behavioral
+(_unit VHDL (spi_slim 0 12 (behavioral 0 44 ))\r
+ (_version v63)\r
+ (_time 1318408985042 2011.10.12 10:43:05)\r
+ (_source (\./../../../trbnet/special/spi_slim.vhd\))\r
+ (_use (.(trb_net_std))(.(trb_net_components))(std(standard))(ieee(std_logic_1164))(ieee(std_logic_arith))(ieee(STD_LOGIC_UNSIGNED)))\r
+ (_parameters dbg)\r
+ (_code 7f712e7f2928226a297a7b7e3c2527)\r
+ (_entity\r
+ (_time 1318408984792)\r
+ (_use (.(trb_net_std))(.(trb_net_components))(std(standard))(ieee(std_logic_1164))(ieee(std_logic_arith))(ieee(STD_LOGIC_UNSIGNED)))\r
+ )\r
+ (_object\r
+ (_type (_internal ~INTEGER~range~0~to~0~12 0 14 (_scalar (_to (i -2147483648)(i 2147483647)))))\r
+ (_generic (_internal SLOW_SPI ~INTEGER~range~0~to~0~12 0 14 \1\ (_entity ((i 1)))))\r
+ (_port (_internal SYSCLK ~extieee.std_logic_1164.STD_LOGIC 0 17 (_entity (_in ))))\r
+ (_port (_internal RESET ~extieee.std_logic_1164.STD_LOGIC 0 18 (_entity (_in ))))\r
+ (_port (_internal START_IN ~extieee.std_logic_1164.STD_LOGIC 0 20 (_entity (_in ))))\r
+ (_port (_internal BUSY_OUT ~extieee.std_logic_1164.STD_LOGIC 0 21 (_entity (_out ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~12 0 22 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_port (_internal CMD_IN ~STD_LOGIC_VECTOR{7~downto~0}~12 0 22 (_entity (_in ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~122 0 23 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_port (_internal ADL_IN ~STD_LOGIC_VECTOR{7~downto~0}~122 0 23 (_entity (_in ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~124 0 24 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_port (_internal ADM_IN ~STD_LOGIC_VECTOR{7~downto~0}~124 0 24 (_entity (_in ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~126 0 25 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_port (_internal ADH_IN ~STD_LOGIC_VECTOR{7~downto~0}~126 0 25 (_entity (_in ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~128 0 26 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_port (_internal MAX_IN ~STD_LOGIC_VECTOR{7~downto~0}~128 0 26 (_entity (_in ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1210 0 27 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_port (_internal TXDATA_IN ~STD_LOGIC_VECTOR{7~downto~0}~1210 0 27 (_entity (_in ))))\r
+ (_port (_internal TX_RD_OUT ~extieee.std_logic_1164.STD_LOGIC 0 28 (_entity (_out ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1212 0 29 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_port (_internal RXDATA_OUT ~STD_LOGIC_VECTOR{7~downto~0}~1212 0 29 (_entity (_out ))))\r
+ (_port (_internal RX_WR_OUT ~extieee.std_logic_1164.STD_LOGIC 0 30 (_entity (_out ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1214 0 31 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_port (_internal TX_RX_A_OUT ~STD_LOGIC_VECTOR{7~downto~0}~1214 0 31 (_entity (_out ))))\r
+ (_port (_internal SPI_SCK_OUT ~extieee.std_logic_1164.STD_LOGIC 0 33 (_entity (_out ))))\r
+ (_port (_internal SPI_CS_OUT ~extieee.std_logic_1164.STD_LOGIC 0 34 (_entity (_out ))))\r
+ (_port (_internal SPI_SDI_IN ~extieee.std_logic_1164.STD_LOGIC 0 35 (_entity (_in ))))\r
+ (_port (_internal SPI_SDO_OUT ~extieee.std_logic_1164.STD_LOGIC 0 36 (_entity (_out ))))\r
+ (_port (_internal CLK_EN_OUT ~extieee.std_logic_1164.STD_LOGIC 0 38 (_entity (_out ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1216 0 39 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_port (_internal BSM_OUT ~STD_LOGIC_VECTOR{7~downto~0}~1216 0 39 (_entity (_out ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~12 0 40 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_port (_internal DEBUG_OUT ~STD_LOGIC_VECTOR{31~downto~0}~12 0 40 (_entity (_out ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{1+SLOW_SPI~downto~0}~13 0 47 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (c 46 )(i 0))))))\r
+ (_signal (_internal div_counter ~STD_LOGIC_VECTOR{1+SLOW_SPI~downto~0}~13 0 47 (_architecture (_uni ))))\r
+ (_signal (_internal div_done_x ~extieee.std_logic_1164.STD_LOGIC 0 48 (_architecture (_uni ))))\r
+ (_signal (_internal div_done ~extieee.std_logic_1164.STD_LOGIC 0 49 (_architecture (_uni ))))\r
+ (_signal (_internal clk_en ~extieee.std_logic_1164.STD_LOGIC 0 50 (_architecture (_uni ))))\r
+ (_type (_internal state_t 0 53 (_enum1 idle csl txcmd txadd_h txadd_m txadd_l txdata rxdata wait1 wait2 wait3 wait4 wait5 wait6 wait7 wait8 csh (_to (i 0)(i 16)))))\r
+ (_signal (_internal STATE state_t 0 55 (_architecture (_uni ))))\r
+ (_signal (_internal NEXT_STATE state_t 0 55 (_architecture (_uni ))))\r
+ (_signal (_internal rx_ena_x ~extieee.std_logic_1164.STD_LOGIC 0 57 (_architecture (_uni ))))\r
+ (_signal (_internal rx_ena ~extieee.std_logic_1164.STD_LOGIC 0 58 (_architecture (_uni ))))\r
+ (_signal (_internal tx_ena_x ~extieee.std_logic_1164.STD_LOGIC 0 59 (_architecture (_uni ))))\r
+ (_signal (_internal tx_ena ~extieee.std_logic_1164.STD_LOGIC 0 60 (_architecture (_uni ))))\r
+ (_signal (_internal busy_x ~extieee.std_logic_1164.STD_LOGIC 0 61 (_architecture (_uni ))))\r
+ (_signal (_internal busy ~extieee.std_logic_1164.STD_LOGIC 0 62 (_architecture (_uni ))))\r
+ (_signal (_internal spi_cs_x ~extieee.std_logic_1164.STD_LOGIC 0 63 (_architecture (_uni ))))\r
+ (_signal (_internal spi_cs ~extieee.std_logic_1164.STD_LOGIC 0 64 (_architecture (_uni ))))\r
+ (_signal (_internal spi_sck_x ~extieee.std_logic_1164.STD_LOGIC 0 65 (_architecture (_uni ))))\r
+ (_signal (_internal spi_sck ~extieee.std_logic_1164.STD_LOGIC 0 66 (_architecture (_uni ))))\r
+ (_signal (_internal tx_load_x ~extieee.std_logic_1164.STD_LOGIC 0 67 (_architecture (_uni ))))\r
+ (_signal (_internal tx_load ~extieee.std_logic_1164.STD_LOGIC 0 68 (_architecture (_uni ))))\r
+ (_signal (_internal tx_done_x ~extieee.std_logic_1164.STD_LOGIC 0 69 (_architecture (_uni ))))\r
+ (_signal (_internal tx_done ~extieee.std_logic_1164.STD_LOGIC 0 70 (_architecture (_uni ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{2~downto~0}~13 0 71 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 2)(i 0))))))\r
+ (_signal (_internal tx_sel_x ~STD_LOGIC_VECTOR{2~downto~0}~13 0 71 (_architecture (_uni ))))\r
+ (_signal (_internal tx_sel ~STD_LOGIC_VECTOR{2~downto~0}~13 0 72 (_architecture (_uni ))))\r
+ (_signal (_internal rx_store_x ~extieee.std_logic_1164.STD_LOGIC 0 73 (_architecture (_uni ))))\r
+ (_signal (_internal rx_store ~extieee.std_logic_1164.STD_LOGIC 0 74 (_architecture (_uni ))))\r
+ (_signal (_internal rx_complete ~extieee.std_logic_1164.STD_LOGIC 0 75 (_architecture (_uni ))))\r
+ (_signal (_internal rst_addr_x ~extieee.std_logic_1164.STD_LOGIC 0 76 (_architecture (_uni ))))\r
+ (_signal (_internal rst_addr ~extieee.std_logic_1164.STD_LOGIC 0 77 (_architecture (_uni ))))\r
+ (_signal (_internal inc_addr_rx_x ~extieee.std_logic_1164.STD_LOGIC 0 79 (_architecture (_uni ))))\r
+ (_signal (_internal inc_addr_rx ~extieee.std_logic_1164.STD_LOGIC 0 80 (_architecture (_uni ))))\r
+ (_signal (_internal inc_addr_tx_x ~extieee.std_logic_1164.STD_LOGIC 0 81 (_architecture (_uni ))))\r
+ (_signal (_internal inc_addr_tx ~extieee.std_logic_1164.STD_LOGIC 0 82 (_architecture (_uni ))))\r
+ (_signal (_internal ce_addr_x ~extieee.std_logic_1164.STD_LOGIC 0 83 (_architecture (_uni ))))\r
+ (_signal (_internal ce_addr ~extieee.std_logic_1164.STD_LOGIC 0 84 (_architecture (_uni ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~13 0 86 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_signal (_internal addr_ctr ~STD_LOGIC_VECTOR{7~downto~0}~13 0 86 (_architecture (_uni ))))\r
+ (_signal (_internal data_done_x ~extieee.std_logic_1164.STD_LOGIC 0 87 (_architecture (_uni ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{5~downto~0}~13 0 88 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 5)(i 0))))))\r
+ (_signal (_internal data_done ~STD_LOGIC_VECTOR{5~downto~0}~13 0 88 (_architecture (_uni ))))\r
+ (_signal (_internal last_tx_bit_x ~extieee.std_logic_1164.STD_LOGIC 0 90 (_architecture (_uni ))))\r
+ (_signal (_internal last_tx_bit ~extieee.std_logic_1164.STD_LOGIC 0 91 (_architecture (_uni ))))\r
+ (_signal (_internal is_data_x ~extieee.std_logic_1164.STD_LOGIC 0 92 (_architecture (_uni ))))\r
+ (_signal (_internal is_data ~extieee.std_logic_1164.STD_LOGIC 0 93 (_architecture (_uni ))))\r
+ (_signal (_internal bsm_x ~STD_LOGIC_VECTOR{7~downto~0}~13 0 96 (_architecture (_uni ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~13 0 97 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_signal (_internal debug_x ~STD_LOGIC_VECTOR{31~downto~0}~13 0 97 (_architecture (_uni ))))\r
+ (_signal (_internal start ~extieee.std_logic_1164.STD_LOGIC 0 99 (_architecture (_uni ))))\r
+ (_signal (_internal cmd_int ~STD_LOGIC_VECTOR{7~downto~0}~13 0 100 (_architecture (_uni ))))\r
+ (_signal (_internal adh_int ~STD_LOGIC_VECTOR{7~downto~0}~13 0 101 (_architecture (_uni ))))\r
+ (_signal (_internal adm_int ~STD_LOGIC_VECTOR{7~downto~0}~13 0 102 (_architecture (_uni ))))\r
+ (_signal (_internal adl_int ~STD_LOGIC_VECTOR{7~downto~0}~13 0 103 (_architecture (_uni ))))\r
+ (_signal (_internal max_int ~STD_LOGIC_VECTOR{7~downto~0}~13 0 104 (_architecture (_uni ))))\r
+ (_signal (_internal tx_sreg ~STD_LOGIC_VECTOR{7~downto~0}~13 0 107 (_architecture (_uni ))))\r
+ (_signal (_internal tx_reg_comb ~STD_LOGIC_VECTOR{7~downto~0}~13 0 108 (_architecture (_uni ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{3~downto~0}~13 0 109 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 3)(i 0))))))\r
+ (_signal (_internal tx_bit_cnt ~STD_LOGIC_VECTOR{3~downto~0}~13 0 109 (_architecture (_uni ))))\r
+ (_signal (_internal rx_sreg ~STD_LOGIC_VECTOR{7~downto~0}~13 0 112 (_architecture (_uni ))))\r
+ (_signal (_internal rx_bit_cnt_clr ~extieee.std_logic_1164.STD_LOGIC 0 113 (_architecture (_uni ))))\r
+ (_signal (_internal rx_bit_cnt ~STD_LOGIC_VECTOR{3~downto~0}~13 0 114 (_architecture (_uni ))))\r
+ (_signal (_internal rx_data ~STD_LOGIC_VECTOR{7~downto~0}~13 0 117 (_architecture (_uni ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~132 0 121 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal NOP ~STD_LOGIC_VECTOR{7~downto~0}~132 0 121 (_architecture (_string \"11111111"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~134 0 122 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal WREN ~STD_LOGIC_VECTOR{7~downto~0}~134 0 122 (_architecture (_string \"00000110"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~136 0 123 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal WRDI ~STD_LOGIC_VECTOR{7~downto~0}~136 0 123 (_architecture (_string \"00000100"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~138 0 124 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal ERASE ~STD_LOGIC_VECTOR{7~downto~0}~138 0 124 (_architecture (_string \"11000111"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1310 0 125 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal DPD ~STD_LOGIC_VECTOR{7~downto~0}~1310 0 125 (_architecture (_string \"10111001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1312 0 126 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal RDPD ~STD_LOGIC_VECTOR{7~downto~0}~1312 0 126 (_architecture (_string \"10101011"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1314 0 128 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal RDID ~STD_LOGIC_VECTOR{7~downto~0}~1314 0 128 (_architecture (_string \"10011111"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1316 0 129 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal RDSR ~STD_LOGIC_VECTOR{7~downto~0}~1316 0 129 (_architecture (_string \"00000101"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1318 0 131 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal WRSR ~STD_LOGIC_VECTOR{7~downto~0}~1318 0 131 (_architecture (_string \"00000001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1320 0 133 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal SE64 ~STD_LOGIC_VECTOR{7~downto~0}~1320 0 133 (_architecture (_string \"11011000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1322 0 134 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal SE32 ~STD_LOGIC_VECTOR{7~downto~0}~1322 0 134 (_architecture (_string \"01010010"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1324 0 135 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal SE4 ~STD_LOGIC_VECTOR{7~downto~0}~1324 0 135 (_architecture (_string \"00100000"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1326 0 136 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal SECP ~STD_LOGIC_VECTOR{7~downto~0}~1326 0 136 (_architecture (_string \"00110110"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1328 0 137 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal SECU ~STD_LOGIC_VECTOR{7~downto~0}~1328 0 137 (_architecture (_string \"00111001"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1330 0 139 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal RDCMD ~STD_LOGIC_VECTOR{7~downto~0}~1330 0 139 (_architecture (_string \"00000011"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1332 0 140 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal RDSPR ~STD_LOGIC_VECTOR{7~downto~0}~1332 0 140 (_architecture (_string \"00111100"\))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1334 0 141 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_constant (_internal PP ~STD_LOGIC_VECTOR{7~downto~0}~1334 0 141 (_architecture (_string \"00000010"\))))\r
+ (_process\r
+ (line__149(_architecture 0 0 149 (_assignment (_simple)(_alias((debug_x(d_31_24))(bsm_x)))(_target(62(d_31_24)))(_sensitivity(61)))))\r
+ (line__150(_architecture 1 0 150 (_assignment (_simple)(_alias((debug_x(d_23_20))(tx_bit_cnt)))(_target(62(d_23_20)))(_sensitivity(71)))))\r
+ (line__151(_architecture 2 0 151 (_assignment (_simple)(_alias((debug_x(d_19_16))(rx_bit_cnt)))(_target(62(d_19_16)))(_sensitivity(74)))))\r
+ (line__152(_architecture 3 0 152 (_assignment (_simple)(_alias((debug_x(15))(busy)))(_target(62(15)))(_sensitivity(32)))))\r
+ (line__153(_architecture 4 0 153 (_assignment (_simple)(_alias((debug_x(14))(start)))(_target(62(14)))(_sensitivity(63)))))\r
+ (line__154(_architecture 5 0 154 (_assignment (_simple)(_alias((debug_x(13))(inc_addr_tx)))(_target(62(13)))(_sensitivity(51)))))\r
+ (line__155(_architecture 6 0 155 (_assignment (_simple)(_alias((debug_x(12))(inc_addr_rx)))(_target(62(12)))(_sensitivity(49)))))\r
+ (line__156(_architecture 7 0 156 (_assignment (_simple)(_alias((debug_x(11))(last_tx_bit)))(_target(62(11)))(_sensitivity(58)))))\r
+ (line__157(_architecture 8 0 157 (_assignment (_simple)(_alias((debug_x(10))(rx_store)))(_target(62(10)))(_sensitivity(44)))))\r
+ (line__158(_architecture 9 0 158 (_assignment (_simple)(_alias((debug_x(9))(rst_addr)))(_target(62(9)))(_sensitivity(47)))))\r
+ (line__159(_architecture 10 0 159 (_assignment (_simple)(_alias((debug_x(8))(rx_ena)))(_target(62(8)))(_sensitivity(28)))))\r
+ (line__160(_architecture 11 0 160 (_assignment (_simple)(_alias((debug_x(7))(data_done(0))))(_target(62(7)))(_sensitivity(56(0))))))\r
+ (line__161(_architecture 12 0 161 (_assignment (_simple)(_alias((debug_x(6))(tx_done)))(_target(62(6)))(_sensitivity(40)))))\r
+ (line__162(_architecture 13 0 162 (_assignment (_simple)(_alias((debug_x(5))(tx_load)))(_target(62(5)))(_sensitivity(38)))))\r
+ (line__163(_architecture 14 0 163 (_assignment (_simple)(_alias((debug_x(4))(tx_ena)))(_target(62(4)))(_sensitivity(30)))))\r
+ (line__164(_architecture 15 0 164 (_assignment (_simple)(_alias((debug_x(3))(is_data)))(_target(62(3)))(_sensitivity(60)))))\r
+ (line__165(_architecture 16 0 165 (_assignment (_simple)(_alias((debug_x(d_2_0))(tx_sel)))(_target(62(d_2_0)))(_sensitivity(42)))))\r
+ (THE_CLOCK_DIVIDER(_architecture 17 0 175 (_process (_simple)(_target(21)(23)(36))(_sensitivity(0))(_read(1)(21)(22)(35)))))\r
+ (line__190(_architecture 18 0 190 (_assignment (_simple)(_target(22))(_sensitivity(21)))))\r
+ (line__192(_architecture 19 0 192 (_assignment (_simple)(_target(35))(_sensitivity(21(_range 47))(21(_range 48))(28)(30))(_read(21(_range 49))(21(_range 50))))))\r
+ (line__195(_architecture 20 0 195 (_assignment (_simple)(_alias((clk_en)(div_done)))(_target(24))(_sensitivity(23)))))\r
+ (THE_START_PROC(_architecture 21 0 200 (_process (_simple)(_target(63)(64)(65)(66)(67)(68))(_sensitivity(0))(_read(1)(2)(4)(5)(6)(7)(8)(32)))))\r
+ (THE_STATEMACHINE(_architecture 22 0 226 (_process (_simple)(_target(25)(28)(30)(32)(34)(38)(40)(42)(44)(47)(60))(_sensitivity(0))(_read(1)(24)(26)(27)(29)(31)(33)(37)(39)(41)(43)(46)(59)))))\r
+ (THE_STATE_TRANSITIONS(_architecture 23 0 260 (_process (_simple)(_target(26)(27)(29)(31)(33)(37)(39)(41)(43)(46)(59))(_sensitivity(25)(56(5))(63)(64)(71)(74)))))\r
+ (THE_STATEMACHINE_OUT(_architecture 24 0 487 (_process (_simple)(_target(61)(73))(_sensitivity(25)))))\r
+ (THE_TXREG_MUX(_architecture 25 0 515 (_process (_simple)(_target(70))(_sensitivity(9)(42)(64)(65)(66)(67)))))\r
+ (THE_TX_SHIFT_AND_BITCOUNT(_architecture 26 0 531 (_process (_simple)(_target(58)(69)(69(d_6_0))(71))(_sensitivity(0))(_read(1)(24)(30)(38)(57)(69(d_6_0))(70)(71)))))\r
+ (line__549(_architecture 27 0 549 (_assignment (_simple)(_target(57))(_sensitivity(71)))))\r
+ (THE_RX_SHIFT_AND_BITCOUNT(_architecture 28 0 552 (_process (_simple)(_target(72)(74))(_sensitivity(0))(_read(1)(16)(24)(28)(72(d_6_0))(74)))))\r
+ (THE_RXDATA_REG(_architecture 29 0 573 (_process (_simple)(_target(45)(75))(_sensitivity(0))(_read(1)(24)(44)(72)))))\r
+ (THE_ADDR_COUNTER(_architecture 30 0 589 (_process (_simple)(_target(49)(51)(53)(54)(56(0))(56(d_5_1))(56))(_sensitivity(0))(_read(1)(47)(48)(50)(52)(53)(54)(55)(56(d_4_0))))))\r
+ (line__609(_architecture 31 0 609 (_assignment (_simple)(_target(48))(_sensitivity(45)))))\r
+ (line__611(_architecture 32 0 611 (_assignment (_simple)(_target(50))(_sensitivity(24)(58)(60)))))\r
+ (line__612(_architecture 33 0 612 (_assignment (_simple)(_target(52))(_sensitivity(49)(51)))))\r
+ (line__614(_architecture 34 0 614 (_assignment (_simple)(_target(55))(_sensitivity(54)(68)))))\r
+ (line__617(_architecture 35 0 617 (_assignment (_simple)(_alias((spi_cs_out)(spi_cs)))(_target(15))(_sensitivity(34)))))\r
+ (line__618(_architecture 36 0 618 (_assignment (_simple)(_alias((spi_sck_out)(spi_sck)))(_target(14))(_sensitivity(36)))))\r
+ (line__619(_architecture 37 0 619 (_assignment (_simple)(_alias((spi_sdo_out)(tx_sreg(7))))(_target(17))(_sensitivity(69(7))))))\r
+ (line__620(_architecture 38 0 620 (_assignment (_simple)(_alias((busy_out)(busy)))(_target(3))(_sensitivity(32)))))\r
+ (line__622(_architecture 39 0 622 (_assignment (_simple)(_alias((tx_rd_out)(_string \"0"\)))(_target(10)))))\r
+ (line__623(_architecture 40 0 623 (_assignment (_simple)(_alias((rxdata_out)(rx_data)))(_target(11))(_sensitivity(75)))))\r
+ (line__624(_architecture 41 0 624 (_assignment (_simple)(_alias((rx_wr_out)(rx_complete)))(_target(12))(_sensitivity(45)))))\r
+ (line__625(_architecture 42 0 625 (_assignment (_simple)(_alias((tx_rx_a_out)(addr_ctr)))(_target(13))(_sensitivity(54)))))\r
+ (line__627(_architecture 43 0 627 (_assignment (_simple)(_alias((clk_en_out)(clk_en)))(_target(18))(_sensitivity(24)))))\r
+ (line__628(_architecture 44 0 628 (_assignment (_simple)(_alias((bsm_out)(bsm_x)))(_target(19))(_sensitivity(61)))))\r
+ (line__629(_architecture 45 0 629 (_assignment (_simple)(_alias((debug_out)(debug_x)))(_target(20))(_sensitivity(62)))))\r
+ )\r
+ (_subprogram\r
+ (_external resolved (ieee std_logic_1164 15))\r
+ (_external or_all (. trb_net_std 1))\r
+ )\r
+ (_type (_external ~extSTD.STANDARD.INTEGER (std STANDARD INTEGER)))\r
+ (_variable (_external work.trb_net_std.c_YES(. trb_net_std c_YES)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_ULOGIC (ieee std_logic_1164 STD_ULOGIC)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC (ieee std_logic_1164 STD_LOGIC)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC_VECTOR (ieee std_logic_1164 STD_LOGIC_VECTOR)))\r
+ )\r
+ (_static\r
+ (771 )\r
+ (514 )\r
+ (33686018 33686018 )\r
+ (33686018 33686018 )\r
+ (33686018 33686018 )\r
+ (33686018 33686018 )\r
+ (33686018 33686018 )\r
+ (131586 )\r
+ (50529026 )\r
+ (197122 )\r
+ (131587 )\r
+ (131843 )\r
+ (131842 )\r
+ (197378 )\r
+ (33686018 33686018 )\r
+ (33686018 50463235 )\r
+ (33686018 50463234 )\r
+ (33686018 33751554 )\r
+ (33686018 50528770 )\r
+ (33686018 33686274 )\r
+ (33686018 50463490 )\r
+ (33686018 50529026 )\r
+ (50463234 33686018 )\r
+ (50463234 50463234 )\r
+ (50463234 33751554 )\r
+ (50463234 50528770 )\r
+ (50463234 50529026 )\r
+ (50463234 50463490 )\r
+ (50463234 33686274 )\r
+ (50463234 33751810 )\r
+ (33686018 33686019 )\r
+ (50529027 50529027 )\r
+ (33751811 33751811 )\r
+ (33686018 131586 )\r
+ (33686018 )\r
+ (33686018 )\r
+ (33686018 )\r
+ (33686018 33686018 )\r
+ (33686018 )\r
+ (33686018 33686018 )\r
+ (33686018 33686018 )\r
+ (33686018 514 )\r
+ )\r
+ (_model . Behavioral 51 -1\r
+ )\r
+)\r
+V 000051 55 12802 1318408985778 Behavioral
+(_unit VHDL (spi_master 0 10 (behavioral 0 37 ))\r
+ (_version v63)\r
+ (_time 1318408985779 2011.10.12 10:43:05)\r
+ (_source (\./../../../trbnet/special/spi_master.vhd\))\r
+ (_use (.(trb_net_std))(.(trb_net_components))(std(standard))(ieee(std_logic_1164))(ieee(std_logic_arith))(ieee(STD_LOGIC_UNSIGNED)))\r
+ (_parameters dbg)\r
+ (_code 5d530b5f090a00480b5a090f4c060f)\r
+ (_entity\r
+ (_time 1318408985776)\r
+ (_use (.(trb_net_std))(.(trb_net_components))(std(standard))(ieee(std_logic_1164))(ieee(std_logic_arith))(ieee(STD_LOGIC_UNSIGNED)))\r
+ )\r
+ (_component\r
+ (.trb_net_components.spi_slim\r
+ (_object\r
+ (_port (_internal SYSCLK ~extieee.std_logic_1164.STD_LOGIC 0 2824 (_entity (_in ))))\r
+ (_port (_internal RESET ~extieee.std_logic_1164.STD_LOGIC 0 2825 (_entity (_in ))))\r
+ (_port (_internal START_IN ~extieee.std_logic_1164.STD_LOGIC 0 2827 (_entity (_in ))))\r
+ (_port (_internal BUSY_OUT ~extieee.std_logic_1164.STD_LOGIC 0 2828 (_entity (_out ))))\r
+ (_port (_internal CMD_IN ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151483 0 2829 (_entity (_in ))))\r
+ (_port (_internal ADL_IN ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151485 0 2830 (_entity (_in ))))\r
+ (_port (_internal ADM_IN ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151487 0 2831 (_entity (_in ))))\r
+ (_port (_internal ADH_IN ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151489 0 2832 (_entity (_in ))))\r
+ (_port (_internal MAX_IN ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151491 0 2833 (_entity (_in ))))\r
+ (_port (_internal TXDATA_IN ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151493 0 2834 (_entity (_in ))))\r
+ (_port (_internal TX_RD_OUT ~extieee.std_logic_1164.STD_LOGIC 0 2835 (_entity (_out ))))\r
+ (_port (_internal RXDATA_OUT ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151495 0 2836 (_entity (_out ))))\r
+ (_port (_internal RX_WR_OUT ~extieee.std_logic_1164.STD_LOGIC 0 2837 (_entity (_out ))))\r
+ (_port (_internal TX_RX_A_OUT ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151497 0 2838 (_entity (_out ))))\r
+ (_port (_internal SPI_SCK_OUT ~extieee.std_logic_1164.STD_LOGIC 0 2840 (_entity (_out ))))\r
+ (_port (_internal SPI_CS_OUT ~extieee.std_logic_1164.STD_LOGIC 0 2841 (_entity (_out ))))\r
+ (_port (_internal SPI_SDI_IN ~extieee.std_logic_1164.STD_LOGIC 0 2842 (_entity (_in ))))\r
+ (_port (_internal SPI_SDO_OUT ~extieee.std_logic_1164.STD_LOGIC 0 2843 (_entity (_out ))))\r
+ (_port (_internal CLK_EN_OUT ~extieee.std_logic_1164.STD_LOGIC 0 2845 (_entity (_out ))))\r
+ (_port (_internal BSM_OUT ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151499 0 2846 (_entity (_out ))))\r
+ (_port (_internal DEBUG_OUT ~extwork.trb_net_components.~STD_LOGIC_VECTOR{31~downto~0}~151501 0 2847 (_entity (_out ))))\r
+ )\r
+ )\r
+ )\r
+ (_instantiation THE_SPI_SLIM 0 91 (_component .trb_net_components.spi_slim )\r
+ (_port\r
+ ((SYSCLK)(clk_in))\r
+ ((RESET)(reset_i))\r
+ ((START_IN)(spi_start))\r
+ ((BUSY_OUT)(spi_busy))\r
+ ((CMD_IN)(reg_ctrl_data(d_31_24)))\r
+ ((ADL_IN)(reg_ctrl_data(d_7_0)))\r
+ ((ADM_IN)(reg_ctrl_data(d_15_8)))\r
+ ((ADH_IN)(reg_ctrl_data(d_23_16)))\r
+ ((MAX_IN)(reg_status_data(d_31_24)))\r
+ ((TXDATA_IN)(bram_wr_d_in))\r
+ ((TX_RD_OUT)(_open))\r
+ ((RXDATA_OUT)(bram_rd_d_out))\r
+ ((RX_WR_OUT)(bram_we_out))\r
+ ((TX_RX_A_OUT)(bram_a_out))\r
+ ((SPI_SCK_OUT)(spi_sck_out))\r
+ ((SPI_CS_OUT)(spi_cs_out))\r
+ ((SPI_SDI_IN)(spi_sdi_in))\r
+ ((SPI_SDO_OUT)(spi_sdo_out))\r
+ ((CLK_EN_OUT)(_open))\r
+ ((BSM_OUT)(spi_bsm))\r
+ ((DEBUG_OUT)(spi_debug))\r
+ )\r
+ (_use (_entity . spi_slim)\r
+ )\r
+ )\r
+ (_object\r
+ (_port (_internal CLK_IN ~extieee.std_logic_1164.STD_LOGIC 0 12 (_entity (_in ))))\r
+ (_port (_internal RESET_IN ~extieee.std_logic_1164.STD_LOGIC 0 13 (_entity (_in ))))\r
+ (_port (_internal BUS_READ_IN ~extieee.std_logic_1164.STD_LOGIC 0 15 (_entity (_in ))))\r
+ (_port (_internal BUS_WRITE_IN ~extieee.std_logic_1164.STD_LOGIC 0 16 (_entity (_in ))))\r
+ (_port (_internal BUS_BUSY_OUT ~extieee.std_logic_1164.STD_LOGIC 0 17 (_entity (_out ))))\r
+ (_port (_internal BUS_ACK_OUT ~extieee.std_logic_1164.STD_LOGIC 0 18 (_entity (_out ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{0~downto~0}~12 0 19 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 0)(i 0))))))\r
+ (_port (_internal BUS_ADDR_IN ~STD_LOGIC_VECTOR{0~downto~0}~12 0 19 (_entity (_in ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~12 0 20 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_port (_internal BUS_DATA_IN ~STD_LOGIC_VECTOR{31~downto~0}~12 0 20 (_entity (_in ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~122 0 21 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_port (_internal BUS_DATA_OUT ~STD_LOGIC_VECTOR{31~downto~0}~122 0 21 (_entity (_out ))))\r
+ (_port (_internal SPI_CS_OUT ~extieee.std_logic_1164.STD_LOGIC 0 23 (_entity (_out ))))\r
+ (_port (_internal SPI_SDI_IN ~extieee.std_logic_1164.STD_LOGIC 0 24 (_entity (_in ))))\r
+ (_port (_internal SPI_SDO_OUT ~extieee.std_logic_1164.STD_LOGIC 0 25 (_entity (_out ))))\r
+ (_port (_internal SPI_SCK_OUT ~extieee.std_logic_1164.STD_LOGIC 0 26 (_entity (_out ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~12 0 28 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_port (_internal BRAM_A_OUT ~STD_LOGIC_VECTOR{7~downto~0}~12 0 28 (_entity (_out ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~124 0 29 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_port (_internal BRAM_WR_D_IN ~STD_LOGIC_VECTOR{7~downto~0}~124 0 29 (_entity (_in ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~126 0 30 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_port (_internal BRAM_RD_D_OUT ~STD_LOGIC_VECTOR{7~downto~0}~126 0 30 (_entity (_out ))))\r
+ (_port (_internal BRAM_WE_OUT ~extieee.std_logic_1164.STD_LOGIC 0 31 (_entity (_out ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~128 0 33 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_port (_internal STAT ~STD_LOGIC_VECTOR{31~downto~0}~128 0 33 (_entity (_out ))))\r
+ (_type (_internal STATES 0 44 (_enum1 sleep rd_bsy wr_bsy rd_rdy wr_rdy rd_ack wr_ack done (_to (i 0)(i 7)))))\r
+ (_signal (_internal CURRENT_STATE STATES 0 45 (_architecture (_uni ))))\r
+ (_signal (_internal NEXT_STATE STATES 0 45 (_architecture (_uni ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~13 0 47 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_signal (_internal status_data ~STD_LOGIC_VECTOR{31~downto~0}~13 0 47 (_architecture (_uni ))))\r
+ (_signal (_internal spi_busy ~extieee.std_logic_1164.STD_LOGIC 0 48 (_architecture (_uni ))))\r
+ (_signal (_internal reg_ctrl_data ~STD_LOGIC_VECTOR{31~downto~0}~13 0 50 (_architecture (_uni ))))\r
+ (_signal (_internal reg_status_data ~STD_LOGIC_VECTOR{31~downto~0}~13 0 51 (_architecture (_uni ))))\r
+ (_signal (_internal reg_bus_data_out ~STD_LOGIC_VECTOR{31~downto~0}~13 0 53 (_architecture (_uni ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~13 0 55 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_signal (_internal spi_bsm ~STD_LOGIC_VECTOR{7~downto~0}~13 0 55 (_architecture (_uni ))))\r
+ (_signal (_internal spi_debug ~STD_LOGIC_VECTOR{31~downto~0}~13 0 56 (_architecture (_uni ))))\r
+ (_signal (_internal spi_start_x ~extieee.std_logic_1164.STD_LOGIC 0 58 (_architecture (_uni ))))\r
+ (_signal (_internal spi_start ~extieee.std_logic_1164.STD_LOGIC 0 59 (_architecture (_uni ))))\r
+ (_signal (_internal bus_busy_x ~extieee.std_logic_1164.STD_LOGIC 0 62 (_architecture (_uni ))))\r
+ (_signal (_internal bus_busy ~extieee.std_logic_1164.STD_LOGIC 0 63 (_architecture (_uni ))))\r
+ (_signal (_internal bus_ack_x ~extieee.std_logic_1164.STD_LOGIC 0 64 (_architecture (_uni ))))\r
+ (_signal (_internal bus_ack ~extieee.std_logic_1164.STD_LOGIC 0 65 (_architecture (_uni ))))\r
+ (_signal (_internal store_wr_x ~extieee.std_logic_1164.STD_LOGIC 0 66 (_architecture (_uni ))))\r
+ (_signal (_internal store_wr ~extieee.std_logic_1164.STD_LOGIC 0 67 (_architecture (_uni ))))\r
+ (_signal (_internal store_rd_x ~extieee.std_logic_1164.STD_LOGIC 0 68 (_architecture (_uni ))))\r
+ (_signal (_internal store_rd ~extieee.std_logic_1164.STD_LOGIC 0 69 (_architecture (_uni ))))\r
+ (_signal (_internal reset_i ~extieee.std_logic_1164.STD_LOGIC 0 71 (_architecture (_uni ))))\r
+ (_process\r
+ (line__80(_architecture 0 0 80 (_process (_simple)(_target(37))(_sensitivity(0))(_read(1)))))\r
+ (STATE_MEM(_architecture 1 0 122 (_process (_simple)(_target(18)(30)(32)(34)(36))(_sensitivity(0))(_read(19)(29)(31)(33)(35)(37)))))\r
+ (TRANSFORM(_architecture 2 0 141 (_process (_simple)(_target(19)(29)(31)(33)(35))(_sensitivity(18)(21)(2)(3)(6)))))\r
+ (THE_WRITE_REG_PROC(_architecture 3 0 218 (_process (_simple)(_target(22)(23)(28))(_sensitivity(0))(_read(27)(34)(37)(6(0))(7)))))\r
+ (line__237(_architecture 4 0 237 (_assignment (_simple)(_target(27))(_sensitivity(34)(6(0))))))\r
+ (THE_READ_REG_PROC(_architecture 5 0 240 (_process (_simple)(_target(24(d_7_0))(24(d_15_8))(24(d_23_16))(24(d_31_24))(24))(_sensitivity(0))(_read(22)(23(d_31_24))(25)(36)(37)(6(0))))))\r
+ (line__257(_architecture 6 0 257 (_assignment (_simple)(_alias((status_data(d_31_24))(spi_bsm)))(_target(20(d_31_24)))(_sensitivity(25)))))\r
+ (line__258(_architecture 7 0 258 (_assignment (_simple)(_alias((status_data(23))(spi_start)))(_target(20(23)))(_sensitivity(28)))))\r
+ (line__259(_architecture 8 0 259 (_assignment (_simple)(_target(20(d_22_0))))))\r
+ (line__262(_architecture 9 0 262 (_assignment (_simple)(_alias((bus_ack_out)(bus_ack)))(_target(5))(_sensitivity(32)))))\r
+ (line__263(_architecture 10 0 263 (_assignment (_simple)(_alias((bus_busy_out)(bus_busy)))(_target(4))(_sensitivity(30)))))\r
+ (line__264(_architecture 11 0 264 (_assignment (_simple)(_alias((bus_data_out)(reg_bus_data_out)))(_target(8))(_sensitivity(24)))))\r
+ (line__265(_architecture 12 0 265 (_assignment (_simple)(_alias((stat(d_31_3))(spi_debug(d_31_3))))(_target(17(d_31_3)))(_sensitivity(26(d_31_3))))))\r
+ (line__266(_architecture 13 0 266 (_assignment (_simple)(_alias((stat(2))(spi_start)))(_target(17(2)))(_sensitivity(28)))))\r
+ (line__267(_architecture 14 0 267 (_assignment (_simple)(_alias((stat(1))(bus_write_in)))(_target(17(1)))(_sensitivity(3)))))\r
+ (line__268(_architecture 15 0 268 (_assignment (_simple)(_alias((stat(0))(bus_read_in)))(_target(17(0)))(_sensitivity(2)))))\r
+ )\r
+ (_subprogram\r
+ (_external resolved (ieee std_logic_1164 15))\r
+ )\r
+ (_type (_external ~extieee.std_logic_1164.STD_ULOGIC (ieee std_logic_1164 STD_ULOGIC)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC (ieee std_logic_1164 STD_LOGIC)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC_VECTOR (ieee std_logic_1164 STD_LOGIC_VECTOR)))\r
+ (_type (_external ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151483 (. trb_net_components ~STD_LOGIC_VECTOR{7~downto~0}~151483)))\r
+ (_type (_external ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151485 (. trb_net_components ~STD_LOGIC_VECTOR{7~downto~0}~151485)))\r
+ (_type (_external ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151487 (. trb_net_components ~STD_LOGIC_VECTOR{7~downto~0}~151487)))\r
+ (_type (_external ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151489 (. trb_net_components ~STD_LOGIC_VECTOR{7~downto~0}~151489)))\r
+ (_type (_external ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151491 (. trb_net_components ~STD_LOGIC_VECTOR{7~downto~0}~151491)))\r
+ (_type (_external ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151493 (. trb_net_components ~STD_LOGIC_VECTOR{7~downto~0}~151493)))\r
+ (_type (_external ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151495 (. trb_net_components ~STD_LOGIC_VECTOR{7~downto~0}~151495)))\r
+ (_type (_external ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151497 (. trb_net_components ~STD_LOGIC_VECTOR{7~downto~0}~151497)))\r
+ (_type (_external ~extwork.trb_net_components.~STD_LOGIC_VECTOR{7~downto~0}~151499 (. trb_net_components ~STD_LOGIC_VECTOR{7~downto~0}~151499)))\r
+ (_type (_external ~extwork.trb_net_components.~STD_LOGIC_VECTOR{31~downto~0}~151501 (. trb_net_components ~STD_LOGIC_VECTOR{31~downto~0}~151501)))\r
+ )\r
+ (_static\r
+ (33686018 33686018 33686018 33686018 33686018 33686018 33686018 33686018 )\r
+ (33686018 33686018 33686018 33686018 33686018 33686018 33686018 33686018 )\r
+ (33686018 33686018 33686018 33686018 33686018 33686018 33686018 33686018 )\r
+ (33686018 33686018 )\r
+ (33686018 33686018 33686018 33686018 33686018 131586 )\r
+ )\r
+ (_model . Behavioral 16 -1\r
+ )\r
+)\r
+V 000049 55 7367 1318408986510 behavior
+(_unit VHDL (testbench 0 5 (behavior 0 8 ))\r
+ (_version v63)\r
+ (_time 1318408986511 2011.10.12 10:43:06)\r
+ (_source (\./../../sim/tb_spi_master.vhd\))\r
+ (_use (std(standard))(ieee(std_logic_1164))(ieee(NUMERIC_STD)))\r
+ (_parameters dbg)\r
+ (_code 3b6d3e3e6c6d6c2c366829616f)\r
+ (_entity\r
+ (_time 1318408986463)\r
+ (_use (std(standard))(ieee(std_logic_1164))(ieee(NUMERIC_STD)))\r
+ )\r
+ (_component\r
+ (spi_master\r
+ (_object\r
+ (_port (_internal CLK_IN ~extieee.std_logic_1164.STD_LOGIC 0 12 (_entity (_in ))))\r
+ (_port (_internal RESET_IN ~extieee.std_logic_1164.STD_LOGIC 0 13 (_entity (_in ))))\r
+ (_port (_internal BUS_READ_IN ~extieee.std_logic_1164.STD_LOGIC 0 14 (_entity (_in ))))\r
+ (_port (_internal BUS_WRITE_IN ~extieee.std_logic_1164.STD_LOGIC 0 15 (_entity (_in ))))\r
+ (_port (_internal BUS_ADDR_IN ~STD_LOGIC_VECTOR{0~to~0}~13 0 16 (_entity (_in ))))\r
+ (_port (_internal BUS_DATA_IN ~STD_LOGIC_VECTOR{31~downto~0}~13 0 17 (_entity (_in ))))\r
+ (_port (_internal SPI_SDI_IN ~extieee.std_logic_1164.STD_LOGIC 0 18 (_entity (_in ))))\r
+ (_port (_internal BRAM_WR_D_IN ~STD_LOGIC_VECTOR{7~downto~0}~13 0 19 (_entity (_in ))))\r
+ (_port (_internal BUS_BUSY_OUT ~extieee.std_logic_1164.STD_LOGIC 0 20 (_entity (_out ))))\r
+ (_port (_internal BUS_ACK_OUT ~extieee.std_logic_1164.STD_LOGIC 0 21 (_entity (_out ))))\r
+ (_port (_internal BUS_DATA_OUT ~STD_LOGIC_VECTOR{31~downto~0}~132 0 22 (_entity (_out ))))\r
+ (_port (_internal SPI_CS_OUT ~extieee.std_logic_1164.STD_LOGIC 0 23 (_entity (_out ))))\r
+ (_port (_internal SPI_SDO_OUT ~extieee.std_logic_1164.STD_LOGIC 0 24 (_entity (_out ))))\r
+ (_port (_internal SPI_SCK_OUT ~extieee.std_logic_1164.STD_LOGIC 0 25 (_entity (_out ))))\r
+ (_port (_internal BRAM_A_OUT ~STD_LOGIC_VECTOR{7~downto~0}~134 0 26 (_entity (_out ))))\r
+ (_port (_internal BRAM_RD_D_OUT ~STD_LOGIC_VECTOR{7~downto~0}~136 0 27 (_entity (_out ))))\r
+ (_port (_internal BRAM_WE_OUT ~extieee.std_logic_1164.STD_LOGIC 0 28 (_entity (_out ))))\r
+ (_port (_internal STAT ~STD_LOGIC_VECTOR{31~downto~0}~138 0 29 (_entity (_out ))))\r
+ )\r
+ )\r
+ )\r
+ (_instantiation uut 0 55 (_component spi_master )\r
+ (_port\r
+ ((CLK_IN)(CLK_IN))\r
+ ((RESET_IN)(RESET_IN))\r
+ ((BUS_READ_IN)(BUS_READ_IN))\r
+ ((BUS_WRITE_IN)(BUS_WRITE_IN))\r
+ ((BUS_ADDR_IN)(BUS_ADDR_IN))\r
+ ((BUS_DATA_IN)(BUS_DATA_IN))\r
+ ((SPI_SDI_IN)(SPI_SDI_IN))\r
+ ((BRAM_WR_D_IN)(BRAM_WR_D_IN))\r
+ ((BUS_BUSY_OUT)(BUS_BUSY_OUT))\r
+ ((BUS_ACK_OUT)(BUS_ACK_OUT))\r
+ ((BUS_DATA_OUT)(BUS_DATA_OUT))\r
+ ((SPI_CS_OUT)(SPI_CS_OUT))\r
+ ((SPI_SDO_OUT)(SPI_SDO_OUT))\r
+ ((SPI_SCK_OUT)(SPI_SCK_OUT))\r
+ ((BRAM_A_OUT)(BRAM_A_OUT))\r
+ ((BRAM_RD_D_OUT)(BRAM_RD_D_OUT))\r
+ ((BRAM_WE_OUT)(BRAM_WE_OUT))\r
+ ((STAT)(STAT))\r
+ )\r
+ (_use (_entity . spi_master)\r
+ (_port\r
+ ((CLK_IN)(CLK_IN))\r
+ ((RESET_IN)(RESET_IN))\r
+ ((BUS_READ_IN)(BUS_READ_IN))\r
+ ((BUS_WRITE_IN)(BUS_WRITE_IN))\r
+ ((BUS_BUSY_OUT)(BUS_BUSY_OUT))\r
+ ((BUS_ACK_OUT)(BUS_ACK_OUT))\r
+ ((BUS_ADDR_IN)(BUS_ADDR_IN))\r
+ ((BUS_DATA_IN)(BUS_DATA_IN))\r
+ ((BUS_DATA_OUT)(BUS_DATA_OUT))\r
+ ((SPI_CS_OUT)(SPI_CS_OUT))\r
+ ((SPI_SDI_IN)(SPI_SDI_IN))\r
+ ((SPI_SDO_OUT)(SPI_SDO_OUT))\r
+ ((SPI_SCK_OUT)(SPI_SCK_OUT))\r
+ ((BRAM_A_OUT)(BRAM_A_OUT))\r
+ ((BRAM_WR_D_IN)(BRAM_WR_D_IN))\r
+ ((BRAM_RD_D_OUT)(BRAM_RD_D_OUT))\r
+ ((BRAM_WE_OUT)(BRAM_WE_OUT))\r
+ ((STAT)(STAT))\r
+ )\r
+ )\r
+ )\r
+ (_object\r
+ (_type (_internal ~STD_LOGIC_VECTOR{0~to~0}~13 0 16 (_array ~extieee.std_logic_1164.STD_LOGIC ((_to (i 0)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~13 0 17 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~13 0 19 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~132 0 22 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~134 0 26 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~136 0 27 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~138 0 29 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_signal (_internal CLK_IN ~extieee.std_logic_1164.STD_LOGIC 0 33 (_architecture (_uni ))))\r
+ (_signal (_internal RESET_IN ~extieee.std_logic_1164.STD_LOGIC 0 34 (_architecture (_uni ))))\r
+ (_signal (_internal BUS_READ_IN ~extieee.std_logic_1164.STD_LOGIC 0 35 (_architecture (_uni ))))\r
+ (_signal (_internal BUS_WRITE_IN ~extieee.std_logic_1164.STD_LOGIC 0 36 (_architecture (_uni ))))\r
+ (_signal (_internal BUS_BUSY_OUT ~extieee.std_logic_1164.STD_LOGIC 0 37 (_architecture (_uni ))))\r
+ (_signal (_internal BUS_ACK_OUT ~extieee.std_logic_1164.STD_LOGIC 0 38 (_architecture (_uni ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{0~to~0}~1310 0 39 (_array ~extieee.std_logic_1164.STD_LOGIC ((_to (i 0)(i 0))))))\r
+ (_signal (_internal BUS_ADDR_IN ~STD_LOGIC_VECTOR{0~to~0}~1310 0 39 (_architecture (_uni ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{31~downto~0}~1312 0 40 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 31)(i 0))))))\r
+ (_signal (_internal BUS_DATA_IN ~STD_LOGIC_VECTOR{31~downto~0}~1312 0 40 (_architecture (_uni ))))\r
+ (_signal (_internal BUS_DATA_OUT ~STD_LOGIC_VECTOR{31~downto~0}~1312 0 41 (_architecture (_uni ))))\r
+ (_signal (_internal SPI_CS_OUT ~extieee.std_logic_1164.STD_LOGIC 0 42 (_architecture (_uni ))))\r
+ (_signal (_internal SPI_SDI_IN ~extieee.std_logic_1164.STD_LOGIC 0 43 (_architecture (_uni ))))\r
+ (_signal (_internal SPI_SDO_OUT ~extieee.std_logic_1164.STD_LOGIC 0 44 (_architecture (_uni ))))\r
+ (_signal (_internal SPI_SCK_OUT ~extieee.std_logic_1164.STD_LOGIC 0 45 (_architecture (_uni ))))\r
+ (_type (_internal ~STD_LOGIC_VECTOR{7~downto~0}~1314 0 46 (_array ~extieee.std_logic_1164.STD_LOGIC ((_downto (i 7)(i 0))))))\r
+ (_signal (_internal BRAM_A_OUT ~STD_LOGIC_VECTOR{7~downto~0}~1314 0 46 (_architecture (_uni ))))\r
+ (_signal (_internal BRAM_WR_D_IN ~STD_LOGIC_VECTOR{7~downto~0}~1314 0 47 (_architecture (_uni ))))\r
+ (_signal (_internal BRAM_RD_D_OUT ~STD_LOGIC_VECTOR{7~downto~0}~1314 0 48 (_architecture (_uni ))))\r
+ (_signal (_internal BRAM_WE_OUT ~extieee.std_logic_1164.STD_LOGIC 0 49 (_architecture (_uni ))))\r
+ (_signal (_internal STAT ~STD_LOGIC_VECTOR{31~downto~0}~1312 0 50 (_architecture (_uni ))))\r
+ (_process\r
+ (THE_CLOCK_GEN(_architecture 0 0 76 (_process (_wait_for)(_target(0)))))\r
+ (THE_TEST_BENCH(_architecture 1 0 82 (_process (_wait_for)(_target(1)(2)(3)(6)(7)(10)(14))(_sensitivity(0))(_read(5)))))\r
+ )\r
+ (_subprogram\r
+ (_external resolved (ieee std_logic_1164 15))\r
+ )\r
+ (_type (_external ~extieee.std_logic_1164.STD_ULOGIC (ieee std_logic_1164 STD_ULOGIC)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC (ieee std_logic_1164 STD_LOGIC)))\r
+ (_type (_external ~extieee.std_logic_1164.STD_LOGIC_VECTOR (ieee std_logic_1164 STD_LOGIC_VECTOR)))\r
+ )\r
+ (_static\r
+ (2 )\r
+ (33686018 33686018 33686018 33686018 33686018 33686018 33686018 33686018 )\r
+ (33686018 33686018 )\r
+ (3 )\r
+ (50463234 50463234 33686018 33686018 33686018 33686018 33686018 33686018 )\r
+ (33686018 50528770 33751555 33751555 50528771 50528771 33686275 33686275 )\r
+ )\r
+ (_model . behavior 2 -1\r
+ )\r
+)\r
--- /dev/null
+\r
+[$GENERAL$]\r
+INIT=Z\r
+prefix=EDF_\r
+user_names=no\r
+edif2sdf_mapfile=\r
+logfile=efd2vhd.log\r
+\r
+[$EXPORT$]\r
+FMAP=NO\r
+HMAP=NO\r
+\r
+[$properties$]\r
+CYMODE=\r
+INIT=\r
+FD INIT=integer\r
+FDC INIT=integer\r
+FDCE INIT=integer\r
+FDCE_1 INIT=integer\r
+FDCP INIT=integer\r
+FDCPE INIT=integer\r
+FDCPE_1 INIT=integer\r
+FDCP_1 INIT=integer\r
+FDC_1 INIT=integer\r
+FDD INIT=integer\r
+FDDC INIT=integer\r
+FDDCE INIT=integer\r
+FDDCP INIT=integer\r
+FDDCPE INIT=integer\r
+FDDP INIT=integer\r
+FDDPE INIT=integer\r
+FDDRCPE INIT=integer\r
+FDDRRSE INIT=integer\r
+FDE INIT=integer\r
+FDE_1 INIT=integer\r
+FDP INIT=integer\r
+FDPE INIT=integer\r
+FDPE_1 INIT=integer\r
+FDP_1 INIT=integer\r
+FDR INIT=integer\r
+FDRE INIT=integer\r
+FDRE_1 INIT=integer\r
+FDRS INIT=integer\r
+FDRSE INIT=integer\r
+FDRSE_1 INIT=integer\r
+FDRS_1 INIT=integer\r
+FDR_1 INIT=integer\r
+FDS INIT=integer\r
+FDSE INIT=integer\r
+FDSE_1 INIT=integer\r
+FDS_1 INIT=integer\r
+FD_1 INIT=integer\r
+FTCP INIT=integer\r
+IDDR INIT_Q1=integer\r
+IDDR INIT_Q2=integer\r
+IDDR2 INIT_Q0=integer\r
+IDDR2 INIT_Q1=integer\r
+IDDR_2CLK INIT_Q1=integer\r
+IDDR_2CLK INIT_Q2=integer\r
+ISERDES INIT_Q1=integer\r
+ISERDES INIT_Q2=integer\r
+ISERDES INIT_Q3=integer\r
+ISERDES INIT_Q4=integer\r
+ISERDES SRVAL_Q1=integer\r
+ISERDES SRVAL_Q2=integer\r
+ISERDES SRVAL_Q3=integer\r
+ISERDES SRVAL_Q4=integer\r
+ISERDES_NODELAY INIT_Q1=integer\r
+ISERDES_NODELAY INIT_Q2=integer\r
+ISERDES_NODELAY INIT_Q3=integer\r
+ISERDES_NODELAY INIT_Q4=integer\r
+ISERDES_NODELAY SRVAL_Q1=integer\r
+ISERDES_NODELAY SRVAL_Q2=integer\r
+ISERDES_NODELAY SRVAL_Q3=integer\r
+ISERDES_NODELAY SRVAL_Q4=integer\r
+LD INIT=integer\r
+LDC INIT=integer\r
+LDCE INIT=integer\r
+LDCE_1 INIT=integer\r
+LDCP INIT=integer\r
+LDCPE INIT=integer\r
+LDCPE_1 INIT=integer\r
+LDCP_1 INIT=integer\r
+LDC_1 INIT=integer\r
+LDE INIT=integer\r
+LDE_1 INIT=integer\r
+LDG INIT=integer\r
+LDP INIT=integer\r
+LDPE INIT=integer\r
+LDPE_1 INIT=integer\r
+LDP_1 INIT=integer\r
+LD_1 INIT=integer\r
+ODDR INIT=integer\r
+ODDR2 INIT=integer\r
+OSERDES INIT_OQ=integer\r
+OSERDES SRVAL_OQ=integer\r
+OSERDES INIT_TQ=integer\r
+OSERDES SRVAL_TQ=integer\r
+OSERDES INIT_OQ=integer\r
+OSERDES INIT_TQ=integer\r
+OSERDES SRVAL_OQ=integer\r
+OSERDES SRVAL_TQ=integer\r
+lut_function=\r
+eqn=\r
+INIT_00=\r
+INIT_01=\r
+INIT_02=\r
+INIT_03=\r
+INIT_04=\r
+INIT_05=\r
+INIT_06=\r
+INIT_07=\r
+INIT_08=\r
+INIT_09=\r
+INIT_0A=\r
+INIT_0B=\r
+INIT_0C=\r
+INIT_0D=\r
+INIT_0E=\r
+INIT_0F=\r
+\r
+INIT_10=\r
+INIT_11=\r
+INIT_12=\r
+INIT_13=\r
+INIT_14=\r
+INIT_15=\r
+INIT_16=\r
+INIT_17=\r
+INIT_18=\r
+INIT_19=\r
+INIT_1A=\r
+INIT_1B=\r
+INIT_1C=\r
+INIT_1D=\r
+INIT_1E=\r
+INIT_1F=\r
+\r
+INIT_20=\r
+INIT_21=\r
+INIT_22=\r
+INIT_23=\r
+INIT_24=\r
+INIT_25=\r
+INIT_26=\r
+INIT_27=\r
+INIT_28=\r
+INIT_29=\r
+INIT_2A=\r
+INIT_2B=\r
+INIT_2C=\r
+INIT_2D=\r
+INIT_2E=\r
+INIT_2F=\r
+\r
+INIT_30=\r
+INIT_31=\r
+INIT_32=\r
+INIT_33=\r
+INIT_34=\r
+INIT_35=\r
+INIT_36=\r
+INIT_37=\r
+INIT_38=\r
+INIT_39=\r
+INIT_3A=\r
+INIT_3B=\r
+INIT_3C=\r
+INIT_3D=\r
+INIT_3E=\r
+INIT_3F=\r
+\r
+INIT_40=\r
+INIT_41=\r
+INIT_42=\r
+INIT_43=\r
+INIT_44=\r
+INIT_45=\r
+INIT_46=\r
+INIT_47=\r
+INIT_48=\r
+INIT_49=\r
+INIT_4A=\r
+INIT_4B=\r
+INIT_4C=\r
+INIT_4D=\r
+INIT_4E=\r
+INIT_4F=\r
+\r
+INIT_50=\r
+INIT_51=\r
+INIT_52=\r
+INIT_53=\r
+INIT_54=\r
+INIT_55=\r
+INIT_56=\r
+INIT_57=\r
+INIT_58=\r
+INIT_59=\r
+INIT_5A=\r
+INIT_5B=\r
+INIT_5C=\r
+INIT_5D=\r
+INIT_5E=\r
+INIT_5F=\r
+\r
+INIT_60=\r
+INIT_61=\r
+INIT_62=\r
+INIT_63=\r
+INIT_64=\r
+INIT_65=\r
+INIT_66=\r
+INIT_67=\r
+INIT_68=\r
+INIT_69=\r
+INIT_6A=\r
+INIT_6B=\r
+INIT_6C=\r
+INIT_6D=\r
+INIT_6E=\r
+INIT_6F=\r
+\r
+INITP_00=\r
+INITP_01=\r
+INITP_02=\r
+INITP_03=\r
+INITP_04=\r
+INITP_05=\r
+INITP_06=\r
+INITP_07=\r
+\r
+LPM_TYPE=\r
+LPM_WIDTH=integer\r
+LPM_DIRECTION=\r
+P_WIDTH=\r
+P_OFFSET=\r
+CLKDV_DIVIDE=real\r
+DUTY_CYCLE_CORRECTION=bool\r
+WIDTH=integer\r
+DIVIDE1_BY=integer\r
+DIVIDE2_BY=integer\r
+TimingChecksOn=bool\r
+Xon=bool\r
+MsgOn=bool\r
+SEL_F500K=bool\r
+SEL_F16K=bool\r
+SEL_F490=bool\r
+SEL_F15=bool\r
+\r
+;added for virtex4 library\r
+CLKFX_DIVIDE=integer\r
+CLKFX_MULTIPLY=integer\r
+CLKIN_DIVIDE_BY_2=bool\r
+CLKIN_PERIOD=real\r
+CLKOUT_PHASE_SHIFT=\r
+CLK_FEEDBACK=\r
+DCM_PERFORMANCE_MODE= \r
+DESKEW_ADJUST=\r
+DFS_FREQUENCY_MODE=\r
+DLL_FREQUENCY_MODE=\r
+FACTORY_JF=\r
+STARTUP_WAIT=bool\r
+PHASE_SHIFT=integer\r
+MONITOR_MODE=\r
+SIM_MONITOR_FILE=\r
+JTAG_CHAIN=integer\r
+INIT_OUT=integer\r
+PRESELECT_I0=bool\r
+PRESELECT_I1=bool\r
+BUFR_DIVIDE=\r
+DSS_MODE=\r
+AREG=integer\r
+B_INPUT=\r
+BREG=integer\r
+CARRYINREG=integer\r
+CARRYINSELREG=integer\r
+CREG=integer\r
+LEGACY_MODE=\r
+MREG=integer\r
+OPMODEREG=integer\r
+PREG=integer\r
+SUBTRACTREG=integer\r
+ALMOST_FULL_OFFSET=\r
+ALMOST_EMPTY_OFFSET= \r
+DATA_WIDTH=integer\r
+FIRST_WORD_FALL_THROUGH=bool\r
+REFCLKSEL=\r
+SYNCLK1OUTEN=\r
+SYNCLK2OUTEN=\r
+CAPACITANCE=\r
+IOSTANDARD=\r
+DIFF_TERM=bool\r
+ICAP_WIDTH=\r
+DDR_CLK_EDGE=\r
+INIT_Q1=\r
+INIT_Q2=\r
+INIT_Q3=\r
+INIT_Q4=\r
+SRTYPE=\r
+IOBDELAY=\r
+IOBDELAY_TYPE=\r
+IOBDELAY_VALUE=integer\r
+DRIVE=integer\r
+SLEW=\r
+INIT_BITSLIPCNT=\r
+;INIT_CE= ;2 elems bit_vector\r
+;INIT_RANK1_PARTIAL= ;5 elems bit_vector\r
+;INIT_RANK2= ;6 elems bit_vector\r
+;INIT_RANK3= ;6 elems bit_vector\r
+BITSLIP_ENABLE=bool\r
+DATA_RATE=\r
+INTERFACE_TYPE=\r
+NUM_CE=integer\r
+SERDES_MODE=\r
+SRVAL_Q1=\r
+SRVAL_Q2=\r
+SRVAL_Q3=\r
+SRVAL_Q4=\r
+INIT_LOADCNT=\r
+SERDES_MODE=\r
+DATA_RATE_OQ=\r
+INIT_OQ=\r
+;INIT_ORANK1= ;6 elems bit_vector\r
+INIT_ORANK2_PARTIAL=\r
+DATA_RATE_TQ=\r
+TRISTATE_WIDTH=integer\r
+INIT_TQ=\r
+INIT_TRANK1=\r
+SRVAL_OQ=\r
+SRVAL_TQ=\r
+EN_REL=bool\r
+RST_DEASSERT_CLK=\r
+DOA_REG=integer\r
+DOB_REG=integer\r
+INIT_A=\r
+INIT_B=\r
+INVERT_CLK_DOA_REG=bool\r
+INVERT_CLK_DOB_REG=bool\r
+RAM_EXTENSION_A=\r
+RAM_EXTENSION_B=\r
+READ_WIDTH_A=integer\r
+READ_WIDTH_B=integer\r
+SIM_COLLISION_CHECK=\r
+SRVAL_A=\r
+SRVAL_B=\r
+WRITE_MODE_A=\r
+WRITE_MODE_B=\r
+WRITE_WIDTH_A=integer\r
+WRITE_WIDTH_B=integer\r
+SRVAL=\r
+WRITE_MODE=\r
+DISABLE_COLLISION_CHECK=bool \r
+ALIGN_COMMA_WORD=integer\r
+BANDGAPSEL=bool\r
+CCCB_ARBITRATOR_DISABLE=bool\r
+CHAN_BOND_LIMIT=integer\r
+CHAN_BOND_MODE=\r
+CHAN_BOND_ONE_SHOT=bool\r
+;CHAN_BOND_SEQ_1_1= ;11 elems bit_vector\r
+;CHAN_BOND_SEQ_1_2= ;11 elems bit_vector\r
+;CHAN_BOND_SEQ_1_3= ;11 elems bit_vector \r
+;CHAN_BOND_SEQ_1_4= ;11 elems bit_vector\r
+CHAN_BOND_SEQ_1_MASK=\r
+;CHAN_BOND_SEQ_2_1= ;11 elems bit_vector\r
+;CHAN_BOND_SEQ_2_2= ;11 elems bit_vector\r
+;CHAN_BOND_SEQ_2_3= ;11 elems bit_vector\r
+;CHAN_BOND_SEQ_2_4= ;11 elems bit_vector\r
+CHAN_BOND_SEQ_2_MASK=\r
+CHAN_BOND_SEQ_2_USE=bool\r
+CHAN_BOND_SEQ_LEN=integer\r
+CLK_CORRECT_USE=bool\r
+CLK_COR_8B10B_DE=bool\r
+CLK_COR_MAX_LAT=integer\r
+CLK_COR_MIN_LAT=integer\r
+;CLK_COR_SEQ_1_2= ;11 elems bit_vector\r
+;CLK_COR_SEQ_1_3= ;11 elems bit_vector\r
+;CLK_COR_SEQ_1_4= ;11 elems bit_vector\r
+CLK_COR_SEQ_1_MASK=\r
+;CLK_COR_SEQ_2_1= ;11 elems bit_vector\r
+;CLK_COR_SEQ_2_2= ;11 elems bit_vector\r
+;CLK_COR_SEQ_2_3= ;11 elems bit_vector\r
+;CLK_COR_SEQ_2_4= ;11 elems bit_vector\r
+CLK_COR_SEQ_2_MASK=\r
+CLK_COR_SEQ_2_USE=bool\r
+CLK_COR_SEQ_DROP=bool\r
+CLK_COR_SEQ_LEN=integer\r
+COMMA32=bool\r
+;COMMA_10B_MASK= ;10 elems bit_vector\r
+;CYCLE_LIMIT_SEL= ;2 elems bit_vector\r
+;DCDR_FILTER= ;3 elems bit_vector\r
+DEC_MCOMMA_DETECT=bool\r
+DEC_PCOMMA_DETECT=bool\r
+DEC_VALID_COMMA_ONLY=bool\r
+;DIGRX_FWDCLK= ;2 elems bit_vector\r
+DIGRX_SYNC_MODE=bool\r
+ENABLE_DCDR=bool\r
+;FDET_HYS_CAL= ;3 elems bit_vector\r
+;FDET_HYS_SEL= ;3 elems bit_vector\r
+;FDET_LCK_CAL= ;3 elems bit_vector\r
+;FDET_LCK_SEL= ;3 elems bit_vector\r
+;LOOPCAL_WAIT= ;2 elems bit_vector\r
+MCOMMA_32B_VALUE=\r
+MCOMMA_DETECT=bool\r
+OPPOSITE_SELECT=bool\r
+PCOMMA_32B_VALUE=\r
+PCOMMA_DETECT=bool\r
+PCS_BIT_SLIP=bool\r
+PMACLKENABLE=bool\r
+PMACOREPWRENABLE=bool\r
+PMA_BIT_SLIP=bool\r
+POWER_ENABLE=bool\r
+REPEATER=bool\r
+;RXAFEEQ= ;9 elems bit_vector\r
+;RXASYNCDIVIDE= ;2 elems bit_vector\r
+RXBY_32=bool\r
+;RXCDRLOS= ;6 elems bit_vector\r
+RXCLK0_FORCE_PMACLK=bool\r
+;RXCLKMODE= ;6 elems bit_vector\r
+RXCPSEL=bool\r
+RXCRCCLOCKDOUBLE=bool\r
+RXCRCENABLE=bool\r
+RXCRCINITVAL=\r
+RXCRCINVERTGEN=bool\r
+RXCRCSAMECLOCK=bool\r
+;RXCYCLE_LIMIT_SEL= ;2 elems bit_vector\r
+;RXDATA_SEL= ;2 elems bit_vector\r
+RXDCCOUPLE=bool\r
+RXDIGRESET=bool\r
+RXDIGRX=bool\r
+RXENABLE=bool\r
+RXEQ=\r
+RXFDCAL_CLOCK_DIVIDE=\r
+;RXFDET_HYS_CAL= ;3 elems bit_vector\r
+;RXFDET_HYS_SEL= ;3 elems bit_vector\r
+;RXFDET_LCK_CAL= ;3 elems bit_vector\r
+;RXFDET_LCK_SEL= ;3 elems bit_vector\r
+RXLB=bool\r
+;RXLKADJ= ;5 elems bit_vector\r
+;RXLOOPCAL_WAIT= ;2 elems bit_vector\r
+RXLOOPFILT=\r
+RXOUTDIV2SEL_A=\r
+RXOUTDIV2SEL_B=\r
+RXPD=bool\r
+RXPLLNDIVSEL=\r
+RXPMACLKSEL=\r
+;RXRCPADJ= ;3 elems bit_vector\r
+RXRECCLK1_USE_SYNC=bool\r
+;RXSLOWDOWN_CAL= ;2 elems bit_vector\r
+RXTADJ=bool\r
+RXUSRDIVISOR=integer\r
+;RXVCODAC_INIT= ;10 elems bit_vector\r
+RXVCO_CTRL_ENABLE=bool\r
+RX_BUFFER_USE=bool\r
+;RX_CLOCK_DIVIDER= ;2 elems bit_vector\r
+RX_LOS_INVALID_INCR=integer\r
+RX_LOS_THRESHOLD=integer\r
+SAMPLE_8X=bool\r
+SH_CNT_MAX=integer\r
+SH_INVALID_CNT_MAX=integer\r
+;SLOWDOWN_CAL= ;2 elems bit_vector\r
+TXABPMACLKSEL=\r
+;TXASYNCDIVIDE= ;2 elems bit_vector\r
+TXCLK0_FORCE_PMACLK=bool\r
+TXCLKMODE=\r
+TXCPSEL=bool\r
+TXCRCCLOCKDOUBLE=bool\r
+TXCRCENABLE=bool\r
+TXCRCINITVAL=\r
+TXCRCINVERTGEN=bool\r
+TXCRCSAMECLOCK=bool\r
+;TXDATA_SEL= ;2 elems bit_vector\r
+;TXDAT_PRDRV_DAC= ;3 elems bit_vector\r
+;TXDAT_TAP_DAC= ;5 elems bit_vector\r
+TXENABLE=bool\r
+TXFDCAL_CLOCK_DIVIDE=\r
+TXHIGHSIGNALEN=bool\r
+TXLOOPFILT=\r
+TXOUTCLK1_USE_SYNC=bool\r
+TXOUTDIV2SEL=\r
+TXPD=bool\r
+TXPHASESEL=bool\r
+TXPLLNDIVSEL=\r
+;TXPOST_PRDRV_DAC= ;3 elems bit_vector\r
+;TXPOST_TAP_DAC= ;5 elems bit_vector\r
+TXPOST_TAP_PD=bool\r
+;TXPRE_PRDRV_DAC= ;3 elems bit_vector\r
+;TXPRE_TAP_DAC= ;5 elems bit_vector\r
+TXPRE_TAP_PD=bool\r
+TXSLEWRATE=bool\r
+TXTERMTRIM=\r
+TX_BUFFER_USE=bool\r
+;TX_CLOCK_DIVIDER= ;2 elems bit_vector\r
+;VCODAC_INIT= ;10 elems bit_vector\r
+VCO_CTRL_ENABLE=bool\r
+\r
+\r
+;added for virtex5 library\r
+A_INPUT=\r
+ACASCREG=integer\r
+ALUMODEREG=integer\r
+AUTORESET_PATTERN_DETEC=boolean\r
+AUTORESET_PATTERN_DETECT_OPTINV=\r
+BANDWIDTH=\r
+BCASCREG=integer\r
+CLKFBOUT_MULT=integer\r
+CLKFBOUT_PHASE=real\r
+CLKIN1_PERIOD=real\r
+CLKIN2_PERIOD=real\r
+CLKOUT0_DIVIDE=integer\r
+CLKOUT0_DUTY_CYCLE=real\r
+CLKOUT0_PHASE=real\r
+CLKOUT1_DIVIDE=integer\r
+CLKOUT1_DUTY_CYCLE=real\r
+CLKOUT1_PHASE=real\r
+CLKOUT2_DIVIDE=integer\r
+CLKOUT2_DUTY_CYCLE=real\r
+CLKOUT2_PHASE=real \r
+CLKOUT3_DIVIDE=integer\r
+CLKOUT3_DUTY_CYCLE=real\r
+CLKOUT3_PHASE=real \r
+CLKOUT4_DIVIDE=integer \r
+CLKOUT4_DUTY_CYCLE=real \r
+CLKOUT4_PHASE=real \r
+CLKOUT5_DIVIDE=integer \r
+CLKOUT5_DUTY_CYCLE=real \r
+CLKOUT5_PHASE=real\r
+COMPENSATION=\r
+CRC_INIT=\r
+DELAY_SRC=\r
+DIVCLK_DIVIDE=integer\r
+DO_REG=integer\r
+EN_ECC_READ=boolean\r
+EN_ECC_SCRUB=boolean\r
+EN_ECC_WRITE=boolean \r
+EN_SYN=boolean\r
+IDELAY_TYPE=\r
+IDELAY_VALUE=integer\r
+INIT_70= \r
+INIT_71= \r
+INIT_72= \r
+INIT_73= \r
+INIT_74= \r
+INIT_75= \r
+INIT_76= \r
+INIT_77= \r
+INIT_78= \r
+INIT_79= \r
+INIT_7A= \r
+INIT_7B= \r
+INIT_7C= \r
+INIT_7D= \r
+INIT_7E= \r
+INIT_7F= \r
+INIT_C=\r
+INIT_D=\r
+INITP_08=\r
+INITP_09=\r
+INITP_0A=\r
+INITP_0B=\r
+INITP_0C=\r
+INITP_0D=\r
+INITP_0E=\r
+INITP_0F=\r
+MASK= \r
+MULTCARRYINREG=integer\r
+ODELAY_VALUE=integer\r
+PATTERN=\r
+PLL_PMCD_MODE=boolean \r
+POLYNOMIAL=\r
+REF_JITTER=real\r
+RESET_ON_LOSS_OF_LOCK=boolean\r
+SEL_MASK=\r
+SEL_PATTERN=\r
+SEL_ROUNDING_MASK=\r
+USE_MULT=\r
+USE_PATTERN_DETECT=\r
+USE_SIMD=\r
+;end of virtex5\r
+\r
+;added for virtex5 (ise9.1i sp2)\r
+CLKFBOUT_DESKEW_ADJUST=\r
+CLKOUT0_DESKEW_ADJUST=\r
+CLKOUT1_DESKEW_ADJUST=\r
+CLKOUT2_DESKEW_ADJUST=\r
+CLKOUT3_DESKEW_ADJUST=\r
+CLKOUT4_DESKEW_ADJUST=\r
+CLKOUT5_DESKEW_ADJUST=\r
+;end of virtex5 (ise9.1i sp2)\r
+\r
+;added for virtex5 (ise9.2i sp1)\r
+PCS_COM_CFG=\r
+SIGNAL_PATTERN=\r
+INIT_FILE=\r
+;end of virtex5 (ise9.2i sp1)\r
+\r
+;added for virtex5 (ise 10.1i)\r
+SIM_MODE=\r
+;end\r
+\r
+;added for spartan6, virtex6 (ise 11.2)\r
+A0REG=integer\r
+A1REG=integer\r
+AC_CAP_DIS_0=boolean\r
+AC_CAP_DIS_1=boolean\r
+ADREG=integer\r
+AUTORESET_PATDET=\r
+B0REG=integer\r
+B1REG=integer\r
+BUFFER_TYPE=\r
+BYPASS_GCLK_FF=boolean\r
+CARRYINSEL=\r
+CARRYOUTREG=integer\r
+CHAN_BOND_2_MAX_SKEW_0=integer\r
+CINVCTRL_SEL=boolean\r
+CLK_SEL_TYPE=\r
+CLKCM_CFG=boolean\r
+CLKFBOUT_MULT_F=real\r
+CLKFXDV_DIVIDE=integer\r
+CLKFX_MD_MAX=real\r
+CLKFBOUT_USE_FINE_PS=boolean\r
+CLKOUT0_DIVIDE_F=real\r
+CLKOUT0_USE_FINE_PS=boolean\r
+CLKOUT1_USE_FINE_PS=boolean\r
+CLKOUT2_USE_FINE_PS=boolean\r
+CLKOUT3_USE_FINE_PS=boolean\r
+CLKOUT4_CASCADE=boolean\r
+CLKOUT4_USE_FINE_PS=boolean\r
+CLKOUT5_USE_FINE_PS=boolean\r
+CLKOUT6_DIVIDE=integer \r
+CLKOUT6_DUTY_CYCLE=real \r
+CLKOUT6_PHASE=real\r
+CLKOUT6_USE_FINE_PS=boolean\r
+CLKRCV_TRST=boolean\r
+CLOCK_HOLD=boolean\r
+COUNTER_WRAPAROUND=\r
+DATA_RATE_OT=\r
+DDR3_DATA=integer\r
+DISABLE_JTAG=boolean\r
+DIVIDE_BYPASS=boolean\r
+DIVIDE=integer\r
+DFS_BANDWIDTH=\r
+DQSMASK_ENABLE=boolean\r
+DYN_CLK_INV_EN=boolean\r
+DYN_CLKDIV_INV_EN=boolean\r
+EN_RSTRAM_A=boolean\r
+EN_RSTRAM_B=boolean\r
+FARSRC=\r
+HIGH_PERFORMANCE_MODE=boolean\r
+I_INVERT=boolean\r
+IBUF_DELAY_VALUE=\r
+IBUF_LOW_PWR=boolean\r
+IDELAY2_VALUE=integer\r
+IDELAY_MODE=\r
+IFD_DELAY_VALUE=\r
+ISERDESE1 INIT_Q1=integer\r
+ISERDESE1 INIT_Q2=integer\r
+ISERDESE1 INIT_Q3=integer\r
+ISERDESE1 INIT_Q4=integer\r
+OSERDESE1 INIT_OQ=integer\r
+OSERDESE1 INIT_TQ=integer\r
+INMODEREG=integer\r
+InstancePath=\r
+ODELAY_TYPE=\r
+OFB_USED=boolean\r
+ONESHOT=boolean\r
+OUTPUT_MODE=\r
+PROG_MD_BANDWIDTH=\r
+PROG_USR=boolean\r
+RAM_MODE=\r
+REF_JITTER1=real\r
+REF_JITTER2=real\r
+REFCLK_FREQUENCY=real\r
+;REFCLKOUT_DLY= ;10 elems bit_vector\r
+RST_PRIORITY_A=\r
+RST_PRIORITY_B=\r
+RSTREG_PRIORITY_A=\r
+RSTREG_PRIORITY_B=\r
+RSTTYPE=\r
+SETUP_ALL=\r
+SIM_DEVICE=\r
+SIM_EFUSE_VALUE=\r
+SIM_TAPDELAY_VALUE=integer\r
+SPREAD_SPECTRUM=\r
+ISERDESE1 SRVAL_Q1=integer\r
+ISERDESE1 SRVAL_Q2=integer\r
+ISERDESE1 SRVAL_Q3=integer\r
+ISERDESE1 SRVAL_Q4=integer\r
+OSERDESE1 SRVAL_OQ=integer\r
+OSERDESE1 SRVAL_TQ=integer\r
+TRAIN_PATTERN=integer\r
+USE_DOUBLER=boolean\r
+USE_DPORT=boolean\r
+;end of spartan6, virtex6 (ise 11.2)\r
+\r
+[$LIBMAP$]\r
+work=.\r
+xilinx=xabelsim\r
+xilinxun=\r
+simprims=simprim\r
+DESIGNS=\r
+\r
+;FPGA Express\r
+VIRTEXE=VIRTEX\r
+COOLRUNNER=XC9500\r
+COOLRUNNER2=COOLRUNNERII\r
+SPARTAN2E=SPARTAN2E\r
+SPARTAN3=SPARTAN3\r
+SPARTAN3A=SPARTAN3A\r
+SPARTAN3E=SPARTAN3E\r
+SPARTANXL=SPARTANX\r
+XC3000A=XC3000\r
+XC3000L=XC3000\r
+XC3100A=XC3000\r
+XC3100L=XC3000\r
+XC4000EX=XC4000X\r
+XC4000L=XC4000E\r
+XC4000XL=XC4000X\r
+XC4000XLA=XC4000X\r
+XC4000XV=XC4000X\r
+XC9500XL=XC9500\r
+XC9500XV=XC9500\r
+\r
+;Synplify\r
+COOLRUNNERII=COOLRUNNERII\r
+Unilib=unisim\r
+XC4000=unisim\r
+XC5000=unisim\r
+\r
+;Exemplar\r
+xcv=unisim\r
+xcv2=unisim\r
+xcv2p=unisim\r
+xcve=unisim\r
+xi3=unisim\r
+xi31=unisim\r
+xi31a=unisim\r
+xi3a=unisim\r
+xi3l=unisim\r
+xi3t=unisim\r
+xi4=unisim\r
+xi4a=unisim\r
+xi4e=unisim\r
+xi4et=unisim\r
+xi4ex=unisim\r
+xi4h=unisim\r
+xi4l=unisim\r
+xi4t=unisim\r
+xi4xl=unisim\r
+xi4xla=unisim\r
+xi4xv=unisim\r
+xi5=unisim\r
+xi5t=unisim\r
+xi72a=unisim\r
+xi73=unisim\r
+xi7t=unisim\r
+xi95=unisim\r
+xi95xl=unisim\r
+xi95xv=unisim\r
+xis=unisim\r
+xis2=unisim\r
+xis2e=unisim\r
+xis3=unisim\r
+xisxl=unisim\r
+Active_lib=\r
+UnlinkedDesignLibrary=\r
+\r
+[$GSRGTS$]\r
+GSR=\r
+GR=\r
+GTS=\r
+PRLD=\r
+\r
+[$INCLUDE$]\r
+line1=library IEEE;\r
+line2=use IEEE.std_logic_1164.all;\r
+line3=library UNISIM;\r
+line4=use UNISIM.vcomponents.all;\r
+line5=library SIMPRIM;\r
+line6=use SIMPRIM.vcomponents.all;\r
+\r
+[TBUF]\r
+.=BUFT\r
+\r
+[VCC]\r
+VCC=P\r
+\r
+[GND]\r
+ground=G\r
+\r
+[X_FF]\r
+IN=I\r
+OUT=O\r
+\r
+;[OPAD]\r
+;OPAD=I\r
+;PAD=I\r
+\r
+;[IPAD]\r
+;IPAD=I\r
+;PAD=I\r
+\r
+;[IOPAD]\r
+;IOPAD=I\r
+;PAD=I\r
+\r
+[X_PU]\r
+OUT=O\r
+\r
+[X_LATCH]\r
+IN=I\r
+OUT=O\r
+\r
+[X_LATCHE]\r
+IN=I\r
+OUT=O\r
+\r
+[x_tri]\r
+IN=I\r
+OUT=O\r
+\r
+[x_buf]\r
+IN=I\r
+OUT=O\r
+\r
+[x_zero]\r
+OUT=O\r
+[x_one]\r
+OUT=O\r
+\r
+[x_and2]\r
+OUT=O\r
+IN1=I1\r
+IN0=I0\r
+\r
+[x_inv]\r
+IN=I\r
+OUT=O\r
+\r
+[x_or2]\r
+IN0=I0\r
+IN1=I1\r
+OUT=O\r
+\r
+[x_ckbuf]\r
+IN=I\r
+OUT=O\r
+\r
+[x_and3]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+OUT=O\r
+\r
+[x_and4]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+OUT=O\r
+\r
+[x_and5]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+OUT=O\r
+\r
+[x_and6]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+IN5=I5\r
+OUT=O\r
+\r
+[x_and7]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+IN5=I5\r
+IN6=I6\r
+OUT=O\r
+\r
+[x_and8]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+IN5=I5\r
+IN6=I6\r
+IN7=I7\r
+OUT=O\r
+\r
+[x_and16]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+IN5=I5\r
+IN6=I6\r
+IN7=I7\r
+IN8=I8\r
+IN9=I9\r
+IN10=I10\r
+IN11=I11\r
+IN12=I12\r
+IN13=I13\r
+IN14=I14\r
+IN15=I15\r
+OUT=O\r
+\r
+[x_or2]\r
+IN0=I0\r
+IN1=I1\r
+OUT=O\r
+\r
+[x_or3]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+OUT=O\r
+\r
+[x_or4]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+OUT=O\r
+\r
+[x_or5]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+OUT=O\r
+\r
+[x_or6]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+IN5=I5\r
+OUT=O\r
+\r
+[x_or7]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+IN5=I5\r
+IN6=I6\r
+OUT=O\r
+\r
+\r
+[x_or8]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+IN5=I5\r
+IN6=I6\r
+IN7=I7\r
+OUT=O\r
+\r
+[x_or16]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+IN5=I5\r
+IN6=I6\r
+IN7=I7\r
+IN8=I8\r
+IN9=I9\r
+IN10=I10\r
+IN11=I11\r
+IN12=I12\r
+IN13=I13\r
+IN14=I14\r
+IN15=I15\r
+OUT=O\r
+\r
+[x_xor2]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+OUT=O\r
+\r
+[x_xor3]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+OUT=O\r
+\r
+[x_xor4]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+OUT=O\r
+\r
+[x_xor5]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+OUT=O\r
+\r
+\r
+[x_lut2]\r
+OUT=O\r
+\r
+[x_lut3]\r
+OUT=O\r
+\r
+[x_lut4]\r
+OUT=O\r
+\r
+[x_RAM16]\r
+OUT=O\r
+IN=I\r
+\r
+[x_RAM32]\r
+OUT=O\r
+IN=I\r
+\r
+[x_RAMS16]\r
+OUT=O\r
+IN=I\r
+\r
+[x_RAMS32]\r
+OUT=O\r
+IN=I\r
+\r
+[x_RAMD16]\r
+OUT=O\r
+IN=I\r
+\r
+[x_RAMD32]\r
+OUT=O\r
+IN=I\r
+\r
+[x_MUX2]\r
+OUT=O\r
+INA=IA\r
+INB=IB\r
+\r
+[x_OR32]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+IN5=I5\r
+IN6=I6\r
+IN7=I7\r
+IN8=I8\r
+IN9=I9\r
+IN10=I10\r
+IN11=I11\r
+IN12=I12\r
+IN13=I13\r
+IN14=I14\r
+IN15=I15\r
+IN16=I16\r
+IN17=I17\r
+IN18=I18\r
+IN19=I19\r
+IN20=I20\r
+IN21=I21\r
+IN22=I22\r
+IN23=I23\r
+IN24=I24\r
+IN25=I25\r
+IN26=I26\r
+IN27=I27\r
+IN28=I28\r
+IN29=I29\r
+IN30=I30\r
+IN31=I31\r
+OUT=O\r
+\r
+[x_PD]\r
+OUT=O\r
+\r
+[x_XOR16]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+IN5=I5\r
+IN6=I6\r
+IN7=I7\r
+IN8=I8\r
+IN9=I9\r
+IN10=I10\r
+IN11=I11\r
+IN12=I12\r
+IN13=I13\r
+IN14=I14\r
+IN15=I15\r
+OUT=O\r
+\r
+[x_XOR32]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+IN5=I5\r
+IN6=I6\r
+IN7=I7\r
+IN8=I8\r
+IN9=I9\r
+IN10=I10\r
+IN11=I11\r
+IN12=I12\r
+IN13=I13\r
+IN14=I14\r
+IN15=I15\r
+IN16=I16\r
+IN17=I17\r
+IN18=I18\r
+IN19=I19\r
+IN20=I20\r
+IN21=I21\r
+IN22=I22\r
+IN23=I23\r
+IN24=I24\r
+IN25=I25\r
+IN26=I26\r
+IN27=I27\r
+IN28=I28\r
+IN29=I29\r
+IN30=I30\r
+IN31=I31\r
+OUT=O\r
+\r
+[x_AND32]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+IN5=I5\r
+IN6=I6\r
+IN7=I7\r
+IN8=I8\r
+IN9=I9\r
+IN10=I10\r
+IN11=I11\r
+IN12=I12\r
+IN13=I13\r
+IN14=I14\r
+IN15=I15\r
+IN16=I16\r
+IN17=I17\r
+IN18=I18\r
+IN19=I19\r
+IN20=I20\r
+IN21=I21\r
+IN22=I22\r
+IN23=I23\r
+IN24=I24\r
+IN25=I25\r
+IN26=I26\r
+IN27=I27\r
+IN28=I28\r
+IN29=I29\r
+IN30=I30\r
+IN31=I31\r
+OUT=O\r
+\r
+[x_XOR6]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+IN5=I5\r
+OUT=O\r
+\r
+[x_XOR7]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+IN5=I5\r
+IN6=I6\r
+OUT=O\r
+\r
+[x_XOR8]\r
+IN0=I0\r
+IN1=I1\r
+IN2=I2\r
+IN3=I3\r
+IN4=I4\r
+IN5=I5\r
+IN6=I6\r
+IN7=I7\r
+OUT=O\r
+\r
+[X_SFF]\r
+IN=I\r
+OUT=O\r
+\r
+[X_SUH]\r
+IN=I\r
+\r
+[FDCE]\r
+GSR=$HIDDEN$\r
+[FDPE]\r
+GSR=$HIDDEN$\r
+[IFDX]\r
+GSR=$HIDDEN$\r
+[IFDXI]\r
+GSR=$HIDDEN$\r
+[ILDX_1]\r
+GSR=$HIDDEN$\r
+GTS=$HIDDEN$\r
+[ILDXI_1]\r
+GSR=$HIDDEN$\r
+GTS=$HIDDEN$\r
+[ILFFX]\r
+GSR=$HIDDEN$\r
+[ILFFXI]\r
+GSR=$HIDDEN$\r
+[ILFLX_1]\r
+GSR=$HIDDEN$\r
+GTS=$HIDDEN$\r
+[ILFLXI_1]\r
+GSR=$HIDDEN$\r
+GTS=$HIDDEN$\r
+[LDCE_1]\r
+GSR=$HIDDEN$\r
+GTS=$HIDDEN$\r
+[LDPE]\r
+GSR=$HIDDEN$\r
+GTS=$HIDDEN$\r
+[LDPE_1]\r
+GSR=$HIDDEN$\r
+GTS=$HIDDEN$\r
+[OAND2]\r
+GTS=$HIDDEN$\r
+[OBUF]\r
+GTS=$HIDDEN$\r
+[OBUFT]\r
+GTS=$HIDDEN$\r
+[OFDTX]\r
+GSR=$HIDDEN$\r
+GTS=$HIDDEN$\r
+[OFDTXI]\r
+GSR=$HIDDEN$\r
+GTS=$HIDDEN$\r
+[OFDX]\r
+GSR=$HIDDEN$\r
+GTS=$HIDDEN$\r
+[OFDXI]\r
+GTS=$HIDDEN$\r
+GSR=$HIDDEN$\r
+[OMUX2]\r
+GTS=$HIDDEN$\r
+[ONAND2]\r
+GTS=$HIDDEN$\r
+[ONOR2]\r
+GTS=$HIDDEN$\r
+[OOR2]\r
+GTS=$HIDDEN$\r
+[OXNOR2]\r
+GTS=$HIDDEN$\r
+[OXOR2]\r
+GTS=$HIDDEN$\r
--- /dev/null
+[View]\r
+Entity=testbench\r
+Architecture=behavior\r
+TopLevelType=1\r
--- /dev/null
+38
+~E 1 "./../../../trbnet/special/spi_slim.vhd" 12 spi_slim
+~A 1 "./../../../trbnet/special/spi_slim.vhd" 44 behavioral
+~E 1 "./../../../trbnet/special/spi_master.vhd" 10 spi_master
+~A 1 "./../../../trbnet/special/spi_master.vhd" 37 behavioral
+~E 1 "./../../sim/tb_spi_master.vhd" 5 testbench
+~A 1 "./../../sim/tb_spi_master.vhd" 8 behavior
--- /dev/null
+[Files List]\r
+X:\Programme\ispTOOLS_80\active-hdl\vlib\Std/src/standard.vhd=S\r
+X:\Programme\ispTOOLS_80\active-hdl\vlib\Std/src/textio.vhd=S\r
+X:\Programme\ispTOOLS_80\active-hdl\vlib\ieee/src/std_logic_1164.vhdl=S\r
+X:\Programme\ispTOOLS_80\active-hdl\vlib\ieee/src/std_logic_1164-body.vhdl=S\r
+X:\Programme\ispTOOLS_80\active-hdl\vlib\ieee/src/arith_p.vhd=S\r
+X:\Programme\ispTOOLS_80\active-hdl\vlib\ieee/src/arith_b.vhd=S\r
+X:\Programme\ispTOOLS_80\active-hdl\vlib\ieee/src/unsigned_p.vhd=S\r
+X:\Programme\ispTOOLS_80\active-hdl\vlib\ieee/src/unsigned_b.vhd=S\r
+I:\VHDL_Pro\trbnet\trb_net_std.vhd=S\r
+X:\Programme\ispTOOLS_80\active-hdl\vlib\ieee/src/numeric_std.vhdl=S\r
+X:\Programme\ispTOOLS_80\active-hdl\vlib\ieee/src/numeric_std-body.vhdl=S\r
+I:\VHDL_Pro\trbnet\trb_net_components.vhd=S\r
+I:\VHDL_Pro\trbnet\special\spi_slim.vhd=S\r
+I:\VHDL_Pro\trbnet\special\spi_master.vhd=S\r
+I:\VHDL_Pro\comp_adcmv3\sim\tb_spi_master.vhd=S\r
--- /dev/null
+-w -s "I:\VHDL_Pro\comp_adcmv3\lever\work\library.cfg" -j "I:\VHDL_Pro\comp_adcmv3\lever\work\projlib.cfg" -d "I:\VHDL_Pro\comp_adcmv3\lever\work\compile" -work work -dbg -e 100 "I:\VHDL_Pro\comp_adcmv3\sim\tb_spi_master.vhd"
\ No newline at end of file
--- /dev/null
+"I:\VHDL_Pro\comp_adcmv3\sim\tb_spi_master.vhd" VHDL work 1 0 809000787\r
+. . 0 0 0
\ No newline at end of file
--- /dev/null
+MESSAGE "File: I:\VHDL_Pro\comp_adcmv3\sim\tb_spi_master.vhd"
+MESSAGE "Compile Entity "testbench""
+MESSAGE "Compile Architecture "behavior" of Entity "testbench""
+SUCCESS "Compile success 0 Errors 0 Warnings Analysis time : 0.2 [s]"
--- /dev/null
+$include = "X:\Programme\ispTOOLS_80\active-hdl\vlib\"\r
+work = "./work.LIB" 1275040549217\r
--- /dev/null
+work = "./work.LIB" 1275040548732
--- /dev/null
+timestamp=1318408986650\r
+\r
+[adcmv3_components]\r
+C=8.2.1986.3485 (Windows)\r
+E=1*516\r
+I=0*51289\r
+M=3|0|v63|1318408980306|./../../design/adcmv3_components.vhd|0*2687*0x812ed3a1beb8f12b3ddb496c1a8e2306b1ddff49|0*51188*0x7bd7e13dc0415552f89596087806a8cf\r
+R=./../../design/adcmv3_components.vhd|8\r
+\r
+[lattice_ecp2m_fifo]\r
+C=8.2.1986.3485 (Windows)\r
+E=1*111484\r
+I=0*68957\r
+M=3|0|v63|1318408981494|./../../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd|0*63283*0xbd21e067de90881e723fea8f31ac1e4dbef34089|0*68837*0x7bd7e13dc0415552f89596087806a8cf\r
+R=./../../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd|8\r
+\r
+[spi_master]\r
+A/behavioral=A/Behavioral 21|./../../../trbnet/special/spi_master.vhd|37|1*275070\r
+B/behavioral=3*79011\r
+C=8.2.1986.3485 (Windows)\r
+C/behavioral=8.2.1986.3485 (Windows)\r
+I=0*172404\r
+I/behavioral=I/Behavioral 0*177642\r
+M=11|0|v63|1318408985775|./../../../trbnet/special/spi_master.vhd|0*171395*0x50075b078eb61e33b3c6d60967ca51592929a240|0*172306*0x7bd7e13dc0415552f89596087806a8cf\r
+M/behavioral=M/Behavioral 21|0|v63|1318408985777|./../../../trbnet/special/spi_master.vhd|0*172765*0xe4c9fd9afb59db5d4e7e55060cb13a5e685a2f9c|0*177530*0x7bd7e13dc0415552f89596087806a8cf\r
+R=./../../../trbnet/special/spi_master.vhd|10\r
+\r
+[spi_slim]\r
+A/behavioral=A/Behavioral 21|./../../../trbnet/special/spi_slim.vhd|44|1*253319\r
+B/behavioral=3*13832\r
+C=8.2.1986.3485 (Windows)\r
+C/behavioral=8.2.1986.3485 (Windows)\r
+I=0*157965\r
+I/behavioral=I/Behavioral 0*170328\r
+M=11|0|v63|1318408984791|./../../../trbnet/special/spi_slim.vhd|0*156830*0x623482ed3c1451f4e16e04faaa21adca5478f018|0*157871*0x7bd7e13dc0415552f89596087806a8cf\r
+M/behavioral=M/Behavioral 21|0|v63|1318408985025|./../../../trbnet/special/spi_slim.vhd|0*158324*0x8a5760de9efc9dde3d0e1c92497bca1fe9c80f13|0*170220*0x7bd7e13dc0415552f89596087806a8cf\r
+R=./../../../trbnet/special/spi_slim.vhd|12\r
+\r
+[testbench]\r
+A/behavior=21|./../../sim/tb_spi_master.vhd|8|1*287923\r
+B/behavior=3*93674\r
+C=8.2.1986.3485 (Windows)\r
+C/behavior=8.2.1986.3485 (Windows)\r
+I=0*178415\r
+I/behavior=0*182405\r
+M=11|0|v63|1318408986462|./../../sim/tb_spi_master.vhd|0*178142*0x563a33b1fd4375ff00a1a7d08e5fd2a9a4d47cba|0*178329*0x7bd7e13dc0415552f89596087806a8cf\r
+M/behavior=21|0|v63|1318408986509|./../../sim/tb_spi_master.vhd|0*178580*0xe4a07397d47420a86c685eab0a1ee1c5070c855c|0*182307*0x7bd7e13dc0415552f89596087806a8cf\r
+R=./../../sim/tb_spi_master.vhd|5\r
+\r
+[trb_net_components]\r
+C=8.2.1986.3485 (Windows)\r
+E=1*119632\r
+I=0*155722\r
+M=3|0|v63|1318408982228|./../../../trbnet/trb_net_components.vhd|0*72108*0x9093fd766f8923453bde12c2fcf467e32d9a9a2e|0*155616*0x7bd7e13dc0415552f89596087806a8cf\r
+R=./../../../trbnet/trb_net_components.vhd|8\r
+\r
+[trb_net_std]\r
+B/trb_net_std=3*0\r
+C=8.2.1986.3485 (Windows)\r
+E=1*236505\r
+I=0*60140\r
+I/trb_net_std=0*62428\r
+M=3|0|v63|1318408980822|./../../../trbnet/trb_net_std.vhd|0*54820*0xd42dc11fec28e37bee8b232cc04dd43c4182f82b|0*60048*0x7bd7e13dc0415552f89596087806a8cf\r
+M/trb_net_std=4|0|v63|1318408983823|./../../../trbnet/trb_net_std.vhd|0*60379*0xb0143da045f0ac3f4d2ba985762b1b8f5518aac5|0*62322*0x7bd7e13dc0415552f89596087806a8cf\r
+R=./../../../trbnet/trb_net_std.vhd|7\r
+\r
+[version]\r
+C=8.2.1986.3485 (Windows)\r
+E=1*0\r
+I=0*512\r
+M=3|0|v63|1318408979775|./../../version.vhd|0*161*0x41161cc985896d40e735f20b7e039aa01115d9c8|0*438*0x7bd7e13dc0415552f89596087806a8cf\r
+R=./../../version.vhd|9\r
+\r
+[~A]\r
+ModifyID=38\r
+Version=73\r
+\r
+[~MFT]\r
+0=48|0work.mgf|182405|0\r
+1=9|1work.mgf|287923|16814\r
+3=3|3work.mgf|93674|0\r
+\r
+[~U]\r
+adcmv3_components=3|0*808|0*905\r
+lattice_ecp2m_fifo=3|0*62679|0*62779\r
+spi_master=11|0*170698|\r
+spi_slim=11|0*156022|\r
+testbench=11|0*178069|\r
+trb_net_components=3|0*69189|0*69289\r
+trb_net_std=3|0*51462|0*51859\r
+version=3|0*0|0*67\r
+\r
--- /dev/null
+[Project]\r
+Current Flow=generic\r
+VCS=0\r
+version=2\r
+Current Config=compile\r
+\r
+[Configurations]\r
+compile=work\r
+\r
+[Library]\r
+work=.\work.lib\r
+\r
+[Settings]\r
+AccessRead=0\r
+AccessReadWrite=0\r
+AccessACCB=0\r
+AccessACCR=0\r
+AccessReadWriteSLP=0\r
+AccessReadTopLevel=0\r
+DisableC=0\r
+ENABLE_ADV_DATAFLOW=1\r
+EnableCC=0\r
+EnableEXC=0\r
+FLOW_TYPE=HDL\r
+LANGUAGE=VHDL\r
+REFRESH_FLOW=1\r
+\r
+[LocalVerilogSets]\r
+EnableSLP=0\r
+EnableDebug=1\r
+EnableExpressionCoverage=0\r
+\r
+[LocalVhdlSets]\r
+EnableExpressionCoverage=0\r
+CompileWithDebug=1\r
+\r
+[$LibMap$]\r
+work=.\r
+\r
+[HierarchyViewer]\r
+SortInfo=u\r
+HierarchyInformation=testbench|behavior|0 \r
+ShowHide=ShowTopLevel\r
+Selected=\r
--- /dev/null
+[Version]\r
+Version=8.2\r
+[Designs]\r
+work=work.adf\r
+[Settings]\r
+Active=work\r
+[Expand]\r
+work=1\r
+[Browser]\r
+sort=order\r
+mode=none\r
+[Order]\r
+order=1\r
+macro=\r
--- /dev/null
+[General]\r
+CurrentVersion=103\r
+[CACHEDOC|Aldec.Project.Generic.7|I:\VHDL_Pro\comp_adcmv3\lever\work\work.adf|]\r
+Path=\r
+THE_START_PROC\r
+[CACHEDOC|Aldec.Hde.HdePlugIn.7|I:\VHDL_Pro\comp_adcmv3\sim\tb_ped_corr_ctrl.vhd|]\r
+CurrentLine=0\r
+CurrentColumn=0\r
+Bookmarks=-1\r
+BookmarksLength=3\r
+Frame=0\r
+WindowWorkspaceInfo=2C0000000000000003000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB000000750000000005000093020000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C800000000000000000000000000000000000000090000000100000029\r
+[CACHEDOC|Aldec.Hde.HdePlugIn.7|I:\VHDL_Pro\trbnet\trb_net_components.vhd|]\r
+CurrentLine=5\r
+CurrentColumn=8\r
+Bookmarks=-1\r
+BookmarksLength=3\r
+Frame=0\r
+WindowWorkspaceInfo=2C0000000000000003000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB0000007500000000050000FE020000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C800000000000000000000000000000000000000090000000100000094\r
+[CACHEDOC|Aldec.Hde.HdePlugIn.7|I:\VHDL_Pro\comp_adcmv3\design\test_media.vhd|]\r
+CurrentLine=216\r
+CurrentColumn=6\r
+Bookmarks=-1\r
+BookmarksLength=3\r
+Frame=0\r
+WindowWorkspaceInfo=2C0000000000000003000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB000000750000000005000093020000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C800000000000000000000000000000000000000090000000100000029\r
+[CACHEDOC|Aldec.Hde.HdePlugIn.7|I:\VHDL_Pro\comp_adcmv3\sim\tb_sfp_rx_handler.vhd|]\r
+CurrentLine=164\r
+CurrentColumn=1\r
+Bookmarks=-1\r
+BookmarksLength=3\r
+Frame=0\r
+WindowWorkspaceInfo=2C0000000000000003000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB000000750000000005000093020000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C800000000000000000000000000000000000000090000000100000029\r
+[CACHEDOC|Aldec.Hde.HdePlugIn.7|I:\VHDL_Pro\comp_adcmv3\sim\tb_media_fifo_mb.vhd|]\r
+CurrentLine=83\r
+CurrentColumn=17\r
+Bookmarks=-1\r
+BookmarksLength=3\r
+Frame=0\r
+WindowWorkspaceInfo=2C0000000000000003000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB000000750000000005000093020000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C800000000000000000000000000000000000000090000000100000029\r
+[CACHEDOC|Aldec.Hde.HdePlugIn.7|I:\VHDL_Pro\comp_adcmv3\sim\tb_apv_trgctrl.vhd|]\r
+CurrentLine=90\r
+CurrentColumn=0\r
+Bookmarks=-1\r
+BookmarksLength=3\r
+Frame=0\r
+WindowWorkspaceInfo=2C0000000000000003000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB0000007500000000050000FE020000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C800000000000000000000000000000000000000090000000100000094\r
+[Gui config]\r
+RunFor=10us\r
+[OPENDOC|Aldec.Hde.HdePlugIn.7|I:\VHDL_Pro\trbnet\trb_net_components.vhd|]\r
+CurrentLine=5\r
+CurrentColumn=8\r
+Bookmarks=-1\r
+BookmarksLength=3\r
+Frame=0\r
+WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF150100007500000000050000FE020000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C8000000000000000000000000000000000000000900000001000000DD\r
+[OPENDOC|Aldec.Hde.HdePlugIn.7|I:\VHDL_Pro\trbnet\special\spi_master.vhd|]\r
+CurrentLine=92\r
+CurrentColumn=1\r
+Bookmarks=-1\r
+BookmarksLength=3\r
+Frame=0\r
+WindowWorkspaceInfo=2C0000000000000001000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF150100007500000000050000FE020000000000000000000005000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C8000000C80000000000000000000000C8000000C8000000000000000000000000000000000000000900000001000000DD\r
--- /dev/null
+[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\..\..\trbnet\trb_net_components.vhd|]\r
+TemplateId=0\r
+[OPENDOC|Aldec.Hde.HdePlugIn.7|.\..\..\..\trbnet\special\spi_master.vhd|]\r
+TemplateId=0\r
+++ /dev/null
-Backplane 0
-===========
-
-ADC0/0 0 0/6 3 0xb000 0x20030001
-ADC0/1 1 0/7 5 0xb001 0x20050001
-ADC0/2 2 0/0 10 0xb002 0x200a0001
-ADC0/3 3 0/2 12 0xb003 0x200c0001
-ADC0/4 4 0/1 9 0xb004 0x20090001
-ADC0/5 5 0/3 7 0xb005 0x20070001
-ADC0/6 6 0/5 0 0xb006 0x20000001
-ADC0/7 7 -/- -- 0xb007 0x200f0001
-
-ADC1/0 8 1/6 4 0xb008 0x20040001
-ADC1/1 9 1/7 6 0xb009 0x20060001
-ADC1/2 10 1/1 11 0xb00a 0x200b0001
-ADC1/3 11 1/0 8 0xb00b 0x20080001
-ADC1/4 12 1/3 14 0xb00c 0x200e0001
-ADC1/5 13 1/2 13 0xb00d 0x200d0001
-ADC1/6 14 1/5 2 0xb00e 0x20020001
-ADC1/7 15 1/4 1 0xb00f 0x20010001
-
-realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-mapAPV 3 5 10 12 9 7 0 - 4 6 11 8 14 13 2 1
-
-Backplane 1
-==========
-
-ADC0/0 0 0/6 12 0xb000 0x200c0001
-ADC0/1 1 0/7 11 0xb001 0x200b0001
-ADC0/2 2 0/0 10 0xb002 0x200a0001
-ADC0/3 3 0/2 9 0xb003 0x20090001
-ADC0/4 4 0/1 8 0xb004 0x20080001
-ADC0/5 5 0/3 7 0xb005 0x20070001
-ADC0/6 6 0/5 13 0xb006 0x200d0001
-ADC0/7 7 0/4 14 0xb007 0x200e0001
-
-ADC1/0 8 1/6 3 0xb008 0x20030001
-ADC1/1 9 1/7 2 0xb009 0x20020001
-ADC1/2 10 1/1 1 0xb00a 0x20010001
-ADC1/3 11 1/0 0 0xb00b 0x20000001
-ADC1/4 12 1/3 6 0xb00c 0x20060001
-ADC1/5 13 1/2 5 0xb00d 0x20050001
-ADC1/6 14 1/5 4 0xb00e 0x20040001
-ADC1/7 15 -/- -- 0xb00f 0x200f0001
-
-realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-mapAPV 12 11 10 9 8 7 13 14 3 2 1 0 6 5 4 -
-
-Backplane 2
-===========
-
-ADC0/0 0 -/- -- 0xb000 0x200f0001
-ADC0/1 1 0/7 4 0xb001 0x20040001
-ADC0/2 2 0/0 5 0xb002 0x20050001
-ADC0/3 3 0/2 6 0xb003 0x20060001
-ADC0/4 4 0/1 0 0xb004 0x20000001
-ADC0/5 5 0/3 1 0xb005 0x20010001
-ADC0/6 6 0/5 2 0xb006 0x20020001
-ADC0/7 7 0/4 3 0xb007 0x20030001
-
-ADC1/0 8 1/6 14 0xb008 0x200e0001
-ADC1/1 9 1/7 13 0xb009 0x200d0001
-ADC1/2 10 1/1 7 0xb00a 0x20070001
-ADC1/3 11 1/0 8 0xb00b 0x20080001
-ADC1/4 12 1/3 9 0xb00c 0x20090001
-ADC1/5 13 1/2 10 0xb00d 0x200a0001
-ADC1/6 14 1/5 11 0xb00e 0x200b0001
-ADC1/7 15 1/4 12 0xb00f 0x200c0001
-
-realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-mapAPV - 4 5 6 0 1 2 3 14 13 7 8 9 10 11 12
-
-Backplane 3
-===========
-
-ADC0/0 0 0/6 10 0xb000 0x200a0001
-ADC0/1 1 0/7 9 0xb001 0x20090001
-ADC0/2 2 0/0 8 0xb002 0x20080001
-ADC0/3 3 0/2 7 0xb003 0x20070001
-ADC0/4 4 0/1 6 0xb004 0x20060001
-ADC0/5 5 0/3 5 0xb005 0x20050001
-ADC0/6 6 0/5 12 0xb006 0x200c0001
-ADC0/7 7 0/4 11 0xb007 0x200b0001
-
-ADC1/0 8 1/6 4 0xb008 0x20040001
-ADC1/1 9 1/7 3 0xb009 0x20030001
-ADC1/2 10 1/1 0 0xb00a 0x20000001
-ADC1/3 11 1/0 2 0xb00b 0x20020001
-ADC1/4 12 1/3 1 0xb00c 0x20010001
-ADC1/5 13 -/- -- 0xb00d 0x200f0001
-ADC1/6 14 1/5 13 0xb00e 0x200d0001
-ADC1/7 15 1/4 14 0xb00f 0x200e0001
-
-realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-mapAPV 10 9 8 7 6 5 12 11 4 3 0 2 1 - 13 14
-
-Backplane 4
-===========
-
-ADC0/0 0 0/6 14 0xb000 0x200e0001
-ADC0/1 1 0/7 13 0xb001 0x200d0001
-ADC0/2 2 -/- -- 0xb002 0x200f0001
-ADC0/3 3 0/2 1 0xb003 0x20010001
-ADC0/4 4 0/1 2 0xb004 0x20020001
-ADC0/5 5 0/3 0 0xb005 0x20000001
-ADC0/6 6 0/5 3 0xb006 0x20030001
-ADC0/7 7 0/4 4 0xb007 0x20040001
-
-ADC1/0 8 1/6 11 0xb008 0x200b0001
-ADC1/1 9 1/7 12 0xb009 0x200c0001
-ADC1/2 10 1/1 5 0xb00a 0x20050001
-ADC1/3 11 1/0 6 0xb00b 0x20060001
-ADC1/4 12 1/3 7 0xb00c 0x20070001
-ADC1/5 13 1/2 8 0xb00d 0x20080001
-ADC1/6 14 1/5 9 0xb00e 0x20090001
-ADC1/7 15 1/4 10 0xb00f 0x200a0001
-
-realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-mapAPV 14 13 - 1 2 0 3 4 11 12 5 6 7 8 9 10
COMPONENT adc_data_handler\r
PORT(\r
RESET_IN : IN std_logic;\r
- RESET_PLL_IN : IN std_logic;\r
ADC_LCLK_IN : IN std_logic;\r
ADC_ADCLK_IN : IN std_logic;\r
ADC_CHNL_IN : IN std_logic_vector(7 downto 0);\r
PLL_CTRL_IN : IN std_logic_vector(3 downto 0); \r
- PLL_LOCK_OUT : OUT std_logic;\r
- CLK40M_OUT : OUT std_logic;\r
- ADC_ADCLK_OUT : OUT std_logic;\r
ADC_DATA7_OUT : OUT std_logic_vector(11 downto 0);\r
ADC_DATA6_OUT : OUT std_logic_vector(11 downto 0);\r
ADC_DATA5_OUT : OUT std_logic_vector(11 downto 0);\r
ADC_DATA2_OUT : OUT std_logic_vector(11 downto 0);\r
ADC_DATA1_OUT : OUT std_logic_vector(11 downto 0);\r
ADC_DATA0_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_CE_OUT : OUT std_logic;\r
+ ADC_VALID_OUT : OUT std_logic;\r
DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
);\r
END COMPONENT;\r
\r
SIGNAL RESET_IN : std_logic;\r
- SIGNAL RESET_PLL_IN : std_logic;\r
SIGNAL ADC_LCLK_IN : std_logic;\r
SIGNAL ADC_ADCLK_IN : std_logic;\r
SIGNAL ADC_CHNL_IN : std_logic_vector(7 downto 0);\r
SIGNAL PLL_CTRL_IN : std_logic_vector(3 downto 0);\r
- SIGNAL PLL_LOCK_OUT : std_logic;\r
- SIGNAL CLK40M_OUT : std_logic;\r
- SIGNAL ADC_ADCLK_OUT : std_logic;\r
SIGNAL ADC_DATA7_OUT : std_logic_vector(11 downto 0);\r
SIGNAL ADC_DATA6_OUT : std_logic_vector(11 downto 0);\r
SIGNAL ADC_DATA5_OUT : std_logic_vector(11 downto 0);\r
SIGNAL ADC_DATA2_OUT : std_logic_vector(11 downto 0);\r
SIGNAL ADC_DATA1_OUT : std_logic_vector(11 downto 0);\r
SIGNAL ADC_DATA0_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_CE_OUT : std_logic;\r
+ SIGNAL ADC_VALID_OUT : std_logic;\r
SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
\r
signal adc_0_real : std_logic_vector(11 downto 0);\r
-- Please check and add your generic clause manually\r
uut: adc_data_handler PORT MAP(\r
RESET_IN => RESET_IN,\r
- RESET_PLL_IN => RESET_PLL_IN,\r
ADC_LCLK_IN => ADC_LCLK_IN,\r
ADC_ADCLK_IN => ADC_ADCLK_IN,\r
ADC_CHNL_IN => ADC_CHNL_IN,\r
PLL_CTRL_IN => PLL_CTRL_IN,\r
- PLL_LOCK_OUT => PLL_LOCK_OUT,\r
- CLK40M_OUT => CLK40M_OUT,\r
- ADC_ADCLK_OUT => ADC_ADCLK_OUT,\r
ADC_DATA7_OUT => ADC_DATA7_OUT,\r
ADC_DATA6_OUT => ADC_DATA6_OUT,\r
ADC_DATA5_OUT => ADC_DATA5_OUT,\r
ADC_DATA2_OUT => ADC_DATA2_OUT,\r
ADC_DATA1_OUT => ADC_DATA1_OUT,\r
ADC_DATA0_OUT => ADC_DATA0_OUT,\r
+ ADC_CE_OUT => ADC_CE_OUT,\r
+ ADC_VALID_OUT => ADC_VALID_OUT,\r
DEBUG_OUT => DEBUG_OUT\r
);\r
\r
begin\r
-- Setup signals\r
reset_in <= '0';\r
- reset_pll_in <= '0';\r
pll_ctrl_in <= x"6";\r
wait for 100 ns;\r
\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT apv_pc_nc_alu\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ START_IN : IN std_logic;\r
+ MAX_FRAMES_IN : IN std_logic_vector(3 downto 0);\r
+ CURR_FRAME_IN : IN std_logic_vector(3 downto 0);\r
+ LOC_FRM_CTR_IN : IN std_logic_vector(3 downto 0);\r
+ EDS_FRM_CTR_IN : IN std_logic_vector(3 downto 0);\r
+ BUF_GOOD_IN : IN std_logic;\r
+ BUF_BAD_IN : IN std_logic;\r
+ BUF_IGNORE_IN : IN std_logic;\r
+ ERROR_IN : IN std_logic_vector(3 downto 0);\r
+ DO_HEADER_IN : IN std_logic;\r
+ DO_ERROR_IN : IN std_logic;\r
+ SUPPRESS_IN : IN std_logic;\r
+ EVT_TYPE_IN : IN std_logic_vector(2 downto 0);\r
+ RAW_ADDR_IN : IN std_logic_vector(6 downto 0);\r
+ RAW_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ PED_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ FRAME_IN : IN std_logic; \r
+ FIFO_DATA_OUT : OUT std_logic_vector(26 downto 0);\r
+ WE_OUT : OUT std_logic;\r
+ COUNT_OUT : OUT std_logic_vector(9 downto 0);\r
+ ANYDATA_OUT : OUT std_logic;\r
+ DBG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL START_IN : std_logic;\r
+ SIGNAL MAX_FRAMES_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL CURR_FRAME_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL LOC_FRM_CTR_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL EDS_FRM_CTR_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL BUF_GOOD_IN : std_logic;\r
+ SIGNAL BUF_BAD_IN : std_logic;\r
+ SIGNAL BUF_IGNORE_IN : std_logic;\r
+ SIGNAL ERROR_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL DO_HEADER_IN : std_logic;\r
+ SIGNAL DO_ERROR_IN : std_logic;\r
+ SIGNAL SUPPRESS_IN : std_logic;\r
+ SIGNAL EVT_TYPE_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL RAW_ADDR_IN : std_logic_vector(6 downto 0);\r
+ SIGNAL RAW_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL PED_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL FRAME_IN : std_logic;\r
+ SIGNAL FIFO_DATA_OUT : std_logic_vector(26 downto 0);\r
+ SIGNAL WE_OUT : std_logic;\r
+ SIGNAL COUNT_OUT : std_logic_vector(9 downto 0);\r
+ SIGNAL ANYDATA_OUT : std_logic;\r
+ SIGNAL DBG_OUT : std_logic_vector(15 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: apv_pc_nc_alu PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ START_IN => START_IN,\r
+ MAX_FRAMES_IN => MAX_FRAMES_IN,\r
+ CURR_FRAME_IN => CURR_FRAME_IN,\r
+ LOC_FRM_CTR_IN => LOC_FRM_CTR_IN,\r
+ EDS_FRM_CTR_IN => EDS_FRM_CTR_IN,\r
+ BUF_GOOD_IN => BUF_GOOD_IN,\r
+ BUF_BAD_IN => BUF_BAD_IN,\r
+ BUF_IGNORE_IN => BUF_IGNORE_IN,\r
+ ERROR_IN => ERROR_IN,\r
+ DO_HEADER_IN => DO_HEADER_IN,\r
+ DO_ERROR_IN => DO_ERROR_IN,\r
+ SUPPRESS_IN => SUPPRESS_IN,\r
+ EVT_TYPE_IN => EVT_TYPE_IN,\r
+ RAW_ADDR_IN => RAW_ADDR_IN,\r
+ RAW_DATA_IN => RAW_DATA_IN,\r
+ PED_DATA_IN => PED_DATA_IN,\r
+ THR_DATA_IN => THR_DATA_IN,\r
+ FRAME_IN => FRAME_IN,\r
+ FIFO_DATA_OUT => FIFO_DATA_OUT,\r
+ WE_OUT => WE_OUT,\r
+ COUNT_OUT => COUNT_OUT,\r
+ ANYDATA_OUT => ANYDATA_OUT,\r
+ DBG_OUT => DBG_OUT\r
+ );\r
+\r
+CLOCK_GEN_PROC: process\r
+begin\r
+ clk_in <= '1'; wait for 5.0 ns;\r
+ clk_in <= '0'; wait for 5.0 ns;\r
+end process CLOCK_GEN_PROC;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ start_in <= '0';\r
+ max_frames_in <= x"0";\r
+ curr_frame_in <= x"0";\r
+ loc_frm_ctr_in <= x"0";\r
+ eds_frm_ctr_in <= x"0";\r
+ buf_good_in <= '0';\r
+ buf_bad_in <= '0';\r
+ buf_ignore_in <= '0';\r
+ error_in <= x"0";\r
+ do_header_in <= '0';\r
+ do_error_in <= '0';\r
+ suppress_in <= '0';\r
+ evt_type_in <= b"000";\r
+ raw_addr_in <= b"000_0000";\r
+ raw_data_in <= b"00_0000_0000_0000_0000_0000_0000_0000_0000_0000"; \r
+ ped_data_in <= b"00_0000_0000_0000_0000";\r
+ thr_data_in <= b"00_0000_0000_0000_0000";\r
+ frame_in <= '0';\r
+ wait for 100 ns;\r
+ \r
+ -- Reset the whole stuff\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ \r
+ -- Tests may start now\r
+ \r
+ -- Stay a while... stay forever!!! Muahahahah!!!!\r
+ wait;\r
+end process THE_TEST_BENCH;\r
+\r
+END;\r
TIME_TRG_IN : IN std_logic_vector(3 downto 0);\r
TRB_TRG_IN : IN std_logic_vector(3 downto 0);\r
STILL_BUSY_IN : IN std_logic;\r
+ SECTOR_IN : IN std_logic_vector(2 downto 0);\r
TRG_3_TODO_IN : IN std_logic_vector(3 downto 0);\r
TRG_3_DELAY_IN : IN std_logic_vector(3 downto 0);\r
TRG_2_TODO_IN : IN std_logic_vector(3 downto 0);\r
SIGNAL TRB_TRG_IN : std_logic_vector(3 downto 0);\r
SIGNAL STILL_BUSY_IN : std_logic;\r
SIGNAL TRG_FOUND_OUT : std_logic;\r
+ SIGNAL SECTOR_IN : std_logic_vector(2 downto 0);\r
SIGNAL TRG_3_TODO_IN : std_logic_vector(3 downto 0);\r
SIGNAL TRG_3_DELAY_IN : std_logic_vector(3 downto 0);\r
SIGNAL TRG_2_TODO_IN : std_logic_vector(3 downto 0);\r
TIME_TRG_IN => TIME_TRG_IN,\r
TRB_TRG_IN => TRB_TRG_IN,\r
STILL_BUSY_IN => STILL_BUSY_IN,\r
+ SECTOR_IN => SECTOR_IN,\r
TRG_FOUND_OUT => TRG_FOUND_OUT,\r
TRG_3_TODO_IN => TRG_3_TODO_IN,\r
TRG_3_DELAY_IN => TRG_3_DELAY_IN,\r
time_trg_in <= x"0";\r
trb_trg_in <= x"0";\r
still_busy_in <= '0';\r
+ sector_in <= b"101";\r
trg_3_todo_in <= x"1";\r
trg_3_delay_in <= x"0";\r
trg_2_todo_in <= x"1";\r
-- send TRB trigger infos\r
wait for 2.3 us;\r
wait until rising_edge(clk_in);\r
- trb_ttype_in <= x"3";\r
+ trb_ttype_in <= x"e";\r
trb_ttag_in <= x"deaf";\r
trb_trnd_in <= x"7c";\r
- trb_tinfo_in <= x"00_05_00"; -- data format = b"101"\r
+ trb_tinfo_in <= x"00_05_01"; -- data format = b"101"\r
wait until rising_edge(clk_in);\r
trb_trgrcvd_in <= '1';\r
\r
-- send TRB trigger infos\r
wait for 2.3 us;\r
wait until rising_edge(clk_in);\r
- trb_ttype_in <= x"9";\r
+ trb_ttype_in <= x"e";\r
trb_ttag_in <= x"deb0";\r
trb_trnd_in <= x"19";\r
trb_tinfo_in <= x"00_00_80"; -- timingtriggerless trigger\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT apv_trgctrl\r
+ PORT(\r
+ CLK_APV_IN : IN std_logic;\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ SYNC_TRG_IN : IN std_logic;\r
+ TIME_TRG_IN : IN std_logic_vector(3 downto 0);\r
+ TRB_TRG_IN : IN std_logic_vector(3 downto 0);\r
+ STILL_BUSY_IN : IN std_logic;\r
+ SECTOR_IN : IN std_logic_vector(2 downto 0);\r
+ TRG_3_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_3_DELAY_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_2_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_2_DELAY_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_1_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_1_DELAY_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_0_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_0_DELAY_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_SETUP_IN : IN std_logic_vector(7 downto 0);\r
+ TRB_TTAG_IN : IN std_logic_vector(15 downto 0);\r
+ TRB_TRND_IN : IN std_logic_vector(7 downto 0);\r
+ TRB_TTYPE_IN : IN std_logic_vector(3 downto 0);\r
+ TRB_TINFO_IN : IN std_logic_vector(23 downto 0);\r
+ TRB_TRGRCVD_IN : IN std_logic;\r
+ TRB_COUNTER_IN : IN std_logic_vector(15 downto 0);\r
+ TRB_LD_COUNTER_IN : IN std_logic;\r
+ EDS_DONE_IN : IN std_logic; \r
+ TRG_FOUND_OUT : OUT std_logic;\r
+ TRB_MISSING_OUT : OUT std_logic;\r
+ TRB_RELEASE_OUT : OUT std_logic;\r
+ TRB_COUNTER_OUT : OUT std_logic_vector(15 downto 0);\r
+ EDS_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ EDS_AVAIL_OUT : OUT std_logic;\r
+ EDS_FULL_OUT : OUT std_logic;\r
+ EDS_LEVEL_OUT : OUT std_logic_vector(4 downto 0);\r
+ FRM_REQD_OUT : OUT std_logic;\r
+ APV_TRG_OUT : OUT std_logic;\r
+ APV_SYNC_OUT : OUT std_logic;\r
+ DEBUG_OUT : OUT std_logic_vector(63 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_APV_IN : std_logic;\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL SYNC_TRG_IN : std_logic;\r
+ SIGNAL TIME_TRG_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRB_TRG_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL STILL_BUSY_IN : std_logic;\r
+ SIGNAL TRG_FOUND_OUT : std_logic;\r
+ SIGNAL SECTOR_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL TRG_3_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_3_DELAY_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_2_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_2_DELAY_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_1_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_1_DELAY_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_0_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_0_DELAY_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_SETUP_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL TRB_TTAG_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL TRB_TRND_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL TRB_TTYPE_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRB_TINFO_IN : std_logic_vector(23 downto 0);\r
+ SIGNAL TRB_TRGRCVD_IN : std_logic;\r
+ SIGNAL TRB_MISSING_OUT : std_logic;\r
+ SIGNAL TRB_RELEASE_OUT : std_logic;\r
+ SIGNAL TRB_COUNTER_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL TRB_LD_COUNTER_IN : std_logic;\r
+ SIGNAL TRB_COUNTER_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL EDS_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL EDS_AVAIL_OUT : std_logic;\r
+ SIGNAL EDS_DONE_IN : std_logic;\r
+ SIGNAL EDS_FULL_OUT : std_logic;\r
+ SIGNAL EDS_LEVEL_OUT : std_logic_vector(4 downto 0);\r
+ SIGNAL FRM_REQD_OUT : std_logic;\r
+ SIGNAL APV_TRG_OUT : std_logic;\r
+ SIGNAL APV_SYNC_OUT : std_logic;\r
+ SIGNAL DEBUG_OUT : std_logic_vector(63 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: apv_trgctrl PORT MAP(\r
+ CLK_APV_IN => CLK_APV_IN,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ SYNC_TRG_IN => SYNC_TRG_IN,\r
+ TIME_TRG_IN => TIME_TRG_IN,\r
+ TRB_TRG_IN => TRB_TRG_IN,\r
+ STILL_BUSY_IN => STILL_BUSY_IN,\r
+ SECTOR_IN => SECTOR_IN,\r
+ TRG_FOUND_OUT => TRG_FOUND_OUT,\r
+ TRG_3_TODO_IN => TRG_3_TODO_IN,\r
+ TRG_3_DELAY_IN => TRG_3_DELAY_IN,\r
+ TRG_2_TODO_IN => TRG_2_TODO_IN,\r
+ TRG_2_DELAY_IN => TRG_2_DELAY_IN,\r
+ TRG_1_TODO_IN => TRG_1_TODO_IN,\r
+ TRG_1_DELAY_IN => TRG_1_DELAY_IN,\r
+ TRG_0_TODO_IN => TRG_0_TODO_IN,\r
+ TRG_0_DELAY_IN => TRG_0_DELAY_IN,\r
+ TRG_SETUP_IN => TRG_SETUP_IN,\r
+ TRB_TTAG_IN => TRB_TTAG_IN,\r
+ TRB_TRND_IN => TRB_TRND_IN,\r
+ TRB_TTYPE_IN => TRB_TTYPE_IN,\r
+ TRB_TINFO_IN => TRB_TINFO_IN,\r
+ TRB_TRGRCVD_IN => TRB_TRGRCVD_IN,\r
+ TRB_MISSING_OUT => TRB_MISSING_OUT,\r
+ TRB_RELEASE_OUT => TRB_RELEASE_OUT,\r
+ TRB_COUNTER_IN => TRB_COUNTER_IN,\r
+ TRB_LD_COUNTER_IN => TRB_LD_COUNTER_IN,\r
+ TRB_COUNTER_OUT => TRB_COUNTER_OUT,\r
+ EDS_DATA_OUT => EDS_DATA_OUT,\r
+ EDS_AVAIL_OUT => EDS_AVAIL_OUT,\r
+ EDS_DONE_IN => EDS_DONE_IN,\r
+ EDS_FULL_OUT => EDS_FULL_OUT,\r
+ EDS_LEVEL_OUT => EDS_LEVEL_OUT,\r
+ FRM_REQD_OUT => FRM_REQD_OUT,\r
+ APV_TRG_OUT => APV_TRG_OUT,\r
+ APV_SYNC_OUT => APV_SYNC_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+-- Generate the clock\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '0'; wait for 5 ns;\r
+ clk_in <= '1'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_APV_CLOCK_GEN: process\r
+begin\r
+ clk_apv_in <= '0'; wait for 12.5 ns;\r
+ clk_apv_in <= '1'; wait for 12.5 ns;\r
+end process THE_APV_CLOCK_GEN;\r
+\r
+-- The real testbench\r
+THE_TESTBENCH_PROC: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ sync_trg_in <= '0';\r
+ time_trg_in <= x"0";\r
+ trb_trg_in <= x"0";\r
+ still_busy_in <= '0';\r
+ sector_in <= b"101";\r
+ trg_3_todo_in <= x"1";\r
+ trg_3_delay_in <= x"0";\r
+ trg_2_todo_in <= x"1";\r
+ trg_2_delay_in <= x"0";\r
+ trg_1_todo_in <= x"1";\r
+ trg_1_delay_in <= x"0";\r
+ trg_0_todo_in <= x"1";\r
+ trg_0_delay_in <= x"0";\r
+ trg_setup_in <= x"10"; -- TRG0 is active, non-inverted\r
+ trb_ttag_in <= x"0000";\r
+ trb_trnd_in <= x"00";\r
+ trb_ttype_in <= x"0";\r
+ trb_tinfo_in <= x"00_00_00";\r
+ trb_trgrcvd_in <= '0';\r
+ trb_counter_in <= x"dead";\r
+ trb_ld_counter_in <= '0';\r
+ eds_done_in <= '0';\r
+ \r
+ wait for 20 ns;\r
+ \r
+ -- Do a reset\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ wait for 100 ns;\r
+ \r
+ -- test may start here\r
+ \r
+ wait until rising_edge(clk_in);\r
+ sync_trg_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ sync_trg_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1 us;\r
+\r
+ -- Set local LVL1 counter to TRBnet value\r
+ wait until rising_edge(clk_in);\r
+ trb_ld_counter_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ trb_ld_counter_in <= '0';\r
+ \r
+ -- first trigger\r
+ -- send in one timing trigger\r
+ wait for 77.7 ns;\r
+ time_trg_in <= x"1"; \r
+ wait for 222.2 ns;\r
+ time_trg_in <= x"0";\r
+ \r
+ -- send TRB trigger infos\r
+ wait for 2.3 us;\r
+ wait until rising_edge(clk_in);\r
+ trb_ttype_in <= x"1";\r
+ trb_ttag_in <= x"dead";\r
+ trb_trnd_in <= x"a0";\r
+ trb_tinfo_in <= x"00_00_00"; -- data format = b"000"\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+\r
+ -- release trigger\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(trb_release_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1.22 us;\r
+\r
+ -- next trigger\r
+ -- send in one timing trigger\r
+ wait for 77.7 ns;\r
+ time_trg_in <= x"1"; \r
+ wait for 222.2 ns;\r
+ time_trg_in <= x"0";\r
+ \r
+ -- send TRB trigger infos\r
+ wait for 2.3 us;\r
+ wait until rising_edge(clk_in);\r
+ trb_ttype_in <= x"2";\r
+ trb_ttag_in <= x"deae";\r
+ trb_trnd_in <= x"42";\r
+ trb_tinfo_in <= x"00_01_00"; -- data format = b"001"\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+\r
+ -- release trigger\r
+ wait until rising_edge(trb_release_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1.11 us;\r
+\r
+ -- next trigger (missing timing trigger)\r
+ -- send TRB trigger infos\r
+ wait for 2.3 us;\r
+ wait until rising_edge(clk_in);\r
+ trb_ttype_in <= x"e";\r
+ trb_ttag_in <= x"deaf";\r
+ trb_trnd_in <= x"7c";\r
+ trb_tinfo_in <= x"00_05_01"; -- data format = b"101"\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+\r
+ -- release trigger\r
+ wait until rising_edge(trb_release_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1.51 us;\r
+\r
+ -- next trigger (timingtriggerless trigger)\r
+ -- send TRB trigger infos\r
+ wait for 2.3 us;\r
+ wait until rising_edge(clk_in);\r
+ trb_ttype_in <= x"9";\r
+ trb_ttag_in <= x"deb0";\r
+ trb_trnd_in <= x"19";\r
+ trb_tinfo_in <= x"00_00_80"; -- timingtriggerless trigger\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+\r
+ -- release trigger\r
+ wait until rising_edge(trb_release_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1.21 us;\r
+\r
+ -- next trigger\r
+ -- send in one timing trigger\r
+ wait for 77.7 ns;\r
+ time_trg_in <= x"1"; \r
+ wait for 222.2 ns;\r
+ time_trg_in <= x"0";\r
+ \r
+ -- send TRB trigger infos\r
+ wait for 2.3 us;\r
+ wait until rising_edge(clk_in);\r
+ trb_ttype_in <= x"4";\r
+ trb_ttag_in <= x"deb1";\r
+ trb_trnd_in <= x"97";\r
+ trb_tinfo_in <= x"00_00_01"; -- data format = b"000", suppress data\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+\r
+ -- release trigger\r
+ wait until rising_edge(trb_release_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1.11 us;\r
+ \r
+ -- release one EDS\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- release one EDS\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- release one EDS\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- release one EDS\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- release one EDS\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ \r
+ -- Stay a while, stay forever.... wuhahahahaha\r
+ wait;\r
+end process THE_TESTBENCH_PROC;\r
+\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT apv_trgctrl\r
+ PORT(\r
+ CLK_APV_IN : IN std_logic;\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ SYNC_TRG_IN : IN std_logic;\r
+ TIME_TRG_IN : IN std_logic_vector(3 downto 0);\r
+ TRB_TRG_IN : IN std_logic_vector(3 downto 0);\r
+ STILL_BUSY_IN : IN std_logic;\r
+ SECTOR_IN : IN std_logic_vector(2 downto 0);\r
+ TRG_3_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_3_DELAY_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_2_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_2_DELAY_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_1_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_1_DELAY_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_0_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_0_DELAY_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_SETUP_IN : IN std_logic_vector(7 downto 0);\r
+ TRB_TTAG_IN : IN std_logic_vector(15 downto 0);\r
+ TRB_TRND_IN : IN std_logic_vector(7 downto 0);\r
+ TRB_TTYPE_IN : IN std_logic_vector(3 downto 0);\r
+ TRB_TINFO_IN : IN std_logic_vector(23 downto 0);\r
+ TRB_TRGRCVD_IN : IN std_logic;\r
+ TRB_COUNTER_IN : IN std_logic_vector(15 downto 0);\r
+ TRB_LD_COUNTER_IN : IN std_logic;\r
+ EDS_DONE_IN : IN std_logic; \r
+ TRG_FOUND_OUT : OUT std_logic;\r
+ TRB_MISSING_OUT : OUT std_logic;\r
+ TRB_RELEASE_OUT : OUT std_logic;\r
+ TRB_COUNTER_OUT : OUT std_logic_vector(15 downto 0);\r
+ EDS_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ EDS_AVAIL_OUT : OUT std_logic;\r
+ EDS_FULL_OUT : OUT std_logic;\r
+ EDS_LEVEL_OUT : OUT std_logic_vector(4 downto 0);\r
+ FRM_REQD_OUT : OUT std_logic;\r
+ APV_TRG_OUT : OUT std_logic;\r
+ APV_SYNC_OUT : OUT std_logic;\r
+ DEBUG_OUT : OUT std_logic_vector(63 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_APV_IN : std_logic;\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL SYNC_TRG_IN : std_logic;\r
+ SIGNAL TIME_TRG_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRB_TRG_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL STILL_BUSY_IN : std_logic;\r
+ SIGNAL TRG_FOUND_OUT : std_logic;\r
+ SIGNAL SECTOR_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL TRG_3_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_3_DELAY_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_2_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_2_DELAY_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_1_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_1_DELAY_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_0_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_0_DELAY_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_SETUP_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL TRB_TTAG_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL TRB_TRND_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL TRB_TTYPE_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRB_TINFO_IN : std_logic_vector(23 downto 0);\r
+ SIGNAL TRB_TRGRCVD_IN : std_logic;\r
+ SIGNAL TRB_MISSING_OUT : std_logic;\r
+ SIGNAL TRB_RELEASE_OUT : std_logic;\r
+ SIGNAL TRB_COUNTER_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL TRB_LD_COUNTER_IN : std_logic;\r
+ SIGNAL TRB_COUNTER_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL EDS_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL EDS_AVAIL_OUT : std_logic;\r
+ SIGNAL EDS_DONE_IN : std_logic;\r
+ SIGNAL EDS_FULL_OUT : std_logic;\r
+ SIGNAL EDS_LEVEL_OUT : std_logic_vector(4 downto 0);\r
+ SIGNAL FRM_REQD_OUT : std_logic;\r
+ SIGNAL APV_TRG_OUT : std_logic;\r
+ SIGNAL APV_SYNC_OUT : std_logic;\r
+ SIGNAL DEBUG_OUT : std_logic_vector(63 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: apv_trgctrl PORT MAP(\r
+ CLK_APV_IN => CLK_APV_IN,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ SYNC_TRG_IN => SYNC_TRG_IN,\r
+ TIME_TRG_IN => TIME_TRG_IN,\r
+ TRB_TRG_IN => TRB_TRG_IN,\r
+ STILL_BUSY_IN => STILL_BUSY_IN,\r
+ SECTOR_IN => SECTOR_IN,\r
+ TRG_FOUND_OUT => TRG_FOUND_OUT,\r
+ TRG_3_TODO_IN => TRG_3_TODO_IN,\r
+ TRG_3_DELAY_IN => TRG_3_DELAY_IN,\r
+ TRG_2_TODO_IN => TRG_2_TODO_IN,\r
+ TRG_2_DELAY_IN => TRG_2_DELAY_IN,\r
+ TRG_1_TODO_IN => TRG_1_TODO_IN,\r
+ TRG_1_DELAY_IN => TRG_1_DELAY_IN,\r
+ TRG_0_TODO_IN => TRG_0_TODO_IN,\r
+ TRG_0_DELAY_IN => TRG_0_DELAY_IN,\r
+ TRG_SETUP_IN => TRG_SETUP_IN,\r
+ TRB_TTAG_IN => TRB_TTAG_IN,\r
+ TRB_TRND_IN => TRB_TRND_IN,\r
+ TRB_TTYPE_IN => TRB_TTYPE_IN,\r
+ TRB_TINFO_IN => TRB_TINFO_IN,\r
+ TRB_TRGRCVD_IN => TRB_TRGRCVD_IN,\r
+ TRB_MISSING_OUT => TRB_MISSING_OUT,\r
+ TRB_RELEASE_OUT => TRB_RELEASE_OUT,\r
+ TRB_COUNTER_IN => TRB_COUNTER_IN,\r
+ TRB_LD_COUNTER_IN => TRB_LD_COUNTER_IN,\r
+ TRB_COUNTER_OUT => TRB_COUNTER_OUT,\r
+ EDS_DATA_OUT => EDS_DATA_OUT,\r
+ EDS_AVAIL_OUT => EDS_AVAIL_OUT,\r
+ EDS_DONE_IN => EDS_DONE_IN,\r
+ EDS_FULL_OUT => EDS_FULL_OUT,\r
+ EDS_LEVEL_OUT => EDS_LEVEL_OUT,\r
+ FRM_REQD_OUT => FRM_REQD_OUT,\r
+ APV_TRG_OUT => APV_TRG_OUT,\r
+ APV_SYNC_OUT => APV_SYNC_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+-- Generate the clock\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '0'; wait for 5 ns;\r
+ clk_in <= '1'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_APV_CLOCK_GEN: process\r
+begin\r
+ clk_apv_in <= '0'; wait for 12.5 ns;\r
+ clk_apv_in <= '1'; wait for 12.5 ns;\r
+end process THE_APV_CLOCK_GEN;\r
+\r
+-- The real testbench\r
+THE_TESTBENCH_PROC: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ sync_trg_in <= '0';\r
+ time_trg_in <= x"0";\r
+ trb_trg_in <= x"0";\r
+ still_busy_in <= '0';\r
+ sector_in <= b"101";\r
+ trg_3_todo_in <= x"1";\r
+ trg_3_delay_in <= x"0";\r
+ trg_2_todo_in <= x"1";\r
+ trg_2_delay_in <= x"0";\r
+ trg_1_todo_in <= x"1";\r
+ trg_1_delay_in <= x"0";\r
+ trg_0_todo_in <= x"1";\r
+ trg_0_delay_in <= x"0";\r
+ trg_setup_in <= x"10"; -- TRG0 is active, non-inverted\r
+ trb_ttag_in <= x"0000";\r
+ trb_trnd_in <= x"00";\r
+ trb_ttype_in <= x"0";\r
+ trb_tinfo_in <= x"00_00_00";\r
+ trb_trgrcvd_in <= '0';\r
+ trb_counter_in <= x"dead";\r
+ trb_ld_counter_in <= '0';\r
+ eds_done_in <= '0';\r
+ \r
+ wait for 20 ns;\r
+ \r
+ -- Do a reset\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ wait for 100 ns;\r
+ \r
+ -- test may start here\r
+ \r
+ wait until rising_edge(clk_in);\r
+ sync_trg_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ sync_trg_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1 us;\r
+\r
+ -- Set local LVL1 counter to TRBnet value\r
+ wait until rising_edge(clk_in);\r
+ trb_ld_counter_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ trb_ld_counter_in <= '0';\r
+ \r
+ -- first trigger\r
+ -- send in one timing trigger\r
+ wait for 77.7 ns;\r
+ time_trg_in <= x"1"; \r
+ wait for 222.2 ns;\r
+ time_trg_in <= x"0";\r
+ \r
+ -- send TRB trigger infos\r
+ wait for 2.3 us;\r
+ wait until rising_edge(clk_in);\r
+ trb_ttype_in <= x"1";\r
+ trb_ttag_in <= x"dead";\r
+ trb_trnd_in <= x"a0";\r
+ trb_tinfo_in <= x"00_00_00"; -- data format = b"000"\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+\r
+ -- release trigger\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(trb_release_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1.22 us;\r
+\r
+ -- next trigger\r
+ -- send in one timing trigger\r
+ wait for 77.7 ns;\r
+ time_trg_in <= x"1"; \r
+ wait for 222.2 ns;\r
+ time_trg_in <= x"0";\r
+ \r
+ -- send TRB trigger infos\r
+ wait for 2.3 us;\r
+ wait until rising_edge(clk_in);\r
+ trb_ttype_in <= x"2";\r
+ trb_ttag_in <= x"deae";\r
+ trb_trnd_in <= x"42";\r
+ trb_tinfo_in <= x"00_01_00"; -- data format = b"001"\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+\r
+ -- release trigger\r
+ wait until rising_edge(trb_release_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1.11 us;\r
+\r
+ -- next trigger (missing timing trigger)\r
+ -- send TRB trigger infos\r
+ wait for 2.3 us;\r
+ wait until rising_edge(clk_in);\r
+ trb_ttype_in <= x"3";\r
+ trb_ttag_in <= x"deaf";\r
+ trb_trnd_in <= x"7c";\r
+ trb_tinfo_in <= x"00_05_00"; -- data format = b"101"\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+\r
+ -- release trigger\r
+ wait until rising_edge(trb_release_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1.51 us;\r
+\r
+ -- next trigger (timingtriggerless trigger)\r
+ -- send TRB trigger infos\r
+ wait for 2.3 us;\r
+ wait until rising_edge(clk_in);\r
+ trb_ttype_in <= x"9";\r
+ trb_ttag_in <= x"deb0";\r
+ trb_trnd_in <= x"19";\r
+ trb_tinfo_in <= x"00_00_80"; -- timingtriggerless trigger\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+\r
+ -- release trigger\r
+ wait until rising_edge(trb_release_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1.21 us;\r
+\r
+ -- next trigger\r
+ -- send in one timing trigger\r
+ wait for 77.7 ns;\r
+ time_trg_in <= x"1"; \r
+ wait for 222.2 ns;\r
+ time_trg_in <= x"0";\r
+ \r
+ -- send TRB trigger infos\r
+ wait for 2.3 us;\r
+ wait until rising_edge(clk_in);\r
+ trb_ttype_in <= x"4";\r
+ trb_ttag_in <= x"deb1";\r
+ trb_trnd_in <= x"97";\r
+ trb_tinfo_in <= x"00_00_01"; -- data format = b"000", suppress data\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+\r
+ -- release trigger\r
+ wait until rising_edge(trb_release_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1.11 us;\r
+ \r
+ -- release one EDS\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- release one EDS\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- release one EDS\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- release one EDS\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- release one EDS\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ \r
+ -- Stay a while, stay forever.... wuhahahahaha\r
+ wait;\r
+end process THE_TESTBENCH_PROC;\r
+\r
+\r
+END;\r
IPU_READOUT_FINISHED_OUT : OUT std_logic;\r
IPU_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
IPU_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);\r
+ IPU_LAST_NUM_OUT : OUT std_logic_vector(31 downto 0);\r
LVL2_COUNTER_OUT : OUT std_logic_vector(15 downto 0);\r
DHDR_BUF_FULL_OUT : OUT std_logic;\r
DBG_BSM_OUT : OUT std_logic_vector(7 downto 0);\r
SIGNAL IPU_READ_IN : std_logic;\r
SIGNAL IPU_LENGTH_OUT : std_logic_vector(15 downto 0);\r
SIGNAL IPU_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL IPU_LAST_NUM_OUT : std_logic_vector(31 downto 0);\r
SIGNAL LVL2_COUNTER_OUT : std_logic_vector(15 downto 0);\r
SIGNAL DHDR_DATA_IN : std_logic_vector(31 downto 0);\r
SIGNAL DHDR_LENGTH_IN : std_logic_vector(15 downto 0);\r
IPU_READ_IN => IPU_READ_IN,\r
IPU_LENGTH_OUT => IPU_LENGTH_OUT,\r
IPU_ERROR_PATTERN_OUT => IPU_ERROR_PATTERN_OUT,\r
+ IPU_LAST_NUM_OUT => IPU_LAST_NUM_OUT,\r
LVL2_COUNTER_OUT => LVL2_COUNTER_OUT,\r
DHDR_DATA_IN => DHDR_DATA_IN,\r
DHDR_LENGTH_IN => DHDR_LENGTH_IN,\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT ipu_fifo_stage\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ SECTOR_IN : IN std_logic_vector(2 downto 0);\r
+ MODULE_IN : IN std_logic_vector(2 downto 0);\r
+ IPU_NUMBER_IN : IN std_logic_vector(15 downto 0);\r
+ IPU_INFORMATION_IN : IN std_logic_vector(7 downto 0);\r
+ IPU_START_READOUT_IN : IN std_logic;\r
+ IPU_READ_IN : IN std_logic;\r
+ DHDR_DATA_IN : IN std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_IN : IN std_logic_vector(15 downto 0);\r
+ DHDR_STORE_IN : IN std_logic;\r
+ FIFO_START_IN : IN std_logic;\r
+ FIFO_SPACE_REQ_IN : IN std_logic_vector(11 downto 0);\r
+ FIFO_0_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_WE_IN : IN std_logic_vector(15 downto 0);\r
+ FIFO_DONE_IN : IN std_logic; \r
+ IPU_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
+ IPU_DATAREADY_OUT : OUT std_logic;\r
+ IPU_READOUT_FINISHED_OUT : OUT std_logic;\r
+ IPU_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
+ IPU_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);\r
+ IPU_LAST_NUM_OUT : OUT std_logic_vector(31 downto 0);\r
+ LVL2_COUNTER_OUT : OUT std_logic_vector(15 downto 0);\r
+ DHDR_BUF_FULL_OUT : OUT std_logic;\r
+ DBG_BSM_OUT : OUT std_logic_vector(7 downto 0);\r
+ DBG_OUT : OUT std_logic_vector(63 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL SECTOR_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL MODULE_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL IPU_NUMBER_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL IPU_INFORMATION_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL IPU_START_READOUT_IN : std_logic;\r
+ SIGNAL IPU_DATA_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL IPU_DATAREADY_OUT : std_logic;\r
+ SIGNAL IPU_READOUT_FINISHED_OUT : std_logic;\r
+ SIGNAL IPU_READ_IN : std_logic;\r
+ SIGNAL IPU_LENGTH_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL IPU_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL IPU_LAST_NUM_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL LVL2_COUNTER_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL DHDR_DATA_IN : std_logic_vector(31 downto 0);\r
+ SIGNAL DHDR_LENGTH_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL DHDR_STORE_IN : std_logic;\r
+ SIGNAL DHDR_BUF_FULL_OUT : std_logic;\r
+ SIGNAL FIFO_START_IN : std_logic;\r
+ SIGNAL FIFO_SPACE_REQ_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL FIFO_0_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_1_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_2_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_3_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_4_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_5_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_6_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_7_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_8_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_9_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_10_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_11_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_12_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_13_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_14_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_15_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_WE_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL FIFO_DONE_IN : std_logic;\r
+ SIGNAL DBG_BSM_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL DBG_OUT : std_logic_vector(63 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: ipu_fifo_stage PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ SECTOR_IN => SECTOR_IN,\r
+ MODULE_IN => MODULE_IN,\r
+ IPU_NUMBER_IN => IPU_NUMBER_IN,\r
+ IPU_INFORMATION_IN => IPU_INFORMATION_IN,\r
+ IPU_START_READOUT_IN => IPU_START_READOUT_IN,\r
+ IPU_DATA_OUT => IPU_DATA_OUT,\r
+ IPU_DATAREADY_OUT => IPU_DATAREADY_OUT,\r
+ IPU_READOUT_FINISHED_OUT => IPU_READOUT_FINISHED_OUT,\r
+ IPU_READ_IN => IPU_READ_IN,\r
+ IPU_LENGTH_OUT => IPU_LENGTH_OUT,\r
+ IPU_ERROR_PATTERN_OUT => IPU_ERROR_PATTERN_OUT,\r
+ LVL2_COUNTER_OUT => LVL2_COUNTER_OUT,\r
+ DHDR_DATA_IN => DHDR_DATA_IN,\r
+ DHDR_LENGTH_IN => DHDR_LENGTH_IN,\r
+ DHDR_STORE_IN => DHDR_STORE_IN,\r
+ DHDR_BUF_FULL_OUT => DHDR_BUF_FULL_OUT,\r
+ FIFO_START_IN => FIFO_START_IN,\r
+ FIFO_SPACE_REQ_IN => FIFO_SPACE_REQ_IN,\r
+ FIFO_0_DATA_IN => FIFO_0_DATA_IN,\r
+ FIFO_1_DATA_IN => FIFO_1_DATA_IN,\r
+ FIFO_2_DATA_IN => FIFO_2_DATA_IN,\r
+ FIFO_3_DATA_IN => FIFO_3_DATA_IN,\r
+ FIFO_4_DATA_IN => FIFO_4_DATA_IN,\r
+ FIFO_5_DATA_IN => FIFO_5_DATA_IN,\r
+ FIFO_6_DATA_IN => FIFO_6_DATA_IN,\r
+ FIFO_7_DATA_IN => FIFO_7_DATA_IN,\r
+ FIFO_8_DATA_IN => FIFO_8_DATA_IN,\r
+ FIFO_9_DATA_IN => FIFO_9_DATA_IN,\r
+ FIFO_10_DATA_IN => FIFO_10_DATA_IN,\r
+ FIFO_11_DATA_IN => FIFO_11_DATA_IN,\r
+ FIFO_12_DATA_IN => FIFO_12_DATA_IN,\r
+ FIFO_13_DATA_IN => FIFO_13_DATA_IN,\r
+ FIFO_14_DATA_IN => FIFO_14_DATA_IN,\r
+ FIFO_15_DATA_IN => FIFO_15_DATA_IN,\r
+ FIFO_WE_IN => FIFO_WE_IN,\r
+ FIFO_DONE_IN => FIFO_DONE_IN,\r
+ DBG_BSM_OUT => DBG_BSM_OUT,\r
+ DBG_OUT => DBG_OUT\r
+ );\r
+\r
+-- Generate the clock\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '0'; wait for 5 ns;\r
+ clk_in <= '1'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+-- The real testbench\r
+THE_TESTBENCH_PROC: process\r
+variable LOOP_I: integer;\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ module_in <= "000";\r
+ sector_in <= "111";\r
+ ipu_number_in <= x"0000";\r
+ ipu_information_in <= x"00";\r
+ ipu_start_readout_in <= '0';\r
+ ipu_read_in <= '0';\r
+ dhdr_data_in <= x"01234567";\r
+ dhdr_length_in <= x"0000";\r
+ dhdr_store_in <= '0';\r
+-- fifo_space_req_in <= x"082"; -- 128 + 2\r
+ fifo_space_req_in <= x"7f8"; \r
+ fifo_start_in <= '0';\r
+ fifo_we_in <= x"0000";\r
+ fifo_done_in <= '0';\r
+ fifo_0_data_in <= (others => '0');\r
+ fifo_1_data_in <= (others => '0');\r
+ fifo_2_data_in <= (others => '0');\r
+ fifo_3_data_in <= (others => '0');\r
+ fifo_4_data_in <= (others => '0');\r
+ fifo_5_data_in <= (others => '0');\r
+ fifo_6_data_in <= (others => '0');\r
+ fifo_7_data_in <= (others => '0');\r
+ fifo_8_data_in <= (others => '0');\r
+ fifo_9_data_in <= (others => '0');\r
+ fifo_10_data_in <= (others => '0');\r
+ fifo_11_data_in <= (others => '0');\r
+ fifo_12_data_in <= (others => '0');\r
+ fifo_13_data_in <= (others => '0');\r
+ fifo_14_data_in <= (others => '0');\r
+ fifo_15_data_in <= (others => '0');\r
+ \r
+ wait for 20 ns;\r
+ \r
+ -- Do a reset\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- test may start here\r
+\r
+ -- Data is coming from processing stage\r
+ -- Start of event\r
+ wait until rising_edge(clk_in);\r
+ fifo_start_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ fifo_start_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Fill data buffers\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_1111_1111_1111";\r
+-- fifo_we_in <= b"1111_1111_0111_1111";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_1111";\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0001_1110";\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0010_1101";\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0011_1100";\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0100_1011";\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1111_1110";\r
+ fifo_we_in <= b"1111_1111_0111_1110";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0001_1110";\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0010_1101";\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0011_1100";\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0100_1011";\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1111_1100";\r
+ fifo_we_in <= b"1111_1111_0111_1100";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0010_1101";\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0011_1100";\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0100_1011";\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1111_1000";\r
+ fifo_we_in <= b"1111_1111_0111_1000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0011_1100";\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0100_1011";\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1111_0000";\r
+ fifo_we_in <= b"1111_1111_0111_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0100_1011";\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1110_0000";\r
+ fifo_we_in <= b"1111_1111_0110_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1100_0000";\r
+ fifo_we_in <= b"1111_1111_0100_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1000_0000";\r
+ fifo_we_in <= b"1111_1111_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_1111_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_1110_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_1100_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_1000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_0000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1110_0000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1101_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1101_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1101_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1100_0000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1110_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1110_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1000_0000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1111_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"0000_0000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Final stage, counter values setting\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ fifo_0_data_in(37 downto 27) <= "10000000001"; -- 1\r
+ fifo_1_data_in(37 downto 27) <= "10000000010"; -- 2\r
+ fifo_2_data_in(37 downto 27) <= "10000000011"; -- 3\r
+ fifo_3_data_in(37 downto 27) <= "10000000100"; -- 4\r
+ fifo_4_data_in(37 downto 27) <= "10000000101"; -- 5\r
+ fifo_5_data_in(37 downto 27) <= "10000000110"; -- 6\r
+ fifo_6_data_in(37 downto 27) <= "10000000111"; -- 7\r
+-- fifo_7_data_in(37 downto 27) <= "10000001000"; -- 8\r
+ fifo_7_data_in(37 downto 27) <= "10000000001"; -- NO DATA\r
+ fifo_8_data_in(37 downto 27) <= "10000001001"; -- 9\r
+ fifo_9_data_in(37 downto 27) <= "10000001010"; -- 10\r
+ fifo_10_data_in(37 downto 27) <= "10000001011"; -- 11\r
+ fifo_11_data_in(37 downto 27) <= "10000001100"; -- 12\r
+ fifo_12_data_in(37 downto 27) <= "10000001101"; -- 13\r
+ fifo_13_data_in(37 downto 27) <= "10000001110"; -- 14\r
+ fifo_14_data_in(37 downto 27) <= "10000001111"; -- 15\r
+ fifo_15_data_in(37 downto 27) <= "10000010000"; -- 16\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Event (0) DHDR\r
+ wait until rising_edge(clk_in);\r
+ dhdr_data_in <= x"1abbcccc";\r
+ dhdr_length_in <= x"0010";\r
+ dhdr_store_in <= '1';\r
+ fifo_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ dhdr_store_in <= '0';\r
+ fifo_done_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 2 us;\r
+ \r
+ -- IPU request\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ ipu_number_in <= x"cccc";\r
+ ipu_information_in <= x"ff";\r
+ ipu_start_readout_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+\r
+\r
+ -- wait for statemachine to react \r
+ -- transfer DHDR\r
+ wait until rising_edge(ipu_dataready_out);\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ THE_LOOP: for i in 0 to 1024 loop\r
+ ipu_read_in <= '1';\r
+ wait until (ipu_dataready_out = '1') or (ipu_readout_finished_out = '1');\r
+ if ipu_readout_finished_out = '1' then exit; end if;\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ if ipu_readout_finished_out = '1' then exit; end if;\r
+ wait until rising_edge(clk_in);\r
+ \r
+ end loop THE_LOOP;\r
+\r
+ wait;\r
+\r
+---\r
+-- theloop : for i in 0 to 100 loop\r
+-- ipu_read_in <= '1';\r
+-- wait until ipu_dataready_out = '1' or ipu_readout_finished_out = '1';\r
+-- if ipu_readout_finished_out = '1' then exit; end if;\r
+-- wait until rising_edge(CLOCK);\r
+-- ipu_read_in <= '0';\r
+-- if ipu_readout_finished_out = '1' then exit; end if;\r
+-- case i is\r
+-- when 3 => wait for 39 ns;\r
+-- when 4 => wait for 49 ns;\r
+-- when 5 => wait for 29 ns;\r
+-- when others => null;\r
+-- end case;\r
+-- wait until rising_edge(CLOCK);\r
+-- if ipu_readout_finished_out = '1' then exit; end if;\r
+-- end loop;\r
+---\r
+\r
+\r
+ wait;\r
+\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(ipu_readout_finished_out);\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ ipu_start_readout_in <= '0';\r
+ \r
+ wait;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ ------------------------------------------------------------------------\r
+ ------------------------------------------------------------------------\r
+\r
+ -- wait for statemachine to react \r
+ -- DHDR\r
+ wait until rising_edge(ipu_dataready_out);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+\r
+ DATA_LOOP: for LOOP_I in 34 downto 0 loop\r
+ -- one data word\r
+ wait until rising_edge(ipu_dataready_out);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ end loop DATA_LOOP;\r
+\r
+\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Stay a while, stay forever.... wuhahahahaha\r
+ wait;\r
+end process THE_TESTBENCH_PROC;\r
+\r
+\r
+END;\r
+\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT ipu_fifo_stage\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ SECTOR_IN : IN std_logic_vector(2 downto 0);\r
+ MODULE_IN : IN std_logic_vector(2 downto 0);\r
+ IPU_NUMBER_IN : IN std_logic_vector(15 downto 0);\r
+ IPU_INFORMATION_IN : IN std_logic_vector(7 downto 0);\r
+ IPU_START_READOUT_IN : IN std_logic;\r
+ IPU_READ_IN : IN std_logic;\r
+ DHDR_DATA_IN : IN std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_IN : IN std_logic_vector(15 downto 0);\r
+ DHDR_STORE_IN : IN std_logic;\r
+ FIFO_SPACE_REQ_IN : IN std_logic_vector(11 downto 0);\r
+ FIFO_START_IN : IN std_logic;\r
+ FIFO_0_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_WE_IN : IN std_logic_vector(15 downto 0);\r
+ FIFO_DONE_IN : IN std_logic; \r
+ IPU_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
+ IPU_DATAREADY_OUT : OUT std_logic;\r
+ IPU_READOUT_FINISHED_OUT : OUT std_logic;\r
+ IPU_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
+ IPU_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);\r
+ DBG_BSM_OUT : OUT std_logic_vector(7 downto 0);\r
+ DBG_OUT : OUT std_logic_vector(63 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL SECTOR_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL MODULE_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL IPU_NUMBER_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL IPU_INFORMATION_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL IPU_START_READOUT_IN : std_logic;\r
+ SIGNAL IPU_DATA_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL IPU_DATAREADY_OUT : std_logic;\r
+ SIGNAL IPU_READOUT_FINISHED_OUT : std_logic;\r
+ SIGNAL IPU_READ_IN : std_logic;\r
+ SIGNAL IPU_LENGTH_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL IPU_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL DHDR_DATA_IN : std_logic_vector(31 downto 0);\r
+ SIGNAL DHDR_LENGTH_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL DHDR_STORE_IN : std_logic;\r
+ SIGNAL FIFO_SPACE_REQ_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL FIFO_START_IN : std_logic;\r
+ SIGNAL FIFO_0_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_1_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_2_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_3_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_4_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_5_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_6_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_7_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_8_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_9_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_10_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_11_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_12_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_13_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_14_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_15_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_WE_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL FIFO_DONE_IN : std_logic;\r
+ SIGNAL DBG_BSM_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL DBG_OUT : std_logic_vector(63 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: ipu_fifo_stage PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ SECTOR_IN => SECTOR_IN,\r
+ MODULE_IN => MODULE_IN,\r
+ IPU_NUMBER_IN => IPU_NUMBER_IN,\r
+ IPU_INFORMATION_IN => IPU_INFORMATION_IN,\r
+ IPU_START_READOUT_IN => IPU_START_READOUT_IN,\r
+ IPU_DATA_OUT => IPU_DATA_OUT,\r
+ IPU_DATAREADY_OUT => IPU_DATAREADY_OUT,\r
+ IPU_READOUT_FINISHED_OUT => IPU_READOUT_FINISHED_OUT,\r
+ IPU_READ_IN => IPU_READ_IN,\r
+ IPU_LENGTH_OUT => IPU_LENGTH_OUT,\r
+ IPU_ERROR_PATTERN_OUT => IPU_ERROR_PATTERN_OUT,\r
+ DHDR_DATA_IN => DHDR_DATA_IN,\r
+ DHDR_LENGTH_IN => DHDR_LENGTH_IN,\r
+ DHDR_STORE_IN => DHDR_STORE_IN,\r
+ FIFO_SPACE_REQ_IN => FIFO_SPACE_REQ_IN,\r
+ FIFO_START_IN => FIFO_START_IN,\r
+ FIFO_0_DATA_IN => FIFO_0_DATA_IN,\r
+ FIFO_1_DATA_IN => FIFO_1_DATA_IN,\r
+ FIFO_2_DATA_IN => FIFO_2_DATA_IN,\r
+ FIFO_3_DATA_IN => FIFO_3_DATA_IN,\r
+ FIFO_4_DATA_IN => FIFO_4_DATA_IN,\r
+ FIFO_5_DATA_IN => FIFO_5_DATA_IN,\r
+ FIFO_6_DATA_IN => FIFO_6_DATA_IN,\r
+ FIFO_7_DATA_IN => FIFO_7_DATA_IN,\r
+ FIFO_8_DATA_IN => FIFO_8_DATA_IN,\r
+ FIFO_9_DATA_IN => FIFO_9_DATA_IN,\r
+ FIFO_10_DATA_IN => FIFO_10_DATA_IN,\r
+ FIFO_11_DATA_IN => FIFO_11_DATA_IN,\r
+ FIFO_12_DATA_IN => FIFO_12_DATA_IN,\r
+ FIFO_13_DATA_IN => FIFO_13_DATA_IN,\r
+ FIFO_14_DATA_IN => FIFO_14_DATA_IN,\r
+ FIFO_15_DATA_IN => FIFO_15_DATA_IN,\r
+ FIFO_WE_IN => FIFO_WE_IN,\r
+ FIFO_DONE_IN => FIFO_DONE_IN,\r
+ DBG_BSM_OUT => DBG_BSM_OUT,\r
+ DBG_OUT => DBG_OUT\r
+ );\r
+\r
+-- Generate the clock\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '0'; wait for 5 ns;\r
+ clk_in <= '1'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+-- The real testbench\r
+THE_TESTBENCH_PROC: process\r
+variable LOOP_I: integer;\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ module_in <= "000";\r
+ sector_in <= "111";\r
+ ipu_number_in <= x"0000";\r
+ ipu_information_in <= x"00";\r
+ ipu_start_readout_in <= '0';\r
+ ipu_read_in <= '0';\r
+ dhdr_data_in <= x"01234567";\r
+ dhdr_length_in <= x"0000";\r
+ dhdr_store_in <= '0';\r
+ fifo_space_req_in <= x"082"; -- 128 + 2\r
+ fifo_start_in <= '0';\r
+ fifo_we_in <= x"0000";\r
+ fifo_done_in <= '0';\r
+ fifo_0_data_in <= (others => '0');\r
+ fifo_1_data_in <= (others => '0');\r
+ fifo_2_data_in <= (others => '0');\r
+ fifo_3_data_in <= (others => '0');\r
+ fifo_4_data_in <= (others => '0');\r
+ fifo_5_data_in <= (others => '0');\r
+ fifo_6_data_in <= (others => '0');\r
+ fifo_7_data_in <= (others => '0');\r
+ fifo_8_data_in <= (others => '0');\r
+ fifo_9_data_in <= (others => '0');\r
+ fifo_10_data_in <= (others => '0');\r
+ fifo_11_data_in <= (others => '0');\r
+ fifo_12_data_in <= (others => '0');\r
+ fifo_13_data_in <= (others => '0');\r
+ fifo_14_data_in <= (others => '0');\r
+ fifo_15_data_in <= (others => '0');\r
+ \r
+ wait for 20 ns;\r
+ \r
+ -- Do a reset\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- test may start here\r
+\r
+ -- Data is coming from processing stage\r
+ -- Start of event\r
+ wait until rising_edge(clk_in);\r
+ fifo_start_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ fifo_start_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Fill data buffers\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_1111_1111_1111";\r
+-- fifo_we_in <= b"1111_1111_0111_1111";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_1111";\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0001_1110";\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0010_1101";\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0011_1100";\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0100_1011";\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1111_1110";\r
+ fifo_we_in <= b"1111_1111_0111_1110";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0001_1110";\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0010_1101";\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0011_1100";\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0100_1011";\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1111_1100";\r
+ fifo_we_in <= b"1111_1111_0111_1100";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0010_1101";\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0011_1100";\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0100_1011";\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1111_1000";\r
+ fifo_we_in <= b"1111_1111_0111_1000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0011_1100";\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0100_1011";\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1111_0000";\r
+ fifo_we_in <= b"1111_1111_0111_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0100_1011";\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1110_0000";\r
+ fifo_we_in <= b"1111_1111_0110_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1100_0000";\r
+ fifo_we_in <= b"1111_1111_0100_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+-- fifo_we_in <= b"1111_1111_1000_0000";\r
+ fifo_we_in <= b"1111_1111_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_1111_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_1110_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_1100_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_1000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_0000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1110_0000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1101_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1101_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1101_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1100_0000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1110_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1110_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1000_0000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1111_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"0000_0000_0000_0000";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Final stage, counter values setting\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ fifo_0_data_in(37 downto 27) <= "10000000001"; -- 1\r
+ fifo_1_data_in(37 downto 27) <= "10000000010"; -- 2\r
+ fifo_2_data_in(37 downto 27) <= "10000000011"; -- 3\r
+ fifo_3_data_in(37 downto 27) <= "10000000100"; -- 4\r
+ fifo_4_data_in(37 downto 27) <= "10000000101"; -- 5\r
+ fifo_5_data_in(37 downto 27) <= "10000000110"; -- 6\r
+ fifo_6_data_in(37 downto 27) <= "10000000111"; -- 7\r
+-- fifo_7_data_in(37 downto 27) <= "10000001000"; -- 8\r
+ fifo_7_data_in(37 downto 27) <= "10000000001"; -- NO DATA\r
+ fifo_8_data_in(37 downto 27) <= "10000001001"; -- 9\r
+ fifo_9_data_in(37 downto 27) <= "10000001010"; -- 10\r
+ fifo_10_data_in(37 downto 27) <= "10000001011"; -- 11\r
+ fifo_11_data_in(37 downto 27) <= "10000001100"; -- 12\r
+ fifo_12_data_in(37 downto 27) <= "10000001101"; -- 13\r
+ fifo_13_data_in(37 downto 27) <= "10000001110"; -- 14\r
+ fifo_14_data_in(37 downto 27) <= "10000001111"; -- 15\r
+ fifo_15_data_in(37 downto 27) <= "10000010000"; -- 16\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Event (0) DHDR\r
+ wait until rising_edge(clk_in);\r
+ dhdr_data_in <= x"1abbcccc";\r
+ dhdr_length_in <= x"0010";\r
+ dhdr_store_in <= '1';\r
+ fifo_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ dhdr_store_in <= '0';\r
+ fifo_done_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 2 us;\r
+ \r
+ -- IPU request\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ ipu_number_in <= x"cccc";\r
+ ipu_information_in <= x"ff";\r
+ ipu_start_readout_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+\r
+\r
+ -- wait for statemachine to react \r
+ -- transfer DHDR\r
+ wait until rising_edge(ipu_dataready_out);\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ THE_LOOP: for i in 0 to 1024 loop\r
+ ipu_read_in <= '1';\r
+ wait until (ipu_dataready_out = '1') or (ipu_readout_finished_out = '1');\r
+ if ipu_readout_finished_out = '1' then exit; end if;\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ if ipu_readout_finished_out = '1' then exit; end if;\r
+ wait until rising_edge(clk_in);\r
+ \r
+ end loop THE_LOOP;\r
+\r
+ wait;\r
+\r
+---\r
+-- theloop : for i in 0 to 100 loop\r
+-- ipu_read_in <= '1';\r
+-- wait until ipu_dataready_out = '1' or ipu_readout_finished_out = '1';\r
+-- if ipu_readout_finished_out = '1' then exit; end if;\r
+-- wait until rising_edge(CLOCK);\r
+-- ipu_read_in <= '0';\r
+-- if ipu_readout_finished_out = '1' then exit; end if;\r
+-- case i is\r
+-- when 3 => wait for 39 ns;\r
+-- when 4 => wait for 49 ns;\r
+-- when 5 => wait for 29 ns;\r
+-- when others => null;\r
+-- end case;\r
+-- wait until rising_edge(CLOCK);\r
+-- if ipu_readout_finished_out = '1' then exit; end if;\r
+-- end loop;\r
+---\r
+\r
+\r
+ wait;\r
+\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(ipu_readout_finished_out);\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ ipu_start_readout_in <= '0';\r
+ \r
+ wait;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ ------------------------------------------------------------------------\r
+ ------------------------------------------------------------------------\r
+\r
+ -- wait for statemachine to react \r
+ -- DHDR\r
+ wait until rising_edge(ipu_dataready_out);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+\r
+ DATA_LOOP: for LOOP_I in 34 downto 0 loop\r
+ -- one data word\r
+ wait until rising_edge(ipu_dataready_out);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ end loop DATA_LOOP;\r
+\r
+\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Stay a while, stay forever.... wuhahahahaha\r
+ wait;\r
+end process THE_TESTBENCH_PROC;\r
+\r
+\r
+END;\r
+\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT fifo_18x16_media_interface\r
+ PORT(\r
+ Data : IN std_logic_vector(17 downto 0);\r
+ Clock : IN std_logic;\r
+ WrEn : IN std_logic;\r
+ RdEn : IN std_logic;\r
+ Reset : IN std_logic; \r
+ Q : OUT std_logic_vector(17 downto 0);\r
+ WCNT : OUT std_logic_vector(4 downto 0);\r
+ Empty : OUT std_logic;\r
+ Full : OUT std_logic;\r
+ AlmostEmpty : OUT std_logic\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL Data : std_logic_vector(17 downto 0);\r
+ SIGNAL Clock : std_logic;\r
+ SIGNAL WrEn : std_logic;\r
+ SIGNAL RdEn : std_logic;\r
+ SIGNAL Reset : std_logic;\r
+ SIGNAL Q : std_logic_vector(17 downto 0);\r
+ SIGNAL WCNT : std_logic_vector(4 downto 0);\r
+ SIGNAL Empty : std_logic;\r
+ SIGNAL Full : std_logic;\r
+ SIGNAL AlmostEmpty : std_logic;\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: fifo_18x16_media_interface PORT MAP(\r
+ Data => Data,\r
+ Clock => Clock,\r
+ WrEn => WrEn,\r
+ RdEn => RdEn,\r
+ Reset => Reset,\r
+ Q => Q,\r
+ WCNT => WCNT,\r
+ Empty => Empty,\r
+ Full => Full,\r
+ AlmostEmpty => AlmostEmpty\r
+ );\r
+\r
+CLOCK_GEN: process\r
+begin\r
+ clock <= '0'; wait for 5.0 ns;\r
+ clock <= '1'; wait for 5.0 ns;\r
+end process CLOCK_GEN;\r
+\r
+\r
+THE_TESTBENCH: process\r
+begin\r
+ -- Setup signals\r
+ data <= b"00_0000_0000_0000_0000";\r
+ wren <= '0';\r
+ rden <= '0';\r
+ reset <= '0';\r
+ wait for 30 ns;\r
+ \r
+ -- Reset the whole story\r
+ wait until rising_edge(clock);\r
+ reset <= '1';\r
+ wait until rising_edge(clock);\r
+ reset <= '0';\r
+ wait for 50 ns;\r
+ \r
+ -- Tests may start now\r
+ wait until rising_edge(clock);\r
+ wren <= '1';\r
+ data <= b"11_0000_0000_0000_0000";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0001";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0010";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0011";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0100";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0101";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0110";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0111";\r
+ wait until rising_edge(clock);\r
+ wren <= '0'; \r
+\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ rden <= '1';\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ rden <= '0';\r
+\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+\r
+ rden <= '1';\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ rden <= '0';\r
+ \r
+ -- Stay a while.... stay forever!!! Muahaha!!!\r
+ wait;\r
+\r
+end process THE_TESTBENCH;\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT fifo_18x16_media_interface\r
+ PORT(\r
+ Data : IN std_logic_vector(17 downto 0);\r
+ Clock : IN std_logic;\r
+ WrEn : IN std_logic;\r
+ RdEn : IN std_logic;\r
+ Reset : IN std_logic; \r
+ Q : OUT std_logic_vector(17 downto 0);\r
+ WCNT : OUT std_logic_vector(4 downto 0);\r
+ Empty : OUT std_logic;\r
+ Full : OUT std_logic;\r
+ AlmostEmpty : OUT std_logic\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL Data : std_logic_vector(17 downto 0);\r
+ SIGNAL Clock : std_logic;\r
+ SIGNAL WrEn : std_logic;\r
+ SIGNAL RdEn : std_logic;\r
+ SIGNAL Reset : std_logic;\r
+ SIGNAL Q : std_logic_vector(17 downto 0);\r
+ SIGNAL WCNT : std_logic_vector(4 downto 0);\r
+ SIGNAL Empty : std_logic;\r
+ SIGNAL Full : std_logic;\r
+ SIGNAL AlmostEmpty : std_logic;\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: fifo_18x16_media_interface PORT MAP(\r
+ Data => Data,\r
+ Clock => Clock,\r
+ WrEn => WrEn,\r
+ RdEn => RdEn,\r
+ Reset => Reset,\r
+ Q => Q,\r
+ WCNT => WCNT,\r
+ Empty => Empty,\r
+ Full => Full,\r
+ AlmostEmpty => AlmostEmpty\r
+ );\r
+\r
+CLOCK_GEN: process\r
+begin\r
+ clock <= '0'; wait for 5.0 ns;\r
+ clock <= '1'; wait for 5.0 ns;\r
+end process CLOCK_GEN;\r
+\r
+\r
+THE_TESTBENCH: process\r
+begin\r
+ -- Setup signals\r
+ data <= b"00_0000_0000_0000_0000";\r
+ wren <= '0';\r
+ rden <= '0';\r
+ reset <= '0';\r
+ wait for 30 ns;\r
+ \r
+ -- Reset the whole story\r
+ wait until rising_edge(clock);\r
+ reset <= '1';\r
+ wait until rising_edge(clock);\r
+ reset <= '0';\r
+ wait for 50 ns;\r
+ \r
+ -- Tests may start now\r
+ wait until rising_edge(clock);\r
+ wren <= '1';\r
+ data <= b"11_0000_0000_0000_0000";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0001";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0010";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0011";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0100";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0101";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0110";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0111";\r
+ wait until rising_edge(clock);\r
+ wren <= '0'; \r
+\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ rden <= '1';\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ rden <= '0';\r
+ \r
+ -- Stay a while.... stay forever!!! Muahaha!!!\r
+ wait;\r
+\r
+end process THE_TESTBENCH;\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT fifo_18x16_media_interface_mb\r
+ PORT(\r
+ Data : IN std_logic_vector(17 downto 0);\r
+ Clock : IN std_logic;\r
+ WrEn : IN std_logic;\r
+ RdEn : IN std_logic;\r
+ Reset : IN std_logic;\r
+ AmEmptySetThresh : IN std_logic_vector(3 downto 0);\r
+ AmEmptyClrThresh : IN std_logic_vector(3 downto 0);\r
+ AmFullSetThresh : IN std_logic_vector(3 downto 0);\r
+ AmFullClrThresh : IN std_logic_vector(3 downto 0); \r
+ Q : OUT std_logic_vector(17 downto 0);\r
+ WCNT : OUT std_logic_vector(4 downto 0);\r
+ Empty : OUT std_logic;\r
+ Full : OUT std_logic;\r
+ AlmostEmpty : OUT std_logic;\r
+ AlmostFull : OUT std_logic\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL Data : std_logic_vector(17 downto 0);\r
+ SIGNAL Clock : std_logic;\r
+ SIGNAL WrEn : std_logic;\r
+ SIGNAL RdEn : std_logic;\r
+ SIGNAL Reset : std_logic;\r
+ SIGNAL AmEmptySetThresh : std_logic_vector(3 downto 0);\r
+ SIGNAL AmEmptyClrThresh : std_logic_vector(3 downto 0);\r
+ SIGNAL AmFullSetThresh : std_logic_vector(3 downto 0);\r
+ SIGNAL AmFullClrThresh : std_logic_vector(3 downto 0);\r
+ SIGNAL Q : std_logic_vector(17 downto 0);\r
+ SIGNAL WCNT : std_logic_vector(4 downto 0);\r
+ SIGNAL Empty : std_logic;\r
+ SIGNAL Full : std_logic;\r
+ SIGNAL AlmostEmpty : std_logic;\r
+ SIGNAL AlmostFull : std_logic;\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: fifo_18x16_media_interface_mb PORT MAP(\r
+ Data => Data,\r
+ Clock => Clock,\r
+ WrEn => WrEn,\r
+ RdEn => RdEn,\r
+ Reset => Reset,\r
+ AmEmptySetThresh => AmEmptySetThresh,\r
+ AmEmptyClrThresh => AmEmptyClrThresh,\r
+ AmFullSetThresh => AmFullSetThresh,\r
+ AmFullClrThresh => AmFullClrThresh,\r
+ Q => Q,\r
+ WCNT => WCNT,\r
+ Empty => Empty,\r
+ Full => Full,\r
+ AlmostEmpty => AlmostEmpty,\r
+ AlmostFull => AlmostFull\r
+ );\r
+\r
+\r
+CLOCK_GEN: process\r
+begin\r
+ clock <= '0'; wait for 5.0 ns;\r
+ clock <= '1'; wait for 5.0 ns;\r
+end process CLOCK_GEN;\r
+\r
+\r
+THE_TESTBENCH: process\r
+begin\r
+ -- Setup signals\r
+ data <= b"00_0000_0000_0000_0000";\r
+ wren <= '0';\r
+ rden <= '0';\r
+ AmEmptySetThresh <= x"4";\r
+ AmEmptyClrThresh <= x"6";\r
+ AmFullSetThresh <= x"e";\r
+ AmFullClrThresh <= x"c";\r
+ reset <= '0';\r
+ wait for 30 ns;\r
+ \r
+ -- Reset the whole story\r
+ wait until rising_edge(clock);\r
+ reset <= '1';\r
+ wait until rising_edge(clock);\r
+ reset <= '0';\r
+ wait for 50 ns;\r
+ \r
+ -- Tests may start now\r
+ wait until rising_edge(clock);\r
+ wren <= '1';\r
+ data <= b"11_0000_0000_0000_0000";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0001";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0010";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0011";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0100";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0101";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0110";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0111";\r
+ wait until rising_edge(clock);\r
+ wren <= '0'; \r
+\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ rden <= '1';\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ rden <= '0';\r
+\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+\r
+ rden <= '1';\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ rden <= '0';\r
+ \r
+ -- Stay a while.... stay forever!!! Muahaha!!!\r
+ wait;\r
+\r
+end process THE_TESTBENCH;\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT fifo_18x16_media_interface_mb\r
+ PORT(\r
+ Data : IN std_logic_vector(17 downto 0);\r
+ Clock : IN std_logic;\r
+ WrEn : IN std_logic;\r
+ RdEn : IN std_logic;\r
+ Reset : IN std_logic;\r
+ AmEmptySetThresh : IN std_logic_vector(3 downto 0);\r
+ AmEmptyClrThresh : IN std_logic_vector(3 downto 0);\r
+ AmFullSetThresh : IN std_logic_vector(3 downto 0);\r
+ AmFullClrThresh : IN std_logic_vector(3 downto 0); \r
+ Q : OUT std_logic_vector(17 downto 0);\r
+ WCNT : OUT std_logic_vector(4 downto 0);\r
+ Empty : OUT std_logic;\r
+ Full : OUT std_logic;\r
+ AlmostEmpty : OUT std_logic;\r
+ AlmostFull : OUT std_logic\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL Data : std_logic_vector(17 downto 0);\r
+ SIGNAL Clock : std_logic;\r
+ SIGNAL WrEn : std_logic;\r
+ SIGNAL RdEn : std_logic;\r
+ SIGNAL Reset : std_logic;\r
+ SIGNAL AmEmptySetThresh : std_logic_vector(3 downto 0);\r
+ SIGNAL AmEmptyClrThresh : std_logic_vector(3 downto 0);\r
+ SIGNAL AmFullSetThresh : std_logic_vector(3 downto 0);\r
+ SIGNAL AmFullClrThresh : std_logic_vector(3 downto 0);\r
+ SIGNAL Q : std_logic_vector(17 downto 0);\r
+ SIGNAL WCNT : std_logic_vector(4 downto 0);\r
+ SIGNAL Empty : std_logic;\r
+ SIGNAL Full : std_logic;\r
+ SIGNAL AlmostEmpty : std_logic;\r
+ SIGNAL AlmostFull : std_logic;\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: fifo_18x16_media_interface_mb PORT MAP(\r
+ Data => Data,\r
+ Clock => Clock,\r
+ WrEn => WrEn,\r
+ RdEn => RdEn,\r
+ Reset => Reset,\r
+ AmEmptySetThresh => AmEmptySetThresh,\r
+ AmEmptyClrThresh => AmEmptyClrThresh,\r
+ AmFullSetThresh => AmFullSetThresh,\r
+ AmFullClrThresh => AmFullClrThresh,\r
+ Q => Q,\r
+ WCNT => WCNT,\r
+ Empty => Empty,\r
+ Full => Full,\r
+ AlmostEmpty => AlmostEmpty,\r
+ AlmostFull => AlmostFull\r
+ );\r
+\r
+\r
+CLOCK_GEN: process\r
+begin\r
+ clock <= '0'; wait for 5.0 ns;\r
+ clock <= '1'; wait for 5.0 ns;\r
+end process CLOCK_GEN;\r
+\r
+\r
+THE_TESTBENCH: process\r
+begin\r
+ -- Setup signals\r
+ data <= b"00_0000_0000_0000_0000";\r
+ wren <= '0';\r
+ rden <= '0';\r
+ AmEmptySetThresh <= x"4";\r
+ AmEmptyClrThresh <= x"6";\r
+ AmFullSetThresh <= x"e";\r
+ AmFullClrThresh => x"c";\r
+ reset <= '0';\r
+ wait for 30 ns;\r
+ \r
+ -- Reset the whole story\r
+ wait until rising_edge(clock);\r
+ reset <= '1';\r
+ wait until rising_edge(clock);\r
+ reset <= '0';\r
+ wait for 50 ns;\r
+ \r
+ -- Tests may start now\r
+ wait until rising_edge(clock);\r
+ wren <= '1';\r
+ data <= b"11_0000_0000_0000_0000";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0001";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0010";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0011";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0100";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0101";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0110";\r
+ wait until rising_edge(clock);\r
+ data <= b"11_0000_0000_0000_0111";\r
+ wait until rising_edge(clock);\r
+ wren <= '0'; \r
+\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ rden <= '1';\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ rden <= '0';\r
+\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+\r
+ rden <= '1';\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ rden <= '0';\r
+ \r
+ -- Stay a while.... stay forever!!! Muahaha!!!\r
+ wait;\r
+\r
+end process THE_TESTBENCH;\r
+\r
+END;\r
PORT(\r
CLK_IN : IN std_logic;\r
RESET_IN : IN std_logic;\r
+ VERBOSE_IN : IN std_logic;\r
EDS_DATA_IN : IN std_logic_vector(39 downto 0);\r
EDS_AVAIL_IN : IN std_logic;\r
BUF_TICK_IN : IN std_logic_vector(15 downto 0);\r
\r
SIGNAL CLK_IN : std_logic;\r
SIGNAL RESET_IN : std_logic;\r
+ SIGNAL VERBOSE_IN : std_logic;\r
SIGNAL EDS_DATA_IN : std_logic_vector(39 downto 0);\r
SIGNAL EDS_AVAIL_IN : std_logic;\r
SIGNAL EDS_DONE_OUT : std_logic;\r
uut: ped_corr_ctrl PORT MAP(\r
CLK_IN => CLK_IN,\r
RESET_IN => RESET_IN,\r
+ VERBOSE_IN => VERBOSE_IN,\r
EDS_DATA_IN => EDS_DATA_IN,\r
EDS_AVAIL_IN => EDS_AVAIL_IN,\r
EDS_DONE_OUT => EDS_DONE_OUT,\r
begin\r
-- Setup signal\r
reset_in <= '0';\r
+ verbose_in <= '0';\r
dhdr_buf_full_in <= '0';\r
eds_data_in <= (others => '0'); \r
eds_avail_in <= '0';\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT ped_corr_ctrl\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ VERBOSE_IN : IN std_logic;\r
+ EDS_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ EDS_AVAIL_IN : IN std_logic;\r
+ BUF_TICK_IN : IN std_logic_vector(15 downto 0);\r
+ BUF_START_IN : IN std_logic_vector(15 downto 0);\r
+ BUF_0_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_1_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_2_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_3_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_4_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_5_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_6_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_7_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_8_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_9_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_10_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_11_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_12_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_13_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_14_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_15_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ PED_0_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_1_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_2_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_3_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_4_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_5_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_6_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_7_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_8_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_9_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_10_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_11_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_12_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_13_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_14_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_15_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_0_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_1_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_2_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_3_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_4_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_5_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_6_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_7_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_8_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_9_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_10_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_11_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_12_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_13_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_14_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_15_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ EDS_DONE_OUT : OUT std_logic;\r
+ DHDR_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
+ DHDR_BUF_FULL_IN : IN std_logic;\r
+ DHDR_STORE_OUT : OUT std_logic;\r
+ FIFO_SPACE_REQ_OUT : OUT std_logic_vector(11 downto 0);\r
+ PED_ADDR_OUT : OUT std_logic_vector(6 downto 0);\r
+ THR_ADDR_OUT : OUT std_logic_vector(6 downto 0);\r
+ BUF_ADDR_OUT : OUT std_logic_vector(6 downto 0);\r
+ BUF_DONE_OUT : OUT std_logic;\r
+ FIFO_START_OUT : OUT std_logic;\r
+ FIFO_0_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_WE_OUT : OUT std_logic_vector(15 downto 0);\r
+ FIFO_DONE_OUT : OUT std_logic;\r
+ DBG_BSM_OUT : OUT std_logic_vector(7 downto 0);\r
+ DBG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL VERBOSE_IN : std_logic;\r
+ SIGNAL EDS_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL EDS_AVAIL_IN : std_logic;\r
+ SIGNAL EDS_DONE_OUT : std_logic;\r
+ SIGNAL DHDR_DATA_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL DHDR_LENGTH_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL DHDR_BUF_FULL_IN : std_logic;\r
+ SIGNAL DHDR_STORE_OUT : std_logic;\r
+ SIGNAL BUF_ADDR_OUT : std_logic_vector(6 downto 0);\r
+ SIGNAL BUF_DONE_OUT : std_logic;\r
+ SIGNAL BUF_TICK_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL BUF_START_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL BUF_0_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_1_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_4_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL THR_ADDR_OUT : std_logic_vector(6 downto 0);\r
+ SIGNAL THR_0_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_1_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_4_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_ADDR_OUT : std_logic_vector(6 downto 0);\r
+ SIGNAL PED_0_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL FIFO_SPACE_REQ_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL FIFO_START_OUT : std_logic;\r
+-- SIGNAL FIFO_0_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL ADC_0_STATUS_OUT : std_logic_vector(25 downto 0);\r
+ SIGNAL ADC_0_DATA_OUT : std_logic_vector(13 downto 0);\r
+ SIGNAL FIFO_1_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_4_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_WE_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL FIFO_DONE_OUT : std_logic;\r
+ SIGNAL DBG_BSM_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL DBG_OUT : std_logic_vector(15 downto 0);\r
+\r
+\r
+ SIGNAL BUF_ADDR : std_logic_vector(6 downto 0);\r
+ SIGNAL PED_ADDR : std_logic_vector(6 downto 0);\r
+ SIGNAL THR_ADDR : std_logic_vector(6 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: ped_corr_ctrl PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ VERBOSE_IN => VERBOSE_IN,\r
+ EDS_DATA_IN => EDS_DATA_IN,\r
+ EDS_AVAIL_IN => EDS_AVAIL_IN,\r
+ EDS_DONE_OUT => EDS_DONE_OUT,\r
+ DHDR_DATA_OUT => DHDR_DATA_OUT,\r
+ DHDR_LENGTH_OUT => DHDR_LENGTH_OUT,\r
+ DHDR_BUF_FULL_IN => DHDR_BUF_FULL_IN,\r
+ DHDR_STORE_OUT => DHDR_STORE_OUT,\r
+ BUF_ADDR_OUT => BUF_ADDR_OUT,\r
+ BUF_DONE_OUT => BUF_DONE_OUT,\r
+ BUF_TICK_IN => BUF_TICK_IN,\r
+ BUF_START_IN => BUF_START_IN,\r
+ BUF_0_DATA_IN => BUF_0_DATA_IN,\r
+ BUF_1_DATA_IN => BUF_1_DATA_IN,\r
+ BUF_2_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_3_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_4_DATA_IN => BUF_4_DATA_IN,\r
+ BUF_5_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_6_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_7_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_8_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_9_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_10_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_11_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_12_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_13_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_14_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ BUF_15_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000",\r
+ PED_ADDR_OUT => PED_ADDR_OUT,\r
+ PED_0_DATA_IN => PED_0_DATA_IN,\r
+ PED_1_DATA_IN => b"00" & x"0000",\r
+ PED_2_DATA_IN => b"00" & x"0000",\r
+ PED_3_DATA_IN => b"00" & x"0000",\r
+ PED_4_DATA_IN => b"00" & x"0000",\r
+ PED_5_DATA_IN => b"00" & x"0000",\r
+ PED_6_DATA_IN => b"00" & x"0000",\r
+ PED_7_DATA_IN => b"00" & x"0000",\r
+ PED_8_DATA_IN => b"00" & x"0000",\r
+ PED_9_DATA_IN => b"00" & x"0000",\r
+ PED_10_DATA_IN => b"00" & x"0000",\r
+ PED_11_DATA_IN => b"00" & x"0000",\r
+ PED_12_DATA_IN => b"00" & x"0000",\r
+ PED_13_DATA_IN => b"00" & x"0000",\r
+ PED_14_DATA_IN => b"00" & x"0000",\r
+ PED_15_DATA_IN => b"00" & x"0000",\r
+ THR_ADDR_OUT => THR_ADDR_OUT,\r
+ THR_0_DATA_IN => THR_0_DATA_IN,\r
+ THR_1_DATA_IN => THR_1_DATA_IN,\r
+ THR_2_DATA_IN => b"00" & x"0000",\r
+ THR_3_DATA_IN => b"00" & x"0000",\r
+ THR_4_DATA_IN => THR_4_DATA_IN,\r
+ THR_5_DATA_IN => b"00" & x"0000",\r
+ THR_6_DATA_IN => b"00" & x"0000",\r
+ THR_7_DATA_IN => b"00" & x"0000",\r
+ THR_8_DATA_IN => b"00" & x"0000",\r
+ THR_9_DATA_IN => b"00" & x"0000",\r
+ THR_10_DATA_IN => b"00" & x"0000",\r
+ THR_11_DATA_IN => b"00" & x"0000",\r
+ THR_12_DATA_IN => b"00" & x"0000",\r
+ THR_13_DATA_IN => b"00" & x"0000",\r
+ THR_14_DATA_IN => b"00" & x"0000",\r
+ THR_15_DATA_IN => b"00" & x"0000",\r
+ FIFO_SPACE_REQ_OUT => FIFO_SPACE_REQ_OUT,\r
+ FIFO_START_OUT => FIFO_START_OUT,\r
+-- FIFO_0_DATA_OUT => FIFO_0_DATA_OUT,\r
+ FIFO_0_DATA_OUT(39 downto 14) => ADC_0_STATUS_OUT,\r
+ FIFO_0_DATA_OUT(13 downto 0) => ADC_0_DATA_OUT,\r
+ FIFO_1_DATA_OUT => FIFO_1_DATA_OUT,\r
+ FIFO_2_DATA_OUT => open,\r
+ FIFO_3_DATA_OUT => open,\r
+ FIFO_4_DATA_OUT => open,\r
+ FIFO_5_DATA_OUT => open,\r
+ FIFO_6_DATA_OUT => open,\r
+ FIFO_7_DATA_OUT => open,\r
+ FIFO_8_DATA_OUT => open,\r
+ FIFO_9_DATA_OUT => open,\r
+ FIFO_10_DATA_OUT => open,\r
+ FIFO_11_DATA_OUT => open,\r
+ FIFO_12_DATA_OUT => open,\r
+ FIFO_13_DATA_OUT => open,\r
+ FIFO_14_DATA_OUT => open,\r
+ FIFO_15_DATA_OUT => open,\r
+ FIFO_WE_OUT => FIFO_WE_OUT,\r
+ FIFO_DONE_OUT => FIFO_DONE_OUT,\r
+ DBG_BSM_OUT => DBG_BSM_OUT,\r
+ DBG_OUT => DBG_OUT\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+-- Delay the BUF and PED address reaction\r
+THE_ADDR_DELAY: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ buf_addr <= buf_addr_out;\r
+ thr_addr <= thr_addr_out;\r
+ ped_addr <= ped_addr_out;\r
+ end if;\r
+end process THE_ADDR_DELAY;\r
+\r
+\r
+-- The real testbench\r
+TESTBENCH: process\r
+begin\r
+ -- Setup signal\r
+ reset_in <= '0';\r
+ verbose_in <= '0';\r
+ dhdr_buf_full_in <= '0';\r
+ eds_data_in <= (others => '0'); \r
+ eds_avail_in <= '0';\r
+ buf_start_in <= (others => '0'); \r
+ buf_tick_in <= (others => '0');\r
+ -- Buffer level information: 7 -> good, 6 -> broken, 5 -> ignore, rest LEVEL\r
+ buf_0_data_in(37 downto 30) <= x"80"; -- good\r
+ buf_1_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_4_data_in(37 downto 30) <= x"40"; -- broken!!!\r
+ -- Buffer frame information: 8 -> APV error, [7:0] row\r
+ buf_0_data_in(29 downto 18) <= x"011"; -- row 0x11, no error\r
+ buf_1_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_4_data_in(29 downto 18) <= x"0aa"; --\r
+ -- Buffer data\r
+ buf_0_data_in(17 downto 14) <= x"0";\r
+ buf_1_data_in(17 downto 14) <= x"0"; buf_1_data_in(13 downto 0) <= "00000000000000";\r
+ buf_4_data_in(17 downto 14) <= x"0"; buf_4_data_in(13 downto 0) <= "00000000000000";\r
+ -- Pedestal data\r
+ -- Threshold data\r
+-- thr_0_data_in <= "00" & x"0000";\r
+ thr_1_data_in <= "00" & x"0000";\r
+ thr_4_data_in <= "00" & x"0000";\r
+\r
+ -- Reset\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "000" -> RAW128\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee00";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"41"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 600 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+\r
+\r
+ -- Tests may start now\r
+ ----------------------------------------------------------------\r
+ -- "000" -> RAW128\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee00";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 600 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "001" -> PED128\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee01";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 600 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "010" -> PED128THR\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee02";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 600 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "011" -> RAW64\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee03";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 600 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "100" -> NC64PED64\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee04";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 600 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "101" -> NC64\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee05";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 600 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "110" -> NC64GOOD\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee06";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 600 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "111" -> NC64THR\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee07";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 600 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- stay a while, stay forever!\r
+ wait; \r
+\r
+end process TESTBENCH; \r
+\r
+-- Data faker for "APV 0"...\r
+BUF_0_DATA_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ case buf_addr is\r
+ when "0000000" => buf_0_data_in(13 downto 0) <= "00" & x"44b";\r
+ when "0000001" => buf_0_data_in(13 downto 0) <= "00" & x"474"; \r
+ when "0000010" => buf_0_data_in(13 downto 0) <= "00" & x"462"; \r
+ when "0000011" => buf_0_data_in(13 downto 0) <= "00" & x"45f"; \r
+-- when "0000100" => buf_0_data_in(13 downto 0) <= "00" & x"44c";\r
+ when "0000100" => buf_0_data_in(13 downto 0) <= "01" & x"111"; -- physical UNDERFLOW\r
+ when "0000101" => buf_0_data_in(13 downto 0) <= "00" & x"457"; \r
+ when "0000110" => buf_0_data_in(13 downto 0) <= "00" & x"476"; \r
+ when "0000111" => buf_0_data_in(13 downto 0) <= "00" & x"456"; \r
+ when "0001000" => buf_0_data_in(13 downto 0) <= "00" & x"450"; \r
+ when "0001001" => buf_0_data_in(13 downto 0) <= "00" & x"45c"; \r
+-- when "0001010" => buf_0_data_in(13 downto 0) <= "00" & x"46b"; \r
+ when "0001010" => buf_0_data_in(13 downto 0) <= "10" & x"eee"; -- physical OVERFLOW\r
+ when "0001011" => buf_0_data_in(13 downto 0) <= "00" & x"461"; \r
+ when "0001100" => buf_0_data_in(13 downto 0) <= "00" & x"466"; \r
+ when "0001101" => buf_0_data_in(13 downto 0) <= "00" & x"449"; \r
+ when "0001110" => buf_0_data_in(13 downto 0) <= "00" & x"450"; \r
+ when "0001111" => buf_0_data_in(13 downto 0) <= "00" & x"451"; \r
+ when "0010000" => buf_0_data_in(13 downto 0) <= "00" & x"432"; \r
+-- when "0010001" => buf_0_data_in(13 downto 0) <= "00" & x"459"; \r
+ when "0010001" => buf_0_data_in(13 downto 0) <= "01" & x"111"; -- correction UNDERFLOW \r
+ when "0010010" => buf_0_data_in(13 downto 0) <= "00" & x"45c"; \r
+ when "0010011" => buf_0_data_in(13 downto 0) <= "00" & x"430"; \r
+ when "0010100" => buf_0_data_in(13 downto 0) <= "00" & x"42f"; \r
+ when "0010101" => buf_0_data_in(13 downto 0) <= "00" & x"452"; \r
+ when "0010110" => buf_0_data_in(13 downto 0) <= "00" & x"43a"; \r
+-- when "0010111" => buf_0_data_in(13 downto 0) <= "00" & x"431"; \r
+ when "0010111" => buf_0_data_in(13 downto 0) <= "10" & x"eee"; -- correction OVERFLOW\r
+ when "0011000" => buf_0_data_in(13 downto 0) <= "00" & x"42b"; \r
+ when "0011001" => buf_0_data_in(13 downto 0) <= "00" & x"443"; \r
+ when "0011010" => buf_0_data_in(13 downto 0) <= "00" & x"424"; \r
+ when "0011011" => buf_0_data_in(13 downto 0) <= "00" & x"436"; \r
+ when "0011100" => buf_0_data_in(13 downto 0) <= "00" & x"45e"; \r
+ when "0011101" => buf_0_data_in(13 downto 0) <= "00" & x"453"; \r
+ when "0011110" => buf_0_data_in(13 downto 0) <= "00" & x"44c"; \r
+ when "0011111" => buf_0_data_in(13 downto 0) <= "00" & x"449"; \r
+ when "0100000" => buf_0_data_in(13 downto 0) <= "00" & x"40a"; \r
+ when "0100001" => buf_0_data_in(13 downto 0) <= "00" & x"43f"; \r
+-- when "0100010" => buf_0_data_in(13 downto 0) <= "00" & x"411"; \r
+ when "0100010" => buf_0_data_in(13 downto 0) <= "00" & x"411"; -- physical OFF \r
+ when "0100011" => buf_0_data_in(13 downto 0) <= "00" & x"455"; \r
+ when "0100100" => buf_0_data_in(13 downto 0) <= "00" & x"44b"; \r
+ when "0100101" => buf_0_data_in(13 downto 0) <= "00" & x"431"; \r
+ when "0100110" => buf_0_data_in(13 downto 0) <= "00" & x"425"; \r
+ when "0100111" => buf_0_data_in(13 downto 0) <= "00" & x"44a"; \r
+ when "0101000" => buf_0_data_in(13 downto 0) <= "00" & x"442"; \r
+ when "0101001" => buf_0_data_in(13 downto 0) <= "00" & x"446"; \r
+ when "0101010" => buf_0_data_in(13 downto 0) <= "00" & x"43e"; \r
+ when "0101011" => buf_0_data_in(13 downto 0) <= "00" & x"441"; \r
+ when "0101100" => buf_0_data_in(13 downto 0) <= "00" & x"45b"; \r
+ when "0101101" => buf_0_data_in(13 downto 0) <= "00" & x"44e"; \r
+ when "0101110" => buf_0_data_in(13 downto 0) <= "00" & x"452"; \r
+-- when "0101111" => buf_0_data_in(13 downto 0) <= "00" & x"469"; \r
+ when "0101111" => buf_0_data_in(13 downto 0) <= "00" & x"469"; -- correction OFF\r
+ when "0110000" => buf_0_data_in(13 downto 0) <= "00" & x"456"; \r
+ when "0110001" => buf_0_data_in(13 downto 0) <= "00" & x"45b"; \r
+ when "0110010" => buf_0_data_in(13 downto 0) <= "00" & x"482"; \r
+ when "0110011" => buf_0_data_in(13 downto 0) <= "00" & x"461"; \r
+ when "0110100" => buf_0_data_in(13 downto 0) <= "00" & x"444"; \r
+ when "0110101" => buf_0_data_in(13 downto 0) <= "00" & x"458"; \r
+ when "0110110" => buf_0_data_in(13 downto 0) <= "00" & x"446"; \r
+ when "0110111" => buf_0_data_in(13 downto 0) <= "00" & x"475"; \r
+ when "0111000" => buf_0_data_in(13 downto 0) <= "00" & x"447"; \r
+ when "0111001" => buf_0_data_in(13 downto 0) <= "00" & x"44f"; \r
+ when "0111010" => buf_0_data_in(13 downto 0) <= "00" & x"433"; \r
+ when "0111011" => buf_0_data_in(13 downto 0) <= "00" & x"470"; \r
+ when "0111100" => buf_0_data_in(13 downto 0) <= "00" & x"46d"; \r
+ when "0111101" => buf_0_data_in(13 downto 0) <= "00" & x"45e"; \r
+ when "0111110" => buf_0_data_in(13 downto 0) <= "00" & x"439"; \r
+ when "0111111" => buf_0_data_in(13 downto 0) <= "00" & x"45a"; \r
+ when "1000000" => buf_0_data_in(13 downto 0) <= "00" & x"43b"; \r
+ when "1000001" => buf_0_data_in(13 downto 0) <= "00" & x"42a"; \r
+ when "1000010" => buf_0_data_in(13 downto 0) <= "00" & x"430"; \r
+ when "1000011" => buf_0_data_in(13 downto 0) <= "00" & x"444"; \r
+ when "1000100" => buf_0_data_in(13 downto 0) <= "00" & x"42b"; \r
+ when "1000101" => buf_0_data_in(13 downto 0) <= "00" & x"42b"; \r
+ when "1000110" => buf_0_data_in(13 downto 0) <= "00" & x"403"; \r
+ when "1000111" => buf_0_data_in(13 downto 0) <= "00" & x"429"; \r
+ when "1001000" => buf_0_data_in(13 downto 0) <= "00" & x"3f4"; \r
+ when "1001001" => buf_0_data_in(13 downto 0) <= "00" & x"41b"; \r
+ when "1001010" => buf_0_data_in(13 downto 0) <= "00" & x"42f"; \r
+ when "1001011" => buf_0_data_in(13 downto 0) <= "00" & x"434"; \r
+ when "1001100" => buf_0_data_in(13 downto 0) <= "00" & x"40a"; \r
+ when "1001101" => buf_0_data_in(13 downto 0) <= "00" & x"416"; \r
+ when "1001110" => buf_0_data_in(13 downto 0) <= "00" & x"412"; \r
+ when "1001111" => buf_0_data_in(13 downto 0) <= "00" & x"418"; \r
+ when "1010000" => buf_0_data_in(13 downto 0) <= "00" & x"411"; \r
+ when "1010001" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; \r
+ when "1010010" => buf_0_data_in(13 downto 0) <= "00" & x"4d6"; \r
+ when "1010011" => buf_0_data_in(13 downto 0) <= "00" & x"40d"; \r
+ when "1010100" => buf_0_data_in(13 downto 0) <= "00" & x"3ec"; \r
+ when "1010101" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; \r
+ when "1010110" => buf_0_data_in(13 downto 0) <= "00" & x"419"; \r
+ when "1010111" => buf_0_data_in(13 downto 0) <= "00" & x"40d"; \r
+ when "1011000" => buf_0_data_in(13 downto 0) <= "00" & x"3f1"; \r
+ when "1011001" => buf_0_data_in(13 downto 0) <= "00" & x"3fa"; \r
+ when "1011010" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; \r
+ when "1011011" => buf_0_data_in(13 downto 0) <= "00" & x"408"; \r
+ when "1011100" => buf_0_data_in(13 downto 0) <= "00" & x"3ee"; \r
+ when "1011101" => buf_0_data_in(13 downto 0) <= "00" & x"3fd"; \r
+ when "1011110" => buf_0_data_in(13 downto 0) <= "00" & x"41b"; \r
+ when "1011111" => buf_0_data_in(13 downto 0) <= "00" & x"3f3"; \r
+ when "1100000" => buf_0_data_in(13 downto 0) <= "00" & x"3b2"; \r
+ when "1100001" => buf_0_data_in(13 downto 0) <= "00" & x"3d6"; \r
+ when "1100010" => buf_0_data_in(13 downto 0) <= "00" & x"3f2"; \r
+ when "1100011" => buf_0_data_in(13 downto 0) <= "00" & x"3f2"; \r
+ when "1100100" => buf_0_data_in(13 downto 0) <= "00" & x"40d"; \r
+ when "1100101" => buf_0_data_in(13 downto 0) <= "00" & x"3e4"; \r
+ when "1100110" => buf_0_data_in(13 downto 0) <= "00" & x"902"; \r
+ when "1100111" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; \r
+ when "1101000" => buf_0_data_in(13 downto 0) <= "00" & x"3d2"; \r
+ when "1101001" => buf_0_data_in(13 downto 0) <= "00" & x"3ef"; \r
+ when "1101010" => buf_0_data_in(13 downto 0) <= "00" & x"490"; \r
+ when "1101011" => buf_0_data_in(13 downto 0) <= "00" & x"402"; \r
+ when "1101100" => buf_0_data_in(13 downto 0) <= "00" & x"3bd"; \r
+ when "1101101" => buf_0_data_in(13 downto 0) <= "00" & x"3d1"; \r
+ when "1101110" => buf_0_data_in(13 downto 0) <= "00" & x"497"; \r
+ when "1101111" => buf_0_data_in(13 downto 0) <= "00" & x"3d2"; \r
+ when "1110000" => buf_0_data_in(13 downto 0) <= "00" & x"3b7"; \r
+ when "1110001" => buf_0_data_in(13 downto 0) <= "00" & x"3da"; \r
+ when "1110010" => buf_0_data_in(13 downto 0) <= "00" & x"4bd"; \r
+ when "1110011" => buf_0_data_in(13 downto 0) <= "00" & x"3c9"; \r
+ when "1110100" => buf_0_data_in(13 downto 0) <= "00" & x"3ba"; \r
+ when "1110101" => buf_0_data_in(13 downto 0) <= "00" & x"3c9"; \r
+ when "1110110" => buf_0_data_in(13 downto 0) <= "00" & x"4e9"; \r
+ when "1110111" => buf_0_data_in(13 downto 0) <= "00" & x"3cc"; \r
+ when "1111000" => buf_0_data_in(13 downto 0) <= "00" & x"3e4"; \r
+ when "1111001" => buf_0_data_in(13 downto 0) <= "00" & x"3b2"; \r
+ when "1111010" => buf_0_data_in(13 downto 0) <= "10" & x"edc"; -- real physical OVERFLOW\r
+ when "1111011" => buf_0_data_in(13 downto 0) <= "00" & x"3c4"; \r
+ when "1111100" => buf_0_data_in(13 downto 0) <= "00" & x"3e6"; \r
+ when "1111101" => buf_0_data_in(13 downto 0) <= "00" & x"3f0"; \r
+ when "1111110" => buf_0_data_in(13 downto 0) <= "00" & x"896"; \r
+ when "1111111" => buf_0_data_in(13 downto 0) <= "00" & x"402"; \r
+ when others => buf_0_data_in(13 downto 0) <= "00" & x"fff"; \r
+ end case;\r
+ end if;\r
+end process BUF_0_DATA_PROC;\r
+\r
+\r
+BUF_0_PED_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ case ped_addr is\r
+ when "0000000" => ped_0_data_in <= "00" & x"0485";\r
+ when "0000001" => ped_0_data_in <= "00" & x"148b"; \r
+ when "0000010" => ped_0_data_in <= "00" & x"2466"; \r
+ when "0000011" => ped_0_data_in <= "00" & x"3479"; \r
+-- when "0000100" => ped_0_data_in <= "00" & x"446e";\r
+ when "0000100" => ped_0_data_in <= "00" & x"446e"; -- physical UNDERFLOW\r
+ when "0000101" => ped_0_data_in <= "00" & x"5470"; \r
+ when "0000110" => ped_0_data_in <= "00" & x"647c"; \r
+ when "0000111" => ped_0_data_in <= "00" & x"7472"; \r
+ when "0001000" => ped_0_data_in <= "00" & x"0472"; \r
+ when "0001001" => ped_0_data_in <= "00" & x"1478"; \r
+-- when "0001010" => ped_0_data_in <= "00" & x"247f"; \r
+ when "0001010" => ped_0_data_in <= "00" & x"247f"; -- physical OVERFLOW\r
+ when "0001011" => ped_0_data_in <= "00" & x"3480"; \r
+ when "0001100" => ped_0_data_in <= "00" & x"4479"; \r
+ when "0001101" => ped_0_data_in <= "00" & x"5464"; \r
+ when "0001110" => ped_0_data_in <= "00" & x"645c"; \r
+ when "0001111" => ped_0_data_in <= "00" & x"7464"; \r
+ when "0010000" => ped_0_data_in <= "00" & x"045a"; \r
+-- when "0010001" => ped_0_data_in <= "00" & x"146f"; \r
+ when "0010001" => ped_0_data_in <= "00" & x"146f"; -- correction UNDERFLOW \r
+ when "0010010" => ped_0_data_in <= "00" & x"245c"; \r
+ when "0010011" => ped_0_data_in <= "00" & x"3445"; \r
+ when "0010100" => ped_0_data_in <= "00" & x"4448"; \r
+ when "0010101" => ped_0_data_in <= "00" & x"546e"; \r
+ when "0010110" => ped_0_data_in <= "00" & x"6450"; \r
+-- when "0010111" => ped_0_data_in <= "00" & x"7448"; \r
+ when "0010111" => ped_0_data_in <= "00" & x"7448"; -- correction OVERFLOW\r
+ when "0011000" => ped_0_data_in <= "00" & x"044d"; \r
+ when "0011001" => ped_0_data_in <= "00" & x"145c"; \r
+ when "0011010" => ped_0_data_in <= "00" & x"243b"; \r
+ when "0011011" => ped_0_data_in <= "00" & x"345a"; \r
+ when "0011100" => ped_0_data_in <= "00" & x"4469"; \r
+ when "0011101" => ped_0_data_in <= "00" & x"546f"; \r
+ when "0011110" => ped_0_data_in <= "00" & x"6455"; \r
+ when "0011111" => ped_0_data_in <= "00" & x"7463"; \r
+ when "0100000" => ped_0_data_in <= "00" & x"0429"; \r
+ when "0100001" => ped_0_data_in <= "00" & x"145b"; \r
+-- when "0100010" => ped_0_data_in <= "00" & x"2435"; \r
+ when "0100010" => ped_0_data_in <= "01" & x"2435"; -- physical OFF \r
+ when "0100011" => ped_0_data_in <= "00" & x"346f"; \r
+ when "0100100" => ped_0_data_in <= "00" & x"4463"; \r
+ when "0100101" => ped_0_data_in <= "00" & x"5454"; \r
+ when "0100110" => ped_0_data_in <= "00" & x"6452"; \r
+ when "0100111" => ped_0_data_in <= "00" & x"746e"; \r
+ when "0101000" => ped_0_data_in <= "00" & x"0469"; \r
+ when "0101001" => ped_0_data_in <= "00" & x"1462"; \r
+ when "0101010" => ped_0_data_in <= "00" & x"2464"; \r
+ when "0101011" => ped_0_data_in <= "00" & x"345e"; \r
+ when "0101100" => ped_0_data_in <= "00" & x"4469"; \r
+ when "0101101" => ped_0_data_in <= "00" & x"5469"; \r
+ when "0101110" => ped_0_data_in <= "00" & x"646d"; \r
+-- when "0101111" => ped_0_data_in <= "00" & x"7485"; \r
+ when "0101111" => ped_0_data_in <= "01" & x"7485"; -- correction OFF\r
+ when "0110000" => ped_0_data_in <= "00" & x"0478"; \r
+ when "0110001" => ped_0_data_in <= "00" & x"147d"; \r
+ when "0110010" => ped_0_data_in <= "00" & x"2468"; \r
+ when "0110011" => ped_0_data_in <= "00" & x"3480"; \r
+ when "0110100" => ped_0_data_in <= "00" & x"447d"; \r
+ when "0110101" => ped_0_data_in <= "00" & x"5480"; \r
+ when "0110110" => ped_0_data_in <= "00" & x"6468"; \r
+ when "0110111" => ped_0_data_in <= "00" & x"7496"; \r
+ when "0111000" => ped_0_data_in <= "00" & x"0471"; \r
+ when "0111001" => ped_0_data_in <= "00" & x"1474"; \r
+ when "0111010" => ped_0_data_in <= "00" & x"246b"; \r
+ when "0111011" => ped_0_data_in <= "00" & x"349b"; \r
+ when "0111100" => ped_0_data_in <= "00" & x"4499"; \r
+ when "0111101" => ped_0_data_in <= "00" & x"5484"; \r
+ when "0111110" => ped_0_data_in <= "00" & x"646d"; \r
+ when "0111111" => ped_0_data_in <= "00" & x"7486"; \r
+ when "1000000" => ped_0_data_in <= "00" & x"048e"; \r
+ when "1000001" => ped_0_data_in <= "00" & x"146e"; \r
+ when "1000010" => ped_0_data_in <= "00" & x"2488"; \r
+ when "1000011" => ped_0_data_in <= "00" & x"3491"; \r
+ when "1000100" => ped_0_data_in <= "00" & x"4487"; \r
+ when "1000101" => ped_0_data_in <= "00" & x"5476"; \r
+ when "1000110" => ped_0_data_in <= "00" & x"6453"; \r
+ when "1000111" => ped_0_data_in <= "00" & x"7484"; \r
+ when "1001000" => ped_0_data_in <= "00" & x"0452"; \r
+ when "1001001" => ped_0_data_in <= "00" & x"146f"; \r
+ when "1001010" => ped_0_data_in <= "00" & x"248d"; \r
+ when "1001011" => ped_0_data_in <= "00" & x"3486"; \r
+ when "1001100" => ped_0_data_in <= "00" & x"445c"; \r
+ when "1001101" => ped_0_data_in <= "00" & x"5475"; \r
+ when "1001110" => ped_0_data_in <= "00" & x"6476"; \r
+ when "1001111" => ped_0_data_in <= "00" & x"7475"; \r
+ when "1010000" => ped_0_data_in <= "00" & x"0472"; \r
+ when "1010001" => ped_0_data_in <= "00" & x"146f"; \r
+ when "1010010" => ped_0_data_in <= "00" & x"244c"; \r
+ when "1010011" => ped_0_data_in <= "00" & x"3479"; \r
+ when "1010100" => ped_0_data_in <= "00" & x"4469"; \r
+ when "1010101" => ped_0_data_in <= "00" & x"547f"; \r
+ when "1010110" => ped_0_data_in <= "00" & x"6478"; \r
+ when "1010111" => ped_0_data_in <= "00" & x"7478"; \r
+ when "1011000" => ped_0_data_in <= "00" & x"0472"; \r
+ when "1011001" => ped_0_data_in <= "00" & x"146c"; \r
+ when "1011010" => ped_0_data_in <= "00" & x"2478"; \r
+ when "1011011" => ped_0_data_in <= "00" & x"3481"; \r
+ when "1011100" => ped_0_data_in <= "00" & x"447a"; \r
+ when "1011101" => ped_0_data_in <= "00" & x"547f"; \r
+ when "1011110" => ped_0_data_in <= "00" & x"649f"; \r
+ when "1011111" => ped_0_data_in <= "00" & x"746f"; \r
+ when "1100000" => ped_0_data_in <= "00" & x"0443"; \r
+ when "1100001" => ped_0_data_in <= "00" & x"145d"; \r
+ when "1100010" => ped_0_data_in <= "00" & x"246f"; \r
+ when "1100011" => ped_0_data_in <= "00" & x"3482"; \r
+ when "1100100" => ped_0_data_in <= "00" & x"4498"; \r
+ when "1100101" => ped_0_data_in <= "00" & x"5483"; \r
+ when "1100110" => ped_0_data_in <= "00" & x"649b"; \r
+ when "1100111" => ped_0_data_in <= "00" & x"74a9"; \r
+ when "1101000" => ped_0_data_in <= "00" & x"0471"; \r
+ when "1101001" => ped_0_data_in <= "00" & x"1488"; \r
+ when "1101010" => ped_0_data_in <= "00" & x"249a"; \r
+ when "1101011" => ped_0_data_in <= "00" & x"349f"; \r
+ when "1101100" => ped_0_data_in <= "00" & x"4473"; \r
+ when "1101101" => ped_0_data_in <= "00" & x"5479"; \r
+ when "1101110" => ped_0_data_in <= "00" & x"648b"; \r
+ when "1101111" => ped_0_data_in <= "00" & x"747e"; \r
+ when "1110000" => ped_0_data_in <= "00" & x"0480"; \r
+ when "1110001" => ped_0_data_in <= "00" & x"1492"; \r
+ when "1110010" => ped_0_data_in <= "00" & x"2482"; \r
+ when "1110011" => ped_0_data_in <= "00" & x"3483"; \r
+ when "1110100" => ped_0_data_in <= "00" & x"447a"; \r
+ when "1110101" => ped_0_data_in <= "00" & x"548a"; \r
+ when "1110110" => ped_0_data_in <= "00" & x"6493"; \r
+ when "1110111" => ped_0_data_in <= "00" & x"7496"; \r
+ when "1111000" => ped_0_data_in <= "00" & x"0495"; \r
+ when "1111001" => ped_0_data_in <= "00" & x"1493"; \r
+ when "1111010" => ped_0_data_in <= "00" & x"2487"; -- real physical OVERFLOW\r
+ when "1111011" => ped_0_data_in <= "00" & x"3496"; \r
+ when "1111100" => ped_0_data_in <= "00" & x"449d"; \r
+ when "1111101" => ped_0_data_in <= "00" & x"54cb"; \r
+ when "1111110" => ped_0_data_in <= "00" & x"64b9"; \r
+ when "1111111" => ped_0_data_in <= "00" & x"74df"; \r
+ when others => ped_0_data_in <= "00" & x"ffff"; \r
+ end case;\r
+ end if;\r
+end process BUF_0_PED_PROC;\r
+\r
+\r
+-- Data faker for "APV 0"...\r
+BUF_0_THR_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ case thr_addr is\r
+-- when "0000000" => thr_0_data_in <= "00" & x"001e";\r
+ when "0000000" => thr_0_data_in <= "00" & x"ffff";\r
+ when "0000001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0000010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "0000011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0000100" => thr_0_data_in <= "00" & x"401e"; \r
+ when "0000101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0000110" => thr_0_data_in <= "00" & x"601b"; \r
+ when "0000111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0001000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "0001001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0001010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "0001011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0001100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "0001101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0001110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "0001111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0010000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "0010001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0010010" => thr_0_data_in <= "00" & x"2021"; \r
+ when "0010011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0010100" => thr_0_data_in <= "00" & x"402d"; \r
+ when "0010101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0010110" => thr_0_data_in <= "00" & x"602a"; \r
+ when "0010111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0011000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "0011001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0011010" => thr_0_data_in <= "00" & x"2021"; \r
+ when "0011011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0011100" => thr_0_data_in <= "00" & x"401e"; \r
+ when "0011101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0011110" => thr_0_data_in <= "00" & x"601b"; \r
+ when "0011111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0100000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "0100001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0100010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "0100011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0100100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "0100101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0100110" => thr_0_data_in <= "00" & x"601b"; \r
+ when "0100111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0101000" => thr_0_data_in <= "00" & x"001b"; \r
+ when "0101001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0101010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "0101011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0101100" => thr_0_data_in <= "00" & x"401e"; \r
+ when "0101101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0101110" => thr_0_data_in <= "00" & x"601b"; \r
+ when "0101111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0110000" => thr_0_data_in <= "00" & x"000f"; \r
+ when "0110001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0110010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "0110011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0110100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "0110101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0110110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "0110111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0111000" => thr_0_data_in <= "00" & x"0021"; \r
+ when "0111001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0111010" => thr_0_data_in <= "00" & x"2027"; \r
+ when "0111011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0111100" => thr_0_data_in <= "00" & x"400f"; \r
+ when "0111101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0111110" => thr_0_data_in <= "00" & x"6048"; \r
+ when "0111111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1000000" => thr_0_data_in <= "00" & x"0024"; \r
+ when "1000001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1000010" => thr_0_data_in <= "00" & x"2024"; \r
+ when "1000011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1000100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1000101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1000110" => thr_0_data_in <= "00" & x"6021"; \r
+ when "1000111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1001000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "1001001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1001010" => thr_0_data_in <= "00" & x"2021"; \r
+ when "1001011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1001100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1001101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1001110" => thr_0_data_in <= "00" & x"601b"; \r
+ when "1001111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1010000" => thr_0_data_in <= "00" & x"001b"; \r
+ when "1010001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1010010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "1010011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1010100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1010101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1010110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "1010111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1011000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "1011001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1011010" => thr_0_data_in <= "00" & x"2021"; \r
+ when "1011011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1011100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1011101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1011110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "1011111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1100000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "1100001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1100010" => thr_0_data_in <= "00" & x"2021"; \r
+ when "1100011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1100100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1100101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1100110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "1100111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1101000" => thr_0_data_in <= "00" & x"0021"; \r
+ when "1101001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1101010" => thr_0_data_in <= "00" & x"2027"; \r
+ when "1101011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1101100" => thr_0_data_in <= "00" & x"4024"; \r
+ when "1101101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1101110" => thr_0_data_in <= "00" & x"6021"; \r
+ when "1101111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1110000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "1110001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1110010" => thr_0_data_in <= "00" & x"2024"; \r
+ when "1110011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1110100" => thr_0_data_in <= "00" & x"400f"; \r
+ when "1110101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1110110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "1110111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1111000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "1111001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1111010" => thr_0_data_in <= "00" & x"2024"; \r
+ when "1111011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1111100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1111101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1111110" => thr_0_data_in <= "00" & x"6021"; \r
+ when "1111111" => thr_0_data_in <= "00" & x"700f"; \r
+ when others => thr_0_data_in <= "00" & x"ffff"; \r
+ end case;\r
+ end if;\r
+end process BUF_0_THR_PROC;\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT ped_corr_ctrl\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ EDS_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ EDS_AVAIL_IN : IN std_logic;\r
+ BUF_TICK_IN : IN std_logic_vector(15 downto 0);\r
+ BUF_START_IN : IN std_logic_vector(15 downto 0);\r
+ BUF_0_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_1_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_2_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_3_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_4_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_5_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_6_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_7_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_8_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_9_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_10_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_11_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_12_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_13_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_14_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_15_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ PED_0_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_1_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_2_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_3_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_4_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_5_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_6_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_7_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_8_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_9_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_10_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_11_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_12_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_13_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_14_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_15_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_0_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_1_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_2_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_3_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_4_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_5_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_6_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_7_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_8_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_9_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_10_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_11_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_12_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_13_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_14_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_15_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ EDS_DONE_OUT : OUT std_logic;\r
+ DHDR_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
+ DHDR_BUF_FULL_IN : IN std_logic;\r
+ DHDR_STORE_OUT : OUT std_logic;\r
+ PED_ADDR_OUT : OUT std_logic_vector(6 downto 0);\r
+ THR_ADDR_OUT : OUT std_logic_vector(6 downto 0);\r
+ BUF_ADDR_OUT : OUT std_logic_vector(6 downto 0);\r
+ BUF_DONE_OUT : OUT std_logic;\r
+ FIFO_START_OUT : OUT std_logic;\r
+ FIFO_0_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_WE_OUT : OUT std_logic_vector(15 downto 0);\r
+ FIFO_DONE_OUT : OUT std_logic;\r
+ DBG_BSM_OUT : OUT std_logic_vector(7 downto 0);\r
+ DBG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL EDS_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL EDS_AVAIL_IN : std_logic;\r
+ SIGNAL EDS_DONE_OUT : std_logic;\r
+ SIGNAL DHDR_DATA_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL DHDR_LENGTH_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL DHDR_BUF_FULL_IN : std_logic;\r
+ SIGNAL DHDR_STORE_OUT : std_logic;\r
+ SIGNAL BUF_ADDR_OUT : std_logic_vector(6 downto 0);\r
+ SIGNAL BUF_DONE_OUT : std_logic;\r
+ SIGNAL BUF_TICK_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL BUF_START_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL BUF_0_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_1_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_2_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_3_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_4_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_5_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_6_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_7_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_8_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_9_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_10_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_11_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_12_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_13_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_14_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_15_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL THR_ADDR_OUT : std_logic_vector(6 downto 0);\r
+ SIGNAL THR_0_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_1_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_2_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_3_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_4_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_5_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_6_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_7_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_8_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_9_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_10_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_11_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_12_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_13_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_14_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_15_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_ADDR_OUT : std_logic_vector(6 downto 0);\r
+ SIGNAL PED_0_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_1_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_2_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_3_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_4_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_5_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_6_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_7_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_8_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_9_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_10_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_11_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_12_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_13_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_14_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_15_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL FIFO_START_OUT : std_logic;\r
+ SIGNAL FIFO_0_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_1_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_2_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_3_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_4_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_5_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_6_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_7_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_8_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_9_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_10_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_11_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_12_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_13_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_14_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_15_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_WE_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL FIFO_DONE_OUT : std_logic;\r
+ SIGNAL DBG_BSM_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL DBG_OUT : std_logic_vector(15 downto 0);\r
+\r
+\r
+ SIGNAL BUF_ADDR : std_logic_vector(6 downto 0);\r
+ SIGNAL PED_ADDR : std_logic_vector(6 downto 0);\r
+ SIGNAL THR_ADDR : std_logic_vector(6 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: ped_corr_ctrl PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ EDS_DATA_IN => EDS_DATA_IN,\r
+ EDS_AVAIL_IN => EDS_AVAIL_IN,\r
+ EDS_DONE_OUT => EDS_DONE_OUT,\r
+ DHDR_DATA_OUT => DHDR_DATA_OUT,\r
+ DHDR_LENGTH_OUT => DHDR_LENGTH_OUT,\r
+ DHDR_BUF_FULL_IN => DHDR_BUF_FULL_IN,\r
+ DHDR_STORE_OUT => DHDR_STORE_OUT,\r
+ BUF_ADDR_OUT => BUF_ADDR_OUT,\r
+ BUF_DONE_OUT => BUF_DONE_OUT,\r
+ BUF_TICK_IN => BUF_TICK_IN,\r
+ BUF_START_IN => BUF_START_IN,\r
+ BUF_0_DATA_IN => BUF_0_DATA_IN,\r
+ BUF_1_DATA_IN => BUF_1_DATA_IN,\r
+ BUF_2_DATA_IN => BUF_2_DATA_IN,\r
+ BUF_3_DATA_IN => BUF_3_DATA_IN,\r
+ BUF_4_DATA_IN => BUF_4_DATA_IN,\r
+ BUF_5_DATA_IN => BUF_5_DATA_IN,\r
+ BUF_6_DATA_IN => BUF_6_DATA_IN,\r
+ BUF_7_DATA_IN => BUF_7_DATA_IN,\r
+ BUF_8_DATA_IN => BUF_8_DATA_IN,\r
+ BUF_9_DATA_IN => BUF_9_DATA_IN,\r
+ BUF_10_DATA_IN => BUF_10_DATA_IN,\r
+ BUF_11_DATA_IN => BUF_11_DATA_IN,\r
+ BUF_12_DATA_IN => BUF_12_DATA_IN,\r
+ BUF_13_DATA_IN => BUF_13_DATA_IN,\r
+ BUF_14_DATA_IN => BUF_14_DATA_IN,\r
+ BUF_15_DATA_IN => BUF_15_DATA_IN,\r
+ PED_ADDR_OUT => PED_ADDR_OUT,\r
+ PED_0_DATA_IN => PED_0_DATA_IN,\r
+ PED_1_DATA_IN => PED_1_DATA_IN,\r
+ PED_2_DATA_IN => PED_2_DATA_IN,\r
+ PED_3_DATA_IN => PED_3_DATA_IN,\r
+ PED_4_DATA_IN => PED_4_DATA_IN,\r
+ PED_5_DATA_IN => PED_5_DATA_IN,\r
+ PED_6_DATA_IN => PED_6_DATA_IN,\r
+ PED_7_DATA_IN => PED_7_DATA_IN,\r
+ PED_8_DATA_IN => PED_8_DATA_IN,\r
+ PED_9_DATA_IN => PED_9_DATA_IN,\r
+ PED_10_DATA_IN => PED_10_DATA_IN,\r
+ PED_11_DATA_IN => PED_11_DATA_IN,\r
+ PED_12_DATA_IN => PED_12_DATA_IN,\r
+ PED_13_DATA_IN => PED_13_DATA_IN,\r
+ PED_14_DATA_IN => PED_14_DATA_IN,\r
+ PED_15_DATA_IN => PED_15_DATA_IN,\r
+ THR_ADDR_OUT => THR_ADDR_OUT,\r
+ THR_0_DATA_IN => THR_0_DATA_IN,\r
+ THR_1_DATA_IN => THR_1_DATA_IN,\r
+ THR_2_DATA_IN => THR_2_DATA_IN,\r
+ THR_3_DATA_IN => THR_3_DATA_IN,\r
+ THR_4_DATA_IN => THR_4_DATA_IN,\r
+ THR_5_DATA_IN => THR_5_DATA_IN,\r
+ THR_6_DATA_IN => THR_6_DATA_IN,\r
+ THR_7_DATA_IN => THR_7_DATA_IN,\r
+ THR_8_DATA_IN => THR_8_DATA_IN,\r
+ THR_9_DATA_IN => THR_9_DATA_IN,\r
+ THR_10_DATA_IN => THR_10_DATA_IN,\r
+ THR_11_DATA_IN => THR_11_DATA_IN,\r
+ THR_12_DATA_IN => THR_12_DATA_IN,\r
+ THR_13_DATA_IN => THR_13_DATA_IN,\r
+ THR_14_DATA_IN => THR_14_DATA_IN,\r
+ THR_15_DATA_IN => THR_15_DATA_IN,\r
+ FIFO_START_OUT => FIFO_START_OUT,\r
+ FIFO_0_DATA_OUT => FIFO_0_DATA_OUT,\r
+ FIFO_1_DATA_OUT => FIFO_1_DATA_OUT,\r
+ FIFO_2_DATA_OUT => FIFO_2_DATA_OUT,\r
+ FIFO_3_DATA_OUT => FIFO_3_DATA_OUT,\r
+ FIFO_4_DATA_OUT => FIFO_4_DATA_OUT,\r
+ FIFO_5_DATA_OUT => FIFO_5_DATA_OUT,\r
+ FIFO_6_DATA_OUT => FIFO_6_DATA_OUT,\r
+ FIFO_7_DATA_OUT => FIFO_7_DATA_OUT,\r
+ FIFO_8_DATA_OUT => FIFO_8_DATA_OUT,\r
+ FIFO_9_DATA_OUT => FIFO_9_DATA_OUT,\r
+ FIFO_10_DATA_OUT => FIFO_10_DATA_OUT,\r
+ FIFO_11_DATA_OUT => FIFO_11_DATA_OUT,\r
+ FIFO_12_DATA_OUT => FIFO_12_DATA_OUT,\r
+ FIFO_13_DATA_OUT => FIFO_13_DATA_OUT,\r
+ FIFO_14_DATA_OUT => FIFO_14_DATA_OUT,\r
+ FIFO_15_DATA_OUT => FIFO_15_DATA_OUT,\r
+ FIFO_WE_OUT => FIFO_WE_OUT,\r
+ FIFO_DONE_OUT => FIFO_DONE_OUT,\r
+ DBG_BSM_OUT => DBG_BSM_OUT,\r
+ DBG_OUT => DBG_OUT\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+-- Delay the BUF and PED address reaction\r
+THE_ADDR_DELAY: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ buf_addr <= buf_addr_out;\r
+ thr_addr <= thr_addr_out;\r
+ ped_addr <= ped_addr_out;\r
+ end if;\r
+end process THE_ADDR_DELAY;\r
+\r
+\r
+-- The real testbench\r
+TESTBENCH: process\r
+begin\r
+ -- Setup signal\r
+ reset_in <= '0';\r
+ dhdr_buf_full_in <= '0';\r
+ eds_data_in <= (others => '0'); \r
+ eds_avail_in <= '0';\r
+ buf_start_in <= (others => '0'); \r
+ buf_tick_in <= (others => '0');\r
+ -- Buffer level information: 7 -> good, 6 -> broken, 5 -> ignore, rest LEVEL\r
+ buf_0_data_in(37 downto 30) <= x"80"; -- good\r
+ buf_1_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_2_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_3_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_4_data_in(37 downto 30) <= x"40"; -- broken!!!\r
+ buf_5_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_6_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_7_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_8_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_9_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_10_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_11_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_12_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_13_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_14_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_15_data_in(37 downto 30) <= x"20"; -- ignore\r
+ -- Buffer frame information: 8 -> APV error, [7:0] row\r
+ buf_0_data_in(29 downto 18) <= x"011"; -- row 0x11, no error\r
+ buf_1_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_2_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_3_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_4_data_in(29 downto 18) <= x"0aa"; --\r
+ buf_5_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_6_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_7_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_8_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_9_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_10_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_11_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_12_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_13_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_14_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_15_data_in(29 downto 18) <= x"0ee"; --\r
+ -- Buffer data\r
+ buf_0_data_in(17 downto 14) <= x"0";\r
+ buf_1_data_in(17 downto 14) <= x"0"; buf_1_data_in(13 downto 0) <= "00000000000000";\r
+ buf_2_data_in(17 downto 14) <= x"0"; buf_2_data_in(13 downto 0) <= "00000000000000";\r
+ buf_3_data_in(17 downto 14) <= x"0"; buf_3_data_in(13 downto 0) <= "00000000000000";\r
+ buf_4_data_in(17 downto 14) <= x"0"; buf_4_data_in(13 downto 0) <= "00000000000000";\r
+ buf_5_data_in(17 downto 14) <= x"0"; buf_5_data_in(13 downto 0) <= "00000000000000";\r
+ buf_6_data_in(17 downto 14) <= x"0"; buf_6_data_in(13 downto 0) <= "00000000000000";\r
+ buf_7_data_in(17 downto 14) <= x"0"; buf_7_data_in(13 downto 0) <= "00000000000000";\r
+ buf_8_data_in(17 downto 14) <= x"0"; buf_8_data_in(13 downto 0) <= "00000000000000";\r
+ buf_9_data_in(17 downto 14) <= x"0"; buf_9_data_in(13 downto 0) <= "00000000000000";\r
+ buf_10_data_in(17 downto 14) <= x"0"; buf_10_data_in(13 downto 0) <= "00000000000000";\r
+ buf_11_data_in(17 downto 14) <= x"0"; buf_11_data_in(13 downto 0) <= "00000000000000";\r
+ buf_12_data_in(17 downto 14) <= x"0"; buf_12_data_in(13 downto 0) <= "00000000000000";\r
+ buf_13_data_in(17 downto 14) <= x"0"; buf_13_data_in(13 downto 0) <= "00000000000000";\r
+ buf_14_data_in(17 downto 14) <= x"0"; buf_14_data_in(13 downto 0) <= "00000000000000";\r
+ buf_15_data_in(17 downto 14) <= x"0"; buf_15_data_in(13 downto 0) <= "00000000000000";\r
+ -- Pedestal data\r
+-- ped_0_data_in <= "00" & x"0000";\r
+ ped_1_data_in <= "00" & x"0000";\r
+ ped_2_data_in <= "00" & x"0000";\r
+ ped_3_data_in <= "00" & x"0000";\r
+ ped_4_data_in <= "00" & x"0000";\r
+ ped_5_data_in <= "00" & x"0000";\r
+ ped_6_data_in <= "00" & x"0000";\r
+ ped_7_data_in <= "00" & x"0000";\r
+ ped_8_data_in <= "00" & x"0000";\r
+ ped_9_data_in <= "00" & x"0000";\r
+ ped_10_data_in <= "00" & x"0000";\r
+ ped_11_data_in <= "00" & x"0000";\r
+ ped_12_data_in <= "00" & x"0000";\r
+ ped_13_data_in <= "00" & x"0000";\r
+ ped_14_data_in <= "00" & x"0000";\r
+ ped_15_data_in <= "00" & x"0000";\r
+ -- Threshold data\r
+-- thr_0_data_in <= "00" & x"0000";\r
+ thr_1_data_in <= "00" & x"0000";\r
+ thr_2_data_in <= "00" & x"0000";\r
+ thr_3_data_in <= "00" & x"0000";\r
+ thr_4_data_in <= "00" & x"0000";\r
+ thr_5_data_in <= "00" & x"0000";\r
+ thr_6_data_in <= "00" & x"0000";\r
+ thr_7_data_in <= "00" & x"0000";\r
+ thr_8_data_in <= "00" & x"0000";\r
+ thr_9_data_in <= "00" & x"0000";\r
+ thr_10_data_in <= "00" & x"0000";\r
+ thr_11_data_in <= "00" & x"0000";\r
+ thr_12_data_in <= "00" & x"0000";\r
+ thr_13_data_in <= "00" & x"0000";\r
+ thr_14_data_in <= "00" & x"0000";\r
+ thr_15_data_in <= "00" & x"0000";\r
+\r
+ -- Reset\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------------------------------\r
+ ----------------------------------------------------------------------------------------\r
+ ----------------------------------------------------------------------------------------\r
+ ----------------------------------------------------------------------------------------\r
+\r
+ ----------------------------------------------------------------\r
+ -- "000" -> RAW128\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee00";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"82"; \r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"83"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+\r
+ ----------------------------------------------------------------\r
+ -- "001" -> PED128\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee19";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"82"; \r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"83"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "010" -> PED128THR\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee22";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"82"; \r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"83"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------------------------------\r
+ ----------------------------------------------------------------------------------------\r
+ ----------------------------------------------------------------------------------------\r
+ ----------------------------------------------------------------------------------------\r
+ wait; \r
+\r
+ -- Tests may start now\r
+ ----------------------------------------------------------------\r
+ -- "000" -> RAW128\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee00";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "001" -> PED128\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee01";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "010" -> PED128THR\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee01";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "100" -> NC64PED64\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee01";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "101" -> NC64\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee01";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "110" -> NC64GOOD\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee01";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "111" -> NC64THR\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee01";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+\r
+\r
+\r
+\r
+ \r
+ -- stay a while, stay forever!\r
+ wait; \r
+end process TESTBENCH; \r
+\r
+-- Data faker for "APV 0"...\r
+BUF_0_DATA_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ case buf_addr is\r
+ when "0000000" => buf_0_data_in(13 downto 0) <= "00" & x"44b";\r
+ when "0000001" => buf_0_data_in(13 downto 0) <= "00" & x"474"; \r
+ when "0000010" => buf_0_data_in(13 downto 0) <= "00" & x"462"; \r
+ when "0000011" => buf_0_data_in(13 downto 0) <= "00" & x"45f"; \r
+-- when "0000100" => buf_0_data_in(13 downto 0) <= "00" & x"44c";\r
+ when "0000100" => buf_0_data_in(13 downto 0) <= "01" & x"111"; -- physical UNDERFLOW\r
+ when "0000101" => buf_0_data_in(13 downto 0) <= "00" & x"457"; \r
+ when "0000110" => buf_0_data_in(13 downto 0) <= "00" & x"476"; \r
+ when "0000111" => buf_0_data_in(13 downto 0) <= "00" & x"456"; \r
+ when "0001000" => buf_0_data_in(13 downto 0) <= "00" & x"450"; \r
+ when "0001001" => buf_0_data_in(13 downto 0) <= "00" & x"45c"; \r
+-- when "0001010" => buf_0_data_in(13 downto 0) <= "00" & x"46b"; \r
+ when "0001010" => buf_0_data_in(13 downto 0) <= "10" & x"eee"; -- physical OVERFLOW\r
+ when "0001011" => buf_0_data_in(13 downto 0) <= "00" & x"461"; \r
+ when "0001100" => buf_0_data_in(13 downto 0) <= "00" & x"466"; \r
+ when "0001101" => buf_0_data_in(13 downto 0) <= "00" & x"449"; \r
+ when "0001110" => buf_0_data_in(13 downto 0) <= "00" & x"450"; \r
+ when "0001111" => buf_0_data_in(13 downto 0) <= "00" & x"451"; \r
+ when "0010000" => buf_0_data_in(13 downto 0) <= "00" & x"432"; \r
+-- when "0010001" => buf_0_data_in(13 downto 0) <= "00" & x"459"; \r
+ when "0010001" => buf_0_data_in(13 downto 0) <= "01" & x"111"; -- correction UNDERFLOW \r
+ when "0010010" => buf_0_data_in(13 downto 0) <= "00" & x"45c"; \r
+ when "0010011" => buf_0_data_in(13 downto 0) <= "00" & x"430"; \r
+ when "0010100" => buf_0_data_in(13 downto 0) <= "00" & x"42f"; \r
+ when "0010101" => buf_0_data_in(13 downto 0) <= "00" & x"452"; \r
+ when "0010110" => buf_0_data_in(13 downto 0) <= "00" & x"43a"; \r
+-- when "0010111" => buf_0_data_in(13 downto 0) <= "00" & x"431"; \r
+ when "0010111" => buf_0_data_in(13 downto 0) <= "10" & x"eee"; -- correction OVERFLOW\r
+ when "0011000" => buf_0_data_in(13 downto 0) <= "00" & x"42b"; \r
+ when "0011001" => buf_0_data_in(13 downto 0) <= "00" & x"443"; \r
+ when "0011010" => buf_0_data_in(13 downto 0) <= "00" & x"424"; \r
+ when "0011011" => buf_0_data_in(13 downto 0) <= "00" & x"436"; \r
+ when "0011100" => buf_0_data_in(13 downto 0) <= "00" & x"45e"; \r
+ when "0011101" => buf_0_data_in(13 downto 0) <= "00" & x"453"; \r
+ when "0011110" => buf_0_data_in(13 downto 0) <= "00" & x"44c"; \r
+ when "0011111" => buf_0_data_in(13 downto 0) <= "00" & x"449"; \r
+ when "0100000" => buf_0_data_in(13 downto 0) <= "00" & x"40a"; \r
+ when "0100001" => buf_0_data_in(13 downto 0) <= "00" & x"43f"; \r
+-- when "0100010" => buf_0_data_in(13 downto 0) <= "00" & x"411"; \r
+ when "0100010" => buf_0_data_in(13 downto 0) <= "00" & x"411"; -- physical OFF \r
+ when "0100011" => buf_0_data_in(13 downto 0) <= "00" & x"455"; \r
+ when "0100100" => buf_0_data_in(13 downto 0) <= "00" & x"44b"; \r
+ when "0100101" => buf_0_data_in(13 downto 0) <= "00" & x"431"; \r
+ when "0100110" => buf_0_data_in(13 downto 0) <= "00" & x"425"; \r
+ when "0100111" => buf_0_data_in(13 downto 0) <= "00" & x"44a"; \r
+ when "0101000" => buf_0_data_in(13 downto 0) <= "00" & x"442"; \r
+ when "0101001" => buf_0_data_in(13 downto 0) <= "00" & x"446"; \r
+ when "0101010" => buf_0_data_in(13 downto 0) <= "00" & x"43e"; \r
+ when "0101011" => buf_0_data_in(13 downto 0) <= "00" & x"441"; \r
+ when "0101100" => buf_0_data_in(13 downto 0) <= "00" & x"45b"; \r
+ when "0101101" => buf_0_data_in(13 downto 0) <= "00" & x"44e"; \r
+ when "0101110" => buf_0_data_in(13 downto 0) <= "00" & x"452"; \r
+-- when "0101111" => buf_0_data_in(13 downto 0) <= "00" & x"469"; \r
+ when "0101111" => buf_0_data_in(13 downto 0) <= "00" & x"469"; -- correction OFF\r
+ when "0110000" => buf_0_data_in(13 downto 0) <= "00" & x"456"; \r
+ when "0110001" => buf_0_data_in(13 downto 0) <= "00" & x"45b"; \r
+ when "0110010" => buf_0_data_in(13 downto 0) <= "00" & x"482"; \r
+ when "0110011" => buf_0_data_in(13 downto 0) <= "00" & x"461"; \r
+ when "0110100" => buf_0_data_in(13 downto 0) <= "00" & x"444"; \r
+ when "0110101" => buf_0_data_in(13 downto 0) <= "00" & x"458"; \r
+ when "0110110" => buf_0_data_in(13 downto 0) <= "00" & x"446"; \r
+ when "0110111" => buf_0_data_in(13 downto 0) <= "00" & x"475"; \r
+ when "0111000" => buf_0_data_in(13 downto 0) <= "00" & x"447"; \r
+ when "0111001" => buf_0_data_in(13 downto 0) <= "00" & x"44f"; \r
+ when "0111010" => buf_0_data_in(13 downto 0) <= "00" & x"433"; \r
+ when "0111011" => buf_0_data_in(13 downto 0) <= "00" & x"470"; \r
+ when "0111100" => buf_0_data_in(13 downto 0) <= "00" & x"46d"; \r
+ when "0111101" => buf_0_data_in(13 downto 0) <= "00" & x"45e"; \r
+ when "0111110" => buf_0_data_in(13 downto 0) <= "00" & x"439"; \r
+ when "0111111" => buf_0_data_in(13 downto 0) <= "00" & x"45a"; \r
+ when "1000000" => buf_0_data_in(13 downto 0) <= "00" & x"43b"; \r
+ when "1000001" => buf_0_data_in(13 downto 0) <= "00" & x"42a"; \r
+ when "1000010" => buf_0_data_in(13 downto 0) <= "00" & x"430"; \r
+ when "1000011" => buf_0_data_in(13 downto 0) <= "00" & x"444"; \r
+ when "1000100" => buf_0_data_in(13 downto 0) <= "00" & x"42b"; \r
+ when "1000101" => buf_0_data_in(13 downto 0) <= "00" & x"42b"; \r
+ when "1000110" => buf_0_data_in(13 downto 0) <= "00" & x"403"; \r
+ when "1000111" => buf_0_data_in(13 downto 0) <= "00" & x"429"; \r
+ when "1001000" => buf_0_data_in(13 downto 0) <= "00" & x"3f4"; \r
+ when "1001001" => buf_0_data_in(13 downto 0) <= "00" & x"41b"; \r
+ when "1001010" => buf_0_data_in(13 downto 0) <= "00" & x"42f"; \r
+ when "1001011" => buf_0_data_in(13 downto 0) <= "00" & x"434"; \r
+ when "1001100" => buf_0_data_in(13 downto 0) <= "00" & x"40a"; \r
+ when "1001101" => buf_0_data_in(13 downto 0) <= "00" & x"416"; \r
+ when "1001110" => buf_0_data_in(13 downto 0) <= "00" & x"412"; \r
+ when "1001111" => buf_0_data_in(13 downto 0) <= "00" & x"418"; \r
+ when "1010000" => buf_0_data_in(13 downto 0) <= "00" & x"411"; \r
+ when "1010001" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; \r
+ when "1010010" => buf_0_data_in(13 downto 0) <= "00" & x"4d6"; \r
+ when "1010011" => buf_0_data_in(13 downto 0) <= "00" & x"40d"; \r
+ when "1010100" => buf_0_data_in(13 downto 0) <= "00" & x"3ec"; \r
+ when "1010101" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; \r
+ when "1010110" => buf_0_data_in(13 downto 0) <= "00" & x"419"; \r
+ when "1010111" => buf_0_data_in(13 downto 0) <= "00" & x"40d"; \r
+ when "1011000" => buf_0_data_in(13 downto 0) <= "00" & x"3f1"; \r
+ when "1011001" => buf_0_data_in(13 downto 0) <= "00" & x"3fa"; \r
+ when "1011010" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; \r
+ when "1011011" => buf_0_data_in(13 downto 0) <= "00" & x"408"; \r
+ when "1011100" => buf_0_data_in(13 downto 0) <= "00" & x"3ee"; \r
+ when "1011101" => buf_0_data_in(13 downto 0) <= "00" & x"3fd"; \r
+ when "1011110" => buf_0_data_in(13 downto 0) <= "00" & x"41b"; \r
+ when "1011111" => buf_0_data_in(13 downto 0) <= "00" & x"3f3"; \r
+ when "1100000" => buf_0_data_in(13 downto 0) <= "00" & x"3b2"; \r
+ when "1100001" => buf_0_data_in(13 downto 0) <= "00" & x"3d6"; \r
+ when "1100010" => buf_0_data_in(13 downto 0) <= "00" & x"3f2"; \r
+ when "1100011" => buf_0_data_in(13 downto 0) <= "00" & x"3f2"; \r
+ when "1100100" => buf_0_data_in(13 downto 0) <= "00" & x"40d"; \r
+ when "1100101" => buf_0_data_in(13 downto 0) <= "00" & x"3e4"; \r
+ when "1100110" => buf_0_data_in(13 downto 0) <= "00" & x"902"; \r
+ when "1100111" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; \r
+ when "1101000" => buf_0_data_in(13 downto 0) <= "00" & x"3d2"; \r
+ when "1101001" => buf_0_data_in(13 downto 0) <= "00" & x"3ef"; \r
+ when "1101010" => buf_0_data_in(13 downto 0) <= "00" & x"490"; \r
+ when "1101011" => buf_0_data_in(13 downto 0) <= "00" & x"402"; \r
+ when "1101100" => buf_0_data_in(13 downto 0) <= "00" & x"3bd"; \r
+ when "1101101" => buf_0_data_in(13 downto 0) <= "00" & x"3d1"; \r
+ when "1101110" => buf_0_data_in(13 downto 0) <= "00" & x"497"; \r
+ when "1101111" => buf_0_data_in(13 downto 0) <= "00" & x"3d2"; \r
+ when "1110000" => buf_0_data_in(13 downto 0) <= "00" & x"3b7"; \r
+ when "1110001" => buf_0_data_in(13 downto 0) <= "00" & x"3da"; \r
+ when "1110010" => buf_0_data_in(13 downto 0) <= "00" & x"4bd"; \r
+ when "1110011" => buf_0_data_in(13 downto 0) <= "00" & x"3c9"; \r
+ when "1110100" => buf_0_data_in(13 downto 0) <= "00" & x"3ba"; \r
+ when "1110101" => buf_0_data_in(13 downto 0) <= "00" & x"3c9"; \r
+ when "1110110" => buf_0_data_in(13 downto 0) <= "00" & x"4e9"; \r
+ when "1110111" => buf_0_data_in(13 downto 0) <= "00" & x"3cc"; \r
+ when "1111000" => buf_0_data_in(13 downto 0) <= "00" & x"3e4"; \r
+ when "1111001" => buf_0_data_in(13 downto 0) <= "00" & x"3b2"; \r
+ when "1111010" => buf_0_data_in(13 downto 0) <= "10" & x"edc"; -- real physical OVERFLOW\r
+ when "1111011" => buf_0_data_in(13 downto 0) <= "00" & x"3c4"; \r
+ when "1111100" => buf_0_data_in(13 downto 0) <= "00" & x"3e6"; \r
+ when "1111101" => buf_0_data_in(13 downto 0) <= "00" & x"3f0"; \r
+ when "1111110" => buf_0_data_in(13 downto 0) <= "00" & x"896"; \r
+ when "1111111" => buf_0_data_in(13 downto 0) <= "00" & x"402"; \r
+ when others => buf_0_data_in(13 downto 0) <= "00" & x"fff"; \r
+ end case;\r
+ end if;\r
+end process BUF_0_DATA_PROC;\r
+\r
+\r
+BUF_0_PED_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ case ped_addr is\r
+ when "0000000" => ped_0_data_in <= "00" & x"0485";\r
+ when "0000001" => ped_0_data_in <= "00" & x"148b"; \r
+ when "0000010" => ped_0_data_in <= "00" & x"2466"; \r
+ when "0000011" => ped_0_data_in <= "00" & x"3479"; \r
+-- when "0000100" => ped_0_data_in <= "00" & x"446e";\r
+ when "0000100" => ped_0_data_in <= "00" & x"446e"; -- physical UNDERFLOW\r
+ when "0000101" => ped_0_data_in <= "00" & x"5470"; \r
+ when "0000110" => ped_0_data_in <= "00" & x"647c"; \r
+ when "0000111" => ped_0_data_in <= "00" & x"7472"; \r
+ when "0001000" => ped_0_data_in <= "00" & x"0472"; \r
+ when "0001001" => ped_0_data_in <= "00" & x"1478"; \r
+-- when "0001010" => ped_0_data_in <= "00" & x"247f"; \r
+ when "0001010" => ped_0_data_in <= "00" & x"247f"; -- physical OVERFLOW\r
+ when "0001011" => ped_0_data_in <= "00" & x"3480"; \r
+ when "0001100" => ped_0_data_in <= "00" & x"4479"; \r
+ when "0001101" => ped_0_data_in <= "00" & x"5464"; \r
+ when "0001110" => ped_0_data_in <= "00" & x"645c"; \r
+ when "0001111" => ped_0_data_in <= "00" & x"7464"; \r
+ when "0010000" => ped_0_data_in <= "00" & x"045a"; \r
+-- when "0010001" => ped_0_data_in <= "00" & x"146f"; \r
+ when "0010001" => ped_0_data_in <= "00" & x"146f"; -- correction UNDERFLOW \r
+ when "0010010" => ped_0_data_in <= "00" & x"245c"; \r
+ when "0010011" => ped_0_data_in <= "00" & x"3445"; \r
+ when "0010100" => ped_0_data_in <= "00" & x"4448"; \r
+ when "0010101" => ped_0_data_in <= "00" & x"546e"; \r
+ when "0010110" => ped_0_data_in <= "00" & x"6450"; \r
+-- when "0010111" => ped_0_data_in <= "00" & x"7448"; \r
+ when "0010111" => ped_0_data_in <= "00" & x"7448"; -- correction OVERFLOW\r
+ when "0011000" => ped_0_data_in <= "00" & x"044d"; \r
+ when "0011001" => ped_0_data_in <= "00" & x"145c"; \r
+ when "0011010" => ped_0_data_in <= "00" & x"243b"; \r
+ when "0011011" => ped_0_data_in <= "00" & x"345a"; \r
+ when "0011100" => ped_0_data_in <= "00" & x"4469"; \r
+ when "0011101" => ped_0_data_in <= "00" & x"546f"; \r
+ when "0011110" => ped_0_data_in <= "00" & x"6455"; \r
+ when "0011111" => ped_0_data_in <= "00" & x"7463"; \r
+ when "0100000" => ped_0_data_in <= "00" & x"0429"; \r
+ when "0100001" => ped_0_data_in <= "00" & x"145b"; \r
+-- when "0100010" => ped_0_data_in <= "00" & x"2435"; \r
+ when "0100010" => ped_0_data_in <= "01" & x"2435"; -- physical OFF \r
+ when "0100011" => ped_0_data_in <= "00" & x"346f"; \r
+ when "0100100" => ped_0_data_in <= "00" & x"4463"; \r
+ when "0100101" => ped_0_data_in <= "00" & x"5454"; \r
+ when "0100110" => ped_0_data_in <= "00" & x"6452"; \r
+ when "0100111" => ped_0_data_in <= "00" & x"746e"; \r
+ when "0101000" => ped_0_data_in <= "00" & x"0469"; \r
+ when "0101001" => ped_0_data_in <= "00" & x"1462"; \r
+ when "0101010" => ped_0_data_in <= "00" & x"2464"; \r
+ when "0101011" => ped_0_data_in <= "00" & x"345e"; \r
+ when "0101100" => ped_0_data_in <= "00" & x"4469"; \r
+ when "0101101" => ped_0_data_in <= "00" & x"5469"; \r
+ when "0101110" => ped_0_data_in <= "00" & x"646d"; \r
+-- when "0101111" => ped_0_data_in <= "00" & x"7485"; \r
+ when "0101111" => ped_0_data_in <= "01" & x"7485"; -- correction OFF\r
+ when "0110000" => ped_0_data_in <= "00" & x"0478"; \r
+ when "0110001" => ped_0_data_in <= "00" & x"147d"; \r
+ when "0110010" => ped_0_data_in <= "00" & x"2468"; \r
+ when "0110011" => ped_0_data_in <= "00" & x"3480"; \r
+ when "0110100" => ped_0_data_in <= "00" & x"447d"; \r
+ when "0110101" => ped_0_data_in <= "00" & x"5480"; \r
+ when "0110110" => ped_0_data_in <= "00" & x"6468"; \r
+ when "0110111" => ped_0_data_in <= "00" & x"7496"; \r
+ when "0111000" => ped_0_data_in <= "00" & x"0471"; \r
+ when "0111001" => ped_0_data_in <= "00" & x"1474"; \r
+ when "0111010" => ped_0_data_in <= "00" & x"246b"; \r
+ when "0111011" => ped_0_data_in <= "00" & x"349b"; \r
+ when "0111100" => ped_0_data_in <= "00" & x"4499"; \r
+ when "0111101" => ped_0_data_in <= "00" & x"5484"; \r
+ when "0111110" => ped_0_data_in <= "00" & x"646d"; \r
+ when "0111111" => ped_0_data_in <= "00" & x"7486"; \r
+ when "1000000" => ped_0_data_in <= "00" & x"048e"; \r
+ when "1000001" => ped_0_data_in <= "00" & x"146e"; \r
+ when "1000010" => ped_0_data_in <= "00" & x"2488"; \r
+ when "1000011" => ped_0_data_in <= "00" & x"3491"; \r
+ when "1000100" => ped_0_data_in <= "00" & x"4487"; \r
+ when "1000101" => ped_0_data_in <= "00" & x"5476"; \r
+ when "1000110" => ped_0_data_in <= "00" & x"6453"; \r
+ when "1000111" => ped_0_data_in <= "00" & x"7484"; \r
+ when "1001000" => ped_0_data_in <= "00" & x"0452"; \r
+ when "1001001" => ped_0_data_in <= "00" & x"146f"; \r
+ when "1001010" => ped_0_data_in <= "00" & x"248d"; \r
+ when "1001011" => ped_0_data_in <= "00" & x"3486"; \r
+ when "1001100" => ped_0_data_in <= "00" & x"445c"; \r
+ when "1001101" => ped_0_data_in <= "00" & x"5475"; \r
+ when "1001110" => ped_0_data_in <= "00" & x"6476"; \r
+ when "1001111" => ped_0_data_in <= "00" & x"7475"; \r
+ when "1010000" => ped_0_data_in <= "00" & x"0472"; \r
+ when "1010001" => ped_0_data_in <= "00" & x"146f"; \r
+ when "1010010" => ped_0_data_in <= "00" & x"244c"; \r
+ when "1010011" => ped_0_data_in <= "00" & x"3479"; \r
+ when "1010100" => ped_0_data_in <= "00" & x"4469"; \r
+ when "1010101" => ped_0_data_in <= "00" & x"547f"; \r
+ when "1010110" => ped_0_data_in <= "00" & x"6478"; \r
+ when "1010111" => ped_0_data_in <= "00" & x"7478"; \r
+ when "1011000" => ped_0_data_in <= "00" & x"0472"; \r
+ when "1011001" => ped_0_data_in <= "00" & x"146c"; \r
+ when "1011010" => ped_0_data_in <= "00" & x"2478"; \r
+ when "1011011" => ped_0_data_in <= "00" & x"3481"; \r
+ when "1011100" => ped_0_data_in <= "00" & x"447a"; \r
+ when "1011101" => ped_0_data_in <= "00" & x"547f"; \r
+ when "1011110" => ped_0_data_in <= "00" & x"649f"; \r
+ when "1011111" => ped_0_data_in <= "00" & x"746f"; \r
+ when "1100000" => ped_0_data_in <= "00" & x"0443"; \r
+ when "1100001" => ped_0_data_in <= "00" & x"145d"; \r
+ when "1100010" => ped_0_data_in <= "00" & x"246f"; \r
+ when "1100011" => ped_0_data_in <= "00" & x"3482"; \r
+ when "1100100" => ped_0_data_in <= "00" & x"4498"; \r
+ when "1100101" => ped_0_data_in <= "00" & x"5483"; \r
+ when "1100110" => ped_0_data_in <= "00" & x"649b"; \r
+ when "1100111" => ped_0_data_in <= "00" & x"74a9"; \r
+ when "1101000" => ped_0_data_in <= "00" & x"0471"; \r
+ when "1101001" => ped_0_data_in <= "00" & x"1488"; \r
+ when "1101010" => ped_0_data_in <= "00" & x"249a"; \r
+ when "1101011" => ped_0_data_in <= "00" & x"349f"; \r
+ when "1101100" => ped_0_data_in <= "00" & x"4473"; \r
+ when "1101101" => ped_0_data_in <= "00" & x"5479"; \r
+ when "1101110" => ped_0_data_in <= "00" & x"648b"; \r
+ when "1101111" => ped_0_data_in <= "00" & x"747e"; \r
+ when "1110000" => ped_0_data_in <= "00" & x"0480"; \r
+ when "1110001" => ped_0_data_in <= "00" & x"1492"; \r
+ when "1110010" => ped_0_data_in <= "00" & x"2482"; \r
+ when "1110011" => ped_0_data_in <= "00" & x"3483"; \r
+ when "1110100" => ped_0_data_in <= "00" & x"447a"; \r
+ when "1110101" => ped_0_data_in <= "00" & x"548a"; \r
+ when "1110110" => ped_0_data_in <= "00" & x"6493"; \r
+ when "1110111" => ped_0_data_in <= "00" & x"7496"; \r
+ when "1111000" => ped_0_data_in <= "00" & x"0495"; \r
+ when "1111001" => ped_0_data_in <= "00" & x"1493"; \r
+ when "1111010" => ped_0_data_in <= "00" & x"2487"; -- real physical OVERFLOW\r
+ when "1111011" => ped_0_data_in <= "00" & x"3496"; \r
+ when "1111100" => ped_0_data_in <= "00" & x"449d"; \r
+ when "1111101" => ped_0_data_in <= "00" & x"54cb"; \r
+ when "1111110" => ped_0_data_in <= "00" & x"64b9"; \r
+ when "1111111" => ped_0_data_in <= "00" & x"74df"; \r
+ when others => ped_0_data_in <= "00" & x"ffff"; \r
+ end case;\r
+ end if;\r
+end process BUF_0_PED_PROC;\r
+\r
+\r
+-- Data faker for "APV 0"...\r
+BUF_0_THR_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ case thr_addr is\r
+ when "0000000" => thr_0_data_in <= "00" & x"001e";\r
+ when "0000001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0000010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "0000011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0000100" => thr_0_data_in <= "00" & x"401e"; \r
+ when "0000101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0000110" => thr_0_data_in <= "00" & x"601b"; \r
+ when "0000111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0001000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "0001001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0001010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "0001011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0001100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "0001101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0001110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "0001111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0010000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "0010001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0010010" => thr_0_data_in <= "00" & x"2021"; \r
+ when "0010011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0010100" => thr_0_data_in <= "00" & x"402d"; \r
+ when "0010101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0010110" => thr_0_data_in <= "00" & x"602a"; \r
+ when "0010111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0011000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "0011001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0011010" => thr_0_data_in <= "00" & x"2021"; \r
+ when "0011011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0011100" => thr_0_data_in <= "00" & x"401e"; \r
+ when "0011101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0011110" => thr_0_data_in <= "00" & x"601b"; \r
+ when "0011111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0100000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "0100001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0100010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "0100011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0100100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "0100101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0100110" => thr_0_data_in <= "00" & x"601b"; \r
+ when "0100111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0101000" => thr_0_data_in <= "00" & x"001b"; \r
+ when "0101001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0101010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "0101011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0101100" => thr_0_data_in <= "00" & x"401e"; \r
+ when "0101101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0101110" => thr_0_data_in <= "00" & x"601b"; \r
+ when "0101111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0110000" => thr_0_data_in <= "00" & x"000f"; \r
+ when "0110001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0110010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "0110011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0110100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "0110101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0110110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "0110111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0111000" => thr_0_data_in <= "00" & x"0021"; \r
+ when "0111001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0111010" => thr_0_data_in <= "00" & x"2027"; \r
+ when "0111011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0111100" => thr_0_data_in <= "00" & x"400f"; \r
+ when "0111101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0111110" => thr_0_data_in <= "00" & x"6048"; \r
+ when "0111111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1000000" => thr_0_data_in <= "00" & x"0024"; \r
+ when "1000001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1000010" => thr_0_data_in <= "00" & x"2024"; \r
+ when "1000011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1000100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1000101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1000110" => thr_0_data_in <= "00" & x"6021"; \r
+ when "1000111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1001000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "1001001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1001010" => thr_0_data_in <= "00" & x"2021"; \r
+ when "1001011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1001100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1001101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1001110" => thr_0_data_in <= "00" & x"601b"; \r
+ when "1001111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1010000" => thr_0_data_in <= "00" & x"001b"; \r
+ when "1010001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1010010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "1010011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1010100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1010101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1010110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "1010111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1011000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "1011001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1011010" => thr_0_data_in <= "00" & x"2021"; \r
+ when "1011011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1011100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1011101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1011110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "1011111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1100000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "1100001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1100010" => thr_0_data_in <= "00" & x"2021"; \r
+ when "1100011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1100100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1100101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1100110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "1100111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1101000" => thr_0_data_in <= "00" & x"0021"; \r
+ when "1101001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1101010" => thr_0_data_in <= "00" & x"2027"; \r
+ when "1101011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1101100" => thr_0_data_in <= "00" & x"4024"; \r
+ when "1101101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1101110" => thr_0_data_in <= "00" & x"6021"; \r
+ when "1101111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1110000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "1110001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1110010" => thr_0_data_in <= "00" & x"2024"; \r
+ when "1110011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1110100" => thr_0_data_in <= "00" & x"400f"; \r
+ when "1110101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1110110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "1110111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1111000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "1111001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1111010" => thr_0_data_in <= "00" & x"2024"; \r
+ when "1111011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1111100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1111101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1111110" => thr_0_data_in <= "00" & x"6021"; \r
+ when "1111111" => thr_0_data_in <= "00" & x"700f"; \r
+ when others => thr_0_data_in <= "00" & x"ffff"; \r
+ end case;\r
+ end if;\r
+end process BUF_0_THR_PROC;\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT pulse_sync\r
+ PORT(\r
+ CLK_A_IN : IN std_logic;\r
+ RESET_A_IN : IN std_logic;\r
+ PULSE_A_IN : IN std_logic;\r
+ CLK_B_IN : IN std_logic;\r
+ RESET_B_IN : IN std_logic; \r
+ PULSE_B_OUT : OUT std_logic\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_A_IN : std_logic;\r
+ SIGNAL RESET_A_IN : std_logic;\r
+ SIGNAL PULSE_A_IN : std_logic;\r
+ SIGNAL CLK_B_IN : std_logic;\r
+ SIGNAL RESET_B_IN : std_logic;\r
+ SIGNAL PULSE_B_OUT : std_logic;\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: pulse_sync PORT MAP(\r
+ CLK_A_IN => CLK_A_IN,\r
+ RESET_A_IN => RESET_A_IN,\r
+ PULSE_A_IN => PULSE_A_IN,\r
+ CLK_B_IN => CLK_B_IN,\r
+ RESET_B_IN => RESET_B_IN,\r
+ PULSE_B_OUT => PULSE_B_OUT\r
+ );\r
+\r
+THE_CLKA_GEN: process\r
+begin\r
+ clk_a_in <= '1'; wait for 5.0 ns;\r
+ clk_a_in <= '0'; wait for 5.0 ns;\r
+end process THE_CLKA_GEN;\r
+\r
+THE_CLKB_GEN: process( clk_a_in )\r
+begin\r
+ clk_b_in <= clk_a_in after 3.141592654 ns;\r
+end process THE_CLKB_GEN;\r
+\r
+THE_TESTBENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_a_in <= '0';\r
+ reset_b_in <= '0';\r
+ pulse_a_in <= '0';\r
+ wait for 173 ns;\r
+\r
+ -- Reset the whole stuff\r
+ reset_a_in <= '1';\r
+ reset_b_in <= '1';\r
+ wait for 200 ns;\r
+ reset_a_in <= '0';\r
+ reset_b_in <= '0';\r
+\r
+ wait for 179 ns;\r
+\r
+ -- Tests may start now\r
+ wait until rising_edge(clk_a_in);\r
+ pulse_a_in <= '1';\r
+ wait until rising_edge(clk_a_in);\r
+ pulse_a_in <= '0';\r
+\r
+ wait for 133 ns;\r
+\r
+ wait until rising_edge(clk_a_in);\r
+ pulse_a_in <= '1';\r
+ wait until rising_edge(clk_a_in);\r
+ wait until rising_edge(clk_a_in);\r
+ pulse_a_in <= '0';\r
+\r
+ wait for 133 ns;\r
+\r
+ wait until rising_edge(clk_a_in);\r
+ pulse_a_in <= '1';\r
+ wait until rising_edge(clk_a_in);\r
+ wait until rising_edge(clk_a_in);\r
+ wait until rising_edge(clk_a_in);\r
+ pulse_a_in <= '0';\r
+ \r
+ -- Stay a while.... stay forever!!! Muahaha!!!\r
+ wait;\r
+end process THE_TESTBENCH;\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT sfp_rx_handler\r
+ PORT(\r
+ SYSCLK : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ MED_READ_IN : IN std_logic;\r
+ SD_RX_DATA_IN : IN std_logic_vector(15 downto 0);\r
+ SD_RX_K_IN : IN std_logic_vector(1 downto 0); \r
+ SD_RX_ALLOW_IN : IN std_logic;\r
+ SD_LINK_OK_IN : IN std_logic;\r
+ SD_SWAP_BYTES_IN : IN std_logic;\r
+ MED_DATA_OUT : OUT std_logic_vector(15 downto 0);\r
+ MED_PACKET_NUM_OUT : OUT std_logic_vector(2 downto 0);\r
+ MED_DATAREADY_OUT : OUT std_logic;\r
+ SEND_RESET_WORDS_OUT : OUT std_logic;\r
+ MAKE_TRBNET_RESET_OUT : OUT std_logic; \r
+ TOC_CTR_OUT : OUT std_logic_vector(9 downto 0);\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL SYSCLK : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL MED_DATA_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL MED_PACKET_NUM_OUT : std_logic_vector(2 downto 0);\r
+ SIGNAL MED_DATAREADY_OUT : std_logic;\r
+ SIGNAL MED_READ_IN : std_logic;\r
+ SIGNAL SD_RX_DATA_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL SD_RX_K_IN : std_logic_vector(1 downto 0);\r
+ SIGNAL SD_RX_ALLOW_IN : std_logic;\r
+ SIGNAL SD_LINK_OK_IN : std_logic;\r
+ SIGNAL SD_SWAP_BYTES_IN : std_logic;\r
+ SIGNAL SEND_RESET_WORDS_OUT : std_logic;\r
+ SIGNAL MAKE_TRBNET_RESET_OUT : std_logic; \r
+ SIGNAL TOC_CTR_OUT : std_logic_vector(9 downto 0);\r
+ SIGNAL BSM_OUT : std_logic_vector(3 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: sfp_rx_handler PORT MAP(\r
+ SYSCLK => SYSCLK,\r
+ RESET_IN => RESET_IN,\r
+ MED_DATA_OUT => MED_DATA_OUT,\r
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,\r
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,\r
+ MED_READ_IN => MED_READ_IN,\r
+ SD_RX_DATA_IN => SD_RX_DATA_IN,\r
+ SD_RX_K_IN => SD_RX_K_IN,\r
+ SD_RX_ALLOW_IN => SD_RX_ALLOW_IN,\r
+ SD_LINK_OK_IN => SD_LINK_OK_IN,\r
+ SD_SWAP_BYTES_IN => SD_SWAP_BYTES_IN,\r
+ SEND_RESET_WORDS_OUT => SEND_RESET_WORDS_OUT,\r
+ MAKE_TRBNET_RESET_OUT => MAKE_TRBNET_RESET_OUT,\r
+ TOC_CTR_OUT => TOC_CTR_OUT,\r
+ BSM_OUT => BSM_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+CLOCK_GEN: process\r
+begin\r
+ sysclk <= '0'; wait for 5.0 ns;\r
+ sysclk <= '1'; wait for 5.0 ns;\r
+end process CLOCK_GEN;\r
+\r
+\r
+THE_TESTBENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '1';\r
+ med_read_in <= '1';\r
+ sd_rx_data_in <= x"bc50";\r
+ sd_rx_k_in <= b"01";\r
+ sd_rx_allow_in <= '0';\r
+ sd_link_ok_in <= '1';\r
+ sd_swap_bytes_in <= '0'; -- '01' on rx_k\r
+ wait for 100 ns;\r
+ \r
+ -- Reset the whole stuff\r
+ wait until rising_edge(sysclk);\r
+ reset_in <= '1';\r
+ wait until rising_edge(sysclk);\r
+ reset_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ sd_rx_allow_in <= '1';\r
+ wait for 100 ns;\r
+\r
+ -- Tests may start now\r
+\r
+ -- Receive reset sequence\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"11";\r
+ sd_rx_data_in <= x"fefe";\r
+ wait for 400 ns;\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"01";\r
+ sd_rx_data_in <= x"bc50";\r
+ wait until rising_edge(sysclk);\r
+\r
+ wait for 500 ns;\r
+\r
+ -- Receive packets\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"00";\r
+ sd_rx_data_in <= x"dead";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"f000";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"e001";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"d002";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"c003";\r
+ wait until rising_edge(sysclk);\r
+ -- End of first packet\r
+ sd_rx_data_in <= x"beef";\r
+ wait until rising_edge(sysclk);\r
+ -- PAUSE\r
+ sd_rx_k_in <= b"01";\r
+ sd_rx_data_in <= x"bc50";\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"00";\r
+ sd_rx_data_in <= x"b004";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"a005";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"9006";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"8007";\r
+ wait until rising_edge(sysclk);\r
+ -- End of second packet\r
+ sd_rx_data_in <= x"affe";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"7008";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"6009";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"500a";\r
+ wait until rising_edge(sysclk);\r
+ -- PAUSE\r
+ sd_rx_k_in <= b"01";\r
+ sd_rx_data_in <= x"bc50";\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"00";\r
+ sd_rx_data_in <= x"400b";\r
+ wait until rising_edge(sysclk);\r
+ -- End of third packet\r
+ sd_rx_k_in <= b"01";\r
+ sd_rx_data_in <= x"bc50";\r
+\r
+ wait;\r
+\r
+ sd_rx_data_in <= x"d00f";\r
+ wait until rising_edge(sysclk);\r
+ -- Packet broken!!!\r
+ sd_rx_k_in <= b"01";\r
+ sd_rx_data_in <= x"bc50";\r
+ wait for 11 us;\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"00";\r
+ sd_rx_data_in <= x"e001";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"fe10";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"ee11";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"de12";\r
+ wait until rising_edge(sysclk);\r
+ -- End of fouth packet\r
+ sd_rx_k_in <= b"01";\r
+ sd_rx_data_in <= x"bc50";\r
+ \r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ \r
+ -- Stay a while... stay forever!!!! Muahahaha!!!!\r
+ wait;\r
+ \r
+end process THE_TESTBENCH;\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT sfp_rx_handler\r
+ PORT(\r
+ SYSCLK : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ MED_READ_IN : IN std_logic;\r
+ SD_RX_DATA_IN : IN std_logic_vector(15 downto 0);\r
+ SD_RX_K_IN : IN std_logic_vector(1 downto 0); \r
+ SD_RX_ALLOW_IN : IN std_logic;\r
+ SD_LINK_OK_IN : IN std_logic;\r
+ SD_SWAP_BYTES_IN : IN std_logic;\r
+ MED_DATA_OUT : OUT std_logic_vector(15 downto 0);\r
+ MED_PACKET_NUM_OUT : OUT std_logic_vector(2 downto 0);\r
+ MED_DATAREADY_OUT : OUT std_logic;\r
+ SEND_RESET_WORDS_OUT : OUT std_logic;\r
+ MAKE_TRBNET_RESET_OUT : OUT std_logic; \r
+ TOC_CTR_OUT : OUT std_logic_vector(9 downto 0);\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL SYSCLK : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL MED_DATA_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL MED_PACKET_NUM_OUT : std_logic_vector(2 downto 0);\r
+ SIGNAL MED_DATAREADY_OUT : std_logic;\r
+ SIGNAL MED_READ_IN : std_logic;\r
+ SIGNAL SD_RX_DATA_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL SD_RX_K_IN : std_logic_vector(1 downto 0);\r
+ SIGNAL SD_RX_ALLOW_IN : std_logic;\r
+ SIGNAL SD_LINK_OK_IN : std_logic;\r
+ SIGNAL SD_SWAP_BYTES_IN : std_logic;\r
+ SIGNAL SEND_RESET_WORDS_OUT : std_logic;\r
+ SIGNAL MAKE_TRBNET_RESET_OUT : std_logic; \r
+ SIGNAL TOC_CTR_OUT : std_logic_vector(9 downto 0);\r
+ SIGNAL BSM_OUT : std_logic_vector(3 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: sfp_rx_handler PORT MAP(\r
+ SYSCLK => SYSCLK,\r
+ RESET_IN => RESET_IN,\r
+ MED_DATA_OUT => MED_DATA_OUT,\r
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,\r
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,\r
+ MED_READ_IN => MED_READ_IN,\r
+ SD_RX_DATA_IN => SD_RX_DATA_IN,\r
+ SD_RX_K_IN => SD_RX_K_IN,\r
+ SD_RX_ALLOW_IN => SD_RX_ALLOW_IN,\r
+ SD_LINK_OK_IN => SD_LINK_OK_IN,\r
+ SD_SWAP_BYTES_IN => SD_SWAP_BYTES_IN,\r
+ SEND_RESET_WORDS_OUT => SEND_RESET_WORDS_OUT,\r
+ MAKE_TRBNET_RESET_OUT => MAKE_TRBNET_RESET_OUT,\r
+ TOC_CTR_OUT => TOC_CTR_OUT,\r
+ BSM_OUT => BSM_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+CLOCK_GEN: process\r
+begin\r
+ sysclk <= '0'; wait for 5.0 ns;\r
+ sysclk <= '1'; wait for 5.0 ns;\r
+end process CLOCK_GEN;\r
+\r
+\r
+THE_TESTBENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '1';\r
+ med_read_in <= '1';\r
+ sd_rx_data_in <= x"bc50";\r
+ sd_rx_k_in <= b"01";\r
+ sd_rx_allow_in <= '0';\r
+ sd_link_ok_in <= '1';\r
+ sd_swap_bytes_in <= '0'; -- '01' on rx_k\r
+ wait for 100 ns;\r
+ \r
+ -- Reset the whole stuff\r
+ wait until rising_edge(sysclk);\r
+ reset_in <= '1';\r
+ wait until rising_edge(sysclk);\r
+ reset_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ sd_rx_allow_in <= '1';\r
+ wait for 100 ns;\r
+\r
+ -- Tests may start now\r
+\r
+ -- Receive reset sequence\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"11";\r
+ sd_rx_data_in <= x"fefe";\r
+ wait for 400 ns;\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"01";\r
+ sd_rx_data_in <= x"bc50";\r
+ wait until rising_edge(sysclk);\r
+\r
+ wait for 500 ns;\r
+\r
+ -- Receive packets\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"00";\r
+ sd_rx_data_in <= x"dead";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"f000";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"e001";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"d002";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"c003";\r
+ wait until rising_edge(sysclk);\r
+ -- End of first packet\r
+ sd_rx_data_in <= x"beef";\r
+ wait until rising_edge(sysclk);\r
+ -- PAUSE\r
+ sd_rx_k_in <= b"01";\r
+ sd_rx_data_in <= x"bc50";\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"00";\r
+ sd_rx_data_in <= x"b004";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"a005";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"9006";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"8007";\r
+ wait until rising_edge(sysclk);\r
+ -- End of second packet\r
+ sd_rx_data_in <= x"affe";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"7008";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"01";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"6009";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"500a";\r
+ wait until rising_edge(sysclk);\r
+ -- PAUSE\r
+ sd_rx_k_in <= b"01";\r
+ sd_rx_data_in <= x"bc50";\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"00";\r
+ sd_rx_data_in <= x"400b";\r
+ wait until rising_edge(sysclk);\r
+ -- End of third packet\r
+ sd_rx_k_in <= b"01";\r
+ sd_rx_data_in <= x"bc50";\r
+\r
+ wait;\r
+\r
+ sd_rx_data_in <= x"d00f";\r
+ wait until rising_edge(sysclk);\r
+ -- Packet broken!!!\r
+ sd_rx_k_in <= b"01";\r
+ sd_rx_data_in <= x"bc50";\r
+ wait for 11 us;\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"00";\r
+ sd_rx_data_in <= x"e001";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"fe10";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"ee11";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"de12";\r
+ wait until rising_edge(sysclk);\r
+ -- End of fouth packet\r
+ sd_rx_k_in <= b"01";\r
+ sd_rx_data_in <= x"bc50";\r
+ \r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ \r
+ -- Stay a while... stay forever!!!! Muahahaha!!!!\r
+ wait;\r
+ \r
+end process THE_TESTBENCH;\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT spi_master\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ BUS_READ_IN : IN std_logic;\r
+ BUS_WRITE_IN : IN std_logic;\r
+ BUS_ADDR_IN : IN std_logic_vector(0 to 0);\r
+ BUS_DATA_IN : IN std_logic_vector(31 downto 0);\r
+ SPI_SDI_IN : IN std_logic;\r
+ BRAM_WR_D_IN : IN std_logic_vector(7 downto 0); \r
+ BUS_BUSY_OUT : OUT std_logic;\r
+ BUS_ACK_OUT : OUT std_logic;\r
+ BUS_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
+ SPI_CS_OUT : OUT std_logic;\r
+ SPI_SDO_OUT : OUT std_logic;\r
+ SPI_SCK_OUT : OUT std_logic;\r
+ BRAM_A_OUT : OUT std_logic_vector(7 downto 0);\r
+ BRAM_RD_D_OUT : OUT std_logic_vector(7 downto 0);\r
+ BRAM_WE_OUT : OUT std_logic;\r
+ STAT : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL BUS_READ_IN : std_logic;\r
+ SIGNAL BUS_WRITE_IN : std_logic;\r
+ SIGNAL BUS_BUSY_OUT : std_logic;\r
+ SIGNAL BUS_ACK_OUT : std_logic;\r
+ SIGNAL BUS_ADDR_IN : std_logic_vector(0 to 0);\r
+ SIGNAL BUS_DATA_IN : std_logic_vector(31 downto 0);\r
+ SIGNAL BUS_DATA_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL SPI_CS_OUT : std_logic;\r
+ SIGNAL SPI_SDI_IN : std_logic;\r
+ SIGNAL SPI_SDO_OUT : std_logic;\r
+ SIGNAL SPI_SCK_OUT : std_logic;\r
+ SIGNAL BRAM_A_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL BRAM_WR_D_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL BRAM_RD_D_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL BRAM_WE_OUT : std_logic;\r
+ SIGNAL STAT : std_logic_vector(31 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: spi_master PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ BUS_READ_IN => BUS_READ_IN,\r
+ BUS_WRITE_IN => BUS_WRITE_IN,\r
+ BUS_BUSY_OUT => BUS_BUSY_OUT,\r
+ BUS_ACK_OUT => BUS_ACK_OUT,\r
+ BUS_ADDR_IN => BUS_ADDR_IN,\r
+ BUS_DATA_IN => BUS_DATA_IN,\r
+ BUS_DATA_OUT => BUS_DATA_OUT,\r
+ SPI_CS_OUT => SPI_CS_OUT,\r
+ SPI_SDI_IN => SPI_SDI_IN,\r
+ SPI_SDO_OUT => SPI_SDO_OUT,\r
+ SPI_SCK_OUT => SPI_SCK_OUT,\r
+ BRAM_A_OUT => BRAM_A_OUT,\r
+ BRAM_WR_D_IN => BRAM_WR_D_IN,\r
+ BRAM_RD_D_OUT => BRAM_RD_D_OUT,\r
+ BRAM_WE_OUT => BRAM_WE_OUT,\r
+ STAT => STAT\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ spi_sdi_in <= '0';\r
+ bus_read_in <= '0';\r
+ bus_write_in <= '0';\r
+ bus_addr_in <= b"0";\r
+ bus_data_in <= x"0000_0000";\r
+ bram_wr_d_in <= x"00";\r
+ \r
+ -- Sync reset\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 140 ns;\r
+ \r
+ -- Tests may start now\r
+ \r
+ -- Set MAX to 0x00 = unknown bytes\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"1";\r
+ bus_data_in <= x"11_00_00_00";\r
+ wait until rising_edge(clk_in);\r
+ bus_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ bus_write_in <= '0';\r
+ wait until falling_edge(bus_ack_out);\r
+ bus_data_in <= x"0000_0000";\r
+ bus_addr_in <= b"0";\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Start SPI access (Read)\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"0";\r
+ bus_data_in <= x"03_aa_bb_cc";\r
+ wait until rising_edge(clk_in);\r
+ bus_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ bus_write_in <= '0';\r
+ wait until falling_edge(bus_ack_out);\r
+ bus_data_in <= x"0000_0000";\r
+ bus_addr_in <= b"0";\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- SPI is busy now...\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"0";\r
+ wait until rising_edge(clk_in);\r
+ bus_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ bus_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"0";\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- SPI is busy now...\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"1";\r
+ wait until rising_edge(clk_in);\r
+ bus_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ bus_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"0";\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Stay a while... stay forever!!!\r
+ wait;\r
+ \r
+end process THE_TEST_BENCH;\r
+END;\r
+\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT spi_master\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ BUS_READ_IN : IN std_logic;\r
+ BUS_WRITE_IN : IN std_logic;\r
+ BUS_ADDR_IN : IN std_logic_vector(0 to 0);\r
+ BUS_DATA_IN : IN std_logic_vector(31 downto 0);\r
+ SPI_SDI_IN : IN std_logic;\r
+ BRAM_WR_D_IN : IN std_logic_vector(7 downto 0); \r
+ BUS_BUSY_OUT : OUT std_logic;\r
+ BUS_ACK_OUT : OUT std_logic;\r
+ BUS_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
+ SPI_CS_OUT : OUT std_logic;\r
+ SPI_SDO_OUT : OUT std_logic;\r
+ SPI_SCK_OUT : OUT std_logic;\r
+ BRAM_A_OUT : OUT std_logic_vector(7 downto 0);\r
+ BRAM_RD_D_OUT : OUT std_logic_vector(7 downto 0);\r
+ BRAM_WE_OUT : OUT std_logic;\r
+ STAT : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL BUS_READ_IN : std_logic;\r
+ SIGNAL BUS_WRITE_IN : std_logic;\r
+ SIGNAL BUS_BUSY_OUT : std_logic;\r
+ SIGNAL BUS_ACK_OUT : std_logic;\r
+ SIGNAL BUS_ADDR_IN : std_logic_vector(0 to 0);\r
+ SIGNAL BUS_DATA_IN : std_logic_vector(31 downto 0);\r
+ SIGNAL BUS_DATA_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL SPI_CS_OUT : std_logic;\r
+ SIGNAL SPI_SDI_IN : std_logic;\r
+ SIGNAL SPI_SDO_OUT : std_logic;\r
+ SIGNAL SPI_SCK_OUT : std_logic;\r
+ SIGNAL BRAM_A_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL BRAM_WR_D_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL BRAM_RD_D_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL BRAM_WE_OUT : std_logic;\r
+ SIGNAL STAT : std_logic_vector(31 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: spi_master PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ BUS_READ_IN => BUS_READ_IN,\r
+ BUS_WRITE_IN => BUS_WRITE_IN,\r
+ BUS_BUSY_OUT => BUS_BUSY_OUT,\r
+ BUS_ACK_OUT => BUS_ACK_OUT,\r
+ BUS_ADDR_IN => BUS_ADDR_IN,\r
+ BUS_DATA_IN => BUS_DATA_IN,\r
+ BUS_DATA_OUT => BUS_DATA_OUT,\r
+ SPI_CS_OUT => SPI_CS_OUT,\r
+ SPI_SDI_IN => SPI_SDI_IN,\r
+ SPI_SDO_OUT => SPI_SDO_OUT,\r
+ SPI_SCK_OUT => SPI_SCK_OUT,\r
+ BRAM_A_OUT => BRAM_A_OUT,\r
+ BRAM_WR_D_IN => BRAM_WR_D_IN,\r
+ BRAM_RD_D_OUT => BRAM_RD_D_OUT,\r
+ BRAM_WE_OUT => BRAM_WE_OUT,\r
+ STAT => STAT\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ spi_sdi_in <= '0';\r
+ bus_read_in <= '0';\r
+ bus_write_in <= '0';\r
+ bus_addr_in <= b"0";\r
+ bus_data_in <= x"0000_0000";\r
+ bram_wr_d_in <= x"00";\r
+ \r
+ -- Sync reset\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 140 ns;\r
+ \r
+ -- Tests may start now\r
+ \r
+ -- Set MAX to 0x00 = unknown bytes\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"1";\r
+ bus_data_in <= x"ff_00_00_00";\r
+ wait until rising_edge(clk_in);\r
+ bus_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ bus_write_in <= '0';\r
+ wait until falling_edge(bus_ack_out);\r
+ bus_data_in <= x"0000_0000";\r
+ bus_addr_in <= b"0";\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Start SPI access (Read)\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"0";\r
+ bus_data_in <= x"03_aa_bb_cc";\r
+ wait until rising_edge(clk_in);\r
+ bus_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ bus_write_in <= '0';\r
+ wait until falling_edge(bus_ack_out);\r
+ bus_data_in <= x"0000_0000";\r
+ bus_addr_in <= b"0";\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- SPI is busy now...\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"0";\r
+ wait until rising_edge(clk_in);\r
+ bus_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ bus_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"0";\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- SPI is busy now...\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"1";\r
+ wait until rising_edge(clk_in);\r
+ bus_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ bus_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"0";\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Stay a while... stay forever!!!\r
+ wait;\r
+ \r
+end process THE_TEST_BENCH;\r
+END;\r
+\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT test_media\r
+ PORT(\r
+ SYSCLK : IN std_logic;\r
+ RESET : IN std_logic;\r
+ CLEAR : IN std_logic;\r
+ MED_READ_IN : IN std_logic;\r
+ SD_RX_DATA_IN : IN std_logic_vector(15 downto 0);\r
+ SD_RX_K_IN : IN std_logic_vector(1 downto 0); \r
+ MED_DATA_OUT : OUT std_logic_vector(15 downto 0);\r
+ MED_PACKET_NUM_OUT : OUT std_logic_vector(2 downto 0);\r
+ MED_DATAREADY_OUT : OUT std_logic;\r
+ TOC_CTR_OUT : OUT std_logic_vector(9 downto 0);\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL SYSCLK : std_logic;\r
+ SIGNAL RESET : std_logic;\r
+ SIGNAL CLEAR : std_logic;\r
+ SIGNAL MED_DATA_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL MED_PACKET_NUM_OUT : std_logic_vector(2 downto 0);\r
+ SIGNAL MED_DATAREADY_OUT : std_logic;\r
+ SIGNAL MED_READ_IN : std_logic;\r
+ SIGNAL SD_RX_DATA_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL SD_RX_K_IN : std_logic_vector(1 downto 0);\r
+ SIGNAL TOC_CTR_OUT : std_logic_vector(9 downto 0);\r
+ SIGNAL BSM_OUT : std_logic_vector(3 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: test_media PORT MAP(\r
+ SYSCLK => SYSCLK,\r
+ RESET => RESET,\r
+ CLEAR => CLEAR,\r
+ MED_DATA_OUT => MED_DATA_OUT,\r
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,\r
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,\r
+ MED_READ_IN => MED_READ_IN,\r
+ SD_RX_DATA_IN => SD_RX_DATA_IN,\r
+ SD_RX_K_IN => SD_RX_K_IN,\r
+ TOC_CTR_OUT => TOC_CTR_OUT,\r
+ BSM_OUT => BSM_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+CLOCK_GEN: process\r
+begin\r
+ sysclk <= '0'; wait for 5.0 ns;\r
+ sysclk <= '1'; wait for 5.0 ns;\r
+end process CLOCK_GEN;\r
+\r
+\r
+THE_TESTBENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset <= '1';\r
+ clear <= '0'; -- unused\r
+ med_read_in <= '1';\r
+ sd_rx_data_in <= x"fefe";\r
+ sd_rx_k_in <= b"10";\r
+ wait for 50 ns;\r
+ \r
+ -- Reset the whole stuff\r
+ wait until rising_edge(sysclk);\r
+ reset <= '1';\r
+ wait until rising_edge(sysclk);\r
+ reset <= '0';\r
+ sd_rx_data_in <= x"bc50";\r
+ wait for 100 ns;\r
+ \r
+ -- Tests may start now\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"00";\r
+ sd_rx_data_in <= x"dead";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"f000";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"e001";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"d002";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"c003";\r
+ wait until rising_edge(sysclk);\r
+ -- End of first packet\r
+ sd_rx_data_in <= x"beef";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"b004";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"a005";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"9006";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"8007";\r
+ wait until rising_edge(sysclk);\r
+ -- End of second packet\r
+ sd_rx_data_in <= x"affe";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"7008";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"10";\r
+ sd_rx_data_in <= x"bc50";\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"00";\r
+ sd_rx_data_in <= x"6009";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"500a";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"400b";\r
+ wait until rising_edge(sysclk);\r
+ -- End of third packet\r
+ sd_rx_k_in <= b"10";\r
+ sd_rx_data_in <= x"bc50";\r
+ \r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ \r
+ -- Stay a while... stay forever!!!! Muahahaha!!!!\r
+ wait;\r
+ \r
+end process THE_TESTBENCH;\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT test_media\r
+ PORT(\r
+ SYSCLK : IN std_logic;\r
+ RESET : IN std_logic;\r
+ CLEAR : IN std_logic;\r
+ MED_READ_IN : IN std_logic;\r
+ SD_RX_DATA_IN : IN std_logic_vector(15 downto 0);\r
+ SD_RX_K_IN : IN std_logic_vector(1 downto 0); \r
+ MED_DATA_OUT : OUT std_logic_vector(15 downto 0);\r
+ MED_PACKET_NUM_OUT : OUT std_logic_vector(2 downto 0);\r
+ MED_DATAREADY_OUT : OUT std_logic;\r
+ TOC_CTR_OUT : OUT std_logic_vector(9 downto 0);\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL SYSCLK : std_logic;\r
+ SIGNAL RESET : std_logic;\r
+ SIGNAL CLEAR : std_logic;\r
+ SIGNAL MED_DATA_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL MED_PACKET_NUM_OUT : std_logic_vector(2 downto 0);\r
+ SIGNAL MED_DATAREADY_OUT : std_logic;\r
+ SIGNAL MED_READ_IN : std_logic;\r
+ SIGNAL SD_RX_DATA_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL SD_RX_K_IN : std_logic_vector(1 downto 0);\r
+ SIGNAL TOC_CTR_OUT : std_logic_vector(9 downto 0);\r
+ SIGNAL BSM_OUT : std_logic_vector(3 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: test_media PORT MAP(\r
+ SYSCLK => SYSCLK,\r
+ RESET => RESET,\r
+ CLEAR => CLEAR,\r
+ MED_DATA_OUT => MED_DATA_OUT,\r
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,\r
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,\r
+ MED_READ_IN => MED_READ_IN,\r
+ SD_RX_DATA_IN => SD_RX_DATA_IN,\r
+ SD_RX_K_IN => SD_RX_K_IN,\r
+ TOC_CTR_OUT => TOC_CTR_OUT,\r
+ BSM_OUT => BSM_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+CLOCK_GEN: process\r
+begin\r
+ sysclk <= '0'; wait for 5.0 ns;\r
+ sysclk <= '1'; wait for 5.0 ns;\r
+end process CLOCK_GEN;\r
+\r
+\r
+THE_TESTBENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset <= '1';\r
+ clear <= '0'; -- unused\r
+ med_read_in <= '1';\r
+ sd_rx_data_in <= x"fefe";\r
+ sd_rx_k_in <= b"10";\r
+ wait for 50 ns;\r
+ \r
+ -- Reset the whole stuff\r
+ wait until rising_edge(sysclk);\r
+ reset <= '1';\r
+ wait until rising_edge(sysclk);\r
+ reset <= '0';\r
+ sd_rx_data_in <= x"bc50";\r
+ wait for 100 ns;\r
+ \r
+ -- Tests may start now\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"00";\r
+ sd_rx_data_in <= x"dead";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"f000";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"e001";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"d002";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"c003";\r
+ wait until rising_edge(sysclk);\r
+ -- End of first packet\r
+ sd_rx_data_in <= x"beef";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"b004";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"a005";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"9006";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"8007";\r
+ wait until rising_edge(sysclk);\r
+ -- End of second packet\r
+ sd_rx_data_in <= x"affe";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"7008";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"10";\r
+ sd_rx_data_in <= x"bc50";\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_k_in <= b"00";\r
+ sd_rx_data_in <= x"6009";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"500a";\r
+ wait until rising_edge(sysclk);\r
+ sd_rx_data_in <= x"400b";\r
+ wait until rising_edge(sysclk);\r
+ -- End of third packet\r
+ sd_rx_k_in <= b"10";\r
+ sd_rx_data_in <= x"bc50";\r
+ \r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ wait until rising_edge(sysclk);\r
+ \r
+ -- Stay a while... stay forever!!!! Muahahaha!!!!\r
+ wait;\r
+ \r
+end process THE_TESTBENCH;\r
+\r
+END;\r
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)
-Wed Nov 04 16:11:12 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem -memformat orca -e
- Circuit name : adc_apv_map_mem
- Module type : rom
- Module Version : 2.4
- Address width : 7
- Ports :
- Inputs : Address[6:0]
- Outputs : Q[3:0]
- I/O buffer : not inserted
- Memory file : i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem
- EDIF output : suppressed
- VHDL output : adc_apv_map_mem.vhd
- VHDL template : adc_apv_map_mem_tmpl.vhd
- VHDL testbench : tb_adc_apv_map_mem_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : adc_apv_map_mem.srp
- Element Usage :
- ROM128X1 : 4
- Estimated Resource Usage:
- LUT : 16
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Wed Nov 04 16:11:12 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem -memformat orca -e \r
- Circuit name : adc_apv_map_mem\r
- Module type : rom\r
- Module Version : 2.4\r
- Address width : 7\r
- Data width : 4\r
- Ports : \r
- Inputs : Address[6:0]\r
- Outputs : Q[3:0]\r
- I/O buffer : not inserted\r
- Memory file : i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem\r
- EDIF output : suppressed\r
- VHDL output : adc_apv_map_mem.vhd\r
- VHDL template : adc_apv_map_mem_tmpl.vhd\r
- VHDL testbench : tb_adc_apv_map_mem_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : adc_apv_map_mem.srp\r
- Estimated Resource Usage:\r
- LUT : 16\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: ..\src\adc_apv_map_mem.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 2.4
--- Wed Nov 04 16:11:12 2009
-
--- parameterized module component declaration
-component adc_apv_map_mem
- port (Address: in std_logic_vector(6 downto 0);
- Q: out std_logic_vector(3 downto 0));
-end component;
-
--- parameterized module component instance
-__ : adc_apv_map_mem
- port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__);
+++ /dev/null
-SCUBA, Version ispLever_v72_PROD_Build (44)
-Fri Apr 24 11:41:10 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_ch_in -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type iol -mode in -width 1 -gear 1 -del 16 -e
- Circuit name : adc_ch_in
- Module type : iol
- Module Version : 3.6
- Ports :
- Inputs : Del[3:0], ECLK, SCLK, Rst, Data[0:0]
- Outputs : Q[1:0]
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : adc_ch_in.vhd
- VHDL template : adc_ch_in_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : adc_ch_in.srp
- Element Usage :
- IB : 1
- IDDRFXA : 1
- DELAYB : 1
- Estimated Resource Usage:
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
--- Module Version: 3.6
--- Fri Apr 24 11:41:10 2009
-
--- parameterized module component declaration
-component adc_ch_in
- port (Del: in std_logic_vector(3 downto 0); ECLK: in std_logic;
- SCLK: in std_logic; Rst: in std_logic;
- Data: in std_logic_vector(0 downto 0);
- Q: out std_logic_vector(1 downto 0));
-end component;
-
--- parameterized module component instance
-__ : adc_ch_in
- port map (Del(3 downto 0)=>__, ECLK=>__, SCLK=>__, Rst=>__, Data(0 downto 0)=>__,
- Q(1 downto 0)=>__);
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)
-Thu Nov 05 10:27:05 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_onewire_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem -memformat orca -e
- Circuit name : adc_onewire_map_mem
- Module type : rom
- Module Version : 2.4
- Address width : 7
- Ports :
- Inputs : Address[6:0]
- Outputs : Q[3:0]
- I/O buffer : not inserted
- Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem
- EDIF output : suppressed
- VHDL output : adc_onewire_map_mem.vhd
- VHDL template : adc_onewire_map_mem_tmpl.vhd
- VHDL testbench : tb_adc_onewire_map_mem_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : adc_onewire_map_mem.srp
- Element Usage :
- ROM128X1 : 4
- Estimated Resource Usage:
- LUT : 16
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Thu Nov 05 10:27:05 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_onewire_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem -memformat orca -e \r
- Circuit name : adc_onewire_map_mem\r
- Module type : rom\r
- Module Version : 2.4\r
- Address width : 7\r
- Data width : 4\r
- Ports : \r
- Inputs : Address[6:0]\r
- Outputs : Q[3:0]\r
- I/O buffer : not inserted\r
- Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem\r
- EDIF output : suppressed\r
- VHDL output : adc_onewire_map_mem.vhd\r
- VHDL template : adc_onewire_map_mem_tmpl.vhd\r
- VHDL testbench : tb_adc_onewire_map_mem_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : adc_onewire_map_mem.srp\r
- Estimated Resource Usage:\r
- LUT : 16\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: adc_onewire_map_mem.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 2.4
--- Thu Nov 05 10:27:05 2009
-
--- parameterized module component declaration
-component adc_onewire_map_mem
- port (Address: in std_logic_vector(6 downto 0);
- Q: out std_logic_vector(3 downto 0));
-end component;
-
--- parameterized module component instance
-__ : adc_onewire_map_mem
- port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__);
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
--- Module Version: 4.2
--- Thu Apr 16 11:20:59 2009
-
--- parameterized module component declaration
-component adc_pll
- port (CLK: in std_logic; RESET: in std_logic; CLKOP: out std_logic;
- LOCK: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : adc_pll
- port map (CLK=>__, RESET=>__, CLKOP=>__, LOCK=>__);
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)
-Tue Oct 13 16:03:30 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_snoop_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 10 -rwidth 16 -waddr_width 10 -wwidth 16 -rnum_words 1024 -wnum_words 1024 -outdata REGISTERED -resetmode SYNC -cascade -1 -e
- Circuit name : adc_snoop_mem
- Module type : RAM_DP
- Module Version : 6.1
- Ports :
- Inputs : WrAddress[9:0], RdAddress[9:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
- Outputs : Q[15:0]
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : adc_snoop_mem.vhd
- VHDL template : adc_snoop_mem_tmpl.vhd
- VHDL testbench : tb_adc_snoop_mem_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : adc_snoop_mem.srp
- Element Usage :
- DP16KB : 1
- Estimated Resource Usage:
- EBR : 1
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Tue Oct 13 16:03:30 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_snoop_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 10 -rwidth 16 -waddr_width 10 -wwidth 16 -rnum_words 1024 -wnum_words 1024 -outdata REGISTERED -resetmode SYNC -cascade -1 -e \r
- Circuit name : adc_snoop_mem\r
- Module type : RAM_DP\r
- Module Version : 6.1\r
- Ports : \r
- Inputs : WrAddress[9:0], RdAddress[9:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn\r
- Outputs : Q[15:0]\r
- I/O buffer : not inserted\r
- EDIF output : suppressed\r
- VHDL output : adc_snoop_mem.vhd\r
- VHDL template : adc_snoop_mem_tmpl.vhd\r
- VHDL testbench : tb_adc_snoop_mem_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : adc_snoop_mem.srp\r
- Estimated Resource Usage:\r
- EBR : 1\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: adc_snoop_mem.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 6.1
--- Tue Oct 13 16:03:30 2009
-
--- parameterized module component declaration
-component adc_snoop_mem
- port (WrAddress: in std_logic_vector(9 downto 0);
- RdAddress: in std_logic_vector(9 downto 0);
- Data: in std_logic_vector(15 downto 0); WE: in std_logic;
- RdClock: in std_logic; RdClockEn: in std_logic;
- Reset: in std_logic; WrClock: in std_logic;
- WrClockEn: in std_logic; Q: out std_logic_vector(15 downto 0));
-end component;
-
--- parameterized module component instance
-__ : adc_snoop_mem
- port map (WrAddress(9 downto 0)=>__, RdAddress(9 downto 0)=>__, Data(15 downto 0)=>__,
- WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, WrClock=>__,
- WrClockEn=>__, Q(15 downto 0)=>__);
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24)
--- Module Version: 3.1
---X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type add -width 16 -unsigned -output_reg -enable -pipeline 0 -e
-
--- Tue Mar 03 10:27:46 2009
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity adder_16bit is
- port (
- DataA: in std_logic_vector(15 downto 0);
- DataB: in std_logic_vector(15 downto 0);
- Clock: in std_logic;
- Reset: in std_logic;
- ClockEn: in std_logic;
- Result: out std_logic_vector(15 downto 0));
-end adder_16bit;
-
-architecture Structure of adder_16bit is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal r0_sum15: std_logic;
- signal r0_sum14: std_logic;
- signal r0_sum13: std_logic;
- signal r0_sum12: std_logic;
- signal r0_sum11: std_logic;
- signal r0_sum10: std_logic;
- signal r0_sum9: std_logic;
- signal r0_sum8: std_logic;
- signal r0_sum7: std_logic;
- signal r0_sum6: std_logic;
- signal r0_sum5: std_logic;
- signal r0_sum4: std_logic;
- signal r0_sum3: std_logic;
- signal r0_sum2: std_logic;
- signal r0_sum1: std_logic;
- signal r0_sum0: std_logic;
- signal addsub_cod_0: std_logic;
- signal tsum0: std_logic;
- signal tsum1: std_logic;
- signal tsum2: std_logic;
- signal tsum3: std_logic;
- signal co0: std_logic;
- signal tsum4: std_logic;
- signal tsum5: std_logic;
- signal co1: std_logic;
- signal tsum6: std_logic;
- signal tsum7: std_logic;
- signal co2: std_logic;
- signal tsum8: std_logic;
- signal tsum9: std_logic;
- signal co3: std_logic;
- signal tsum10: std_logic;
- signal tsum11: std_logic;
- signal co4: std_logic;
- signal tsum12: std_logic;
- signal tsum13: std_logic;
- signal co5: std_logic;
- signal tsum14: std_logic;
- signal tsum15: std_logic;
- signal co6: std_logic;
- signal co7d: std_logic;
- signal co7: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- attribute GSR : string;
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- FF_16: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum15, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum15);
-
- FF_15: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum14, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum14);
-
- FF_14: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum13, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum13);
-
- FF_13: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum12, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum12);
-
- FF_12: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum11, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum11);
-
- FF_11: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum10, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum10);
-
- FF_10: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum9, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum9);
-
- FF_9: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum8, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum8);
-
- FF_8: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum7, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum7);
-
- FF_7: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum6, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum6);
-
- FF_6: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum5, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum5);
-
- FF_5: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum4, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum4);
-
- FF_4: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum3, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum3);
-
- FF_3: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum2, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum2);
-
- FF_2: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum1, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum1);
-
- FF_1: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum0, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum0);
-
- FF_0: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>co7d, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>addsub_cod_0);
-
- addsub_0: FADD2B
- port map (A0=>DataA(0), A1=>DataA(1), B0=>DataB(0), B1=>DataB(1),
- CI=>scuba_vlo, COUT=>co0, S0=>tsum0, S1=>tsum1);
-
- addsub_1: FADD2B
- port map (A0=>DataA(2), A1=>DataA(3), B0=>DataB(2), B1=>DataB(3),
- CI=>co0, COUT=>co1, S0=>tsum2, S1=>tsum3);
-
- addsub_2: FADD2B
- port map (A0=>DataA(4), A1=>DataA(5), B0=>DataB(4), B1=>DataB(5),
- CI=>co1, COUT=>co2, S0=>tsum4, S1=>tsum5);
-
- addsub_3: FADD2B
- port map (A0=>DataA(6), A1=>DataA(7), B0=>DataB(6), B1=>DataB(7),
- CI=>co2, COUT=>co3, S0=>tsum6, S1=>tsum7);
-
- addsub_4: FADD2B
- port map (A0=>DataA(8), A1=>DataA(9), B0=>DataB(8), B1=>DataB(9),
- CI=>co3, COUT=>co4, S0=>tsum8, S1=>tsum9);
-
- addsub_5: FADD2B
- port map (A0=>DataA(10), A1=>DataA(11), B0=>DataB(10),
- B1=>DataB(11), CI=>co4, COUT=>co5, S0=>tsum10, S1=>tsum11);
-
- addsub_6: FADD2B
- port map (A0=>DataA(12), A1=>DataA(13), B0=>DataB(12),
- B1=>DataB(13), CI=>co5, COUT=>co6, S0=>tsum12, S1=>tsum13);
-
- addsub_7: FADD2B
- port map (A0=>DataA(14), A1=>DataA(15), B0=>DataB(14),
- B1=>DataB(15), CI=>co6, COUT=>co7, S0=>tsum14, S1=>tsum15);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- addsubd: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co7, COUT=>open, S0=>co7d, S1=>open);
-
- Result(15) <= r0_sum15;
- Result(14) <= r0_sum14;
- Result(13) <= r0_sum13;
- Result(12) <= r0_sum12;
- Result(11) <= r0_sum11;
- Result(10) <= r0_sum10;
- Result(9) <= r0_sum9;
- Result(8) <= r0_sum8;
- Result(7) <= r0_sum7;
- Result(6) <= r0_sum6;
- Result(5) <= r0_sum5;
- Result(4) <= r0_sum4;
- Result(3) <= r0_sum3;
- Result(2) <= r0_sum2;
- Result(1) <= r0_sum1;
- Result(0) <= r0_sum0;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of adder_16bit is
- for Structure
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
--- Module Version: 3.1
--- Tue Mar 03 10:27:46 2009
-
--- parameterized module component declaration
-component adder_16bit
- port (DataA: in std_logic_vector(15 downto 0);
- DataB: in std_logic_vector(15 downto 0); Clock: in std_logic;
- Reset: in std_logic; ClockEn: in std_logic;
- Result: out std_logic_vector(15 downto 0));
-end component;
-
--- parameterized module component instance
-__ : adder_16bit
- port map (DataA(15 downto 0)=>__, DataB(15 downto 0)=>__, Clock=>__,
- Reset=>__, ClockEn=>__, Result(15 downto 0)=>__);
+++ /dev/null
-[Device]\r
-Family=latticeecp2m\r
-PartType=LFE2M100E\r
-PartName=LFE2M100E-6F900C\r
-SpeedGrade=-6\r
-Package=FPBGA900\r
-OperatingCondition=COM\r
-Status=P\r
-\r
-[IP]\r
-VendorName=Lattice Semiconductor Corporation\r
-CoreType=LPM\r
-CoreStatus=Demo\r
-CoreName=Adder\r
-CoreRevision=3.1\r
-ModuleName=adder_5bit\r
-SourceFormat=VHDL\r
-ParameterFileVersion=1.0\r
-Date=03/03/2009\r
-Time=10:10:12\r
-\r
-[Parameters]\r
-Verilog=0\r
-VHDL=1\r
-EDIF=1\r
-Destination=Synplicity\r
-Expression=BusA(0 to 7)\r
-Order=Big Endian [MSB:LSB]\r
-IO=0\r
-InputWidth=5\r
-Representation=Unsigned\r
-UseCIport=0\r
-COport=None\r
-OutReg=1\r
-Complex=0\r
-Stage=0\r
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24)
--- Module Version: 3.1
---X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type add -width 5 -unsigned -output_reg -enable -e
-
--- Tue Mar 03 10:10:12 2009
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity adder_5bit is
- port (
- DataA: in std_logic_vector(4 downto 0);
- DataB: in std_logic_vector(4 downto 0);
- Clock: in std_logic;
- Reset: in std_logic;
- ClockEn: in std_logic;
- Result: out std_logic_vector(4 downto 0));
-end adder_5bit;
-
-architecture Structure of adder_5bit is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal r0_sum4: std_logic;
- signal r0_sum3: std_logic;
- signal r0_sum2: std_logic;
- signal r0_sum1: std_logic;
- signal r0_sum0: std_logic;
- signal tsum0: std_logic;
- signal tsum1: std_logic;
- signal tsum2: std_logic;
- signal tsum3: std_logic;
- signal co0: std_logic;
- signal tsum4: std_logic;
- signal co1: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- attribute GSR : string;
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- FF_4: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum4, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum4);
-
- FF_3: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum3, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum3);
-
- FF_2: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum2, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum2);
-
- FF_1: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum1, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum1);
-
- FF_0: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum0, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum0);
-
- addsub_0: FADD2B
- port map (A0=>DataA(0), A1=>DataA(1), B0=>DataB(0), B1=>DataB(1),
- CI=>scuba_vlo, COUT=>co0, S0=>tsum0, S1=>tsum1);
-
- addsub_1: FADD2B
- port map (A0=>DataA(2), A1=>DataA(3), B0=>DataB(2), B1=>DataB(3),
- CI=>co0, COUT=>co1, S0=>tsum2, S1=>tsum3);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- addsub_2: FADD2B
- port map (A0=>DataA(4), A1=>scuba_vlo, B0=>DataB(4),
- B1=>scuba_vlo, CI=>co1, COUT=>open, S0=>tsum4, S1=>open);
-
- Result(4) <= r0_sum4;
- Result(3) <= r0_sum3;
- Result(2) <= r0_sum2;
- Result(1) <= r0_sum1;
- Result(0) <= r0_sum0;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of adder_5bit is
- for Structure
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
--- Module Version: 3.1
--- Tue Mar 03 10:10:12 2009
-
--- parameterized module component declaration
-component adder_5bit
- port (DataA: in std_logic_vector(4 downto 0);
- DataB: in std_logic_vector(4 downto 0); Clock: in std_logic;
- Reset: in std_logic; ClockEn: in std_logic;
- Result: out std_logic_vector(4 downto 0));
-end component;
-
--- parameterized module component instance
-__ : adder_5bit
- port map (DataA(4 downto 0)=>__, DataB(4 downto 0)=>__, Clock=>__,
- Reset=>__, ClockEn=>__, Result(4 downto 0)=>__);
+++ /dev/null
-[Device]\r
-Family=latticeecp2m\r
-PartType=LFE2M35E\r
-PartName=LFE2M35E-6F672C\r
-SpeedGrade=-6\r
-Package=FPBGA672\r
-OperatingCondition=COM\r
-Status=P\r
-\r
-[IP]\r
-VendorName=Lattice Semiconductor Corporation\r
-CoreType=LPM\r
-CoreStatus=Demo\r
-CoreName=Adder\r
-CoreRevision=3.1\r
-ModuleName=adder_6bit\r
-SourceFormat=VHDL\r
-ParameterFileVersion=1.0\r
-Date=08/27/2008\r
-Time=11:31:51\r
-\r
-[Parameters]\r
-Verilog=0\r
-VHDL=1\r
-EDIF=1\r
-Destination=Synplicity\r
-Expression=BusA(0 to 7)\r
-Order=Big Endian [MSB:LSB]\r
-IO=0\r
-InputWidth=6\r
-Representation=Unsigned\r
-UseCIport=0\r
-COport=None\r
-OutReg=1\r
-Complex=0\r
-Stage=0\r
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58)
--- Module Version: 3.1
---X:\Programme\ispTOOLS_71\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type add -width 6 -unsigned -output_reg -enable -e
-
--- Wed Aug 27 11:31:51 2008
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity adder_6bit is
- port (
- DataA: in std_logic_vector(5 downto 0);
- DataB: in std_logic_vector(5 downto 0);
- Clock: in std_logic;
- Reset: in std_logic;
- ClockEn: in std_logic;
- Result: out std_logic_vector(5 downto 0));
-end adder_6bit;
-
-architecture Structure of adder_6bit is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal r0_sum5: std_logic;
- signal r0_sum4: std_logic;
- signal r0_sum3: std_logic;
- signal r0_sum2: std_logic;
- signal r0_sum1: std_logic;
- signal r0_sum0: std_logic;
- signal addsub_cod_0: std_logic;
- signal tsum0: std_logic;
- signal tsum1: std_logic;
- signal tsum2: std_logic;
- signal tsum3: std_logic;
- signal co0: std_logic;
- signal tsum4: std_logic;
- signal tsum5: std_logic;
- signal co1: std_logic;
- signal co2d: std_logic;
- signal co2: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- attribute GSR : string;
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- FF_6: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum5, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum5);
-
- FF_5: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum4, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum4);
-
- FF_4: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum3, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum3);
-
- FF_3: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum2, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum2);
-
- FF_2: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum1, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum1);
-
- FF_1: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tsum0, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_sum0);
-
- FF_0: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>co2d, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>addsub_cod_0);
-
- addsub_0: FADD2B
- port map (A0=>DataA(0), A1=>DataA(1), B0=>DataB(0), B1=>DataB(1),
- CI=>scuba_vlo, COUT=>co0, S0=>tsum0, S1=>tsum1);
-
- addsub_1: FADD2B
- port map (A0=>DataA(2), A1=>DataA(3), B0=>DataB(2), B1=>DataB(3),
- CI=>co0, COUT=>co1, S0=>tsum2, S1=>tsum3);
-
- addsub_2: FADD2B
- port map (A0=>DataA(4), A1=>DataA(5), B0=>DataB(4), B1=>DataB(5),
- CI=>co1, COUT=>co2, S0=>tsum4, S1=>tsum5);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- addsubd: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co2, COUT=>open, S0=>co2d, S1=>open);
-
- Result(5) <= r0_sum5;
- Result(4) <= r0_sum4;
- Result(3) <= r0_sum3;
- Result(2) <= r0_sum2;
- Result(1) <= r0_sum1;
- Result(0) <= r0_sum0;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of adder_6bit is
- for Structure
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v71_PROD_Build (58)
--- Module Version: 3.1
--- Wed Aug 27 11:31:51 2008
-
--- parameterized module component declaration
-component adder_6bit
- port (DataA: in std_logic_vector(5 downto 0);
- DataB: in std_logic_vector(5 downto 0); Clock: in std_logic;
- Reset: in std_logic; ClockEn: in std_logic;
- Result: out std_logic_vector(5 downto 0));
-end component;
-
--- parameterized module component instance
-__ : adder_6bit
- port map (DataA(5 downto 0)=>__, DataB(5 downto 0)=>__, Clock=>__,
- Reset=>__, ClockEn=>__, Result(5 downto 0)=>__);
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)
-Wed Nov 04 16:10:56 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_adc_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem -memformat orca -e
- Circuit name : apv_adc_map_mem
- Module type : rom
- Module Version : 2.4
- Address width : 7
- Ports :
- Inputs : Address[6:0]
- Outputs : Q[3:0]
- I/O buffer : not inserted
- Memory file : i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem
- EDIF output : suppressed
- VHDL output : apv_adc_map_mem.vhd
- VHDL template : apv_adc_map_mem_tmpl.vhd
- VHDL testbench : tb_apv_adc_map_mem_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : apv_adc_map_mem.srp
- Element Usage :
- ROM128X1 : 4
- Estimated Resource Usage:
- LUT : 16
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Wed Nov 04 16:10:56 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_adc_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem -memformat orca -e \r
- Circuit name : apv_adc_map_mem\r
- Module type : rom\r
- Module Version : 2.4\r
- Address width : 7\r
- Data width : 4\r
- Ports : \r
- Inputs : Address[6:0]\r
- Outputs : Q[3:0]\r
- I/O buffer : not inserted\r
- Memory file : i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem\r
- EDIF output : suppressed\r
- VHDL output : apv_adc_map_mem.vhd\r
- VHDL template : apv_adc_map_mem_tmpl.vhd\r
- VHDL testbench : tb_apv_adc_map_mem_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : apv_adc_map_mem.srp\r
- Estimated Resource Usage:\r
- LUT : 16\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: ..\src\apv_adc_map_mem.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 2.4
--- Wed Nov 04 16:10:56 2009
-
--- parameterized module component declaration
-component apv_adc_map_mem
- port (Address: in std_logic_vector(6 downto 0);
- Q: out std_logic_vector(3 downto 0));
-end component;
-
--- parameterized module component instance
-__ : apv_adc_map_mem
- port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__);
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)
-Wed Oct 14 17:47:59 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv2/src/apv_mapping.mem -memformat orca -e
- Circuit name : apv_map_mem
- Module type : rom
- Module Version : 2.4
- Address width : 7
- Ports :
- Inputs : Address[6:0]
- Outputs : Q[3:0]
- I/O buffer : not inserted
- Memory file : i:/vhdl_pro/adcmv2/src/apv_mapping.mem
- EDIF output : suppressed
- VHDL output : apv_map_mem.vhd
- VHDL template : apv_map_mem_tmpl.vhd
- VHDL testbench : tb_apv_map_mem_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : apv_map_mem.srp
- Element Usage :
- ROM128X1 : 4
- Estimated Resource Usage:
- LUT : 16
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Wed Oct 14 17:47:59 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv2/src/apv_mapping.mem -memformat orca -e \r
- Circuit name : apv_map_mem\r
- Module type : rom\r
- Module Version : 2.4\r
- Address width : 7\r
- Data width : 4\r
- Ports : \r
- Inputs : Address[6:0]\r
- Outputs : Q[3:0]\r
- I/O buffer : not inserted\r
- Memory file : i:/vhdl_pro/adcmv2/src/apv_mapping.mem\r
- EDIF output : suppressed\r
- VHDL output : apv_map_mem.vhd\r
- VHDL template : apv_map_mem_tmpl.vhd\r
- VHDL testbench : tb_apv_map_mem_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : apv_map_mem.srp\r
- Estimated Resource Usage:\r
- LUT : 16\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: ..\src\apv_map_mem.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 2.4
--- Wed Oct 14 17:47:59 2009
-
--- parameterized module component declaration
-component apv_map_mem
- port (Address: in std_logic_vector(6 downto 0);
- Q: out std_logic_vector(3 downto 0));
-end component;
-
--- parameterized module component instance
-__ : apv_map_mem
- port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__);
+++ /dev/null
-[Device]\r
-Family=latticeecp2m\r
-PartType=LFE2M100E\r
-PartName=LFE2M100E-6F900C\r
-SpeedGrade=-6\r
-Package=FPBGA900\r
-OperatingCondition=COM\r
-Status=P\r
-\r
-[IP]\r
-VendorName=Lattice Semiconductor Corporation\r
-CoreType=LPM\r
-CoreStatus=Demo\r
-CoreName=Comparator\r
-CoreRevision=3.1\r
-ModuleName=comp14bit\r
-SourceFormat=VHDL\r
-ParameterFileVersion=1.0\r
-Date=02/26/2009\r
-Time=14:35:12\r
-\r
-[Parameters]\r
-Verilog=0\r
-VHDL=1\r
-EDIF=1\r
-Destination=Synplicity\r
-Expression=BusA(0 to 7)\r
-Order=Big Endian [MSB:LSB]\r
-IO=0\r
-InputWidth=14\r
-FuncComparator= A >= B\r
-ReprComparator=Unsigned\r
-Lut=0\r
-OutReg=1\r
-Stage=0\r
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v72_PROD_Build (44)
--- Module Version: 3.1
---X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n comp14bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type comp -width 14 -unsigned -port ageb -output_reg -enable -pipeline 0 -e
-
--- Thu Feb 26 14:35:13 2009
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity comp14bit is
- port (
- DataA: in std_logic_vector(13 downto 0);
- DataB: in std_logic_vector(13 downto 0);
- Clock: in std_logic;
- ClockEn: in std_logic;
- Aclr: in std_logic;
- AGEB: out std_logic);
-end comp14bit;
-
-architecture Structure of comp14bit is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal cmp_ci: std_logic;
- signal co0: std_logic;
- signal co1: std_logic;
- signal co2: std_logic;
- signal co3: std_logic;
- signal co4: std_logic;
- signal co5: std_logic;
- signal ageb_out: std_logic;
- signal ageb_out_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- attribute GSR : string;
- attribute GSR of FF_0 : label is "ENABLED";
-
-begin
- -- component instantiation statements
- FF_0: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>ageb_out, SP=>ClockEn, CK=>Clock, CD=>Aclr, Q=>AGEB);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- cmp_ci_a: FADD2B
- port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
- S1=>open);
-
- cmp_0: AGEB2
- port map (A0=>DataA(0), A1=>DataA(1), B0=>DataB(0), B1=>DataB(1),
- CI=>cmp_ci, GE=>co0);
-
- cmp_1: AGEB2
- port map (A0=>DataA(2), A1=>DataA(3), B0=>DataB(2), B1=>DataB(3),
- CI=>co0, GE=>co1);
-
- cmp_2: AGEB2
- port map (A0=>DataA(4), A1=>DataA(5), B0=>DataB(4), B1=>DataB(5),
- CI=>co1, GE=>co2);
-
- cmp_3: AGEB2
- port map (A0=>DataA(6), A1=>DataA(7), B0=>DataB(6), B1=>DataB(7),
- CI=>co2, GE=>co3);
-
- cmp_4: AGEB2
- port map (A0=>DataA(8), A1=>DataA(9), B0=>DataB(8), B1=>DataB(9),
- CI=>co3, GE=>co4);
-
- cmp_5: AGEB2
- port map (A0=>DataA(10), A1=>DataA(11), B0=>DataB(10),
- B1=>DataB(11), CI=>co4, GE=>co5);
-
- cmp_6: AGEB2
- port map (A0=>DataA(12), A1=>DataA(13), B0=>DataB(12),
- B1=>DataB(13), CI=>co5, GE=>ageb_out_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>ageb_out_c, COUT=>open, S0=>ageb_out,
- S1=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of comp14bit is
- for Structure
- for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44)
--- Module Version: 3.1
--- Thu Feb 26 14:35:13 2009
-
--- parameterized module component declaration
-component comp14bit
- port (DataA: in std_logic_vector(13 downto 0);
- DataB: in std_logic_vector(13 downto 0); Clock: in std_logic;
- ClockEn: in std_logic; Aclr: in std_logic;
- AGEB: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : comp14bit
- port map (DataA(13 downto 0)=>__, DataB(13 downto 0)=>__, Clock=>__,
- ClockEn=>__, Aclr=>__, AGEB=>__);
+++ /dev/null
-[Device]\r
-Family=latticeecp2m\r
-PartType=LFE2M100E\r
-PartName=LFE2M100E-6F900C\r
-SpeedGrade=-6\r
-Package=FPBGA900\r
-OperatingCondition=COM\r
-Status=P\r
-\r
-[IP]\r
-VendorName=Lattice Semiconductor Corporation\r
-CoreType=LPM\r
-CoreStatus=Demo\r
-CoreName=Comparator\r
-CoreRevision=3.1\r
-ModuleName=comp4bit\r
-SourceFormat=VHDL\r
-ParameterFileVersion=1.0\r
-Date=10/09/2009\r
-Time=16:19:24\r
-\r
-[Parameters]\r
-Verilog=0\r
-VHDL=1\r
-EDIF=1\r
-Destination=Synplicity\r
-Expression=BusA(0 to 7)\r
-Order=Big Endian [MSB:LSB]\r
-IO=0\r
-InputWidth=4\r
-FuncComparator= A > B\r
-ReprComparator=Unsigned\r
-Lut=0\r
-OutReg=0\r
-Stage=0\r
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)
-Fri Oct 09 16:19:24 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n comp4bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type comp -width 4 -unsigned -port agtb -e
- Circuit name : comp4bit
- Module type : comp
- Module Version : 3.1
- Width : 4
- Ports :
- Inputs : DataA[3:0], DataB[3:0]
- Outputs : AGTB
- I/O buffer : not inserted
- Representation : unsigned number
- EDIF output : suppressed
- VHDL output : comp4bit.vhd
- VHDL template : comp4bit_tmpl.vhd
- VHDL testbench : tb_comp4bit_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : comp4bit.srp
- Element Usage :
- ALEB2 : 2
- FADD2B : 2
- INV : 1
- Estimated Resource Usage:
- LUT : 8
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 3.1
---X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n comp4bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type comp -width 4 -unsigned -port agtb -e
-
--- Fri Oct 09 16:19:24 2009
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity comp4bit is
- port (
- DataA: in std_logic_vector(3 downto 0);
- DataB: in std_logic_vector(3 downto 0);
- AGTB: out std_logic);
-end comp4bit;
-
-architecture Structure of comp4bit is
-
- -- internal signal declarations
- signal co1_inv: std_logic;
- signal scuba_vhi: std_logic;
- signal cmp_ci: std_logic;
- signal co0: std_logic;
- signal co1: std_logic;
- signal agtb_out_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component ALEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; LE: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- INV_0: INV
- port map (A=>co1, Z=>co1_inv);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- cmp_ci_a: FADD2B
- port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
- S1=>open);
-
- cmp_0: ALEB2
- port map (A0=>DataA(0), A1=>DataA(1), B0=>DataB(0), B1=>DataB(1),
- CI=>cmp_ci, LE=>co0);
-
- cmp_1: ALEB2
- port map (A0=>DataA(2), A1=>DataA(3), B0=>DataB(2), B1=>DataB(3),
- CI=>co0, LE=>agtb_out_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>agtb_out_c, COUT=>open, S0=>co1, S1=>open);
-
- AGTB <= co1_inv;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of comp4bit is
- for Structure
- for all:ALEB2 use entity ecp2m.ALEB2(V); end for;
- for all:FADD2B use entity ecp2m.FADD2B(V); end for;
- for all:INV use entity ecp2m.INV(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Fri Oct 09 16:19:24 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n comp4bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type comp -width 4 -unsigned -port agtb -e \r
- Circuit name : comp4bit\r
- Module type : comp\r
- Module Version : 3.1\r
- Width : 4\r
- Ports : \r
- Inputs : DataA[3:0], DataB[3:0]\r
- Outputs : AGTB\r
- I/O buffer : not inserted\r
- Representation : unsigned number\r
- EDIF output : suppressed\r
- VHDL output : comp4bit.vhd\r
- VHDL template : comp4bit_tmpl.vhd\r
- VHDL testbench : tb_comp4bit_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : comp4bit.srp\r
- Estimated Resource Usage:\r
- LUT : 8\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: comp4bit.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 3.1
--- Fri Oct 09 16:19:24 2009
-
--- parameterized module component declaration
-component comp4bit
- port (DataA: in std_logic_vector(3 downto 0);
- DataB: in std_logic_vector(3 downto 0); AGTB: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : comp4bit
- port map (DataA(3 downto 0)=>__, DataB(3 downto 0)=>__, AGTB=>__);
+++ /dev/null
-SCUBA, Version ispLever_v72_PROD_Build (44)
-Fri Nov 20 11:16:48 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n crossover -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -pfu_fifo -addr_width 4 -data_width 96 -num_words 16 -rdata_width 96 -no_enable -pe -1 -pf -1 -rfill -fill -e
- Circuit name : crossover
- Module type : ebfifo
- Module Version : 5.0
- Ports :
- Inputs : Data[95:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
- Outputs : Q[95:0], WCNT[4:0], RCNT[4:0], Empty, Full
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : crossover.vhd
- VHDL template : crossover_tmpl.vhd
- VHDL testbench : tb_crossover_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : crossover.srp
- Element Usage :
- AGEB2 : 6
- AND2 : 2
- CU2 : 6
- FADD2B : 8
- FSUB2B : 6
- FD1P3BX : 2
- FD1P3DX : 124
- FD1S3BX : 1
- FD1S3DX : 31
- INV : 2
- OR2 : 1
- ROM16X1 : 13
- DPR16X4A : 24
- XOR2 : 10
- Estimated Resource Usage:
- LUT : 78
- DRAM : 24
- Reg : 158
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_PROD_Build (44)\r
-Fri Nov 20 11:16:48 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n crossover -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -pfu_fifo -addr_width 4 -data_width 96 -num_words 16 -rdata_width 96 -no_enable -pe -1 -pf -1 -rfill -fill -e \r
- Circuit name : crossover\r
- Module type : ebfifo\r
- Module Version : 5.0\r
- Ports : \r
- Inputs : Data[95:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset\r
- Outputs : Q[95:0], WCNT[4:0], RCNT[4:0], Empty, Full\r
- I/O buffer : not inserted\r
- EDIF output : suppressed\r
- VHDL output : crossover.vhd\r
- VHDL template : crossover_tmpl.vhd\r
- VHDL testbench : tb_crossover_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : crossover.srp\r
- Estimated Resource Usage:\r
- LUT : 78\r
- DRAM : 24\r
- Reg : 158\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: ..\src\crossover.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44)
--- Module Version: 5.0
--- Fri Nov 20 11:16:48 2009
-
--- parameterized module component declaration
-component crossover
- port (Data: in std_logic_vector(95 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic; Q: out std_logic_vector(95 downto 0);
- WCNT: out std_logic_vector(4 downto 0);
- RCNT: out std_logic_vector(4 downto 0); Empty: out std_logic;
- Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : crossover
- port map (Data(95 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(95 downto 0)=>__, WCNT(4 downto 0)=>__,
- RCNT(4 downto 0)=>__, Empty=>__, Full=>__);
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
--- Module Version: 2.4
--- Tue Mar 03 09:38:59 2009
-
--- parameterized module component declaration
-component decoder_8bit
- port (Address: in std_logic_vector(7 downto 0);
- Q: out std_logic_vector(3 downto 0));
-end component;
-
--- parameterized module component instance
-__ : decoder_8bit
- port map (Address(7 downto 0)=>__, Q(3 downto 0)=>__);
+++ /dev/null
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
-\r
-library work;\r
-use work.adcmv3_components.all;\r
-\r
-entity dhdr_buf is\r
-port(\r
- CLK_IN : in std_logic; -- 100MHz master clock\r
- RESET_IN : in std_logic;\r
- -- DHDR information block\r
- DHDR_DATA_IN : in std_logic_vector(47 downto 0); -- EDS data input\r
- DHDR_WE_IN : in std_logic; -- EDS write enable\r
- DHDR_DONE_IN : in std_logic; -- release EDS\r
- DHDR_DATA_OUT : out std_logic_vector(47 downto 0);\r
- DHDR_AVAILABLE_OUT : out std_logic;\r
- -- trigger busy information\r
- BUF_FULL_OUT : out std_logic;\r
- BUF_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
- -- Debug signals\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
-);\r
-end;\r
-\r
-architecture behavioral of dhdr_buf is\r
-\r
--- normal signals\r
-signal debug : std_logic_vector(15 downto 0);\r
-\r
--- Signals for controlling the DHDR buffer memory\r
-signal dhdr_data : std_logic_vector(47 downto 0);\r
-signal dhdr_rd_addr : std_logic_vector(3 downto 0);\r
-signal dhdr_wr_addr : std_logic_vector(3 downto 0);\r
-signal dhdr_wr : std_logic;\r
-signal dhdr_rd : std_logic;\r
-signal dhdr_free_ctr : std_logic_vector(4 downto 0); -- fill level counter\r
-signal dhdr_free_up : std_logic;\r
-signal dhdr_free_down : std_logic;\r
-signal dhdr_available_x : std_logic;\r
-signal dhdr_available : std_logic; -- at least one valid EDS entry is available\r
-signal dhdr_full_x : std_logic;\r
-signal dhdr_full : std_logic;\r
-\r
-begin\r
-\r
--- General process for syncing combinatorial signals\r
-THE_SYNC_PROC: process( clk_in )\r
-begin\r
- if( rising_edge(clk_in) ) then\r
- dhdr_available <= dhdr_available_x;\r
- dhdr_full <= dhdr_full_x;\r
- end if;\r
-end process THE_SYNC_PROC;\r
-\r
--- Write address pointer for EDS buffer\r
-dhdr_wr <= dhdr_we_in;\r
-\r
-THE_WR_ADDR_PROC: process( clk_in )\r
-begin\r
- if( rising_edge(clk_in) ) then\r
- if ( reset_in = '1' ) then\r
- dhdr_wr_addr <= (others => '0');\r
- elsif( dhdr_wr = '1' ) then\r
- dhdr_wr_addr <= dhdr_wr_addr + 1;\r
- end if;\r
- end if;\r
-end process THE_WR_ADDR_PROC;\r
-\r
--- Read address pointer for EDS buffer\r
-dhdr_rd <= dhdr_done_in;\r
-\r
-THE_RD_ADDR_PROC: process( clk_in )\r
-begin\r
- if( rising_edge(clk_in) ) then\r
- if ( reset_in = '1' ) then\r
- dhdr_rd_addr <= (others => '0');\r
- elsif( dhdr_rd = '1' ) then\r
- dhdr_rd_addr <= dhdr_rd_addr + 1;\r
- end if;\r
- end if;\r
-end process THE_RD_ADDR_PROC;\r
-\r
--- Buffer fill level counter\r
-dhdr_free_down <= dhdr_we_in;\r
-dhdr_free_up <= dhdr_done_in;\r
-\r
-THE_DHDR_FREE_COUNTER_PROC: process( clk_in )\r
-begin\r
- if( rising_edge(clk_in) ) then\r
- if ( reset_in = '1' ) then\r
- dhdr_free_ctr <= b"10000";\r
- elsif( (dhdr_free_down = '1') and (dhdr_free_up = '0') ) then\r
- dhdr_free_ctr <= dhdr_free_ctr - 1;\r
- elsif( (dhdr_free_down = '0') and (dhdr_free_up = '1') ) then\r
- dhdr_free_ctr <= dhdr_free_ctr + 1;\r
- end if;\r
- end if;\r
-end process THE_DHDR_FREE_COUNTER_PROC;\r
-\r
-dhdr_full_x <= '1' when (dhdr_free_ctr = b"00001") else '0'; -- was zero before\r
-dhdr_available_x <= '1' when (dhdr_free_ctr /= b"10000") else '0'; \r
--- danger. may also fail in case you release an entry before reserving it!\r
-\r
--- replace this ugly rd/wr/free counters and the DPRAM by a FIFO.\r
-\r
--- A 16x32b DPRAM is used for buffering the DataHeaDeR (DHDR)\r
-THE_DHDR_BUFFER: dhdr_buffer_dpram\r
-port map(\r
- WRADDRESS => dhdr_wr_addr,\r
- DATA => dhdr_data_in,\r
- WRCLOCK => clk_in,\r
- WE => dhdr_we_in,\r
- WRCLOCKEN => '1',\r
- RDADDRESS => dhdr_rd_addr,\r
- RDCLOCK => clk_in,\r
- RDCLOCKEN => '1',\r
- RESET => reset_in,\r
- Q => dhdr_data\r
-);\r
-\r
--- Are there any EDS to work on?\r
---dhdr_available_x <= '1' when (dhdr_wr_addr /= dhdr_rd_addr) else '0';\r
--- Epic fail: take 17 fast triggers => WR_ADDR = 1.\r
--- one slow IPU transfer => RD_ADDR = 1.\r
--- and as (1 /= 1) is false, the buffer is empty, blocking the next IPU transfer.\r
-\r
--- Debug signals\r
-debug(15 downto 0) <= (others => '0');\r
-\r
--- Output signals\r
-dhdr_data_out <= dhdr_data;\r
-dhdr_available_out <= dhdr_available;\r
-buf_full_out <= dhdr_full;\r
-buf_level_out <= dhdr_free_ctr;\r
-debug_out <= debug;\r
-\r
-end behavioral;\r
+++ /dev/null
-[Device]\r
-Family=latticeecp2m\r
-PartType=LFE2M100E\r
-PartName=LFE2M100E-6F900C\r
-SpeedGrade=-6\r
-Package=FPBGA900\r
-OperatingCondition=COM\r
-Status=P\r
-\r
-[IP]\r
-VendorName=Lattice Semiconductor Corporation\r
-CoreType=LPM\r
-CoreStatus=Demo\r
-CoreName=Distributed_DPRAM\r
-CoreRevision=3.4\r
-ModuleName=dhdr_buffer_dpram\r
-SourceFormat=VHDL\r
-ParameterFileVersion=1.0\r
-Date=03/03/2009\r
-Time=16:49:44\r
-\r
-[Parameters]\r
-Verilog=0\r
-VHDL=1\r
-EDIF=1\r
-Destination=Synplicity\r
-Expression=BusA(0 to 7)\r
-Order=Big Endian [MSB:LSB]\r
-IO=0\r
-Addresses=16\r
-Data=48\r
-LUT=1\r
-MemFile=\r
-MemFormat=orca\r
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24)
--- Module Version: 3.4
---X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type sdpram -rdata_width 48 -data_width 48 -num_rows 16 -outData REGISTERED -e
-
--- Tue Mar 03 16:49:44 2009
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity dhdr_buffer_dpram is
- port (
- WrAddress: in std_logic_vector(3 downto 0);
- Data: in std_logic_vector(47 downto 0);
- WrClock: in std_logic;
- WE: in std_logic;
- WrClockEn: in std_logic;
- RdAddress: in std_logic_vector(3 downto 0);
- RdClock: in std_logic;
- RdClockEn: in std_logic;
- Reset: in std_logic;
- Q: out std_logic_vector(47 downto 0));
-end dhdr_buffer_dpram;
-
-architecture Structure of dhdr_buffer_dpram is
-
- -- internal signal declarations
- signal scuba_vlo: std_logic;
- signal scuba_vhi: std_logic;
- signal dataout47_ffin: std_logic;
- signal dataout46_ffin: std_logic;
- signal dataout45_ffin: std_logic;
- signal dataout44_ffin: std_logic;
- signal dataout43_ffin: std_logic;
- signal dataout42_ffin: std_logic;
- signal dataout41_ffin: std_logic;
- signal dataout40_ffin: std_logic;
- signal dataout39_ffin: std_logic;
- signal dataout38_ffin: std_logic;
- signal dataout37_ffin: std_logic;
- signal dataout36_ffin: std_logic;
- signal dataout35_ffin: std_logic;
- signal dataout34_ffin: std_logic;
- signal dataout33_ffin: std_logic;
- signal dataout32_ffin: std_logic;
- signal dataout31_ffin: std_logic;
- signal dataout30_ffin: std_logic;
- signal dataout29_ffin: std_logic;
- signal dataout28_ffin: std_logic;
- signal dataout27_ffin: std_logic;
- signal dataout26_ffin: std_logic;
- signal dataout25_ffin: std_logic;
- signal dataout24_ffin: std_logic;
- signal dataout23_ffin: std_logic;
- signal dataout22_ffin: std_logic;
- signal dataout21_ffin: std_logic;
- signal dataout20_ffin: std_logic;
- signal dataout19_ffin: std_logic;
- signal dataout18_ffin: std_logic;
- signal dataout17_ffin: std_logic;
- signal dataout16_ffin: std_logic;
- signal dataout15_ffin: std_logic;
- signal dataout14_ffin: std_logic;
- signal dataout13_ffin: std_logic;
- signal dataout12_ffin: std_logic;
- signal dataout11_ffin: std_logic;
- signal dataout10_ffin: std_logic;
- signal dataout9_ffin: std_logic;
- signal dataout8_ffin: std_logic;
- signal dataout7_ffin: std_logic;
- signal dataout6_ffin: std_logic;
- signal dataout5_ffin: std_logic;
- signal dataout4_ffin: std_logic;
- signal dataout3_ffin: std_logic;
- signal dataout2_ffin: std_logic;
- signal dataout1_ffin: std_logic;
- signal dataout0_ffin: std_logic;
- signal dec0_wre3: std_logic;
-
- -- local component declarations
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component ROM16X1
- -- synopsys translate_off
- generic (initval : in String);
- -- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component DPR16X4A
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; WCK: in std_logic; WRE: in std_logic;
- RAD0: in std_logic; RAD1: in std_logic;
- RAD2: in std_logic; RAD3: in std_logic;
- WAD0: in std_logic; WAD1: in std_logic;
- WAD2: in std_logic; WAD3: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- attribute initval : string;
- attribute GSR : string;
- attribute initval of LUT4_0 : label is "0x8000";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
-
-begin
- -- component instantiation statements
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- LUT4_0: ROM16X1
- -- synopsys translate_off
- generic map (initval=> "0x8000")
- -- synopsys translate_on
- port map (AD3=>WE, AD2=>WrClockEn, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec0_wre3);
-
- FF_47: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout47_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(47));
-
- FF_46: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout46_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(46));
-
- FF_45: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout45_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(45));
-
- FF_44: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout44_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(44));
-
- FF_43: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout43_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(43));
-
- FF_42: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout42_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(42));
-
- FF_41: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout41_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(41));
-
- FF_40: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout40_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(40));
-
- FF_39: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout39_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(39));
-
- FF_38: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout38_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(38));
-
- FF_37: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout37_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(37));
-
- FF_36: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout36_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(36));
-
- FF_35: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout35_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(35));
-
- FF_34: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout34_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(34));
-
- FF_33: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout33_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(33));
-
- FF_32: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout32_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(32));
-
- FF_31: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout31_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(31));
-
- FF_30: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout30_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(30));
-
- FF_29: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout29_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(29));
-
- FF_28: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout28_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(28));
-
- FF_27: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout27_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(27));
-
- FF_26: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout26_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(26));
-
- FF_25: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout25_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(25));
-
- FF_24: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout24_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(24));
-
- FF_23: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout23_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(23));
-
- FF_22: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout22_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(22));
-
- FF_21: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout21_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(21));
-
- FF_20: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout20_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(20));
-
- FF_19: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout19_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(19));
-
- FF_18: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout18_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(18));
-
- FF_17: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout17_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(17));
-
- FF_16: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout16_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(16));
-
- FF_15: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout15_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(15));
-
- FF_14: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout14_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(14));
-
- FF_13: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout13_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(13));
-
- FF_12: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout12_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(12));
-
- FF_11: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout11_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(11));
-
- FF_10: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout10_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(10));
-
- FF_9: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout9_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(9));
-
- FF_8: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout8_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(8));
-
- FF_7: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout7_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(7));
-
- FF_6: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout6_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(6));
-
- FF_5: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout5_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(5));
-
- FF_4: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout4_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(4));
-
- FF_3: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout3_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(3));
-
- FF_2: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout2_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(2));
-
- FF_1: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout1_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(1));
-
- FF_0: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>dataout0_ffin, SP=>RdClockEn, CK=>RdClock,
- CD=>Reset, Q=>Q(0));
-
- mem_0_0: DPR16X4A
- port map (DI0=>Data(44), DI1=>Data(45), DI2=>Data(46),
- DI3=>Data(47), WCK=>WrClock, WRE=>dec0_wre3,
- RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
- RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
- WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout44_ffin,
- DO1=>dataout45_ffin, DO2=>dataout46_ffin,
- DO3=>dataout47_ffin);
-
- mem_0_1: DPR16X4A
- port map (DI0=>Data(40), DI1=>Data(41), DI2=>Data(42),
- DI3=>Data(43), WCK=>WrClock, WRE=>dec0_wre3,
- RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
- RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
- WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout40_ffin,
- DO1=>dataout41_ffin, DO2=>dataout42_ffin,
- DO3=>dataout43_ffin);
-
- mem_0_2: DPR16X4A
- port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
- DI3=>Data(39), WCK=>WrClock, WRE=>dec0_wre3,
- RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
- RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
- WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout36_ffin,
- DO1=>dataout37_ffin, DO2=>dataout38_ffin,
- DO3=>dataout39_ffin);
-
- mem_0_3: DPR16X4A
- port map (DI0=>Data(32), DI1=>Data(33), DI2=>Data(34),
- DI3=>Data(35), WCK=>WrClock, WRE=>dec0_wre3,
- RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
- RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
- WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout32_ffin,
- DO1=>dataout33_ffin, DO2=>dataout34_ffin,
- DO3=>dataout35_ffin);
-
- mem_0_4: DPR16X4A
- port map (DI0=>Data(28), DI1=>Data(29), DI2=>Data(30),
- DI3=>Data(31), WCK=>WrClock, WRE=>dec0_wre3,
- RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
- RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
- WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout28_ffin,
- DO1=>dataout29_ffin, DO2=>dataout30_ffin,
- DO3=>dataout31_ffin);
-
- mem_0_5: DPR16X4A
- port map (DI0=>Data(24), DI1=>Data(25), DI2=>Data(26),
- DI3=>Data(27), WCK=>WrClock, WRE=>dec0_wre3,
- RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
- RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
- WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout24_ffin,
- DO1=>dataout25_ffin, DO2=>dataout26_ffin,
- DO3=>dataout27_ffin);
-
- mem_0_6: DPR16X4A
- port map (DI0=>Data(20), DI1=>Data(21), DI2=>Data(22),
- DI3=>Data(23), WCK=>WrClock, WRE=>dec0_wre3,
- RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
- RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
- WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout20_ffin,
- DO1=>dataout21_ffin, DO2=>dataout22_ffin,
- DO3=>dataout23_ffin);
-
- mem_0_7: DPR16X4A
- port map (DI0=>Data(16), DI1=>Data(17), DI2=>Data(18),
- DI3=>Data(19), WCK=>WrClock, WRE=>dec0_wre3,
- RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
- RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
- WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout16_ffin,
- DO1=>dataout17_ffin, DO2=>dataout18_ffin,
- DO3=>dataout19_ffin);
-
- mem_0_8: DPR16X4A
- port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14),
- DI3=>Data(15), WCK=>WrClock, WRE=>dec0_wre3,
- RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
- RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
- WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout12_ffin,
- DO1=>dataout13_ffin, DO2=>dataout14_ffin,
- DO3=>dataout15_ffin);
-
- mem_0_9: DPR16X4A
- port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10),
- DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3,
- RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
- RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
- WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout8_ffin,
- DO1=>dataout9_ffin, DO2=>dataout10_ffin, DO3=>dataout11_ffin);
-
- mem_0_10: DPR16X4A
- port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7),
- WCK=>WrClock, WRE=>dec0_wre3, RAD0=>RdAddress(0),
- RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3),
- WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2),
- WAD3=>WrAddress(3), DO0=>dataout4_ffin, DO1=>dataout5_ffin,
- DO2=>dataout6_ffin, DO3=>dataout7_ffin);
-
- mem_0_11: DPR16X4A
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- WCK=>WrClock, WRE=>dec0_wre3, RAD0=>RdAddress(0),
- RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3),
- WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2),
- WAD3=>WrAddress(3), DO0=>dataout0_ffin, DO1=>dataout1_ffin,
- DO2=>dataout2_ffin, DO3=>dataout3_ffin);
-
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of dhdr_buffer_dpram is
- for Structure
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
- for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
--- Module Version: 3.4
--- Tue Mar 03 16:49:44 2009
-
--- parameterized module component declaration
-component dhdr_buffer_dpram
- port (WrAddress: in std_logic_vector(3 downto 0);
- Data: in std_logic_vector(47 downto 0); WrClock: in std_logic;
- WE: in std_logic; WrClockEn: in std_logic;
- RdAddress: in std_logic_vector(3 downto 0);
- RdClock: in std_logic; RdClockEn: in std_logic;
- Reset: in std_logic; Q: out std_logic_vector(47 downto 0));
-end component;
-
--- parameterized module component instance
-__ : dhdr_buffer_dpram
- port map (WrAddress(3 downto 0)=>__, Data(47 downto 0)=>__, WrClock=>__,
- WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, RdClock=>__,
- RdClockEn=>__, Reset=>__, Q(47 downto 0)=>__);
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44)
--- Module Version: 3.2
--- Thu Jan 29 18:49:16 2009
-
--- parameterized module component declaration
-component dll_100m
- port (clk: in std_logic; resetn: in std_logic;
- aluhold: in std_logic; clkop: out std_logic;
- clkos: out std_logic; lock: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : dll_100m
- port map (clk=>__, resetn=>__, aluhold=>__, clkop=>__, clkos=>__,
- lock=>__);
+++ /dev/null
-SCUBA, Version ispLever_v72_PROD_Build (44)
-Fri Nov 20 19:14:28 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n dpram_8x19 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 19 -waddr_width 4 -wwidth 19 -rnum_words 16 -wnum_words 16 -outData UNREGISTERED -e
- Circuit name : dpram_8x19
- Module type : sdpram
- Module Version : 3.4
- Address width : 4
- Ports :
- Inputs : WrAddress[3:0], Data[18:0], WrClock, WE, WrClockEn, RdAddress[3:0]
- Outputs : Q[18:0]
- I/O buffer : not inserted
- Clock edge : rising edge
- EDIF output : suppressed
- VHDL output : dpram_8x19.vhd
- VHDL template : dpram_8x19_tmpl.vhd
- VHDL testbench : tb_dpram_8x19_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : dpram_8x19.srp
- Element Usage :
- ROM16X1 : 1
- DPR16X4A : 5
- Estimated Resource Usage:
- LUT : 1
- DRAM : 5
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_PROD_Build (44)\r
-Fri Nov 20 19:14:28 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n dpram_8x19 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 19 -waddr_width 4 -wwidth 19 -rnum_words 16 -wnum_words 16 -outData UNREGISTERED -e \r
- Circuit name : dpram_8x19\r
- Module type : sdpram\r
- Module Version : 3.4\r
- Address width : 4\r
- Data width : 19\r
- Ports : \r
- Inputs : WrAddress[3:0], Data[18:0], WrClock, WE, WrClockEn, RdAddress[3:0]\r
- Outputs : Q[18:0]\r
- I/O buffer : not inserted\r
- Clock edge : rising edge\r
- EDIF output : suppressed\r
- VHDL output : dpram_8x19.vhd\r
- VHDL template : dpram_8x19_tmpl.vhd\r
- VHDL testbench : tb_dpram_8x19_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : dpram_8x19.srp\r
- Estimated Resource Usage:\r
- LUT : 1\r
- DRAM : 5\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: ..\src\dpram_8x19.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44)
--- Module Version: 3.4
--- Fri Nov 20 19:14:28 2009
-
--- parameterized module component declaration
-component dpram_8x19
- port (WrAddress: in std_logic_vector(3 downto 0);
- Data: in std_logic_vector(18 downto 0); WrClock: in std_logic;
- WE: in std_logic; WrClockEn: in std_logic;
- RdAddress: in std_logic_vector(3 downto 0);
- Q: out std_logic_vector(18 downto 0));
-end component;
-
--- parameterized module component instance
-__ : dpram_8x19
- port map (WrAddress(3 downto 0)=>__, Data(18 downto 0)=>__, WrClock=>__,
- WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, Q(18 downto 0)=>__);
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v71_PROD_Build (58)
--- Module Version: 3.3
--- Fri Aug 29 14:24:36 2008
-
--- parameterized module component declaration
-component eds_buffer_dpram
- port (WrAddress: in std_logic_vector(3 downto 0);
- Data: in std_logic_vector(39 downto 0); WrClock: in std_logic;
- WE: in std_logic; WrClockEn: in std_logic;
- RdAddress: in std_logic_vector(3 downto 0);
- RdClock: in std_logic; RdClockEn: in std_logic;
- Reset: in std_logic; Q: out std_logic_vector(39 downto 0));
-end component;
-
--- parameterized module component instance
-__ : eds_buffer_dpram
- port map (WrAddress(3 downto 0)=>__, Data(39 downto 0)=>__, WrClock=>__,
- WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, RdClock=>__,
- RdClockEn=>__, Reset=>__, Q(39 downto 0)=>__);
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41)
--- Module Version: 4.7
--- Thu Mar 11 10:33:40 2010
-
--- parameterized module component declaration
-component fifo_16x11
- port (Data: in std_logic_vector(10 downto 0); Clock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- Q: out std_logic_vector(10 downto 0);
- WCNT: out std_logic_vector(4 downto 0); Empty: out std_logic;
- Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_16x11
- port map (Data(10 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__,
- Reset=>__, Q(10 downto 0)=>__, WCNT(4 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
--- Module Version: 4.5
--- Fri Feb 27 12:01:58 2009
-
--- parameterized module component declaration
-component fifo_2kx27
- port (Data: in std_logic_vector(26 downto 0); Clock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- Q: out std_logic_vector(26 downto 0);
- WCNT: out std_logic_vector(11 downto 0); Empty: out std_logic;
- Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : fifo_2kx27
- port map (Data(26 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__,
- Reset=>__, Q(26 downto 0)=>__, WCNT(11 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)
-Mon Sep 14 13:08:21 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n frame_status_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 12 -waddr_width 4 -wwidth 12 -rnum_words 16 -wnum_words 16 -outData REGISTERED -e
- Circuit name : frame_status_mem
- Module type : sdpram
- Module Version : 3.5
- Address width : 4
- Ports :
- Inputs : WrAddress[3:0], Data[11:0], WrClock, WE, WrClockEn, RdAddress[3:0], RdClock, RdClockEn, Reset
- Outputs : Q[11:0]
- I/O buffer : not inserted
- Clock edge : rising edge
- EDIF output : suppressed
- VHDL output : frame_status_mem.vhd
- VHDL template : frame_status_mem_tmpl.vhd
- VHDL testbench : tb_frame_status_mem_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : frame_status_mem.srp
- Element Usage :
- FD1P3DX : 12
- ROM16X1 : 1
- DPR16X4A : 3
- Estimated Resource Usage:
- LUT : 1
- DRAM : 3
- Reg : 12
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Mon Sep 14 13:08:21 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n frame_status_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 12 -waddr_width 4 -wwidth 12 -rnum_words 16 -wnum_words 16 -outData REGISTERED -e \r
- Circuit name : frame_status_mem\r
- Module type : sdpram\r
- Module Version : 3.5\r
- Address width : 4\r
- Data width : 12\r
- Ports : \r
- Inputs : WrAddress[3:0], Data[11:0], WrClock, WE, WrClockEn, RdAddress[3:0], RdClock, RdClockEn, Reset\r
- Outputs : Q[11:0]\r
- I/O buffer : not inserted\r
- Clock edge : rising edge\r
- EDIF output : suppressed\r
- VHDL output : frame_status_mem.vhd\r
- VHDL template : frame_status_mem_tmpl.vhd\r
- VHDL testbench : tb_frame_status_mem_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : frame_status_mem.srp\r
- Estimated Resource Usage:\r
- LUT : 1\r
- DRAM : 3\r
- Reg : 12\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: frame_status_mem.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 3.5
--- Mon Sep 14 13:08:21 2009
-
--- parameterized module component declaration
-component frame_status_mem
- port (WrAddress: in std_logic_vector(3 downto 0);
- Data: in std_logic_vector(11 downto 0); WrClock: in std_logic;
- WE: in std_logic; WrClockEn: in std_logic;
- RdAddress: in std_logic_vector(3 downto 0);
- RdClock: in std_logic; RdClockEn: in std_logic;
- Reset: in std_logic; Q: out std_logic_vector(11 downto 0));
-end component;
-
--- parameterized module component instance
-__ : frame_status_mem
- port map (WrAddress(3 downto 0)=>__, Data(11 downto 0)=>__, WrClock=>__,
- WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, RdClock=>__,
- RdClockEn=>__, Reset=>__, Q(11 downto 0)=>__);
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)
-Mon Sep 14 12:58:01 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n input_bram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 11 -rwidth 18 -waddr_width 11 -wwidth 18 -rnum_words 2048 -wnum_words 2048 -outdata REGISTERED -resetmode SYNC -cascade -1 -e
- Circuit name : input_bram
- Module type : RAM_DP
- Module Version : 6.1
- Ports :
- Inputs : WrAddress[10:0], RdAddress[10:0], Data[17:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
- Outputs : Q[17:0]
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : input_bram.vhd
- VHDL template : input_bram_tmpl.vhd
- VHDL testbench : tb_input_bram_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : input_bram.srp
- Element Usage :
- DP16KB : 2
- Estimated Resource Usage:
- EBR : 2
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Mon Sep 14 12:58:01 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n input_bram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 11 -rwidth 18 -waddr_width 11 -wwidth 18 -rnum_words 2048 -wnum_words 2048 -outdata REGISTERED -resetmode SYNC -cascade -1 -e \r
- Circuit name : input_bram\r
- Module type : RAM_DP\r
- Module Version : 6.1\r
- Ports : \r
- Inputs : WrAddress[10:0], RdAddress[10:0], Data[17:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn\r
- Outputs : Q[17:0]\r
- I/O buffer : not inserted\r
- EDIF output : suppressed\r
- VHDL output : input_bram.vhd\r
- VHDL template : input_bram_tmpl.vhd\r
- VHDL testbench : tb_input_bram_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : input_bram.srp\r
- Estimated Resource Usage:\r
- EBR : 2\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: ..\src\input_bram.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 6.1
--- Mon Sep 14 12:58:01 2009
-
--- parameterized module component declaration
-component input_bram
- port (WrAddress: in std_logic_vector(10 downto 0);
- RdAddress: in std_logic_vector(10 downto 0);
- Data: in std_logic_vector(17 downto 0); WE: in std_logic;
- RdClock: in std_logic; RdClockEn: in std_logic;
- Reset: in std_logic; WrClock: in std_logic;
- WrClockEn: in std_logic; Q: out std_logic_vector(17 downto 0));
-end component;
-
--- parameterized module component instance
-__ : input_bram
- port map (WrAddress(10 downto 0)=>__, RdAddress(10 downto 0)=>__,
- Data(17 downto 0)=>__, WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__,
- WrClock=>__, WrClockEn=>__, Q(17 downto 0)=>__);
+++ /dev/null
-SCUBA, Version ispLever_v8.0_PROD_Build (41)\r
-Fri Apr 16 11:05:24 2010\r
- \r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.\r
- \r
-BEGIN SCUBA Module Synthesis\r
- \r
- Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_1kx18 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -addr_width 10 -data_width 18 -num_words 1024 -no_enable -pe -1 -pf -1 -fill -e \r
- Circuit name : fifo_1kx18\r
- Module type : fifoblk\r
- Module Version : 4.8\r
- Ports : \r
- Inputs : Data[17:0], Clock, WrEn, RdEn, Reset\r
- Outputs : Q[17:0], WCNT[10:0], Empty, Full\r
- I/O buffer : not inserted\r
- EDIF output : suppressed\r
- VHDL output : fifo_1kx18.vhd\r
- VHDL template : fifo_1kx18_tmpl.vhd\r
- VHDL testbench : tb_fifo_1kx18_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : fifo_1kx18.srp\r
- Estimated Resource Usage:\r
- LUT : 80\r
- EBR : 1\r
- Reg : 35\r
- \r
-END SCUBA Module Synthesis\r
-\r
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)
-Thu Oct 29 11:23:03 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n mult_3x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dspmult -simple_portname -pfu_mult -widtha 3 -widthb 8 -widthp 11 -PL_stages 0 -output_reg -clk0 -ce0 -rst0 -e
- Circuit name : mult_3x8
- Module type : dspmult_a
- Module Version : 4.3
- Ports :
- Inputs : Clock, ClkEn, Aclr, DataA[2:0], DataB[7:0]
- Outputs : Result[10:0]
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : mult_3x8.vhd
- VHDL template : mult_3x8_tmpl.vhd
- VHDL testbench : tb_mult_3x8_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : mult_3x8.srp
- Element Usage :
- AND2 : 9
- FADD2B : 6
- FD1P3DX : 11
- MULT2 : 4
- Estimated Resource Usage:
- LUT : 29
- Reg : 11
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Thu Oct 29 11:23:03 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n mult_3x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dspmult -simple_portname -pfu_mult -widtha 3 -widthb 8 -widthp 11 -PL_stages 0 -output_reg -clk0 -ce0 -rst0 -e \r
- Circuit name : mult_3x8\r
- Module type : dspmult_a\r
- Module Version : 4.3\r
- Ports : \r
- Inputs : Clock, ClkEn, Aclr, DataA[2:0], DataB[7:0]\r
- Outputs : Result[10:0]\r
- I/O buffer : not inserted\r
- EDIF output : suppressed\r
- VHDL output : mult_3x8.vhd\r
- VHDL template : mult_3x8_tmpl.vhd\r
- VHDL testbench : tb_mult_3x8_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : mult_3x8.srp\r
- Estimated Resource Usage:\r
- LUT : 29\r
- Reg : 11\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: ..\src\mult_3x8.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 4.3
--- Thu Oct 29 11:23:03 2009
-
--- parameterized module component declaration
-component mult_3x8
- port (Clock: in std_logic; ClkEn: in std_logic;
- Aclr: in std_logic; DataA: in std_logic_vector(2 downto 0);
- DataB: in std_logic_vector(7 downto 0);
- Result: out std_logic_vector(10 downto 0));
-end component;
-
--- parameterized module component instance
-__ : mult_3x8
- port map (Clock=>__, ClkEn=>__, Aclr=>__, DataA(2 downto 0)=>__,
- DataB(7 downto 0)=>__, Result(10 downto 0)=>__);
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)
-Thu Nov 05 15:51:35 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n onewire_spare_one -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 3 -num_words 8 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem -memformat orca -e
- Circuit name : onewire_spare_one
- Module type : rom
- Module Version : 2.4
- Address width : 3
- Ports :
- Inputs : Address[2:0]
- Outputs : Q[3:0]
- I/O buffer : not inserted
- Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem
- EDIF output : suppressed
- VHDL output : onewire_spare_one.vhd
- VHDL template : onewire_spare_one_tmpl.vhd
- VHDL testbench : tb_onewire_spare_one_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : onewire_spare_one.srp
- Element Usage :
- ROM16X1 : 4
- Estimated Resource Usage:
- LUT : 4
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Thu Nov 05 15:51:35 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n onewire_spare_one -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 3 -num_words 8 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem -memformat orca -e \r
- Circuit name : onewire_spare_one\r
- Module type : rom\r
- Module Version : 2.4\r
- Address width : 3\r
- Data width : 4\r
- Ports : \r
- Inputs : Address[2:0]\r
- Outputs : Q[3:0]\r
- I/O buffer : not inserted\r
- Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem\r
- EDIF output : suppressed\r
- VHDL output : onewire_spare_one.vhd\r
- VHDL template : onewire_spare_one_tmpl.vhd\r
- VHDL testbench : tb_onewire_spare_one_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : onewire_spare_one.srp\r
- Estimated Resource Usage:\r
- LUT : 4\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: onewire_spare_one.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 2.4
--- Thu Nov 05 15:51:35 2009
-
--- parameterized module component declaration
-component onewire_spare_one
- port (Address: in std_logic_vector(2 downto 0);
- Q: out std_logic_vector(3 downto 0));
-end component;
-
--- parameterized module component instance
-__ : onewire_spare_one
- port map (Address(2 downto 0)=>__, Q(3 downto 0)=>__);
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)
-Mon Sep 14 12:54:09 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n ped_thr_true -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ramdp -device LFE2M100E -aaddr_width 7 -widtha 18 -baddr_width 7 -widthb 18 -anum_words 128 -bnum_words 128 -outdataA REGISTERED -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -cascade -1 -e
- Circuit name : ped_thr_true
- Module type : RAM_DP_TRUE
- Module Version : 7.1
- Ports :
- Inputs : DataInA[17:0], DataInB[17:0], AddressA[6:0], AddressB[6:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
- Outputs : QA[17:0], QB[17:0]
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : ped_thr_true.vhd
- VHDL template : ped_thr_true_tmpl.vhd
- VHDL testbench : tb_ped_thr_true_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : ped_thr_true.srp
- Element Usage :
- DP16KB : 1
- Estimated Resource Usage:
- EBR : 1
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 7.1
--- Mon Sep 14 12:54:09 2009
-
--- parameterized module component declaration
-component ped_thr_true
- port (DataInA: in std_logic_vector(17 downto 0);
- DataInB: in std_logic_vector(17 downto 0);
- AddressA: in std_logic_vector(6 downto 0);
- AddressB: in std_logic_vector(6 downto 0);
- ClockA: in std_logic; ClockB: in std_logic;
- ClockEnA: in std_logic; ClockEnB: in std_logic;
- WrA: in std_logic; WrB: in std_logic; ResetA: in std_logic;
- ResetB: in std_logic; QA: out std_logic_vector(17 downto 0);
- QB: out std_logic_vector(17 downto 0));
-end component;
-
--- parameterized module component instance
-__ : ped_thr_true
- port map (DataInA(17 downto 0)=>__, DataInB(17 downto 0)=>__,
- AddressA(6 downto 0)=>__, AddressB(6 downto 0)=>__, ClockA=>__,
- ClockB=>__, ClockEnA=>__, ClockEnB=>__, WrA=>__, WrB=>__, ResetA=>__,
- ResetB=>__, QA(17 downto 0)=>__, QB(17 downto 0)=>__);
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44)
--- Module Version: 4.2
--- Fri Jan 30 10:01:31 2009
-
--- parameterized module component declaration
-component pll_40m
- port (CLK: in std_logic; RESET: in std_logic; DPAMODE: in std_logic;
- DPHASE0: in std_logic; DPHASE1: in std_logic; DPHASE2: in std_logic;
- DPHASE3: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic;
- LOCK: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : pll_40m
- port map (CLK=>__, RESET=>__, DPAMODE=>__, DPHASE0=>__, DPHASE1=>__,
- DPHASE2=>__, DPHASE3=>__, CLKOP=>__, CLKOS=>__, LOCK=>__);
+++ /dev/null
-library ieee; \r
-use ieee.std_logic_1164.all; \r
-use ieee.std_logic_arith.all; \r
-use ieee.std_logic_unsigned.all;\r
-\r
-library work;\r
-use work.adcmv3_components.all;\r
-\r
-entity reset_handler is\r
-port( \r
- CLEAR_IN : in std_logic; -- async reset from outside, if available (otherwise '0')\r
- RESET_IN : in std_logic; -- for testing, if not needed, set to '0'\r
- CLK_IN : in std_logic;\r
- TRB_RESET_IN : in std_logic;\r
- RESET_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
-);\r
-end;\r
-\r
-architecture behavioral of reset_handler is\r
-\r
--- normal signals\r
-signal async_sampler : std_logic_vector(7 downto 0);\r
-signal async_pulse_x : std_logic;\r
-signal async_pulse : std_logic;\r
-signal reset_cnt : std_logic_vector(15 downto 0);\r
-signal debug : std_logic_vector(15 downto 0);\r
-signal reset : std_logic;\r
-\r
-attribute syn_preserve : boolean;\r
-attribute syn_preserve of async_sampler : signal is true;\r
-attribute syn_preserve of async_pulse : signal is true;\r
-attribute syn_preserve of reset : signal is true;\r
-attribute syn_preserve of reset_cnt : signal is true;\r
- \r
-begin \r
-\r
--- sample the async reset line and react only on a long pulse\r
-THE_ASYNC_SAMPLER_PROC: process( clk_in )\r
-begin\r
- if( rising_edge(clk_in) ) then\r
- async_sampler(7 downto 0) <= async_sampler(6 downto 0) & clear_in;\r
- async_pulse <= async_pulse_x;\r
- end if;\r
-end process THE_ASYNC_SAMPLER_PROC;\r
-\r
-async_pulse_x <= '1' when ( async_sampler = x"ff" ) else '0';\r
-\r
--- one global reset counter\r
-THE_GLOBAL_RESET_PROC: process( clk_in )\r
-begin\r
- if( rising_edge(clk_in) ) then\r
- if( (async_pulse = '1') or (reset_in = '1') or (trb_reset_in = '1') ) then\r
- reset_cnt <= (others => '0');\r
- reset <= '1';\r
- else\r
- reset_cnt <= reset_cnt + 1;\r
- reset <= '1';\r
- if( reset_cnt = x"001F" ) then\r
- reset <= '0';\r
- reset_cnt <= x"001F";\r
- end if;\r
- end if;\r
- end if;\r
-end process THE_GLOBAL_RESET_PROC;\r
-\r
-\r
--- Debug signals\r
-debug <= reset_cnt;\r
-\r
--- Output signals\r
-debug_out <= debug;\r
-reset_out <= reset;\r
- \r
-end behavioral; \r
-
\ No newline at end of file
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)
-Tue Aug 11 14:48:40 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n slv_onewire_dpram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 6 -rwidth 32 -waddr_width 7 -wwidth 16 -rnum_words 64 -wnum_words 128 -resetmode SYNC -cascade -1 -e
- Circuit name : slv_onewire_dpram
- Module type : RAM_DP
- Module Version : 6.1
- Ports :
- Inputs : WrAddress[6:0], RdAddress[5:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
- Outputs : Q[31:0]
- I/O buffer : not inserted
- EDIF output : suppressed
- VHDL output : slv_onewire_dpram.vhd
- VHDL template : slv_onewire_dpram_tmpl.vhd
- VHDL testbench : tb_slv_onewire_dpram_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : slv_onewire_dpram.srp
- Element Usage :
- DP16KB : 1
- Estimated Resource Usage:
- EBR : 1
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Tue Aug 11 14:48:40 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n slv_onewire_dpram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 6 -rwidth 32 -waddr_width 7 -wwidth 16 -rnum_words 64 -wnum_words 128 -resetmode SYNC -cascade -1 -e \r
- Circuit name : slv_onewire_dpram\r
- Module type : RAM_DP\r
- Module Version : 6.1\r
- Ports : \r
- Inputs : WrAddress[6:0], RdAddress[5:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn\r
- Outputs : Q[31:0]\r
- I/O buffer : not inserted\r
- EDIF output : suppressed\r
- VHDL output : slv_onewire_dpram.vhd\r
- VHDL template : slv_onewire_dpram_tmpl.vhd\r
- VHDL testbench : tb_slv_onewire_dpram_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : slv_onewire_dpram.srp\r
- Estimated Resource Usage:\r
- EBR : 1\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: slv_onewire_dpram.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 6.1
--- Tue Aug 11 14:48:40 2009
-
--- parameterized module component declaration
-component slv_onewire_dpram
- port (WrAddress: in std_logic_vector(6 downto 0);
- RdAddress: in std_logic_vector(5 downto 0);
- Data: in std_logic_vector(15 downto 0); WE: in std_logic;
- RdClock: in std_logic; RdClockEn: in std_logic;
- Reset: in std_logic; WrClock: in std_logic;
- WrClockEn: in std_logic; Q: out std_logic_vector(31 downto 0));
-end component;
-
--- parameterized module component instance
-__ : slv_onewire_dpram
- port map (WrAddress(6 downto 0)=>__, RdAddress(5 downto 0)=>__, Data(15 downto 0)=>__,
- WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, WrClock=>__,
- WrClockEn=>__, Q(31 downto 0)=>__);
+++ /dev/null
-[Device]\r
-Family=latticeecp2m\r
-PartType=LFE2M100E\r
-PartName=LFE2M100E-6F900C\r
-SpeedGrade=-6\r
-Package=FPBGA900\r
-OperatingCondition=COM\r
-Status=P\r
-\r
-[IP]\r
-VendorName=Lattice Semiconductor Corporation\r
-CoreType=LPM\r
-CoreStatus=Demo\r
-CoreName=Subtractor\r
-CoreRevision=3.1\r
-ModuleName=suber_12bit\r
-SourceFormat=VHDL\r
-ParameterFileVersion=1.0\r
-Date=10/27/2009\r
-Time=16:54:01\r
-\r
-[Parameters]\r
-Verilog=0\r
-VHDL=1\r
-EDIF=1\r
-Destination=Synplicity\r
-Expression=BusA(0 to 7)\r
-Order=Big Endian [MSB:LSB]\r
-IO=0\r
-InputWidth=12\r
-Representation=Unsigned\r
-UseCIport=0\r
-COport=None\r
-OutReg=1\r
-Complex=0\r
-Stage=0\r
+++ /dev/null
-SCUBA, Version ispLever_v72_SP2_Build (23)
-Tue Oct 27 16:54:01 2009
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp. All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
-Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
-
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n suber_12bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type mgaddsub -direction sub -width 12 -unsigned -output_reg -enable -pipeline 0 -e
- Circuit name : suber_12bit
- Module type : sub
- Module Version : 3.1
- Width : 12
- Ports :
- Inputs : DataA[11:0], DataB[11:0], Clock, Reset, ClockEn
- Outputs : Result[11:0]
- I/O buffer : not inserted
- Representation : unsigned number
- EDIF output : suppressed
- VHDL output : suber_12bit.vhd
- VHDL template : suber_12bit_tmpl.vhd
- VHDL testbench : tb_suber_12bit_tmpl.vhd
- VHDL purpose : for synthesis and simulation
- Bus notation : big endian
- Report output : suber_12bit.srp
- Element Usage :
- FSUB2B : 7
- FD1P3DX : 12
- Estimated Resource Usage:
- LUT : 14
- Reg : 12
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 3.1
---X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type sub -width 12 -unsigned -output_reg -enable -pipeline 0 -e
-
--- Tue Oct 27 16:54:01 2009
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity suber_12bit is
- port (
- DataA: in std_logic_vector(11 downto 0);
- DataB: in std_logic_vector(11 downto 0);
- Clock: in std_logic;
- Reset: in std_logic;
- ClockEn: in std_logic;
- Result: out std_logic_vector(11 downto 0));
-end suber_12bit;
-
-architecture Structure of suber_12bit is
-
- -- internal signal declarations
- signal r0_diff11: std_logic;
- signal r0_diff10: std_logic;
- signal r0_diff9: std_logic;
- signal r0_diff8: std_logic;
- signal r0_diff7: std_logic;
- signal r0_diff6: std_logic;
- signal r0_diff5: std_logic;
- signal r0_diff4: std_logic;
- signal r0_diff3: std_logic;
- signal r0_diff2: std_logic;
- signal r0_diff1: std_logic;
- signal r0_diff0: std_logic;
- signal tdiff0: std_logic;
- signal scuba_vhi: std_logic;
- signal tdiff1: std_logic;
- signal tdiff2: std_logic;
- signal co0: std_logic;
- signal tdiff3: std_logic;
- signal tdiff4: std_logic;
- signal co1: std_logic;
- signal tdiff5: std_logic;
- signal tdiff6: std_logic;
- signal co2: std_logic;
- signal tdiff7: std_logic;
- signal tdiff8: std_logic;
- signal co3: std_logic;
- signal tdiff9: std_logic;
- signal tdiff10: std_logic;
- signal co4: std_logic;
- signal tdiff11: std_logic;
- signal co5: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component FSUB2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3DX
- -- synopsys translate_off
- generic (GSR : in String);
- -- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- attribute GSR : string;
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- FF_11: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tdiff11, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_diff11);
-
- FF_10: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tdiff10, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_diff10);
-
- FF_9: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tdiff9, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_diff9);
-
- FF_8: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tdiff8, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_diff8);
-
- FF_7: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tdiff7, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_diff7);
-
- FF_6: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tdiff6, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_diff6);
-
- FF_5: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tdiff5, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_diff5);
-
- FF_4: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tdiff4, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_diff4);
-
- FF_3: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tdiff3, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_diff3);
-
- FF_2: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tdiff2, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_diff2);
-
- FF_1: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tdiff1, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_diff1);
-
- FF_0: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>tdiff0, SP=>ClockEn, CK=>Clock, CD=>Reset,
- Q=>r0_diff0);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- addsub_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>DataA(0), B0=>scuba_vlo,
- B1=>DataB(0), BI=>scuba_vlo, BOUT=>co0, S0=>open, S1=>tdiff0);
-
- addsub_1: FSUB2B
- port map (A0=>DataA(1), A1=>DataA(2), B0=>DataB(1), B1=>DataB(2),
- BI=>co0, BOUT=>co1, S0=>tdiff1, S1=>tdiff2);
-
- addsub_2: FSUB2B
- port map (A0=>DataA(3), A1=>DataA(4), B0=>DataB(3), B1=>DataB(4),
- BI=>co1, BOUT=>co2, S0=>tdiff3, S1=>tdiff4);
-
- addsub_3: FSUB2B
- port map (A0=>DataA(5), A1=>DataA(6), B0=>DataB(5), B1=>DataB(6),
- BI=>co2, BOUT=>co3, S0=>tdiff5, S1=>tdiff6);
-
- addsub_4: FSUB2B
- port map (A0=>DataA(7), A1=>DataA(8), B0=>DataB(7), B1=>DataB(8),
- BI=>co3, BOUT=>co4, S0=>tdiff7, S1=>tdiff8);
-
- addsub_5: FSUB2B
- port map (A0=>DataA(9), A1=>DataA(10), B0=>DataB(9),
- B1=>DataB(10), BI=>co4, BOUT=>co5, S0=>tdiff9, S1=>tdiff10);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- addsub_6: FSUB2B
- port map (A0=>DataA(11), A1=>scuba_vlo, B0=>DataB(11),
- B1=>scuba_vlo, BI=>co5, BOUT=>open, S0=>tdiff11, S1=>open);
-
- Result(11) <= r0_diff11;
- Result(10) <= r0_diff10;
- Result(9) <= r0_diff9;
- Result(8) <= r0_diff8;
- Result(7) <= r0_diff7;
- Result(6) <= r0_diff6;
- Result(5) <= r0_diff5;
- Result(4) <= r0_diff4;
- Result(3) <= r0_diff3;
- Result(2) <= r0_diff2;
- Result(1) <= r0_diff1;
- Result(0) <= r0_diff0;
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of suber_12bit is
- for Structure
- for all:FSUB2B use entity ecp2m.FSUB2B(V); end for;
- for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-Starting process: \r
-\r
-SCUBA, Version ispLever_v72_SP2_Build (23)\r
-Tue Oct 27 16:54:01 2009\r
-\r
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
-Copyright (c) 1995 AT&T Corp. All rights reserved.\r
-Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
-Copyright (c) 2001 Agere Systems All rights reserved.\r
-Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
-\r
-BEGIN SCUBA Module Synthesis\r
-\r
- Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n suber_12bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type mgaddsub -direction sub -width 12 -unsigned -output_reg -enable -pipeline 0 -e \r
- Circuit name : suber_12bit\r
- Module type : sub\r
- Module Version : 3.1\r
- Width : 12\r
- Ports : \r
- Inputs : DataA[11:0], DataB[11:0], Clock, Reset, ClockEn\r
- Outputs : Result[11:0]\r
- I/O buffer : not inserted\r
- Representation : unsigned number\r
- EDIF output : suppressed\r
- VHDL output : suber_12bit.vhd\r
- VHDL template : suber_12bit_tmpl.vhd\r
- VHDL testbench : tb_suber_12bit_tmpl.vhd\r
- VHDL purpose : for synthesis and simulation\r
- Bus notation : big endian\r
- Report output : suber_12bit.srp\r
- Estimated Resource Usage:\r
- LUT : 14\r
- Reg : 12\r
-\r
-END SCUBA Module Synthesis\r
-\r
-File: suber_12bit.lpc created.\r
-\r
-\r
-End process: completed successfully.\r
-\r
-\r
-Total Warnings: 0\r
-\r
-Total Errors: 0\r
-\r
-\r
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 3.1
--- Tue Oct 27 16:54:01 2009
-
--- parameterized module component declaration
-component suber_12bit
- port (DataA: in std_logic_vector(11 downto 0);
- DataB: in std_logic_vector(11 downto 0); Clock: in std_logic;
- Reset: in std_logic; ClockEn: in std_logic;
- Result: out std_logic_vector(11 downto 0));
-end component;
-
--- parameterized module component instance
-__ : suber_12bit
- port map (DataA(11 downto 0)=>__, DataB(11 downto 0)=>__, Clock=>__,
- Reset=>__, ClockEn=>__, Result(11 downto 0)=>__);
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component adc_apv_map_mem
- port (Address : in std_logic_vector(6 downto 0);
- Q : out std_logic_vector(3 downto 0)
- );
- end component;
-
- signal Address : std_logic_vector(6 downto 0) := (others => '0');
- signal Q : std_logic_vector(3 downto 0);
-begin
- u1 : adc_apv_map_mem
- port map (Address => Address, Q => Q
- );
-
- process
-
- begin
- Address <= (others => '0') ;
- wait for 100 ns;
- wait for 10 ns;
- for i in 0 to 131 loop
- wait for 10 ns;
- Address <= Address + '1' ;
- end loop;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-ENTITY testbench IS\r
-END testbench;\r
-\r
-ARCHITECTURE behavior OF testbench IS \r
-\r
- COMPONENT adc_data_handler\r
- PORT(\r
- RESET_IN : IN std_logic;\r
- RESET_PLL_IN : IN std_logic;\r
- ADC_LCLK_IN : IN std_logic;\r
- ADC_ADCLK_IN : IN std_logic;\r
- ADC_CHNL_IN : IN std_logic_vector(7 downto 0);\r
- PLL_CTRL_IN : IN std_logic_vector(3 downto 0); \r
- PLL_LOCK_OUT : OUT std_logic;\r
- CLK40M_OUT : OUT std_logic;\r
- ADC_ADCLK_OUT : OUT std_logic;\r
- ADC_DATA7_OUT : OUT std_logic_vector(11 downto 0);\r
- ADC_DATA6_OUT : OUT std_logic_vector(11 downto 0);\r
- ADC_DATA5_OUT : OUT std_logic_vector(11 downto 0);\r
- ADC_DATA4_OUT : OUT std_logic_vector(11 downto 0);\r
- ADC_DATA3_OUT : OUT std_logic_vector(11 downto 0);\r
- ADC_DATA2_OUT : OUT std_logic_vector(11 downto 0);\r
- ADC_DATA1_OUT : OUT std_logic_vector(11 downto 0);\r
- ADC_DATA0_OUT : OUT std_logic_vector(11 downto 0);\r
- DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
- );\r
- END COMPONENT;\r
-\r
- SIGNAL RESET_IN : std_logic;\r
- SIGNAL RESET_PLL_IN : std_logic;\r
- SIGNAL ADC_LCLK_IN : std_logic;\r
- SIGNAL ADC_ADCLK_IN : std_logic;\r
- SIGNAL ADC_CHNL_IN : std_logic_vector(7 downto 0);\r
- SIGNAL PLL_CTRL_IN : std_logic_vector(3 downto 0);\r
- SIGNAL PLL_LOCK_OUT : std_logic;\r
- SIGNAL CLK40M_OUT : std_logic;\r
- SIGNAL ADC_ADCLK_OUT : std_logic;\r
- SIGNAL ADC_DATA7_OUT : std_logic_vector(11 downto 0);\r
- SIGNAL ADC_DATA6_OUT : std_logic_vector(11 downto 0);\r
- SIGNAL ADC_DATA5_OUT : std_logic_vector(11 downto 0);\r
- SIGNAL ADC_DATA4_OUT : std_logic_vector(11 downto 0);\r
- SIGNAL ADC_DATA3_OUT : std_logic_vector(11 downto 0);\r
- SIGNAL ADC_DATA2_OUT : std_logic_vector(11 downto 0);\r
- SIGNAL ADC_DATA1_OUT : std_logic_vector(11 downto 0);\r
- SIGNAL ADC_DATA0_OUT : std_logic_vector(11 downto 0);\r
- SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
-\r
- signal adc_0_real : std_logic_vector(11 downto 0);\r
- signal adc_7_real : std_logic_vector(11 downto 0);\r
-\r
-BEGIN\r
-\r
--- Please check and add your generic clause manually\r
- uut: adc_data_handler PORT MAP(\r
- RESET_IN => RESET_IN,\r
- RESET_PLL_IN => RESET_PLL_IN,\r
- ADC_LCLK_IN => ADC_LCLK_IN,\r
- ADC_ADCLK_IN => ADC_ADCLK_IN,\r
- ADC_CHNL_IN => ADC_CHNL_IN,\r
- PLL_CTRL_IN => PLL_CTRL_IN,\r
- PLL_LOCK_OUT => PLL_LOCK_OUT,\r
- CLK40M_OUT => CLK40M_OUT,\r
- ADC_ADCLK_OUT => ADC_ADCLK_OUT,\r
- ADC_DATA7_OUT => ADC_DATA7_OUT,\r
- ADC_DATA6_OUT => ADC_DATA6_OUT,\r
- ADC_DATA5_OUT => ADC_DATA5_OUT,\r
- ADC_DATA4_OUT => ADC_DATA4_OUT,\r
- ADC_DATA3_OUT => ADC_DATA3_OUT,\r
- ADC_DATA2_OUT => ADC_DATA2_OUT,\r
- ADC_DATA1_OUT => ADC_DATA1_OUT,\r
- ADC_DATA0_OUT => ADC_DATA0_OUT,\r
- DEBUG_OUT => DEBUG_OUT\r
- );\r
-\r
-THE_CLOCK_GEN: process\r
-begin\r
- adc_lclk_in <= '1'; wait for 4.16 ns;\r
- adc_lclk_in <= '0'; wait for 4.16 ns;\r
-end process THE_CLOCK_GEN;\r
-\r
-BLA: process\r
-variable adc_0_data : unsigned(11 downto 0) := x"000";\r
-variable adc_7_data : unsigned(11 downto 0) := x"fff";\r
-variable my_bit : integer := 0;\r
-begin\r
- \r
- my_bit := 0;\r
- adc_0_real <= std_logic_vector(adc_0_data);\r
- adc_7_real <= std_logic_vector(adc_7_data);\r
- \r
- BIT_LOOP: for I in 0 to 5 loop\r
-\r
- wait until rising_edge(adc_lclk_in);\r
- wait for 2.08 ns;\r
- if( I < 3 ) then\r
- adc_adclk_in <= '1'; \r
- else\r
- adc_adclk_in <= '0'; -- second half\r
- end if;\r
- adc_chnl_in(7) <= adc_7_data(my_bit);\r
- adc_chnl_in(6 downto 1) <= (others => '0');\r
- adc_chnl_in(0) <= adc_0_data(my_bit);\r
- my_bit := my_bit + 1;\r
- wait until falling_edge(adc_lclk_in);\r
- wait for 2.08 ns;\r
- adc_chnl_in(7) <= adc_7_data(my_bit);\r
- adc_chnl_in(6 downto 1) <= (others => '0');\r
- adc_chnl_in(0) <= adc_0_data(my_bit);\r
- my_bit := my_bit + 1;\r
- \r
- end loop BIT_LOOP;\r
- \r
- adc_7_data := adc_7_data - 1;\r
- adc_0_data := adc_0_data + 1;\r
-\r
-end process BLA;\r
-\r
-THE_TEST_BENCH: process\r
-begin\r
- -- Setup signals\r
- reset_in <= '0';\r
- reset_pll_in <= '0';\r
- pll_ctrl_in <= x"6";\r
- wait for 100 ns;\r
-\r
- -- Reset all\r
- reset_in <= '1';\r
- wait for 100 ns;\r
- reset_in <= '0';\r
- wait for 100 ns;\r
-\r
- -- Tests may start now\r
-\r
-\r
-\r
-\r
-\r
- -- Stay a while, stay forever!\r
- wait;\r
- \r
-end process THE_TEST_BENCH;\r
-\r
-END;\r
-\r
-\r
--- -- ADCLK = '1' => first half of data word\r
--- wait until rising_edge(adc_lclk_in);\r
--- wait for 2.08 ns;\r
--- adc_adclk_in <= '1'; adc_chnl_in <= b"0000_0000"; -- Bit D0\r
--- wait until falling_edge(adc_lclk_in);\r
--- wait for 2.08 ns;\r
--- adc_adclk_in <= '1'; adc_chnl_in <= b"1111_1111"; -- Bit D1\r
--- wait until rising_edge(adc_lclk_in);\r
--- wait for 2.08 ns;\r
--- adc_adclk_in <= '1'; adc_chnl_in <= b"0000_0000"; -- Bit D2\r
--- wait until falling_edge(adc_lclk_in);\r
--- wait for 2.08 ns;\r
--- adc_adclk_in <= '1'; adc_chnl_in <= b"1111_1111"; -- Bit D3\r
--- wait until rising_edge(adc_lclk_in);\r
--- wait for 2.08 ns;\r
--- adc_adclk_in <= '1'; adc_chnl_in <= b"0000_0000"; -- Bit D4\r
--- wait until falling_edge(adc_lclk_in);\r
--- wait for 2.08 ns;\r
--- adc_adclk_in <= '1'; adc_chnl_in <= b"1111_1111"; -- Bit D5\r
--- -- ADCLK = '0' => second half of data word\r
--- wait until rising_edge(adc_lclk_in);\r
--- wait for 2.08 ns;\r
--- adc_adclk_in <= '0'; adc_chnl_in <= b"0000_0000"; -- Bit D6\r
--- wait until falling_edge(adc_lclk_in);\r
--- wait for 2.08 ns;\r
--- adc_adclk_in <= '0'; adc_chnl_in <= b"1111_1111"; -- Bit D7\r
--- wait until rising_edge(adc_lclk_in);\r
--- wait for 2.08 ns;\r
--- adc_adclk_in <= '0'; adc_chnl_in <= b"0000_0000"; -- Bit D8\r
--- wait until falling_edge(adc_lclk_in);\r
--- wait for 2.08 ns;\r
--- adc_adclk_in <= '0'; adc_chnl_in <= b"1111_1111"; -- Bit D9\r
--- wait until rising_edge(adc_lclk_in);\r
--- wait for 2.08 ns;\r
--- adc_adclk_in <= '0'; adc_chnl_in <= b"0000_0000"; -- Bit D10\r
--- wait until falling_edge(adc_lclk_in);\r
--- wait for 2.08 ns;\r
--- adc_adclk_in <= '0'; adc_chnl_in <= b"1111_1111"; -- Bit D11\r
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component adc_onewire_map_mem
- port (Address : in std_logic_vector(6 downto 0);
- Q : out std_logic_vector(3 downto 0)
- );
- end component;
-
- signal Address : std_logic_vector(6 downto 0) := (others => '0');
- signal Q : std_logic_vector(3 downto 0);
-begin
- u1 : adc_onewire_map_mem
- port map (Address => Address, Q => Q
- );
-
- process
-
- begin
- Address <= (others => '0') ;
- wait for 100 ns;
- wait for 10 ns;
- for i in 0 to 131 loop
- wait for 10 ns;
- Address <= Address + '1' ;
- end loop;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component apv_adc_map_mem
- port (Address : in std_logic_vector(6 downto 0);
- Q : out std_logic_vector(3 downto 0)
- );
- end component;
-
- signal Address : std_logic_vector(6 downto 0) := (others => '0');
- signal Q : std_logic_vector(3 downto 0);
-begin
- u1 : apv_adc_map_mem
- port map (Address => Address, Q => Q
- );
-
- process
-
- begin
- Address <= (others => '0') ;
- wait for 100 ns;
- wait for 10 ns;
- for i in 0 to 131 loop
- wait for 10 ns;
- Address <= Address + '1' ;
- end loop;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component apv_map_mem
- port (Address : in std_logic_vector(6 downto 0);
- Q : out std_logic_vector(3 downto 0)
- );
- end component;
-
- signal Address : std_logic_vector(6 downto 0) := (others => '0');
- signal Q : std_logic_vector(3 downto 0);
-begin
- u1 : apv_map_mem
- port map (Address => Address, Q => Q
- );
-
- process
-
- begin
- Address <= (others => '0') ;
- wait for 100 ns;
- wait for 10 ns;
- for i in 0 to 131 loop
- wait for 10 ns;
- Address <= Address + '1' ;
- end loop;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component comp4bit
- port (DataA : in std_logic_vector(3 downto 0);
- DataB : in std_logic_vector(3 downto 0); AGTB: out std_logic
- );
- end component;
-
- signal DataA : std_logic_vector(3 downto 0) := (others => '0');
- signal DataB : std_logic_vector(3 downto 0) := (others => '0');
- signal AGTB: std_logic;
-begin
- u1 : comp4bit
- port map (DataA => DataA, DataB => DataB, AGTB => AGTB
- );
-
- process
-
- begin
- DataA <= (others => '0') ;
- for i in 0 to 200 loop
- wait for 10 ns;
- DataA <= DataA + '1' ;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- DataB <= (others => '0') ;
- for i in 0 to 100 loop
- wait for 10 ns;
- DataB <= DataB + '1' ;
- end loop;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component crossfifo
- port (Data : in std_logic_vector(95 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(95 downto 0); Empty: out std_logic;
- Full: out std_logic; AlmostEmpty: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(95 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(95 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
- signal AlmostEmpty: std_logic;
-begin
- u1 : crossfifo
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, Empty => Empty, Full => Full, AlmostEmpty => AlmostEmpty
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 259 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 259 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 259 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v72_PROD_Build (44)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component crossover
- port (Data : in std_logic_vector(95 downto 0);
- WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
- RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
- Q : out std_logic_vector(95 downto 0);
- WCNT : out std_logic_vector(4 downto 0);
- RCNT : out std_logic_vector(4 downto 0); Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- signal Data : std_logic_vector(95 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal RdClock: std_logic := '0';
- signal WrEn: std_logic := '0';
- signal RdEn: std_logic := '0';
- signal Reset: std_logic := '0';
- signal RPReset: std_logic := '0';
- signal Q : std_logic_vector(95 downto 0);
- signal WCNT : std_logic_vector(4 downto 0);
- signal RCNT : std_logic_vector(4 downto 0);
- signal Empty: std_logic;
- signal Full: std_logic;
-begin
- u1 : crossover
- port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
- WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
- Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full
- );
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 19 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- RdClock <= not RdClock after 5.00 ns;
-
- process
-
- begin
- WrEn <= '0' ;
- wait for 100 ns;
- wait until Reset = '0';
- for i in 0 to 19 loop
- wait until WrClock'event and WrClock = '1';
- WrEn <= '1' after 1 ns;
- end loop;
- WrEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RdEn <= '0' ;
- wait until Reset = '0';
- wait until WrEn = '1';
- wait until WrEn = '0';
- for i in 0 to 19 loop
- wait until RdClock'event and RdClock = '1';
- RdEn <= '1' after 1 ns;
- end loop;
- RdEn <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- RPReset <= '1' ;
- wait for 100 ns;
- RPReset <= '0' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v72_PROD_Build (44)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component dpram_8x19
- port (WrAddress : in std_logic_vector(3 downto 0);
- Data : in std_logic_vector(18 downto 0); WrClock: in std_logic;
- WE: in std_logic; WrClockEn: in std_logic;
- RdAddress : in std_logic_vector(3 downto 0);
- Q : out std_logic_vector(18 downto 0)
- );
- end component;
-
- signal WrAddress : std_logic_vector(3 downto 0) := (others => '0');
- signal Data : std_logic_vector(18 downto 0) := (others => '0');
- signal WrClock: std_logic := '0';
- signal WE: std_logic := '0';
- signal WrClockEn: std_logic := '0';
- signal RdAddress : std_logic_vector(3 downto 0) := (others => '0');
- signal Q : std_logic_vector(18 downto 0);
-begin
- u1 : dpram_8x19
- port map (WrAddress => WrAddress, Data => Data, WrClock => WrClock,
- WE => WE, WrClockEn => WrClockEn, RdAddress => RdAddress, Q => Q
- );
-
- process
-
- begin
- WrAddress <= (others => '0') ;
- wait for 100 ns;
- wait for 10 ns;
- for i in 0 to 38 loop
- wait until WrClock'event and WrClock = '1';
- WrAddress <= WrAddress + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- Data <= (others => '0') ;
- wait for 100 ns;
- wait for 10 ns;
- for i in 0 to 19 loop
- wait until WrClock'event and WrClock = '1';
- Data <= Data + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- WrClock <= not WrClock after 5.00 ns;
-
- process
-
- begin
- WE <= '0' ;
- wait for 10 ns;
- for i in 0 to 19 loop
- wait until WrClock'event and WrClock = '1';
- WE <= '1' after 1 ns;
- end loop;
- WE <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- WrClockEn <= '0' ;
- wait for 100 ns;
- wait for 10 ns;
- WrClockEn <= '1' ;
- wait;
- end process;
-
- process
-
- begin
- RdAddress <= (others => '0') ;
- wait for 100 ns;
- wait for 10 ns;
- for i in 0 to 38 loop
- wait for 10 ns;
- RdAddress <= RdAddress + '1' ;
- end loop;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component mult_3x8
- port (Clock: in std_logic; ClkEn: in std_logic;
- Aclr: in std_logic; DataA : in std_logic_vector(2 downto 0);
- DataB : in std_logic_vector(7 downto 0);
- Result : out std_logic_vector(10 downto 0)
- );
- end component;
-
- signal Clock: std_logic := '0';
- signal ClkEn: std_logic := '0';
- signal Aclr: std_logic := '0';
- signal DataA : std_logic_vector(2 downto 0) := (others => '0');
- signal DataB : std_logic_vector(7 downto 0) := (others => '0');
- signal Result : std_logic_vector(10 downto 0);
-begin
- u1 : mult_3x8
- port map (Clock => Clock, ClkEn => ClkEn, Aclr => Aclr, DataA => DataA,
- DataB => DataB, Result => Result
- );
-
- Clock <= not Clock after 5.00 ns;
-
- process
-
- begin
- ClkEn <= '1' ;
- wait;
- end process;
-
- process
-
- begin
- Aclr <= '1' ;
- wait for 100 ns;
- Aclr <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- DataA <= (others => '0') ;
- for i in 0 to 200 loop
- wait until Clock'event and Clock = '1';
- DataA <= DataA + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- DataB <= (others => '0') ;
- for i in 0 to 200 loop
- wait until Clock'event and Clock = '1';
- DataB <= DataB + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component onewire_spare_one
- port (Address : in std_logic_vector(2 downto 0);
- Q : out std_logic_vector(3 downto 0)
- );
- end component;
-
- signal Address : std_logic_vector(2 downto 0) := (others => '0');
- signal Q : std_logic_vector(3 downto 0);
-begin
- u1 : onewire_spare_one
- port map (Address => Address, Q => Q
- );
-
- process
-
- begin
- Address <= (others => '0') ;
- wait for 100 ns;
- wait for 10 ns;
- for i in 0 to 11 loop
- wait for 10 ns;
- Address <= Address + '1' ;
- end loop;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity tb is
-end entity tb;
-
-
-architecture test of tb is
-
- component suber_12bit
- port (DataA : in std_logic_vector(11 downto 0);
- DataB : in std_logic_vector(11 downto 0); Clock: in std_logic;
- Reset: in std_logic; ClockEn: in std_logic;
- Result : out std_logic_vector(11 downto 0)
- );
- end component;
-
- signal DataA : std_logic_vector(11 downto 0) := (others => '0');
- signal DataB : std_logic_vector(11 downto 0) := (others => '0');
- signal Clock: std_logic := '0';
- signal Reset: std_logic := '0';
- signal ClockEn: std_logic := '0';
- signal Result : std_logic_vector(11 downto 0);
-begin
- u1 : suber_12bit
- port map (DataA => DataA, DataB => DataB, Clock => Clock, Reset => Reset,
- ClockEn => ClockEn, Result => Result
- );
-
- process
-
- begin
- DataA <= (others => '0') ;
- for i in 0 to 200 loop
- wait until Clock'event and Clock = '1';
- DataA <= DataA + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- process
-
- begin
- DataB <= (others => '0') ;
- for i in 0 to 200 loop
- wait until Clock'event and Clock = '1';
- DataB <= DataB + '1' after 1 ns;
- end loop;
- wait;
- end process;
-
- Clock <= not Clock after 5.00 ns;
-
- process
-
- begin
- Reset <= '1' ;
- wait for 100 ns;
- Reset <= '0' ;
- wait;
- end process;
-
- process
-
- begin
- ClockEn <= '1' ;
- wait;
- end process;
-
-end architecture test;
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41)
--- Module Version: 4.7
--- Mon Dec 14 14:54:16 2009
-
--- parameterized module component declaration
-component test_fifo
- port (Data: in std_logic_vector(17 downto 0); Clock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- Q: out std_logic_vector(17 downto 0); Empty: out std_logic;
- Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : test_fifo
- port map (Data(17 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__,
- Reset=>__, Q(17 downto 0)=>__, Empty=>__, Full=>__);
+++ /dev/null
--- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 5.2
--- Wed Nov 18 17:17:38 2009
-
--- parameterized module component declaration
-component testfifo
- port (Data: in std_logic_vector(95 downto 0);
- WrClock: in std_logic; RdClock: in std_logic;
- WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
- RPReset: in std_logic; Q: out std_logic_vector(95 downto 0);
- Empty: out std_logic; Full: out std_logic);
-end component;
-
--- parameterized module component instance
-__ : testfifo
- port map (Data(95 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
- RdEn=>__, Reset=>__, RPReset=>__, Q(95 downto 0)=>__, Empty=>__,
- Full=>__);
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
---library work;
---use work.trb_net_std.all;
-
-entity trb_net_sbuf2 is
- generic( DATA_WIDTH : integer := 19;
- VERSION : integer := 0
- );
- port( CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- connections to data source A
- COMB_DATAREADY_IN : in std_logic;
- COMB_NEXT_READ_OUT : out std_logic;
- COMB_READ_IN : in std_logic;
- COMB_DATA_IN : in std_logic_vector (DATA_WIDTH-1 downto 0);
- -- connections to data sink B
- SYN_DATAREADY_OUT : out std_logic;
- SYN_DATA_OUT : out std_logic_vector (DATA_WIDTH-1 downto 0);
- SYN_READ_IN : in std_logic;
- -- status signals
- FIFO_WR_OUT : out std_logic;
- FIFO_RD_OUT : out std_logic;
- STAT_BUFFER : out std_logic
- );
-end trb_net_sbuf2;
-
-architecture trb_net_sbuf_arch of trb_net_sbuf2 is
-
- component fifo_sbuf is
- port( Data : in std_logic_vector(18 downto 0);
- Clock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- Q : out std_logic_vector(18 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic
- );
- end component;
-
- signal fifo_data_in : std_logic_vector(18 downto 0);
- signal fifo_data_out : std_logic_vector(18 downto 0);
- signal reg_fifo_data_out : std_logic_vector(18 downto 0);
- signal fifo_wr_en : std_logic;
- signal fifo_rd_en : std_logic;
- signal fifo_empty : std_logic;
- signal fifo_full : std_logic;
- signal fifo_almost_full : std_logic;
- signal fifo_read_before : std_logic;
- signal next_last_fifo_read : std_logic;
- signal last_fifo_read : std_logic;
- signal comb_next_read : std_logic;
-
-begin
-
--- write to fifo if fifo is not full and data is available
-fifo_data_in <= comb_data_in;
-fifo_wr_en <= comb_dataready_in and comb_read_in and not fifo_full;
-comb_next_read <= not fifo_almost_full;
-
--- fifo read signal
---fifo_rd_en <= syn_read_in or not fifo_read_before;
-fifo_rd_en <= syn_read_in or (not next_last_fifo_read and not fifo_read_before);
-
--- the fifo
-THE_BUFFER : fifo_sbuf
-port map( Data => fifo_data_in,
- Clock => clk,
- WrEn => fifo_wr_en,
- RdEn => fifo_rd_en,
- Reset => reset,
- Q => fifo_data_out,
- Empty => fifo_empty,
- Full => fifo_full,
- AlmostFull => fifo_almost_full
- );
-
--- is data on output valid?
-PROC_DETECT_VALID_READS : process( clk )
-begin
- if( rising_edge(CLK) ) then
- if ( reset = '1' ) then
- fifo_read_before <= '0';
- elsif( clk_en = '1' ) then
- if ( next_last_fifo_read = '1' ) then
- fifo_read_before <= '1';
- elsif( syn_read_in = '1' ) then
- fifo_read_before <= '0';
- end if;
- end if;
- end if;
-end process PROC_DETECT_VALID_READS;
-
--- keep track of fifo read operations
-PROC_LAST_FIFO_READ : process( clk )
-begin
- if( rising_edge(clk) ) then
- next_last_fifo_read <= fifo_rd_en and not fifo_empty;
- last_fifo_read <= next_last_fifo_read and not RESET;
- end if;
-end process PROC_LAST_FIFO_READ;
-
--- register on fifo outputs
-PROC_SYNC_FIFO_OUTPUTS: process( clk )
-begin
- if( rising_edge(clk) )then
- if( next_last_fifo_read = '1' ) then
- reg_fifo_data_out <= fifo_data_out;
- end if;
- end if;
-end process PROC_SYNC_FIFO_OUTPUTS;
-
--- connect to outputs
-syn_dataready_out <= fifo_read_before;
-syn_data_out <= reg_fifo_data_out;
-comb_next_read_out <= comb_next_read;
-
-fifo_wr_out <= fifo_wr_en;
-fifo_rd_out <= fifo_rd_en;
-
-stat_buffer <= fifo_full;
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-entity trb_net_sbuf3 is
- generic( DATA_WIDTH : integer := 18 );
- port( -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN : in std_logic; --comb logic provides data word
- COMB_next_READ_OUT : out std_logic; --sbuf can read in NEXT cycle
- COMB_READ_IN : in std_logic; --comb logic IS reading
- -- the COMB_next_READ_OUT should be connected via comb. logic to a register
- -- to provide COMB_READ_IN (feedback path with 1 cycle delay)
- COMB_DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0); -- Data word
- -- Port to synchronous output.
- SYN_DATAREADY_OUT : out std_logic;
- SYN_DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0); -- Data word
- SYN_READ_IN : in std_logic;
- -- Status and control port
- DEBUG_OUT : out std_logic_vector(15 downto 0);
- STAT_BUFFER : out std_logic
- );
-end entity;
-
-architecture trb_net_sbuf3_arch of trb_net_sbuf3 is
-
-signal current_b0_buffer : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal current_b1_buffer : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal current_b2_buffer : std_logic_vector (DATA_WIDTH-1 downto 0);
-
-signal next_next_READ_OUT : std_logic;
-signal current_next_READ_OUT : std_logic;
-signal next_SYN_DATAREADY_OUT : std_logic;
-signal current_SYN_DATAREADY_OUT : std_logic;
-
-type BUFFER_STATE is (BUFFER_EMPTY, BUFFER_B2_FULL, BUFFER_B1_FULL,BUFFER_B0_FULL);
-signal current_buffer_state : BUFFER_STATE;
-signal next_buffer_state : BUFFER_STATE;
-signal current_buffer_state_int : std_logic_vector(1 downto 0);
-
-signal current_got_overflow : std_logic;
-signal next_got_overflow : std_logic;
-signal combined_COMB_DATAREADY_IN : std_logic;
-
-signal move_b1_b2 : std_logic;
-signal move_b0_b1 : std_logic;
-
-signal load_b2 : std_logic;
-signal load_b1 : std_logic;
-signal load_b0 : std_logic;
-
-signal debug : std_logic_vector(15 downto 0);
-
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_preserve of current_SYN_DATAREADY_OUT : signal is true;
-attribute syn_keep of current_SYN_DATAREADY_OUT : signal is true;
-attribute syn_preserve of current_next_READ_OUT : signal is true;
-attribute syn_keep of current_next_READ_OUT : signal is true;
-attribute syn_hier : string;
-attribute syn_hier of trb_net_sbuf3_arch : architecture is "flatten, firm";
-
-
-begin
-
-SYN_DATA_OUT <= current_b2_buffer;
-SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT;
-COMB_next_READ_OUT <= current_next_READ_OUT;
-
-STAT_BUFFER <= current_got_overflow;
-
-combined_COMB_DATAREADY_IN <= (COMB_DATAREADY_IN and COMB_READ_IN);
-
-THE_FSM: process(current_buffer_state, SYN_READ_IN,
- current_SYN_DATAREADY_OUT, current_got_overflow,
- combined_COMB_DATAREADY_IN)
-begin -- process COMB
- next_buffer_state <= current_buffer_state;
- next_next_READ_OUT <= '1';
- load_b0 <= '0';
- load_b1 <= '0';
- load_b2 <= '0';
- move_b1_b2 <= '0';
- move_b0_b1 <= '0';
- next_SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT;
- next_got_overflow <= current_got_overflow;
-
- case current_buffer_state is
-
- when BUFFER_EMPTY =>
- current_buffer_state_int <= "00";
- if( combined_COMB_DATAREADY_IN = '1' ) then
- next_buffer_state <= BUFFER_B2_FULL;
- load_b2 <= '1';
- next_SYN_DATAREADY_OUT <= '1';
- end if;
-
- when BUFFER_B2_FULL =>
- current_buffer_state_int <= "01";
- next_SYN_DATAREADY_OUT <= '1';
- if ( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '1') ) then
- load_b2 <= '1';
- elsif( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '0') ) then
- next_buffer_state <= BUFFER_B1_FULL;
- next_next_READ_OUT <= '0';
- load_b1 <= '1';
- elsif( (combined_COMB_DATAREADY_IN = '0') and (SYN_READ_IN = '1') ) then
- next_buffer_state <= BUFFER_EMPTY;
- next_SYN_DATAREADY_OUT <= '0';
- end if;
-
- when BUFFER_B1_FULL =>
- current_buffer_state_int <= "10";
- next_SYN_DATAREADY_OUT <= '1';
- next_next_READ_OUT <= '0';
- if ( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '1') ) then
- load_b1 <= '1';
- move_b1_b2 <= '1';
- elsif( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '0') ) then
- next_buffer_state <= BUFFER_B0_FULL;
- load_b0 <= '1';
- elsif( (combined_COMB_DATAREADY_IN = '0') and (SYN_READ_IN = '1') ) then
- next_buffer_state <= BUFFER_B2_FULL;
- next_next_READ_OUT <= '1';
- move_b1_b2 <= '1';
- end if;
-
- when BUFFER_B0_FULL =>
- current_buffer_state_int <= "11";
- next_SYN_DATAREADY_OUT <= '1';
- next_next_READ_OUT <= '0';
- if ( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '0') ) then
- next_got_overflow <= '1';
- elsif( (combined_COMB_DATAREADY_IN = '0') and (SYN_READ_IN = '1') ) then
- move_b1_b2 <= '1';
- move_b0_b1 <= '1';
- next_buffer_state <= BUFFER_B1_FULL;
- elsif( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '1') ) then
- move_b1_b2 <= '1';
- move_b0_b1 <= '1';
- load_b0 <= '1';
- end if;
-
- end case;
-end process;
-
-PROC_FSM_REG : process(CLK)
-begin
- if( rising_edge(CLK) ) then
- if ( RESET = '1' ) then
- current_buffer_state <= BUFFER_EMPTY;
- current_got_overflow <= '0';
- current_SYN_DATAREADY_OUT <= '0';
- current_next_READ_OUT <= '0';
- elsif( CLK_EN = '1' ) then
- current_buffer_state <= next_buffer_state;
- current_got_overflow <= next_got_overflow;
- current_SYN_DATAREADY_OUT <= next_SYN_DATAREADY_OUT;
- current_next_READ_OUT <= next_next_READ_OUT;
- end if;
- end if;
-end process;
-
-
-PROC_REG_BUFFERS : process(CLK)
-begin
- if( rising_edge(CLK) ) then
- if move_b1_b2 = '1' then
- current_b2_buffer <= current_b1_buffer;
- end if;
-
- if move_b0_b1 = '1' then
- current_b1_buffer <= current_b0_buffer;
- end if;
-
- if load_b2 = '1' then
- current_b2_buffer <= COMB_DATA_IN;
- end if;
-
- if load_b1 = '1' then
- current_b1_buffer <= COMB_DATA_IN;
- end if;
-
- if load_b0 = '1' then
- current_b0_buffer <= COMB_DATA_IN;
- end if;
- end if;
-end process;
-
--- Debug signals
-debug(15 downto 14) <= current_buffer_state_int;
-
-debug(13 downto 6) <= (others => '0');
-
-debug(5) <= move_b1_b2;
-debug(4) <= move_b0_b1;
-debug(3) <= '0';
-debug(2) <= load_b2;
-debug(1) <= load_b1;
-debug(0) <= load_b0;
-
-debug_out <= debug;
-
-end architecture;
-
+++ /dev/null
-
---## attention, automatically generated. Don't change by hand.
-library ieee;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use ieee.numeric_std.all;
-
-package version is
-
- constant VERSION_NUMBER_TIME : std_logic_vector(31 downto 0) := CONV_STD_LOGIC_VECTOR(1272371189,32);
-
-end package version;
-
--- /dev/null
+#!/usr/bin/perl
+#############################
+
+use warnings;
+use strict;
+
+my $CTIME_String = localtime(time);
+
+print "Script started: $CTIME_String\n";
+
+system("echo $CTIME_String > benchmark.txt");
+
+exit;
-test
+########## Tcl recorder starts at 04/29/10 17:40:28 ##########\r
+\r
+# Commands to make the Process: \r
+# Hierarchy\r
+if [runCmd "\"$cpld_bin/edfin\" -i edif_adcmv3.edn -jhd edif_adcmv3.jhd -log edif_adcmv3.log -dev orca -lbp \"$fpga_dir/data\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 04/29/10 17:40:28 ###########\r
+\r
+\r
+########## Tcl recorder starts at 04/29/10 17:40:31 ##########\r
+\r
+# Commands to make the Process: \r
+# Generate Bitstream Data\r
+if [runCmd "\"$fpga_dir/bin/lin/edif2ngd\" -l LatticeECP2M -d LFE2M100E \"edif_adcmv3.edn\" \"adcmv3.ngo\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$fpga_dir/bin/lin/edif2ngd\" -l LatticeECP2M -d LFE2M100E \"edif_adcmv3.edn\" \"edif_adcmv3.ngo\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$fpga_dir/bin/lin/edfupdate\" -t \"edif_adcmv3.tcy\" -w \"adcmv3.ngo\" -m \"adcmv3.ngo\" \"edif_adcmv3.ngx\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$fpga_dir/bin/lin/ngdbuild\" -a LatticeECP2M -d LFE2M100E -p \"$fpga_dir/ep5a00/data\" -p \"$fpga_dir/ep5m00/data\" \"adcmv3.ngo\" \"edif_adcmv3.ngd\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [runCmd "\"$fpga_dir/bin/lin/map\" -a LatticeECP2M -p LFE2M100E -t FPBGA900 -s 6 \"edif_adcmv3.ngd\" -o \"edif_adcmv3_map.ncd\" -mp \"edif_adcmv3.mrp\" \"edif_adcmv3.lpf\" -tdm -td_pack"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [catch {open edif_adcmv3.cm2 w} rspFile] {\r
+ puts stderr "Cannot create response file edif_adcmv3.cm2: $rspFile"\r
+} else {\r
+ puts $rspFile "-t edif_adcmv3.mt\r
+-to edif_adcmv3.tw1\r
+-o edif_adcmv3.tcm\r
+-log edif_adcmv3.log\r
+-pr edif_adcmv3.prf\r
+-rpt edif_adcmv3.mrp\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/checkpoint\" -m -f \"edif_adcmv3.cmm\" -f \"edif_adcmv3.cm2\" -arch LatticeECP2M \"edif_adcmv3_map.ncd\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+file delete edif_adcmv3.cm2\r
+if [catch {open edif_adcmv3.p2t w} rspFile] {\r
+ puts stderr "Cannot create response file edif_adcmv3.p2t: $rspFile"\r
+} else {\r
+ puts $rspFile "-w\r
+-i 5\r
+-l 5\r
+-n 8\r
+-t 1\r
+-s 1\r
+-c 1\r
+-e 2\r
+-m nodelist.txt\r
+-exp parCDP=1\r
+-exp parCDR=1\r
+-exp parPlcInLimit=0\r
+-exp parPlcInNeighborSize=1\r
+-exp parPathBased=ON\r
+-exp parHold=ON\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open edif_adcmv3.p3t w} rspFile] {\r
+ puts stderr "Cannot create response file edif_adcmv3.p3t: $rspFile"\r
+} else {\r
+ puts $rspFile "-rem\r
+-log edif_adcmv3.log\r
+-o edif_adcmv3_mp.par\r
+-pr edif_adcmv3.prf\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/multipar\" -p edif_adcmv3.p2t -f \"edif_adcmv3.p3t\" \"edif_adcmv3_map.ncd\" \"edif_adcmv3.ncd\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+if [catch {open edif_adcmv3.cm2 w} rspFile] {\r
+ puts stderr "Cannot create response file edif_adcmv3.cm2: $rspFile"\r
+} else {\r
+ puts $rspFile "-t edif_adcmv3.pt\r
+-to edif_adcmv3.twr\r
+-o edif_adcmv3.tcp\r
+-log edif_adcmv3.log\r
+-pr edif_adcmv3.prf\r
+-rpt edif_adcmv3.par\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$cpld_bin/checkpoint\" -p -f \"edif_adcmv3.cmp\" -f \"edif_adcmv3.cm2\" -arch LatticeECP2M \"edif_adcmv3.ncd\" -l 60"] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+file delete edif_adcmv3.cm2\r
+if [catch {open edif_adcmv3.t2b w} rspFile] {\r
+ puts stderr "Cannot create response file edif_adcmv3.t2b: $rspFile"\r
+} else {\r
+ puts $rspFile "-g CfgMode:Disable\r
+-g RamCfg:Reset\r
+-g ES:No\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$fpga_dir/bin/lin/bitgen\" -f \"edif_adcmv3.t2b\" -w \"edif_adcmv3.ncd\" \"edif_adcmv3.prf\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+\r
+########## Tcl recorder end at 04/29/10 17:40:31 ###########\r
+\r
+\r
+########## Tcl recorder starts at 04/29/10 18:35:01 ##########\r
+\r
+# Commands to make the Process: \r
+# Bitstream Report - HTML\r
+if [catch {open edif_adcmv3.info w} rspFile] {\r
+ puts stderr "Cannot create response file edif_adcmv3.info: $rspFile"\r
+} else {\r
+ puts $rspFile "Project File: edif_adcmv3.syn\r
+Location: $proj_dir\r
+Family: LatticeECP2M\r
+Design Entry Type: EDIF\r
+Synthesis Tool: Synplify\r
+Device: LFE2M100E\r
+Speed grade: -6\r
+Package type: FPBGA900\r
+Operating conditions: Commercial\r
+Part name: LFE2M100E-6F900C\r
+Project source: edif_adcmv3.edn\r
+Logical Preference File: edif_adcmv3.lpf\r
+Preference File: edif_adcmv3.prf\r
+"\r
+ close $rspFile\r
+}\r
+if [catch {open edif_adcmv3.rsp w} rspFile] {\r
+ puts stderr "Cannot create response file edif_adcmv3.rsp: $rspFile"\r
+} else {\r
+ puts $rspFile "-mrp edif_adcmv3.mrp\r
+-pad edif_adcmv3.pad\r
+-par edif_adcmv3.par\r
+-ptwr edif_adcmv3.twr\r
+-bgn edif_adcmv3.bgn\r
+-info edif_adcmv3.info\r
+edif_adcmv3\r
+"\r
+ close $rspFile\r
+}\r
+if [runCmd "\"$fpga_dir/bin/lin/htmlrpt\" -f \"edif_adcmv3.rsp\""] {\r
+ return\r
+} else {\r
+ vwait done\r
+ if [checkResult $done] {\r
+ return\r
+ }\r
+}\r
+file delete edif_adcmv3.info\r
+file delete edif_adcmv3.rsp\r
+\r
+########## Tcl recorder end at 04/29/10 18:35:01 ###########\r
+\r
--- /dev/null
+SCHEMATIC START ;
+# map: version ispLever_v8.0_PROD_Build (41) -- WARNING: Map write only section -- Wed Jun 23 16:09:10 2010
+
+SYSCONFIG PERSISTENT=OFF CONFIG_MODE=SPI DONE_OD=OFF DONE_EX=OFF MCCLK_FREQ=34 CONFIG_SECURE=OFF WAKE_UP=21 COMPRESS_CONFIG=OFF INBUF=OFF ENABLE_NDR=OFF ;
+PGROUP "THE_SLAVE_BUS/THE_SPI_MASTER/SPI_group"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_31"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_32"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_33"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_34"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_35"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_36"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_37"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_38"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10039"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10040"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10041"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10042"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10043"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10044"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10045"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10046"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10047"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10048"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10049"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10050"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10051"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10052"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10053"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10054"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10055"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10056"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10057"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10058"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10059"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10060"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10061"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10062"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10063"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10064"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10065"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10066"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10067"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10068"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10069"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10070"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10071"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10072"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10073"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10074"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10075"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10076"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10077"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10078"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10079"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10080"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10081"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10082"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10083"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10084"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10085"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10086"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10087"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10088"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10089"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10090"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10091"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10092"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10093"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10094"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10095"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10096"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10097"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10098"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10099"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10100"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10101"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10102"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10103"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10104"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10105"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10106"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10107"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10108"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10109"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10110"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10111"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10112"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10113"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10114"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10115"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10116"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10117"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10118"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10119"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10120"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10121"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10122"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10123"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10124"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10173"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10183"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10234"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10235"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10236"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10237"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10238"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10239"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10240"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10241"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10242"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10243"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10244"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10245"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10246"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10247"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10248"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_10249"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10442"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10443"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10444"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10445"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10446"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10447"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10448"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10449"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10450"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_10762"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11838"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11839"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/tx_sel_x_i_0_o2_0_0/SLICE_11840"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11841"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11842"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11843"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11844"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11845"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_11846"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12055"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12056"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12057"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12058"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12059"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12060"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12061"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12062"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12063"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_12064"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12272"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12550"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12551"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12555"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12581"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12582"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12602"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12603"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12604"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12605"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12606"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12607"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12608"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12609"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12610"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12644"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12645"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12646"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12647"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12648"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12649"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_12650"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_12651"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12794"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12827"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12828"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12829"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12830"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12831"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12857"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12858"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12859"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_12860"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13038"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13039"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13040"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13041"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13042"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13043"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13044"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13045"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13046"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13047"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13048"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13049"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13050"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13051"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13052"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13053"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13054"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13055"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13056"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13057"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13058"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13059"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13060"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/THE_SPI_SLIM/SLICE_13061"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_13062"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_13063"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_13064"
+ COMP "THE_SLAVE_BUS/THE_SPI_MASTER/SLICE_13065";
+PGROUP "THE_RICH_TRB/RICH_TRB_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_49"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_50"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_51"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_52"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_53"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_54"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_55"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_56"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_57"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_58"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_59"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_60"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_61"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_62"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_63"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_64"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_65"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_66"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_67"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_139"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_140"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_141"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_142"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_143"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_144"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_145"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_146"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_147"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_148"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_149"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_150"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_151"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_152"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_153"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_154"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_155"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_156"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_157"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_158"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_159"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_160"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_161"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_162"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_163"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_495"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_496"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_497"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_498"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_499"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_500"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_501"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_502"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_503"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_504"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_505"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_506"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_507"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_508"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_8202"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_8203"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8335"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8336"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8337"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8338"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8339"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8340"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8341"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8342"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8343"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_8344"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8345"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8346"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8347"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8348"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8349"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8350"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8369"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8370"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8371"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8372"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8373"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8374"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8375"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8376"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8395"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8396"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8400"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8401"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8406"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8407"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8419"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8420"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8579"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8580"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8581"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_8582"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8583"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8584"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8585"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8586"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8587"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8588"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8589"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_8590"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8815"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8816"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8817"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8818"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8819"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8820"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8821"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8822"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8823"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8824"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8825"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8826"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8827"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8828"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8829"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8830"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8831"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8832"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8833"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8834"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8835"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8836"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8837"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8838"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8839"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8840"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8841"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8842"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8843"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8844"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8845"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8846"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8847"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8848"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8849"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8850"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8851"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8852"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8853"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_8854"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9080"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9081"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9082"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9083"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9084"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9085"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9086"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9087"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9088"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9089"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9090"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9091"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_9238"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_9239"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_9243"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_9244"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9249"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9250"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9251"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9252"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9253"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_9254"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_9255"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_9256"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11043"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11044"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11045"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11046"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11047"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11048"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11049"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11050"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_11052"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11062"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11063"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11064"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11065"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11066"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11067"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11068"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11070"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11071"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11072"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11073"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11074"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11075"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11076"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11077"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11078"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11080"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_11081"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_11215"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/next_state_3_0__m18/SLICE_11607"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/next_state_3_0__m37/SLICE_11608"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/next_state_3_0__m50/SLICE_11609"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/next_state_3_0__m60/SLICE_11610"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/next_state_3_0__m53/SLICE_11611"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/reset_timecounter_2/SLICE_11612"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/next_state_3_0__m9/SLICE_11613"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12085"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12086"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12087"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12088"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12089"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12090"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12091"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12092"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12113"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12114"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12115"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12116"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12117"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12118"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12119"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12120"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12121"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12122"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12123"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12124"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12125"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12126"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12127"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12128"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12129"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12130"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12131"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12132"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_12133"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12309"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_12315"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12557"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12595"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12617"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12621"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12622"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12659"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12660"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12661"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12662"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12677"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12678"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12679"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12803"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12810"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12843"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12867"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12868"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12929"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12931"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12944"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_12945"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_12946"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_12979"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_12980"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13152"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13153"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13154"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13155"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13156"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13157"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13158"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_gen_1wire_onewire_interface/SLICE_13159"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13234"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13235"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13236"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13237"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13238"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13239"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13240"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13241"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13242"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13243"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13244"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13245"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13246"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13247"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13248"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13249"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13250"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13251"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13252"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13253"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13254"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13255"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13256"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13257"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13258"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13259"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13260"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13261"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13262"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13263"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13264"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_ipu_apl_the_ipudata_apl/SLICE_13265"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_13266"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_13267"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_gentrgapi_the_trigger_apl/SLICE_13268"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13351"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13352"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13353"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13354"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13355"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13356"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13357"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13358"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13359"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13360"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13361"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13362"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13363"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13364"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13365"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13366"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13367"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13368"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13369"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13370"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13371"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13372"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13373"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13374"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13375"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13376"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13377"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13378"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13379"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13380"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13381"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/SLICE_13382";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/HUBLOGIC_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_68"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_69"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_70"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_71"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_72"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8201"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8327"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8328"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8329"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8330"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8331"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8332"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8333"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_8334"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9092"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9093"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9096"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9186"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9215"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9216"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9217"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9218"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9219"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9220"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9221"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9222"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9223"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9224"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9225"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9226"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9227"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9228"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9229"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_9230"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_11859"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_12093"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12310"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12618"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12797"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12804"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12836"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12863"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12864"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12930"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_12969"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13160"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13161"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13162"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13163"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13164"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13165"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13166"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13167"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13168"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13169"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13170"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13171"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13172"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13173"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13174"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13175"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/SLICE_13176"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_13177"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_13178"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_13179"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_13180"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_13181"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_13182"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_13183"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/SLICE_13184"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/THE_STAT_RAM/ram_1_ram_1_0_0";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/RegIO_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_73"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_74"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_75"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_76"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_77"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_78"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_79"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_80"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_81"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_82"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_83"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_84"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_85"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_86"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_87"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_88"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_89"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_90"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_91"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_92"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_93"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_94"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_95"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_96"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_97"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_98"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_99"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_100"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_101"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_102"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_103"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_104"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_105"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_106"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_107"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_108"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_109"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_110"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_111"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_112"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_113"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_114"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_115"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_116"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_117"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_118"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_119"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_120"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_121"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_122"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_123"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_124"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_125"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_126"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_127"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_128"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_129"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_130"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_131"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_132"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_133"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_134"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_135"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_136"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_137"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_138"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8366"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8393"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8394"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8397"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8398"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8399"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8408"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_8457"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9094"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9095"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9097"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9098"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9099"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9100"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9101"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9102"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9103"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9104"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9105"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9106"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9107"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9108"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9109"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9110"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9111"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9112"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9113"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9114"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9115"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9116"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9117"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9118"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9119"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9120"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9121"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9122"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9123"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9124"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9125"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9126"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9127"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9128"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9129"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9130"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9131"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9132"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9133"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9134"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9135"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9136"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9137"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9138"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9139"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9140"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9141"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9142"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9143"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9144"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9145"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9146"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9147"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9148"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9149"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9150"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9151"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9152"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9153"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9154"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9155"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9156"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9157"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9158"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9159"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9160"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9161"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9162"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9163"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9164"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9165"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9166"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9167"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9168"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9170"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9171"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9172"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9173"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9174"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9175"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9176"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9177"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9178"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9179"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9180"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9181"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9182"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9183"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9184"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9185"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9187"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9188"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9189"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9190"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/board_rom/SLICE_9191"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/board_rom/SLICE_9192"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/board_rom/SLICE_9193"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/board_rom/SLICE_9194"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/board_rom/SLICE_9195"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/board_rom/SLICE_9196"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9197"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9198"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9199"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9200"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9201"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9202"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9203"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9204"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9205"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9206"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9207"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9208"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9209"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9210"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9211"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9212"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9213"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9214"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9231"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9232"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9233"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9234"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9235"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9236"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9237"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9248"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_9292"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10707"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10708"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10709"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10710"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10711"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10712"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10713"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10714"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10715"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10716"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10717"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10718"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10719"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_10720"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11135"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11137"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11169"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11170"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11171"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11172"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11173"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11174"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11175"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11176"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11177"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11178"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11179"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11180"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11181"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11182"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11183"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11184"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11186"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11189"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_2/SLICE_11614"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_6/SLICE_11615"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_11/SLICE_11616"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_10/SLICE_11617"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_8/SLICE_11618"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_7/SLICE_11619"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_5/SLICE_11620"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_14/SLICE_11621"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_1/SLICE_11622"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_13/SLICE_11623"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_9/SLICE_11624"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_4/SLICE_11625"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_0/SLICE_11626"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_3/SLICE_11627"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_12/SLICE_11628"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_14_i_m2_15/SLICE_11629"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_6/SLICE_11630"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_11/SLICE_11631"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_9/SLICE_11632"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_9/SLICE_11633"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_8/SLICE_11634"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_12/SLICE_11635"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_14/SLICE_11636"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_10/SLICE_11637"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_14/SLICE_11638"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_10/SLICE_11639"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_5/SLICE_11640"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_13/SLICE_11641"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_13/SLICE_11642"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_4/SLICE_11643"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_0_12/SLICE_11644"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_bm_RNO_0_8/SLICE_11645"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_18_RNO_0_7/SLICE_11646"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_13/SLICE_11647"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_6/SLICE_11648"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_2/SLICE_11649"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_2/SLICE_11650"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_11/SLICE_11651"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_11/SLICE_11652"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_bm_RNO_1_7/SLICE_11653"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_9/SLICE_11654"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_9/SLICE_11655"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_4/SLICE_11656"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_4/SLICE_11657"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_6/SLICE_11658"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_6/SLICE_11659"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_0/SLICE_11660"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_3/SLICE_11661"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_3/SLICE_11662"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_14/SLICE_11663"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_10/SLICE_11664"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_8/SLICE_11665"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_12/SLICE_11666"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_5/SLICE_11667"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_1/SLICE_11668"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_5/SLICE_11669"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_11_1/SLICE_11670"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_14/SLICE_11671"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_10/SLICE_11672"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_5/SLICE_11673"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_4/SLICE_11674"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_13/SLICE_11675"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_1_12/SLICE_11676"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_bm_RNO_8/SLICE_11677"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_bm_RNO_0_7/SLICE_11678"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_18_RNO_1_7/SLICE_11679"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_12_0/SLICE_11680"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_15_2/SLICE_11681"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_bm_RNO_11/SLICE_11682"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_15_7/SLICE_11683"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_15_6/SLICE_11684"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_15_0/SLICE_11685"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_15_3/SLICE_11686"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_15_1/SLICE_11687"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_15_4/SLICE_11688"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_15_i_m2_15/SLICE_11689"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_3/SLICE_11690"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_1/SLICE_11691"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_2/SLICE_11692"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_13_0/SLICE_11693"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_2_m2_2_15/SLICE_11694"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/current_state_RNIRU6N2_10/SLICE_11695"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_11/SLICE_11696"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_9/SLICE_11697"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_14/SLICE_11698"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_10/SLICE_11699"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_12/SLICE_11700"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_8/SLICE_11701"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_5/SLICE_11702"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/next_API_DATA_OUT_20_13/SLICE_11703"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11829"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11830"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_11860"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12094"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12095"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12096"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12097"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12098"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12099"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12100"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12101"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12102"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12103"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12104"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12105"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12106"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12107"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12108"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12109"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12110"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12111"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12112"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12311"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12312"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12313"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12314"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12556"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12619"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12620"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12663"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12664"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12665"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12666"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12667"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12668"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12669"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12670"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12671"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12672"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12673"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12674"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12675"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12676"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12805"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12806"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12807"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12808"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12809"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12837"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12838"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12839"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12840"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12841"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12842"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12865"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12866"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12907"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12908"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12936"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12977"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_12978"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13185"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13186"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13187"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13188"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13189"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13190"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13191"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13192"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13193"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13194"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13195"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13196"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13197"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13198"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13199"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13200"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13201"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13202"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13203"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13204"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13205"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13206"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13207"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13208"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13209"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13210"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13211"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13212"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13213"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13214"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13215"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13216"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13217"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13218"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13219"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13220"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13221"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13222"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13223"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13224"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13225"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13226"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13227"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13228"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13229"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13230"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13231"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13232"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/SLICE_13233";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/API_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_164"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_165"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_166"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_167"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_168"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_169"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_170"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_171"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_172"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_173"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_174"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_175"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_176"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_177"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_178"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_179"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_180"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_181"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_182"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_183"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_184"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_185"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_186"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_187"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_188"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_189"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_190"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_191"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_192"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_193"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_194"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_195"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_196"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_197"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_198"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_199"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_200"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_201"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_202"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_203"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_204"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_205"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_206"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_207"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_208"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_209"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_210"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_211"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_212"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_213"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_214"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_215"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_216"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_217"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_218"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_219"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_220"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_221"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_222"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_223"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_224"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_225"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_226"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_227"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_228"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_229"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_230"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_231"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_232"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_233"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_234"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_235"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_236"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_237"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_238"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_239"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_240"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_241"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_242"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_243"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8360"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8361"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8362"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8363"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8364"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8365"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8368"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8385"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8386"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8387"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8388"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8389"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8390"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8391"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8392"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8404"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8405"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_8412"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8413"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_8424"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8458"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8459"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8460"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8461"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_8976"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8977"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8978"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8979"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8980"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8981"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8982"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8983"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8984"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8985"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8986"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8987"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8988"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8989"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8990"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8991"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8992"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8993"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8994"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8995"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8996"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8997"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8998"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8999"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_9000"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_9001"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9002"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9003"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9004"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_9005"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9006"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9007"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9008"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9009"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9010"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9011"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9012"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9013"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9014"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9015"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9016"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9017"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9018"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9019"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9020"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9021"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9022"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9023"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9024"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9025"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9026"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9027"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9028"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9029"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9030"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9031"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9032"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_9034"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9035"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9036"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9037"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9038"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9039"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9040"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9041"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9042"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9043"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9044"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9045"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9046"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9047"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9048"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9049"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9050"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9051"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9052"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9053"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9054"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9055"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9056"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9057"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9058"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9059"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9060"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9061"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9062"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9063"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9064"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9065"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9066"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9067"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9068"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9069"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9070"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9071"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9072"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9073"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9074"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9075"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9076"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9077"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9078"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_9079"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_14/SLICE_11704"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_1/SLICE_11705"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_5/SLICE_11706"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_6/SLICE_11707"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_7/SLICE_11708"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_13/SLICE_11709"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_15/SLICE_11710"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_12/SLICE_11711"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_10/SLICE_11712"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_9/SLICE_11713"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_8/SLICE_11714"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_3/SLICE_11715"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_0/SLICE_11716"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_11/SLICE_11717"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/state_to_apl_ns_1_0__m16/SLICE_11718"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_11861"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_11862"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_11863"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_11864"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_11865"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_11866"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_12042"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12134"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12135"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12136"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12137"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12316"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12552"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12558"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12559"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12580"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12587"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12623"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12624"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12680"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12792"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_12811"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12812"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12813"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_12909"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_12947"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12974"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_13269"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_13270"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_13271"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13272"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13273"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13274"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13275"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13276"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13277"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13278"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13279"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13280"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13281"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_13993"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/pdp_ram_0_0_0"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/pdp_ram_0_0_0";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/API_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_244"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_245"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_246"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_247"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_248"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_249"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_250"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_251"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_252"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_253"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_254"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_255"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_256"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_257"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_258"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_259"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_260"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_261"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_262"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_263"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_264"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_265"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_266"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_267"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_268"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_269"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_270"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_271"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_272"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_273"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_274"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_275"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_276"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_277"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_278"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_279"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_280"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_281"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_282"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_283"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_284"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_285"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_286"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_287"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_288"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_289"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_290"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_291"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_292"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_293"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_294"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_295"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_296"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_297"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_298"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_299"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_300"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_301"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_302"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_303"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_304"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_305"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_306"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_307"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_308"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_309"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_310"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_311"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_312"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_313"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_314"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_315"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_316"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_317"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_318"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_319"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_320"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_321"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_322"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_323"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8351"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8352"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8353"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8354"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8355"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8356"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8357"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8358"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8359"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8367"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8377"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8378"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8379"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8380"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8381"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8382"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8383"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8384"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8402"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8403"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_8409"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_8410"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_8411"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8422"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8423"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_8704"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_8705"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8706"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8707"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8708"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8709"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8710"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8711"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8712"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8713"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8714"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8715"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8716"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8717"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_8718"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8719"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8720"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8721"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8722"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8723"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8724"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8725"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8726"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8727"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8728"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8729"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_8730"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8731"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8732"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_8733"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8734"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8735"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8736"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8737"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_8738"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8739"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8740"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8741"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8742"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8743"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8744"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8745"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8746"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8747"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8748"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8749"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8750"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8751"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8752"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8753"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8754"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8755"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8756"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8757"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8758"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8759"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8760"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8761"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8762"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8764"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8765"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8766"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8767"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8768"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8769"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8770"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8771"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8772"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8773"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8774"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8775"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8776"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8777"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8778"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8779"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8780"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8781"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8782"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8783"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8784"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8785"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8786"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8787"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8788"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8789"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8790"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8791"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8792"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8793"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8794"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8795"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8796"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8797"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8798"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8799"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8800"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8801"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8802"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8803"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8805"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8806"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8807"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8808"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8809"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8810"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8811"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8812"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8813"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_8814"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_9291"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/state_to_apl_RNO_0_1/SLICE_11719"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_0/SLICE_11720"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_7/SLICE_11721"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_9/SLICE_11722"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_12/SLICE_11723"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_13/SLICE_11724"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_5/SLICE_11725"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_11/SLICE_11726"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_15/SLICE_11727"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_14/SLICE_11728"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_10/SLICE_11729"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_8/SLICE_11730"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_6/SLICE_11731"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_3/SLICE_11732"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/next_INT_MASTER_DATA_OUT_7_1/SLICE_11733"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_11867"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_12043"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12138"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12139"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12140"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12141"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12142"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12560"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12561"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12625"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12626"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12681"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12682"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_12793"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12814"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_12815"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12844"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12845"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12846"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12869"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12932"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12937"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12971"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_12981"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/SLICE_13282"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_13283"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL2/SLICE_13284"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF_TO_APL/gen_version_0_sbuf/SLICE_13285"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SBUF/gen_version_0_sbuf/SLICE_13286"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13287"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13288"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13289"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13290"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13291"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13292"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13293"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/SLICE_13294"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/SLICE_13994"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_INT_FIFO_TO_INT/fifo/pdp_ram_0_0_0"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/GEN_FIFO_TO_APL_FIFO_TO_APL/fifo/pdp_ram_0_0_0";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_324"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_325"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_326"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_327"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_328"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_329"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_330"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_331"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_332"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_333"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_334"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_335"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_336"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8214"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8281"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8282"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8283"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8284"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8285"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8286"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8299"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8300"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8462"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8463"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8930"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8931"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8932"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8933"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8934"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8935"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8936"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8937"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8938"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8939"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8940"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8941"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8942"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8943"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8944"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8945"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8946"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8947"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8948"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8949"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8950"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8951"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8952"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8953"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8954"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8955"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8956"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8957"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8958"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8959"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8960"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8961"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8962"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8963"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8964"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8965"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8966"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8967"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8968"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8969"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8970"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8971"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8972"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8973"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_9242"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_9247"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/un1_current_EOB_word_1_sqmuxa_1_0/SLICE_11734"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_5/SLICE_11735"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_14/SLICE_11736"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_4/SLICE_11737"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_6/SLICE_11738"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_8/SLICE_11739"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_13/SLICE_11740"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_15/SLICE_11741"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_12/SLICE_11742"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_11/SLICE_11743"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_10/SLICE_11744"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_9/SLICE_11745"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_7/SLICE_11746"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_3/SLICE_11747"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11868"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11869"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11870"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11871"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11872"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12143"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12144"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_12145"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12146"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12147"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12148"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12149"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_12150"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12151"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12562"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12596"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12627"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12683"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12684"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12685"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12686"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12687"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12870"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12871"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12872"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12910"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12925"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12943"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12948"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12972"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_13295"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_13296"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13297"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13298"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13299"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13300"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13301"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13302"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13303"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13304"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13305"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13306";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_337"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_338"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_339"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_340"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_341"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_342"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_343"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_344"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_345"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_346"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_347"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_348"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_349"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_350"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_351"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_352"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_353"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_354"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_355"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_356"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_357"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_358"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_359"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_360"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_361"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_362"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_363"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_364"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_365"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_366"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_367"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_368"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_369"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_370"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_371"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_372"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_373"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_374"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_375"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_376"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_377"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_378"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_379"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_380"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8426"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8443"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8444"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8445"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8446"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8447"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8448"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8449"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8450"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8455"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8456"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8863"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8864"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8865"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8866"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8867"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8868"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8869"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8870"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8871"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8872"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8873"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8874"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8875"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8876"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8877"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8878"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8879"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8880"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8881"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8882"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8883"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8884"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8885"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8886"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8887"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8888"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8889"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8890"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8891"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_8893"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_8894"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8896"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8897"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8898"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8899"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8900"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8901"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8902"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8903"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8904"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8905"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8906"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8907"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8908"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8909"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8910"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8911"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8912"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8913"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8914"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8915"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8916"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8917"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8918"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8919"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8920"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8974"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8975"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_11873"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12155"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12156"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12157"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_12158"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12159"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12160"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12588"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12688"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12689"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12690"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12691"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12795"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_12816"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12817"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12847"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12873"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12889"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12911"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12912"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_13309"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_13310"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_13311"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_13312"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_13313"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_13314"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/pdp_ram_0_0_0";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_381"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_382"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_383"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_384"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_385"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_386"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_387"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_388"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_389"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_390"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_391"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_392"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_393"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8210"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8263"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8264"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8265"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8266"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8267"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8268"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8269"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8270"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8291"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8292"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8660"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8661"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8662"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8663"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8664"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8665"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8666"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_8667"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8668"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8669"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8670"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8671"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8672"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8673"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8674"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8675"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8676"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8677"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8678"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8679"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8680"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8681"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8682"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8683"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8684"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8685"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8686"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8687"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8688"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8689"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8690"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8691"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8692"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8693"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8694"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8695"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8696"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8697"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8698"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8699"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8700"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8701"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8702"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8703"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_9241"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_9246"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_cnsts2/SLICE_11748"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_6/SLICE_11749"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_4/SLICE_11750"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_14/SLICE_11751"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_15/SLICE_11752"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_11/SLICE_11753"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_5/SLICE_11754"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_3/SLICE_11755"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_8/SLICE_11756"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_9/SLICE_11757"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_10/SLICE_11758"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_12/SLICE_11759"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_13/SLICE_11760"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/current_output_data_buffer_4_7/SLICE_11761"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11874"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11875"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11876"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12161"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12162"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_12163"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12164"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12165"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12166"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12167"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12168"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12169"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_12170"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12563"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12597"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12628"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12629"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12692"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12693"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12694"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12695"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12848"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12874"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_12913"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12933"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12934"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12973"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12982"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12983"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/GEN_CRC_CRC_gen/SLICE_13315"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_13316"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13317"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13318"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13319"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13320"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13321"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13322"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13323"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13324"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13325"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13326"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13995";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_394"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_395"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_396"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_397"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_398"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_399"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_400"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_401"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_402"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_403"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_404"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_405"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_406"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_407"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_408"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_409"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_410"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_411"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_412"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_413"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_414"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_415"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_416"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_417"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_418"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_419"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_420"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_421"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_422"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_423"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_424"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_425"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_426"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_427"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_428"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_429"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_430"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_431"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_432"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_433"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_434"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_435"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_436"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_437"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8421"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8435"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8436"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8437"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8438"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8439"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8440"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8441"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8442"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8453"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8454"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8591"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8592"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8593"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8594"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8595"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8596"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8597"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8598"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8599"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8600"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8601"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_8602"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8603"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8604"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8605"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8606"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8607"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8608"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8609"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8610"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8611"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8612"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8613"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8614"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8615"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8616"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8617"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8618"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8619"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_8621"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_8622"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8624"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8625"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8626"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8627"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8628"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8629"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8630"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8631"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8632"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8633"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8634"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8635"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8636"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8637"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8638"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8639"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8640"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8641"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8642"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8643"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8644"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8645"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8646"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8647"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8648"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8649"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8650"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_11877"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12173"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12174"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12175"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_12176"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12177"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12178"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12589"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12696"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12697"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12698"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12699"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12796"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_12818"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12819"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12849"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12875"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12890"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_12914"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12915"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_13330"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_13331"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_crc_THE_CRC/SLICE_13332"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_13333"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_13334"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_13335"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_13336"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/pdp_ram_0_0_0";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_438"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_439"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_440"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_441"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_442"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_443"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_444"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_445"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_446"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_447"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_448"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_449"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_450"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8208"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8248"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8249"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8250"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8251"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8252"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8253"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8254"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8255"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8256"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8257"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8258"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8259"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8289"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8290"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8527"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8528"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8529"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8530"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8531"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8532"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8533"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8534"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8535"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8536"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8537"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8538"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8539"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8540"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8541"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8542"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8543"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_8544"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8545"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8546"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8547"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8548"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8549"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8550"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8551"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8552"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8553"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8554"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8555"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8556"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8557"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8558"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8559"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8560"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8561"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8562"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8563"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8564"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8565"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8566"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8567"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8568"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8569"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_8570"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_9240"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_9245"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11878"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11879"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11880"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_11881"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12179"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12180"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12181"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12182"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12183"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12184"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12185"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12186"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12187"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12553"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12564"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12565"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12590"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12598"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12700"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12701"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12702"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12820"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12850"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12916"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12938"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_12939"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/THE_SBUF/gen_version_0_sbuf/SLICE_13337"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13338"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13339"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13340"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13341"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13342"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13343"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13344"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13345"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13346"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13347"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13348"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/SLICE_13349";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_451"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_452"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_453"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_454"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_455"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_456"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_457"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_458"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_459"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_460"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_461"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_462"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_463"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_464"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_465"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_466"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_467"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_468"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_469"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_470"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_471"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_472"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_473"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_474"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_475"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_476"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_477"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_478"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_479"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_480"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_481"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_482"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_483"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_484"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_485"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_486"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_487"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_488"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_489"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_490"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_491"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_492"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_493"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_494"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8425"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8427"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8428"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8429"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8430"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8431"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8432"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8433"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8434"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8451"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8452"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8464"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8465"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8466"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8467"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8468"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8469"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8470"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8471"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8472"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8473"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8474"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8475"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8476"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8477"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8478"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8479"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8480"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8481"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8482"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8483"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_8485"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_8486"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8488"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8489"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8490"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8491"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8492"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8493"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8494"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8495"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8496"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8497"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8498"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8499"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8500"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8501"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/gen_init_sbuf_SBUF_INIT/gen_version_0_sbuf/SLICE_8502"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8503"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8504"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8505"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8506"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8507"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8508"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8509"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8510"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8511"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8512"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8513"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8514"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8515"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8516"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8571"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8572"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8573"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8574"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8575"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8576"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8577"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_8578"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_12191"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12192"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12591"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12821"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12851"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12891"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/SLICE_12917"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_12918"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/SLICE_13350"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/THE_FIFO/fifo/pdp_ram_0_0_0";
+PGROUP "THE_RICH_TRB/THE_MEDIA_INTERFACE/media_interface_group"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_509"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_510"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_511"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_512"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_513"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_514"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_515"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_516"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_517"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_518"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_519"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_520"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_521"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_522"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_523"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_524"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_525"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_526"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_527"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_528"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_529"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_530"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_531"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_532"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_533"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_534"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_535"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_536"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_537"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_538"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_539"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_540"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_541"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_542"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_543"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_544"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_545"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_546"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_547"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_548"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_549"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_550"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_551"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_552"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_553"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_554"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_555"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_556"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_557"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_558"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_559"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_560"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_561"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_562"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_563"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_564"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_565"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_566"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_567"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_568"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_569"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_570"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_571"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_572"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_573"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_574"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_575"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_576"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_577"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_578"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_579"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_580"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_581"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_582"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_583"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_584"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_585"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_586"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_587"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_588"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_589"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_590"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_591"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_592"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_593"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_594"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_595"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_4348"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_4478"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8028"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8029"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8030"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8031"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8032"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8033"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8034"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8035"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8036"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8037"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8038"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8039"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8040"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8041"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8042"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8043"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8044"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8045"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8046"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8047"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8048"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8049"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8050"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8051"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8052"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8053"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8054"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8055"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8056"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8057"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8058"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8059"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8060"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8061"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8062"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8063"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8064"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8065"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8066"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8067"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8068"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8069"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8070"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8071"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8072"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8073"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8074"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8075"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8076"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8077"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8078"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8079"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8080"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8081"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8082"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8083"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_8084"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8085"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8086"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8087"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8088"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8089"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8090"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8091"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8092"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8093"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8094"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8095"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8096"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8097"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8098"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8099"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8100"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8101"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8102"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8103"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8104"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8105"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8106"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8107"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8108"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8109"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8110"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8111"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8112"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8113"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8114"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8115"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8116"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8117"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8118"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8119"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8120"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8121"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8122"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8123"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8124"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8125"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8126"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8127"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8128"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8129"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_8130"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8132"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8133"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8134"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8135"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8136"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8137"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8138"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8139"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8140"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_K_DELAY/SLICE_8141"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8142"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8143"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8144"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8145"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8146"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8147"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_STATUS_SYNC/SLICE_8148"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_STATUS_SYNC/SLICE_8149"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8150"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8151"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8152"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8153"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8154"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8155"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8156"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8157"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8158"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8159"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8160"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8161"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8162"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8163"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8164"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8165"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8166"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8167"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8168"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8169"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8170"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8171"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8172"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8173"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8174"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8175"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8176"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_DATA_DELAY/SLICE_8177"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_K_DELAY/SLICE_8178"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8179"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8180"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8181"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8182"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8183"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8184"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8185"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_8188"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_RX_ALLOW_SYNC/SLICE_8189"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8190"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8191"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8192"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8193"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8194"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8195"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8196"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8197"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8198"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_8199"
+ COMP "SLICE_8200"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9271"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9272"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9273"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9274"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9275"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9276"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9277"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9278"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9279"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9280"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9281"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9282"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9283"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9284"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9285"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9286"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_9287"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9288"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9289"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_9290"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_11190"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_RNO_0_3/SLICE_11762"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/ce_tctr_RNO_1/SLICE_11763"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_RNO_0_2/SLICE_11764"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_RNO_0_1/SLICE_11765"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/rx_allow_RNO_0/SLICE_11766"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/CURRENT_STATE_RNO_0_0/SLICE_11767"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12193"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12194"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12195"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12196"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12197"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12198"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12199"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12200"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12201"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12202"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12203"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12204"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12205"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12206"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12207"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/SLICE_12208"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12209"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12210"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_12211"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_12554"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12566"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_12703"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_12704"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_12705"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_12706"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12822"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12823"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12824"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12825"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12852"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12853"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12854"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12855"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12919"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_12920"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12921"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/SLICE_12922"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_12935"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_12940"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/SLICE_13383"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13384"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13385"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13386"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13387"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13388"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13389"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_SFP_LSM/SLICE_13390"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_13391"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_13392"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_13393"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_13394"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/SLICE_13395"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_FPGA_TO_SFP/FIFO_DP_BRAM/pdp_ram_0_0_0"
+ COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/THE_FIFO_SFP_TO_FPGA/FIFO_DP_BRAM/pdp_ram_0_0_0";
+PGROUP "THE_APV_TRGCTRL/APV_TRG_CTRL_group"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_596"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_597"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_598"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_599"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_600"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_601"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_602"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_603"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_604"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_605"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_606"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_607"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_608"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_609"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_610"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_611"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_612"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_613"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_614"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_615"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_616"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_617"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_618"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_619"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_620"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_621"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_622"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_623"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_624"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_625"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_626"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_627"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_628"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_629"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_630"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_631"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_632"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_633"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_634"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_635"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_636"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_637"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_638"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_639"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_640"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_641"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_642"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_643"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_644"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_645"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_646"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_647"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_648"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_649"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_650"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_651"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_652"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_653"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_654"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_655"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_656"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_657"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_0/SLICE_3971"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3972"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3973"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_1/SLICE_3974"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3975"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3976"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_2/SLICE_3977"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3978"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3979"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_3/SLICE_3980"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3981"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3982"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_4/SLICE_3983"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3984"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3985"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_5/SLICE_3986"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3987"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3988"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_6/SLICE_3989"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3990"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3991"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_7/SLICE_3992"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3993"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3994"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_8/SLICE_3995"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3996"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3997"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/mem_0_9/SLICE_3998"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_3999"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_4000"
+ COMP "THE_APV_TRGCTRL/SC_TRG0_STRECH/SLICE_4911"
+ COMP "THE_APV_TRGCTRL/SC_TRG0_STRECH/SLICE_4912"
+ COMP "THE_APV_TRGCTRL/SC_TRG0_STRECH/SLICE_4913"
+ COMP "THE_APV_TRGCTRL/SC_TRG1_STRECH/SLICE_4914"
+ COMP "THE_APV_TRGCTRL/SC_TRG1_STRECH/SLICE_4915"
+ COMP "THE_APV_TRGCTRL/SC_TRG1_STRECH/SLICE_4916"
+ COMP "THE_APV_TRGCTRL/SC_TRG2_STRECH/SLICE_4917"
+ COMP "THE_APV_TRGCTRL/SC_TRG2_STRECH/SLICE_4918"
+ COMP "THE_APV_TRGCTRL/SC_TRG2_STRECH/SLICE_4919"
+ COMP "THE_APV_TRGCTRL/SC_TRG3_STRECH/SLICE_4920"
+ COMP "THE_APV_TRGCTRL/SC_TRG3_STRECH/SLICE_4921"
+ COMP "THE_APV_TRGCTRL/SC_TRG3_STRECH/SLICE_4922"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_4923"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_4924"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_4925"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_4926"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_4927"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_4928"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/THE_APVTRGSTART_SYNC/SLICE_4930"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/THE_APVTRGSTART_SYNC/SLICE_4931"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/THE_APVTRGSTART_SYNC/SLICE_4932"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/THE_APVTRGSTART_SYNC/SLICE_4933"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4934"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4935"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4936"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGDONE_SYNC/SLICE_4938"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGDONE_SYNC/SLICE_4939"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGDONE_SYNC/SLICE_4940"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGSENT_SYNC/SLICE_4942"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGSENT_SYNC/SLICE_4943"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGSENT_SYNC/SLICE_4944"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGSTART_SYNC/SLICE_4946"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGSTART_SYNC/SLICE_4947"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGSTART_SYNC/SLICE_4948"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4949"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4950"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4951"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/THE_APVTRGSTART_SYNC/SLICE_4952"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4953"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4954"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4955"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_4956"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4957"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4958"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4959"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGDONE_SYNC/SLICE_4961"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGDONE_SYNC/SLICE_4962"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGDONE_SYNC/SLICE_4963"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGSENT_SYNC/SLICE_4965"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGSENT_SYNC/SLICE_4966"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGSENT_SYNC/SLICE_4967"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGSTART_SYNC/SLICE_4969"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGSTART_SYNC/SLICE_4970"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGSTART_SYNC/SLICE_4971"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4972"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4973"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4974"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/THE_APVTRGSTART_SYNC/SLICE_4975"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4976"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4977"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4978"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_4979"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_4980"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_4981"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_4982"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGDONE_SYNC/SLICE_4984"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGDONE_SYNC/SLICE_4985"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGDONE_SYNC/SLICE_4986"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGSENT_SYNC/SLICE_4988"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGSENT_SYNC/SLICE_4989"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGSENT_SYNC/SLICE_4990"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGSTART_SYNC/SLICE_4992"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGSTART_SYNC/SLICE_4993"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGSTART_SYNC/SLICE_4994"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_4995"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_4996"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_4997"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/THE_APVTRGSTART_SYNC/SLICE_4998"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_4999"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_5000"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_5001"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_5002"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5003"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5004"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5005"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGDONE_SYNC/SLICE_5007"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGDONE_SYNC/SLICE_5008"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGDONE_SYNC/SLICE_5009"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGSENT_SYNC/SLICE_5011"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGSENT_SYNC/SLICE_5012"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGSENT_SYNC/SLICE_5013"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGSTART_SYNC/SLICE_5015"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGSTART_SYNC/SLICE_5016"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGSTART_SYNC/SLICE_5017"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5018"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5019"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5020"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/THE_APVTRGSTART_SYNC/SLICE_5021"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5022"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5023"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5024"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5025"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5026"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5027"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5028"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5029"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5030"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5031"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5032"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5033"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5034"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5035"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5036"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5037"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5038"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5039"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5040"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5041"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5042"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_5043"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5044"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5045"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5046"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5047"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5048"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5049"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5050"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/THE_TIME_TRG_3_SYNC/SLICE_5051"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5052"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5053"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5054"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5055"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5056"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5057"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5058"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5059"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5060"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5061"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5062"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5063"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5064"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5065"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5066"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5067"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5068"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5069"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5070"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5071"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5072"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5073"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5074"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5075"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5076"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5077"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5078"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5079"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5080"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5081"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5082"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5083"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5084"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5085"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_5086"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_5087"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_5088"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_5089"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_5090"
+ COMP "THE_APV_TRGCTRL/SLICE_5091"
+ COMP "THE_APV_TRGCTRL/SLICE_5092"
+ COMP "THE_APV_TRGCTRL/SLICE_5093"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5094"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5095"
+ COMP "THE_APV_TRGCTRL/SLICE_5096"
+ COMP "THE_APV_TRGCTRL/SLICE_5097"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5098"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5099"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5100"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5101"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_5102"
+ COMP "THE_APV_TRGCTRL/SLICE_5103"
+ COMP "THE_APV_TRGCTRL/SLICE_5104"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_5105"
+ COMP "THE_APV_TRGCTRL/SLICE_5106"
+ COMP "THE_APV_TRGCTRL/SLICE_5107"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5109"
+ COMP "THE_APV_TRGCTRL/THE_RESET_SYNC/SLICE_5110"
+ COMP "THE_APV_TRGCTRL/SLICE_10602"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_10605"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_10606"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_10607"
+ COMP "THE_APV_TRGCTRL/SLICE_10608"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/SLICE_10764"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_11053"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_11069"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_11079"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_11082"
+ COMP "THE_APV_TRGCTRL/THE_MAX_TRG/SLICE_11083"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_11192"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_11193"
+ COMP "THE_APV_TRGCTRL/SLICE_11194"
+ COMP "THE_APV_TRGCTRL/SLICE_11195"
+ COMP "THE_APV_TRGCTRL/SLICE_11196"
+ COMP "THE_APV_TRGCTRL/SLICE_11197"
+ COMP "THE_APV_TRGCTRL/SLICE_11198"
+ COMP "THE_APV_TRGCTRL/SLICE_11199"
+ COMP "THE_APV_TRGCTRL/SLICE_11200"
+ COMP "THE_APV_TRGCTRL/SLICE_11201"
+ COMP "THE_APV_TRGCTRL/SLICE_11202"
+ COMP "THE_APV_TRGCTRL/SLICE_11203"
+ COMP "THE_APV_TRGCTRL/SLICE_11204"
+ COMP "THE_APV_TRGCTRL/SLICE_11205"
+ COMP "THE_APV_TRGCTRL/SLICE_11206"
+ COMP "THE_APV_TRGCTRL/SLICE_11207"
+ COMP "THE_APV_TRGCTRL/SLICE_11208"
+ COMP "THE_APV_TRGCTRL/SLICE_11209"
+ COMP "THE_APV_TRGCTRL/SLICE_11210"
+ COMP "THE_APV_TRGCTRL/SLICE_11211"
+ COMP "THE_APV_TRGCTRL/SLICE_11212"
+ COMP "THE_APV_TRGCTRL/SLICE_11213"
+ COMP "THE_APV_TRGCTRL/SLICE_11214"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/THE_TRG_PRIORITY_PROC_todo_start_6_m2_0/SLICE_11768"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/THE_TRG_PRIORITY_PROC_todo_start_6_m2_1/SLICE_11769"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/THE_TRG_PRIORITY_PROC_todo_start_6_m2_2/SLICE_11770"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/THE_TRG_PRIORITY_PROC_todo_start_6_m2_3/SLICE_11771"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_0/SLICE_12317"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_1/SLICE_12318"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_2/SLICE_12319"
+ COMP "THE_APV_TRGCTRL/THE_APV_TRG_HANDLER_3/SLICE_12320"
+ COMP "THE_APV_TRGCTRL/THE_APV_SYNC_HANDLER/SLICE_12599"
+ COMP "THE_APV_TRGCTRL/THE_EDS_BUF/THE_EDS_BUFFER/SLICE_13396"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_13397"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_13398"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_13399"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_13400"
+ COMP "THE_APV_TRGCTRL/THE_REAL_TRG_HANDLER/SLICE_13401";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_700"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_701"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_702"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_703"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_704"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_705"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_706"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_707"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_708"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_709"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_710"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_711"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_712"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_713"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_714"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_715"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_716"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4145"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4146"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4147"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4148"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4149"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4150"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4151"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4152"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7180"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7181"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7182"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7184"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7185"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7186"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7188"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7191"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7192"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7193"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_7194"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7196"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7197"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7198"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7199"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7200"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7201"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7202"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7203"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7204"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7205"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_7206"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_10624"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_10625"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_10626"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_10686"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10702"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_13408"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_13409"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_13410"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/SLICE_13411"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_11_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_717"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_718"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_719"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_720"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_721"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_722"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_723"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_724"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_725"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_726"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_727"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_728"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_729"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_730"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_731"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_732"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_733"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4153"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4154"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4155"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4156"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4157"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4158"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4159"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4160"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7696"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7697"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7698"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7700"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7701"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7702"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7704"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7707"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7708"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7709"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_7710"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7712"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7713"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7714"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7715"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7716"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7717"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7718"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7719"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7720"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7721"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_7722"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_10663"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_10664"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_10665"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_10684"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10700"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_13412"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_13413"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_13414"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/SLICE_13415"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_9_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_734"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_735"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_736"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_737"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_738"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_739"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_740"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_741"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_742"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_743"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_744"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_745"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_746"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_747"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_748"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_749"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_750"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4161"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4162"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4163"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4164"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4165"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4166"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4167"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4168"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7610"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7611"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7612"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7614"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7615"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7616"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7618"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7621"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7622"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7623"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_7624"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7626"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7627"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7628"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7629"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7630"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7631"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7632"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7633"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7634"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7635"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_7636"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_10660"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_10661"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_10662"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_10683"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10699"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_13416"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_13417"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_13418"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/SLICE_13419"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_8_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_751"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_752"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_753"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_754"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_755"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_756"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_757"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_758"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_759"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_760"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_761"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_762"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_763"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_764"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_765"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_766"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_767"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4169"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4170"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4171"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4172"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4173"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4174"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4175"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4176"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7524"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7525"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7526"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7528"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7529"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7530"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7532"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7535"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7536"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7537"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_7538"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7540"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7541"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7542"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7543"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7544"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7545"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7546"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7547"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7548"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7549"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_7550"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_10636"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_10637"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_10638"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_10690"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10706"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_13420"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_13421"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_13422"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/SLICE_13423"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_15_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_768"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_769"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_770"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_771"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_772"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_773"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_774"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_775"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_776"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_777"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_778"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_779"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_780"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_781"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_782"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_783"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_784"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4177"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4178"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4179"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4180"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4181"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4182"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4183"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4184"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7438"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7439"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7440"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7442"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7443"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7444"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7446"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7449"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7450"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7451"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7452"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7454"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7455"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7456"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7457"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7458"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7459"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7460"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7461"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7462"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7463"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_7464"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_10633"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_10634"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_10635"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_10689"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10705"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_13424"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_13425"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_13426"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/SLICE_13427"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_14_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_785"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_786"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_787"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_788"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_789"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_790"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_791"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_792"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_793"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_794"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_795"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_796"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_797"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_798"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_799"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_800"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_801"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4185"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4186"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4187"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4188"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4189"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4190"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4191"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4192"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7266"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7267"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7268"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7270"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7271"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7272"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7274"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7277"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7278"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7279"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_7280"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7282"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7283"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7284"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7285"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7286"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7287"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7288"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7289"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7290"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7291"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_7292"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_10627"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_10628"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_10629"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_10687"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10703"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_13428"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_13429"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_13430"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/SLICE_13431"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_12_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_802"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_803"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_804"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_805"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_806"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_807"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_808"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_809"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_810"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_811"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_812"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_813"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_814"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_815"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_816"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_817"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_818"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4193"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4194"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4195"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4196"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4197"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4198"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4199"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4200"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7352"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7353"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7354"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7356"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7357"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7358"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7360"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7363"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7364"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7365"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7366"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7368"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7369"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7370"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7371"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7372"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7373"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7374"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7375"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7376"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7377"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_7378"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_10630"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_10631"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_10632"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_10688"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10704"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_13432"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_13433"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_13434"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_13435"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/SLICE_13436"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_13_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_819"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_820"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_821"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_822"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_823"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_824"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_825"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_826"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_827"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_828"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_829"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_830"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_831"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_832"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_833"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_834"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_835"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4201"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4202"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4203"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4204"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4205"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4206"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4207"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4208"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7094"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7095"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7096"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7098"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7099"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7100"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7102"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7105"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7106"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7107"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7108"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7110"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7111"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7112"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7113"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7114"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7115"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7116"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7117"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7118"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7119"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_7120"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_10621"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_10622"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_10623"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_10685"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10701"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_13437"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_13438"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_13439"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/SLICE_13440"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC1_10_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1092"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1093"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1094"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1095"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1096"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1097"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1098"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1099"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1100"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1101"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1102"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1103"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1104"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1105"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1106"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1107"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_1108"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4225"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4226"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4227"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4228"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4229"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4230"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4231"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4232"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6406"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6407"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6408"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6410"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6411"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6412"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_6414"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6417"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6418"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6419"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_6420"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6422"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6423"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6424"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6425"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6426"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6427"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6428"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6429"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6430"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6431"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_6432"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_10618"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_10619"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_10620"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_10675"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10691"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_13502"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_13503"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_13504"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/SLICE_13505"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_0_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1109"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1110"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1111"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1112"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1113"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1114"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1115"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1116"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1117"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1118"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1119"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1120"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1121"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1122"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1123"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1124"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_1125"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4233"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4234"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4235"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4236"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4237"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4238"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4239"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4240"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6922"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6923"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6924"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6926"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6927"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6928"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_6930"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6933"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6934"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6935"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_6936"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6938"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6939"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6940"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6941"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6942"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6943"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6944"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6945"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6946"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6947"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_6948"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_10654"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_10655"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_10656"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_10681"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10697"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_13506"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_13507"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_13508"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_13509"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/SLICE_13510"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_6_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1126"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1127"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1128"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1129"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1130"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1131"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1132"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1133"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1134"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1135"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1136"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1137"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1138"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1139"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1140"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1141"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_1142"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4241"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4242"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4243"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4244"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4245"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4246"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4247"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4248"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7008"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7009"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_7010"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7012"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7013"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_7014"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_7016"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7019"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7020"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_7021"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_7022"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7024"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7025"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7026"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7027"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7028"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7029"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7030"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7031"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7032"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7033"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_7034"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_10657"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_10658"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_10659"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_10682"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10698"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_13511"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_13512"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_13513"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_13514"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/SLICE_13515"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_7_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1143"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1144"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1145"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1146"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1147"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1148"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1149"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1150"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1151"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1152"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1153"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1154"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1155"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1156"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1157"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1158"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_1159"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4249"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4250"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4251"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4252"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4253"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4254"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4255"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4256"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6578"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6579"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6580"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6582"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6583"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6584"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_6586"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6589"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6590"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6591"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_6592"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6594"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6595"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6596"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6597"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6598"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6599"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6600"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6601"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6602"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6603"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_6604"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_10642"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_10643"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_10644"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_10677"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10693"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_13516"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_13517"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_13518"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/SLICE_13519"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_2_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1160"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1161"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1162"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1163"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1164"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1165"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1166"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1167"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1168"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1169"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1170"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1171"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1172"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1173"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1174"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1175"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_1176"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4257"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4258"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4259"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4260"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4261"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4262"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4263"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4264"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6836"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6837"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6838"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6840"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6841"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6842"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_6844"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6847"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6848"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6849"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_6850"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6852"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6853"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6854"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6855"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6856"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6857"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6858"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6859"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6860"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6861"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_6862"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_10651"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_10652"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_10653"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_10680"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10696"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_13520"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_13521"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_13522"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_13523"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/SLICE_13524"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_5_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1177"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1178"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1179"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1180"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1181"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1182"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1183"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1184"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1185"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1186"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1187"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1188"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1189"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1190"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1191"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1192"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_1193"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4265"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4266"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4267"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4268"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4269"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4270"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4271"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4272"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6492"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6493"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6494"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6496"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6497"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6498"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_6500"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6503"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6504"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6505"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_6506"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6508"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6509"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6510"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6511"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6512"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6513"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6514"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6515"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6516"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6517"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_6518"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_10639"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_10640"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_10641"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_10676"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10692"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_13525"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_13526"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_13527"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/SLICE_13528"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_1_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1194"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1195"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1196"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1197"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1198"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1199"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1200"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1201"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1202"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1203"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1204"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1205"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1206"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1207"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1208"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1209"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_1210"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4273"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4274"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4275"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4276"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4277"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4278"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4279"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4280"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6664"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6665"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6666"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6668"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6669"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6670"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_6672"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6675"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6676"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6677"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_6678"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6680"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6681"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6682"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6683"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6684"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6685"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6686"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6687"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6688"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6689"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_6690"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_10645"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_10646"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_10647"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_10678"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10694"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_13529"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_13530"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_13531"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/SLICE_13532"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_3_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/APV_RAW_BUF_group"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1211"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1212"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1213"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1214"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1215"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1216"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1217"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1218"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1219"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1220"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1221"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1222"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1223"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1224"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1225"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1226"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_1227"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_0/SLICE_4281"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4282"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_1/SLICE_4283"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4284"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4285"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/mem_0_2/SLICE_4286"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4287"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_FRAME_STATUS_MEM/SLICE_4288"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6750"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6751"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_ADC_LAST_SYNCER/SLICE_6752"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6754"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6755"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_ADC_START_SYNCER/SLICE_6756"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_APV_LOCKED_SYNC/SLICE_6758"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6761"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6762"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_6763"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_APV_ADCOK_SYNC/SLICE_6764"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6766"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6767"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6768"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6769"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6770"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6771"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6772"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6773"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6774"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6775"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_6776"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_10648"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_10649"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_10650"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_10679"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_TICKMARK_SYNCER/SLICE_10695"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_13533"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_13534"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_13535"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_13536"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/SLICE_13537"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_0_1"
+ COMP "THE_RAW_BUF_STAGE/GEN_ADC0_4_THE_APV_RAW_BUFFER/THE_INPUT_BRAM/input_bram_0_1_0";
+PGROUP "THE_IPU_STAGE/IPU_FIFO_STAGE_group"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2339"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2340"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2341"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2342"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2343"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2344"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2345"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2346"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2347"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2348"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2349"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2350"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2351"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2352"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2353"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2354"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2355"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2356"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2357"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2358"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2359"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2360"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2361"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2362"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2363"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2364"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2365"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2366"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2367"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2368"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2369"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2370"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2371"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2372"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2373"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2374"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2375"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2376"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2377"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2378"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2379"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2380"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_2381"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2382"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2383"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2384"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2385"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2386"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2387"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2388"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2389"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2390"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2391"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2392"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2393"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2394"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2395"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2396"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2397"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2398"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2399"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2400"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2401"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2402"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2403"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2404"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2405"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2406"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2407"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2408"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2409"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2410"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2411"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2412"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2413"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2414"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2415"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2416"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2417"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2418"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2419"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2420"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2421"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2422"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2423"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_2424"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2425"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2426"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2427"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2428"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2429"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2430"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2431"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2432"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2433"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2434"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2435"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2436"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2437"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2438"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2439"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2440"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2441"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2442"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2443"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2444"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2445"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2446"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2447"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2448"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2449"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2450"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2451"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2452"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2453"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2454"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2455"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2456"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2457"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2458"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2459"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2460"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2461"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2462"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2463"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2464"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2465"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2466"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_2467"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2468"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2469"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2470"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2471"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2472"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2473"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2474"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2475"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2476"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2477"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2478"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2479"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2480"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2481"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2482"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2483"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2484"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2485"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2486"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2487"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2488"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2489"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2490"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2491"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2492"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2493"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2494"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2495"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2496"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2497"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2498"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2499"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2500"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2501"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2502"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2503"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2504"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2505"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2506"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2507"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2508"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2509"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_2510"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2511"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2512"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2513"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2514"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2515"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2516"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2517"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2518"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2519"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2520"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2521"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2522"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2523"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2524"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2525"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2526"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2527"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2528"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2529"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2530"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2531"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2532"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2533"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2534"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2535"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2536"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2537"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2538"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2539"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2540"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2541"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2542"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2543"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2544"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2545"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2546"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2547"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2548"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2549"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2550"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2551"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2552"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_2553"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2554"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2555"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2556"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2557"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2558"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2559"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2560"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2561"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2562"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2563"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2564"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2565"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2566"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2567"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2568"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2569"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2570"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2571"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2572"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2573"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2574"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2575"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2576"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2577"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2578"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2579"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2580"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2581"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2582"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2583"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2584"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2585"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2586"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2587"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2588"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2589"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2590"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2591"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2592"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2593"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2594"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2595"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_2596"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2597"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2598"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2599"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2600"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2601"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2602"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2603"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2604"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2605"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2606"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2607"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2608"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2609"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2610"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2611"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2612"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2613"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2614"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2615"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2616"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2617"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2618"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2619"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2620"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2621"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2622"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2623"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2624"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2625"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2626"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2627"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2628"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2629"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2630"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2631"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2632"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2633"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2634"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2635"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2636"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2637"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2638"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_2639"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2640"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2641"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2642"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2643"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2644"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2645"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2646"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2647"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2648"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2649"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2650"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2651"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2652"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2653"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2654"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2655"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2656"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2657"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2658"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2659"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2660"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2661"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2662"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2663"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2664"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2665"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2666"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2667"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2668"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2669"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2670"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2671"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2672"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2673"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2674"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2675"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2676"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2677"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2678"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2679"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2680"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2681"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_2682"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2683"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2684"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2685"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2686"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2687"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2688"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2689"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2690"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2691"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2692"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2693"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2694"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2695"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2696"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2697"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2698"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2699"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2700"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2701"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2702"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2703"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2704"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2705"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2706"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2707"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2708"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2709"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2710"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2711"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2712"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2713"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2714"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2715"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2716"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2717"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2718"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2719"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2720"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2721"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2722"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2723"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2724"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_2725"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2726"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2727"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2728"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2729"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2730"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2731"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2732"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2733"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2734"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2735"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2736"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2737"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2738"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2739"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2740"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2741"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2742"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2743"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2744"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2745"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2746"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2747"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2748"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2749"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2750"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2751"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2752"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2753"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2754"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2755"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2756"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2757"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2758"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2759"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2760"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2761"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2762"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2763"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2764"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2765"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2766"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2767"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_2768"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2769"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2770"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2771"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2772"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2773"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2774"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2775"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2776"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2777"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2778"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2779"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2780"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2781"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2782"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2783"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2784"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2785"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2786"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2787"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2788"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2789"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2790"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2791"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2792"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2793"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2794"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2795"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2796"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2797"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2798"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2799"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2800"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2801"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2802"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2803"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2804"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2805"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2806"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2807"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2808"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2809"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2810"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_2811"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2812"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2813"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2814"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2815"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2816"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2817"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2818"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2819"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2820"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2821"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2822"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2823"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2824"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2825"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2826"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2827"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2828"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2829"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2830"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2831"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2832"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2833"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2834"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2835"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2836"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2837"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2838"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2839"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2840"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2841"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2842"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2843"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2844"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2845"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2846"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2847"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2848"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2849"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2850"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2851"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2852"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2853"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_2854"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2855"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2856"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2857"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2858"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2859"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2860"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2861"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2862"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2863"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2864"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2865"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2866"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2867"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2868"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2869"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2870"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2871"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2872"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2873"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2874"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2875"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2876"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2877"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2878"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2879"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2880"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2881"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2882"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2883"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2884"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2885"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2886"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2887"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2888"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2889"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2890"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2891"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2892"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2893"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2894"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2895"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2896"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_2897"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2898"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2899"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2900"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2901"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2902"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2903"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2904"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2905"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2906"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2907"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2908"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2909"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2910"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2911"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2912"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2913"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2914"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2915"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2916"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2917"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2918"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2919"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2920"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2921"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2922"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2923"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2924"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2925"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2926"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2927"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2928"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2929"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2930"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2931"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2932"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2933"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2934"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2935"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2936"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2937"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2938"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2939"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_2940"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2941"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2942"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2943"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2944"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2945"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2946"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2947"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2948"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2949"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2950"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2951"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2952"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2953"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2954"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2955"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2956"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2957"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2958"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2959"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2960"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2961"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2962"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2963"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2964"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2965"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2966"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2967"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2968"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2969"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2970"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2971"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2972"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2973"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2974"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2975"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2976"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2977"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2978"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2979"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2980"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2981"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2982"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_2983"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2984"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2985"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2986"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2987"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2988"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2989"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2990"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2991"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2992"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2993"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2994"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2995"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2996"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2997"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2998"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_2999"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3000"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3001"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3002"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3003"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3004"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3005"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3006"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3007"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3008"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3009"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3010"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3011"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3012"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3013"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3014"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3015"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3016"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3017"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3018"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3019"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3020"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3021"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3022"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3023"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3024"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3025"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_3026"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3027"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3028"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3029"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3030"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3031"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3032"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3033"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3034"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3035"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3036"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3037"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3038"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3039"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3040"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3041"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3042"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3043"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3044"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3045"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3046"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3047"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3048"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3049"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3050"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3051"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3052"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3053"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3054"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3055"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3056"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3057"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3058"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3059"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3060"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3061"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3062"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_3063"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3064"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3065"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3066"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3067"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3068"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3069"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3070"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3071"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3072"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3073"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3074"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3075"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3076"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3077"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3078"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3079"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3080"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3081"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3082"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3083"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3084"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3085"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3086"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3087"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3088"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3089"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3090"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3091"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3092"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3093"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3094"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3095"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3096"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3097"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3098"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3099"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_3100"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3101"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3102"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3103"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3104"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3105"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3106"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3107"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3108"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3109"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3110"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3111"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3112"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3113"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3114"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3115"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3116"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3117"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3118"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3119"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3120"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3121"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3122"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3123"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3124"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3125"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3126"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3127"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3128"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3129"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3130"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3131"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3132"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3133"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3134"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3135"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3136"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_3137"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3138"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3139"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3140"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3141"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3142"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3143"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3144"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3145"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3146"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3147"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3148"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3149"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3150"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3151"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3152"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3153"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3154"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3155"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3156"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3157"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3158"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3159"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3160"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3161"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3162"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3163"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3164"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3165"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3166"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3167"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3168"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3169"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3170"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3171"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3172"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3173"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_3174"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3175"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3176"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3177"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3178"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3179"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3180"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3181"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3182"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3183"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3184"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3185"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3186"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3187"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3188"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3189"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3190"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3191"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3192"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3193"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3194"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3195"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3196"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3197"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3198"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3199"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3200"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3201"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3202"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3203"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3204"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3205"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3206"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3207"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3208"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3209"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3210"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_3211"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3212"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3213"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3214"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3215"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3216"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3217"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3218"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3219"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3220"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3221"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3222"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3223"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3224"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3225"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3226"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3227"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3228"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3229"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3230"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3231"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3232"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3233"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3234"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3235"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3236"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3237"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3238"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3239"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3240"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3241"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3242"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3243"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3244"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3245"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3246"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3247"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_3248"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3249"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3250"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3251"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3252"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3253"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3254"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3255"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3256"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3257"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3258"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3259"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3260"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3261"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3262"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3263"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3264"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3265"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3266"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3267"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3268"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3269"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3270"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3271"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3272"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3273"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3274"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3275"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3276"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3277"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3278"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3279"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3280"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3281"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3282"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3283"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3284"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_3285"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3286"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3287"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3288"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3289"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3290"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3291"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3292"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3293"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3294"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3295"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3296"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3297"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3298"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3299"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3300"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3301"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3302"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3303"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3304"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3305"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3306"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3307"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3308"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3309"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3310"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3311"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3312"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3313"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3314"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3315"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3316"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3317"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3318"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3319"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3320"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3321"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_3322"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3323"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3324"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3325"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3326"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3327"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3328"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3329"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3330"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3331"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3332"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3333"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3334"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3335"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3336"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3337"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3338"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3339"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3340"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3341"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3342"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3343"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3344"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3345"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3346"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3347"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3348"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3349"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3350"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3351"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3352"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3353"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3354"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3355"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3356"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3357"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3358"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_3359"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3360"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3361"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3362"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3363"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3364"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3365"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3366"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3367"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3368"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3369"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3370"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3371"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3372"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3373"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3374"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3375"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3376"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3377"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3378"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3379"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3380"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3381"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3382"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3383"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3384"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3385"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3386"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3387"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3388"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3389"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3390"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3391"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3392"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3393"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3394"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3395"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_3396"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3397"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3398"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3399"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3400"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3401"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3402"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3403"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3404"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3405"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3406"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3407"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3408"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3409"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3410"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3411"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3412"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3413"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3414"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3415"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3416"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3417"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3418"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3419"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3420"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3421"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3422"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3423"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3424"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3425"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3426"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3427"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3428"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3429"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3430"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3431"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3432"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_3433"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3434"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3435"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3436"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3437"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3438"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3439"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3440"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3441"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3442"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3443"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3444"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3445"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3446"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3447"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3448"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3449"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3450"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3451"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3452"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3453"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3454"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3455"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3456"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3457"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3458"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3459"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3460"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3461"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3462"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3463"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3464"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3465"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3466"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3467"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3468"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3469"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_3470"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3471"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3472"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3473"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3474"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3475"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3476"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3477"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3478"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3479"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3480"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3481"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3482"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3483"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3484"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3485"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3486"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3487"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3488"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3489"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3490"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3491"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3492"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3493"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3494"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3495"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3496"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3497"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3498"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3499"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3500"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3501"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3502"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3503"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3504"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3505"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3506"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_3507"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3508"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3509"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3510"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3511"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3512"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3513"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3514"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3515"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3516"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3517"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3518"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3519"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3520"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3521"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3522"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3523"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3524"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3525"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3526"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3527"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3528"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3529"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3530"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3531"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3532"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3533"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3534"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3535"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3536"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3537"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3538"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3539"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3540"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3541"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3542"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3543"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_3544"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3545"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3546"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3547"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3548"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3549"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3550"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3551"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3552"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3553"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3554"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3555"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3556"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3557"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3558"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3559"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3560"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3561"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3562"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3563"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3564"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3565"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3566"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3567"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3568"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3569"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3570"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3571"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3572"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3573"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3574"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3575"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3576"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3577"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3578"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3579"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3580"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_3581"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3582"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3583"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3584"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3585"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3586"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3587"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3588"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3589"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3590"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3591"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3592"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3593"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3594"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3595"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3596"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3597"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3598"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3599"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3600"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3601"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3602"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3603"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3604"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3605"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3606"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3607"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3608"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3609"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3610"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3611"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3612"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3613"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3614"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3615"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3616"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3617"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_3618"
+ COMP "THE_IPU_STAGE/SLICE_3619"
+ COMP "THE_IPU_STAGE/SLICE_3620"
+ COMP "THE_IPU_STAGE/SLICE_3621"
+ COMP "THE_IPU_STAGE/SLICE_3622"
+ COMP "THE_IPU_STAGE/SLICE_3623"
+ COMP "THE_IPU_STAGE/SLICE_3624"
+ COMP "THE_IPU_STAGE/SLICE_3625"
+ COMP "THE_IPU_STAGE/SLICE_3626"
+ COMP "THE_IPU_STAGE/SLICE_3627"
+ COMP "THE_IPU_STAGE/SLICE_3628"
+ COMP "THE_IPU_STAGE/SLICE_3629"
+ COMP "THE_IPU_STAGE/SLICE_3630"
+ COMP "THE_IPU_STAGE/SLICE_3631"
+ COMP "THE_IPU_STAGE/SLICE_3632"
+ COMP "THE_IPU_STAGE/SLICE_3633"
+ COMP "THE_IPU_STAGE/SLICE_3634"
+ COMP "THE_IPU_STAGE/SLICE_3635"
+ COMP "THE_IPU_STAGE/SLICE_3636"
+ COMP "THE_IPU_STAGE/SLICE_3637"
+ COMP "THE_IPU_STAGE/SLICE_3638"
+ COMP "THE_IPU_STAGE/SLICE_3639"
+ COMP "THE_IPU_STAGE/SLICE_3640"
+ COMP "THE_IPU_STAGE/SLICE_3641"
+ COMP "THE_IPU_STAGE/SLICE_3642"
+ COMP "THE_IPU_STAGE/SLICE_3643"
+ COMP "THE_IPU_STAGE/SLICE_3644"
+ COMP "THE_IPU_STAGE/SLICE_3645"
+ COMP "THE_IPU_STAGE/SLICE_3646"
+ COMP "THE_IPU_STAGE/SLICE_3647"
+ COMP "THE_IPU_STAGE/SLICE_3648"
+ COMP "THE_IPU_STAGE/SLICE_3649"
+ COMP "THE_IPU_STAGE/SLICE_3650"
+ COMP "THE_IPU_STAGE/SLICE_3651"
+ COMP "THE_IPU_STAGE/SLICE_3652"
+ COMP "THE_IPU_STAGE/SLICE_3653"
+ COMP "THE_IPU_STAGE/SLICE_3654"
+ COMP "THE_IPU_STAGE/SLICE_3655"
+ COMP "THE_IPU_STAGE/SLICE_3656"
+ COMP "THE_IPU_STAGE/SLICE_3657"
+ COMP "THE_IPU_STAGE/SLICE_3658"
+ COMP "THE_IPU_STAGE/SLICE_3659"
+ COMP "THE_IPU_STAGE/SLICE_3660"
+ COMP "THE_IPU_STAGE/SLICE_3661"
+ COMP "THE_IPU_STAGE/SLICE_3662"
+ COMP "THE_IPU_STAGE/SLICE_3663"
+ COMP "THE_IPU_STAGE/SLICE_3664"
+ COMP "THE_IPU_STAGE/SLICE_3665"
+ COMP "THE_IPU_STAGE/SLICE_3666"
+ COMP "THE_IPU_STAGE/SLICE_3667"
+ COMP "THE_IPU_STAGE/SLICE_3668"
+ COMP "THE_IPU_STAGE/SLICE_3669"
+ COMP "THE_IPU_STAGE/SLICE_3670"
+ COMP "THE_IPU_STAGE/SLICE_3671"
+ COMP "THE_IPU_STAGE/SLICE_3672"
+ COMP "THE_IPU_STAGE/SLICE_3673"
+ COMP "THE_IPU_STAGE/SLICE_3674"
+ COMP "THE_IPU_STAGE/SLICE_3675"
+ COMP "THE_IPU_STAGE/SLICE_3676"
+ COMP "THE_IPU_STAGE/SLICE_3677"
+ COMP "THE_IPU_STAGE/SLICE_3678"
+ COMP "THE_IPU_STAGE/SLICE_3679"
+ COMP "THE_IPU_STAGE/SLICE_3680"
+ COMP "THE_IPU_STAGE/SLICE_3681"
+ COMP "THE_IPU_STAGE/SLICE_3682"
+ COMP "THE_IPU_STAGE/SLICE_3683"
+ COMP "THE_IPU_STAGE/SLICE_3684"
+ COMP "THE_IPU_STAGE/SLICE_3685"
+ COMP "THE_IPU_STAGE/SLICE_3686"
+ COMP "THE_IPU_STAGE/SLICE_3687"
+ COMP "THE_IPU_STAGE/SLICE_3688"
+ COMP "THE_IPU_STAGE/SLICE_3689"
+ COMP "THE_IPU_STAGE/SLICE_3690"
+ COMP "THE_IPU_STAGE/SLICE_3691"
+ COMP "THE_IPU_STAGE/SLICE_3692"
+ COMP "THE_IPU_STAGE/SLICE_3693"
+ COMP "THE_IPU_STAGE/SLICE_3694"
+ COMP "THE_IPU_STAGE/SLICE_3695"
+ COMP "THE_IPU_STAGE/SLICE_3696"
+ COMP "THE_IPU_STAGE/SLICE_3697"
+ COMP "THE_IPU_STAGE/SLICE_3698"
+ COMP "THE_IPU_STAGE/SLICE_3699"
+ COMP "THE_IPU_STAGE/SLICE_3700"
+ COMP "THE_IPU_STAGE/SLICE_3701"
+ COMP "THE_IPU_STAGE/SLICE_3702"
+ COMP "THE_IPU_STAGE/SLICE_3703"
+ COMP "THE_IPU_STAGE/SLICE_3704"
+ COMP "THE_IPU_STAGE/SLICE_3705"
+ COMP "THE_IPU_STAGE/SLICE_3706"
+ COMP "THE_IPU_STAGE/SLICE_3707"
+ COMP "THE_IPU_STAGE/SLICE_3708"
+ COMP "THE_IPU_STAGE/SLICE_3709"
+ COMP "THE_IPU_STAGE/SLICE_3710"
+ COMP "THE_IPU_STAGE/SLICE_3711"
+ COMP "THE_IPU_STAGE/SLICE_3712"
+ COMP "THE_IPU_STAGE/SLICE_3713"
+ COMP "THE_IPU_STAGE/SLICE_3714"
+ COMP "THE_IPU_STAGE/SLICE_3715"
+ COMP "THE_IPU_STAGE/SLICE_3716"
+ COMP "THE_IPU_STAGE/SLICE_3717"
+ COMP "THE_IPU_STAGE/SLICE_3718"
+ COMP "THE_IPU_STAGE/SLICE_3719"
+ COMP "THE_IPU_STAGE/SLICE_3720"
+ COMP "THE_IPU_STAGE/SLICE_3721"
+ COMP "THE_IPU_STAGE/SLICE_3722"
+ COMP "THE_IPU_STAGE/SLICE_3723"
+ COMP "THE_IPU_STAGE/SLICE_3724"
+ COMP "THE_IPU_STAGE/SLICE_3725"
+ COMP "THE_IPU_STAGE/SLICE_3726"
+ COMP "THE_IPU_STAGE/SLICE_3727"
+ COMP "THE_IPU_STAGE/SLICE_3728"
+ COMP "THE_IPU_STAGE/SLICE_3729"
+ COMP "THE_IPU_STAGE/SLICE_3730"
+ COMP "THE_IPU_STAGE/SLICE_3731"
+ COMP "THE_IPU_STAGE/SLICE_3732"
+ COMP "THE_IPU_STAGE/SLICE_3733"
+ COMP "THE_IPU_STAGE/SLICE_3734"
+ COMP "THE_IPU_STAGE/SLICE_3735"
+ COMP "THE_IPU_STAGE/SLICE_3736"
+ COMP "THE_IPU_STAGE/SLICE_3737"
+ COMP "THE_IPU_STAGE/SLICE_3738"
+ COMP "THE_IPU_STAGE/SLICE_3739"
+ COMP "THE_IPU_STAGE/SLICE_3740"
+ COMP "THE_IPU_STAGE/SLICE_3741"
+ COMP "THE_IPU_STAGE/SLICE_3742"
+ COMP "THE_IPU_STAGE/SLICE_3743"
+ COMP "THE_IPU_STAGE/SLICE_3744"
+ COMP "THE_IPU_STAGE/SLICE_3745"
+ COMP "THE_IPU_STAGE/SLICE_3746"
+ COMP "THE_IPU_STAGE/SLICE_3747"
+ COMP "THE_IPU_STAGE/SLICE_3748"
+ COMP "THE_IPU_STAGE/SLICE_3749"
+ COMP "THE_IPU_STAGE/SLICE_3750"
+ COMP "THE_IPU_STAGE/SLICE_3751"
+ COMP "THE_IPU_STAGE/SLICE_3752"
+ COMP "THE_IPU_STAGE/SLICE_3753"
+ COMP "THE_IPU_STAGE/SLICE_3754"
+ COMP "THE_IPU_STAGE/SLICE_3755"
+ COMP "THE_IPU_STAGE/SLICE_3756"
+ COMP "THE_IPU_STAGE/SLICE_3757"
+ COMP "THE_IPU_STAGE/SLICE_3758"
+ COMP "THE_IPU_STAGE/SLICE_3759"
+ COMP "THE_IPU_STAGE/SLICE_3760"
+ COMP "THE_IPU_STAGE/SLICE_3761"
+ COMP "THE_IPU_STAGE/SLICE_3762"
+ COMP "THE_IPU_STAGE/SLICE_3763"
+ COMP "THE_IPU_STAGE/SLICE_3764"
+ COMP "THE_IPU_STAGE/SLICE_3765"
+ COMP "THE_IPU_STAGE/SLICE_3766"
+ COMP "THE_IPU_STAGE/SLICE_3767"
+ COMP "THE_IPU_STAGE/SLICE_3768"
+ COMP "THE_IPU_STAGE/SLICE_3769"
+ COMP "THE_IPU_STAGE/SLICE_3770"
+ COMP "THE_IPU_STAGE/SLICE_3771"
+ COMP "THE_IPU_STAGE/SLICE_3772"
+ COMP "THE_IPU_STAGE/SLICE_3773"
+ COMP "THE_IPU_STAGE/SLICE_3774"
+ COMP "THE_IPU_STAGE/SLICE_3775"
+ COMP "THE_IPU_STAGE/SLICE_3776"
+ COMP "THE_IPU_STAGE/SLICE_3777"
+ COMP "THE_IPU_STAGE/SLICE_3778"
+ COMP "THE_IPU_STAGE/SLICE_3779"
+ COMP "THE_IPU_STAGE/SLICE_3780"
+ COMP "THE_IPU_STAGE/SLICE_3781"
+ COMP "THE_IPU_STAGE/SLICE_3782"
+ COMP "THE_IPU_STAGE/SLICE_3783"
+ COMP "THE_IPU_STAGE/SLICE_3784"
+ COMP "THE_IPU_STAGE/SLICE_3785"
+ COMP "THE_IPU_STAGE/SLICE_3786"
+ COMP "THE_IPU_STAGE/SLICE_3787"
+ COMP "THE_IPU_STAGE/SLICE_3788"
+ COMP "THE_IPU_STAGE/SLICE_3789"
+ COMP "THE_IPU_STAGE/SLICE_3790"
+ COMP "THE_IPU_STAGE/SLICE_3791"
+ COMP "THE_IPU_STAGE/SLICE_3792"
+ COMP "THE_IPU_STAGE/SLICE_3793"
+ COMP "THE_IPU_STAGE/SLICE_3794"
+ COMP "THE_IPU_STAGE/SLICE_3795"
+ COMP "THE_IPU_STAGE/SLICE_3796"
+ COMP "THE_IPU_STAGE/SLICE_3797"
+ COMP "THE_IPU_STAGE/SLICE_3798"
+ COMP "THE_IPU_STAGE/SLICE_3799"
+ COMP "THE_IPU_STAGE/SLICE_3800"
+ COMP "THE_IPU_STAGE/SLICE_3801"
+ COMP "THE_IPU_STAGE/SLICE_3802"
+ COMP "THE_IPU_STAGE/SLICE_3803"
+ COMP "THE_IPU_STAGE/SLICE_3804"
+ COMP "THE_IPU_STAGE/SLICE_3805"
+ COMP "THE_IPU_STAGE/SLICE_3806"
+ COMP "THE_IPU_STAGE/SLICE_3807"
+ COMP "THE_IPU_STAGE/SLICE_3808"
+ COMP "THE_IPU_STAGE/SLICE_3809"
+ COMP "THE_IPU_STAGE/SLICE_3810"
+ COMP "THE_IPU_STAGE/SLICE_3811"
+ COMP "THE_IPU_STAGE/SLICE_3812"
+ COMP "THE_IPU_STAGE/SLICE_3813"
+ COMP "THE_IPU_STAGE/SLICE_3814"
+ COMP "THE_IPU_STAGE/SLICE_3815"
+ COMP "THE_IPU_STAGE/SLICE_3816"
+ COMP "THE_IPU_STAGE/SLICE_3817"
+ COMP "THE_IPU_STAGE/SLICE_3818"
+ COMP "THE_IPU_STAGE/SLICE_3819"
+ COMP "THE_IPU_STAGE/SLICE_3820"
+ COMP "THE_IPU_STAGE/SLICE_3821"
+ COMP "THE_IPU_STAGE/SLICE_3822"
+ COMP "THE_IPU_STAGE/SLICE_3823"
+ COMP "THE_IPU_STAGE/SLICE_3824"
+ COMP "THE_IPU_STAGE/SLICE_3825"
+ COMP "THE_IPU_STAGE/SLICE_3826"
+ COMP "THE_IPU_STAGE/SLICE_3827"
+ COMP "THE_IPU_STAGE/SLICE_3828"
+ COMP "THE_IPU_STAGE/SLICE_3829"
+ COMP "THE_IPU_STAGE/SLICE_3830"
+ COMP "THE_IPU_STAGE/SLICE_3831"
+ COMP "THE_IPU_STAGE/SLICE_3832"
+ COMP "THE_IPU_STAGE/SLICE_3833"
+ COMP "THE_IPU_STAGE/SLICE_3834"
+ COMP "THE_IPU_STAGE/SLICE_3835"
+ COMP "THE_IPU_STAGE/SLICE_3836"
+ COMP "THE_IPU_STAGE/SLICE_3837"
+ COMP "THE_IPU_STAGE/SLICE_3838"
+ COMP "THE_IPU_STAGE/SLICE_3839"
+ COMP "THE_IPU_STAGE/SLICE_3840"
+ COMP "THE_IPU_STAGE/SLICE_3841"
+ COMP "THE_IPU_STAGE/SLICE_3842"
+ COMP "THE_IPU_STAGE/SLICE_3843"
+ COMP "THE_IPU_STAGE/SLICE_3844"
+ COMP "THE_IPU_STAGE/SLICE_3845"
+ COMP "THE_IPU_STAGE/SLICE_3846"
+ COMP "THE_IPU_STAGE/SLICE_3847"
+ COMP "THE_IPU_STAGE/SLICE_3848"
+ COMP "THE_IPU_STAGE/SLICE_3849"
+ COMP "THE_IPU_STAGE/SLICE_3850"
+ COMP "THE_IPU_STAGE/SLICE_3851"
+ COMP "THE_IPU_STAGE/SLICE_3852"
+ COMP "THE_IPU_STAGE/SLICE_3853"
+ COMP "THE_IPU_STAGE/SLICE_3854"
+ COMP "THE_IPU_STAGE/SLICE_3855"
+ COMP "THE_IPU_STAGE/SLICE_3856"
+ COMP "THE_IPU_STAGE/SLICE_3857"
+ COMP "THE_IPU_STAGE/SLICE_3858"
+ COMP "THE_IPU_STAGE/SLICE_3859"
+ COMP "THE_IPU_STAGE/SLICE_3860"
+ COMP "THE_IPU_STAGE/SLICE_3861"
+ COMP "THE_IPU_STAGE/SLICE_3862"
+ COMP "THE_IPU_STAGE/SLICE_3863"
+ COMP "THE_IPU_STAGE/SLICE_3864"
+ COMP "THE_IPU_STAGE/SLICE_3865"
+ COMP "THE_IPU_STAGE/SLICE_3866"
+ COMP "THE_IPU_STAGE/SLICE_3867"
+ COMP "THE_IPU_STAGE/SLICE_3868"
+ COMP "THE_IPU_STAGE/SLICE_3869"
+ COMP "THE_IPU_STAGE/SLICE_3870"
+ COMP "THE_IPU_STAGE/SLICE_3871"
+ COMP "THE_IPU_STAGE/SLICE_3872"
+ COMP "THE_IPU_STAGE/SLICE_3873"
+ COMP "THE_IPU_STAGE/SLICE_3874"
+ COMP "THE_IPU_STAGE/SLICE_3875"
+ COMP "THE_IPU_STAGE/SLICE_3876"
+ COMP "THE_IPU_STAGE/SLICE_3877"
+ COMP "THE_IPU_STAGE/SLICE_3878"
+ COMP "THE_IPU_STAGE/SLICE_3879"
+ COMP "THE_IPU_STAGE/SLICE_3880"
+ COMP "THE_IPU_STAGE/SLICE_3881"
+ COMP "THE_IPU_STAGE/SLICE_3882"
+ COMP "THE_IPU_STAGE/SLICE_3883"
+ COMP "THE_IPU_STAGE/SLICE_3884"
+ COMP "THE_IPU_STAGE/SLICE_3885"
+ COMP "THE_IPU_STAGE/SLICE_3886"
+ COMP "THE_IPU_STAGE/SLICE_3887"
+ COMP "THE_IPU_STAGE/SLICE_3888"
+ COMP "THE_IPU_STAGE/SLICE_3889"
+ COMP "THE_IPU_STAGE/SLICE_3890"
+ COMP "THE_IPU_STAGE/SLICE_3891"
+ COMP "THE_IPU_STAGE/SLICE_3892"
+ COMP "THE_IPU_STAGE/SLICE_3893"
+ COMP "THE_IPU_STAGE/SLICE_3894"
+ COMP "THE_IPU_STAGE/SLICE_3895"
+ COMP "THE_IPU_STAGE/SLICE_3896"
+ COMP "THE_IPU_STAGE/SLICE_3897"
+ COMP "THE_IPU_STAGE/SLICE_3898"
+ COMP "THE_IPU_STAGE/SLICE_3899"
+ COMP "THE_IPU_STAGE/SLICE_3900"
+ COMP "THE_IPU_STAGE/SLICE_3901"
+ COMP "THE_IPU_STAGE/SLICE_3902"
+ COMP "THE_IPU_STAGE/SLICE_3903"
+ COMP "THE_IPU_STAGE/SLICE_3904"
+ COMP "THE_IPU_STAGE/SLICE_3905"
+ COMP "THE_IPU_STAGE/SLICE_3906"
+ COMP "THE_IPU_STAGE/SLICE_3907"
+ COMP "THE_IPU_STAGE/SLICE_3908"
+ COMP "THE_IPU_STAGE/SLICE_3909"
+ COMP "THE_IPU_STAGE/SLICE_3910"
+ COMP "THE_IPU_STAGE/SLICE_3911"
+ COMP "THE_IPU_STAGE/SLICE_3912"
+ COMP "THE_IPU_STAGE/SLICE_3913"
+ COMP "THE_IPU_STAGE/SLICE_3914"
+ COMP "THE_IPU_STAGE/SLICE_3915"
+ COMP "THE_IPU_STAGE/SLICE_3916"
+ COMP "THE_IPU_STAGE/SLICE_3917"
+ COMP "THE_IPU_STAGE/SLICE_3918"
+ COMP "THE_IPU_STAGE/SLICE_3919"
+ COMP "THE_IPU_STAGE/SLICE_3920"
+ COMP "THE_IPU_STAGE/SLICE_3921"
+ COMP "THE_IPU_STAGE/SLICE_3922"
+ COMP "THE_IPU_STAGE/SLICE_3923"
+ COMP "THE_IPU_STAGE/SLICE_3924"
+ COMP "THE_IPU_STAGE/SLICE_3925"
+ COMP "THE_IPU_STAGE/SLICE_3926"
+ COMP "THE_IPU_STAGE/SLICE_3927"
+ COMP "THE_IPU_STAGE/SLICE_3928"
+ COMP "THE_IPU_STAGE/SLICE_3929"
+ COMP "THE_IPU_STAGE/SLICE_3930"
+ COMP "THE_IPU_STAGE/SLICE_3931"
+ COMP "THE_IPU_STAGE/SLICE_3932"
+ COMP "THE_IPU_STAGE/SLICE_3933"
+ COMP "THE_IPU_STAGE/SLICE_3934"
+ COMP "THE_IPU_STAGE/SLICE_3935"
+ COMP "THE_IPU_STAGE/SLICE_3936"
+ COMP "THE_IPU_STAGE/SLICE_3937"
+ COMP "THE_IPU_STAGE/SLICE_3938"
+ COMP "THE_IPU_STAGE/SLICE_3939"
+ COMP "THE_IPU_STAGE/SLICE_3940"
+ COMP "THE_IPU_STAGE/SLICE_3941"
+ COMP "THE_IPU_STAGE/SLICE_3942"
+ COMP "THE_IPU_STAGE/SLICE_3943"
+ COMP "THE_IPU_STAGE/SLICE_3944"
+ COMP "THE_IPU_STAGE/SLICE_3945"
+ COMP "THE_IPU_STAGE/SLICE_3946"
+ COMP "THE_IPU_STAGE/SLICE_3947"
+ COMP "THE_IPU_STAGE/SLICE_3948"
+ COMP "THE_IPU_STAGE/SLICE_3949"
+ COMP "THE_IPU_STAGE/SLICE_3950"
+ COMP "THE_IPU_STAGE/SLICE_3951"
+ COMP "THE_IPU_STAGE/SLICE_3952"
+ COMP "THE_IPU_STAGE/SLICE_5111"
+ COMP "THE_IPU_STAGE/SLICE_5112"
+ COMP "THE_IPU_STAGE/SLICE_5113"
+ COMP "THE_IPU_STAGE/SLICE_5114"
+ COMP "THE_IPU_STAGE/SLICE_5115"
+ COMP "THE_IPU_STAGE/SLICE_5116"
+ COMP "THE_IPU_STAGE/SLICE_5117"
+ COMP "THE_IPU_STAGE/SLICE_5118"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_5119"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_5120"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_5121"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_5122"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_5123"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_5124"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_5125"
+ COMP "THE_IPU_STAGE/SLICE_5126"
+ COMP "THE_IPU_STAGE/SLICE_5127"
+ COMP "THE_IPU_STAGE/SLICE_5128"
+ COMP "THE_IPU_STAGE/SLICE_5129"
+ COMP "THE_IPU_STAGE/SLICE_5130"
+ COMP "THE_IPU_STAGE/SLICE_5131"
+ COMP "THE_IPU_STAGE/SLICE_5132"
+ COMP "THE_IPU_STAGE/SLICE_5133"
+ COMP "THE_IPU_STAGE/SLICE_5134"
+ COMP "THE_IPU_STAGE/SLICE_5135"
+ COMP "THE_IPU_STAGE/SLICE_5136"
+ COMP "THE_IPU_STAGE/SLICE_5137"
+ COMP "THE_IPU_STAGE/SLICE_5138"
+ COMP "THE_IPU_STAGE/SLICE_5139"
+ COMP "THE_IPU_STAGE/SLICE_5140"
+ COMP "THE_IPU_STAGE/SLICE_5141"
+ COMP "THE_IPU_STAGE/SLICE_5142"
+ COMP "THE_IPU_STAGE/SLICE_5143"
+ COMP "THE_IPU_STAGE/SLICE_5144"
+ COMP "THE_IPU_STAGE/SLICE_5145"
+ COMP "THE_IPU_STAGE/SLICE_5146"
+ COMP "THE_IPU_STAGE/SLICE_5147"
+ COMP "THE_IPU_STAGE/SLICE_5148"
+ COMP "THE_IPU_STAGE/SLICE_5149"
+ COMP "THE_IPU_STAGE/SLICE_5150"
+ COMP "THE_IPU_STAGE/SLICE_5151"
+ COMP "THE_IPU_STAGE/SLICE_5152"
+ COMP "THE_IPU_STAGE/SLICE_5153"
+ COMP "THE_IPU_STAGE/SLICE_5154"
+ COMP "THE_IPU_STAGE/SLICE_5155"
+ COMP "THE_IPU_STAGE/SLICE_5156"
+ COMP "THE_IPU_STAGE/SLICE_5157"
+ COMP "THE_IPU_STAGE/SLICE_5158"
+ COMP "THE_IPU_STAGE/SLICE_5159"
+ COMP "THE_IPU_STAGE/SLICE_5160"
+ COMP "THE_IPU_STAGE/SLICE_5161"
+ COMP "THE_IPU_STAGE/SLICE_5162"
+ COMP "THE_IPU_STAGE/SLICE_5164"
+ COMP "THE_IPU_STAGE/SLICE_5165"
+ COMP "THE_IPU_STAGE/SLICE_5167"
+ COMP "THE_IPU_STAGE/SLICE_5168"
+ COMP "THE_IPU_STAGE/SLICE_5169"
+ COMP "THE_IPU_STAGE/SLICE_5170"
+ COMP "THE_IPU_STAGE/SLICE_5171"
+ COMP "THE_IPU_STAGE/SLICE_5172"
+ COMP "THE_IPU_STAGE/SLICE_5173"
+ COMP "THE_IPU_STAGE/SLICE_5174"
+ COMP "THE_IPU_STAGE/SLICE_5175"
+ COMP "THE_IPU_STAGE/SLICE_5176"
+ COMP "THE_IPU_STAGE/SLICE_5177"
+ COMP "THE_IPU_STAGE/SLICE_5178"
+ COMP "THE_IPU_STAGE/SLICE_5180"
+ COMP "THE_IPU_STAGE/SLICE_5181"
+ COMP "THE_IPU_STAGE/SLICE_5182"
+ COMP "THE_IPU_STAGE/SLICE_5183"
+ COMP "THE_IPU_STAGE/SLICE_5184"
+ COMP "THE_IPU_STAGE/SLICE_5185"
+ COMP "THE_IPU_STAGE/SLICE_5186"
+ COMP "THE_IPU_STAGE/SLICE_5187"
+ COMP "THE_IPU_STAGE/SLICE_5188"
+ COMP "THE_IPU_STAGE/SLICE_5189"
+ COMP "THE_IPU_STAGE/SLICE_10760"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_10977"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_10978"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_10979"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_10980"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_10981"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_10982"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_10983"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_10984"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_10985"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_10986"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_10987"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_10988"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_10989"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_10990"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_10991"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_10992"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_10993"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_10994"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_10995"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_10996"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_10997"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_10998"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_10999"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_11000"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_11001"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_11002"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_11003"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_11004"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_11005"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_11006"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_11007"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_11008"
+ COMP "THE_IPU_STAGE/SLICE_11018"
+ COMP "THE_IPU_STAGE/SLICE_11019"
+ COMP "THE_IPU_STAGE/SLICE_11020"
+ COMP "THE_IPU_STAGE/SLICE_11021"
+ COMP "THE_IPU_STAGE/SLICE_11022"
+ COMP "THE_IPU_STAGE/SLICE_11023"
+ COMP "THE_IPU_STAGE/SLICE_11024"
+ COMP "THE_IPU_STAGE/SLICE_11025"
+ COMP "THE_IPU_STAGE/SLICE_11026"
+ COMP "THE_IPU_STAGE/SLICE_11027"
+ COMP "THE_IPU_STAGE/SLICE_11028"
+ COMP "THE_IPU_STAGE/SLICE_11029"
+ COMP "THE_IPU_STAGE/SLICE_11030"
+ COMP "THE_IPU_STAGE/SLICE_11031"
+ COMP "THE_IPU_STAGE/SLICE_11032"
+ COMP "THE_IPU_STAGE/SLICE_11033"
+ COMP "THE_IPU_STAGE/SLICE_11034"
+ COMP "THE_IPU_STAGE/SLICE_11035"
+ COMP "THE_IPU_STAGE/SLICE_11036"
+ COMP "THE_IPU_STAGE/SLICE_11037"
+ COMP "THE_IPU_STAGE/SLICE_11038"
+ COMP "THE_IPU_STAGE/SLICE_11039"
+ COMP "THE_IPU_STAGE/SLICE_11040"
+ COMP "THE_IPU_STAGE/SLICE_11041"
+ COMP "THE_IPU_STAGE/SLICE_11042"
+ COMP "THE_IPU_STAGE/SLICE_11051"
+ COMP "THE_IPU_STAGE/SLICE_11054"
+ COMP "THE_IPU_STAGE/SLICE_11055"
+ COMP "THE_IPU_STAGE/SLICE_11056"
+ COMP "THE_IPU_STAGE/SLICE_11057"
+ COMP "THE_IPU_STAGE/SLICE_11058"
+ COMP "THE_IPU_STAGE/SLICE_11059"
+ COMP "THE_IPU_STAGE/SLICE_11060"
+ COMP "THE_IPU_STAGE/SLICE_11061"
+ COMP "THE_IPU_STAGE/next_fifo_last_m5/SLICE_11821"
+ COMP "THE_IPU_STAGE/next_fifo_last_m8/SLICE_11822"
+ COMP "THE_IPU_STAGE/next_fifo_last_m11/SLICE_11823"
+ COMP "THE_IPU_STAGE/next_fifo_last_m14/SLICE_11824"
+ COMP "THE_IPU_STAGE/next_fifo_sel_m13_0/SLICE_11825"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_11832"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_11833"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_11834"
+ COMP "THE_IPU_STAGE/SLICE_11835"
+ COMP "THE_IPU_STAGE/SLICE_11882"
+ COMP "THE_IPU_STAGE/SLICE_11883"
+ COMP "THE_IPU_STAGE/SLICE_11884"
+ COMP "THE_IPU_STAGE/SLICE_11885"
+ COMP "THE_IPU_STAGE/SLICE_11886"
+ COMP "THE_IPU_STAGE/SLICE_11887"
+ COMP "THE_IPU_STAGE/SLICE_11888"
+ COMP "THE_IPU_STAGE/SLICE_11889"
+ COMP "THE_IPU_STAGE/SLICE_11890"
+ COMP "THE_IPU_STAGE/SLICE_11891"
+ COMP "THE_IPU_STAGE/SLICE_11892"
+ COMP "THE_IPU_STAGE/SLICE_11893"
+ COMP "THE_IPU_STAGE/SLICE_11894"
+ COMP "THE_IPU_STAGE/SLICE_11895"
+ COMP "THE_IPU_STAGE/SLICE_11896"
+ COMP "THE_IPU_STAGE/SLICE_11897"
+ COMP "THE_IPU_STAGE/SLICE_11898"
+ COMP "THE_IPU_STAGE/SLICE_11899"
+ COMP "THE_IPU_STAGE/SLICE_11900"
+ COMP "THE_IPU_STAGE/SLICE_11901"
+ COMP "THE_IPU_STAGE/SLICE_11902"
+ COMP "THE_IPU_STAGE/SLICE_11903"
+ COMP "THE_IPU_STAGE/SLICE_11904"
+ COMP "THE_IPU_STAGE/SLICE_11905"
+ COMP "THE_IPU_STAGE/SLICE_11906"
+ COMP "THE_IPU_STAGE/SLICE_11907"
+ COMP "THE_IPU_STAGE/SLICE_11908"
+ COMP "THE_IPU_STAGE/SLICE_11909"
+ COMP "THE_IPU_STAGE/SLICE_11910"
+ COMP "THE_IPU_STAGE/SLICE_11911"
+ COMP "THE_IPU_STAGE/SLICE_11912"
+ COMP "THE_IPU_STAGE/SLICE_11913"
+ COMP "THE_IPU_STAGE/SLICE_11914"
+ COMP "THE_IPU_STAGE/SLICE_11915"
+ COMP "THE_IPU_STAGE/SLICE_11916"
+ COMP "THE_IPU_STAGE/SLICE_11917"
+ COMP "THE_IPU_STAGE/SLICE_11918"
+ COMP "THE_IPU_STAGE/SLICE_11919"
+ COMP "THE_IPU_STAGE/SLICE_11920"
+ COMP "THE_IPU_STAGE/SLICE_11921"
+ COMP "THE_IPU_STAGE/SLICE_11922"
+ COMP "THE_IPU_STAGE/SLICE_11923"
+ COMP "THE_IPU_STAGE/SLICE_11924"
+ COMP "THE_IPU_STAGE/SLICE_11925"
+ COMP "THE_IPU_STAGE/SLICE_11926"
+ COMP "THE_IPU_STAGE/SLICE_11927"
+ COMP "THE_IPU_STAGE/SLICE_11928"
+ COMP "THE_IPU_STAGE/SLICE_11929"
+ COMP "THE_IPU_STAGE/SLICE_11930"
+ COMP "THE_IPU_STAGE/SLICE_11931"
+ COMP "THE_IPU_STAGE/SLICE_11932"
+ COMP "THE_IPU_STAGE/SLICE_11933"
+ COMP "THE_IPU_STAGE/SLICE_11934"
+ COMP "THE_IPU_STAGE/SLICE_11935"
+ COMP "THE_IPU_STAGE/SLICE_11936"
+ COMP "THE_IPU_STAGE/SLICE_11937"
+ COMP "THE_IPU_STAGE/SLICE_11938"
+ COMP "THE_IPU_STAGE/SLICE_11939"
+ COMP "THE_IPU_STAGE/SLICE_11940"
+ COMP "THE_IPU_STAGE/SLICE_11941"
+ COMP "THE_IPU_STAGE/SLICE_11942"
+ COMP "THE_IPU_STAGE/SLICE_11943"
+ COMP "THE_IPU_STAGE/SLICE_11944"
+ COMP "THE_IPU_STAGE/SLICE_11945"
+ COMP "THE_IPU_STAGE/SLICE_11946"
+ COMP "THE_IPU_STAGE/SLICE_11947"
+ COMP "THE_IPU_STAGE/SLICE_11948"
+ COMP "THE_IPU_STAGE/SLICE_11949"
+ COMP "THE_IPU_STAGE/SLICE_11950"
+ COMP "THE_IPU_STAGE/SLICE_11951"
+ COMP "THE_IPU_STAGE/SLICE_11952"
+ COMP "THE_IPU_STAGE/SLICE_11953"
+ COMP "THE_IPU_STAGE/SLICE_11954"
+ COMP "THE_IPU_STAGE/SLICE_11955"
+ COMP "THE_IPU_STAGE/SLICE_11956"
+ COMP "THE_IPU_STAGE/SLICE_11957"
+ COMP "THE_IPU_STAGE/SLICE_11958"
+ COMP "THE_IPU_STAGE/SLICE_11959"
+ COMP "THE_IPU_STAGE/SLICE_11960"
+ COMP "THE_IPU_STAGE/SLICE_11961"
+ COMP "THE_IPU_STAGE/SLICE_11962"
+ COMP "THE_IPU_STAGE/SLICE_11963"
+ COMP "THE_IPU_STAGE/SLICE_11964"
+ COMP "THE_IPU_STAGE/SLICE_11965"
+ COMP "THE_IPU_STAGE/SLICE_11966"
+ COMP "THE_IPU_STAGE/SLICE_11967"
+ COMP "THE_IPU_STAGE/SLICE_11968"
+ COMP "THE_IPU_STAGE/SLICE_11969"
+ COMP "THE_IPU_STAGE/SLICE_11970"
+ COMP "THE_IPU_STAGE/SLICE_11971"
+ COMP "THE_IPU_STAGE/SLICE_11972"
+ COMP "THE_IPU_STAGE/SLICE_11973"
+ COMP "THE_IPU_STAGE/SLICE_11974"
+ COMP "THE_IPU_STAGE/SLICE_11975"
+ COMP "THE_IPU_STAGE/SLICE_11976"
+ COMP "THE_IPU_STAGE/SLICE_11977"
+ COMP "THE_IPU_STAGE/SLICE_11978"
+ COMP "THE_IPU_STAGE/SLICE_11979"
+ COMP "THE_IPU_STAGE/SLICE_11980"
+ COMP "THE_IPU_STAGE/SLICE_11981"
+ COMP "THE_IPU_STAGE/SLICE_11982"
+ COMP "THE_IPU_STAGE/SLICE_11983"
+ COMP "THE_IPU_STAGE/SLICE_11984"
+ COMP "THE_IPU_STAGE/SLICE_11985"
+ COMP "THE_IPU_STAGE/SLICE_11986"
+ COMP "THE_IPU_STAGE/SLICE_11987"
+ COMP "THE_IPU_STAGE/SLICE_11988"
+ COMP "THE_IPU_STAGE/SLICE_11989"
+ COMP "THE_IPU_STAGE/SLICE_11990"
+ COMP "THE_IPU_STAGE/SLICE_11991"
+ COMP "THE_IPU_STAGE/SLICE_11992"
+ COMP "THE_IPU_STAGE/SLICE_11993"
+ COMP "THE_IPU_STAGE/SLICE_11994"
+ COMP "THE_IPU_STAGE/SLICE_11995"
+ COMP "THE_IPU_STAGE/SLICE_11996"
+ COMP "THE_IPU_STAGE/SLICE_11997"
+ COMP "THE_IPU_STAGE/SLICE_11998"
+ COMP "THE_IPU_STAGE/SLICE_11999"
+ COMP "THE_IPU_STAGE/SLICE_12000"
+ COMP "THE_IPU_STAGE/SLICE_12001"
+ COMP "THE_IPU_STAGE/SLICE_12002"
+ COMP "THE_IPU_STAGE/SLICE_12003"
+ COMP "THE_IPU_STAGE/SLICE_12004"
+ COMP "THE_IPU_STAGE/SLICE_12005"
+ COMP "THE_IPU_STAGE/SLICE_12006"
+ COMP "THE_IPU_STAGE/SLICE_12007"
+ COMP "THE_IPU_STAGE/SLICE_12008"
+ COMP "THE_IPU_STAGE/SLICE_12009"
+ COMP "THE_IPU_STAGE/SLICE_12010"
+ COMP "THE_IPU_STAGE/SLICE_12011"
+ COMP "THE_IPU_STAGE/SLICE_12012"
+ COMP "THE_IPU_STAGE/SLICE_12013"
+ COMP "THE_IPU_STAGE/SLICE_12014"
+ COMP "THE_IPU_STAGE/SLICE_12015"
+ COMP "THE_IPU_STAGE/SLICE_12016"
+ COMP "THE_IPU_STAGE/SLICE_12017"
+ COMP "THE_IPU_STAGE/SLICE_12018"
+ COMP "THE_IPU_STAGE/SLICE_12019"
+ COMP "THE_IPU_STAGE/SLICE_12020"
+ COMP "THE_IPU_STAGE/SLICE_12021"
+ COMP "THE_IPU_STAGE/SLICE_12022"
+ COMP "THE_IPU_STAGE/SLICE_12023"
+ COMP "THE_IPU_STAGE/SLICE_12024"
+ COMP "THE_IPU_STAGE/SLICE_12025"
+ COMP "THE_IPU_STAGE/SLICE_12026"
+ COMP "THE_IPU_STAGE/SLICE_12027"
+ COMP "THE_IPU_STAGE/SLICE_12028"
+ COMP "THE_IPU_STAGE/SLICE_12029"
+ COMP "THE_IPU_STAGE/SLICE_12030"
+ COMP "THE_IPU_STAGE/SLICE_12031"
+ COMP "THE_IPU_STAGE/SLICE_12032"
+ COMP "THE_IPU_STAGE/SLICE_12033"
+ COMP "THE_IPU_STAGE/SLICE_12034"
+ COMP "THE_IPU_STAGE/SLICE_12035"
+ COMP "THE_IPU_STAGE/SLICE_12036"
+ COMP "THE_IPU_STAGE/SLICE_12037"
+ COMP "THE_IPU_STAGE/SLICE_12038"
+ COMP "THE_IPU_STAGE/SLICE_12039"
+ COMP "THE_IPU_STAGE/SLICE_12040"
+ COMP "THE_IPU_STAGE/SLICE_12041"
+ COMP "THE_IPU_STAGE/SLICE_12267"
+ COMP "THE_IPU_STAGE/SLICE_12268"
+ COMP "THE_IPU_STAGE/SLICE_12269"
+ COMP "THE_IPU_STAGE/SLICE_12270"
+ COMP "THE_IPU_STAGE/SLICE_12271"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12533"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12534"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12535"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12536"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12537"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12538"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12539"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12540"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12541"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12542"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12543"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12544"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12545"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12546"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12547"
+ COMP "THE_IPU_STAGE/THE_ADC_APV_MAP_MEM/SLICE_12548"
+ COMP "THE_IPU_STAGE/SLICE_12567"
+ COMP "THE_IPU_STAGE/SLICE_12568"
+ COMP "THE_IPU_STAGE/SLICE_12569"
+ COMP "THE_IPU_STAGE/SLICE_12570"
+ COMP "THE_IPU_STAGE/SLICE_12571"
+ COMP "THE_IPU_STAGE/SLICE_12572"
+ COMP "THE_IPU_STAGE/SLICE_12573"
+ COMP "THE_IPU_STAGE/SLICE_12574"
+ COMP "THE_IPU_STAGE/SLICE_12575"
+ COMP "THE_IPU_STAGE/SLICE_12576"
+ COMP "THE_IPU_STAGE/SLICE_12577"
+ COMP "THE_IPU_STAGE/SLICE_12578"
+ COMP "THE_IPU_STAGE/SLICE_12579"
+ COMP "THE_IPU_STAGE/SLICE_12631"
+ COMP "THE_IPU_STAGE/SLICE_12632"
+ COMP "THE_IPU_STAGE/SLICE_12633"
+ COMP "THE_IPU_STAGE/SLICE_12634"
+ COMP "THE_IPU_STAGE/SLICE_12635"
+ COMP "THE_IPU_STAGE/SLICE_12636"
+ COMP "THE_IPU_STAGE/SLICE_12637"
+ COMP "THE_IPU_STAGE/SLICE_12638"
+ COMP "THE_IPU_STAGE/SLICE_12639"
+ COMP "THE_IPU_STAGE/SLICE_12640"
+ COMP "THE_IPU_STAGE/SLICE_12741"
+ COMP "THE_IPU_STAGE/SLICE_12742"
+ COMP "THE_IPU_STAGE/SLICE_12743"
+ COMP "THE_IPU_STAGE/SLICE_12744"
+ COMP "THE_IPU_STAGE/SLICE_12745"
+ COMP "THE_IPU_STAGE/SLICE_12746"
+ COMP "THE_IPU_STAGE/SLICE_12747"
+ COMP "THE_IPU_STAGE/SLICE_12748"
+ COMP "THE_IPU_STAGE/SLICE_12749"
+ COMP "THE_IPU_STAGE/SLICE_12750"
+ COMP "THE_IPU_STAGE/SLICE_12751"
+ COMP "THE_IPU_STAGE/SLICE_12752"
+ COMP "THE_IPU_STAGE/SLICE_12753"
+ COMP "THE_IPU_STAGE/SLICE_12754"
+ COMP "THE_IPU_STAGE/SLICE_12755"
+ COMP "THE_IPU_STAGE/SLICE_12756"
+ COMP "THE_IPU_STAGE/SLICE_12757"
+ COMP "THE_IPU_STAGE/SLICE_12758"
+ COMP "THE_IPU_STAGE/SLICE_12759"
+ COMP "THE_IPU_STAGE/SLICE_12760"
+ COMP "THE_IPU_STAGE/SLICE_12761"
+ COMP "THE_IPU_STAGE/SLICE_12762"
+ COMP "THE_IPU_STAGE/SLICE_12763"
+ COMP "THE_IPU_STAGE/SLICE_12764"
+ COMP "THE_IPU_STAGE/SLICE_12765"
+ COMP "THE_IPU_STAGE/SLICE_12766"
+ COMP "THE_IPU_STAGE/SLICE_12767"
+ COMP "THE_IPU_STAGE/SLICE_12768"
+ COMP "THE_IPU_STAGE/SLICE_12769"
+ COMP "THE_IPU_STAGE/SLICE_12770"
+ COMP "THE_IPU_STAGE/SLICE_12771"
+ COMP "THE_IPU_STAGE/SLICE_12772"
+ COMP "THE_IPU_STAGE/SLICE_12773"
+ COMP "THE_IPU_STAGE/SLICE_12774"
+ COMP "THE_IPU_STAGE/SLICE_12775"
+ COMP "THE_IPU_STAGE/SLICE_12776"
+ COMP "THE_IPU_STAGE/SLICE_12777"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_12779"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_12780"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_12781"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_12782"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_12783"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_12784"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_12785"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_12786"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_12787"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_12788"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_12789"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_12790"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_12791"
+ COMP "THE_IPU_STAGE/SLICE_12826"
+ COMP "THE_IPU_STAGE/SLICE_12876"
+ COMP "THE_IPU_STAGE/SLICE_12877"
+ COMP "THE_IPU_STAGE/SLICE_12878"
+ COMP "THE_IPU_STAGE/SLICE_12879"
+ COMP "THE_IPU_STAGE/SLICE_12880"
+ COMP "THE_IPU_STAGE/SLICE_12881"
+ COMP "THE_IPU_STAGE/SLICE_12882"
+ COMP "THE_IPU_STAGE/SLICE_12883"
+ COMP "THE_IPU_STAGE/SLICE_12884"
+ COMP "THE_IPU_STAGE/SLICE_12885"
+ COMP "THE_IPU_STAGE/SLICE_12886"
+ COMP "THE_IPU_STAGE/SLICE_12887"
+ COMP "THE_IPU_STAGE/SLICE_12888"
+ COMP "THE_IPU_STAGE/SLICE_12892"
+ COMP "THE_IPU_STAGE/SLICE_12893"
+ COMP "THE_IPU_STAGE/SLICE_12894"
+ COMP "THE_IPU_STAGE/SLICE_12895"
+ COMP "THE_IPU_STAGE/SLICE_12896"
+ COMP "THE_IPU_STAGE/SLICE_12897"
+ COMP "THE_IPU_STAGE/SLICE_12898"
+ COMP "THE_IPU_STAGE/SLICE_12899"
+ COMP "THE_IPU_STAGE/SLICE_12900"
+ COMP "THE_IPU_STAGE/SLICE_12901"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_12902"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_12903"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_12904"
+ COMP "THE_IPU_STAGE/SLICE_12923"
+ COMP "THE_IPU_STAGE/SLICE_12924"
+ COMP "THE_IPU_STAGE/SLICE_12941"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_12951"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_12952"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_12953"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_12954"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_12955"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_12956"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_12957"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_12958"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_12959"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_12960"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_12961"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_12962"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_12963"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_12964"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_12965"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_12966"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_12967"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_12968"
+ COMP "THE_IPU_STAGE/SLICE_12985"
+ COMP "THE_IPU_STAGE/SLICE_12986"
+ COMP "THE_IPU_STAGE/SLICE_12987"
+ COMP "THE_IPU_STAGE/SLICE_12988"
+ COMP "THE_IPU_STAGE/SLICE_12989"
+ COMP "THE_IPU_STAGE/SLICE_12990"
+ COMP "THE_IPU_STAGE/SLICE_12991"
+ COMP "THE_IPU_STAGE/SLICE_12992"
+ COMP "THE_IPU_STAGE/SLICE_12993"
+ COMP "THE_IPU_STAGE/SLICE_12994"
+ COMP "THE_IPU_STAGE/SLICE_12995"
+ COMP "THE_IPU_STAGE/SLICE_12996"
+ COMP "THE_IPU_STAGE/SLICE_12997"
+ COMP "THE_IPU_STAGE/SLICE_12998"
+ COMP "THE_IPU_STAGE/SLICE_12999"
+ COMP "THE_IPU_STAGE/SLICE_13000"
+ COMP "THE_IPU_STAGE/SLICE_13001"
+ COMP "THE_IPU_STAGE/SLICE_13002"
+ COMP "THE_IPU_STAGE/SLICE_13003"
+ COMP "THE_IPU_STAGE/SLICE_13004"
+ COMP "THE_IPU_STAGE/SLICE_13005"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_13767"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/SLICE_13768"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_13769"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/SLICE_13770"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_13771"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/SLICE_13772"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_13773"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_13774"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_13775"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/SLICE_13776"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_13777"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/SLICE_13778"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_13779"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/SLICE_13780"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_13781"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/SLICE_13782"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_13783"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/SLICE_13784"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_13785"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/SLICE_13786"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_13787"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/SLICE_13788"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_13789"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/SLICE_13790"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_13791"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/SLICE_13792"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_13793"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/SLICE_13794"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_13795"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/SLICE_13796"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_13797"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/SLICE_13798"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/SLICE_13799"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_13800"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_13801"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/SLICE_13802"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_13803"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_13804"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_13805"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_13806"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/SLICE_13807"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_13808"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/SLICE_13809"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_13810"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/SLICE_13811"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_13812"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_13813"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_13814"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/SLICE_13815"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_13816"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_13817"
+ COMP "THE_IPU_STAGE/SLICE_13818"
+ COMP "THE_IPU_STAGE/SLICE_13819"
+ COMP "THE_IPU_STAGE/SLICE_13820"
+ COMP "THE_IPU_STAGE/SLICE_13821"
+ COMP "THE_IPU_STAGE/SLICE_13822"
+ COMP "THE_IPU_STAGE/SLICE_13823"
+ COMP "THE_IPU_STAGE/SLICE_13824"
+ COMP "THE_IPU_STAGE/SLICE_13825"
+ COMP "THE_IPU_STAGE/SLICE_13826"
+ COMP "THE_IPU_STAGE/SLICE_13827"
+ COMP "THE_IPU_STAGE/SLICE_13828"
+ COMP "THE_IPU_STAGE/SLICE_13829"
+ COMP "THE_IPU_STAGE/SLICE_13830"
+ COMP "THE_IPU_STAGE/SLICE_13831"
+ COMP "THE_IPU_STAGE/SLICE_13832"
+ COMP "THE_IPU_STAGE/SLICE_13833"
+ COMP "THE_IPU_STAGE/SLICE_13834"
+ COMP "THE_IPU_STAGE/SLICE_13835"
+ COMP "THE_IPU_STAGE/SLICE_13836"
+ COMP "THE_IPU_STAGE/SLICE_13837"
+ COMP "THE_IPU_STAGE/SLICE_13838"
+ COMP "THE_IPU_STAGE/SLICE_13839"
+ COMP "THE_IPU_STAGE/SLICE_13840"
+ COMP "THE_IPU_STAGE/SLICE_13841"
+ COMP "THE_IPU_STAGE/SLICE_13842"
+ COMP "THE_IPU_STAGE/SLICE_13843"
+ COMP "THE_IPU_STAGE/SLICE_13844"
+ COMP "THE_IPU_STAGE/SLICE_13845"
+ COMP "THE_IPU_STAGE/SLICE_13846"
+ COMP "THE_IPU_STAGE/SLICE_13847"
+ COMP "THE_IPU_STAGE/SLICE_13848"
+ COMP "THE_IPU_STAGE/SLICE_13849"
+ COMP "THE_IPU_STAGE/SLICE_13850"
+ COMP "THE_IPU_STAGE/SLICE_13851"
+ COMP "THE_IPU_STAGE/SLICE_13852"
+ COMP "THE_IPU_STAGE/SLICE_13853"
+ COMP "THE_IPU_STAGE/SLICE_13854"
+ COMP "THE_IPU_STAGE/SLICE_13855"
+ COMP "THE_IPU_STAGE/SLICE_13856"
+ COMP "THE_IPU_STAGE/SLICE_13857"
+ COMP "THE_IPU_STAGE/SLICE_13858"
+ COMP "THE_IPU_STAGE/SLICE_13859"
+ COMP "THE_IPU_STAGE/SLICE_13860"
+ COMP "THE_IPU_STAGE/SLICE_13861"
+ COMP "THE_IPU_STAGE/SLICE_13862"
+ COMP "THE_IPU_STAGE/SLICE_13863"
+ COMP "THE_IPU_STAGE/SLICE_13864"
+ COMP "THE_IPU_STAGE/SLICE_13865"
+ COMP "THE_IPU_STAGE/SLICE_13866"
+ COMP "THE_IPU_STAGE/SLICE_13867"
+ COMP "THE_IPU_STAGE/SLICE_13868"
+ COMP "THE_IPU_STAGE/SLICE_13869"
+ COMP "THE_IPU_STAGE/SLICE_13870"
+ COMP "THE_IPU_STAGE/SLICE_13871"
+ COMP "THE_IPU_STAGE/SLICE_13872"
+ COMP "THE_IPU_STAGE/SLICE_13873"
+ COMP "THE_IPU_STAGE/SLICE_13874"
+ COMP "THE_IPU_STAGE/SLICE_13875"
+ COMP "THE_IPU_STAGE/SLICE_13876"
+ COMP "THE_IPU_STAGE/SLICE_13877"
+ COMP "THE_IPU_STAGE/SLICE_13878"
+ COMP "THE_IPU_STAGE/SLICE_13879"
+ COMP "THE_IPU_STAGE/SLICE_13880"
+ COMP "THE_IPU_STAGE/SLICE_13881"
+ COMP "THE_IPU_STAGE/SLICE_13882"
+ COMP "THE_IPU_STAGE/SLICE_13883"
+ COMP "THE_IPU_STAGE/SLICE_13884"
+ COMP "THE_IPU_STAGE/SLICE_13885"
+ COMP "THE_IPU_STAGE/SLICE_13886"
+ COMP "THE_IPU_STAGE/SLICE_13887"
+ COMP "THE_IPU_STAGE/SLICE_13888"
+ COMP "THE_IPU_STAGE/SLICE_13889"
+ COMP "THE_IPU_STAGE/SLICE_13890"
+ COMP "THE_IPU_STAGE/SLICE_13891"
+ COMP "THE_IPU_STAGE/SLICE_13892"
+ COMP "THE_IPU_STAGE/SLICE_13893"
+ COMP "THE_IPU_STAGE/SLICE_13894"
+ COMP "THE_IPU_STAGE/SLICE_13895"
+ COMP "THE_IPU_STAGE/SLICE_13896"
+ COMP "THE_IPU_STAGE/SLICE_13897"
+ COMP "THE_IPU_STAGE/SLICE_13898"
+ COMP "THE_IPU_STAGE/SLICE_13899"
+ COMP "THE_IPU_STAGE/SLICE_13900"
+ COMP "THE_IPU_STAGE/SLICE_13901"
+ COMP "THE_IPU_STAGE/SLICE_13902"
+ COMP "THE_IPU_STAGE/SLICE_13903"
+ COMP "THE_IPU_STAGE/SLICE_13904"
+ COMP "THE_IPU_STAGE/SLICE_13905"
+ COMP "THE_IPU_STAGE/SLICE_13906"
+ COMP "THE_IPU_STAGE/SLICE_13907"
+ COMP "THE_IPU_STAGE/SLICE_13908"
+ COMP "THE_IPU_STAGE/SLICE_13909"
+ COMP "THE_IPU_STAGE/SLICE_13910"
+ COMP "THE_IPU_STAGE/SLICE_13911"
+ COMP "THE_IPU_STAGE/SLICE_13912"
+ COMP "THE_IPU_STAGE/SLICE_13913"
+ COMP "THE_IPU_STAGE/SLICE_13914"
+ COMP "THE_IPU_STAGE/SLICE_13915"
+ COMP "THE_IPU_STAGE/SLICE_13916"
+ COMP "THE_IPU_STAGE/SLICE_13917"
+ COMP "THE_IPU_STAGE/SLICE_13918"
+ COMP "THE_IPU_STAGE/SLICE_13919"
+ COMP "THE_IPU_STAGE/SLICE_13920"
+ COMP "THE_IPU_STAGE/SLICE_13921"
+ COMP "THE_IPU_STAGE/SLICE_13922"
+ COMP "THE_IPU_STAGE/SLICE_13923"
+ COMP "THE_IPU_STAGE/SLICE_13924"
+ COMP "THE_IPU_STAGE/SLICE_13925"
+ COMP "THE_IPU_STAGE/SLICE_13926"
+ COMP "THE_IPU_STAGE/SLICE_13927"
+ COMP "THE_IPU_STAGE/SLICE_13928"
+ COMP "THE_IPU_STAGE/SLICE_13929"
+ COMP "THE_IPU_STAGE/SLICE_13930"
+ COMP "THE_IPU_STAGE/SLICE_13931"
+ COMP "THE_IPU_STAGE/SLICE_13932"
+ COMP "THE_IPU_STAGE/SLICE_13933"
+ COMP "THE_IPU_STAGE/SLICE_13934"
+ COMP "THE_IPU_STAGE/SLICE_13935"
+ COMP "THE_IPU_STAGE/SLICE_13936"
+ COMP "THE_IPU_STAGE/SLICE_13937"
+ COMP "THE_IPU_STAGE/SLICE_13938"
+ COMP "THE_IPU_STAGE/SLICE_13939"
+ COMP "THE_IPU_STAGE/SLICE_13940"
+ COMP "THE_IPU_STAGE/SLICE_13941"
+ COMP "THE_IPU_STAGE/SLICE_13942"
+ COMP "THE_IPU_STAGE/SLICE_13943"
+ COMP "THE_IPU_STAGE/SLICE_13944"
+ COMP "THE_IPU_STAGE/SLICE_13945"
+ COMP "THE_IPU_STAGE/SLICE_13946"
+ COMP "THE_IPU_STAGE/SLICE_13947"
+ COMP "THE_IPU_STAGE/SLICE_13948"
+ COMP "THE_IPU_STAGE/SLICE_13949"
+ COMP "THE_IPU_STAGE/SLICE_13950"
+ COMP "THE_IPU_STAGE/SLICE_13951"
+ COMP "THE_IPU_STAGE/SLICE_13952"
+ COMP "THE_IPU_STAGE/SLICE_13953"
+ COMP "THE_IPU_STAGE/SLICE_13954"
+ COMP "THE_IPU_STAGE/SLICE_13955"
+ COMP "THE_IPU_STAGE/SLICE_13956"
+ COMP "THE_IPU_STAGE/SLICE_13957"
+ COMP "THE_IPU_STAGE/SLICE_13958"
+ COMP "THE_IPU_STAGE/SLICE_13959"
+ COMP "THE_IPU_STAGE/SLICE_13960"
+ COMP "THE_IPU_STAGE/SLICE_13961"
+ COMP "THE_IPU_STAGE/SLICE_13962"
+ COMP "THE_IPU_STAGE/SLICE_13963"
+ COMP "THE_IPU_STAGE/SLICE_13964"
+ COMP "THE_IPU_STAGE/SLICE_13965"
+ COMP "THE_IPU_STAGE/SLICE_13966"
+ COMP "THE_IPU_STAGE/SLICE_13967"
+ COMP "THE_IPU_STAGE/SLICE_13968"
+ COMP "THE_IPU_STAGE/SLICE_13969"
+ COMP "THE_IPU_STAGE/SLICE_13970"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/SLICE_13996"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/SLICE_13997"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/SLICE_13998"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/SLICE_13999"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/SLICE_14000"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/SLICE_14001"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/SLICE_14002"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/SLICE_14003"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/SLICE_14004"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/SLICE_14005"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/SLICE_14006"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_LFIFO/pdp_ram_0_0_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_9_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_8_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_4_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_12_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_15_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_5_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_13_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_10_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_7_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_1_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_2_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_3_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_0_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_11_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_1_1"
+ COMP "THE_IPU_STAGE/GEN_FIFO_14_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_2_0"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_0_2"
+ COMP "THE_IPU_STAGE/GEN_FIFO_6_THE_DFIFO/pdp_ram_0_1_1";
+REGION "ADC0_REGION" "R59C2" 46 4 DEVSIZE;
+PGROUP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4505"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4506"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4507"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4508"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4509"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4510"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4511"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4512"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4513"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4514"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4515"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4516"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4517"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4518"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4519"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4520"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4521"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4522"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4523"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4524"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4525"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4526"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4527"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4528"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4529"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4530"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4531"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4532"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4533"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4534"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4535"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4613"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4614"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4615"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4616"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4617"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4618"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4619"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4620"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4621"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4622"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4623"
+ COMP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/SLICE_4624";
+LOCATE PGROUP "THE_ADC0_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;
+PGROUP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4536"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4537"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4538"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4539"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4540"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4541"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4542"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4543"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4544"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4545"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4546"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4547"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4548"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4549"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4550"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4551"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4552"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4553"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4554"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4555"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4556"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4557"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4558"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4559"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4625"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4626"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4627"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4628"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4629"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4630"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4631"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4632"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4633"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4634"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4635"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4636"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4662"
+ COMP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/SLICE_4686";
+LOCATE PGROUP "THE_ADC0_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;
+PGROUP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4560"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4561"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4562"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4563"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4564"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4565"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4566"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4567"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4568"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4569"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4570"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4571"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4572"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4573"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4574"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4575"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4576"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4577"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4578"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4579"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4580"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4581"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4582"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4583"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4612"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4637"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4638"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4639"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4640"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4641"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4642"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4643"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4644"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4645"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4646"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4647"
+ COMP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/SLICE_4648";
+LOCATE PGROUP "THE_ADC0_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;
+PGROUP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4584"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4585"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4586"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4587"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4588"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4589"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4590"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4591"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4592"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4593"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4594"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4595"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4596"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4597"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4598"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4599"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4600"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4601"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4602"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4603"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4604"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4605"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4606"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4607"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4649"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4650"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4651"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4652"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4653"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4654"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4655"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4656"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4657"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4658"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4659"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4660"
+ COMP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/SLICE_4661";
+LOCATE PGROUP "THE_ADC0_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group" REGION "ADC0_REGION" ;
+PGROUP "THE_ADC0_HANDLER/ADC_DATA_HANDLER_group"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4608"
+ COMP "THE_ADC0_HANDLER/SLICE_4610"
+ COMP "THE_ADC0_HANDLER/SLICE_4611"
+ COMP "THE_ADC0_HANDLER/SLICE_4663"
+ COMP "THE_ADC0_HANDLER/SLICE_4664"
+ COMP "THE_ADC0_HANDLER/SLICE_4665"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4666"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4667"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4668"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4669"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4670"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4671"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4672"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4673"
+ COMP "THE_ADC0_HANDLER/THE_RESET_SYNC/SLICE_4674"
+ COMP "THE_ADC0_HANDLER/SLICE_4676"
+ COMP "THE_ADC0_HANDLER/SLICE_4677"
+ COMP "THE_ADC0_HANDLER/SLICE_4678"
+ COMP "THE_ADC0_HANDLER/SLICE_4679"
+ COMP "THE_ADC0_HANDLER/SLICE_4680"
+ COMP "THE_ADC0_HANDLER/SLICE_4681"
+ COMP "THE_ADC0_HANDLER/SLICE_4682"
+ COMP "THE_ADC0_HANDLER/SLICE_4683"
+ COMP "THE_ADC0_HANDLER/SLICE_4684"
+ COMP "THE_ADC0_HANDLER/SLICE_4685"
+ COMP "THE_ADC0_HANDLER/SLICE_10456"
+ COMP "THE_ADC0_HANDLER/SLICE_10469"
+ COMP "THE_ADC0_HANDLER/SLICE_10504"
+ COMP "THE_ADC0_HANDLER/SLICE_10505"
+ COMP "THE_ADC0_HANDLER/SLICE_10506"
+ COMP "THE_ADC0_HANDLER/SLICE_10507"
+ COMP "THE_ADC0_HANDLER/SLICE_10508"
+ COMP "THE_ADC0_HANDLER/SLICE_10509"
+ COMP "THE_ADC0_HANDLER/SLICE_10546"
+ COMP "THE_ADC0_HANDLER/SLICE_10547"
+ COMP "THE_ADC0_HANDLER/SLICE_10548"
+ COMP "THE_ADC0_HANDLER/SLICE_10549"
+ COMP "THE_ADC0_HANDLER/SLICE_10550"
+ COMP "THE_ADC0_HANDLER/SLICE_10551"
+ COMP "THE_ADC0_HANDLER/SLICE_10552"
+ COMP "THE_ADC0_HANDLER/SLICE_10553"
+ COMP "THE_ADC0_HANDLER/SLICE_10554"
+ COMP "THE_ADC0_HANDLER/SLICE_10555"
+ COMP "THE_ADC0_HANDLER/SLICE_10556"
+ COMP "THE_ADC0_HANDLER/SLICE_10557"
+ COMP "THE_ADC0_HANDLER/SLICE_10558"
+ COMP "THE_ADC0_HANDLER/SLICE_10559"
+ COMP "THE_ADC0_HANDLER/SLICE_10560"
+ COMP "THE_ADC0_HANDLER/SLICE_10561"
+ COMP "THE_ADC0_HANDLER/SLICE_10562"
+ COMP "THE_ADC0_HANDLER/SLICE_10563"
+ COMP "THE_ADC0_HANDLER/SLICE_10564"
+ COMP "THE_ADC0_HANDLER/SLICE_10565"
+ COMP "THE_ADC0_HANDLER/SLICE_10566"
+ COMP "THE_ADC0_HANDLER/SLICE_10567"
+ COMP "THE_ADC0_HANDLER/SLICE_10568"
+ COMP "THE_ADC0_HANDLER/SLICE_10569"
+ COMP "THE_ADC0_HANDLER/SLICE_10570"
+ COMP "THE_ADC0_HANDLER/SLICE_10571"
+ COMP "THE_ADC0_HANDLER/SLICE_10572"
+ COMP "THE_ADC0_HANDLER/SLICE_10573"
+ COMP "THE_ADC0_HANDLER/SLICE_10574"
+ COMP "THE_ADC0_HANDLER/SLICE_10575"
+ COMP "THE_ADC0_HANDLER/SLICE_10576"
+ COMP "THE_ADC0_HANDLER/SLICE_10577"
+ COMP "THE_ADC0_HANDLER/SLICE_10578"
+ COMP "THE_ADC0_HANDLER/SLICE_10579"
+ COMP "THE_ADC0_HANDLER/SLICE_10580"
+ COMP "THE_ADC0_HANDLER/SLICE_10581"
+ COMP "THE_ADC0_HANDLER/SLICE_10582"
+ COMP "THE_ADC0_HANDLER/SLICE_10583"
+ COMP "THE_ADC0_HANDLER/SLICE_10584"
+ COMP "THE_ADC0_HANDLER/SLICE_10585"
+ COMP "THE_ADC0_HANDLER/SLICE_10586"
+ COMP "THE_ADC0_HANDLER/SLICE_10587"
+ COMP "THE_ADC0_HANDLER/SLICE_13403"
+ COMP "THE_ADC0_HANDLER/SLICE_13404";
+REGION "ADC1_REGION" "R9C2" 49 4 DEVSIZE;
+PGROUP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4713"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4714"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4715"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4716"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4717"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4718"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4719"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4720"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4721"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4722"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4723"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4724"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4725"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4726"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4727"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4728"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4729"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4730"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4731"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4732"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4733"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4734"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4735"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4736"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4737"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4738"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4739"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4740"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4741"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4742"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4743"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4821"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4822"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4823"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4824"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4825"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4826"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4827"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4828"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4829"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4830"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4831"
+ COMP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/SLICE_4832";
+LOCATE PGROUP "THE_ADC1_HANDLER/THE_ADC_0_1_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;
+PGROUP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4744"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4745"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4746"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4747"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4748"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4749"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4750"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4751"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4752"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4753"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4754"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4755"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4756"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4757"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4758"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4759"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4760"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4761"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4762"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4763"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4764"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4765"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4766"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4767"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4833"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4834"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4835"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4836"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4837"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4838"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4839"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4840"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4841"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4842"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4843"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4844"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4870"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4884"
+ COMP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/SLICE_4885";
+LOCATE PGROUP "THE_ADC1_HANDLER/THE_ADC_2_3_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;
+PGROUP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4768"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4769"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4770"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4771"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4772"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4773"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4774"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4775"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4776"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4777"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4778"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4779"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4780"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4781"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4782"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4783"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4784"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4785"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4786"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4787"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4788"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4789"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4790"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4791"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4820"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4845"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4846"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4847"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4848"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4849"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4850"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4851"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4852"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4853"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4854"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4855"
+ COMP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/SLICE_4856";
+LOCATE PGROUP "THE_ADC1_HANDLER/THE_ADC_4_5_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;
+PGROUP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4792"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4793"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4794"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4795"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4796"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4797"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4798"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4799"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4800"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4801"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4802"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4803"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4804"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4805"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4806"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4807"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4808"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4809"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4810"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4811"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4812"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4813"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4814"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4815"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4857"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4858"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4859"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4860"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4861"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4862"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4863"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4864"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4865"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4866"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4867"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4868"
+ COMP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/SLICE_4869";
+LOCATE PGROUP "THE_ADC1_HANDLER/THE_ADC_6_7_CH/TWOCHANNELS_group" REGION "ADC1_REGION" ;
+PGROUP "THE_ADC1_HANDLER/ADC_DATA_HANDLER_group"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4816"
+ COMP "THE_ADC1_HANDLER/SLICE_4818"
+ COMP "THE_ADC1_HANDLER/SLICE_4819"
+ COMP "THE_ADC1_HANDLER/SLICE_4871"
+ COMP "THE_ADC1_HANDLER/SLICE_4872"
+ COMP "THE_ADC1_HANDLER/SLICE_4873"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4874"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4875"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4876"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4877"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4878"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4879"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4880"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4881"
+ COMP "THE_ADC1_HANDLER/THE_RESET_SYNC/SLICE_4882"
+ COMP "THE_ADC1_HANDLER/SLICE_4886"
+ COMP "THE_ADC1_HANDLER/SLICE_4887"
+ COMP "THE_ADC1_HANDLER/SLICE_4888"
+ COMP "THE_ADC1_HANDLER/SLICE_4889"
+ COMP "THE_ADC1_HANDLER/SLICE_4890"
+ COMP "THE_ADC1_HANDLER/SLICE_4891"
+ COMP "THE_ADC1_HANDLER/SLICE_4892"
+ COMP "THE_ADC1_HANDLER/SLICE_4893"
+ COMP "THE_ADC1_HANDLER/SLICE_4894"
+ COMP "THE_ADC1_HANDLER/SLICE_4895"
+ COMP "THE_ADC1_HANDLER/SLICE_10474"
+ COMP "THE_ADC1_HANDLER/SLICE_10487"
+ COMP "THE_ADC1_HANDLER/SLICE_10510"
+ COMP "THE_ADC1_HANDLER/SLICE_10511"
+ COMP "THE_ADC1_HANDLER/SLICE_10512"
+ COMP "THE_ADC1_HANDLER/SLICE_10513"
+ COMP "THE_ADC1_HANDLER/SLICE_10514"
+ COMP "THE_ADC1_HANDLER/SLICE_10515"
+ COMP "THE_ADC1_HANDLER/SLICE_10516"
+ COMP "THE_ADC1_HANDLER/SLICE_10517"
+ COMP "THE_ADC1_HANDLER/SLICE_10518"
+ COMP "THE_ADC1_HANDLER/SLICE_10519"
+ COMP "THE_ADC1_HANDLER/SLICE_10520"
+ COMP "THE_ADC1_HANDLER/SLICE_10521"
+ COMP "THE_ADC1_HANDLER/SLICE_10522"
+ COMP "THE_ADC1_HANDLER/SLICE_10523"
+ COMP "THE_ADC1_HANDLER/SLICE_10524"
+ COMP "THE_ADC1_HANDLER/SLICE_10525"
+ COMP "THE_ADC1_HANDLER/SLICE_10526"
+ COMP "THE_ADC1_HANDLER/SLICE_10527"
+ COMP "THE_ADC1_HANDLER/SLICE_10528"
+ COMP "THE_ADC1_HANDLER/SLICE_10529"
+ COMP "THE_ADC1_HANDLER/SLICE_10530"
+ COMP "THE_ADC1_HANDLER/SLICE_10531"
+ COMP "THE_ADC1_HANDLER/SLICE_10532"
+ COMP "THE_ADC1_HANDLER/SLICE_10533"
+ COMP "THE_ADC1_HANDLER/SLICE_10534"
+ COMP "THE_ADC1_HANDLER/SLICE_10535"
+ COMP "THE_ADC1_HANDLER/SLICE_10536"
+ COMP "THE_ADC1_HANDLER/SLICE_10537"
+ COMP "THE_ADC1_HANDLER/SLICE_10538"
+ COMP "THE_ADC1_HANDLER/SLICE_10539"
+ COMP "THE_ADC1_HANDLER/SLICE_10540"
+ COMP "THE_ADC1_HANDLER/SLICE_10541"
+ COMP "THE_ADC1_HANDLER/SLICE_10542"
+ COMP "THE_ADC1_HANDLER/SLICE_10543"
+ COMP "THE_ADC1_HANDLER/SLICE_10544"
+ COMP "THE_ADC1_HANDLER/SLICE_10545"
+ COMP "THE_ADC1_HANDLER/SLICE_10588"
+ COMP "THE_ADC1_HANDLER/SLICE_10589"
+ COMP "THE_ADC1_HANDLER/SLICE_10590"
+ COMP "THE_ADC1_HANDLER/SLICE_10591"
+ COMP "THE_ADC1_HANDLER/SLICE_10592"
+ COMP "THE_ADC1_HANDLER/SLICE_10593"
+ COMP "THE_ADC1_HANDLER/SLICE_10594"
+ COMP "THE_ADC1_HANDLER/SLICE_10595"
+ COMP "THE_ADC1_HANDLER/SLICE_10596"
+ COMP "THE_ADC1_HANDLER/SLICE_10597"
+ COMP "THE_ADC1_HANDLER/SLICE_10598"
+ COMP "THE_ADC1_HANDLER/SLICE_10599"
+ COMP "THE_ADC1_HANDLER/SLICE_13406"
+ COMP "THE_ADC1_HANDLER/SLICE_13407";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8204"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8205"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8206"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8215"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8216"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8217"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8218"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8219"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8220"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8221"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8222"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8223"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8224"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8225"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8226"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8227"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8228"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8229"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8230"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8231"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8232"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8233"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8234"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8235"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8236"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8237"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8238"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8239"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8240"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8241"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8242"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8243"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8244"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8287"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8288"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8301"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8302"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8303"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8304"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8305"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8306"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8307"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8308"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8309"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8310"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8311"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8312"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_8313"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8314"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8315"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8316"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8317"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8318"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8319"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/ARBITER/SLICE_8320"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8321"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/ARBITER/SLICE_8322"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/ARBITER/SLICE_8323"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/ARBITER/SLICE_8324"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8325"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_8326"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9257"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9258"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9259"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9260"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9261"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9262"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9263"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9264"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9265"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9266"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9267"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9268"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9269"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_9270"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/k_1_0/SLICE_11606"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_11831"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_11853"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_11854"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_11855"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_11856"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_11857"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_11858"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12082"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12083"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12275"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12276"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12277"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12278"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12279"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12280"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12281"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12282"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12283"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12284"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12285"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12286"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12287"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12288"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12289"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12290"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12291"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12292"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12293"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12294"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12295"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12296"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12297"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12298"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12299"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12300"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12301"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12302"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12303"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12304"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12305"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12306"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12307"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12308"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12586"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12593"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12594"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12616"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12800"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12801"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/ARBITER/SLICE_12835"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12926"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12927"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_12928"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/MUX_SBUF/gen_version_0_sbuf/SLICE_13143"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/ARBITER/SLICE_13144"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/ARBITER/SLICE_13145"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13146"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13147"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13148"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13149"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13150"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13986"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13987"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13988"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13989"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13990"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13991"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/MPLEX/SLICE_13992";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8207"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8245"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8246"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8247"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8517"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8518"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8519"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8520"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8521"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8522"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8523"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8524"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8525"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8526"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12188"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12189"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12190";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8209"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8260"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8261"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8262"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8415"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8416"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8651"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8652"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8653"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8654"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8655"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8656"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8657"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8658"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8659"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12171"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12172"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_13327"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_13328"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_13329";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/TRMBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8211"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8212"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8271"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8272"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8273"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8274"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8275"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8276"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8277"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8293"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8294"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8295"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8296"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8297"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8298"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8855"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8856"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8857"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8858"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8859"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8860"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8861"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_8862"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_11827"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_11828"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_12084"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_12657"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_12658"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_12802"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_12862"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_2_gentermbuf_termbuf/SLICE_13151";
+PGROUP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8213"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8278"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8279"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8280"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8414"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8417"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8418"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8921"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8922"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8923"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8924"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8925"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8926"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8927"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8928"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_8929"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12152"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12153"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_12154"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_13307"
+ COMP "THE_RICH_TRB/THE_UNIFIED_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/SLICE_13308";
+PGROUP "THE_SLAVE_BUS/THE_BUS_HANDLER/Bus_handler_group"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_9325"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_9326"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_9327"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_9328"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_9329"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_9330"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_9331"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10164"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10165"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10166"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10167"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10168"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10169"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10170"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10407"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10408"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10409"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10410"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10411"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10412"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10413"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10414"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10415"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10416"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10417"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10418"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10419"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10420"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10421"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10422"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10423"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10424"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10425"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10426"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10427"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10428"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10429"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10430"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10431"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10432"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10433"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10434"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10435"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10436"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10437"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10438"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10439"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10440"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10441"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_10451"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11138"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11139"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11140"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11141"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11142"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11143"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11144"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11145"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11146"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11147"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11148"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11149"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11150"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11151"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11152"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11153"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11154"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11155"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11156"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11157"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11158"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11159"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11160"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11161"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11162"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11163"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11164"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11165"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11166"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11167"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11168"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11185"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11187"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11188"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m113/SLICE_11511"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m559/SLICE_11512"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m961/SLICE_11513"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m966/SLICE_11514"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1035/SLICE_11515"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1042/SLICE_11516"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1300/SLICE_11517"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1553/SLICE_11518"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2091/SLICE_11519"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_DAT_WRITE_ACK_OUT_1_16_i_m2/SLICE_11520"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2755/SLICE_11521"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2749/SLICE_11522"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2746/SLICE_11523"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2737/SLICE_11524"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2726/SLICE_11525"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2723/SLICE_11526"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2707/SLICE_11527"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2693/SLICE_11528"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2687/SLICE_11529"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2369/SLICE_11530"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2318/SLICE_11531"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2243/SLICE_11532"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2139/SLICE_11533"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1981/SLICE_11534"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1942/SLICE_11535"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1855/SLICE_11536"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1852/SLICE_11537"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1846/SLICE_11538"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1626/SLICE_11539"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1571/SLICE_11540"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1557/SLICE_11541"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1472/SLICE_11542"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1341/SLICE_11543"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1164/SLICE_11544"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1046/SLICE_11545"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1027/SLICE_11546"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1020/SLICE_11547"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m946/SLICE_11548"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m923/SLICE_11549"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m909/SLICE_11550"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m889/SLICE_11551"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m887/SLICE_11552"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m687/SLICE_11553"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m681/SLICE_11554"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m677/SLICE_11555"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m671/SLICE_11556"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m656/SLICE_11557"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m651/SLICE_11558"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m512/SLICE_11559"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m484/SLICE_11560"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m468/SLICE_11561"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m437/SLICE_11562"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m406/SLICE_11563"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m377/SLICE_11564"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m283/SLICE_11565"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m227/SLICE_11566"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m197/SLICE_11567"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m188/SLICE_11568"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m178/SLICE_11569"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m174/SLICE_11570"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m150/SLICE_11571"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2673/SLICE_11572"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2732/SLICE_11573"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2702/SLICE_11574"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2608/SLICE_11575"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2502/SLICE_11576"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1625/SLICE_11577"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1796/SLICE_11578"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2098/SLICE_11579"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2634/SLICE_11580"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2682/SLICE_11581"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_DAT_WRITE_ACK_OUT_1_13_i_m2/SLICE_11582"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_DAT_WRITE_ACK_OUT_1_4_i_m2/SLICE_11583"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2779/SLICE_11584"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2661/SLICE_11585"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2656/SLICE_11586"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2651/SLICE_11587"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2641/SLICE_11588"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2628/SLICE_11589"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2615/SLICE_11590"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2601/SLICE_11591"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2572/SLICE_11592"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2309/SLICE_11593"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2057/SLICE_11594"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1764/SLICE_11595"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1748/SLICE_11596"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1727/SLICE_11597"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1672/SLICE_11598"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1399/SLICE_11599"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1398/SLICE_11600"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1173/SLICE_11601"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1013/SLICE_11602"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2636/SLICE_11603"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m2630/SLICE_11604"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/proc_reg_output_signals_un18_dat_data_out_m1674/SLICE_11605"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11847"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11848"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11849"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11850"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11851"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_11852"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12068"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12069"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12070"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12071"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12072"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12073"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12074"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12075"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12076"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12077"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12078"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12079"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12080"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12081"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12274"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12583"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12584"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12585"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12592"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12611"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12612"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12613"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12614"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12615"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12653"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12654"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12655"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12656"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12798"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12799"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12833"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12834"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12861"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12905"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12906"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12942"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12970"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12975"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_12976"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13077"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13078"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13079"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13080"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13081"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13082"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13083"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13084"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13085"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13086"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13087"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13088"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13089"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13090"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13091"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13092"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13093"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13094"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13095"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13096"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13097"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13098"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13099"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13100"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13101"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13102"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13103"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13104"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13105"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13106"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13107"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13108"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13109"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13110"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13111"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13112"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13113"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13114"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13115"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13116"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13117"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13118"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13119"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13120"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13121"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13122"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13123"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13124"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13125"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13126"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13127"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13128"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13129"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13130"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13131"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13132"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13133"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13134"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13135"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13136"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13137"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13138"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13139"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13140"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13141"
+ COMP "THE_SLAVE_BUS/THE_BUS_HANDLER/SLICE_13142";
+PGROUP "THE_SLAVE_BUS/THE_SPI_MEMORY/SPI_group"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/SLICE_10125"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/SLICE_10126"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/SLICE_10127"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/SLICE_10128"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/SLICE_10174"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/SLICE_13037"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_0_1"
+ COMP "THE_SLAVE_BUS/THE_SPI_MEMORY/THE_BUS_SPI_DPRAM/spi_dpram_32_to_8_0_1_0";
+LOCATE COMP "APV0_SDA" SITE "Y6" ;
+LOCATE COMP "APV0A_CLK" SITE "AC7" ;
+LOCATE COMP "CLK100M" SITE "AJ14" ;
+LOCATE COMP "ADC0_OUT_7" SITE "T5" ;
+LOCATE COMP "ADC0_OUT_6" SITE "U3" ;
+LOCATE COMP "ADC0_OUT_5" SITE "U5" ;
+LOCATE COMP "ADC0_OUT_4" SITE "Y1" ;
+LOCATE COMP "ADC0_OUT_3" SITE "AA1" ;
+LOCATE COMP "ADC0_OUT_2" SITE "AB2" ;
+LOCATE COMP "ADC0_OUT_1" SITE "AC1" ;
+LOCATE COMP "ADC0_OUT_0" SITE "AD2" ;
+LOCATE COMP "ADC0_ADCLK" SITE "R3" ;
+LOCATE COMP "ADC1_OUT_7" SITE "E2" ;
+LOCATE COMP "ADC1_OUT_6" SITE "G2" ;
+LOCATE COMP "ADC1_OUT_5" SITE "J5" ;
+LOCATE COMP "ADC1_OUT_4" SITE "J3" ;
+LOCATE COMP "ADC1_OUT_3" SITE "K2" ;
+LOCATE COMP "ADC1_OUT_2" SITE "N5" ;
+LOCATE COMP "ADC1_OUT_1" SITE "M4" ;
+LOCATE COMP "ADC1_OUT_0" SITE "P3" ;
+LOCATE COMP "ADC1_ADCLK" SITE "D2" ;
+LOCATE COMP "U_SPI_SDO" SITE "AE24" ;
+LOCATE COMP "U_SPI_SDI" SITE "AE25" ;
+LOCATE COMP "U_SPI_SCK" SITE "AF26" ;
+LOCATE COMP "U_SPI_CS" SITE "AD24" ;
+LOCATE COMP "APV1_1W_7" SITE "B15" ;
+LOCATE COMP "APV1_1W_6" SITE "A16" ;
+LOCATE COMP "APV1_1W_5" SITE "B16" ;
+LOCATE COMP "APV1_1W_4" SITE "A17" ;
+LOCATE COMP "APV1_1W_3" SITE "B17" ;
+LOCATE COMP "APV1_1W_2" SITE "C16" ;
+LOCATE COMP "APV1_1W_1" SITE "C17" ;
+LOCATE COMP "APV1_1W_0" SITE "D16" ;
+LOCATE COMP "APV0_1W_7" SITE "AJ16" ;
+LOCATE COMP "APV0_1W_6" SITE "AK16" ;
+LOCATE COMP "APV0_1W_5" SITE "AJ17" ;
+LOCATE COMP "APV0_1W_4" SITE "AK17" ;
+LOCATE COMP "APV0_1W_3" SITE "AG18" ;
+LOCATE COMP "APV0_1W_2" SITE "AG19" ;
+LOCATE COMP "APV0_1W_1" SITE "AG20" ;
+LOCATE COMP "APV0_1W_0" SITE "AG21" ;
+LOCATE COMP "FPGA_LED_ADC_1" SITE "H3" ;
+LOCATE COMP "FPGA_LED_ADC_0" SITE "V2" ;
+LOCATE COMP "FPGA_LED_PLL" SITE "AG22" ;
+LOCATE COMP "FPGA_LED_LINK" SITE "K26" ;
+LOCATE COMP "FPGA_LED_TXD" SITE "J27" ;
+LOCATE COMP "FPGA_LED_RXD" SITE "J28" ;
+LOCATE COMP "FPGA_LED_6" SITE "G28" ;
+LOCATE COMP "FPGA_LED_5" SITE "G27" ;
+LOCATE COMP "FPGA_LED_4" SITE "H28" ;
+LOCATE COMP "FPGA_LED_3" SITE "H27" ;
+LOCATE COMP "BP_LED" SITE "AE8" ;
+LOCATE COMP "BP_ONEWIRE" SITE "F7" ;
+LOCATE COMP "BP_SECTOR_2" SITE "AF12" ;
+LOCATE COMP "BP_SECTOR_1" SITE "AF13" ;
+LOCATE COMP "BP_SECTOR_0" SITE "AF15" ;
+LOCATE COMP "BP_MODULE_2" SITE "F13" ;
+LOCATE COMP "BP_MODULE_1" SITE "E12" ;
+LOCATE COMP "BP_MODULE_0" SITE "G11" ;
+LOCATE COMP "ADCM_ONEWIRE" SITE "F29" ;
+LOCATE COMP "SD_TXDIS" SITE "J29" ;
+LOCATE COMP "SD_LOS" SITE "F30" ;
+LOCATE COMP "SD_PRESENT" SITE "G30" ;
+LOCATE COMP "UC_REBOOT" SITE "Y28" ;
+LOCATE COMP "UC_RESET" SITE "V26" ;
+LOCATE COMP "ADC1_LCLK" SITE "L3" ;
+LOCATE COMP "ADC1_SCK" SITE "F1" ;
+LOCATE COMP "ADC1_SDI" SITE "F2" ;
+LOCATE COMP "ADC1_CS" SITE "E1" ;
+LOCATE COMP "ADC1_PD" SITE "H1" ;
+LOCATE COMP "ADC1_RST" SITE "G3" ;
+LOCATE COMP "ADC1_CLK" SITE "H2" ;
+LOCATE COMP "ADC0_LCLK" SITE "T3" ;
+LOCATE COMP "ADC0_SCK" SITE "W2" ;
+LOCATE COMP "ADC0_SDI" SITE "AB1" ;
+LOCATE COMP "ADC0_CS" SITE "AC3" ;
+LOCATE COMP "ADC0_PD" SITE "V1" ;
+LOCATE COMP "ADC0_RST" SITE "AD3" ;
+LOCATE COMP "ADC0_CLK" SITE "W1" ;
+LOCATE COMP "ENB_LVDS_7" SITE "F6" ;
+LOCATE COMP "ENB_LVDS_6" SITE "D5" ;
+LOCATE COMP "ENB_LVDS_5" SITE "D4" ;
+LOCATE COMP "ENB_LVDS_4" SITE "E5" ;
+LOCATE COMP "ENB_LVDS_3" SITE "D15" ;
+LOCATE COMP "ENB_LVDS_2" SITE "E13" ;
+LOCATE COMP "ENB_LVDS_1" SITE "D13" ;
+LOCATE COMP "ENB_LVDS_0" SITE "D12" ;
+LOCATE COMP "APV1_SCL" SITE "K6" ;
+LOCATE COMP "APV1_SDA" SITE "K7" ;
+LOCATE COMP "APV1_RST" SITE "K5" ;
+LOCATE COMP "APV1B_TRG" SITE "G6" ;
+LOCATE COMP "APV1A_TRG" SITE "L5" ;
+LOCATE COMP "APV1B_CLK" SITE "G5" ;
+LOCATE COMP "APV1A_CLK" SITE "J8" ;
+LOCATE COMP "ENA_LVDS_7" SITE "AG2" ;
+LOCATE COMP "ENA_LVDS_6" SITE "AG3" ;
+LOCATE COMP "ENA_LVDS_5" SITE "AG4" ;
+LOCATE COMP "ENA_LVDS_4" SITE "AG5" ;
+LOCATE COMP "ENA_LVDS_3" SITE "AG11" ;
+LOCATE COMP "ENA_LVDS_2" SITE "AG12" ;
+LOCATE COMP "ENA_LVDS_1" SITE "AG13" ;
+LOCATE COMP "ENA_LVDS_0" SITE "AG15" ;
+LOCATE COMP "APV0_SCL" SITE "AA6" ;
+LOCATE COMP "APV0_RST" SITE "AA5" ;
+LOCATE COMP "APV0B_TRG" SITE "AB4" ;
+LOCATE COMP "APV0A_TRG" SITE "Y9" ;
+LOCATE COMP "APV0B_CLK" SITE "W3" ;
+LOCATE COMP "EXT_IN_3" SITE "AA30" ;
+LOCATE COMP "EXT_IN_2" SITE "AB30" ;
+LOCATE COMP "EXT_IN_1" SITE "AB29" ;
+LOCATE COMP "EXT_IN_0" SITE "AB28" ;
+LOCATE COMP "THE_RICH_TRB/THE_MEDIA_INTERFACE/gen_serdes_2_THE_SERDES/PCSC_INST" SITE "URPCS" ;
+LOCATE COMP "THE_100M_DLL/dll_100m_0_0" SITE "DLL_R103C1" ;
+FREQUENCY NET "clk_adc" 40.000000 MHz ;
+FREQUENCY NET "CLK100M_c" 100.000000 MHz ;
+FREQUENCY NET "clk_apv_c" 40.000000 MHz ;
+FREQUENCY NET "cts_clk40m" 40.000000 MHz ;
+FREQUENCY NET "sysclk_c" 100.000000 MHz ;
+FREQUENCY NET "EXT_IN_c_3" 40.000000 MHz ;
+SCHEMATIC END ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+DEFINE PORT GROUP "enable_lvds_group" "EN?_LVDS_{0:7}" ;
+USERCODE HEX "DEADAFFE" ;
+REGION "MEDIA_INTERFACE_REGION" "R9C100" 10 28 DEVSIZE;
+PERIOD PORT "ADC0_LCLK" 4.166600 nS ;
+USE PRIMARY PURE NET "ADC0_LCLK_c" ;
+DEFINE PORT GROUP "ADC0_INPUT" "ADC0_OUT*"
+"ADC0_ADCLK*" ;
+INPUT_SETUP GROUP "ADC0_INPUT"0.600000 ns HOLD 0.600000 ns CLKPORT "ADC0_LCLK" ;
+PERIOD PORT "ADC1_LCLK" 4.166600 nS ;
+USE PRIMARY PURE NET "ADC1_LCLK_c" ;
+DEFINE PORT GROUP "ADC1_INPUT" "ADC1_OUT*"
+"ADC1_ADCLK*" ;
+INPUT_SETUP GROUP "ADC1_INPUT"0.600000 ns HOLD 0.600000 ns CLKPORT "ADC1_LCLK" ;
+COMMERCIAL ;
--- /dev/null
+
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSC quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSC quad to the final design requirements.
+
+DEVICE_NAME "LFE2M100E"
+PROTOCOL "GIGE"
+CH0_MODE "DISABLE"
+CH1_MODE "DISABLE"
+CH2_MODE "SINGLE"
+CH3_MODE "DISABLE"
+PLL_SRC "CORE_TXREFCLK"
+DATARANGE "MEDHIGH"
+CH2_CDR_SRC "CORE_RXREFCLK"
+CH2_DATA_WIDTH "16"
+CH2_REFCK_MULT "20X"
+#REFCLK_RATE 100.0
+#FPGAINTCLK_RATE 100.0
+CH2_TDRV_AMP "0"
+CH2_TX_PRE "DISABLE"
+CH2_RTERM_TX "50"
+CH2_RX_EQ "DISABLE"
+CH2_RTERM_RX "50"
+CH2_RX_DCC "DC"
+LOS_THRESHOLD "0"
+PLL_TERM "50"
+PLL_DCC "AC"
+PLL_LOL_SET "0"
+CH2_TX_SB "NORMAL"
+CH2_RX_SB "NORMAL"
+CH2_8B10B "NORMAL"
+COMMA_A "1100000101"
+COMMA_B "0011111010"
+COMMA_M "1111111111"
+CH2_COMMA_ALIGN "AUTO"
+CH2_CTC_BYP "NORMAL"
+CC_MATCH1 "0000000000"
+CC_MATCH2 "0000000000"
+CC_MATCH3 "0110111100"
+CC_MATCH4 "0001010000"
+CC_MATCH_MODE "MATCH_3_4"
+CC_MIN_IPG "3"
+CCHMARK "9"
+CCLMARK "7"
+OS_REFCK2CORE "1"
+OS_PLLQCLKPORTS "0"
+OS_INT_ALL "0"
+
--- /dev/null
+ssh -L 33092:hadeb05.gsi.de:33092 -L 1702:hadeb05.gsi.de:1702 -L 32773:lxcad01.gsi.de:32773 -L 27000:lxcad01.gsi.de:27000 -L 64863:lxcad01.gsi.de:64863 -L 1717:lxcad01.gsi.de:1717 hadaq@lxi001.gsi.de -N -v
jspc29 / adcm.git / commitdiff