*** empty log message ***

diff --git a/trb_net16_addresses.vhd b/trb_net16_addresses.vhd
index 4257a20f681b18465f3deb751873e413573fd869..01961e87d1ffacab4ae6b886aaaf73112b7fdacc 100644 (file)
--- a/trb_net16_addresses.vhd
+++ b/trb_net16_addresses.vhd
@@ -17,22 +17,23 @@ entity trb_net16_addresses is
     CLK    : in std_logic;
     RESET  : in std_logic;
     CLK_EN : in std_logic;
-    API_DATA_IN       : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
-    API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
-    API_DATAREADY_IN  : in  std_logic;
-    API_READ_OUT      : out std_logic;
-    RAM_DATA_IN       : in  std_logic_vector(15 downto 0);
-    RAM_DATA_OUT      : out std_logic_vector(15 downto 0);
-    RAM_ADDR_IN       : in  std_logic_vector(2 downto 0);
-    RAM_WR_IN         : in  std_logic;
-    API_DATA_OUT      : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
-    API_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0);
-    API_DATAREADY_OUT : out std_logic;
-    API_READ_IN       : in  std_logic;
-    ADDRESS_REJECTED  : out std_logic;
-    API_SEND_OUT      : out std_logic;
-    ADDRESS_OUT       : out std_logic_vector(15 downto 0);
-    STAT_DEBUG        : out std_logic_vector(15 downto 0)
+    API_DATA_IN         : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    API_PACKET_NUM_IN   : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    API_DATAREADY_IN    : in  std_logic;
+    API_READ_OUT        : out std_logic;
+    RAM_DATA_IN         : in  std_logic_vector(15 downto 0);
+    RAM_DATA_OUT        : out std_logic_vector(15 downto 0);
+    RAM_ADDR_IN         : in  std_logic_vector(2 downto 0);
+    RAM_WR_IN           : in  std_logic;
+    API_DATA_OUT        : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    API_PACKET_NUM_OUT  : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    API_DATAREADY_OUT   : out std_logic;
+    API_READ_IN         : in  std_logic;
+    ADDRESS_REJECTED    : out std_logic;
+    DONT_UNDERSTAND_OUT : out std_logic;
+    API_SEND_OUT        : out std_logic;
+    ADDRESS_OUT         : out std_logic_vector(15 downto 0);
+    STAT_DEBUG          : out std_logic_vector(15 downto 0)
     );
 end entity;
 
@@ -102,6 +103,7 @@ begin
         elsif CLK_EN = '1' then
           buf_API_READ_OUT <= '1';
           ADDRESS_REJECTED <= '0';
+          DONT_UNDERSTAND_OUT <= '0';
           --recv_set_address    <= '0';
 
           --control sending state
@@ -121,7 +123,7 @@ begin
                   sending_state <= send_uid_1;
                   ram_read_addr1 <= "0000";
                 when SET_ADDRESS => recv_set_address <= '1';
-                when others      => null;
+                when others      => DONT_UNDERSTAND_OUT <= '1';
               end case;
             end if;
             if recv_set_address = '1' then

diff --git a/trb_net16_med_ecp_sfp.vhd b/trb_net16_med_ecp_sfp.vhd
index 8d129c2744ca641f85eb01ae985ab8dcb9c5d2e2..763f8940c672a3ce0175c49eaf3d4921a4e67f44 100644 (file)
--- a/trb_net16_med_ecp_sfp.vhd
+++ b/trb_net16_med_ecp_sfp.vhd
@@ -241,6 +241,9 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is
   signal led_counter          : std_logic_vector(17 downto 0);
   signal rx_led, tx_led       : std_logic;
 
+  signal comb_rx_k            : std_logic_vector(1 downto 0);
+  signal comb_rx_data         : std_logic_vector(15 downto 0);
+
 begin
 
 --------------------------------------------------------------------------
@@ -274,11 +277,26 @@ THE_RX_K_SYNC: signal_sync
   port map(
     RESET    => RESET,
     D_IN     => rx_k,
-    CLK0     => clock,
+    CLK0     => ff_rxhalfclk,
     CLK1     => clock,
     D_OUT    => rx_k_q
     );
 
+THE_RX_SYNC: signal_sync
+  generic map(
+    DEPTH => 2,
+    WIDTH => 18
+    )
+  port map(
+    RESET    => RESET,
+    D_IN(15 downto 0)  => comb_rx_data,
+    D_IN(17 downto 16) => comb_rx_k,
+    CLK0     => ff_rxhalfclk,
+    CLK1     => ff_rxhalfclk,
+    D_OUT(17 downto 16)=> rx_k,
+    D_OUT(15 downto 0) => rx_data
+    );
+
 
 -- "Swap Bytes" indicator
 THE_SWAP_BYTES_PROC: process( clock )
@@ -534,8 +552,8 @@ port map( core_txrefclk        => clock,
       ffc_trst          => '0',
       hdoutp2          => sd_txd_p_out,
       hdoutn2          => sd_txd_n_out,
-      ff_rxdata_ch2        => rx_data,
-      ff_rx_k_cntrl_ch2      => rx_k,
+      ff_rxdata_ch2        => comb_rx_data,
+      ff_rx_k_cntrl_ch2      => comb_rx_k,
       ff_rxfullclk_ch2      => open,
       ff_rxhalfclk_ch2      => ff_rxhalfclk,
       ff_disp_err_ch2      => open,
@@ -606,7 +624,7 @@ fifo_rx_rd_en <= '1';
 THE_BYTE_SWAP_PROC: process( ff_rxhalfclk )
 begin
   if( rising_edge(ff_rxhalfclk) ) then
-    last_rx <= rx_k(1) & rx_data(15 downto 8);
+    last_rx <= rx_k(1) & rx_d(15 downto 8);
     if( swap_bytes = '0' ) then
       fifo_rx_din   <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
       fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);

diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd
index a82fac2e72b3435c26bd3e4224ae49588f790be2..af294598ea938dcedff8e026777ed8eafbbb51e5 100644 (file)
--- a/trb_net16_regIO.vhd
+++ b/trb_net16_regIO.vhd
@@ -110,22 +110,23 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is
       CLK    : in std_logic;
       RESET  : in std_logic;
       CLK_EN : in std_logic;
-      API_DATA_IN       : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
-      API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
-      API_DATAREADY_IN  : in  std_logic;
-      API_READ_OUT      : out std_logic;
-      RAM_DATA_IN       : in  std_logic_vector(15 downto 0);
-      RAM_DATA_OUT      : out std_logic_vector(15 downto 0);
-      RAM_ADDR_IN       : in  std_logic_vector(2 downto 0);
-      RAM_WR_IN         : in  std_logic;
-      API_DATA_OUT      : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
-      API_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0);
-      API_DATAREADY_OUT : out std_logic;
-      API_READ_IN       : in  std_logic;
-      ADDRESS_REJECTED  : out std_logic;
-      API_SEND_OUT      : out std_logic;
-      ADDRESS_OUT       : out std_logic_vector(15 downto 0);
-      STAT_DEBUG        : out std_logic_vector(15 downto 0)
+      API_DATA_IN         : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+      API_PACKET_NUM_IN   : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+      API_DATAREADY_IN    : in  std_logic;
+      API_READ_OUT        : out std_logic;
+      RAM_DATA_IN         : in  std_logic_vector(15 downto 0);
+      RAM_DATA_OUT        : out std_logic_vector(15 downto 0);
+      RAM_ADDR_IN         : in  std_logic_vector(2 downto 0);
+      RAM_WR_IN           : in  std_logic;
+      API_DATA_OUT        : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+      API_PACKET_NUM_OUT  : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+      API_DATAREADY_OUT   : out std_logic;
+      API_READ_IN         : in  std_logic;
+      ADDRESS_REJECTED    : out std_logic;
+      DONT_UNDERSTAND_OUT : out std_logic;
+      API_SEND_OUT        : out std_logic;
+      ADDRESS_OUT         : out std_logic_vector(15 downto 0);
+      STAT_DEBUG          : out std_logic_vector(15 downto 0)
       );
   end component;
 
@@ -190,6 +191,7 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is
   signal ADR_DATAREADY_OUT : std_logic;
   signal ADR_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0);
   signal ADR_REJECTED : std_logic;
+  signal ADR_DONT_UNDERSTAND : std_logic;
   signal buf_API_ERROR_PATTERN_OUT  : std_logic_vector(31 downto 0);
   signal rom_read_addr,buf_rom_read_addr : std_logic_vector(2 downto 0);
   signal rom_read_dout : std_logic_vector(15 downto 0);
@@ -251,6 +253,7 @@ begin
       RAM_ADDR_IN       => IDRAM_ADDR_IN,
       RAM_WR_IN         => IDRAM_WR_IN,
       ADDRESS_REJECTED  => ADR_REJECTED,
+      DONT_UNDERSTAND_OUT => ADR_DONT_UNDERSTAND,
       ADDRESS_OUT       => MY_ADDRESS_OUT,
       STAT_DEBUG        => buf_STAT_ADDR_DEBUG
       );
@@ -346,6 +349,9 @@ begin
           ADR_READ_IN <= API_READ_IN;
           if ADR_REJECTED = '1' then
             next_state <= SEND_REPLY_SHORT_TRANSFER;
+          elsif ADR_DONT_UNDERSTAND = '1' then
+            next_state <= SEND_REPLY_SHORT_TRANSFER;
+            next_dont_understand <= '1';
           elsif ADR_DATAREADY_OUT = '1' and ADR_SEND_OUT = '1' then
             next_state <= ADDRESS_ACK;
           end if;
@@ -353,9 +359,6 @@ begin
         when ADDRESS_ACK =>
           ADR_READ_IN <= API_READ_IN;
           ADR_DATAREADY_IN <= API_DATAREADY_IN;
---           next_API_SEND_OUT <= ADR_SEND_OUT;
---           next_API_DATAREADY_OUT <= ADR_DATAREADY_OUT;
---           next_API_DATA_OUT <= ADR_DATA_OUT;
           if ADR_SEND_OUT = '0' then
             next_state <= SEND_REPLY_DATA_finish;
           end if;