--use work.minmax.all;
--use work.monitor_config.all;
--use debug.fifo32bit;
-
+use work.mathhelpers.all;
entity jtag_cmd_m26c is
generic(
MAX_NUMCHIPS : integer := 7; -- maximum number of chips in this chain controllers chain (because number of chips can be 0, best chose 2^n-1 as maximum to save logic. if memory should be used completely, choose 2^n.)
- MAX_NUMCHIPS_PLUS_ONE_LD : integer := 3; -- LD of value plus one, rounded up, or ld rounded down + 1, because the next binary digit needs one bit more (i.e, 2 needs second bit)
- MAX_NUMCHIPS_LD : integer := 3; -- LD of value, rounded up
- MAX_REGISTERS : integer := 14; -- number of registers per chip. Because of ram3 layout, values of 2^n-2 should be chosen.
- MAX_REGISTERS_LD : integer := 4; -- LD of value, rounded up.
- MAX_REGISTERS_PLUS_ONE_LD : integer := 4; -- LD of (value plus one)
- MAX_REGISTERS_PLUS_TWO_LD : integer := 4; -- LD of (value plus two)
- MAX_REGLEN_LD : integer := 12; -- LD of naximum register length.
- MAX_REGLEN_PLUS_ONE_LD : integer := 12; -- LD of (register length+1)
-
+ MAX_REGISTERS : integer := 14; -- maximum number of registers per chip. Because of ram3 layout, values of 2^n-2 should be chosen.
+ MAX_REGLEN : integer := 4095; -- maximum number of bits for one register. Should be chosen as 2^n-1
WRITE_ERROR_THRESHOLD : integer := 3; -- if at least WRITE_ERROR_THRESHOLD bits are different from written value, count as WRITE_ERROR/DATA_CHANGED.
READ_ERROR_THRESHOLD : integer := 4; -- if at least READ_ERROR_THRESHOLD bits are different from 32 bit ID, set
JTAG_M26_IRLEN : integer := 5; -- length of the instruction register of the connected chips
- JTAG_M26_IRLEN_LD : integer := 3; -- ld of value, rounded up
JTAG_M26_IR_ID_CODE : std_logic_vector(4 downto 0) := "01110"; -- Code selecting DEV_ID register of Mimosa26
JTAG_M26_DEV_ID : std_logic_vector(31 downto 0) := x"4D323601"; -- Mimosa26 DEV_ID, which the sensor should send.
-- GLOBAL_JTAG_COUNTER_BITS : integer := 10; --
JTAG_CHAIN_BROKEN_COUNTER_BITS : integer := 10; -- counter width
JTAG_TDO_EXPECTED_MAXDELAY : integer := 3; -- set range to 0..value for delay of expected TDO value
- JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD : integer := 2; -- ceil of ld( value plus one)
RESET_WAIT_DURATION : unsigned := "10000000" -- 128 clock cycles at 100 mhz
);
port(
architecture arch_cmd_m26c of jtag_cmd_m26c is
+constant MAX_NUMCHIPS_PLUS_ONE_LD : integer := log2_ceil(MAX_NUMCHIPS+1); -- LD of value plus one, rounded up, or ld rounded down + 1, because the next binary digit needs one bit more (i.e, 2 needs second bit)
+constant MAX_NUMCHIPS_LD : integer := log2_ceil(MAX_NUMCHIPS); -- LD of value, rounded up
+constant MAX_REGISTERS_LD : integer := log2_ceil(MAX_REGISTERS); -- LD of value, rounded up.
+constant MAX_REGISTERS_PLUS_ONE_LD : integer := log2_ceil(MAX_REGISTERS+1); -- LD of (value plus one)
+constant MAX_REGISTERS_PLUS_TWO_LD : integer := log2_ceil(MAX_REGISTERS+2); -- LD of (value plus two)
+constant MAX_REGLEN_LD : integer := log2_ceil(MAX_REGLEN); -- LD of naximum register length.
+constant MAX_REGLEN_PLUS_ONE_LD : integer := log2_ceil(MAX_REGLEN+1); -- LD of (register length+1)
+constant JTAG_M26_IRLEN_LD : integer := log2_ceil(JTAG_M26_IRLEN); -- ld of value, rounded up
+constant JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD : integer := log2_ceil(JTAG_TDO_EXPECTED_MAXDELAY+1); -- ceil of ld( value plus one)
-- component fifo32bit IS
-- port (
-- clk: IN std_logic;