Maybe fixing the Baseline follower

diff --git a/ADC/source/adc_handler.vhd b/ADC/source/adc_handler.vhd
index 2de252c4ab14c4fdc768f72a5414eef9277b6a27..dccabd504871d4d896aec2d4341cd06792d64c21 100644 (file)
--- a/ADC/source/adc_handler.vhd
+++ b/ADC/source/adc_handler.vhd
@@ -507,9 +507,9 @@ begin
             when x"1c" => BUS_TX.data(1 downto 0)              <= std_logic_vector(to_unsigned(config_cfd.DebugMode, 2));
             when x"1d" =>
               BUS_TX.data(7 downto 0)   <= std_logic_vector(config_cfd.IntegrateWindow);
-              BUS_TX.data(12 downto 8)  <= std_logic_vector(config_cfd.CFDDelay);
-              BUS_TX.data(16 downto 13) <= std_logic_vector(config_cfd.CFDMult);
-              BUS_TX.data(20 downto 17) <= std_logic_vector(config_cfd.CFDMultDly);
+              BUS_TX.data(12 downto 8)  <= std_logic_vector(resize(config_cfd.CFDDelay,5));
+              BUS_TX.data(16 downto 13) <= std_logic_vector(resize(config_cfd.CFDMult,4));
+              BUS_TX.data(20 downto 17) <= std_logic_vector(resize(config_cfd.CFDMultDly,4));
             when others =>
               BUS_TX.ack     <= '0';
               BUS_TX.unknown <= '1';
@@ -555,9 +555,9 @@ begin
             when x"1c" => config_cfd.DebugMode                    <= to_integer(unsigned(BUS_RX.data(1 downto 0)));  
             when x"1d" =>
               config_cfd.IntegrateWindow <= unsigned(BUS_RX.data(7 downto 0));
-              config_cfd.CFDDelay        <= unsigned(BUS_RX.data(12 downto 8));
-              config_cfd.CFDMult         <= unsigned(BUS_RX.data(16 downto 13));
-              config_cfd.CFDMultDly      <= unsigned(BUS_RX.data(20 downto 17));
+              config_cfd.CFDDelay        <= resize(unsigned(BUS_RX.data(12 downto  8)), config_cfd.CFDDelay'length);
+              config_cfd.CFDMult         <= resize(unsigned(BUS_RX.data(16 downto 13)), config_cfd.CFDMult'length);
+              config_cfd.CFDMultDly      <= resize(unsigned(BUS_RX.data(20 downto 17)), config.CFDMult'length);
             when others => BUS_TX.ack    <= '0';
               BUS_TX.unknown             <= '1';
           end case;

diff --git a/ADC/source/adc_package.vhd b/ADC/source/adc_package.vhd
index cfd39ca28f319edc5851df851215ad43f88c8e36..f8321526686abb756b20b94701fc071438330c04 100644 (file)
--- a/ADC/source/adc_package.vhd
+++ b/ADC/source/adc_package.vhd
@@ -50,9 +50,9 @@ package adc_package is
     PolarityInvert   : std_logic;
     BaselineAverage  : unsigned(4 downto 0);
     BaselineAlwaysOn : std_logic;
-    CFDDelay         : unsigned(4 downto 0);
-    CFDMult          : unsigned(3 downto 0);
-    CFDMultDly       : unsigned(3 downto 0);
+    CFDDelay         : unsigned(2 downto 0);
+    CFDMult          : unsigned(2 downto 0);
+    CFDMultDly       : unsigned(2 downto 0);
     IntegrateWindow  : unsigned(7 downto 0);
     TriggerDelay     : unsigned(11 downto 0);
     CheckWord1       : std_logic_vector(RESOLUTION - 1 downto 0);

diff --git a/ADC/source/adc_processor_cfd_ch.vhd b/ADC/source/adc_processor_cfd_ch.vhd
index aee508cf97b6a1f4b35c91ed47430780b52f7850..c7878a1994ede010e5d459d96e7a6dd57cc6da0c 100644 (file)
--- a/ADC/source/adc_processor_cfd_ch.vhd
+++ b/ADC/source/adc_processor_cfd_ch.vhd
@@ -35,7 +35,7 @@ architecture arch of adc_processor_cfd_ch is
   constant RESOLUTION_CFD  : integer := RESOLUTION_PROD + 1; -- this should be 16 to fit into the readout ram
 
   constant RESOLUTION_BASEAVG : integer := RESOLUTION + 2 ** CONF.BaselineAverage'length - 1;
-  constant LENGTH_BASEDLY     : integer := 32; -- longer than typical pulses?
+  constant LENGTH_BASEDLY     : integer := 128; -- longer than typical pulses?
   constant LENGTH_CFDDLY      : integer := 2 ** CONF.CFDDelay'length;
   constant LENGTH_INTDLY      : integer := 3;  -- must match CFD/zeroX calculation chain