add missing changes to control signals

diff --git a/media_interfaces/med_ecp5_sfp_sync_2.vhd b/media_interfaces/med_ecp5_sfp_sync_2.vhd
index aee845356c9831c9ae73125324020a10f7239d5c..5a7d72331cfabbbd2016f426249f0280c912d9e9 100644 (file)
--- a/media_interfaces/med_ecp5_sfp_sync_2.vhd
+++ b/media_interfaces/med_ecp5_sfp_sync_2.vhd
@@ -133,7 +133,6 @@ end generate;
 --   clk_200_i        <= clk_200_internal;
 -- end generate;
 
-
 -------------------------------------------------      
 -- Serdes
 -------------------------------------------------      
@@ -195,7 +194,7 @@ THE_SERDES : entity work.dual_serdes
         serdes1_rxrefclk          => CLK_INTERNAL_FULL,
         serdes1_rx_serdes_rst_c   => rx_serdes_rst(1),
         serdes1_serdes_rst_dual_c => '0',
-        serdes1_signal_detect_c   => '0',
+        serdes1_signal_detect_c   => signal_detect_i,
         serdes1_txdata            => tx_data(1),
         serdes1_tx_disp_sel(0)    => '0',
         serdes1_tx_force_disp(0)  => '0',
@@ -284,7 +283,7 @@ THE_SERDES : entity work.dual_serdes_1
         serdes1_rxrefclk          => CLK_INTERNAL_FULL,
         serdes1_rx_serdes_rst_c   => rx_serdes_rst(1),
         serdes1_serdes_rst_dual_c => '0',
-        serdes1_signal_detect_c   => '0',
+        serdes1_signal_detect_c   => signal_detect_i,
         serdes1_txdata            => tx_data(1),
         serdes1_tx_disp_sel(0)    => '0',
         serdes1_tx_force_disp(0)  => '0',

diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd
index dfbc73a050eb7ff397ea34cebbdaad5fad5a31a1..c1ce4e2fb2059138a52d3d4217371dc52dcd6238 100644 (file)
--- a/media_interfaces/sync/med_sync_control.vhd
+++ b/media_interfaces/sync/med_sync_control.vhd
@@ -421,6 +421,8 @@ DEBUG_OUT(8)  <= rx_serdes_rst_i;
 DEBUG_OUT(9)  <= finished_reset_rx;
 DEBUG_OUT(10) <= finished_reset_tx;
 DEBUG_OUT(11) <= reset_i;
-DEBUG_OUT(31 downto 12) <= (others => '0');
+DEBUG_OUT(12) <= CLEAR;
+DEBUG_OUT(16 downto 13) <= rx_fsm_state;
+DEBUG_OUT(31 downto 17) <= (others => '0');
 
 end architecture;