signal flag_half_full : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
signal flag_almost_full_combined : std_logic;
signal flag_half_full_combined : std_logic;
-
+ signal tmg_trg_error_i : std_logic;
begin
end generate;
- header_buffer_data_in <= "000000" & TMG_TRG_ERROR_IN & LVL1_TRG_INFO_IN(0) & LVL1_TRG_TYPE_IN & LVL1_TRG_CODE_IN & LVL1_TRG_NUMBER_IN;
+ header_buffer_data_in <= "000000" & tmg_trg_error_i & LVL1_TRG_INFO_IN(0) & LVL1_TRG_TYPE_IN & LVL1_TRG_CODE_IN & LVL1_TRG_NUMBER_IN;
+
+process(CLOCK)
+ begin
+ if rising_edge(CLOCK) then
+ tmg_trg_error_i <= (TMG_TRG_ERROR_IN or tmg_trg_error_i) and not header_buffer_write;
+ end if;
+ end process;
---------------------------------------------------------------------------
);
+
+
---------------------------------------------------------------------------
-- Length FIFO
---------------------------------------------------------------------------
current_state <= next_state;
error_not_found <= next_error_not_found;
error_missing <= next_error_missing;
+ error_lvl1 <= next_error_lvl1;
lvl1_fifo_read <= next_lvl1_fifo_read;
hdr_fifo_read <= next_hdr_fifo_read;
ipu_finished_i <= next_ipu_finished_i;
if rising_edge(CLK) then
case to_integer(unsigned(HUB_CTRL_TIMEOUT_TIME(k*4+3 downto k*4))) is
when 0 => current_timeout_value(k) <= std_logic_vector(to_unsigned(0,16));
- when 1 => current_timeout_value(k) <= std_logic_vector(to_unsigned(64,16) - unsigned(hub_level&'0'));
- when 2 => current_timeout_value(k) <= std_logic_vector(to_unsigned(128,16) - unsigned(hub_level&'0'));
- when 3 => current_timeout_value(k) <= std_logic_vector(to_unsigned(256,16) - unsigned(hub_level&'0'));
+ when 1 => current_timeout_value(k) <= std_logic_vector(to_unsigned(128,16) - unsigned(hub_level&'0'));
+ when 2 => current_timeout_value(k) <= std_logic_vector(to_unsigned(256,16) - unsigned(hub_level&'0'));
+ when 3 => current_timeout_value(k) <= std_logic_vector(to_unsigned(512,16) - unsigned(hub_level&'0'));
when 4 => current_timeout_value(k) <= std_logic_vector(to_unsigned(1024,16) - unsigned(hub_level&'0'));
when 5 => current_timeout_value(k) <= std_logic_vector(to_unsigned(2048,16) - unsigned(hub_level&'0'));
when 6 => current_timeout_value(k) <= std_logic_vector(to_unsigned(4096,16) - unsigned(hub_level&'0'));
--Timeouts 88-8B
if reg_STROBES(8) = '1' then
HC_STAT_REGS(8*32+31 downto 8*32) <= (others => '0');
- else
+ elsif combined_resync = '0' and reset_i = '0' then
HC_STAT_REGS(8*32+31 downto 8*32) <= STAT_TIMEOUT(0*32+31 downto 0*32) or HC_STAT_REGS(8*32+31 downto 8*32);
end if;
if reg_STROBES(9) = '1' then
HC_STAT_REGS(9*32+31 downto 9*32) <= (others => '0');
- else
+ elsif combined_resync = '0' and reset_i = '0' then
HC_STAT_REGS(9*32+31 downto 9*32) <= STAT_TIMEOUT(1*32+31 downto 1*32) or HC_STAT_REGS(9*32+31 downto 9*32);
end if;
if reg_STROBES(10) = '1' then
HC_STAT_REGS(10*32+31 downto 10*32) <= (others => '0');
- else
+ elsif combined_resync = '0' and reset_i = '0' then
HC_STAT_REGS(10*32+31 downto 10*32) <= STAT_TIMEOUT(2*32+31 downto 2*32) or HC_STAT_REGS(10*32+31 downto 10*32);
end if;
if reg_STROBES(11) = '1' then
HC_STAT_REGS(11*32+31 downto 11*32) <= (others => '0');
- else
+ elsif combined_resync = '0' and reset_i = '0' then
HC_STAT_REGS(11*32+31 downto 11*32) <= STAT_TIMEOUT(3*32+31 downto 3*32) or HC_STAT_REGS(11*32+31 downto 11*32);
end if;
begin
if rising_edge(CLK) then
connection_timed_out(i) <= '0';
- if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0'
+ if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or got_trm(i) = '1'
or locking_point(i) = '1' or reg_CTRL_TIMEOUT_TIME = 0 then
timeout_counter(i) <= (others => '0');
elsif timeout_counter(i) = reg_CTRL_TIMEOUT_TIME then
end generate;
-
----------------------------------
--saving (D)HDR
----------------------------------
begin
if rising_edge(CLK) then
connection_timed_out(i) <= '0';
- if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0'
+ if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or got_trm(i) = '1'
or locking_point(i) = '1' or reg_CTRL_TIMEOUT_TIME = 0 then
timeout_counter(i) <= (others => '0');
elsif timeout_counter(i) = reg_CTRL_TIMEOUT_TIME then
connection_timed_out(i) <= '1';
- elsif timer_ms_tick = '1' and INIT_READ_IN(i) = '0' and INIT_DATAREADY_OUT(i) = '1' then
- timeout_counter(i) <= timeout_counter(i) + to_unsigned(2,2);
- elsif timer_ms_tick = '1' and REPLY_POOL_next_read = '1' and got_trm(i) = '0' then
+-- elsif timer_ms_tick = '1' and INIT_READ_IN(i) = '0' and INIT_DATAREADY_OUT(i) = '1' then
+-- timeout_counter(i) <= timeout_counter(i) + to_unsigned(2,2);
+ elsif timer_ms_tick = '1' and ((REPLY_POOL_next_read = '1' and got_trm(i) = '0')
+ or (INIT_READ_IN(i) = '0' and INIT_DATAREADY_OUT(i) = '1')) then
timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1);
end if;
end if;
output_tmp <= '0';
recv_bit <= '0';
strong_pullup <= '0';
+ state <= START;
else
recv_bit_ready <= next_recv_bit_ready;
state <= next_state;