vcd dumpfile vcdfile.vcd
vcd dumpvars -m /APL1/
vcd dumpvars -m /API1/ACTIVE_API/
+vcd dumpvars -m /API1/ACTIVE_API/INIT_SBUF/
vcd dumpvars -m /API1/ACTIVE_API/FIFO_TO_INT/
vcd dumpvars -m /API1/IOBUF/
vcd dumpvars -m /API1/IOBUF/INITOBUF/
vcd dumpvars -m /API1/IOBUF/REPLYIBUF/
vcd dumpvars -m /API2/IOBUF/INITIBUF/
+vcd dumpvars -m /API2/IOBUF/INITOBUF/
vcd dumpvars -m /API2/ACTIVE_API/
run 5000 ns
quit
\ No newline at end of file
-[size] 1272 937
+[size] 1272 936
[pos] -1 -1
-*-28.799541 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-25.799541 160100000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
@200
-DUMMY_APL
-@29
-trb_net_dummy_apl_apibuf_testbench.APL1.apl_write_out
@28
+trb_net_dummy_apl_apibuf_testbench.APL1.apl_write_out
trb_net_dummy_apl_apibuf_testbench.APL1.apl_fifo_full_in
@22
#apl_data_out[47:0] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[47] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[46] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[45] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[44] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[43] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[42] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[41] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[40] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[39] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[38] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[37] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[36] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[35] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[34] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[33] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[32] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[31] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[30] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[29] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[28] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[27] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[26] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[25] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[24] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[23] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[22] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[21] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[20] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[19] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[18] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[17] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[16] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[15] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[14] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[13] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[12] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[11] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[10] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[9] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[8] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[7] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[6] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[5] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[4] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[3] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[2] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[1] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[0]
@28
#apl_typ_in[2:0] trb_net_dummy_apl_apibuf_testbench.APL1.apl_typ_in[2] trb_net_dummy_apl_apibuf_testbench.APL1.apl_typ_in[1] trb_net_dummy_apl_apibuf_testbench.APL1.apl_typ_in[0]
trb_net_dummy_apl_apibuf_testbench.APL1.apl_dataready_in
+trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.apl_dataready_out
@22
#apl_seqnr_in[7:0] trb_net_dummy_apl_apibuf_testbench.APL1.apl_seqnr_in[7] trb_net_dummy_apl_apibuf_testbench.APL1.apl_seqnr_in[6] trb_net_dummy_apl_apibuf_testbench.APL1.apl_seqnr_in[5] trb_net_dummy_apl_apibuf_testbench.APL1.apl_seqnr_in[4] trb_net_dummy_apl_apibuf_testbench.APL1.apl_seqnr_in[3] trb_net_dummy_apl_apibuf_testbench.APL1.apl_seqnr_in[2] trb_net_dummy_apl_apibuf_testbench.APL1.apl_seqnr_in[1] trb_net_dummy_apl_apibuf_testbench.APL1.apl_seqnr_in[0]
@200
#int_init_data_out[50:0] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[50] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[49] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[48] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[47] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[46] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[45] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[44] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[43] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[42] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[41] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[40] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[39] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[38] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[37] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[36] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[35] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[34] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[33] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[32] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[31] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[30] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[29] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[28] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[27] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[26] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[25] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[24] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[23] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[22] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[21] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[20] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[19] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[18] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[17] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[16] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[15] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[14] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[13] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[12] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[11] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[10] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[9] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[8] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[7] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[6] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[5] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[4] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[3] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[2] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[1] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[0]
@28
trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_read
+@22
+#fifo_to_int_data_out[47:0] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[47] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[46] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[45] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[44] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[43] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[42] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[41] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[40] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[39] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[38] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[37] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[36] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[35] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[34] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[33] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[32] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[31] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[30] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[29] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[28] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[27] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[26] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[25] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[24] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[23] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[22] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[21] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[20] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[19] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[18] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[17] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[16] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[15] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[14] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[13] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[12] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[11] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[10] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[9] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[8] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[7] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[6] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[5] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[4] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[3] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[2] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[1] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_data_out[0]
+@28
+trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.sbuf_free
+trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_read_in
+trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.INIT_SBUF.syn_read_in
+trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.INIT_SBUF.comb_read_in
+trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.INIT_SBUF.comb_dataready_in
+trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.INIT_SBUF.next_next_read_out
+trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.INIT_SBUF.current_next_read_out
+trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.INIT_SBUF.syn_dataready_out
+trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.INIT_SBUF.next_got_overflow
@200
+-
-IOBUF
@22
#stat_locked[31:0] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[31] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[30] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[29] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[28] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[27] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[26] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[25] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[24] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[23] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[22] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[21] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[20] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[19] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[18] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[17] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[16] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[15] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[14] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[13] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[12] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[11] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[10] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[9] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[8] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[7] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[6] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[5] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[4] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[3] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[2] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[1] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.stat_locked[0]
#transmitted_buffers[1:0] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.transmitted_buffers[1] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.transmitted_buffers[0]
@22
#stat_locked[15:0] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[15] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[14] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[13] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[12] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[11] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[10] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[9] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[8] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[7] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[6] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[5] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[4] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[3] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[2] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[1] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.stat_locked[0]
+#current_output_buffer[50:0] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[50] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[49] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[48] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[47] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[46] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[45] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[44] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[43] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[42] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[41] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[40] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[39] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[38] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[37] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[36] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[35] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[34] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[33] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[32] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[31] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[30] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[29] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[28] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[27] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[26] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[25] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[24] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[23] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[22] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[21] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[20] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[19] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[18] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[17] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[16] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[15] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[14] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[13] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[12] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[11] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[10] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[9] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[8] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[7] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[6] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[5] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[4] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[3] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[2] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[1] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.current_output_buffer[0]
+@28
+trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.sent_eob
+trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.sent_ack
+trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.send_ack_in
+trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.int_read_out
+trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.int_dataready_in
+trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.comb_next_read
@200
-
-IBUF (Rec)
#fifo_data_out[50:0] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[50] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[49] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[48] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[47] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[46] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[45] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[44] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[43] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[42] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[41] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[40] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[39] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[38] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[37] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[36] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[35] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[34] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[33] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[32] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[31] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[30] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[29] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[28] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[27] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[26] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[25] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[24] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[23] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[22] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[21] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[20] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[19] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[18] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[17] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[16] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[15] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[14] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[13] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[12] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[11] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[10] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[9] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[8] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[7] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[6] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[5] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[4] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[3] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[2] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[1] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[0]
#int_data_out[50:0] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[50] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[49] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[48] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[47] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[46] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[45] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[44] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[43] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[42] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[41] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[40] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[39] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[38] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[37] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[36] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[35] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[34] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[33] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[32] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[31] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[30] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[29] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[28] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[27] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[26] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[25] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[24] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[23] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[22] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[21] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[20] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[19] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[18] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[17] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[16] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[15] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[14] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[13] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[12] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[11] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[10] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[9] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[8] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[7] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[6] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[5] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[4] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[3] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[2] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[1] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[0]
@28
-trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.reg_int_dataready_out
trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.reg_eob_out
@22
#stat_buffer[31:0] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[31] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[30] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[29] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[28] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[27] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[26] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[25] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[24] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[23] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[22] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[21] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[20] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[19] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[18] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[17] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[16] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[15] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[14] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[13] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[12] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[11] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[10] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[9] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[8] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[7] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[6] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[5] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[4] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[3] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[2] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[1] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_buffer[0]
trb_net_dummy_apl_apibuf_testbench.API2.ACTIVE_API.int_reply_read_in
@22
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+@28
+trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.INIT_SBUF.next_got_overflow
--by the media (via the TrbNetIOMultiplexer)
MED_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
MED_INIT_READ_IN: in STD_LOGIC; -- Media is reading
- MED_INIT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
MED_INIT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
-- (the IOBUF MUST read)
--by the media (via the TrbNetIOMultiplexer)
MED_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
MED_REPLY_READ_IN: in STD_LOGIC; -- Media is reading
- MED_REPLY_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
MED_REPLY_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
-- (the IOBUF MUST read)
TARGET_ADDRESS => x"0002",
-- TARGET_ADDRESS => x"000f",
PREFILL_LENGTH => 0,
- TRANSFER_LENGTH => 4)
+-- TRANSFER_LENGTH => 2)
+ TRANSFER_LENGTH => 16)
port map (
CLK => clk,
RESET => reset,
API2: trb_net_active_apibuf
generic map (
- FIFO_TERM_BUFFER_DEPTH => 0)
+ FIFO_TERM_BUFFER_DEPTH => 3)
port map (
CLK => clk,
RESET => reset,
-- quit
-- isimwave isimwavedata.xwv
-
+-- gtkwave vcdfile.vcd settings_aplbuf.sav &
vhdl work "../trb_net_fifo.vhd"
vhdl work "../xilinx/trb_net_fifo_arch.vhd"
vhdl work "../xilinx/shift_lut_x16.vhd"
+vhdl work "../trb_net_sbuf.vhd"
vhdl work "../trb_net_ibuf.vhd"
vhdl work "../trb_net_obuf.vhd"
vhdl work "../trb_net_iobuf.vhd"
end component;
+ component trb_net_sbuf is
+
+ generic (DATA_WIDTH : integer := 56);
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- port to combinatorial logic
+ COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
+ COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
+ COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ -- Port to synchronous output.
+ SYN_DATAREADY_OUT: out STD_LOGIC;
+ SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ SYN_READ_IN: in STD_LOGIC;
+ -- Status and control port
+ STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0);
+ CTRL_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
+ );
+ END component;
+
-- signals for the APL to INT fifo:
signal fifo_to_int_data_in : std_logic_vector(47 downto 0);
signal fifo_to_int_write : std_logic;
signal tb_registered_target, tb_next_registered_target: std_logic_vector(15 downto 0);
signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0);
-signal next_INT_INIT_DATA_OUT, reg_INT_INIT_DATA_OUT: std_logic_vector(50 downto 0);
-signal next_INT_INIT_DATAREADY_OUT, reg_INT_INIT_DATAREADY_OUT: std_logic;
+signal next_INT_INIT_DATA_OUT: std_logic_vector(50 downto 0);
+signal next_INT_INIT_DATAREADY_OUT: std_logic;
+signal sbuf_free, sbuf_next_READ: std_logic;
signal next_INT_REPLY_READ_OUT, reg_INT_REPLY_READ_OUT: std_logic;
signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic;
signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(47 downto 0);
end process;
-
-
+INIT_SBUF: trb_net_sbuf
+ generic map (DATA_WIDTH => 51)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ COMB_DATAREADY_IN => next_INT_INIT_DATAREADY_OUT,
+ COMB_next_READ_OUT => sbuf_next_READ,
+ COMB_READ_IN => '1',
+ COMB_DATA_IN => next_INT_INIT_DATA_OUT,
+ SYN_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,
+ SYN_DATA_OUT => INT_INIT_DATA_OUT,
+ SYN_READ_IN => INT_INIT_READ_IN,
+ CTRL_BUFFER => (others => '0')
+ );
+
+sbuf_free <= sbuf_next_READ or INT_INIT_READ_IN; --sbuf killed in next cycle
+
-- combinatorial part of state machine
STATE_COMB : process(current_state, APL_SEND_IN, combined_header, INT_INIT_READ_IN,
APL_WRITE_IN, fifo_to_int_empty, next_registered_header, registered_header,
- reg_INT_INIT_DATA_OUT, reg_INT_INIT_DATA_OUT,
fifo_to_int_data_out, combined_trailer,
next_registered_trailer, fifo_to_int_data_out, fifo_to_apl_empty,
INT_REPLY_DATAREADY_IN, reg_INT_REPLY_READ_OUT,fifo_to_apl_read,
reg_APL_DATAREADY_OUT, fifo_to_apl_data_out, reg_APL_DATAREADY_OUT,
- APL_READ_IN)
+ APL_READ_IN, sbuf_free)
begin -- process
next_state <= MY_ERROR;
next_registered_header <= registered_header;
-- SEND_HEADER
-------------------------------------------------------------------------------
elsif current_state = SEND_HEADER then
- if INT_INIT_READ_IN = '1' then -- kill current header
+ if sbuf_free = '1' then -- kill current header
next_state <= RUNNING;
if fifo_to_int_empty = '1' then
next_INT_INIT_DATAREADY_OUT <= '0';
end if; -- fifo_to_int_empty
else
next_state <= SEND_HEADER;
- next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_HDR;
- next_INT_INIT_DATA_OUT(DWORD_POSITION) <= registered_header;
- next_INT_INIT_DATAREADY_OUT <= '1';
end if;
-------------------------------------------------------------------------------
-- RUNNING
else
next_state <= SHUTDOWN;
next_registered_trailer <= combined_trailer;
- if fifo_to_int_empty = '0' then
+ if sbuf_free = '1' then
-- data words have to be prepared
next_INT_INIT_DATAREADY_OUT <= '1';
next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT;
next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out;
- if INT_INIT_READ_IN = '1' and reg_INT_INIT_DATAREADY_OUT = '1' then
- fifo_to_int_read <= '1';
- else
- fifo_to_int_read <= '0';
- -- but keep the old content
- next_INT_INIT_DATA_OUT <= reg_INT_INIT_DATA_OUT;
- end if;
+ fifo_to_int_read <= '1';
end if; -- fifo_to_int_empty = '0'
end if;
else -- APL_SEND_IN: still running
next_state <= RUNNING;
- if fifo_to_int_empty = '0' then
+ if fifo_to_int_empty = '0' and sbuf_free = '1' then
-- data words have to be prepared
next_INT_INIT_DATAREADY_OUT <= '1';
next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT;
next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out;
- if INT_INIT_READ_IN = '1' and reg_INT_INIT_DATAREADY_OUT = '1' then
- fifo_to_int_read <= '1';
- else
- fifo_to_int_read <= '0';
- -- but keep the old content
- next_INT_INIT_DATA_OUT <= reg_INT_INIT_DATA_OUT;
- end if;
+ fifo_to_int_read <= '1';
end if; -- fifo_to_int_empty = '0'
end if;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
elsif current_state = SHUTDOWN then
next_state <= SHUTDOWN;
- if fifo_to_int_empty = '0' then
+ if fifo_to_int_empty = '0' and sbuf_free = '1' then
-- data words have to be prepared
next_INT_INIT_DATAREADY_OUT <= '1';
next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT;
next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out;
- if INT_INIT_READ_IN = '1' and reg_INT_INIT_DATAREADY_OUT = '1' then
- fifo_to_int_read <= '1';
- else
- fifo_to_int_read <= '0';
- -- but keep the old content
- next_INT_INIT_DATA_OUT <= reg_INT_INIT_DATA_OUT;
- end if;
- elsif INT_INIT_READ_IN = '1' and reg_INT_INIT_DATAREADY_OUT = '1' then
+ fifo_to_int_read <= '1';
+ elsif sbuf_free = '1' then
-- we are done
next_state <= SEND_TRAILER;
next_INT_INIT_DATAREADY_OUT <= '1';
next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM;
next_INT_INIT_DATA_OUT(DWORD_POSITION) <= registered_trailer;
- else
- -- but keep the old content
- next_INT_INIT_DATA_OUT <= reg_INT_INIT_DATA_OUT;
- next_INT_INIT_DATAREADY_OUT <= reg_INT_INIT_DATAREADY_OUT;
end if;
-------------------------------------------------------------------------------
-- SEND_TRAILER
-------------------------------------------------------------------------------
elsif current_state = SEND_TRAILER then
- if INT_INIT_READ_IN = '1' then -- kill current trailer
+ if sbuf_free = '1' then -- kill current trailer
next_state <= WAITING;
next_INT_INIT_DATAREADY_OUT <= '0';
else
next_state <= SEND_TRAILER;
- next_INT_INIT_DATAREADY_OUT <= '1';
- next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM;
- next_INT_INIT_DATA_OUT(DWORD_POSITION) <= registered_trailer;
end if;
-------------------------------------------------------------------------------
-- WAITING => for the answer
else '0';
APL_FIFO_FULL_OUT <= fifo_to_int_full; -- APL has to stop writing
- INT_INIT_DATA_OUT <= reg_INT_INIT_DATA_OUT; -- registered output for
- -- internal port
- INT_INIT_DATAREADY_OUT <= reg_INT_INIT_DATAREADY_OUT;
+
INT_REPLY_READ_OUT <= reg_INT_REPLY_READ_OUT;
if rising_edge(CLK) then
if RESET = '1' then
sequence_counter <= (others => '0');
- reg_INT_INIT_DATA_OUT <= (others => '0');
- reg_INT_INIT_DATAREADY_OUT <= '0';
+-- reg_INT_INIT_DATA_OUT <= (others => '0');
+-- reg_INT_INIT_DATAREADY_OUT <= '0';
reg_INT_REPLY_READ_OUT <= '0';
-- reg_APL_DATAREADY_OUT <= '0';
-- reg_APL_DATA_OUT <= (others => '0');
tb_registered_target <= ILLEGAL_ADRESS;
elsif CLK_EN = '1' then
sequence_counter <= next_sequence_counter;
- reg_INT_INIT_DATA_OUT <= next_INT_INIT_DATA_OUT;
- reg_INT_INIT_DATAREADY_OUT <= next_INT_INIT_DATAREADY_OUT;
+-- reg_INT_INIT_DATA_OUT <= next_INT_INIT_DATA_OUT;
+-- reg_INT_INIT_DATAREADY_OUT <= next_INT_INIT_DATAREADY_OUT;
reg_INT_REPLY_READ_OUT <= next_INT_REPLY_READ_OUT;
-- reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT;
-- reg_APL_DATA_OUT <= next_APL_DATA_OUT;
else
sequence_counter <= sequence_counter;
- reg_INT_INIT_DATA_OUT <= reg_INT_INIT_DATA_OUT;
- reg_INT_INIT_DATAREADY_OUT <= reg_INT_INIT_DATAREADY_OUT;
+-- reg_INT_INIT_DATA_OUT <= reg_INT_INIT_DATA_OUT;
+-- reg_INT_INIT_DATAREADY_OUT <= reg_INT_INIT_DATAREADY_OUT;
reg_INT_REPLY_READ_OUT <= reg_INT_REPLY_READ_OUT;
-- reg_APL_DATAREADY_OUT <= reg_APL_DATAREADY_OUT;
-- reg_APL_DATA_OUT <= reg_APL_DATA_OUT;
end component;
+ component trb_net_sbuf is
+
+ generic (DATA_WIDTH : integer := 56);
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- port to combinatorial logic
+ COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
+ COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
+ COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ -- Port to synchronous output.
+ SYN_DATAREADY_OUT: out STD_LOGIC;
+ SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ SYN_READ_IN: in STD_LOGIC;
+ -- Status and control port
+ STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0);
+ CTRL_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
+ );
+ END component;
+
signal fifo_data_in : std_logic_vector(50 downto 0);
signal fifo_data_out : std_logic_vector(50 downto 0);
signal fifo_write, fifo_read : std_logic;
--arrived
signal is_locked, got_locked,release_locked : std_logic;
signal got_eob_out, reg_eob_out: std_logic;
-signal tmp_INT_DATAREADY_OUT, reg_INT_DATAREADY_OUT: std_logic;
-signal tmp_INT_DATA_OUT, reg_INT_DATA_OUT: std_logic_vector(50 downto 0);
+signal sbuf_free, comb_next_read: std_logic;
+signal tmp_INT_DATAREADY_OUT: std_logic;
+signal tmp_INT_DATA_OUT: std_logic_vector(50 downto 0);
signal current_last_header, next_last_header : std_logic_vector(50 downto 0);
type ERROR_STATE is (IDLE, GOT_OVERFLOW_ERROR, GOT_LOCKED_ERROR, GOT_UNDEFINED_ERROR);
-
-
+ SBUF: trb_net_sbuf
+ generic map (DATA_WIDTH => 51)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ COMB_DATAREADY_IN => tmp_INT_DATAREADY_OUT,
+ COMB_next_READ_OUT => comb_next_read,
+ COMB_READ_IN => '1',
+ COMB_DATA_IN => tmp_INT_DATA_OUT,
+ SYN_DATAREADY_OUT => INT_DATAREADY_OUT,
+ SYN_DATA_OUT => INT_DATA_OUT,
+ SYN_READ_IN => INT_READ_IN,
+ CTRL_BUFFER => (others => '0')
+ );
+
+ sbuf_free <= comb_next_read or INT_READ_IN; --sbuf killed
-- this process controls what will be forwarded to the internal point
- DATA_OUT : process (INT_HEADER_IN, fifo_data_out, reg_INT_DATA_OUT,
+ DATA_OUT : process (INT_HEADER_IN, fifo_data_out,
current_last_header, tmp_INT_DATAREADY_OUT, INT_READ_IN,
- reg_INT_DATAREADY_OUT, release_locked, is_locked)
+ release_locked, is_locked, sbuf_free, fifo_empty)
begin
- tmp_INT_DATA_OUT <= reg_INT_DATA_OUT;
- tmp_INT_DATAREADY_OUT <= reg_INT_DATAREADY_OUT;
+ tmp_INT_DATA_OUT <= (others => '1');
+ tmp_INT_DATAREADY_OUT <= '0';
got_eob_out <= '0';
fifo_read <= '0';
got_locked <= is_locked;
next_last_header <= current_last_header;
if fifo_empty = '0' then
- if (INT_READ_IN = '1' and reg_INT_DATAREADY_OUT = '1') or reg_INT_DATAREADY_OUT = '0' then
+ if sbuf_free = '1' and fifo_data_out(TYPE_POSITION) = TYPE_DAT then
-- next data word can be registered
tmp_INT_DATA_OUT <= fifo_data_out;
tmp_INT_DATAREADY_OUT <= '1';
fifo_read <= '1';
- if fifo_data_out(TYPE_POSITION) = TYPE_TRM then
- got_eob_out <= '1';
- if release_locked = '0' then
- got_locked <= '1';
- end if;
- elsif (fifo_data_out(TYPE_POSITION) = TYPE_EOB) then
- fifo_read <= '1';
- got_eob_out <= '1';
- tmp_INT_DATAREADY_OUT <= '0';
- -- this should happen only one CLK cycle
- else -- no TRM, normal read
- got_eob_out <= '0';
-
- if fifo_data_out(TYPE_POSITION) = TYPE_HDR then
- next_last_header <= fifo_data_out;
- end if;
+ elsif sbuf_free = '1' and fifo_data_out(TYPE_POSITION) = TYPE_TRM then
+ got_eob_out <= '1'; --exactly when buffer is killed
+ tmp_INT_DATA_OUT <= fifo_data_out;
+ tmp_INT_DATAREADY_OUT <= '1';
+ if release_locked = '0' then
+ got_locked <= '1';
end if;
- elsif (fifo_data_out(TYPE_POSITION) = TYPE_EOB) then
+ fifo_read <= '1';
+ elsif sbuf_free = '1' and fifo_data_out(TYPE_POSITION) = TYPE_HDR then
+ next_last_header <= fifo_data_out;
+ tmp_INT_DATA_OUT <= fifo_data_out;
+ tmp_INT_DATAREADY_OUT <= '1';
+ fifo_read <= '1';
+ elsif fifo_data_out(TYPE_POSITION) = TYPE_EOB then
fifo_read <= '1';
got_eob_out <= '1';
+ tmp_INT_DATAREADY_OUT <= '0';
-- this should happen only one CLK cycle
- end if; -- end valid read
-
+ end if;
else
tmp_INT_DATAREADY_OUT <= '0';
- end if;
-
- end process;
-
- -- for HDR retransmit we need another solution to do not overwrite the reg_
- -- DATA word
--- tmp_INT_DATA_OUT <= (others => '0');
--- if INT_HEADER_IN = '1' then
--- tmp_INT_DATA_OUT <= current_last_header;
--- elsif tmp_INT_DATAREADY_OUT ='1' then
--- tmp_INT_DATA_OUT <= fifo_data_out;
--- else
--- tmp_INT_DATA_OUT(TYPE_POSITION) <= TYPE_ILLEGAL;
--- end if;
--- end process;
-
-reg_dataout: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- reg_INT_DATA_OUT <= (others => '0');
- reg_INT_DATAREADY_OUT <= '0';
- elsif CLK_EN = '1' then
- reg_INT_DATA_OUT <= tmp_INT_DATA_OUT;
- reg_INT_DATAREADY_OUT <= tmp_INT_DATAREADY_OUT;
- else
- reg_INT_DATA_OUT <= reg_INT_DATA_OUT;
- reg_INT_DATAREADY_OUT <= reg_INT_DATAREADY_OUT;
- end if;
- end if;
+ end if;
end process;
-
-INT_DATAREADY_OUT <= reg_INT_DATAREADY_OUT;
-INT_DATA_OUT <= reg_INT_DATA_OUT;
-
+--BUGBUG HDR retransmit needed
+
release_locked <= CTRL_LOCKED(0);
STAT_LOCKED(0) <= is_locked;
STAT_LOCKED(15 downto 1) <= (others => '0');
--by the media (via the TrbNetIOMultiplexer)
MED_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
MED_INIT_READ_IN: in STD_LOGIC; -- Media is reading
- MED_INIT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
MED_INIT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
-- (the IOBUF MUST read)
--by the media (via the TrbNetIOMultiplexer)
MED_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
MED_REPLY_READ_IN: in STD_LOGIC; -- Media is reading
- MED_REPLY_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
MED_REPLY_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
-- (the IOBUF MUST read)
MED_DATAREADY_OUT: out STD_LOGIC;
MED_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
MED_READ_IN: in STD_LOGIC;
- MED_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-- Internal direction port
INT_DATAREADY_IN: in STD_LOGIC;
INT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
INT_READ_OUT: out STD_LOGIC;
- INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-- Status and control port
STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0);
CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0);
MED_DATAREADY_OUT => MED_INIT_DATAREADY_OUT,
MED_DATA_OUT => MED_INIT_DATA_OUT,
MED_READ_IN => MED_INIT_READ_IN,
- MED_ERROR_OUT => MED_INIT_ERROR_OUT,
INT_DATAREADY_IN => INT_INIT_DATAREADY_IN,
INT_DATA_IN => INT_INIT_DATA_IN,
INT_READ_OUT => INT_INIT_READ_OUT,
- INT_ERROR_IN => (others => '0'),
STAT_LOCKED(15 downto 0) => INITOBUF_stat_locked,
CTRL_LOCKED(15 downto 0) => INITOBUF_ctrl_locked,
STAT_BUFFER(31 downto 0) => INITOBUF_stat_buffer,
MED_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT,
MED_DATA_OUT => MED_REPLY_DATA_OUT,
MED_READ_IN => MED_REPLY_READ_IN,
- MED_ERROR_OUT => MED_REPLY_ERROR_OUT,
INT_DATAREADY_IN => INT_REPLY_DATAREADY_IN,
INT_DATA_IN => INT_REPLY_DATA_IN,
INT_READ_OUT => INT_REPLY_READ_OUT,
- INT_ERROR_IN => (others => '0'),
STAT_LOCKED(15 downto 0) => REPLYOBUF_stat_locked,
CTRL_LOCKED(15 downto 0) => REPLYOBUF_ctrl_locked,
STAT_BUFFER(31 downto 0) => REPLYOBUF_stat_buffer,
MED_DATAREADY_OUT: out STD_LOGIC;
MED_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
MED_READ_IN: in STD_LOGIC;
- MED_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-- Internal direction port
INT_DATAREADY_IN: in STD_LOGIC;
INT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
INT_READ_OUT: out STD_LOGIC;
- INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-- Status and control port
STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0);
CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0);
architecture trb_net_obuf_arch of trb_net_obuf is
- signal current_output_buffer, next_output_buffer : STD_LOGIC_VECTOR (53 downto 0);
- signal current_ACK_word, current_EOB_word, current_DATA_word, current_NOP_word :
- STD_LOGIC_VECTOR (53 downto 0);
- signal current_DATAREADY_OUT, next_DATAREADY_OUT : STD_LOGIC;
+ component trb_net_sbuf is
+
+ generic (DATA_WIDTH : integer := 56);
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- port to combinatorial logic
+ COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
+ COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
+ COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ -- Port to synchronous output.
+ SYN_DATAREADY_OUT: out STD_LOGIC;
+ SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ SYN_READ_IN: in STD_LOGIC;
+ -- Status and control port
+ STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0);
+ CTRL_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
+ );
+ END component;
+
+ signal current_output_buffer : STD_LOGIC_VECTOR (50 downto 0);
+ signal current_ACK_word, current_EOB_word, current_DATA_word, current_NOP_word :
+ STD_LOGIC_VECTOR (50 downto 0);
+ signal comb_dataready, comb_next_read, comb_read ,sbuf_free: STD_LOGIC;
+ signal reg_INT_READ_OUT , next_INT_READ_OUT:STD_LOGIC;
+
signal next_SEND_ACK_IN, reg_SEND_ACK_IN : STD_LOGIC;
signal sent_ACK, sent_EOB, sent_DATA : STD_LOGIC;
begin
- MED_DATAREADY_OUT <= current_DATAREADY_OUT;
- MED_DATA_OUT <= current_output_buffer(50 downto 0);
- MED_ERROR_OUT <= current_output_buffer(53 downto 51);
-
+ SBUF: trb_net_sbuf
+ generic map (DATA_WIDTH => 51)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ COMB_DATAREADY_IN => comb_dataready,
+ COMB_next_READ_OUT => comb_next_read,
+ COMB_READ_IN => comb_read,
+ COMB_DATA_IN => current_output_buffer,
+ SYN_DATAREADY_OUT => MED_DATAREADY_OUT,
+ SYN_DATA_OUT => MED_DATA_OUT,
+ SYN_READ_IN => MED_READ_IN,
+ CTRL_BUFFER => (others => '0')
+ );
+
decrease_TRANSMITTED_BUFFERS <= GOT_ACK_IN;
+ comb_read <= '1';
+ INT_READ_OUT <= reg_INT_READ_OUT;
+ sbuf_free <= comb_next_read or MED_READ_IN; --sbuf killed
- COMB_NEXT_TRANSFER : process(current_output_buffer, current_DATAREADY_OUT, sent_DATA,
- MED_READ_IN, current_DATA_word, sent_EOB, sent_ACK,
- current_EOB_word, current_ACK_word, reg_SEND_ACK_IN )
- begin -- process
- next_DATAREADY_OUT <= current_DATAREADY_OUT;
- next_output_buffer <= current_output_buffer;
- INT_READ_OUT <= '0';
+ COMB_NEXT_TRANSFER : process(current_NOP_word, MED_READ_IN, comb_next_read,
+ CURRENT_DATA_COUNT,reg_SEND_ACK_IN,reg_INT_READ_OUT,
+ INT_DATAREADY_IN, INT_DATA_IN, sent_ACK, sent_EOB,
+ current_ACK_word,current_EOB_word, sbuf_free, sent_data,
+ max_DATA_COUNT,next_DATA_COUNT,
+ next_TRANSMITTED_BUFFERS)
+ begin
+ current_output_buffer <= current_NOP_word;
+ next_INT_READ_OUT <= '1';
increase_TRANSMITTED_BUFFERS <= '0';
next_DATA_COUNT <= CURRENT_DATA_COUNT;
next_SEND_ACK_IN <= reg_SEND_ACK_IN;
--- EOB should go into the stream
- if (current_DATAREADY_OUT = '0' and sent_ACK = '1')
- or (current_DATAREADY_OUT = '1' and sent_ACK = '1' and MED_READ_IN = '1' ) then
- next_DATAREADY_OUT <= '1';
- next_output_buffer <= current_ACK_word;
- next_SEND_ACK_IN <= '0';
- else
- next_SEND_ACK_IN <= sent_ACK;
- if (current_DATAREADY_OUT = '0' and sent_EOB = '1')
- or (current_DATAREADY_OUT = '1' and sent_EOB = '1' and MED_READ_IN = '1' ) then
- next_DATAREADY_OUT <= '1';
- next_output_buffer <= current_EOB_word;
- next_DATA_COUNT <= (others => '0');
+ comb_dataready <= '0';
+-- The read of data words have highest priority if this was prepared
+ if (reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1') then
+ current_output_buffer <= INT_DATA_IN;
+ comb_dataready <= '1'; --I hope sbuf can store
+ if INT_DATA_IN(TYPE_POSITION) = TYPE_TRM then --TRM means EOB
+ next_DATA_COUNT <= (others => '0');
increase_TRANSMITTED_BUFFERS <= '1';
--- we have something to offer
- elsif (current_DATAREADY_OUT = '0' and sent_DATA = '1')
- or (current_DATAREADY_OUT = '1' and sent_DATA = '1' and MED_READ_IN = '1' ) then
- next_DATAREADY_OUT <= '1';
- next_output_buffer <= current_DATA_word;
- INT_READ_OUT <= '1';
- if INT_DATA_IN(TYPE_POSITION) = TYPE_TRM then --TRM means EOB
- next_DATA_COUNT <= (others => '0');
- increase_TRANSMITTED_BUFFERS <= '1';
- else
- next_DATA_COUNT <= CURRENT_DATA_COUNT +1;
- end if;
--- we will be empty in the next step
- elsif (current_DATAREADY_OUT = '0' and sent_DATA = '0')
- or (current_DATAREADY_OUT = '1' and sent_DATA = '0' and MED_READ_IN = '1' ) then
- next_DATAREADY_OUT <= '0';
- next_output_buffer <= current_NOP_word;
+ else
+ next_DATA_COUNT <= CURRENT_DATA_COUNT +1;
end if;
+-- Otherwise we fill the gap
+ elsif sent_ACK = '1' and sbuf_free = '1' then
+ current_output_buffer <= current_ACK_word;
+ next_SEND_ACK_IN <= '0';
+ comb_dataready <= '1';
+ elsif sent_EOB = '1' and sbuf_free = '1' then
+ current_output_buffer <= current_EOB_word;
+ next_DATA_COUNT <= (others => '0');
+ increase_TRANSMITTED_BUFFERS <= '1';
+ comb_dataready <= '1';
+ end if;
+-- If we are not able to fill ACK or EOB now, we have to stop activity
+ if (reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1'
+ and (sent_ACK = '1' or sent_EOB = '1' )) then
+ next_INT_READ_OUT <= '0';
+ if sent_ACK = '1' then
+ next_SEND_ACK_IN <= '1';
+ end if;
+ end if;
+--finally, block data read if the rec buffer is full
+ if sent_data = '0' or
+ (next_DATA_COUNT = max_DATA_COUNT-1) or
+ next_TRANSMITTED_BUFFERS(1) = '1'
+ then
+ next_INT_READ_OUT <= '0';
end if;
+
end process;
if rising_edge(CLK) then
if RESET = '1' then
reg_SEND_ACK_IN <= '0';
- current_output_buffer <= (others => '0');
- current_DATAREADY_OUT <= '0';
CURRENT_DATA_COUNT <= (others => '0');
+ reg_INT_READ_OUT <= '0';
elsif CLK_EN = '1' then
- reg_SEND_ACK_IN <= next_SEND_ACK_IN;
- current_output_buffer <= next_output_buffer;
- current_DATAREADY_OUT <= next_DATAREADY_OUT;
+ reg_SEND_ACK_IN <= next_SEND_ACK_IN;
CURRENT_DATA_COUNT <= next_DATA_COUNT;
+ reg_INT_READ_OUT <= next_INT_READ_OUT;
else
reg_SEND_ACK_IN <= reg_SEND_ACK_IN;
- current_output_buffer <= current_output_buffer;
- current_DATAREADY_OUT <= current_DATAREADY_OUT;
CURRENT_DATA_COUNT <= CURRENT_DATA_COUNT;
+ reg_INT_READ_OUT <= reg_INT_READ_OUT;
end if;
end if;
end process;
current_ACK_word(47 downto 20) <= (others => '0');
current_ACK_word(BUFFER_SIZE_POSITION) <= SEND_BUFFER_SIZE_IN;
current_ACK_word(15 downto 0) <= (others => '0');
- current_ACK_word(53 downto 51) <= (others => '0');
sent_ACK <= SEND_ACK_IN or reg_SEND_ACK_IN;
current_EOB_word(TYPE_POSITION) <= TYPE_EOB;
current_EOB_word(47 downto 0) <= (others => '0');
- current_EOB_word(53 downto 51) <= (others => '0');
gen_sent_EOB : process (CURRENT_DATA_COUNT, max_DATA_COUNT)
begin
if (CURRENT_DATA_COUNT = max_DATA_COUNT-1) then
current_NOP_word(TYPE_POSITION) <= TYPE_ILLEGAL;
current_NOP_word(47 downto 0) <= (others => '0');
- current_NOP_word(53 downto 51) <= (others => '0');
current_DATA_word(50 downto 0) <= INT_DATA_IN;
- current_DATA_word(53 downto 51) <= INT_ERROR_IN;
- sent_DATA <= INT_DATAREADY_IN
- and not TRANSMITTED_BUFFERS(1);
+ sent_DATA <= not TRANSMITTED_BUFFERS(1);
-- generate max_DATA_COUNT, comb. operation which should be registered
next_max_DATA_COUNT <= "0000000000000100" when REC_BUFFER_SIZE_IN="0001" else
type BUFFER_STATE is (BUFFER_EMPTY, BUFFER_B2_FULL, BUFFER_B1_FULL);
signal current_buffer_state, next_buffer_state : BUFFER_STATE;
+ signal test_buffer_state : STD_LOGIC_VECTOR (1 downto 0);
+
signal current_got_overflow, next_got_overflow : std_logic;
begin
COMB: process (current_buffer_state, COMB_DATAREADY_IN, COMB_READ_IN,
SYN_READ_IN, COMB_DATA_IN, current_b1_buffer, current_b2_buffer,
- current_SYN_DATAREADY_OUT)
+ current_SYN_DATAREADY_OUT, current_got_overflow)
begin -- process COMB
next_buffer_state <= current_buffer_state;
next_next_READ_OUT <= '1';
next_b1_buffer <= current_b1_buffer;
next_SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT;
next_got_overflow <= current_got_overflow;
+ test_buffer_state <= "00";
if current_buffer_state = BUFFER_EMPTY then
+ test_buffer_state <= "01";
if COMB_DATAREADY_IN = '1' and COMB_READ_IN = '1' then
-- COMB logic is writing into the sbuf
next_buffer_state <= BUFFER_B2_FULL;
next_SYN_DATAREADY_OUT <= '1';
end if;
elsif current_buffer_state = BUFFER_B2_FULL then
+ test_buffer_state <= "10";
if COMB_DATAREADY_IN = '1' and COMB_READ_IN = '1' and SYN_READ_IN = '1' then
-- COMB logic is writing into the sbuf
-- at the same time syn port is reading
elsif SYN_READ_IN = '1' then
next_buffer_state <= BUFFER_EMPTY;
next_SYN_DATAREADY_OUT <= '0';
+ else
+ next_buffer_state <= BUFFER_B2_FULL;
+ next_next_READ_OUT <= '0';
+ next_SYN_DATAREADY_OUT <= '1';
end if;
elsif current_buffer_state = BUFFER_B1_FULL then
+ test_buffer_state <= "11";
if COMB_DATAREADY_IN = '1' and COMB_READ_IN = '1' and SYN_READ_IN = '1' then
-- COMB logic is writing into the sbuf
-- at the same time syn port is reading
next_next_READ_OUT <= '0';
next_b2_buffer <= current_b1_buffer;
next_SYN_DATAREADY_OUT <= '1';
- end if;
+ else
+ next_buffer_state <= BUFFER_B1_FULL;
+ next_next_READ_OUT <= '0';
+ next_SYN_DATAREADY_OUT <= '1';
+ end if;
end if;
end process COMB;
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