-----------------------------------------------------------------------
-- Statistics
-----------------------------------------------------------------------
+-- the_stat_proc : process(CLOCK)
+-- begin
+-- if rising_edge(CLOCK) then
+-- gen_buffer_stat : for i in 0 to DATA_INTERFACE_NUMBER-1 loop
+-- if buf_STAT_DATA_BUFFER_LEVEL(i*32+17) = '1' and TIMER_TICKS_IN(0) = '1' then
+-- timer_fifo_almost_full(i) <= timer_fifo_almost_full(i) + to_unsigned(1,1);
+-- end if;
+-- end loop;
+-- if buf_STAT_HEADER_BUFFER_LEVEL(17) = '1' and TIMER_TICKS_IN(0) = '1' then
+-- timer_lvl1_almost_full <= timer_lvl1_almost_full + to_unsigned(1,1);
+-- end if;
+-- if buf_STAT_HEADER_BUFFER_LEVEL(20) = '1' and TIMER_TICKS_IN(0) = '1' then
+-- timer_lvl1_idle <= timer_lvl1_idle + to_unsigned(1,1);
+-- end if;
+-- if (buf_STAT_HEADER_BUFFER_LEVEL(21) = '1' or buf_STAT_HEADER_BUFFER_LEVEL(22) = '1') and TIMER_TICKS_IN(0) = '1' then
+-- timer_lvl1_working <= timer_lvl1_working + to_unsigned(1,1);
+-- end if;
+-- end if;
+-- end process;
+--
+-- the_ipu_stat_proc : process(CLOCK)
+-- begin
+-- if rising_edge(CLOCK) then
+-- if (status_ipu_handler_i(3 downto 0) = x"0")
+-- and TIMER_TICKS_IN(0) = '1' then
+-- timer_ipu_idle <= timer_ipu_idle + to_unsigned(1,1);
+-- end if;
+-- if (status_ipu_handler_i(3 downto 0) = x"2" or status_ipu_handler_i(3 downto 0) = x"3" or status_ipu_handler_i(3 downto 0) = x"4")
+-- and (status_ipu_handler_i(7) = '1' or status_ipu_handler_i(6) = '0')
+-- and TIMER_TICKS_IN(0) = '1' then
+-- timer_ipu_working <= timer_ipu_working + to_unsigned(1,1);
+-- end if;
+-- if status_ipu_handler_i(6) = '1' and status_ipu_handler_i(7) = '0' and TIMER_TICKS_IN(0) = '1' then
+-- timer_ipu_waiting <= timer_ipu_waiting + to_unsigned(1,1);
+-- end if;
+-- end if;
+-- end process;
+--
+-- proc_read_stat : process(CLOCK)
+-- variable addr : integer range 0 to 31;
+-- begin
+-- if rising_edge(CLOCK) then
+-- addr := to_integer(unsigned(STATISTICS_ADDR_IN));
+-- if STATISTICS_READ_IN = '1' then
+-- if addr < DATA_INTERFACE_NUMBER then
+-- STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_fifo_almost_full(addr));
+-- STATISTICS_READY_OUT <= '1';
+-- STATISTICS_UNKNOWN_OUT <= '0';
+-- elsif addr >= 16 and addr <= 21 then
+-- case addr is
+-- when 16 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_lvl1_almost_full);
+-- when 17 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_lvl1_idle);
+-- when 18 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_lvl1_working);
+-- when 19 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_idle);
+-- when 20 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_working);
+-- when 21 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_waiting);
+-- when others => STATISTICS_DATA_OUT <= (others => '0');
+-- end case;
+-- STATISTICS_READY_OUT <= '1';
+-- STATISTICS_UNKNOWN_OUT <= '0';
+-- else
+-- STATISTICS_READY_OUT <= '0';
+-- STATISTICS_UNKNOWN_OUT <= '1';
+-- end if;
+-- else
+-- STATISTICS_READY_OUT <= '0';
+-- STATISTICS_UNKNOWN_OUT <= '0';
+-- end if;
+-- end if;
+-- end process;
+
the_stat_proc : process(CLOCK)
begin
if rising_edge(CLOCK) then
STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_fifo_almost_full(addr));
STATISTICS_READY_OUT <= '1';
STATISTICS_UNKNOWN_OUT <= '0';
- elsif addr >= 16 and addr <= 21 then
+ elsif addr >= 16 and addr <= 22 then
case addr is
when 16 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_lvl1_almost_full);
when 17 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_lvl1_idle);
when 19 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_idle);
when 20 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_working);
when 21 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_waiting);
+ when 22 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_waiting);
when others => STATISTICS_DATA_OUT <= (others => '0');
end case;
STATISTICS_READY_OUT <= '1';
end if;
end process;
+-- DATA HANDLER
+-- DEBUG_OUT(0) <= data_buffer_write(0);
+-- DEBUG_OUT(1) <= IPU_DATA_READ_IN(0);
+-- DEBUG_OUT(3 downto 2) <= "00";
+-- DEBUG_OUT(7 downto 4) <= data_buffer_data_in(35 downto 32);
+-- DEBUG_OUT(10 downto 8) <= lvl1_state_bits;
+-- DEBUG_OUT(11) <= '0';
+-- DEBUG_OUT(14 downto 12) <= buffer_state_bits(0);
+-- DEBUG_OUT(31 downto 15) <= (others => '0');
+
+
+-- IPU HANDLER
+-- state_bits <= x"0" when current_state = IDLE
+-- else x"1" when current_state = WAIT_FOR_LENGTH
+-- -- else x"2" when current_state = GOT_LENGTH
+-- else x"3" when current_state = SEND_DHDR
+-- else x"4" when current_state = READ_DATA
+-- else x"5" when current_state = END_READOUT
+-- else x"F";
+--
+-- STATUS_OUT( 3 downto 0) <= state_bits;
+-- STATUS_OUT( 4) <= dat_fifo_read(0);
+-- STATUS_OUT( 5) <= dat_fifo_valid_read;
+-- STATUS_OUT( 6) <= ipu_dataready_i;
+-- STATUS_OUT( 7) <= IPU_READ_IN;
+-- STATUS_OUT(11 downto 8) <= DAT_DATA_FLAGS_IN(3 downto 0);
+-- STATUS_OUT(12) <= error_not_found;
+-- STATUS_OUT(13) <= error_missing;
+-- STATUS_OUT(14) <= error_sync;
+-- STATUS_OUT(15) <= error_not_configured;
+-- STATUS_OUT(23 downto 16) <= DAT_DATA_IN(7 downto 0);
+-- STATUS_OUT(31 downto 24) <= (others => '0');
+--
+
-----------------------------------------------------------------------
-- Debug
CLK_EN : in std_logic;\r
\r
--TrbNet connect\r
- APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_FIFO_COUNT_IN : in std_logic_vector (11*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_DATA_OUT : out std_logic_vector (16*3-1 downto 0);\r
+ APL_PACKET_NUM_OUT : out std_logic_vector (3*3-1 downto 0);\r
+ APL_DATAREADY_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_READ_IN : in std_logic_vector (3-1 downto 0);\r
+ APL_SHORT_TRANSFER_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_DTYPE_OUT : out std_logic_vector (4*3-1 downto 0);\r
+ APL_ERROR_PATTERN_OUT : out std_logic_vector (32*3-1 downto 0);\r
+ APL_SEND_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*3-1 downto 0);\r
+ APL_DATA_IN : in std_logic_vector (16*3-1 downto 0);\r
+ APL_PACKET_NUM_IN : in std_logic_vector (3*3-1 downto 0);\r
+ APL_TYP_IN : in std_logic_vector (3*3-1 downto 0);\r
+ APL_DATAREADY_IN : in std_logic_vector (3-1 downto 0);\r
+ APL_READ_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_RUN_IN : in std_logic_vector (3-1 downto 0);\r
+ APL_SEQNR_IN : in std_logic_vector (8*3-1 downto 0);\r
+ APL_FIFO_COUNT_IN : in std_logic_vector (11*3-1 downto 0);\r
\r
--Internal Data Bus\r
BUS_ADDR_IN : in std_logic_vector(31 downto 0);\r
BUS_CYC_IN : in std_logic;\r
BUS_STB_IN : in std_logic;\r
BUS_LOCK_IN : in std_logic;\r
--- BUS_CTI_IN : in std_logic_vector(2 downto 0);\r
BUS_ACK_OUT : out std_logic;\r
\r
EXT_TRIGGER_INFO : out std_logic_vector(15 downto 0);\r
end entity;\r
\r
\r
---address range is 100 to FFF\r
--- (c is channel number * 2 + 1 if active part)\r
-\r
---sending data. sending is released when 1c0 is written\r
---1c0 wr (3..0) Dtype (8) short transfer sender_control 9bit used\r
---1c1 wr target address sender_target 16bit used\r
---1c2 wr Errorbits sender_error 32bit used\r
---1c3 w sender data fifo sender_data 16bit used\r
---1c4 r sender fifo status (9..0 datacount, 16 full, 17 empty)\r
---1c5 wr Extended Trigger Information sender_trigger_information 16bit\r
---1cF r status (0)transfer running sender_status 1bit used\r
-\r
---received data\r
---2c3 r receiver data fifo, (20..18)type receiver_data 16bit used\r
---2c4 r receiver fifo status (9..0 datacount, 16 full, 17 empty)\r
-\r
-\r
---3c0 (7..0) seq_num apis_tatus\r
\r
--700 - 71F DMA configuration\r
\r
\r
\r
architecture trb_net_bridge_pcie_apl_arch of trb_net_bridge_pcie_apl is\r
- signal fifo_net_to_pci_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0);\r
--- signal fifo_net_to_pci_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0);\r
- signal fifo_net_to_pci_dout : std_logic_vector(32*2**c_MUX_WIDTH-1 downto 0);\r
--- signal fifo_net_to_pci_din : std_logic_vector(18*2**c_MUX_WIDTH-1 downto 0);\r
- signal fifo_net_to_pci_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);\r
- signal fifo_net_to_pci_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);\r
--- signal fifo_pci_to_net_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0);\r
--- signal fifo_pci_to_net_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0);\r
--- signal fifo_pci_to_net_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);\r
--- signal fifo_pci_to_net_dout : std_logic_vector(18*2**c_MUX_WIDTH-1 downto 0);\r
--- signal fifo_pci_to_net_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);\r
--- signal fifo_pci_to_net_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);\r
- signal next_APL_SEND_OUT : std_logic_vector(2**c_MUX_WIDTH-1 downto 0);\r
- signal sender_control : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0);\r
- signal sender_target : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0);\r
- signal sender_error : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0);\r
- signal sender_status : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0);\r
- signal api_status : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0);\r
-\r
- signal channel_address : integer range 0 to 7;\r
--- signal comb_channel_address : integer range 0 to 7;\r
--- signal last_CPU_ADDRESS : std_logic_vector(15 downto 0);\r
-\r
--- signal next_CPU_DATA_OUT: std_logic_vector(31 downto 0);\r
--- signal buf_CPU_DATA_OUT : std_logic_vector(31 downto 0);\r
--- signal last_fifo_read : std_logic;\r
--- signal buf_CPU_DATAREADY_OUT : std_logic;\r
--- signal b_CPU_DATAREADY_OUT : std_logic;\r
-\r
-\r
- signal bus_ack_i : std_logic;\r
- signal bus_data_i : std_logic_vector(31 downto 0);\r
- signal bus_rdat_i : std_logic_vector(31 downto 0);\r
- signal bus_read_i : std_logic;\r
- signal bus_write_i : std_logic;\r
- signal bus_stb_rising : std_logic;\r
- signal bus_stb_last : std_logic;\r
- signal bus_write_last : std_logic;\r
- signal bus_read_last : std_logic;\r
+ signal fifo_net_to_pci_read : std_logic_vector(3 downto 0);\r
+ signal fifo_net_to_pci_dout : std_logic_vector(32*4-1 downto 0);\r
+ signal fifo_net_to_pci_valid_read : std_logic_vector(3 downto 0);\r
+ signal fifo_net_to_pci_empty : std_logic_vector(3 downto 0);\r
+ signal next_APL_SEND_OUT : std_logic_vector(2 downto 0);\r
+ signal sender_control : std_logic_vector(32*4-1 downto 0);\r
+ signal sender_target : std_logic_vector(32*4-1 downto 0);\r
+ signal sender_error : std_logic_vector(32*4-1 downto 0);\r
+ signal sender_status : std_logic_vector(32*4-1 downto 0);\r
+ signal api_status : std_logic_vector(32*4-1 downto 0);\r
+\r
+ signal channel_address : integer range 0 to 3;\r
+\r
+ signal bus_ack_i : std_logic := '0';\r
+ signal bus_data_i : std_logic_vector(31 downto 0) := (others => '0');\r
+ signal bus_rdat_i : std_logic_vector(31 downto 0) := (others => '0');\r
+ signal bus_read_i : std_logic := '0';\r
+ signal bus_write_i : std_logic := '0';\r
+ signal bus_stb_rising : std_logic := '0';\r
+ signal bus_stb_last : std_logic := '0';\r
+ signal bus_write_last : std_logic := '0';\r
+ signal bus_read_last : std_logic := '0';\r
\r
signal send_reset_counter : unsigned(10 downto 0);\r
\r
bus_read_i <= not BUS_WE_IN and bus_stb_rising;\r
bus_write_i <= BUS_WE_IN and bus_stb_rising;\r
\r
- channel_address <= to_integer(unsigned(BUS_ADDR_IN(6 downto 4)));\r
+ channel_address <= to_integer(unsigned(BUS_ADDR_IN(6 downto 5)));\r
\r
read_regs : process(sender_control, sender_target, sender_error, sender_status, APL_FIFO_COUNT_IN,\r
BUS_ADDR_IN, api_status, fifo_net_to_pci_empty, bus_data_i, channel_address, fifo_net_to_pci_dout)\r
--middle nibble is dont care\r
when x"10" =>\r
bus_data_i <= sender_control(channel_address*32+31 downto channel_address*32);\r
- when x"11" =>\r
- bus_data_i <= sender_target(channel_address*32+31 downto channel_address*32);\r
+-- when x"11" =>\r
+-- bus_data_i <= sender_target(channel_address*32+31 downto channel_address*32);\r
when x"12" =>\r
bus_data_i <= sender_error(channel_address*32+31 downto channel_address*32);\r
-- when x"14" =>\r
sender_target <= (others => '0');\r
sender_error <= (others => '0');\r
else\r
- if bus_write_i = '1' and BUS_ADDR_IN(11 downto 8) = x"1" then\r
+ if bus_write_i = '1' and BUS_ADDR_IN(11 downto 8) = x"1" and USE_CHANNELS(channel_address) = c_YES then\r
case BUS_ADDR_IN(3 downto 0) is\r
--middle nibble is dont care\r
when x"0" =>\r
- sender_control(channel_address*32+8 downto channel_address*32) <= BUS_WDAT_IN(8 downto 0);\r
+ sender_control(channel_address*32+31 downto channel_address*32) <= BUS_WDAT_IN(31 downto 0);\r
when x"1" =>\r
sender_target(channel_address*32+15 downto channel_address*32) <= BUS_WDAT_IN(15 downto 0);\r
when x"2" =>\r
end if;\r
end process;\r
\r
- gen_api_connect : for i in 0 to 2**(c_MUX_WIDTH)-1 generate\r
\r
-\r
- api_status(i*32+7 downto i*32) <= APL_SEQNR_IN(i*8+7 downto i*8);\r
- api_status(i*32+31 downto i*32+8) <= (others => '0');\r
- sender_status(i*32) <= APL_RUN_IN(i);\r
- sender_status(i*32+31 downto i*32+1) <= (others => '0');\r
-\r
-\r
- --connection to API\r
- next_APL_SEND_OUT(i) <= '1' when BUS_ADDR_IN(11 downto 8) = x"1"\r
- and BUS_ADDR_IN(7 downto 4) = std_logic_vector(to_unsigned(i,4))\r
+ api_status(0*32+7 downto 0*32) <= APL_SEQNR_IN(0*8+7 downto 0*8);\r
+ api_status(1*32+7 downto 1*32) <= APL_SEQNR_IN(1*8+7 downto 1*8);\r
+ api_status(2*32+7 downto 2*32) <= (others => '0');\r
+ api_status(3*32+7 downto 3*32) <= APL_SEQNR_IN(2*8+7 downto 2*8);\r
+ api_status(0*32+31 downto 0*32+8) <= (others => '0');\r
+ api_status(1*32+31 downto 1*32+8) <= (others => '0');\r
+ api_status(2*32+31 downto 2*32+8) <= (others => '0');\r
+ api_status(3*32+31 downto 3*32+8) <= (others => '0');\r
+ sender_status(0*32) <= APL_RUN_IN(0);\r
+ sender_status(1*32) <= APL_RUN_IN(1);\r
+ sender_status(2*32) <= '0';\r
+ sender_status(3*32) <= APL_RUN_IN(2);\r
+ sender_status(0*32+31 downto 0*32+1)<= (others => '0');\r
+ sender_status(1*32+31 downto 1*32+1)<= (others => '0');\r
+ sender_status(2*32+31 downto 2*32+1)<= (others => '0');\r
+ sender_status(3*32+31 downto 3*32+1)<= (others => '0');\r
+\r
+ next_APL_SEND_OUT(0) <= '1' when BUS_ADDR_IN(11 downto 8) = x"1"\r
+ and BUS_ADDR_IN(6 downto 5) = "00"\r
+ and BUS_ADDR_IN(3 downto 0) = x"0"\r
+ and bus_write_last = '1' else '0';\r
+ next_APL_SEND_OUT(1) <= '1' when BUS_ADDR_IN(11 downto 8) = x"1"\r
+ and BUS_ADDR_IN(6 downto 5) = "01"\r
+ and BUS_ADDR_IN(3 downto 0) = x"0"\r
+ and bus_write_last = '1' else '0';\r
+ next_APL_SEND_OUT(2) <= '1' when BUS_ADDR_IN(11 downto 8) = x"1"\r
+ and BUS_ADDR_IN(6 downto 5) = "11"\r
and BUS_ADDR_IN(3 downto 0) = x"0"\r
and bus_write_last = '1' else '0';\r
\r
- APL_DATAREADY_OUT(i) <= '1' when BUS_ADDR_IN(11 downto 8) = x"1"\r
- and BUS_ADDR_IN(7 downto 4) = std_logic_vector(to_unsigned(i,4))\r
+ APL_DATAREADY_OUT(0) <= '1' when BUS_ADDR_IN(11 downto 8) = x"1"\r
+ and BUS_ADDR_IN(6 downto 5) = "00"\r
+ and BUS_ADDR_IN(3 downto 0) = x"3"\r
+ and bus_write_i = '1' else '0';\r
+ APL_DATAREADY_OUT(1) <= '1' when BUS_ADDR_IN(11 downto 8) = x"1"\r
+ and BUS_ADDR_IN(6 downto 5) = "01"\r
+ and BUS_ADDR_IN(3 downto 0) = x"3"\r
+ and bus_write_i = '1' else '0';\r
+ APL_DATAREADY_OUT(2) <= '1' when BUS_ADDR_IN(11 downto 8) = x"1"\r
+ and BUS_ADDR_IN(6 downto 5) = "11"\r
and BUS_ADDR_IN(3 downto 0) = x"3"\r
and bus_write_i = '1' else '0';\r
\r
- APL_DATA_OUT((i+1)*16-1 downto i*16) <= BUS_WDAT_IN(15 downto 0);\r
- APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= BUS_WDAT_IN(17 downto 16);\r
- APL_PACKET_NUM_OUT(i*3+2) <= '0';\r
- APL_SHORT_TRANSFER_OUT(i) <= sender_control(i*32+8);\r
- APL_ERROR_PATTERN_OUT(i*32+31 downto i*32) <= sender_error(i*32+31 downto i*32);\r
- APL_TARGET_ADDRESS_OUT(i*16+15 downto i*16) <= sender_target(i*32+15 downto i*32);\r
- APL_DTYPE_OUT(i*4+3 downto i*4) <= sender_control(i*32+3 downto i*32);\r
-\r
-\r
- --connection from API\r
- fifo_net_to_pci_empty(i) <= not APL_DATAREADY_IN(i); --or_all(APL_FIFO_COUNT_IN(11*i+10 downto 11*i));\r
-\r
- fifo_net_to_pci_dout(32*i+c_DATA_WIDTH-1 downto 32*i) <= APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i);\r
- fifo_net_to_pci_dout(32*i+c_DATA_WIDTH) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i);\r
- fifo_net_to_pci_dout(32*i+c_DATA_WIDTH+1) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2);\r
- fifo_net_to_pci_dout(i*32+31 downto i*32+25) <= (others => '0');\r
- fifo_net_to_pci_dout(i*32+24) <= fifo_net_to_pci_valid_read(i);\r
- fifo_net_to_pci_dout(i*32+23 downto i*32+18) <= (others => '0');\r
- APL_READ_OUT(i) <= fifo_net_to_pci_read(i);\r
-\r
--- fifo_net_to_pci_din(18*i+c_DATA_WIDTH-1 downto 18*i) <= APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i);\r
--- fifo_net_to_pci_din(18*i+c_DATA_WIDTH) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i);\r
--- fifo_net_to_pci_din(18*i+c_DATA_WIDTH+1) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2);\r
--- fifo_net_to_pci_write(i) <= APL_DATAREADY_IN(i) and not fifo_net_to_pci_full(i);\r
--- APL_DATAREADY_OUT(i) <= fifo_pci_to_net_valid_read(i);\r
--- APL_DATA_OUT((i+1)*16-1 downto i*16) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH-1 downto i*18);\r
--- APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH+1 downto i*18+c_DATA_WIDTH);\r
--- APL_PACKET_NUM_OUT(i*3+2) <= '0';\r
--- fifo_pci_to_net_read(i) <= APL_READ_IN(i); --NOT CORRECT - last packet may be lost, but transfer size is limited anyhow\r
-\r
- end generate;\r
+ APL_DATA_OUT <= BUS_WDAT_IN(15 downto 0) & BUS_WDAT_IN(15 downto 0) & BUS_WDAT_IN(15 downto 0);\r
+ APL_PACKET_NUM_OUT <= '0' & BUS_WDAT_IN(17 downto 16) & '0' & BUS_WDAT_IN(17 downto 16) & '0' & BUS_WDAT_IN(17 downto 16);\r
+ APL_SHORT_TRANSFER_OUT <= sender_control(96+8) & sender_control(32+8) & sender_control(8);\r
+ APL_ERROR_PATTERN_OUT <= sender_error(127 downto 96) & sender_error(63 downto 32) & sender_error(31 downto 0);\r
+-- APL_TARGET_ADDRESS_OUT <= sender_control(127 downto 112) & sender_control(63 downto 48) & sender_control(31 downto 16);\r
+ APL_TARGET_ADDRESS_OUT <= sender_target(111 downto 96) & sender_target(47 downto 32) & sender_target(15 downto 0);\r
+ APL_DTYPE_OUT <= sender_control(99 downto 96) & sender_control(35 downto 32) & sender_control(3 downto 0);\r
\r
+ APL_READ_OUT <= fifo_net_to_pci_read(3) & fifo_net_to_pci_read(1) & fifo_net_to_pci_read(0);\r
+ fifo_net_to_pci_empty <= not (APL_DATAREADY_IN(2) & '0' & APL_DATAREADY_IN(1) & APL_DATAREADY_IN(0));\r
+ fifo_net_to_pci_dout(31 downto 0) <= "0000000" & fifo_net_to_pci_valid_read(0) & "000000"\r
+ & APL_PACKET_NUM_IN(2) & APL_PACKET_NUM_IN(0) & APL_DATA_IN(15 downto 0);\r
+ fifo_net_to_pci_dout(63 downto 32) <= "0000000" & fifo_net_to_pci_valid_read(1) & "000000"\r
+ & APL_PACKET_NUM_IN(5) & APL_PACKET_NUM_IN(3) & APL_DATA_IN(31 downto 16);\r
+ fifo_net_to_pci_dout(95 downto 64) <= (others => '0');\r
+ fifo_net_to_pci_dout(127 downto 96) <= "0000000" & fifo_net_to_pci_valid_read(3) & "000000"\r
+ & APL_PACKET_NUM_IN(8) & APL_PACKET_NUM_IN(6) & APL_DATA_IN(47 downto 32);\r
\r
\r
\r
proc_fifo_readwrite : process(BUS_ADDR_IN, bus_read_i, channel_address, APL_DATAREADY_IN, fifo_net_to_pci_read)\r
begin\r
- fifo_net_to_pci_valid_read <= fifo_net_to_pci_read and APL_DATAREADY_IN;\r
+ fifo_net_to_pci_valid_read(0) <= fifo_net_to_pci_read(0) and APL_DATAREADY_IN(0);\r
+ fifo_net_to_pci_valid_read(1) <= fifo_net_to_pci_read(1) and APL_DATAREADY_IN(1);\r
+ fifo_net_to_pci_valid_read(3) <= fifo_net_to_pci_read(3) and APL_DATAREADY_IN(2);\r
fifo_net_to_pci_read <= (others => '0');\r
if BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0) = x"23" then\r
fifo_net_to_pci_read(channel_address) <= bus_read_i;\r
end if;\r
end process;\r
\r
--- process(BUS_ADDR_IN, bus_data_i, fifo_net_to_pci_dout, bus_read_i, bus_write_i, channel_address)\r
--- begin\r
--- if BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0) = x"23" then\r
--- bus_rdat_i <= fifo_net_to_pci_dout(channel_address*32+31 downto channel_address*32);\r
--- bus_ack_i <= (bus_read_i or bus_write_i);\r
--- else\r
-\r
--- end if;\r
--- end process;\r
-\r
-\r
---------------------------------\r
--- fifo as bridge to pci\r
---------------------------------\r
-\r
-\r
--- gen_incoming_fifos : for i in 0 to 2**(c_MUX_WIDTH)-1 generate\r
--- gen_used_fifos : if USE_CHANNELS(i/2) = c_YES generate\r
--- -- FIFO_NET_TO_PCI: trb_net16_fifo\r
--- -- generic map(\r
--- -- USE_VENDOR_CORES => c_YES,\r
--- -- USE_DATA_COUNT => c_YES,\r
--- -- DEPTH => 6\r
--- -- )\r
--- -- port map(\r
--- -- CLK => CLK,\r
--- -- RESET => RESET,\r
--- -- CLK_EN => '1',\r
--- -- READ_ENABLE_IN => fifo_net_to_pci_read(i),\r
--- -- WRITE_ENABLE_IN => fifo_net_to_pci_write(i),\r
--- -- DATA_IN => fifo_net_to_pci_din(18*i+15 downto 18*i),\r
--- -- PACKET_NUM_IN => fifo_net_to_pci_din(18*i+17 downto 18*i+16),\r
--- -- DATA_OUT => fifo_net_to_pci_dout(32*i+15 downto 32*i),\r
--- -- PACKET_NUM_OUT => fifo_net_to_pci_dout(32*i+17 downto 32*i+16),\r
--- -- DATA_COUNT_OUT => fifo_net_to_pci_data_count(i)(10 downto 0),\r
--- -- full_out => fifo_net_to_pci_full(i),\r
--- -- empty_out => fifo_net_to_pci_empty(i)\r
--- -- );\r
---\r
--- -- FIFO_PCI_TO_NET: trb_net16_fifo\r
--- -- generic map(\r
--- -- USE_VENDOR_CORES => c_YES,\r
--- -- USE_DATA_COUNT => c_YES,\r
--- -- DEPTH => 6\r
--- -- )\r
--- -- port map(\r
--- -- CLK => CLK,\r
--- -- RESET => RESET,\r
--- -- CLK_EN => '1',\r
--- -- READ_ENABLE_IN => fifo_pci_to_net_read(i),\r
--- -- WRITE_ENABLE_IN => fifo_pci_to_net_write(i),\r
--- -- DATA_IN => BUS_WDAT_IN(15 downto 0),\r
--- -- PACKET_NUM_IN => BUS_WDAT_IN(17 downto 16),\r
--- -- DATA_OUT => fifo_pci_to_net_dout(18*i+15 downto 18*i),\r
--- -- PACKET_NUM_OUT => fifo_pci_to_net_dout(18*i+17 downto 18*i+16),\r
--- -- DATA_COUNT_OUT => fifo_pci_to_net_data_count(i)(10 downto 0),\r
--- -- full_out => fifo_pci_to_net_full(i),\r
--- -- empty_out => fifo_pci_to_net_empty(i)\r
--- -- );\r
--- end generate;\r
--- end generate;\r
-\r
--- proc_valid_read : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- end if;\r
--- end process;\r
-\r
-\r
--------------------------------\r
-- network reset\r
--------------------------------\r
entity trb_net_bridge_pcie_endpoint is
generic(
- USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
- AUTO_ANSWER_INCOMING_REQUESTS : channel_config_t := (c_YES,c_YES,c_YES,c_YES)
+ USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES)
);
port(
RESET : in std_logic;
BUS_CYC_IN : in std_logic;
BUS_STB_IN : in std_logic;
BUS_LOCK_IN : in std_logic;
--- BUS_CTI_IN : in std_logic_vector(2 downto 0);
BUS_ACK_OUT : out std_logic;
MED_DATAREADY_IN : in STD_LOGIC;
signal APL_STAT : std_logic_vector(31 downto 0);
- signal APL_DATA_IN : std_logic_vector(2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0);
- signal APL_PACKET_NUM_IN : std_logic_vector(2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0);
- signal APL_DATAREADY_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0);
- signal APL_READ_OUT : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0);
- signal APL_SHORT_TRANSFER_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0);
- signal APL_DTYPE_IN : std_logic_vector(2**(c_MUX_WIDTH)*4-1 downto 0);
- signal APL_SEND_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0);
- signal APL_DATA_OUT : std_logic_vector(2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0);
- signal APL_PACKET_NUM_OUT : std_logic_vector(2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0);
- signal APL_TYP_OUT : std_logic_vector(2**(c_MUX_WIDTH)*3-1 downto 0);
- signal APL_DATAREADY_OUT : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0);
- signal APL_READ_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0);
- signal APL_RUN_OUT : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0);
- signal APL_SEQNR_OUT : std_logic_vector(2**(c_MUX_WIDTH)*8-1 downto 0);
- signal APL_TARGET_ADDRESS_OUT : std_logic_vector(2**(c_MUX_WIDTH)*16-1 downto 0);
- signal APL_ERROR_PATTERN_IN : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0);
- signal APL_TARGET_ADDRESS_IN : std_logic_vector(2**(c_MUX_WIDTH)*16-1 downto 0);
- signal APL_FIFO_COUNT_OUT : std_logic_vector(2**(c_MUX_WIDTH)*11-1 downto 0);
+ signal APL_DATA_IN : std_logic_vector(4*16-1 downto 0);
+ signal APL_PACKET_NUM_IN : std_logic_vector(4*3-1 downto 0);
+ signal APL_DATAREADY_IN : std_logic_vector(4-1 downto 0);
+ signal APL_READ_OUT : std_logic_vector(4-1 downto 0);
+ signal APL_SHORT_TRANSFER_IN : std_logic_vector(4-1 downto 0);
+ signal APL_DTYPE_IN : std_logic_vector(4*4-1 downto 0);
+ signal APL_SEND_IN : std_logic_vector(4-1 downto 0);
+ signal APL_DATA_OUT : std_logic_vector(4*16-1 downto 0);
+ signal APL_PACKET_NUM_OUT : std_logic_vector(4*3-1 downto 0);
+ signal APL_TYP_OUT : std_logic_vector(4*3-1 downto 0);
+ signal APL_DATAREADY_OUT : std_logic_vector(4-1 downto 0);
+ signal APL_READ_IN : std_logic_vector(4-1 downto 0);
+ signal APL_RUN_OUT : std_logic_vector(4-1 downto 0);
+ signal APL_SEQNR_OUT : std_logic_vector(4*8-1 downto 0);
+ signal APL_TARGET_ADDRESS_OUT : std_logic_vector(4*16-1 downto 0);
+ signal APL_ERROR_PATTERN_IN : std_logic_vector(4*32-1 downto 0);
+ signal APL_TARGET_ADDRESS_IN : std_logic_vector(4*16-1 downto 0);
+ signal APL_FIFO_COUNT_OUT : std_logic_vector(4*11-1 downto 0);
signal APL_MY_ADDRESS_IN : std_logic_vector(15 downto 0);
- signal buf_api_stat_fifo_to_int : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0);
- signal buf_api_stat_fifo_to_apl : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0);
+ signal buf_api_stat_fifo_to_int : std_logic_vector(4*32-1 downto 0);
+ signal buf_api_stat_fifo_to_apl : std_logic_vector(4*32-1 downto 0);
signal CLK_EN : std_logic;
gen_used_channel : if USE_CHANNELS(i) = c_YES generate
IOBUF: trb_net16_iobuf
generic map (
- USE_CHECKSUM => cfg_USE_CHECKSUM(i)
+ USE_CHECKSUM => cfg_USE_CHECKSUM(i),
+ INIT_CAN_SEND_DATA => c_YES,
+ INIT_CAN_RECEIVE_DATA => c_NO,
+ REPLY_CAN_SEND_DATA => c_NO,
+ REPLY_CAN_RECEIVE_DATA => c_YES
)
port map (
-- Misc
gen_pas_apis : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate
gen_used_api : if USE_CHANNELS(i) = c_YES generate
- gen_passive_api : if AUTO_ANSWER_INCOMING_REQUESTS(i) = c_NO generate
- DAT_PASSIVE_API: trb_net16_api_base
- generic map (
- API_TYPE => c_API_PASSIVE,
- FIFO_TO_INT_DEPTH => c_FIFO_BRAM,
- FIFO_TO_APL_DEPTH => c_FIFO_BRAM,
- FORCE_REPLY => cfg_FORCE_REPLY(i),
- SBUF_VERSION => 0,
- USE_VENDOR_CORES => c_YES,
- SECURE_MODE_TO_APL => c_YES,
- SECURE_MODE_TO_INT => c_YES,
- APL_WRITE_ALL_WORDS => c_YES,
- BROADCAST_BITMASK => x"FF"
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET_i,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => APL_DATA_IN((2*i+1)*c_DATA_WIDTH-1 downto 2*i*c_DATA_WIDTH),
- APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((2*i+1)*c_NUM_WIDTH-1 downto 2*i*c_NUM_WIDTH),
- APL_DATAREADY_IN => APL_DATAREADY_IN(2*i),
- APL_READ_OUT => APL_READ_OUT(2*i),
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(2*i),
- APL_DTYPE_IN => APL_DTYPE_IN((2*i+1)*4-1 downto 2*i*4),
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((2*i+1)*32-1 downto 2*i*32),
- APL_SEND_IN => APL_SEND_IN(2*i),
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((2*i+1)*16-1 downto 2*i*16),
- -- Receiver port
- APL_DATA_OUT => APL_DATA_OUT((2*i+1)*c_DATA_WIDTH-1 downto 2*i*c_DATA_WIDTH),
- APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((2*i+1)*c_NUM_WIDTH-1 downto 2*i*c_NUM_WIDTH),
- APL_TYP_OUT => APL_TYP_OUT((2*i+1)*3-1 downto 2*i*3),
- APL_DATAREADY_OUT => APL_DATAREADY_OUT(2*i),
- APL_READ_IN => APL_READ_IN(2*i),
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT(2*i),
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_LENGTH_IN => x"FFFF",
- APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+1)*8-1 downto 2*i*8),
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
- INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i),
- INT_MASTER_DATAREADY_IN => '0',
- INT_MASTER_DATA_IN => (others => '0'),
- INT_MASTER_PACKET_NUM_IN => (others => '0'),
- INT_MASTER_READ_OUT => open,
- INT_SLAVE_DATAREADY_OUT => open,
- INT_SLAVE_DATA_OUT => open,
- INT_SLAVE_PACKET_NUM_OUT => open,
- INT_SLAVE_READ_IN => '1',
- INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
- INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i),
- CTRL_SEQNR_RESET => '0',
- -- Status and control port
- STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+1)*32-1 downto 2*i*32),
- STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+1)*32-1 downto 2*i*32)
- );
-
DAT_ACTIVE_API: trb_net16_api_base
- generic map (
- API_TYPE => c_API_ACTIVE,
- FIFO_TO_INT_DEPTH => c_FIFO_BRAM,
- FIFO_TO_APL_DEPTH => c_FIFO_BRAM,
- FORCE_REPLY => cfg_FORCE_REPLY(i),
- SBUF_VERSION => 0,
- USE_VENDOR_CORES => c_YES,
- SECURE_MODE_TO_APL => c_YES,
- SECURE_MODE_TO_INT => c_YES,
- APL_WRITE_ALL_WORDS => c_YES,
- BROADCAST_BITMASK => x"FF"
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET_i,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => APL_DATA_IN((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH),
- APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH),
- APL_DATAREADY_IN => APL_DATAREADY_IN(2*i+1),
- APL_READ_OUT => APL_READ_OUT(2*i+1),
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(2*i+1),
- APL_DTYPE_IN => APL_DTYPE_IN((2*i+2)*4-1 downto (2*i+1)*4),
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((2*i+2)*32-1 downto (2*i+1)*32),
- APL_SEND_IN => APL_SEND_IN(2*i+1),
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((2*i+2)*16-1 downto (2*i+1)*16),
- -- Receiver port
- APL_DATA_OUT => APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH),
- APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH),
- APL_TYP_OUT => APL_TYP_OUT((2*i+2)*3-1 downto (2*i+1)*3),
- APL_DATAREADY_OUT => APL_DATAREADY_OUT(2*i+1),
- APL_READ_IN => APL_READ_IN(2*i+1),
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT(2*i+1),
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_LENGTH_IN => x"FFFF",
- APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8),
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
- INT_MASTER_DATA_OUT => tmp_apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i),
- INT_MASTER_DATAREADY_IN => '0',
- INT_MASTER_DATA_IN => (others => '0'),
- INT_MASTER_PACKET_NUM_IN => (others => '0'),
- INT_MASTER_READ_OUT => open,
- INT_SLAVE_DATAREADY_OUT => open,
- INT_SLAVE_DATA_OUT => open,
- INT_SLAVE_PACKET_NUM_OUT => open,
- INT_SLAVE_READ_IN => '1',
- INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
- INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i),
- CTRL_SEQNR_RESET => '0',
- -- Status and control port
- STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32),
- STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32)
- );
- end generate;
- gen_auto_answer : if AUTO_ANSWER_INCOMING_REQUESTS(i) = c_YES generate
- DAT_ACTIVE_API: trb_net16_api_base
- generic map (
- API_TYPE => c_API_ACTIVE,
- FIFO_TO_INT_DEPTH => c_FIFO_BRAM,
- FIFO_TO_APL_DEPTH => c_FIFO_BRAM,
- FORCE_REPLY => cfg_FORCE_REPLY(i),
- SBUF_VERSION => 0,
- USE_VENDOR_CORES => c_YES,
- SECURE_MODE_TO_APL => c_YES,
- SECURE_MODE_TO_INT => c_YES,
- APL_WRITE_ALL_WORDS => c_YES,
- BROADCAST_BITMASK => x"FF"
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET_i,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => APL_DATA_IN((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH),
- APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH),
- APL_DATAREADY_IN => APL_DATAREADY_IN(2*i+1),
- APL_READ_OUT => APL_READ_OUT(2*i+1),
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(2*i+1),
- APL_DTYPE_IN => APL_DTYPE_IN((2*i+2)*4-1 downto (2*i+1)*4),
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((2*i+2)*32-1 downto (2*i+1)*32),
- APL_SEND_IN => APL_SEND_IN(2*i+1),
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((2*i+2)*16-1 downto (2*i+1)*16),
- -- Receiver port
- APL_DATA_OUT => APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH),
- APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH),
- APL_TYP_OUT => APL_TYP_OUT((2*i+2)*3-1 downto (2*i+1)*3),
- APL_DATAREADY_OUT => APL_DATAREADY_OUT(2*i+1),
- APL_READ_IN => APL_READ_IN(2*i+1),
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT(2*i+1),
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_LENGTH_IN => x"FFFF",
- APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8),
- APL_FIFO_COUNT_OUT => APL_FIFO_COUNT_OUT((2*i+1)*11+10 downto (2*i+1)*11),
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
- INT_MASTER_DATA_OUT => tmp_apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i),
- INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
- INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_OUT => buf_to_apl_INIT_READ(i),
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
- INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i),
- INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
- INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i),
- CTRL_SEQNR_RESET => '0',
- -- Status and control port
- STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32),
- STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32)
- );
-
-
-
-
-
-
- APL_READ_OUT(2*i) <= '0';
- APL_DATAREADY_OUT(2*i) <= '0';
- APL_RUN_OUT(2*i) <= '0';
- APL_SEQNR_OUT(2*i*8+7 downto 2*i*8) <= (others => '0');
- APL_DATA_OUT(2*i*c_DATA_WIDTH+15 downto 2*i*c_DATA_WIDTH) <= (others => '0');
- APL_PACKET_NUM_OUT(2*i*c_NUM_WIDTH+2 downto 2*i*c_NUM_WIDTH) <= (others => '0');
- APL_TYP_OUT(2*i*3+2 downto 2*i*3) <= (others => '0');
- APL_FIFO_COUNT_OUT(2*i*11+10 downto 2*i*11) <= (others => '0');
- buf_api_stat_fifo_to_int(2*i*32+31 downto 2*i*32) <= (others => '0');
- buf_api_stat_fifo_to_apl(2*i*32+31 downto 2*i*32) <= (others => '0');
-
-
- end generate;
+ generic map (
+ API_TYPE => c_API_ACTIVE,
+ FIFO_TO_INT_DEPTH => c_FIFO_BRAM,
+ FIFO_TO_APL_DEPTH => c_FIFO_BRAM,
+ FORCE_REPLY => cfg_FORCE_REPLY(i),
+ SBUF_VERSION => 0,
+ USE_VENDOR_CORES => c_YES,
+ SECURE_MODE_TO_APL => c_YES,
+ SECURE_MODE_TO_INT => c_YES,
+ APL_WRITE_ALL_WORDS => c_YES,
+ BROADCAST_BITMASK => x"FF"
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET_i,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => APL_DATA_IN(i*16+15 downto i*16),
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN(i*3+2 downto i*3),
+ APL_DATAREADY_IN => APL_DATAREADY_IN(i),
+ APL_READ_OUT => APL_READ_OUT(i),
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(i),
+ APL_DTYPE_IN => APL_DTYPE_IN(i*4+3 downto i*4),
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN(i*32+31 downto i*32),
+ APL_SEND_IN => APL_SEND_IN(i),
+ APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN(i*16+15 downto i*16),
+ -- Receiver port
+ APL_DATA_OUT => APL_DATA_OUT(i*16+15 downto i*16),
+ APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT(i*3+2 downto i*3),
+ APL_TYP_OUT => APL_TYP_OUT(i*3+2 downto i*3),
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT(i),
+ APL_READ_IN => APL_READ_IN(i),
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT(i),
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_LENGTH_IN => x"FFFF",
+ APL_SEQNR_OUT => APL_SEQNR_OUT(i*8+7 downto i*8),
+ APL_FIFO_COUNT_OUT => APL_FIFO_COUNT_OUT(i*11+10 downto i*11),
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
+ INT_MASTER_DATA_OUT => tmp_apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i),
+ INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
+ INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_MASTER_READ_OUT => buf_to_apl_INIT_READ(i),
+ INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
+ INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i),
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
+ INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_SLAVE_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i),
+ CTRL_SEQNR_RESET => '0',
+ -- Status and control port
+ STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int(i*32+31 downto i*32),
+ STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl(i*32+31 downto i*32)
+ );
+
end generate;
gen_no_api : if USE_CHANNELS(i) = c_NO generate
- APL_READ_OUT(2*i+1) <= '1';
- APL_READ_OUT(2*i) <= '1';
- APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i)*c_DATA_WIDTH) <= (others => '0');
- APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i)*c_NUM_WIDTH) <= (others => '0');
- APL_TYP_OUT((2*i+2)*3-1 downto (2*i)*3) <= (others => '0');
- APL_DATAREADY_OUT(2*i+1) <= '0';
- APL_DATAREADY_OUT(2*i) <= '0';
- APL_RUN_OUT(2*i+1) <= '0';
- APL_RUN_OUT(2*i) <= '0';
- APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i)*8) <= (others => '0');
- buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i)*32) <= (others => '0');
- buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i)*32) <= (others => '0');
+ APL_READ_OUT(i) <= '1';
+ APL_DATA_OUT(i*16+15 downto i*16) <= (others => '0');
+ APL_PACKET_NUM_OUT(i*3+2 downto i*3) <= (others => '0');
+ APL_TYP_OUT(i*3+2 downto i*3) <= (others => '0');
+ APL_DATAREADY_OUT(i) <= '0';
+ APL_RUN_OUT(i) <= '0';
+ APL_SEQNR_OUT(i*8+7 downto i*8) <= (others => '0');
+ buf_api_stat_fifo_to_int(i*32+31 downto i*32) <= (others => '0');
+ buf_api_stat_fifo_to_apl(i*32+31 downto i*32) <= (others => '0');
tmp_apl_to_buf_init_data(i*16+15 downto i*16) <= (others => '0');
- APL_FIFO_COUNT_OUT(2*i*11+21 downto 2*i*11) <= (others => '0');
+ APL_FIFO_COUNT_OUT(i*11+10 downto i*11) <= (others => '0');
end generate;
end generate;
CLK => CLK,
RESET => RESET_i,
CLK_EN => CLK_EN,
- APL_DATA_OUT => APL_DATA_IN,
- APL_PACKET_NUM_OUT => APL_PACKET_NUM_IN,
- APL_DATAREADY_OUT => APL_DATAREADY_IN,
- APL_READ_IN => APL_READ_OUT,
+ APL_DATA_OUT => APL_DATA_IN,
+ APL_PACKET_NUM_OUT => APL_PACKET_NUM_IN,
+ APL_DATAREADY_OUT => APL_DATAREADY_IN,
+ APL_READ_IN => APL_READ_OUT,
APL_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_IN,
APL_DTYPE_OUT => APL_DTYPE_IN,
APL_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_IN,
- APL_SEND_OUT => APL_SEND_IN,
- APL_DATA_IN => APL_DATA_OUT,
- APL_PACKET_NUM_IN => APL_PACKET_NUM_OUT,
- APL_TYP_IN => APL_TYP_OUT,
- APL_DATAREADY_IN => APL_DATAREADY_OUT,
- APL_READ_OUT => APL_READ_IN,
- APL_RUN_IN => APL_RUN_OUT,
- APL_SEQNR_IN => APL_SEQNR_OUT,
+ APL_SEND_OUT => APL_SEND_IN,
+ APL_DATA_IN => APL_DATA_OUT,
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_OUT,
+ APL_TYP_IN => APL_TYP_OUT,
+ APL_DATAREADY_IN => APL_DATAREADY_OUT,
+ APL_READ_OUT => APL_READ_IN,
+ APL_RUN_IN => APL_RUN_OUT,
+ APL_SEQNR_IN => APL_SEQNR_OUT,
APL_TARGET_ADDRESS_OUT => APL_TARGET_ADDRESS_IN,
- APL_FIFO_COUNT_IN => APL_FIFO_COUNT_OUT,
+ APL_FIFO_COUNT_IN => APL_FIFO_COUNT_OUT,
EXT_TRIGGER_INFO => reg_extended_trigger_information,
- BUS_ADDR_IN => BUS_ADDR_IN,
- BUS_WDAT_IN => BUS_WDAT_IN,
- BUS_RDAT_OUT => BUS_RDAT_OUT,
- BUS_SEL_IN => BUS_SEL_IN,
- BUS_WE_IN => BUS_WE_IN,
- BUS_CYC_IN => BUS_CYC_IN,
- BUS_STB_IN => BUS_STB_IN,
- BUS_LOCK_IN => BUS_LOCK_IN,
--- BUS_CTI_IN => BUS_CTI_IN,
- BUS_ACK_OUT => BUS_ACK_OUT,
- SEND_RESET_OUT => SEND_RESET_OUT,
+ BUS_ADDR_IN => BUS_ADDR_IN,
+ BUS_WDAT_IN => BUS_WDAT_IN,
+ BUS_RDAT_OUT => BUS_RDAT_OUT,
+ BUS_SEL_IN => BUS_SEL_IN,
+ BUS_WE_IN => BUS_WE_IN,
+ BUS_CYC_IN => BUS_CYC_IN,
+ BUS_STB_IN => BUS_STB_IN,
+ BUS_LOCK_IN => BUS_LOCK_IN,
+ BUS_ACK_OUT => BUS_ACK_OUT,
+ SEND_RESET_OUT => SEND_RESET_OUT,
STAT => STAT,
CTRL => (others => '0')
);
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all;
+
+entity trb_net_bridge_pcie_endpoint_hub is
+ generic(
+ NUM_LINKS : integer range 1 to 4 := 2;
+ USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
+ COMPILE_TIME : std_logic_vector(31 downto 0) := (others => '0')
+ );
+ port(
+ RESET : in std_logic;
+ CLK : in std_logic;
+
+ BUS_ADDR_IN : in std_logic_vector(31 downto 0);
+ BUS_WDAT_IN : in std_logic_vector(31 downto 0);
+ BUS_RDAT_OUT : out std_logic_vector(31 downto 0);
+ BUS_SEL_IN : in std_logic_vector(3 downto 0);
+ BUS_WE_IN : in std_logic;
+ BUS_CYC_IN : in std_logic;
+ BUS_STB_IN : in std_logic;
+ BUS_LOCK_IN : in std_logic;
+ BUS_ACK_OUT : out std_logic;
+
+ SPI_CLK_OUT : out std_logic;
+ SPI_D_OUT : out std_logic;
+ SPI_D_IN : in std_logic;
+ SPI_CE_OUT : out std_logic;
+
+ MED_DATAREADY_IN : in std_logic_vector (NUM_LINKS-1 downto 0);
+ MED_DATA_IN : in std_logic_vector (16*NUM_LINKS-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (3*NUM_LINKS-1 downto 0);
+ MED_READ_OUT : out std_logic_vector (NUM_LINKS-1 downto 0);
+
+ MED_DATAREADY_OUT : out std_logic_vector (NUM_LINKS-1 downto 0);
+ MED_DATA_OUT : out std_logic_vector (16*NUM_LINKS-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector (3*NUM_LINKS-1 downto 0);
+ MED_READ_IN : in std_logic_vector (NUM_LINKS-1 downto 0);
+
+ MED_STAT_OP_IN : in std_logic_vector (16*NUM_LINKS-1 downto 0);
+ MED_CTRL_OP_OUT : out std_logic_vector (16*NUM_LINKS-1 downto 0);
+
+ SEND_RESET_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector (31 downto 0)
+ );
+end entity;
+
+--address range is 100 to FFF
+-- (c is channel number * 2 + 1 if active part)
+
+--sending data. sending is released when 1c0 is written
+--1c0 wr (3..0) Dtype (8) short transfer sender_control 25bit used
+-- (31..16) target address
+--1c2 wr Errorbits sender_error 32bit used
+--1c3 w sender data fifo sender_data 16bit used
+--1c5 wr Extended Trigger Information sender_trigger_information 16bit
+--1cF r status (0)transfer running sender_status 1bit used
+
+--received data
+--2c3 r receiver data fifo, (20..18)type receiver_data 16bit used
+--2c4 r receiver fifo status (9..0 datacount, 16 full, 17 empty)
+
+
+--3c0 (7..0) seq_num apis_tatus
+
+
+--7c0 DMA Address dma_address(31..0)
+--7c1 DMA Buffer Size dma_buffer(31..0)
+-- write : size of available buffer in RAM (byte)
+-- read : remaining buffer size (i.e. how many bytes have been written)
+--7c2 DMA Control/Status dma_control
+-- (0) write: enable DMA / read: '1' while DMA active, '0' after DMA finished
+
+architecture trb_net_bridge_pcie_endpoint_hub_arch of trb_net_bridge_pcie_endpoint_hub is
+
+ signal reset_i : std_logic;
+ signal clk_en : std_logic;
+
+ signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0);
+ signal apl_to_buf_INIT_DATA : std_logic_vector (3*c_DATA_WIDTH downto 0);
+ signal tmp_apl_to_buf_INIT_DATA : std_logic_vector (3*c_DATA_WIDTH downto 0);
+ signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (3*c_NUM_WIDTH downto 0);
+ signal apl_to_buf_INIT_READ : std_logic_vector(3 downto 0);
+
+ signal buf_to_apl_INIT_DATAREADY: std_logic_vector(3 downto 0);
+ signal buf_to_apl_INIT_DATA : std_logic_vector (3*c_DATA_WIDTH downto 0);
+ signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (3*c_NUM_WIDTH downto 0);
+ signal buf_to_apl_INIT_READ : std_logic_vector(3 downto 0);
+
+ signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(3 downto 0);
+ signal apl_to_buf_REPLY_DATA : std_logic_vector (3*c_DATA_WIDTH downto 0);
+ signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (3*c_NUM_WIDTH downto 0);
+ signal apl_to_buf_REPLY_READ : std_logic_vector(3 downto 0);
+
+ signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(3 downto 0);
+ signal buf_to_apl_REPLY_DATA : std_logic_vector (3*c_DATA_WIDTH downto 0);
+ signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (3*c_NUM_WIDTH downto 0);
+ signal buf_to_apl_REPLY_READ : std_logic_vector(3 downto 0);
+
+
+
+ signal common_ctrl : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal common_stat : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal my_address : std_logic_vector(15 downto 0);
+ signal timer_ticks : std_logic_vector(1 downto 0);
+ signal hub_ctrl_debug : std_logic_vector(31 downto 0);
+
+
+ signal apl_stat : std_logic_vector(31 downto 0);
+
+ signal apl_data_in : std_logic_vector(3*16-1 downto 0);
+ signal apl_packet_num_in : std_logic_vector(3*3-1 downto 0);
+ signal apl_dataready_in : std_logic_vector(3-1 downto 0);
+ signal apl_read_out : std_logic_vector(3-1 downto 0);
+ signal apl_short_transfer_in : std_logic_vector(3-1 downto 0);
+ signal apl_dtype_in : std_logic_vector(3*4-1 downto 0);
+ signal apl_send_in : std_logic_vector(3-1 downto 0);
+ signal apl_data_out : std_logic_vector(3*16-1 downto 0);
+ signal apl_packet_num_out : std_logic_vector(3*3-1 downto 0);
+ signal apl_typ_out : std_logic_vector(3*3-1 downto 0);
+ signal apl_dataready_out : std_logic_vector(3-1 downto 0);
+ signal apl_read_in : std_logic_vector(3-1 downto 0);
+ signal apl_run_out : std_logic_vector(3-1 downto 0);
+ signal apl_seqnr_out : std_logic_vector(3*8-1 downto 0);
+ signal apl_target_address_out : std_logic_vector(3*16-1 downto 0);
+ signal apl_error_pattern_in : std_logic_vector(3*32-1 downto 0);
+ signal apl_target_address_in : std_logic_vector(3*16-1 downto 0);
+ signal apl_fifo_count_out : std_logic_vector(3*11-1 downto 0);
+ signal apl_my_address_in : std_logic_vector(15 downto 0);
+ signal next_apl_send_in : std_logic_vector(2 downto 0);
+
+ signal buf_api_stat_fifo_to_int : std_logic_vector(3*32-1 downto 0);
+ signal buf_api_stat_fifo_to_apl : std_logic_vector(3*32-1 downto 0);
+ signal reg_extended_trigger_information : std_logic_vector(15 downto 0);
+
+
+ signal fifo_net_to_pci_read : std_logic_vector(3 downto 0);
+ signal fifo_net_to_pci_dout : std_logic_vector(32*4-1 downto 0);
+ signal fifo_net_to_pci_valid_read : std_logic_vector(3 downto 0);
+ signal fifo_net_to_pci_empty : std_logic_vector(3 downto 0);
+ signal sender_control : std_logic_vector(32*4-1 downto 0);
+ signal sender_target : std_logic_vector(32*4-1 downto 0);
+ signal sender_error : std_logic_vector(32*4-1 downto 0);
+ signal sender_status : std_logic_vector(32*4-1 downto 0);
+ signal api_status : std_logic_vector(32*4-1 downto 0);
+
+ signal channel_address : integer range 0 to 3;
+
+ signal bus_ack_i : std_logic := '0';
+ signal bus_data_i : std_logic_vector(31 downto 0) := (others => '0');
+ signal bus_read_i : std_logic := '0';
+ signal bus_write_i : std_logic := '0';
+ signal bus_stb_rising : std_logic := '0';
+ signal bus_stb_last : std_logic := '0';
+ signal bus_write_last : std_logic := '0';
+ signal bus_read_last : std_logic := '0';
+
+ signal send_reset_counter : unsigned(10 downto 0);
+
+ signal bus_spi_read_i : std_logic;
+ signal bus_spi_write_i : std_logic;
+ signal bus_spi_ack_i : std_logic;
+ signal bus_spi_data_i : std_logic_vector(31 downto 0);
+
+begin
+
+ RESET_i <= RESET;
+ APL_MY_ADDRESS_IN <= x"FCCC";
+
+ THE_HUB : trb_net16_hub_base
+ generic map (
+ --hub control
+ INIT_ADDRESS => x"FC00",
+ COMPILE_TIME => COMPILE_TIME,
+ COMPILE_VERSION => (others => '0'),
+ HARDWARE_VERSION => x"73000000",
+ HUB_CTRL_BROADCAST_BITMASK => x"FF",
+ CLOCK_FREQUENCY => 150,
+ USE_ONEWIRE => c_NO,
+ BROADCAST_SPECIAL_ADDR => x"FF",
+ MII_NUMBER => NUM_LINKS,
+ MII_IS_UPLINK => (NUM_LINKS => c_YES, NUM_LINKS+1 => c_YES, others => c_NO), --NUM_LINKS => c_YES, NUM_LINKS+1 => c_YES,
+ MII_IS_DOWNLINK => (others => c_YES), --NUM_LINKS => c_YES, NUM_LINKS+1 => c_YES,
+ MII_IS_UPLINK_ONLY => (others => c_NO), --NUM_LINKS => c_YES,
+ INIT_ENDPOINT_ID => x"0001",
+ INT_NUMBER => 3,
+ INT_CHANNELS => (0=>0,1=>1,2=>3,others=>0)
+ )
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => '1',
+
+ --Media interfacces
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_PACKET_NUM_OUT=> MED_PACKET_NUM_OUT,
+ MED_READ_IN => MED_READ_IN,
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
+ MED_READ_OUT => MED_READ_OUT,
+ MED_STAT_OP => MED_STAT_OP_IN,
+ MED_CTRL_OP => MED_CTRL_OP_OUT,
+
+ INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY,
+ INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA,
+ INT_INIT_PACKET_NUM_OUT => buf_to_apl_INIT_PACKET_NUM,
+ INT_INIT_READ_IN => buf_to_apl_INIT_READ,
+ INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY,
+ INT_INIT_DATA_IN => apl_to_buf_INIT_DATA,
+ INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM,
+ INT_INIT_READ_OUT => apl_to_buf_INIT_READ,
+ INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY,
+ INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_OUT => buf_to_apl_REPLY_PACKET_NUM,
+ INT_REPLY_READ_IN => buf_to_apl_REPLY_READ,
+ INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY,
+ INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM,
+ INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ,
+ --REGIO INTERFACE
+ REGIO_ADDR_OUT => open,
+ REGIO_READ_ENABLE_OUT => open,
+ REGIO_WRITE_ENABLE_OUT => open,
+ REGIO_DATA_OUT => open,
+ REGIO_DATA_IN => (others => '0'),
+ REGIO_DATAREADY_IN => '0',
+ REGIO_NO_MORE_DATA_IN => '1',
+ REGIO_WRITE_ACK_IN => '0',
+ REGIO_UNKNOWN_ADDR_IN => '1',
+ REGIO_TIMEOUT_OUT => open,
+ TIMER_TICKS_OUT => timer_ticks,
+ ONEWIRE => open,
+ ONEWIRE_MONITOR_IN => '0',
+ ONEWIRE_MONITOR_OUT=> open,
+ MY_ADDRESS_OUT => my_address,
+ COMMON_CTRL_REGS => common_ctrl,
+ COMMON_STAT_REGS => common_stat,
+ MPLEX_CTRL => (others => '0'),
+ CTRL_DEBUG => hub_ctrl_debug,
+ STAT_DEBUG => open
+ );
+
+ hub_ctrl_debug(2 downto 0) <= not ERROR_OK;
+ hub_ctrl_debug(31 downto 3) <= (others => '0');
+
+
+ gen_pas_apis : for i in 0 to 2 generate
+ DAT_ACTIVE_API: trb_net16_api_base
+ generic map (
+ API_TYPE => c_API_ACTIVE,
+ FIFO_TO_INT_DEPTH => c_FIFO_BRAM,
+ FIFO_TO_APL_DEPTH => c_FIFO_BRAM,
+ FORCE_REPLY => cfg_FORCE_REPLY(i),
+ SBUF_VERSION => 0,
+ USE_VENDOR_CORES => c_YES,
+ SECURE_MODE_TO_APL => c_YES,
+ SECURE_MODE_TO_INT => c_YES,
+ APL_WRITE_ALL_WORDS => c_YES,
+ BROADCAST_BITMASK => x"FF"
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET_i,
+ CLK_EN => '1',
+ -- APL Transmitter port
+ APL_DATA_IN => APL_DATA_IN(i*16+15 downto i*16),
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN(i*3+2 downto i*3),
+ APL_DATAREADY_IN => APL_DATAREADY_IN(i),
+ APL_READ_OUT => APL_READ_OUT(i),
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(i),
+ APL_DTYPE_IN => APL_DTYPE_IN(i*4+3 downto i*4),
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN(i*32+31 downto i*32),
+ APL_SEND_IN => APL_SEND_IN(i),
+ APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN(i*16+15 downto i*16),
+ -- Receiver port
+ APL_DATA_OUT => APL_DATA_OUT(i*16+15 downto i*16),
+ APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT(i*3+2 downto i*3),
+ APL_TYP_OUT => APL_TYP_OUT(i*3+2 downto i*3),
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT(i),
+ APL_READ_IN => APL_READ_IN(i),
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT(i),
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_LENGTH_IN => x"FFFF",
+ APL_SEQNR_OUT => APL_SEQNR_OUT(i*8+7 downto i*8),
+ APL_FIFO_COUNT_OUT => APL_FIFO_COUNT_OUT(i*11+10 downto i*11),
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
+ INT_MASTER_DATA_OUT => tmp_apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i),
+ INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
+ INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_MASTER_READ_OUT => buf_to_apl_INIT_READ(i),
+ INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
+ INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i),
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
+ INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_SLAVE_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i),
+ CTRL_SEQNR_RESET => '0',
+ -- Status and control port
+ STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int(i*32+31 downto i*32),
+ STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl(i*32+31 downto i*32)
+ );
+
+ end generate;
+
+--Add additional word for trigger information
+ apl_to_buf_INIT_DATA(apl_to_buf_INIT_DATA'left downto 16) <= tmp_apl_to_buf_INIT_DATA(apl_to_buf_INIT_DATA'left downto 16);
+
+ proc_add_trigger_info : process(tmp_apl_to_buf_INIT_DATA, apl_to_buf_INIT_PACKET_NUM,reg_extended_trigger_information)
+ begin
+ if apl_to_buf_INIT_PACKET_NUM(2 downto 0) = c_F0 then
+ apl_to_buf_INIT_DATA(15 downto 0) <= reg_extended_trigger_information;
+ else
+ apl_to_buf_INIT_DATA(15 downto 0) <= tmp_apl_to_buf_INIT_DATA(15 downto 0);
+ end if;
+ end process;
+
+ apl_to_buf_INIT_DATAREADY(3) <= '0';
+ apl_to_buf_REPLY_DATAREADY(3) <= '0';
+ apl_to_buf_INIT_READ(3) <= '0';
+ apl_to_buf_REPLY_READ(3) <= '0';
+
+ tmp_apl_to_buf_INIT_DATA(48) <= '0';
+ apl_to_buf_REPLY_DATA(48) <= '0';
+ apl_to_buf_INIT_PACKET_NUM(9) <= '0';
+ apl_to_buf_REPLY_PACKET_NUM(9) <= '0';
+
+
+
+-- APL : trb_net_bridge_pcie_apl
+-- port map(
+-- CLK => CLK,
+-- RESET => RESET_i,
+-- CLK_EN => '1',
+-- APL_DATA_OUT => apl_data_in,
+-- APL_PACKET_NUM_OUT => apl_packet_num_in,
+-- APL_DATAREADY_OUT => apl_dataready_in,
+-- APL_READ_IN => apl_read_out,
+-- APL_SHORT_TRANSFER_OUT => apl_short_transfer_in,
+-- APL_DTYPE_OUT => apl_dtype_in,
+-- APL_ERROR_PATTERN_OUT => apl_error_pattern_in,
+-- APL_SEND_OUT => apl_send_in,
+-- APL_DATA_IN => apl_data_out,
+-- APL_PACKET_NUM_IN => apl_packet_num_out,
+-- APL_TYP_IN => apl_typ_out,
+-- APL_DATAREADY_IN => apl_dataready_out,
+-- APL_READ_OUT => apl_read_in,
+-- APL_RUN_IN => apl_run_out,
+-- APL_SEQNR_IN => apl_seqnr_out,
+-- APL_TARGET_ADDRESS_OUT => apl_target_address_in,
+-- APL_FIFO_COUNT_IN => apl_fifo_count_out,
+-- EXT_TRIGGER_INFO => reg_extended_trigger_information,
+-- BUS_ADDR_IN => BUS_ADDR_IN,
+-- BUS_WDAT_IN => BUS_WDAT_IN,
+-- BUS_RDAT_OUT => BUS_RDAT_OUT,
+-- BUS_SEL_IN => BUS_SEL_IN,
+-- BUS_WE_IN => BUS_WE_IN,
+-- BUS_CYC_IN => BUS_CYC_IN,
+-- BUS_STB_IN => BUS_STB_IN,
+-- BUS_LOCK_IN => BUS_LOCK_IN,
+-- BUS_ACK_OUT => BUS_ACK_OUT,
+-- SEND_RESET_OUT => SEND_RESET_OUT,
+-- STAT => open,
+-- CTRL => (others => '0')
+-- );
+
+
+--------------------------------
+-- r/w registers
+--------------------------------
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ bus_stb_last <= BUS_STB_IN;
+ bus_read_last <= bus_read_i;
+ bus_write_last <= bus_write_i;
+ end if;
+ end process;
+
+ bus_stb_rising <= BUS_STB_IN and not bus_stb_last;
+ bus_read_i <= not BUS_WE_IN and bus_stb_rising and BUS_ADDR_IN(23 downto 16) = x"00";
+ bus_write_i <= BUS_WE_IN and bus_stb_rising and BUS_ADDR_IN(23 downto 16) = x"00";
+
+ bus_spi_read_i <= not BUS_WE_IN and bus_stb_rising and BUS_ADDR_IN(23 downto 16) = x"01";
+ bus_spi_write_i <= BUS_WE_IN and bus_stb_rising and BUS_ADDR_IN(23 downto 16) = x"01";
+
+ channel_address <= to_integer(unsigned(BUS_ADDR_IN(6 downto 5)));
+
+ read_regs : process(sender_control, sender_target, sender_error, sender_status, apl_fifo_count_out,
+ BUS_ADDR_IN, api_status, fifo_net_to_pci_empty, bus_data_i, channel_address, fifo_net_to_pci_dout)
+ variable tmp : std_logic_vector(7 downto 0);
+ begin
+ bus_data_i <= (others => '0');
+ tmp := BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0);
+ case tmp is --middle nibble is dont care
+ when x"10" =>
+ bus_data_i <= sender_control(channel_address*32+31 downto channel_address*32);
+ when x"12" =>
+ bus_data_i <= sender_error(channel_address*32+31 downto channel_address*32);
+ when x"15" =>
+ if channel_address = 0 then
+ bus_data_i <= x"0000" & reg_extended_trigger_information;
+ else
+ bus_data_i <= x"10000000";
+ end if;
+ when x"1F" =>
+ bus_data_i <= sender_status(channel_address*32+31 downto channel_address*32);
+ when x"23" =>
+ bus_data_i <= fifo_net_to_pci_dout(channel_address*32+31 downto channel_address*32);
+ when x"24" =>
+ bus_data_i <= x"000" & "00" & fifo_net_to_pci_empty(channel_address) & '0'
+ & "00000" & apl_fifo_count_out(11*channel_address+10 downto 11*channel_address);
+ when x"30" =>
+ bus_data_i <= api_status(channel_address*32+31 downto channel_address*32);
+ when others =>
+ bus_data_i <= x"10000000"; --"1000000000000000000" & CTRL(31 downto 19);
+ end case;
+ end process;
+
+
+ write_regs : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ sender_control <= (others => '0');
+ sender_target <= (others => '0');
+ sender_error <= (others => '0');
+ else
+ if bus_write_i = '1' and BUS_ADDR_IN(11 downto 8) = x"1" and USE_CHANNELS(channel_address) = c_YES then
+ case BUS_ADDR_IN(3 downto 0) is
+ --middle nibble is dont care
+ when x"0" =>
+ sender_control(channel_address*32+31 downto channel_address*32) <= BUS_WDAT_IN(31 downto 0);
+ when x"1" =>
+ sender_target(channel_address*32+15 downto channel_address*32) <= BUS_WDAT_IN(15 downto 0);
+ when x"2" =>
+ sender_error(channel_address*32+31 downto channel_address*32) <= BUS_WDAT_IN(31 downto 0);
+ when x"5" =>
+ if channel_address = 0 then
+ reg_extended_trigger_information <= BUS_WDAT_IN(15 downto 0);
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+--------------------------------
+-- connection to API
+--------------------------------
+
+ proc_api_connect : process(apl_seqnr_out, apl_run_out, BUS_ADDR_IN, bus_write_last, bus_write_i,
+ sender_control, sender_error, fifo_net_to_pci_read, apl_dataready_out,
+ fifo_net_to_pci_valid_read, apl_packet_num_out, sender_target)
+ begin
+ api_status <= (others => '0');
+ sender_status <= (others => '0');
+ next_apl_send_in <= (others => '0');
+ apl_dataready_in <= (others => '0');
+ api_status(0*32+7 downto 0*32) <= apl_seqnr_out(0*8+7 downto 0*8);
+ api_status(1*32+7 downto 1*32) <= apl_seqnr_out(1*8+7 downto 1*8);
+ api_status(3*32+7 downto 3*32) <= apl_seqnr_out(2*8+7 downto 2*8);
+ sender_status(0*32) <= apl_run_out(0);
+ sender_status(1*32) <= apl_run_out(1);
+ sender_status(3*32) <= apl_run_out(2);
+ if BUS_ADDR_IN(11 downto 0) = x"110" and bus_write_last = '1' then
+ next_apl_send_in(0) <= '1';
+ end if;
+ if BUS_ADDR_IN(11 downto 0) = x"130" and bus_write_last = '1' then
+ next_apl_send_in(1) <= '1';
+ end if;
+ if BUS_ADDR_IN(11 downto 0) = x"170" and bus_write_last = '1' then
+ next_apl_send_in(2) <= '1';
+ end if;
+ if BUS_ADDR_IN(11 downto 0) = x"113" and bus_write_i = '1' then
+ apl_dataready_in(0) <= '1';
+ end if;
+ if BUS_ADDR_IN(11 downto 0) = x"133" and bus_write_i = '1' then
+ apl_dataready_in(1) <= '1';
+ end if;
+ if BUS_ADDR_IN(11 downto 0) = x"173" and bus_write_i = '1' then
+ apl_dataready_in(2) <= '1';
+ end if;
+
+ apl_data_in <= BUS_WDAT_IN(15 downto 0) & BUS_WDAT_IN(15 downto 0) & BUS_WDAT_IN(15 downto 0);
+ apl_packet_num_in <= '0' & BUS_WDAT_IN(17 downto 16) & '0' & BUS_WDAT_IN(17 downto 16) & '0' & BUS_WDAT_IN(17 downto 16);
+ apl_short_transfer_in <= sender_control(96+8) & sender_control(32+8) & sender_control(8);
+ apl_error_pattern_in <= sender_error(127 downto 96) & sender_error(63 downto 32) & sender_error(31 downto 0);
+ apl_target_address_in <= sender_control(127 downto 112) & sender_control(63 downto 48) & sender_control(31 downto 16);
+ -- apl_target_address_in <= sender_target(111 downto 96) & sender_target(47 downto 32) & sender_target(15 downto 0);
+ apl_dtype_in <= sender_control(99 downto 96) & sender_control(35 downto 32) & sender_control(3 downto 0);
+
+ apl_read_in <= fifo_net_to_pci_read(3) & fifo_net_to_pci_read(1) & fifo_net_to_pci_read(0);
+ fifo_net_to_pci_empty <= not (apl_dataready_out(2) & '0' & apl_dataready_out(1) & apl_dataready_out(0));
+ fifo_net_to_pci_dout(31 downto 0) <= "0000000" & fifo_net_to_pci_valid_read(0) & "000000"
+ & apl_packet_num_out(2) & apl_packet_num_out(0) & apl_data_out(15 downto 0);
+ fifo_net_to_pci_dout(63 downto 32) <= "0000000" & fifo_net_to_pci_valid_read(1) & "000000"
+ & apl_packet_num_out(5) & apl_packet_num_out(3) & apl_data_out(31 downto 16);
+ fifo_net_to_pci_dout(95 downto 64) <= (others => '0');
+ fifo_net_to_pci_dout(127 downto 96) <= "0000000" & fifo_net_to_pci_valid_read(3) & "000000"
+ & apl_packet_num_out(8) & apl_packet_num_out(6) & apl_data_out(47 downto 32);
+ end process;
+
+
+ proc_fifo_readwrite : process(BUS_ADDR_IN, bus_read_i, channel_address, apl_dataready_out, fifo_net_to_pci_read)
+ begin
+ fifo_net_to_pci_valid_read(0) <= fifo_net_to_pci_read(0) and apl_dataready_out(0);
+ fifo_net_to_pci_valid_read(1) <= fifo_net_to_pci_read(1) and apl_dataready_out(1);
+ fifo_net_to_pci_valid_read(3) <= fifo_net_to_pci_read(3) and apl_dataready_out(2);
+ fifo_net_to_pci_read <= (others => '0');
+ if BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0) = x"23" then
+ fifo_net_to_pci_read(channel_address) <= bus_read_i;
+ end if;
+ end process;
+
+ proc_register_cpu_output : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ apl_send_in <= next_apl_send_in;
+ if bus_spi_ack_i = '1' then
+ BUS_RDAT_OUT <= bus_spi_data_i(31 downto 0);
+ else
+ BUS_RDAT_OUT <= bus_data_i(31 downto 0);
+ end if;
+ BUS_ACK_OUT <= (bus_read_i or bus_write_i) or bus_spi_ack_i;
+ end if;
+ end process;
+
+
+--------------------------------
+-- SPI Flash Programming
+--------------------------------
+-- bus_spi_write_i --strobe
+-- bus_spi_read_i --strobe
+-- BUS_WDAT_IN --32bit write data valid with strobe
+-- BUS_ADDR_IN --15 downto 0 - your address space
+--
+-- bus_spi_ack_i -- ack strobe from SPI handler
+-- bus_spi_data_i -- 32bit data from SPI
+--
+-- SPI_CLK_OUT : out std_logic;
+-- SPI_D_OUT : out std_logic;
+-- SPI_D_IN : in std_logic;
+-- SPI_CE_OUT : out std_logic;
+
+
+--------------------------------
+-- network reset
+--------------------------------
+ SEND_RESET_OUT <= not send_reset_counter(10);
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ send_reset_counter <= (others => '1');
+ elsif BUS_ADDR_IN = x"00000010" and bus_write_i = '1' and BUS_WDAT_IN(15) = '1' then
+ send_reset_counter <= (others => '0');
+ elsif send_reset_counter(10) = '0' then
+ send_reset_counter <= send_reset_counter + to_unsigned(1,1);
+ end if;
+ end if;
+ end process;
+
+
+
+end architecture;
\ No newline at end of file
jspc29 / trbnet.git / commitdiff