smaller bugfixes to slow control addresses.

diff --git a/mupix/Mupix8/sources/HitbusHistogram.vhd b/mupix/Mupix8/sources/HitbusHistogram.vhd
index 191ddb1efe9239226e4bd705dc6b551dd2e0145a..a8812593493e6ba7451300048c8af5b04ca7a38c 100644 (file)
--- a/mupix/Mupix8/sources/HitbusHistogram.vhd
+++ b/mupix/Mupix8/sources/HitbusHistogram.vhd
@@ -246,28 +246,28 @@ begin
 
       elsif SLV_READ_IN = '1' then
         case SLV_ADDR_IN is
-          when x"0800" =>
+          when x"0070" =>
             SLV_DATA_OUT <= histo_ctrl;
             SLV_ACK_OUT  <= '1';
-          when x"0801" =>
+          when x"0071" =>
             SLV_DATA_OUT(31 downto 16)                <= (others => '0');
             SLV_DATA_OUT(HistogramRange - 1 downto 0) <= hitbus_HistoWrAddr;
             SLV_ACK_OUT                               <= '1';
-          when x"0802" =>
+          when x"0072" =>
             SLV_DATA_OUT(31 downto 16)                <= (others => '0');
             SLV_DATA_OUT(HistogramRange - 1 downto 0) <= latency_histoWraddr;
             SLV_ACK_OUT                               <= '1';
-          when x"0803" =>
+          when x"0073" =>
             ReadHisto         <= '1';
             ReadAddr_i        <= std_logic_vector(readcounter);
             reading_histo_mem <= '1';
-          when x"0804" =>
+          when x"0074" =>
             SLV_DATA_OUT(HistogramRange - 1 downto 0) <= std_logic_vector(readcounter);
             SLV_ACK_OUT                               <= '1';
-          when x"0805" =>
+          when x"0075" =>
             SLV_DATA_OUT(0) <= hitbus;
             SLV_ACK_OUT <= '1';
-        when x"0806" =>
+        when x"0076" =>
                SLV_DATA_OUT(HistogramRange - 1 downto 0) <= std_logic_vector(hitbus_wait);
                SLV_ACK_OUT <= '1';
           when others =>
@@ -276,13 +276,13 @@ begin
 
       elsif SLV_WRITE_IN = '1' then
         case SLV_ADDR_IN is
-          when x"0800" =>
+          when x"0070" =>
             histo_ctrl  <= SLV_DATA_IN;
             SLV_ACK_OUT <= '1';
-          when x"0804" =>
+          when x"0074" =>
             readcounter <= unsigned(SLV_DATA_IN(HistogramRange - 1 downto 0));
             SLV_ACK_OUT <= '1';
-          when x"0806" => 
+          when x"0076" => 
                hitbus_wait <= unsigned(SLV_DATA_IN(HistogramRange - 1 downto 0));
                SLV_ACK_OUT <= '1';     
           when others =>

diff --git a/mupix/Mupix8/sources/MupixBoard.vhd b/mupix/Mupix8/sources/MupixBoard.vhd
index 3e86b3696346cbc16f87295d3cb7c7fcbc804bc8..ee3d9aee7944d391cad58de1cfce70a16a34b6d9 100644 (file)
--- a/mupix/Mupix8/sources/MupixBoard.vhd
+++ b/mupix/Mupix8/sources/MupixBoard.vhd
@@ -289,14 +289,14 @@ begin  -- Behavioral
           1      => x"0080",            -- Mupix DAC and Pixel Control
           2      => x"0090",            -- Board Control
           3      => x"0100",            -- mupix readout
-          4      => x"0120",            -- mupix readout
+          4      => x"0120",            -- trigger handler
           others => x"0000"),
         PORT_ADDR_MASK => (
           0      => 4,                  -- HitBus Histograms        
           1      => 4,                  -- Mupix DAC and Pixel Control
           2      => 4,                  -- Board Control
-          3      => 8,                  -- mupix readout
-          4      => 8,                  -- mupix readout
+          3      => 4,                  -- mupix readout
+          4      => 4,                  -- trigger handler
           others => 0)
        --PORT_MASK_ENABLE => 1
       )

diff --git a/mupix/Mupix8/sources/MupixDataLink.vhd b/mupix/Mupix8/sources/MupixDataLink.vhd
index f99724387b3f24f34488d94a9c9cb86c0479e5e7..bd663d7f84a5d45d97bddc89dc6b7456b2283658 100644 (file)
--- a/mupix/Mupix8/sources/MupixDataLink.vhd
+++ b/mupix/Mupix8/sources/MupixDataLink.vhd
@@ -354,12 +354,12 @@ begin
                                SLV_NO_MORE_DATA_OUT <= '0';
                                SLV_ACK_OUT          <= '0';
                        else
-                               SLV_DATA_OUT         <= (others => '0');
-                               SLV_UNKNOWN_ADDR_OUT <= '0';
-                               SLV_NO_MORE_DATA_OUT <= '0';
-                               SLV_ACK_OUT          <= '0';
-                               reset_error_cnt_i    <= '0';
-                               --TODO: write this with channel select and not explicitly with registers
+                SLV_DATA_OUT         <= (others => '0');
+                SLV_UNKNOWN_ADDR_OUT <= '0';
+                SLV_NO_MORE_DATA_OUT <= '0';
+                SLV_ACK_OUT          <= '0';
+                reset_error_cnt_i    <= '0';
+                
                                if SLV_READ_IN = '1' then
                                        case SLV_ADDR_IN is
                                                when x"0000" => --read counters are already synchronous to trb system clock
@@ -402,18 +402,24 @@ begin
                                                when x"000b" =>
                                                        SLV_DATA_OUT <= std_logic_vector(error_cnt(3));
                                                        SLV_ACK_OUT  <= '1';
+                        when x"000c" =>
+                            SLV_DATA_OUT <= x"aabbccdd";
+                                                       SLV_ACK_OUT  <= '1';
                                                when others =>
                                                        SLV_UNKNOWN_ADDR_OUT <= '1';
                                        end case;
+                end if;
                                        
-                               elsif SLV_WRITE_IN = '1' then
+                               if SLV_WRITE_IN = '1' then
                                        case SLV_ADDR_IN is
                                                when x"000c" => 
                                                        reset_error_cnt_i <= SLV_DATA_IN(0);
+                                                       SLV_ACK_OUT       <= '1';
                                                when others => 
                                                        SLV_UNKNOWN_ADDR_OUT <= '1';
                                        end case;
                                end if;
+                               
                        end if;
                end if;
        end process SLV_BUS;

diff --git a/mupix/Mupix8/trb3_periph.vhd b/mupix/Mupix8/trb3_periph.vhd
index fe6836b33c953cad17ab8cb260a54d9983d77835..67adcb134b50aa6e2e1430104469a979671a0996 100644 (file)
--- a/mupix/Mupix8/trb3_periph.vhd
+++ b/mupix/Mupix8/trb3_periph.vhd
@@ -367,7 +367,7 @@ architecture trb3_periph_arch of trb3_periph is
   signal time_counter : unsigned(31 downto 0);
 
   -- MuPix Regio Bus
-  signal mu_regio_addr_in_0          : std_logic_vector (15 downto 0);
+  signal mu_regio_addr_in_0          : std_logic_vector (15 downto 0) := (others => '0');
   signal mu_regio_data_in_0          : std_logic_vector (31 downto 0);
   signal mu_regio_data_out_0         : std_logic_vector (31 downto 0);
   signal mu_regio_read_enable_in_0   : std_logic;
@@ -379,7 +379,7 @@ architecture trb3_periph_arch of trb3_periph is
   signal mu_regio_unknown_addr_out_0 : std_logic;
 
   -- MuPix data link Regio Bus
-  signal mupixdata_regio_addr_in_0          : std_logic_vector (15 downto 0);
+  signal mupixdata_regio_addr_in_0          : std_logic_vector (15 downto 0) := (others => '0');
   signal mupixdata_regio_data_in_0          : std_logic_vector (31 downto 0);
   signal mupixdata_regio_data_out_0         : std_logic_vector (31 downto 0);
   signal mupixdata_regio_read_enable_in_0   : std_logic;
@@ -394,7 +394,7 @@ architecture trb3_periph_arch of trb3_periph is
   signal reset_timestamps_i                    : std_logic;
   signal reset_eventcounters_i                 : std_logic;
   signal reset_mupixdata_i                     : std_logic;
-  signal resethandler_regio_addr_in_0          : std_logic_vector (15 downto 0);
+  signal resethandler_regio_addr_in_0          : std_logic_vector (15 downto 0) := (others => '0');
   signal resethandler_regio_data_in_0          : std_logic_vector (31 downto 0);
   signal resethandler_regio_data_out_0         : std_logic_vector (31 downto 0);
   signal resethandler_regio_read_enable_in_0   : std_logic;
@@ -701,7 +701,7 @@ begin
       BUS_ADDR_OUT(3*16+15 downto 3*16+12) => open,
       BUS_TIMEOUT_OUT(3)                   => open,
       BUS_DATA_IN(3*32+31 downto 3*32)     => mupixdata_regio_data_out_0,
-      BUS_DATAREADY_IN(3)                  => mupixdata_regio_dataready_out_0,
+      BUS_DATAREADY_IN(3)                  => mupixdata_regio_ack_out_0,
       BUS_WRITE_ACK_IN(3)                  => mupixdata_regio_ack_out_0,
       BUS_NO_MORE_DATA_IN(3)               => mupixdata_regio_no_more_data_out_0,
       BUS_UNKNOWN_ADDR_IN(3)               => mupixdata_regio_unknown_addr_out_0,