corrected css

diff --git a/xml_spielwiese/MIMOSA26_JTAG_SPEC.xml b/xml_spielwiese/MIMOSA26_JTAG_SPEC.xml
index 2fd9ee1642dd8553dd5b77fa34be5ffa84fac451..d809cb2175517343e2ddee545583c93b914c861c 100644 (file)
--- a/xml_spielwiese/MIMOSA26_JTAG_SPEC.xml
+++ b/xml_spielwiese/MIMOSA26_JTAG_SPEC.xml
@@ -7,7 +7,7 @@
        <description>
 The CONTROL_PIX_REG registers are 40 bits large; they allow setting parameters of the readout controller. These
 registers are reserved for sensor's debugging by the IPHC/IRFU group. A end user has to respect to the default values.
-\t</description>
+</description>
 <field
        name="NU"
        start="36"
@@ -64,7 +64,7 @@ registers are reserved for sensor's debugging by the IPHC/IRFU group. A end user
        <description>
 The CONTROL_SUZE_REG registers are 48 bits large; they allow setting parameters of the readout controller for SUZE.
 We suggest an end user to only use default values except for data stream output parameters
-\t</description>
+</description>
 <field
        name="NU"
        start="46"
@@ -212,7 +212,7 @@ The BIAS_DAC register is 152 bit wide; it sets simultaneously the 19 DAC registe
 As show bellow these 8-bit DACs set voltage and current bias. After reset the register is set to 0, a value which fixes the
 minimum power consumption of the circuit. The current values of the DACs are read while the new values are downloaded
 during the access to the register. An image of the value of each DAC can be measured on its corresponding test pad.
-\t</description>
+</description>
 <field
        name="IKIMO"
        start="144"
@@ -376,7 +376,7 @@ column if it is noisy, by gating Latch signal and setting the output discriminat
 The default value of the DIS_DISCRI register is 0; it means that all discriminators are activated. Setting a bit to 1 disables
 the corresponding discriminator. In MIMOSA26, the DisableLatch&lt;0&gt; is on the left hand side while DisableLatch&lt;1151&gt;
 is on the right hand side.
-\t</description>
+</description>
 <field
        name="DisDiscri"
        start="0"
@@ -396,7 +396,7 @@ The register called Header_Reg includes 4 registers of 16 bits as shown below.
 For both modes according to the register DUALCHANNEL the header and the trailer of each data frame can be
 different. The following table shows the possible Header and the Trailer which ensure the unicity in the data frame. The
 unicity is guaranteed without the Frame counter.
-\t</description>
+</description>
 <field
        name="header0"
        start="48"
@@ -446,7 +446,7 @@ register is read to emulate the discriminators outputs of these two supplementar
 After the initialisation phase (reset), this register is preset to 0.
 
 In MIMOSA26, the LinePatL0Reg &lt;0&gt; is on the left hand side while LinePatL0Reg &lt;1151&gt; is on the right hand side.
-\t</description>
+</description>
 <field
        name="LinePatL0Reg"
        start="0"
@@ -472,7 +472,7 @@ register is read to emulate the discriminators outputs of these two supplementar
 
 In MIMOSA26, the LinePatL1Reg &lt;0&gt; is on the left hand side while LinePatL1Reg &lt;1151&gt; is on the right hand side.
 With Line1_PAT_REG together these two signals will form the elements of the simulated frame given to SUZE part.
-\t</description>
+</description>
 <field
        name="LinePatL1Reg"
        start="0"
@@ -492,7 +492,7 @@ The RO_MODE0 registers are 8 bits large; they allow the user to select specific
 (1) The minimum wide of asynchronous external START signal is 500 ns, and this signal is active at high level.
 (2) When En_ExtStart is disabled, it’s possible to generate internal START by accessing JTAG_Start bit. JTAG_Start
 signal is realized by three JTAG access: First step, this bit is set to 0, second step it is set to 1, and at last it is set to 0.
-\t</description>
+</description>
 <field
        name="EnVDiscriTestDigital"
        start="7"
@@ -564,7 +564,7 @@ signal is realized by three JTAG access: First step, this bit is set to 0, secon
        size="8" >
        <description>
 The RO_MODE1 registers are 8 bits large; they allow selecting specific analogue mode of the chip.
-\t</description>
+</description>
 <field
        name="startframe"
        start="7"
@@ -637,7 +637,7 @@ The RO_MODE1 registers are 8 bits large; they allow selecting specific analogue
        <description>
 The SEQUENCER_PIX_REG registers are 128 bits large; this register contains all parameters to generate readout pixel
 and discriminator sequence.
-\t</description>
+</description>
 <field
        name="DataRdPix"
        start="112"
@@ -702,7 +702,7 @@ and discriminator sequence.
        <description>
 The SEQUENCER_SUZE_REG registers are 160 bits large; this register contains all parameters to generate readout zero
 suppression (SUZE) sequence.
-\t</description>
+</description>
 <field
        name="dckreadpixmux"
        start="144"

diff --git a/xml_spielwiese/styles.css b/xml_spielwiese/styles.css
index 4c9fc8fde7538fae40d501e1252c84850247cdea..85fa1f56ef9c1998e0607f99d33a7bd5dab95889 100644 (file)
--- a/xml_spielwiese/styles.css
+++ b/xml_spielwiese/styles.css
@@ -80,6 +80,15 @@ table.fields td {
 }
 
 
+table.registers td:nth-child(2) {
+  background:lightgrey;
+  }
+
+table.fields td:nth-child(2) {
+  background:#dea;
+  }
+
+
 table.fields td.button_move, table.registers td.button_move {
   background:orange;
   cursor:pointer;