fixed stretch, which works now. Starting to work on Coin now

diff --git a/trigger_coin.vhd b/trigger_coin.vhd
index ee2de1179b50b5e2511f648794add9d0680a585d..6a43c87f95f4d46b1bebf29d218cec293f176ea1 100644 (file)
--- a/trigger_coin.vhd
+++ b/trigger_coin.vhd
@@ -6,9 +6,12 @@ library work;
   use work.trb_net_std.all;
   
   
-entity trg_coin is
+entity trg_coincidence is
   port(
-  
+    clk_in      : in std_logic;
+    signals     : in std_logic_vector(31 downto 0);
+--     reg_inhalt  : in std_logic_vector(31 downto 0);
+    processed_signals   : out std_logic_vector(31 downto 0)
   
   )
 end trg_coin;
@@ -22,9 +25,9 @@ end trg_coin;
   
   
   
-architecture behave of trg_coin is 
+architecture behave of trg_coincidence is 
 
-  SIGNAL ......:std_logic...
+  
   
   
   

diff --git a/trigger_logic.vhd b/trigger_logic.vhd
index 39559d0ae4160c403a3b994e81733c7ecd944224..80b6bd9116f4cdfac3d83871f6db834244df1d42 100644 (file)
--- a/trigger_logic.vhd
+++ b/trigger_logic.vhd
@@ -29,6 +29,7 @@ end entity;
 architecture arch of trigger_logic is
 
 constant CHANNELS : integer := 32;
+constant NEUES : integer := 155;
 
 --Registers
 signal reg_enable1 : std_logic_vector(CHANNELS-1 downto 0):=(others => '0');
@@ -70,7 +71,7 @@ signal str_2_cion : std_logic_vector(CHANNELS-1 downto 0);
 signal coin_2_out : std_logic_vector(CHANNELS-1 downto 0);
 
 signal address_i : integer range 0 to 255;
-
+signal tester : std_logic_vector(CHANNELS-1 downto 0);
 -- 
 
 
@@ -83,6 +84,7 @@ begin
 ---------------------------------------------------------------------------
 
 address_i <= to_integer(unsigned(BUS_RX.addr(7 downto 0)));
+tester <= str_2_cion;
 
 
 PROC_REGS : process begin
@@ -232,7 +234,14 @@ THE_STRETCH: entity work.trg_stretch
   );
 end generate;  
 
-
-  
+-- THE_COIN : entity work.trg_coincidence
+-- 
+--   port map(
+--   clk_in           => CLK,
+--   signals          => str_2_cion,
+-- --   reg_inhalt       => reg_coin1,
+--   processed_signals=> coin_2_out
+--   );
+--   
   
 end architecture;

diff --git a/trigger_strech.vhd b/trigger_strech.vhd
index c2cece5d16a540465f114fd11caee5b275b07d52..bade4ca0517051df51d6cc4e21cf298132ff34b8 100644 (file)
--- a/trigger_strech.vhd
+++ b/trigger_strech.vhd
@@ -18,12 +18,7 @@ end trg_stretch;
   
   
   
-  
-  
-  
-  
-  
-  
+ 
   
 architecture behave of trg_stretch is 
 
@@ -36,31 +31,35 @@ signal pulse_11 : std_logic;                                            -- every
 signal output : std_logic:='0';
 signal tester : unsigned(31 downto 0):= x"00000000";
 signal downcounter : integer range 0 to 1022;
+signal bessererTest : std_logic;
 
 
 begin
   processed_signal<=output;
   stretch_time_int <= to_integer(unsigned(stretch_time(9 downto 0)));                                         -- umschreiben passt noch nicht
   stretch_type_int <= to_integer(unsigned(stretch_type(1 downto 0)));
-  --   output <= '1';
+--   output <= '1';
+  bessererTest <= '1';
 
 PROC_STRETCH_1: process begin
  wait until rising_edge(clk_in);
- if signal_in='1' then
+  if signal_in='1' then
     output<='1';
     downcounter<=stretch_time_int;
 --   elsif stretch_type=x"0" then
-
   elsif signal_in='0' then
+    if stretch_type_int = 0 then 
+      output <= '0';
+    end if;
     if stretch_type_int = 1 then
-  tester<= tester +1 ;
+      tester<= tester +1 ;
       if downcounter> 0 then
         downcounter <= downcounter -1;
       else 
         output<='0';
-     end if;
+      end if;
      end if; 
-  if stretch_type_int= 2 then
+    if stretch_type_int= 2 then
       if downcounter > 0 and pulse_10='1' then
         downcounter<= downcounter -1 ;
       else