SD_LED_YELLOW_OUT : out std_logic;
SD_LED_RED_OUT : out std_logic;
-- Debug
- DEBUG_OUT : out std_logic_vector(255 downto 0)
+ DEBUG_OUT : out std_logic_vector(63 downto 0)
);
end entity gbe_med_interface_single_5G;
end component;
signal sd_rx_clk : std_logic;
- signal sd_tx_clk : std_logic;
signal sd_tx_kcntl : std_logic_vector(0 downto 0);
signal sd_tx_data : std_logic_vector(7 downto 0);
signal xmit : std_logic_vector(0 downto 0);
signal link_tx_ready : std_logic;
signal pll_lol : std_logic;
- signal debug : std_logic_vector(255 downto 0);
+ signal debug : std_logic_vector(63 downto 0);
+ -- for replacing register interface
signal delay_q : std_logic_vector(7 downto 0);
signal pulse : std_logic;
- signal pulse2 : std_logic;
begin
--------------------------------------------------------------------
--------------------------------------------------------------------
--- debug(255 downto 0) <= (others => '0');
DEBUG_OUT <= debug;
-- debug(19..0) are on INTCOM
-- debug(33..20) are on GPIO
CLK_125_OUT <= CLK_125_IN;
CLK_125_RX_OUT <= sd_rx_clk;
+ -- Some notes on clocks: the SerDes uses TX and RX bridge FIFO, with RX FIFO being clocked on
+ -- both read and write side by rx_pclk, and TX FIFO being clocked on write side by txi_clk.
+ -- For TX, we can use local 125MHz clock.
+ -- For RX, the SGMII core implements the CTC FIFO, and by clocking SGMII also by local 125MHz
+ -- (except serdes_recovered_clk, which goes to rx_pclk) we have *everthing* behind the SGMII
+ -- on local 125MHz clock.
+
gbe_serdes: entity serdes_gbe
port map(
-- external I/Os
pll_refclki => CLK_125_IN, -- TX reference clock for PLL
rxrefclk => CLK_125_IN, -- RX reference clock for CDR
txi_clk => CLK_125_IN, -- feeds the TX FIFO
- tx_pclk => sd_tx_clk, -- not really needed?
+ tx_pclk => open, -- not really needed
rx_pclk => sd_rx_clk, -- recovered RX clock, also used on FIFO!
-- TX channel
txdata => sd_tx_data,
tx_serdes_rst_c => '0'
);
+ -- RSL for TX of SerDes, based on extRSL logic
THE_MAIN_TX_RST: main_tx_reset_RS
port map (
CLEAR => rst_dual,
LINK_TX_READY_OUT => link_tx_ready,
STATE_OUT => open
);
-
+
+ -- RSL for RX of SerDes, based on extRSL logic
+ -- CAVEAT: reset signals MUST BE sync'ed to recovered RX clock!
THE_MAIN_RX_RST: main_rx_reset_RS
port map(
CLEAR => rst_dual,
D_OUT(0) => rx_pcs_rst_q,
D_OUT(1) => rx_serdes_rst_q
);
-
+
+ -- LED signals
+ -- Link Status
SD_LED_GREEN_OUT <= '1' when (link_tx_ready = '1') and (link_rx_ready = '1') and (an_complete = '1')
else '0';
+ -- Activity - must be stretched for human eyes
SD_LED_YELLOW_OUT <= '1' when (pcs_tx_en = '1') or (pcs_rx_en = '1')
else '0';
+ -- Error, maybe?
SD_LED_RED_OUT <= '0';
-- -- "Good" debugging pins
-- debug(31) <= '0';
-- debug(32) <= link_rx_ready;
-- debug(33) <= link_tx_ready;
- debug(126) <= link_rx_ready;
- debug(127) <= link_tx_ready;
+ debug(62) <= link_rx_ready;
+ debug(63) <= link_tx_ready;
-- SGMII core
SGMII_GBE_PCS : sgmii_gbe_core
MAC_AN_READY_OUT <= an_complete;
- -- "Good" debugging pins
- debug(7 downto 0) <= pcs_txd;
- debug(15 downto 8) <= pcs_rxd;
- debug(16) <= pcs_tx_en;
- debug(17) <= pcs_tx_er;
- debug(18) <= pcs_rx_en;
- debug(19) <= pcs_rx_er;
- -- "Bad" debugging pins
- debug(20) <= pll_lol;
- debug(21) <= rx_cdr_lol;
- debug(22) <= rx_los_low;
- debug(23) <= sd_rx_cv_error(0);
- debug(24) <= lsm_status;
- debug(25) <= mr_main_reset;
- debug(26) <= mr_an_enable;
- debug(27) <= mr_restart_an;
- debug(28) <= mr_page_rx;
- debug(29) <= an_complete;
- debug(30) <= an_link_ok;
- debug(31) <= '0';
- debug(32) <= link_rx_ready;
- debug(33) <= link_tx_ready;
-
--- SIMPLE ---
operational_rate <= b"10";
--- /SIMPLE ---
mr_main_reset <= rst_dual;
mr_restart_an <= pulse;
mr_an_enable <= link_rx_ready;
--- mr_adv_ability <= x"01a0";
mr_adv_ability <= x"0020";
SYNC_PROC: process( CLK_125_IN )
end process SYNC_PROC;
pulse <= not delay_q(7) and delay_q(6);
- pulse2 <= not delay_q(3) and delay_q(0);
--- /SIMPLE ---
-- u0_ri : register_interface_hb port map(
-- mr_page_rx => mr_page_rx,
-- mr_lp_adv_ability => mr_lp_adv_ability
-- );
+
+ -- "Good" debugging pins
+ debug(7 downto 0) <= pcs_txd;
+ debug(15 downto 8) <= pcs_rxd;
+ debug(16) <= pcs_tx_en;
+ debug(17) <= pcs_tx_er;
+ debug(18) <= pcs_rx_en;
+ debug(19) <= pcs_rx_er;
+ -- "Bad" debugging pins
+ debug(20) <= pll_lol;
+ debug(21) <= rx_cdr_lol;
+ debug(22) <= rx_los_low;
+ debug(23) <= sd_rx_cv_error(0);
+ debug(24) <= lsm_status;
+ debug(25) <= mr_main_reset;
+ debug(26) <= mr_an_enable;
+ debug(27) <= mr_restart_an;
+ debug(28) <= mr_page_rx;
+ debug(29) <= an_complete;
+ debug(30) <= an_link_ok;
+ debug(31) <= '0';
+ debug(32) <= link_rx_ready;
+ debug(33) <= link_tx_ready;
MAC: tsmac_gbe
port map(
-- used also to filter out frames with different addresses
-- after main configuration (by setting TsMAC filtering accordingly)
-
-
entity trb_net16_gbe_mac_control is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- signals to/from main controller
- MC_TSMAC_READY_OUT : out std_logic;
- MC_RECONF_IN : in std_logic;
- MC_GBE_EN_IN : in std_logic;
- MC_RX_DISCARD_FCS : in std_logic;
- MC_PROMISC_IN : in std_logic;
- MC_MAC_ADDR_IN : in std_logic_vector(47 downto 0);
-
--- signal to/from Host interface of TriSpeed MAC
- TSM_HADDR_OUT : out std_logic_vector(7 downto 0);
- TSM_HDATA_OUT : out std_logic_vector(7 downto 0);
- TSM_HCS_N_OUT : out std_logic;
- TSM_HWRITE_N_OUT : out std_logic;
- TSM_HREAD_N_OUT : out std_logic;
- TSM_HREADY_N_IN : in std_logic;
- TSM_HDATA_EN_N_IN : in std_logic;
-
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end trb_net16_gbe_mac_control;
+ port (
+ CLK : in std_logic; -- system clock
+ RESET : in std_logic;
+ -- signals to/from main controller
+ MC_TSMAC_READY_OUT : out std_logic;
+ MC_RECONF_IN : in std_logic;
+ MC_GBE_EN_IN : in std_logic;
+ MC_RX_DISCARD_FCS : in std_logic;
+ MC_PROMISC_IN : in std_logic;
+ MC_MAC_ADDR_IN : in std_logic_vector(47 downto 0);
+ -- signal to/from Host interface of TriSpeed MAC
+ TSM_HADDR_OUT : out std_logic_vector(7 downto 0);
+ TSM_HDATA_OUT : out std_logic_vector(7 downto 0);
+ TSM_HCS_N_OUT : out std_logic;
+ TSM_HWRITE_N_OUT : out std_logic;
+ TSM_HREAD_N_OUT : out std_logic;
+ TSM_HREADY_N_IN : in std_logic;
+ TSM_HDATA_EN_N_IN : in std_logic;
+ -- Debug
+ DEBUG_OUT : out std_logic_vector(63 downto 0)
+ );
+end entity trb_net16_gbe_mac_control;
architecture trb_net16_gbe_mac_control of trb_net16_gbe_mac_control is
MAC_CONF_MACHINE_PROC : process(CLK)
begin
- if RESET = '1' then
- mac_conf_current_state <= IDLE;
+ if RESET = '1' then
+ mac_conf_current_state <= IDLE;
elsif rising_edge(CLK) then
--- if (RESET = '1') then
--- mac_conf_current_state <= IDLE;
--- else
- mac_conf_current_state <= mac_conf_next_state;
--- end if;
+ mac_conf_current_state <= mac_conf_next_state;
end if;
end process MAC_CONF_MACHINE_PROC;
case mac_conf_current_state is
when IDLE =>
- if (MC_RECONF_IN = '1') then
- mac_conf_next_state <= DISABLE;
- else
- mac_conf_next_state <= IDLE;
- end if;
+ if (MC_RECONF_IN = '1') then
+ mac_conf_next_state <= DISABLE;
+ else
+ mac_conf_next_state <= IDLE;
+ end if;
when DISABLE =>
- if (TSM_HREADY_N_IN = '0') then
- mac_conf_next_state <= WRITE_TX_RX_CTRL1;
- else
- mac_conf_next_state <= DISABLE;
- end if;
-
+ if (TSM_HREADY_N_IN = '0') then
+ mac_conf_next_state <= WRITE_TX_RX_CTRL1;
+ else
+ mac_conf_next_state <= DISABLE;
+ end if;
+
when WRITE_TX_RX_CTRL1 =>
- if (TSM_HREADY_N_IN = '0') then
- mac_conf_next_state <= WRITE_TX_RX_CTRL2;
- else
- mac_conf_next_state <= WRITE_TX_RX_CTRL1;
- end if;
-
- when WRITE_TX_RX_CTRL2 =>
- if (TSM_HREADY_N_IN = '0') then
- mac_conf_next_state <= ENABLE;
- else
- mac_conf_next_state <= WRITE_TX_RX_CTRL2;
- end if;
+ if (TSM_HREADY_N_IN = '0') then
+ mac_conf_next_state <= WRITE_TX_RX_CTRL2;
+ else
+ mac_conf_next_state <= WRITE_TX_RX_CTRL1;
+ end if;
+
+ when WRITE_TX_RX_CTRL2 =>
+ if (TSM_HREADY_N_IN = '0') then
+ mac_conf_next_state <= ENABLE;
+ else
+ mac_conf_next_state <= WRITE_TX_RX_CTRL2;
+ end if;
when ENABLE =>
- if (TSM_HREADY_N_IN = '0') then
- mac_conf_next_state <= READY;
- else
- mac_conf_next_state <= ENABLE;
- end if;
+ if (TSM_HREADY_N_IN = '0') then
+ mac_conf_next_state <= READY;
+ else
+ mac_conf_next_state <= ENABLE;
+ end if;
when READY =>
- if (MC_RECONF_IN = '1') then
- mac_conf_next_state <= DISABLE;
- else
- mac_conf_next_state <= READY;
- end if;
+ if (MC_RECONF_IN = '1') then
+ mac_conf_next_state <= DISABLE;
+ else
+ mac_conf_next_state <= READY;
+ end if;
end case;
HADDR_PROC : process(CLK)
begin
- if rising_edge(CLK) then
- case mac_conf_current_state is
- when IDLE =>
- TSM_HADDR_OUT <= x"00";
- when DISABLE =>
- TSM_HADDR_OUT <= x"00";
- when WRITE_TX_RX_CTRL1 =>
- TSM_HADDR_OUT <= x"02";
- when WRITE_TX_RX_CTRL2 =>
- TSM_HADDR_OUT <= x"03";
- when ENABLE =>
- TSM_HADDR_OUT <= x"00";
- when READY =>
- TSM_HADDR_OUT <= x"00";
- end case;
- end if;
+ if rising_edge(CLK) then
+ case mac_conf_current_state is
+ when IDLE =>
+ TSM_HADDR_OUT <= x"00";
+ when DISABLE =>
+ TSM_HADDR_OUT <= x"00";
+ when WRITE_TX_RX_CTRL1 =>
+ TSM_HADDR_OUT <= x"02";
+ when WRITE_TX_RX_CTRL2 =>
+ TSM_HADDR_OUT <= x"03";
+ when ENABLE =>
+ TSM_HADDR_OUT <= x"00";
+ when READY =>
+ TSM_HADDR_OUT <= x"00";
+ end case;
+ end if;
end process HADDR_PROC;
HDATA_PROC : process(CLK)
begin
- if rising_edge(CLK) then
- case mac_conf_current_state is
- when IDLE =>
- TSM_HDATA_OUT <= x"00";
- when DISABLE =>
- TSM_HDATA_OUT <= x"00";
- when WRITE_TX_RX_CTRL1 =>
- TSM_HDATA_OUT <= reg_tx_rx_ctrl1;
- when WRITE_TX_RX_CTRL2 =>
- TSM_HDATA_OUT <= reg_tx_rx_ctrl2;
- when ENABLE =>
- TSM_HDATA_OUT <= reg_mode;
- when READY =>
- TSM_HDATA_OUT <= x"00";
- end case;
- end if;
+ if rising_edge(CLK) then
+ case mac_conf_current_state is
+ when IDLE =>
+ TSM_HDATA_OUT <= x"00";
+ when DISABLE =>
+ TSM_HDATA_OUT <= x"00";
+ when WRITE_TX_RX_CTRL1 =>
+ TSM_HDATA_OUT <= reg_tx_rx_ctrl1;
+ when WRITE_TX_RX_CTRL2 =>
+ TSM_HDATA_OUT <= reg_tx_rx_ctrl2;
+ when ENABLE =>
+ TSM_HDATA_OUT <= reg_mode;
+ when READY =>
+ TSM_HDATA_OUT <= x"00";
+ end case;
+ end if;
end process HDATA_PROC;
process(CLK)
begin
- if rising_edge(CLK) then
- if (mac_conf_current_state = IDLE or mac_conf_current_state = READY) then
- hcs_n <= '1';
- hwrite_n <= '1';
- elsif (TSM_HREADY_N_IN = '1') then
- hcs_n <= '0';
- hwrite_n <= '0';
- else
- hcs_n <= '1';
- hwrite_n <= '1';
- end if;
-
- if (mac_conf_current_state = READY) then
- tsmac_ready <= '1';
- else
- tsmac_ready <= '0';
- end if;
- end if;
+ if rising_edge(CLK) then
+ if (mac_conf_current_state = IDLE or mac_conf_current_state = READY) then
+ hcs_n <= '1';
+ hwrite_n <= '1';
+ elsif (TSM_HREADY_N_IN = '1') then
+ hcs_n <= '0';
+ hwrite_n <= '0';
+ else
+ hcs_n <= '1';
+ hwrite_n <= '1';
+ end if;
+
+ if (mac_conf_current_state = READY) then
+ tsmac_ready <= '1';
+ else
+ tsmac_ready <= '0';
+ end if;
+ end if;
end process;
TSM_HCS_N_OUT <= hcs_n;
TSM_HREAD_N_OUT <= '1';
MC_TSMAC_READY_OUT <= tsmac_ready;
-
end trb_net16_gbe_mac_control;
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