use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.all;
entity etrax_interface is
generic(
FPGA_REGISTER_IN : in std_logic_vector(STATUS_REGISTERS*32-1 downto 0);
FPGA_REGISTER_OUT : out std_logic_vector(CONTROL_REGISTERS*32-1 downto 0);
--Reset FPGA via Etrax
- EXTERNAL_RESET : out std_logic
+ EXTERNAL_RESET : out std_logic;
+ STAT : out std_logic_vector(7 downto 0)
);
end etrax_interface;
architecture etrax_interface of etrax_interface is
signal ETRAX_RW_STATE_currentstate,ETRAX_RW_STATE_nextstate : ETRAX_RW_STATE_MACHINE;
signal etrax_trigger_pulse : std_logic;
- signal saved_rw_mode : std_logic_vector(17 downto 0);
+ signal saved_rw_mode : std_logic_vector(15 downto 0);
signal saved_address : std_logic_vector (15 downto 0);
signal saved_data : std_logic_vector(31 downto 0);
signal saved_data_fpga : std_logic_vector(31 downto 0);
signal reg_BUSC, last_BUSC : std_logic_vector(1 downto 0);
begin
+
+ STAT(3 downto 0) <= communication_state;
+ STAT(4) <= read_cycle;
+ STAT(5) <= write_cycle;
+ STAT(7 downto 6) <= "00";
+
MAKE_RESET: process (CLK)
begin
if rising_edge(CLK) then
saved_address <= (others => '0');
saved_data <= (others => '0');
elsif ETRAX_RW_STATE_currentstate = IDLE and etrax_trigger_pulse = '1' then
- saved_rw_mode <= ETRAX_DATA_BUS_C;
+ saved_rw_mode <= ETRAX_DATA_BUS_C(15 downto 0);
elsif ETRAX_RW_STATE_currentstate = SAVE_ADDRESS_2 and etrax_trigger_pulse = '1' then
saved_address(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0);
elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_1 and etrax_trigger_pulse = '1' then
if rising_edge(CLK) then
stat_num := conv_integer(saved_address(3 downto 0));
ctrl_num := conv_integer(saved_address(3 downto 0));
- case saved_rw_mode(7 downto 0) is
- when x"00" =>
+ case saved_rw_mode(14 downto 0) is
+ when "000000000000000" =>
if saved_rw_mode(15) = '1' then
if saved_address(15 downto 8) = 0 then
if saved_address(7 downto 4) = 0 then --status regs
RESET : in std_logic;
CLK_EN : in std_logic;
DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data
- PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data
+ PACKET_NUM_IN : in std_logic_vector(1 downto 0); -- Input data
WRITE_ENABLE_IN : in std_logic;
DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data
- PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data
+ PACKET_NUM_OUT : out std_logic_vector(1 downto 0); -- Input data
READ_ENABLE_IN : in std_logic;
FULL_OUT : out std_logic; -- Full Flag
EMPTY_OUT : out std_logic;
end component;
- signal din, dout : std_logic_vector(c_DATA_WIDTH + c_NUM_WIDTH-1 downto 0);
+ signal din, dout : std_logic_vector(17 downto 0);
signal depth16 : std_logic_vector(7 downto 0);
begin
din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN;
- din(c_DATA_WIDTH + c_NUM_WIDTH -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN;
+ din(c_DATA_WIDTH + 1 downto c_DATA_WIDTH) <= PACKET_NUM_IN;
DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0);
- PACKET_NUM_OUT <= dout(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH);
+ PACKET_NUM_OUT <= dout(c_DATA_WIDTH + 1 downto c_DATA_WIDTH);
DEPTH_OUT <= std_logic_vector(to_unsigned(DEPTH,8));
gen_FIFO6 : if DEPTH = 6 generate
use work.trb_net16_hub_func.all;
entity flexi_PCS_channel_synch is
-
+
port (
SYSTEM_CLK : in std_logic;
TX_CLK : in std_logic;
TX_K : out std_logic_vector(1 downto 0);
DATA_VALID_IN : in std_logic;
DATA_VALID_OUT : out std_logic;
- FLEXI_PCS_STATUS : out std_logic_vector(15 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(1 downto 0);
+ FLEXI_PCS_STATUS : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
MED_ERROR_OUT : out std_logic_vector(2 downto 0);
MED_READ_IN : in std_logic
);
signal fifo_almost_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almost_empty : std_logic;
- signal packet_number : std_logic_vector(1 downto 0);
+ signal packet_number : std_logic_vector(c_NUM_WIDTH-1 downto 0);
signal start_counter_1 : std_logic_vector(31 downto 0);
signal start_counter_2 : std_logic_vector(31 downto 0);
signal fifo_rd_pulse : std_logic;
signal fifo_rd_en_hub : std_logic;
begin
SEND_ERROR: process (SYSTEM_CLK, RESET,SYNCH_CURRENT)
- begin
+ begin
if rising_edge(SYSTEM_CLK) then
- if RESET = '1' then
+ if RESET = '1' then
MED_ERROR_OUT <= ERROR_NC;
elsif SYNCH_CURRENT = NORMAL_OPERATION_1 or SYNCH_CURRENT = NORMAL_OPERATION_2 then
MED_ERROR_OUT <= ERROR_OK;
end process SEND_ERROR;
PACKET_NUM: process (SYSTEM_CLK, RESET,fifo_rd_en)
begin
- if rising_edge(SYSTEM_CLK) then
- if RESET = '1' then
- packet_number <= "11";
+ if rising_edge(SYSTEM_CLK) then
+ if RESET = '1' then
+ packet_number <= "011";
elsif fifo_rd_en = '1' then
- packet_number <= packet_number + 1;
+ if packet_number = c_max_word_number then
+ packet_number <= "000";
+ else
+ packet_number <= packet_number + 1;
+ end if;
end if;
end if;
end process PACKET_NUM;
AlmostFull => fifo_opt_almost_full
);
DATA_SEND_TO_LINK: process (TX_CLK, RESET, DATA_VALID_IN,fifo_opt_empty_synch,fifo_opt_empty_synch_synch)
- begin
+ begin
if rising_edge(TX_CLK) then --falling ???
if RESET = '1' then
tx_k_i <= '0';
fifo_opt_not_empty <= not fifo_opt_empty;
end if;
end if;
- end process DATA_SEND_TO_LINK;
+ end process DATA_SEND_TO_LINK;
SYNCH_DATA: process (TX_CLK)
- begin
+ begin
if rising_edge(TX_CLK) then
TXD_SYNCH <= txd_synch_i;
TX_K(0) <= tx_k_i;
- TX_K(1) <= '0';
- end if;
+ TX_K(1) <= '0';
+ end if;
end process SYNCH_DATA;
-- TX_FORCE_DISP(1) <= '0';
-----------------------------------------------------------------------------
-- from link to hub
-----------------------------------------------------------------------------
-
+
CHANNEL_FIFO_TO_FPGA: flexi_PCS_fifo_EBR
port map (
Data => fifo_data_in,
signal_in => not_fifo_empty,
pulse => fifo_rd_pulse);
READING_THE_FIFO: process (SYSTEM_CLK, RESET, fifo_rd_pulse,MED_READ_IN,fifo_empty,data_valid_out_i)
- begin
+ begin
if rising_edge(SYSTEM_CLK) then
if RESET = '1' then
data_valid_out_i <= '0';
RXD_SYNCH <= fifo_data_out(15 downto 0);
-- DATA_VALID_OUT <= fifo_data_out(16) and (not fifo_empty);
VALID_DATA_SEND_TO_API: process (RX_CLK, RESET)
- begin
+ begin
if rising_edge(RX_CLK) then
if RESET = '1' then
rxd_synch_i <= (others => '0');
end if;
end process VALID_DATA_SEND_TO_API;
SHIFT_OR_NOT_DATA_IN: process (RX_CLK, RESET, SYNCH_CURRENT)
- begin
+ begin
if rising_edge(RX_CLK) then
- if RESET = '1' then
+ if RESET = '1' then
fifo_data_in <= (others => '0');
elsif SYNCH_CURRENT = NORMAL_OPERATION_2 then
fifo_data_in <= '0' & (not RX_K(0)) & RXD;
rx_rst_i <= '0';
resync_counter_up <= '1';
resync_counter_clr <= '0';
- if resync_counter(16) = '1' then --at least 400us
+ if resync_counter(16) = '1' then --at least 400us
SYNCH_NEXT <= RESYNC3;
else
SYNCH_NEXT <= RESYNC2;
end if;
-
+
when RESYNC3 =>
fifo_rst <= '0';
fifo_wr_en <= '0';
if resync_counter(27) = '1' and (rxd_synch_i = x"bc50" or rxd_synch_i = x"bcc5") and rx_k_synch_i(1) = '1' then
SYNCH_NEXT <= NORMAL_OPERATION_1;
elsif resync_counter(26) = '1' and (rxd_synch_i /= x"bc50" or rx_k_synch_i(1) = '0') then
- SYNCH_NEXT <= RESYNC1;
+ SYNCH_NEXT <= RESYNC1;
else
SYNCH_NEXT <= WAIT_1;
end if;
resync_counter_clr <= '0';
if resync_counter(27) = '1' and (rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc") and rx_k_synch_i(0) = '1' then
SYNCH_NEXT <= NORMAL_OPERATION_2;
- elsif resync_counter(26) = '1'and (rxd_synch_i(7 downto 0) /= x"bc" or rx_k_synch_i(0) = '0') then
+ elsif resync_counter(26) = '1' and (rxd_synch_i(7 downto 0) /= x"bc" or rx_k_synch_i(0) = '0') then
SYNCH_NEXT <= RESYNC1;
else
SYNCH_NEXT <= WAIT_2;
end if;
when NORMAL_OPERATION_1 =>
fifo_rst <= '0';
- fifo_wr_en <= not rx_k_synch_i(1);
+ fifo_wr_en <= not rx_k_synch_i(1);
fsm_debug_register(2 downto 0) <= "110";
rx_rst_i <= '0';
resync_counter_up <= '0';
resync_counter_clr <= '0';
if cv_i(0) = '1' or cv_i(1) = '1' then
- SYNCH_NEXT <= IDLE;
+ SYNCH_NEXT <= IDLE;
else
SYNCH_NEXT <= NORMAL_OPERATION_1;
end if;
when NORMAL_OPERATION_2 =>
fifo_rst <='0';--RESET;--'0';sim
- fifo_wr_en <= not rx_k_synch_i(0);
+ fifo_wr_en <= not rx_k_synch_i(0);
fsm_debug_register(2 downto 0) <= "111";
rx_rst_i <= '0';
resync_counter_up <= '0';
resync_counter_clr <= '0';
if cv_i(0) = '1' or cv_i(1) = '1' then
- SYNCH_NEXT <= IDLE;
+ SYNCH_NEXT <= IDLE;
else
SYNCH_NEXT <= NORMAL_OPERATION_2;
end if;
port map (
QOUT => resync_counter,
UP => resync_counter_up,
- CLK => SYSTEM_CLK,
+ CLK => SYSTEM_CLK,
CLR => resync_counter_clr);
cv_or <= cv_i(0) or cv_i(1);
CV_COUNTER_INST: simpleupcounter_16bit
port map (
QOUT => cv_counter,
UP => cv_or,
- CLK => RX_CLK,
+ CLK => RX_CLK,
CLR => RESET);
WR_COUNTER_INST: simpleupcounter_16bit
port map (
QOUT => fifo_wr_cnt,
UP => fifo_wr_en,
- CLK => SYSTEM_CLK,
+ CLK => SYSTEM_CLK,
CLR => RESET);
fifo_rd_en_dv <= fifo_rd_en and fifo_data_out(16) and fifo_empty;
RD_COUNTER_INST: simpleupcounter_16bit
port map (
QOUT => fifo_rd_cnt,
UP => DATA_VALID_IN,--fifo_rd_en_dv,--fifo_rd_en,
- CLK => SYSTEM_CLK,
+ CLK => SYSTEM_CLK,
CLR => RESET);
end flexi_PCS_channel_synch;
--reciving idle for 1ms and start e11o until recive e11o and idle
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
+use work.trb_net_std.all;
entity flexi_PCS_synch is
generic (
MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
MED_ERROR_OUT : out std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0);
architecture flexi_PCS_synch of flexi_PCS_synch is
component flexi_PCS_channel_synch
port (
- SYSTEM_CLK : in std_logic;
+ SYSTEM_CLK : in std_logic;
TX_CLK : in std_logic;
RX_CLK : in std_logic;
RESET : in std_logic;
DATA_VALID_IN : in std_logic;
DATA_VALID_OUT : out std_logic;
FLEXI_PCS_STATUS : out std_logic_vector(15 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
MED_ERROR_OUT : out std_logic_vector(2 downto 0);
MED_READ_IN : in std_logic
);
port map (
SYSTEM_CLK => SYSTEM_CLK,
TX_CLK => CLK(bit_index/4), --4 different channles clk
- RX_CLK => RX_CLK(bit_index),
+ RX_CLK => RX_CLK(bit_index),
RESET => RESET,
RXD => RXD((bit_index*16+15) downto bit_index*16),
RXD_SYNCH => MED_DATA_OUT((bit_index*16+15) downto bit_index*16),
DATA_VALID_IN => MED_DATAREADY_IN(bit_index),
DATA_VALID_OUT => MED_DATAREADY_OUT(bit_index),
FLEXI_PCS_STATUS => FLEXI_PCS_SYNCH_STATUS((bit_index*16+15) downto bit_index*16),
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((bit_index*2+1) downto bit_index*2),
- MED_ERROR_OUT => MED_ERROR_OUT((bit_index*3+2) downto bit_index*3),
- MED_READ_IN => MED_READ_IN(bit_index)
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(((bit_index+1)*c_NUM_WIDTH-1) downto bit_index*c_NUM_WIDTH),
+ MED_ERROR_OUT => MED_ERROR_OUT((bit_index*3+2) downto bit_index*3),
+ MED_READ_IN => MED_READ_IN(bit_index)
);
- end generate CHANNEL_GENERATE;
-end flexi_PCS_synch;
+ end generate;
+end architecture;
MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
MED_ERROR_OUT : out std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0);
USE_CHECKSUM : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES);
IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
- INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
signal txd_synch_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
signal tx_k_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
signal rxb_pclk_a : std_logic_vector((HOW_MANY_CHANNELS+3)/4 -1 downto 0);
- signal rx_clk_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
+ signal rx_clk_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
signal flexi_pcs_synch_status_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
signal word_align_en : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
signal med_dataready_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
--test
- signal data_valid_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ signal data_valid_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
signal med_dataready_out_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
signal med_read_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
signal med_read_out_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- signal med_data_out_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- signal med_data_in_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
- signal med_packet_num_out_i : std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0);
- signal med_packet_num_in_i : std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0);
+ signal med_data_out_i : std_logic_vector(HOW_MANY_CHANNELS*c_DATA_WIDTH-1 downto 0);
+ signal med_data_in_i : std_logic_vector(HOW_MANY_CHANNELS*c_DATA_WIDTH-1 downto 0);
+ signal med_packet_num_out_i : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
+ signal med_packet_num_in_i : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
signal med_error_out_i : std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0);
signal med_stat_op_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
signal med_ctrl_op_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
signal serdes_ref_clk : std_logic;
signal serdes_ref_lock : std_logic;
signal serdes_ref_clks : std_logic;
- signal med_packet_num_in_s : std_logic_vector(HOW_MANY_CHANNELS*2 -1 downto 0);
+ signal med_packet_num_in_s : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH -1 downto 0);
signal mplex_ctrl_i : std_logic_vector (HOW_MANY_CHANNELS*32-1 downto 0);
- signal word_counter_for_api_00 : std_logic_vector(1 downto 0);
- signal word_counter_for_api_01 : std_logic_vector(1 downto 0);
signal global_reset_i : std_logic;
signal global_reset_cnt : std_logic_vector(3 downto 0):=x"0";
signal registered_signals : std_logic_vector(7 downto 0);
signal cv_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
signal rx_clk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
signal ref_pclk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0);
-
+
begin
GLOBAL_RESET: process(LVDS_CLK_200P,global_reset_cnt)
begin
-- begin
-- used_channels_locked(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16);
-- end generate LOK_STATUS_DIOD_EN;
-
+
--lock_pattern(15 downto HOW_MANY_CHANNELS) <= lok_i(16 downto HOW_MANY_CHANNELS +1);
QUAD_GENERATE : for bit_index in 0 to ((HOW_MANY_CHANNELS+3)/4-1) generate
begin
MED_STAT_OP => med_stat_op_i,
MED_CTRL_OP => med_ctrl_op_i
);
- ADO_TTL(34 downto 19) <= med_read_in_i(0) & flexi_pcs_synch_status_i(2 downto 1) & med_packet_num_out_i(1 downto 0) & rx_k_i(1 downto 0) & rxd_i(3 downto 0) & med_dataready_out_i(0) & med_data_out_i(3 downto 0);
+ ADO_TTL(34 downto 19) <= flexi_pcs_synch_status_i(2 downto 0) & med_packet_num_out_i(1 downto 0) & rx_k_i(1 downto 0) & rxd_i(3 downto 0) & med_dataready_out_i(0) & med_data_out_i(3 downto 0);
-- ADO_TTL(34 downto 19) <= med_dataready_out_i(0)& med_data_out_i(14 downto 0);
ADO_TTL(15 downto 0) <= med_read_out_i(0) & flexi_pcs_synch_status_i(7 downto 6) & med_packet_num_in_i(1 downto 0) & tx_k_i(1 downto 0) & txd_synch_i(3 downto 0) & med_dataready_in_i(0) & med_data_in_i(3 downto 0);
-- ADO_TTL(15 downto 0) <= rx_k_i(1 downto 0) & rxd_i(13 downto 0);
HUB_REGISTER_15 => hub_register_15_i,
HUB_REGISTER_16 => hub_register_16_i
);
--------------------------------------------------------------------------------
--- Just lvl1 and lvl2 without trbnet
--------------------------------------------------------------------------------
--- CONNECT_ALL: for channel_nr in 1 to HOW_MANY_CHANNELS -1 generate
--- med_dataready_in_i(channel_nr) <= med_dataready_out_i(0);
--- med_data_in_i(channel_nr*16+15 downto channel_nr*16) <= med_data_out_i(15 downto 0);
--- SAVE_LVL1_DATA_READY: process(LVDS_CLK_200P, global_reset_i, med_dataready_out_i, med_data_out_i)
--- begin
--- if rising_edge(LVDS_CLK_200P) then
--- if global_reset_i = '1' or all_lvl1_ready = '1' or all_lvl1_ready_delay2 = '1' then
--- saved_lvl1_ready(channel_nr) <= '0';
--- elsif med_dataready_out_i(channel_nr) = '1' and med_data_out_i(channel_nr*16+15 downto channel_nr*16+12) = x"1" and hub_register_0e_and_0d(channel_nr) = '1'then
--- saved_lvl1_ready(channel_nr) <= '1';
--- end if;
--- end if;
--- end process SAVE_LVL1_DATA_READY;
--- SAVE_LVL2_DATA_READY: process(LVDS_CLK_200P, global_reset_i, med_dataready_out_i, med_data_out_i)
--- begin
--- if rising_edge(LVDS_CLK_200P) then
--- if global_reset_i = '1' or all_lvl2_ready = '1' or all_lvl2_ready_delay2 = '1' then
--- saved_lvl2_ready(channel_nr) <= '0';
--- elsif med_dataready_out_i(channel_nr) = '1' and med_data_out_i(channel_nr*16+15 downto channel_nr*16+12) = x"2" and hub_register_0e_and_0d(channel_nr) = '1'then
--- saved_lvl2_ready(channel_nr) <= '1';
--- end if;
--- end if;
--- end process SAVE_LVL2_DATA_READY;
--- end generate CONNECT_ALL;
-
--- SET_LVL1_LVL2_READY: process (LVDS_CLK_200P, global_reset_i)
--- begin
--- if rising_edge(LVDS_CLK_200P) then
--- if global_reset_i = '1' or all_lvl1_ready_delay1 = '1' or all_lvl1_ready_delay2 = '1' or hub_register_0e_and_0d = x"0000" then -- asynchronous reset (active low)
--- all_lvl1_ready <= '0';
--- all_lvl2_ready <= '0';
--- elsif saved_lvl1_ready = hub_register_0e_and_0d(HOW_MANY_CHANNELS-1 downto 0) then
--- all_lvl1_ready <= '1';
--- all_lvl2_ready <= '0';
--- elsif saved_lvl1_ready = hub_register_0e_and_0d(HOW_MANY_CHANNELS-1 downto 0) and saved_lvl2_ready = hub_register_0e_and_0d(HOW_MANY_CHANNELS-1 downto 0) then
--- all_lvl1_ready <= '1';
--- all_lvl2_ready <= '0';
--- elsif saved_lvl2_ready = hub_register_0e_and_0d(HOW_MANY_CHANNELS-1 downto 0) then
--- all_lvl1_ready <= '0';
--- all_lvl2_ready <= '1';
--- else
--- all_lvl1_ready <= '0';
--- all_lvl2_ready <= '0';
--- end if;
--- end if;
--- end process SET_LVL1_LVl2_READY;
--- DELAY_READY: process (LVDS_CLK_200P, global_reset_i)
--- begin -- process DELAY_READY
--- if rising_edge(LVDS_CLK_200P) then
--- if global_reset_i = '1' then -- asynchronous reset (active low)
--- all_lvl1_ready_delay1 <= '0';
--- all_lvl1_ready_delay2 <= '0';
--- all_lvl2_ready_delay1 <= '0';
--- all_lvl2_ready_delay2 <= '0';
--- else
--- all_lvl1_ready_delay1 <= all_lvl1_ready;
--- all_lvl1_ready_delay2 <= all_lvl1_ready_delay1;
--- all_lvl2_ready_delay1 <= all_lvl2_ready;
--- all_lvl2_ready_delay2 <= all_lvl2_ready_delay1;
-
--- end if;
--- end if;
--- end process DELAY_READY;
--- med_read_in_i(0) <= '1';--med_read_counter(3) or med_read_counter(2);
--- -- med_dataready_in_i(0) <= all_lready;--med_dataready_out_i(1);
--- SEND_LVL1_LVL2_ACK: process (LVDS_CLK_200P, global_reset_i)
--- begin
--- if rising_edge(LVDS_CLK_200P) then
--- if global_reset_i = '1' then
--- med_dataready_in_i(0) <= '0';
--- med_data_in_i(15 downto 0) <= x"0000";
--- elsif all_lvl1_ready = '1' or all_lvl1_ready_delay1 = '1' or all_lvl1_ready_delay2 = '1' then
--- med_dataready_in_i(0) <= '1';
--- med_data_in_i(15 downto 0) <= x"1000";
--- elsif all_lvl2_ready = '1' or all_lvl2_ready_delay1 = '1' or all_lvl2_ready_delay2 = '1'then
--- med_dataready_in_i(0) <= '1';
--- med_data_in_i(15 downto 0) <= x"2000";
--- else
--- med_dataready_in_i(0) <= '0';
--- med_data_in_i(15 downto 0) <= x"0000";
--- end if;
--- end if;
--- end process SEND_LVL1_LVL2_ACK;
--- med_read_in_i(HOW_MANY_CHANNELS-1 downto 1) <= (others => '1');
-
--- -- saved_ready(0) <= '1';
--- -- MAKE_RAED: process (LVDS_CLK_200P, global_reset_i)
--- -- begin -- process MAKE_RAED
--- -- if rising_edge(LVDS_CLK_200P) then
--- -- if global_reset_i = '1' then -- asynchronous reset (active low)
--- -- med_read_counter <= (others => '0');
--- -- else
--- -- med_read_counter <= med_read_counter + 1;
--- -- end if;
--- -- end if;
--- -- end process MAKE_RAED;
-
-
--------------------------------------------------------------------------------
--- end "Just lvl1 without trbnet"
--------------------------------------------------------------------------------
process (LVDS_CLK_200P, global_reset_i, med_dataready_out_i)
- begin
+ begin
if rising_edge(LVDS_CLK_200P) then
if global_reset_i = '1' then -- asynchronous reset (active low)
registered_signals(0) <= '0';
end if;
end process;
process (rx_clk_i(0), global_reset_i, rx_k_i(0))
- begin
+ begin
if rising_edge(rx_clk_i(0)) then
if global_reset_i = '1' then -- asynchronous reset (active low)
registered_signals(1) <= '0';
end if;
end process;
process (rx_clk_i(0), global_reset_i,rx_k_i(1))
- begin
+ begin
if rising_edge(rx_clk_i(0)) then
if global_reset_i = '1' then -- asynchronous reset (active low)
registered_signals(2) <= '0';
end if;
end process;
registered_signals(4 downto 3) <= rx_k_i(1) & rx_k_i(0);
--- SYNCH_DATA: process (ref_pclk(0), global_reset_i)
--- begin -- process SYNCH_DATA
--- if falling_edge(ref_pclk(0)) then
--- if global_reset_i = '1' then
--- hub_register_0a_i_synch <= (others => '0');
--- hub_register_0e_and_0d_synch <= (others => '0');
--- else
--- hub_register_0a_i_synch <= hub_register_0a_i;
--- hub_register_0e_and_0d_synch <= hub_register_0e_and_0d;
--- end if;
--- end if;
--- end process SYNCH_DATA;
-
+
+
+
-- hub_register_00_i(7 downto 0) <= flexi_pcs_synch_status_i(7 downto 0);
-- hub_register_01_i(7 downto 0) <= hub_stat_gen_i(15 downto 8);
hub_register_02_i(7 downto 0) <= (others => '0');--saved_lvl1_ready(7 downto 0);--rxd_i(7 downto 0); --; --rxd_1_a(15 downto 8);
-- hub_register_14_i <= flexi_pcs_synch_status_i(23+8*16 downto 16+8*16);
-- hub_register_15_i <= flexi_pcs_synch_status_i(39+8*16 downto 32+8*16);
-- hub_register_16_i <= flexi_pcs_synch_status_i(63+8*16 downto 56+8*16);
-
+
hub_register_06_i(7 downto 0) <= tx_k_i(1 downto 0) & med_error_out_i(5 downto 0);
hub_register_07_i(7 downto 0) <= hub_stat_gen_i(31 downto 24);--flexi_pcs_synch_status_i(39 downto 32);
hub_register_08_i(7 downto 0) <= hub_stat_gen_i(23 downto 16);--flexi_pcs_synch_status_i(55 downto 48);
begin
WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate
TX_DIS(16-not_connected) <= '1';
- end generate WHEN_NOT_ALL_EN;
+ end generate;
end generate;
---------------------------------------------------------------------------
begin
hub_register_00_i(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16);
end generate LOK_STATUS_REGISTER_0;
-
+
LOK_STATUS_REGISTER_1 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 - 8) generate
begin
hub_register_01_i(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16+8*16);
DWAIT <= global_reset_i;
CV_COUNTERaaa: process (LVDS_CLK_200P, global_reset_i)
- begin
+ begin
if rising_edge(LVDS_CLK_200P) then -- rising clock edge
if global_reset_i = '1' then -- asynchronous reset (active low)
cv_counter <= (others => '0');
end if;
end process CV_COUNTERaaa;
CV_COUNTERaab: process (ref_pclk(0), global_reset_i)
- begin
+ begin
if rising_edge(ref_pclk(0)) then -- rising clock edge
if global_reset_i = '1' then -- asynchronous reset (active low)
cv_countera <= (others => '0');
RT(2) <= flexi_pcs_ref_clk;--cv_counter(0);
RT(1) <= not switch_rx_clk;--ref_pclk(0);
-
+
RT(3) <= LVDS_CLK_200P;
RT(4) <= rx_k_i(0);
RT(5) <= med_dataready_out_i(0);--serdes_ref_clk;
RT(6) <= med_data_out_i(0);--serdes_ref_clks;
RT(7) <= med_data_out_i(1);--serdes_ref_lock;
-
----------------------------------------------------------------------------
--- simulation
- ---------------------------------------------------------------------------
--- clock_gclk : process
--- begin
--- ref_pclk(0) <= '0';
--- wait for 5 ns;
--- ref_pclk_a <= '1';
--- wait for 5 ns;
--- end process;
-end hub;
+
+
+end architecture;
signal next_fifo_was_not_empty, fifo_was_not_empty : std_logic;
signal endpoint_reached : std_logic;
+ signal sbuf_status : std_logic_vector(2 downto 0);
begin
---------------------------------------
SYN_DATAREADY_OUT => buf_INT_MASTER_DATAREADY_OUT,
SYN_DATA_OUT => INT_MASTER_DATA_OUT,
SYN_PACKET_NUM_OUT => buf_INT_MASTER_PACKET_NUM_OUT,
- SYN_READ_IN => INT_MASTER_READ_IN
+ SYN_READ_IN => INT_MASTER_READ_IN,
+ STAT_BUFFER => sbuf_status(0)
);
process(CLK)
SYN_DATAREADY_OUT => reg_APL_DATAREADY_OUT,
SYN_DATA_OUT => reg_APL_DATA_OUT,
SYN_PACKET_NUM_OUT => reg_APL_PACKET_NUM_OUT,
- SYN_READ_IN => APL_READ_IN
+ SYN_READ_IN => APL_READ_IN,
+ STAT_BUFFER => sbuf_status(1)
);
SBUF_TO_APL2: trb_net_sbuf
generic map (
COMB_DATA_IN => next_APL_TYP_OUT,
SYN_DATAREADY_OUT => sbuf_apl_type_dataready,
SYN_DATA_OUT => buf_APL_TYP_OUT,
- SYN_READ_IN => APL_READ_IN
+ SYN_READ_IN => APL_READ_IN,
+ STAT_BUFFER => sbuf_status(2)
);
reg_APL_TYP_OUT <= TYPE_ILLEGAL when sbuf_apl_type_dataready = '0' else buf_APL_TYP_OUT;
OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
INIT_CAN_SEND_DATA : integer range 0 to 1 := c_NO;
REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;
USE_CHECKSUM : integer range 0 to 1 := c_YES;
DAT_CHANNEL : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL
);
CLK : in std_logic;
RESET : in std_logic;
CLK_EN : in std_logic;
+ RESET_TRBNET_IN : in std_logic;
-- Media direction port
MED_DATAREADY_OUT : out std_logic;
MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
MED_READ_OUT : out std_logic;
MED_ERROR_IN : in std_logic_vector (2 downto 0);
- MED_STAT_OP : in std_logic_vector (15 downto 0);
- MED_CTRL_OP : out std_logic_vector (15 downto 0);
-- APL Transmitter port
APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
-- Status and control port
STAT_GEN: out std_logic_vector (31 downto 0);
- STAT_LOCKED: out std_logic_vector (31 downto 0);
STAT_INIT_BUFFER: out std_logic_vector (31 downto 0);
STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0);
STAT_api_control_signals: out std_logic_vector(31 downto 0);
STAT_MPLEX: out std_logic_vector(31 downto 0);
CTRL_GEN: in std_logic_vector (31 downto 0);
- CTRL_LOCKED: in std_logic_vector (31 downto 0);
STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
MPLEX_CTRL: in std_logic_vector (31 downto 0);
API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
+ API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0);
+ STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);
+ STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0)
);
end entity;
USE_CHECKSUM : integer range 0 to 1 := c_YES;
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
- REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
+ REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES
);
port(
-- Misc
STAT_GEN: out std_logic_vector (31 downto 0);
STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0);
CTRL_GEN: in std_logic_vector (31 downto 0);
- STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0)
+ STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);
+ STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0)
);
end component;
signal buf_STAT_INIT_BUFFER : std_logic_vector (31 downto 0);
signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (31 downto 0);
+signal reset_internal : std_logic;
+
+
begin
+ reset_internal <= RESET_TRBNET_IN or RESET;
MED_CTRL_OP(15) <= MED_STAT_OP(15);
MED_CTRL_OP(14 downto 0) <= (others => '0');
termbuf: trb_net16_term_buf
port map(
CLK => CLK,
- RESET => RESET,
+ RESET => reset_internal,
CLK_EN => CLK_EN,
MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2),
port map (
-- Misc
CLK => CLK,
- RESET => RESET,
+ RESET => reset_internal,
CLK_EN => CLK_EN,
-- APL Transmitter port
APL_DATA_IN => APL_DATA_IN,
port map (
-- Misc
CLK => CLK,
- RESET => RESET,
+ RESET => reset_internal,
CLK_EN => CLK_EN,
-- APL Transmitter port
APL_DATA_IN => APL_DATA_IN,
STAT_api_control_signals(10 downto 8) <= apl_to_buf_INIT_DATA(2 downto 0);
STAT_api_control_signals(11) <= apl_to_buf_INIT_DATAREADY;
STAT_api_control_signals(12) <= apl_to_buf_INIT_READ;
+STAT_api_control_signals(15 downto 13) <= (others => '0');
STAT_api_control_signals(19 downto 16) <= MED_INIT_DATA_OUT(3 downto 0);
STAT_api_control_signals(21 downto 20) <= MED_INIT_PACKET_NUM_OUT(1 downto 0);
STAT_api_control_signals(22) <= MED_INIT_DATAREADY_OUT and MED_INIT_READ_IN;
+STAT_api_control_signals(28 downto 23) <= (others => '0');
--STAT_api_control_signals(30 downto 13) <= (others => '0');
STAT_api_control_signals(31) <= buf_to_apl_INIT_READ;
USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(DAT_CHANNEL),
USE_CHECKSUM => USE_CHECKSUM,
INIT_CAN_SEND_DATA => INIT_CAN_SEND_DATA,
- REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA
+ REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA,
+ REPLY_CAN_RECEIVE_DATA => REPLY_CAN_RECEIVE_DATA
)
port map (
-- Misc
CLK => CLK ,
- RESET => RESET,
+ RESET => reset_internal,
CLK_EN => CLK_EN,
-- Media direction port
MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT,
STAT_GEN => STAT_GEN,
STAT_IBUF_BUFFER => buf_STAT_INIT_BUFFER,
CTRL_GEN => CTRL_GEN,
- STAT_CTRL_IBUF_BUFFER => STAT_CTRL_INIT_BUFFER
+ STAT_CTRL_IBUF_BUFFER => STAT_CTRL_INIT_BUFFER,
+ STAT_INIT_OBUF_DEBUG => STAT_INIT_OBUF_DEBUG,
+ STAT_REPLY_OBUF_DEBUG => STAT_REPLY_OBUF_DEBUG
);
STAT_INIT_BUFFER <= buf_STAT_INIT_BUFFER;
port map (
CLK => CLK,
- RESET => RESET,
+ RESET => reset_internal,
CLK_EN => CLK_EN,
MED_DATAREADY_IN => MED_DATAREADY_IN,
MED_DATA_IN => MED_DATA_IN,
INT_DATA_IN => m_DATA_OUT,
INT_PACKET_NUM_IN => m_PACKET_NUM_OUT,
INT_READ_OUT => m_READ_IN,
- CTRL => MPLEX_CTRL
+ CTRL => MPLEX_CTRL,
+ STAT => STAT_MPLEX
);
end architecture;
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
- INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) :=
(others => '1');
USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
-
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
+ INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
+ INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"
INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
ENABLE : in std_logic;
- CTRL: in STD_LOGIC_VECTOR (31 downto 0)
+ CTRL: in STD_LOGIC_VECTOR (9 downto 0)
);
end component;
USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
USE_CHECKSUM : integer range 0 to 1 := c_YES;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- SECURE_MODE : integer range 0 to 1 := c_YES
- --use sbuf in med_to_api direction?
+ SECURE_MODE : integer range 0 to 1 := c_YES;
+ REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES
);
port(
-- Misc
signal CRC_RESET, CRC_enable : std_logic;
signal CRC_match : std_logic;
+ signal crc_out : std_logic_vector(15 downto 0);
signal last_fifo_read : std_logic;
signal throw_away : std_logic;
signal fifo_read_before : std_logic;
+ signal stat_sbufs : std_logic_vector(1 downto 0);
begin
------------------------
--the input fifo
RESET => CRC_RESET,
CLK_EN => CRC_enable,
DATA_IN => fifo_data_out,
- CRC_OUT => open,
+ CRC_OUT => crc_out,
CRC_match => CRC_match
);
process(last_fifo_read, fifo_long_packet_num_out, current_fifo_packet_type)
SYN_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,
SYN_DATA_OUT => INT_INIT_DATA_OUT,
SYN_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT,
- SYN_READ_IN => INT_INIT_READ_IN
+ SYN_READ_IN => INT_INIT_READ_IN,
+ STAT_BUFFER => stat_sbufs(0)
);
- SBUF_REPLY: trb_net16_sbuf
- generic map (
- Version => SBUF_VERSION
- )
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => tmp_INT_REPLY_DATAREADY_OUT,
- COMB_next_READ_OUT => comb_next_reply_read,
- COMB_READ_IN => '1',
- COMB_DATA_IN => tmp_INT_DATA_OUT,
- COMB_PACKET_NUM_IN => tmp_INT_PACKET_NUM_OUT,
- SYN_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT,
- SYN_DATA_OUT => INT_REPLY_DATA_OUT,
- SYN_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT,
- SYN_READ_IN => INT_REPLY_READ_IN
- );
-
process(CLK)
begin
if rising_edge(CLK) then
sbuf_init_free <= comb_next_init_read;
- sbuf_reply_free <= comb_next_reply_read;
end if;
end process;
+
+ gen_reply_sbuf : if REPLY_CAN_RECEIVE_DATA = c_YES generate
+ SBUF_REPLY: trb_net16_sbuf
+ generic map (
+ Version => SBUF_VERSION
+ )
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ COMB_DATAREADY_IN => tmp_INT_REPLY_DATAREADY_OUT,
+ COMB_next_READ_OUT => comb_next_reply_read,
+ COMB_READ_IN => '1',
+ COMB_DATA_IN => tmp_INT_DATA_OUT,
+ COMB_PACKET_NUM_IN => tmp_INT_PACKET_NUM_OUT,
+ SYN_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT,
+ SYN_DATA_OUT => INT_REPLY_DATA_OUT,
+ SYN_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT,
+ SYN_READ_IN => INT_REPLY_READ_IN,
+ STAT_BUFFER => stat_sbufs(1)
+ );
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ sbuf_reply_free <= comb_next_reply_read;
+ end if;
+ end process;
+ end generate;
+ gen_no_reply_sbuf : if REPLY_CAN_RECEIVE_DATA = c_NO generate
+ sbuf_reply_free <= '1';
+ INT_REPLY_DATA_OUT <= (others => '0');
+ INT_REPLY_PACKET_NUM_OUT <= (others => '0');
+ INT_REPLY_DATAREADY_OUT <= '0';
+ stat_sbufs(1) <= '0';
+ comb_next_reply_read <= '1';
+ end generate;
end generate;
gen_notsecure : if SECURE_MODE = 0 generate
INT_INIT_DATA_OUT <= tmp_INT_DATA_OUT;
fifo_empty, sbuf_reply_free, last_fifo_read, current_fifo_packet_type,
fifo_read_before, INT_INIT_READ_IN, INT_REPLY_READ_IN, CRC_match)
begin
+
tmp_INT_DATA_OUT <= fifo_data_out;
tmp_INT_PACKET_NUM_OUT <= fifo_long_packet_num_out;
tmp_INT_INIT_DATAREADY_OUT <= '0';
CRC_RESET <= '1';
end if;
end if;
+ if REPLY_CAN_RECEIVE_DATA = c_NO then
+ tmp_INT_REPLY_DATAREADY_OUT <= '0';
+ end if;
fifo_read <= not fifo_empty and not (fifo_read_before and ((not sbuf_init_free and not current_fifo_packet_type(3))
or (not sbuf_reply_free and current_fifo_packet_type(3))
or not throw_away));
if (fifo_read_before = '1' and (current_fifo_packet_type(2 downto 0) /= TYPE_EOB)) then
if SECURE_MODE = 1 then
tmp_INT_INIT_DATAREADY_OUT <= (sbuf_init_free) and not current_fifo_packet_type(3);
- tmp_INT_REPLY_DATAREADY_OUT <= (sbuf_reply_free ) and current_fifo_packet_type(3);
+ if REPLY_CAN_RECEIVE_DATA = c_YES then
+ tmp_INT_REPLY_DATAREADY_OUT <= (sbuf_reply_free ) and current_fifo_packet_type(3);
+ end if;
else
tmp_INT_INIT_DATAREADY_OUT <= not current_fifo_packet_type(3);
- tmp_INT_REPLY_DATAREADY_OUT <= current_fifo_packet_type(3);
+ if REPLY_CAN_RECEIVE_DATA = c_YES then
+ tmp_INT_REPLY_DATAREADY_OUT <= current_fifo_packet_type(3);
+ end if;
end if;
end if;
INPUT_IN : in std_logic_vector (WIDTH-1 downto 0);
RESULT_OUT: out std_logic_vector (WIDTH-1 downto 0);
ENABLE : in std_logic;
- CTRL : in std_logic_vector (31 downto 0)
+ CTRL : in std_logic_vector (9 downto 0)
);
end component;
signal arbiter_CLK_EN : std_logic;
signal buf_INT_DATA_OUT: STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
signal buf_INT_PACKET_NUM_OUT: STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
--- signal demux_comb_dataready_in : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+ signal sbuf_status : std_logic;
+
begin
-------------------------------------------------------------------------------
-- DEMUX
INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT;
--current_demux_READ <= INT_READ_IN;
- demux_next_READ <= (others => '1');
+-- demux_next_READ <= (others => '1');
MED_READ_OUT <= current_MED_READ_OUT;
- comb_demux : process (next_demux_dr_tmp, demux_next_READ, INT_READ_IN,
+ comb_demux : process (next_demux_dr_tmp, INT_READ_IN,
MED_DATAREADY_IN, current_MED_READ_OUT,
MED_PACKET_NUM_IN, demux_dr_tmp)
begin
INPUT_IN => INT_DATAREADY_IN,
RESULT_OUT => final_INT_READ_OUT,
ENABLE => mux_enable,
- CTRL => CTRL
+ CTRL => CTRL(9 downto 0)
);
arbiter_CLK_EN <= CLK_EN and not next_endpoint_locked;
-- current_INT_READ_OUT <= tmp_INT_READ_OUT when endpoint_locked = '0'
-- else final_INT_READ_OUT;
- STAT(15 downto 0) <= (others => '0');
+ STAT(0) <= sbuf_status;
+ STAT(15 downto 1) <= (others => '0');
STAT(18 downto 16) <= current_mux_buffer(c_DATA_WIDTH+c_NUM_WIDTH-1 downto c_DATA_WIDTH) xor current_mux_packet_number;
STAT(31 downto 19) <= (others => '0');
SYN_DATAREADY_OUT => MED_DATAREADY_OUT,
SYN_DATA_OUT => MED_DATA_OUT,
SYN_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
- SYN_READ_IN => MED_READ_IN
+ SYN_READ_IN => MED_READ_IN,
+ STAT_BUFFER => sbuf_status
);
USE_CHECKSUM : integer range 0 to 1 := c_YES;
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
- REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
+ REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES
);
port(
-- Misc
USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
USE_CHECKSUM : integer range 0 to 1 := c_YES;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- SECURE_MODE : integer range 0 to 1 := c_YES
- --use sbuf in med_to_api direction?
+ SECURE_MODE : integer range 0 to 1 := c_YES;
+ REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES
);
port(
-- Misc
USE_ACKNOWLEDGE => USE_ACKNOWLEDGE,
USE_CHECKSUM => USE_CHECKSUM,
SBUF_VERSION => SBUF_VERSION,
- SECURE_MODE => IBUF_SECURE_MODE
+ SECURE_MODE => IBUF_SECURE_MODE,
+ REPLY_CAN_RECEIVE_DATA => REPLY_CAN_RECEIVE_DATA
)
port map (
CLK => CLK,
end generate;
genINITOBUF2 : if INIT_CAN_SEND_DATA = 0 generate
gen_INITOBUF3 : if USE_ACKNOWLEDGE = 1 generate
+ STAT_INIT_OBUF_DEBUG <= (others => '0');
INITOBUF : trb_net16_obuf_nodata
port map (
CLK => CLK,
end generate;
genREPLYOBUF2 : if REPLY_CAN_SEND_DATA = 0 generate
gen_REPLYOBUF3 : if USE_ACKNOWLEDGE = 1 generate
+ STAT_REPLY_OBUF_DEBUG <= (others => '0');
REPLYOBUF : trb_net16_obuf_nodata
port map (
CLK => CLK,
entity trb_net16_med_ecp_sfp is
port( CLK : in std_logic;
RESET : in std_logic; -- synchronous reset
- CLK_EN : in std_logic;
+ CLK_EN : in std_logic;
--Internal Connection
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_IN : in std_logic;
- MED_ERROR_OUT : out std_logic_vector(2 downto 0);
- REFCLK2CORE_OUT : out std_logic;
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic;
+ MED_READ_IN : in std_logic;
+ MED_ERROR_OUT : out std_logic_vector(2 downto 0);
+ REFCLK2CORE_OUT : out std_logic;
--SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic;
- SD_REFCLK_N_IN : in std_logic;
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_REFCLK_P_IN : in std_logic;
+ SD_REFCLK_N_IN : in std_logic;
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0);
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0)
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0);
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)
);
end entity;
end component;
component trb_net_fifo_16bit_bram_dualport is
- generic(
- USE_STATUS_FLAGS : integer := c_YES
- );
- port( read_clock_in : in std_logic;
- write_clock_in : in std_logic;
- read_enable_in : in std_logic;
- write_enable_in : in std_logic;
- fifo_gsr_in : in std_logic;
- write_data_in : in std_logic_vector(17 downto 0);
- read_data_out : out std_logic_vector(17 downto 0);
- full_out : out std_logic;
- empty_out : out std_logic;
- fifostatus_out : out std_logic_vector(3 downto 0);
- valid_read_out : out std_logic;
- almost_empty_out : out std_logic;
- almost_full_out : out std_logic
- );
+ generic(
+ USE_STATUS_FLAGS : integer := c_YES
+ );
+ port( read_clock_in : in std_logic;
+ write_clock_in : in std_logic;
+ read_enable_in : in std_logic;
+ write_enable_in : in std_logic;
+ fifo_gsr_in : in std_logic;
+ write_data_in : in std_logic_vector(17 downto 0);
+ read_data_out : out std_logic_vector(17 downto 0);
+ full_out : out std_logic;
+ empty_out : out std_logic;
+ fifostatus_out : out std_logic_vector(3 downto 0);
+ valid_read_out : out std_logic;
+ almost_empty_out : out std_logic;
+ almost_full_out : out std_logic
+ );
end component;
component dcs is
signal sfp_prsnt_n : std_logic; -- synchronized input signals
signal sfp_los : std_logic; -- synchronized input signals
+ signal buf_STAT_OP : std_logic_vector(15 downto 15);
+ signal buf_RESET_TRBNET_OUT : std_logic;
+ signal resync_counter : std_logic_vector(2 downto 0);
+ signal internal_reset : std_logic;
+ signal send_resync_counter : std_logic_vector(11 downto 0);
+ signal next_send_resync, send_resync : std_logic;
+
+ signal led_counter : std_logic_vector(17 downto 0);
+ signal rx_led, tx_led : std_logic;
+
begin
--------------------------------------------------------------------------
reset_me_x <= '0';
med_error_x <= ERROR_WAIT;
end if;
- when LINK => if( (sfp_prsnt_n = '1') or (sfp_los = '1') ) then
+ when LINK => if( (sfp_prsnt_n = '1') or (sfp_los = '1')) then
NEXT_STATE <= SLEEP;
quad_rst_x <= '1';
lane_rst_x <= '1';
rst_ctr_x <= '1';
+ elsif send_resync = '1' then
+ NEXT_STATE <= WRXA;
+ reset_me_x <= '0';
+ med_error_x <= ERROR_WAIT;
else
NEXT_STATE <= LINK;
rx_allow_x <= '1';
when QRST => state_bits <= "0001";
info_led <= timing_ctr(21); -- too high
when WPAR => state_bits <= "0010";
- info_led <= timing_ctr(21) and timing_ctr(24); -- nice frequence for human eye
+ info_led <= timing_ctr(21) and timing_ctr(24); -- nice frequency for human eye
when WLOS => state_bits <= "0011";
info_led <= timing_ctr(22);
when ALIGN => state_bits <= "0100";
end if;
end process;
+
+--Detect resync (incl. SFP_LOS)
+---------------
+
+
+ process(clock)
+ begin
+ if rising_edge(clock) then
+ buf_STAT_OP(15) <= '0';
+ buf_RESET_TRBNET_OUT <= '0';
+ if reset_me = '1' then
+ buf_RESET_TRBNET_OUT <= '0';
+ end if;
+ if buf_MED_DATAREADY_OUT = '1' then
+ if fifo_rx_dout(7 downto 0) = x"7F" then
+ resync_counter <= resync_counter + 1;
+ else
+ resync_counter <= "000";
+ end if;
+ end if;
+ if resync_counter(2) = '1' or sfp_los = '1' then
+ resync_counter <= resync_counter + 1;
+ buf_STAT_OP(15) <= '1';
+ buf_RESET_TRBNET_OUT <= '1';
+ end if;
+ if resync_counter = "111" then
+ buf_STAT_OP(15) <= '0';
+ buf_RESET_TRBNET_OUT <= '0';
+ end if;
+ end if;
+ end process;
+
+ process(clock)
+ begin
+ if rising_edge(clock) then
+ if reset_me = '1' then
+ next_send_resync <= '0';
+ send_resync_counter <= (others => '0');
+ else
+ if not (send_resync_counter = 0) then
+ send_resync_counter <= send_resync_counter + 1;
+ end if;
+ if CTRL_OP(15) = '1' and send_resync_counter = 0 then
+ next_send_resync <= '1';
+ send_resync_counter <= x"001";
+ end if;
+ if send_resync_counter = x"00F" then
+ next_send_resync <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ INST_SYNC_RESYNC : signal_sync
+ generic map(
+ WIDTH => 1,
+ DEPTH => 2
+ )
+ port map(
+ RESET => RESET,
+ CLK0 => ff_txhalfclk,
+ CLK1 => ff_txhalfclk,
+ D_IN(0) => next_send_resync,
+ D_OUT(0) => send_resync
+ );
+
--TX Fifo & Data output to Serdes
---------------------
THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
if( (last_fifo_tx_empty = '1') or (tx_allow = '0') ) then
tx_data <= x"c5bc";
tx_k <= "01";
+ elsif send_resync = '1' then
+ tx_data <= x"7F7F";
+ tx_k <= "00";
else
tx_data <= fifo_tx_dout(15 downto 0);
tx_k <= "00";
end process THE_SERDES_INPUT_PROC;
--
-med_error_out <= med_error;
+
+
+--Generate LED signals
+----------------------
+process(clock)
+ begin
+ if rising_edge(CLK) then
+ led_counter <= led_counter + 1;
+
+ if buf_med_dataready_out = '1' then
+ rx_led <= '1';
+ elsif led_counter = 0 then
+ rx_led <= '0';
+ end if;
+
+ if tx_k(0) = '0' then
+ tx_led <= '1';
+ elsif led_counter = 0 then
+ tx_led <= '0';
+ end if;
+
+ end if;
+ end process;
+
link_led <= (timing_ctr(24) or tx_allow_q) and not sfp_los;
-stat_op(8 downto 0) <= (others => '0'); -- unused
+stat_op(2 downto 0) <= med_error;
+stat_op(8 downto 3) <= (others => '0'); -- unused
stat_op(9) <= link_led;
-stat_op(10) <= buf_med_dataready_out; --rx led
-stat_op(11) <= not tx_k(0); --tx led
-stat_op(13 downto 12)<= (others => '0'); -- unused
+stat_op(10) <= rx_led; --rx led
+stat_op(11) <= tx_led; --tx led
+stat_op(12) <= '0'; -- unused
+stat_op(13) <= buf_RESET_TRBNET_OUT;
stat_op(14) <= reset_me; -- reset out
-stat_op(15) <= '0'; -- protocol error
+stat_op(15) <= buf_STAT_OP(15); -- protocol error
-- Debug output
stat_debug(3 downto 0) <= state_bits;
MED_READ_OUT : out std_logic;
MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_ERROR_OUT : out std_logic_vector (2 downto 0);
STAT : out std_logic_vector (63 downto 0);
STAT_MONITOR : out std_logic_vector ( 100 downto 0);
STAT_OP : out std_logic_vector (15 downto 0);
full_out: OUT std_logic;
empty_out: OUT std_logic;
fifostatus_out: OUT std_logic_vector(3 downto 0); --counter for 1/16th of fifo
- valid_read_out: OUT std_logic
+ valid_read_out: OUT std_logic;
+ almost_empty_out:OUT std_logic;
+ almost_full_out :OUT std_logic
);
end component trb_net_fifo_16bit_bram_dualport;
+ component signal_sync is
+ generic(
+ WIDTH : integer := 1;
+ DEPTH : integer := 2
+ );
+ port(
+ RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register
+ CLK0 : in std_logic; --clock for first FF
+ CLK1 : in std_logic; --Clock for other FF
+ D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input
+ D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output
+ );
+ end component;
signal fifo_din_a : std_logic_vector(17 downto 0);
signal fifo_dout_a : std_logic_vector(17 downto 0);
signal fifo_empty_m : std_logic;
signal fifo_full_m : std_logic;
signal fifo_valid_read_m, fifo_valid_read_a : std_logic;
+ signal fifo_almost_full_m, fifo_almost_full_a : std_logic;
+ signal fifo_almost_empty_m, fifo_almost_empty_a : std_logic;
signal fifo_reset : std_logic;
signal fifo_status_a : std_logic_vector(3 downto 0);
signal fifo_status_m : std_logic_vector(3 downto 0);
- signal last_fifo_rd_en_a, last_fifo_rd_en_m : std_logic;
signal buf_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0);
signal buf_MED_READ_OUT : std_logic;
signal buf_MED_DATAREADY_OUT : std_logic;
signal tx_allow : std_logic;
signal internal_reset : std_logic;
- signal reset_packet_num : std_logic;
signal reg_RXD : std_logic_vector(15 downto 0);
signal reg_RX_DV : std_logic;
signal reg_TX_EN : std_logic;
signal TLK_CLK_neg : std_logic;
- signal CLK_Out, CLK_FB_Out, FB_CLK : std_logic;
+ signal CLK_FB_Out, FB_CLK : std_logic;
- signal buf_STAT : std_logic_vector(33 downto 32);
type tlk_state_t is (RESETTING, WAIT_FOR_RX_LOCK, WAIT_FOR_TX_ALLOW, WORKING);
signal current_state, next_state : tlk_state_t;
signal next_tx_allow, next_rx_allow : std_logic;
signal resync_counter : std_logic_vector(2 downto 0);
signal buf_STAT_OP : std_logic_vector(15 downto 0);
- signal send_resync : std_logic;
+ signal send_resync : std_logic_vector(0 downto 0);
+ signal send_resync_counter : std_logic_vector(11 downto 0);
+ signal next_send_resync : std_logic_vector(0 downto 0);
+ signal buf_RESET_TRBNET_OUT : std_logic;
+
+ signal led_counter : std_logic_vector(17 downto 0);
+ signal rx_led, tx_led, link_led : std_logic;
+
begin
TLK_ENABLE <= not RESET;
full_out => fifo_full_a,
empty_out => fifo_empty_a,
fifostatus_out => fifo_status_a,
- valid_read_out => fifo_valid_read_a
+ valid_read_out => fifo_valid_read_a,
+ almost_empty_out=> fifo_almost_empty_a,
+ almost_full_out => fifo_almost_full_a
);
fifo_wr_en_a <= ((reg_RX_DV and not reg_RX_ER) ) and rx_allow;
-- fifo_rd_en_a <= not fifo_almost_empty_a and rx_allow;
- buf_MED_DATAREADY_OUT <= fifo_valid_read_a and fifo_dout_a(16) and rx_allow;
- MED_ERROR_OUT <= buf_MED_ERROR_OUT;
- buf_STAT_OP(2 downto 0) <= buf_MED_ERROR_OUT;
- STAT_OP <= buf_STAT_OP;
+ buf_MED_DATAREADY_OUT <= fifo_valid_read_a and fifo_dout_a(16) and not fifo_dout_a(17) and rx_allow;
fifo_reset <= internal_reset;
- fifo_din_a <= '0' & (reg_RX_DV and not reg_RX_ER) & reg_RXD;
+ fifo_din_a <= reg_RX_ER & reg_RX_DV & reg_RXD;
+
+--STAT_OP & LED
+---------------
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ led_counter <= led_counter + 1;
+
+ if buf_med_dataready_out = '1' then
+ rx_led <= '1';
+ elsif led_counter = 0 then
+ rx_led <= '0';
+ end if;
+
+ if MED_DATAREADY_IN = '1' then
+ tx_led <= '1';
+ elsif led_counter = 0 then
+ tx_led <= '0';
+ end if;
+
+ end if;
+ end process;
+
+ link_led <= (timing_ctr(24) or tx_allow_q) and not sfp_los;
+
+ stat_op(2 downto 0) <= buf_MED_ERROR_OUT;
+ stat_op(8 downto 3) <= (others => '0'); -- unused
+ stat_op(9) <= link_led;
+ stat_op(10) <= rx_led; --rx led
+ stat_op(11) <= tx_led; --tx led
+ stat_op(12) <= '0'; -- unused
+ stat_op(13) <= buf_RESET_TRBNET_OUT;
+ stat_op(14) <= SFP_LOS; -- reset out
+ stat_op(15) <= buf_RESET_TRBNET_OUT; -- protocol error
+
process(CLK)
begin
STAT(11)<= fifo_dout_a(14);
STAT(12)<= fifo_din_a(14);
-- STAT(11)<= last_fifo_rd_en_a;
+ STAT(13) <= internal_reset;
STAT(14) <= reg_RX_DV;
STAT(15) <= reg_RX_ER;
STAT(31 downto 16) <= reg_RXD;
STAT(50 downto 49) <= fifo_dout_m(17 downto 16);
STAT(54 downto 51) <= fifo_din_a(3 downto 0);
STAT(56 downto 55) <= fifo_din_a(17 downto 16);
+ STAT(58 downto 57) <= "00";
STAT(59) <= TLK_CLK_neg;
STAT(60) <= fifo_wr_en_m;
- STAT(61) <= reset_packet_num;
+ STAT(61) <= buf_RESET_TRBNET_OUT;
STAT(63 downto 62) <= resync_counter(1 downto 0);
--STAT(63 downto 57) <= (others => '0');
STAT_MONITOR(17 downto 0) <= fifo_din_a;
-
+ STAT_MONITOR(18) <= fifo_almost_full_m;
+ STAT_MONITOR(19) <= fifo_almost_full_a;
+ STAT_MONITOR(20) <= fifo_almost_empty_m;
+ STAT_MONITOR(21) <= fifo_almost_empty_a;
+ STAT_MONITOR(37 downto 22) <= CTRL_OP;
+ STAT_MONITOR(100 downto 38) <= (others => '0');
process(TLK_RX_CLK)
begin
process(CLK)
begin
if rising_edge(CLK) then
- if internal_reset = '1' or reset_packet_num = '1' then
+ if internal_reset = '1' or buf_RESET_TRBNET_OUT = '1' then
buf_MED_PACKET_NUM_OUT <= c_H0;
elsif buf_MED_DATAREADY_OUT = '1' then
if buf_MED_PACKET_NUM_OUT = c_max_word_number then
end if;
end process;
---Detect resync
+--Detect resync (incl. SFP_LOS)
---------------
+
+RESET_TRBNET_OUT <= buf_RESET_TRBNET_OUT;
+
process(CLK)
begin
if rising_edge(CLK) then
buf_STAT_OP(15) <= '0';
- reset_packet_num <= '0';
+ buf_RESET_TRBNET_OUT <= '0';
+ if RESET = '1' or internal_reset = '1' then
+ buf_RESET_TRBNET_OUT <= '0';
+ end if;
if buf_MED_DATAREADY_OUT = '1' then
if fifo_dout_a(7 downto 0) = x"7F" then
resync_counter <= resync_counter + 1;
resync_counter <= "000";
end if;
end if;
- if resync_counter = "100" then
- buf_STAT_OP(15) <= '1';
- reset_packet_num <= '1';
+ if resync_counter(2) = '1' or SFP_LOS = '1' then
+ resync_counter <= resync_counter + 1;
+ buf_STAT_OP(15) <= '1';
+ buf_RESET_TRBNET_OUT <= '1';
+ end if;
+ if resync_counter = "111" then
+ buf_STAT_OP(15) <= '0';
+ buf_RESET_TRBNET_OUT <= '0';
end if;
end if;
end process;
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ next_send_resync <= "0";
+ send_resync_counter <= (others => '0');
+ else
+ if not (send_resync_counter = 0) then
+ send_resync_counter <= send_resync_counter + 1;
+ end if;
+ if CTRL_OP(15) = '1' and send_resync_counter(11 downto 4) = 0 then
+ next_send_resync <= "1";
+ send_resync_counter <= x"001";
+ end if;
+ if send_resync_counter = x"00F" then
+ next_send_resync <= "0";
+ end if;
+ end if;
+ end if;
+ end process;
+
+ INST_SYNC_RESYNC : signal_sync
+ generic map(
+ WIDTH => 1,
+ DEPTH => 2
+ )
+ port map(
+ RESET => RESET,
+ CLK0 => TLK_CLK_neg,
+ CLK1 => TLK_CLK_neg,
+ D_IN => next_send_resync,
+ D_OUT => send_resync
+ );
+
-------------
--Sender
-------------
PSCLK => '0',
RST => RESET,
CLK0 => CLK_FB_Out, -- for feedback
- CLK90=> CLK_Out,
+ CLK90=> open,
LOCKED => open
);
--
valid_read_out => fifo_valid_read_m,
full_out => fifo_full_m,
empty_out => fifo_empty_m,
- fifostatus_out => fifo_status_m
+ fifostatus_out => fifo_status_m,
+ almost_empty_out=> fifo_almost_empty_m,
+ almost_full_out => fifo_almost_full_m
);
TLK_TX_ER <= '0';
begin
if rising_edge(CLK) then
fifo_wr_en_m <= (MED_DATAREADY_IN and buf_MED_READ_OUT);-- or fifo_almost_empty_m;
- fifo_din_m <= '0' & (MED_DATAREADY_IN and buf_MED_READ_OUT) & MED_DATA_IN;
+ fifo_din_m <= MED_PACKET_NUM_IN(2) & (MED_DATAREADY_IN and buf_MED_READ_OUT) & MED_DATA_IN;
end if;
end process;
process(TLK_CLK_neg)
begin
if rising_edge(TLK_CLK_neg) then
- if send_resync = '0' then
+ if send_resync(0) = '0' then
reg_TXD <= fifo_dout_m(15 downto 0);
else
reg_TXD <= x"007F";
end if;
- reg_TX_EN <= (fifo_valid_read_m and fifo_dout_m(16)) or send_resync; --last_fifo_rd_en_m;
+ reg_TX_EN <= (fifo_valid_read_m and fifo_dout_m(16)) or send_resync(0); --last_fifo_rd_en_m;
end if;
end process;
+
-------------
--Medium states
-------------
- medium_states : process(current_state, tx_allow, rx_allow, internal_reset,
- reg_RX_ER, reg_RX_DV, buf_MED_ERROR_OUT, counter)
+ medium_states : process(current_state, tx_allow, rx_allow, internal_reset, MED_READ_IN,
+ reg_RX_ER, reg_RX_DV, buf_MED_ERROR_OUT, counter, send_resync)
begin
next_state <= current_state;
next_tx_allow <= tx_allow;
next_state <= WAIT_FOR_RX_LOCK;
next_MED_ERROR_OUT <= ERROR_WAIT;
end if;
+ if MED_READ_IN = '0' then
+ next_MED_ERROR_OUT <= ERROR_NC;
+ end if;
+ if send_resync(0) = '1' then
+ next_state <= WAIT_FOR_RX_LOCK;
+ next_MED_ERROR_OUT <= ERROR_NC;
+ counter_reset <= '1';
+ end if;
end process;
process(current_state)
signal CRC : std_logic_vector(15 downto 0);
signal buf_MED_DATAREADY_OUT : std_logic;
signal buf_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal sbuf_status : std_logic;
+ signal crc_match : std_logic;
begin
-- gen_sbuf : if SECURE_MODE = 1 generate
SYN_DATAREADY_OUT => buf_MED_DATAREADY_OUT,
SYN_DATA_OUT => MED_DATA_OUT,
SYN_PACKET_NUM_OUT => buf_MED_PACKET_NUM_OUT,
- SYN_READ_IN => MED_READ_IN
+ SYN_READ_IN => MED_READ_IN,
+ STAT_BUFFER => sbuf_status
);
MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT;
CLK_EN => CRC_enable,
DATA_IN => INT_DATA_IN,
CRC_OUT => CRC,
- CRC_match => open
+ CRC_match => crc_match
);
end generate;
gen_no_crc : if USE_CHECKSUM = 0 generate
type fsm_state_t is (IDLE, HEADER_RECV, REG_READ, REG_WRITE, ONE_READ, ONE_WRITE, SEND_REPLY_SHORT_TRANSFER, MEM_START_WRITE,
MEM_READ, MEM_WRITE, DAT_START_READ, DAT_READ, SEND_REPLY_DATA_finish, ADDRESS_ACK, ADDRESS_RECV,MEM_START_READ);
signal current_state, next_state : fsm_state_t;
- signal HDR_F1, HDR_F2, HDR_F3, HDR_F0 : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal next_HDR_F1, next_HDR_F2, next_HDR_F3, next_HDR_F0 : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+-- signal HDR_F1, HDR_F2, HDR_F3, HDR_F0 : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+-- signal next_HDR_F1, next_HDR_F2, next_HDR_F3, next_HDR_F0 : std_logic_vector(c_DATA_WIDTH-1 downto 0);
signal next_Reg_high, saved_Reg_high : std_logic_vector(15 downto 0);
signal next_Reg_low, saved_Reg_low : std_logic_vector(15 downto 0);
signal next_address, address : std_logic_vector(15 downto 0) := x"0000";
fsm : process(current_state,
API_DATA_IN, API_PACKET_NUM_IN, API_TYP_IN, API_DATAREADY_IN, API_READ_IN,
- HDR_F1, HDR_F2, HDR_F3, address, saved_Reg_high, saved_Reg_low, saved_operation,
+ address, saved_Reg_high, saved_Reg_low, saved_operation,
buf_API_SEND_OUT, next_packet_counter, buf_API_DATA_OUT, buf_API_SHORT_TRANSFER_OUT,
REGISTERS_IN, buf_REGISTERS_OUT, reg_enable_pattern, DAT_NO_MORE_DATA_IN,
DAT_DATAREADY_IN, buf_DAT_DATA_IN, ADR_REJECTED,
ADR_READ_OUT, ADR_DATAREADY_OUT, ADR_DATA_OUT, ADR_PACKET_NUM_OUT, length, dont_understand,
buf_rom_read_addr, ADR_SEND_OUT, rom_read_dout, COMMON_STAT_REG_IN, buf_COMMON_CTRL_REG_OUT
+-- , HDR_F1, HDR_F2, HDR_F3
)
variable regnum_STAT : integer range 0 to 2**NUM_STAT_REGS-1;
variable regnum_CTRL : integer range 0 to 2**NUM_CTRL_REGS-1;
variable regnum_cCTRL : integer range 0 to std_COMCTRLREG-1;
begin
next_state <= current_state;
- next_HDR_F1 <= HDR_F1;
- next_HDR_F2 <= HDR_F2;
- next_HDR_F3 <= HDR_F3;
+-- next_HDR_F1 <= HDR_F1;
+-- next_HDR_F2 <= HDR_F2;
+-- next_HDR_F3 <= HDR_F3;
next_address <= address;
next_Reg_high <= saved_Reg_high;
next_Reg_low <= saved_Reg_low;
when HEADER_RECV => --read and save HDR
if API_DATAREADY_IN = '1' then
case API_PACKET_NUM_IN is
- when c_F0 =>
- next_HDR_F0 <= API_DATA_IN;
- when c_F1 =>
- next_HDR_F1 <= API_DATA_IN;
- when c_F2 =>
- next_HDR_F2 <= API_DATA_IN;
+-- when c_F0 =>
+-- next_HDR_F0 <= API_DATA_IN;
+-- when c_F1 =>
+-- next_HDR_F1 <= API_DATA_IN;
+-- when c_F2 =>
+-- next_HDR_F2 <= API_DATA_IN;
when c_F3 =>
- next_HDR_F3 <= API_DATA_IN;
+-- next_HDR_F3 <= API_DATA_IN;
case API_DATA_IN(3 downto 0) is
when c_read_register_type => next_state <= ONE_READ;
when c_write_register_type => next_state <= ONE_WRITE;
end case;
when MEM_START_WRITE =>
- if API_PACKET_NUM_IN = c_F0 and API_TYP_IN = TYPE_DAT and API_DATAREADY_IN = '1' then
+ if USE_DAT_PORT = c_NO then
+ next_state <= SEND_REPLY_SHORT_TRANSFER;
+ next_dont_understand <= '1';
+ elsif API_PACKET_NUM_IN = c_F0 and API_TYP_IN = TYPE_DAT and API_DATAREADY_IN = '1' then
next_address <= API_DATA_IN;
next_state <= MEM_WRITE;
end if;
dont_understand <= '0';
else
current_state <= next_state;
- HDR_F0 <= next_HDR_F0;
- HDR_F1 <= next_HDR_F1;
- HDR_F2 <= next_HDR_F2;
- HDR_F3 <= next_HDR_F3;
+-- HDR_F0 <= next_HDR_F0;
+-- HDR_F1 <= next_HDR_F1;
+-- HDR_F2 <= next_HDR_F2;
+-- HDR_F3 <= next_HDR_F3;
buf_API_SEND_OUT <= next_API_SEND_OUT;
buf_API_SHORT_TRANSFER_OUT <= next_API_SHORT_TRANSFER_OUT;
address <= next_address;
process(CLK)
begin
if rising_edge(CLK) then
- if DAT_DATAREADY_IN = '1' then
+ if RESET = '1' then
+ buf_DAT_DATA_IN <= (others => '0');
+ elsif DAT_DATAREADY_IN = '1' then
buf_DAT_DATA_IN <= DAT_DATA_IN;
end if;
end if;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_ARITH.ALL;
USE IEEE.std_logic_UNSIGNED.ALL;
-LIBRARY unisim;
-USE UNISIM.VComponents.all;
library work;
use work.trb_net_std.all;
INPUT_IN : in std_logic_vector (WIDTH-1 downto 0);
RESULT_OUT: out std_logic_vector (WIDTH-1 downto 0);
ENABLE : in std_logic;
- CTRL : in std_logic_vector (31 downto 0)
+ CTRL : in std_logic_vector (9 downto 0)
);
end trb_net_priority_arbiter;
PATTERN_OUT : out STD_LOGIC_VECTOR (WIDTH-1 downto 0)
);
END component;
-
+
signal next_fixed_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0);
signal next_rr_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0);
signal next_p1_pattern, current_p1_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0);
signal leading_rr_pattern1, leading_rr_pattern2: STD_LOGIC_VECTOR (WIDTH-1 downto 0);
signal next_final_pattern, current_final_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0);
signal current_rr_mask, next_rr_mask: STD_LOGIC_VECTOR (7 downto 0);
-
+
signal use_rr: STD_LOGIC;
-
-
+ signal enc1_pattern : std_logic_vector(WIDTH-1 downto 0);
+
begin
---------------------------------------------------------------------------
)
port map(
INPUT_IN => INPUT_IN,
+ PATTERN_OUT => enc1_pattern,
RESULT_OUT => next_fixed_pattern
);
-- from the current p1 and p2 pattern, look what would be the next rr pattern
-- find out what would be the next rr pattern
-- we call this proposed pattern
-
+
ENC2: trb_net_priority_encoder
generic map (
WIDTH => WIDTH
end if;
if or_all(sampled_rr_pattern1) = '1' then
- next_rr_pattern <= proposed_rr_pattern1;
+ next_rr_pattern <= proposed_rr_pattern1;
elsif or_all(sampled_rr_pattern2) = '1' then
next_rr_pattern <= proposed_rr_pattern2;
end if;
-
+
if (CTRL(9) = '1') and (CTRL(8) = '0') then -- rol
next_rr_mask(6 downto 0) <= current_rr_mask(7 downto 1);
next_rr_mask(7) <= current_rr_mask(0);
end process;
end architecture;
-
+
type BUFFER_STATE is (BUFFER_EMPTY, BUFFER_B2_FULL, BUFFER_B1_FULL);
signal current_buffer_state, next_buffer_state : BUFFER_STATE;
- signal current_buffer_state_int : STD_LOGIC_VECTOR (1 downto 0);
+-- signal current_buffer_state_int : STD_LOGIC_VECTOR (1 downto 0);
signal current_got_overflow, next_got_overflow : std_logic;
signal combined_COMB_DATAREADY_IN: std_logic;
next_got_overflow <= current_got_overflow;
if current_buffer_state = BUFFER_EMPTY then
- current_buffer_state_int <= "00";
+-- current_buffer_state_int <= "00";
if combined_COMB_DATAREADY_IN = '1' then
-- COMB logic is writing into the sbuf
next_buffer_state <= BUFFER_B2_FULL;
next_SYN_DATAREADY_OUT <= '1';
end if;
elsif current_buffer_state = BUFFER_B2_FULL then
- current_buffer_state_int <= "01";
+-- current_buffer_state_int <= "01";
if combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '1' then
-- COMB logic is writing into the sbuf
-- at the same time syn port is reading
next_SYN_DATAREADY_OUT <= '1';
end if;
elsif current_buffer_state = BUFFER_B1_FULL then
- current_buffer_state_int <= "10";
+-- current_buffer_state_int <= "10";
next_SYN_DATAREADY_OUT <= '1';
next_next_READ_OUT <= '0';
end entity trb_net_fifo_16bit_bram_dualport;
architecture trb_net_fifo_16bit_bram_dualport_arch of trb_net_fifo_16bit_bram_dualport is
+
+ signal buf_empty_out, buf_full_out : std_logic;
+
attribute box_type: string;
component xilinx_fifo_dualport_18x1k
port (
wr_clk => write_clock_in,
wr_en => write_enable_in,
dout => read_data_out,
- empty => empty_out,
- full => full_out,
+ empty => buf_empty_out,
+ full => buf_full_out,
valid => valid_read_out
);
-almost_full_out <= '0';
-almost_empty_out <= '0';
+empty_out <= buf_empty_out;
+full_out <= buf_full_out;
+almost_full_out <= buf_full_out;
+almost_empty_out <= buf_empty_out;
fifostatus_out <= (others => '0');
-end architecture trb_net_fifo_16bit_bram_dualport_arch;
+end architecture;
jspc29 / trbnet.git / commitdiff