added hub entities, Jan

diff --git a/trb_net16_base_hub.vhd b/trb_net16_base_hub.vhd
new file mode 100644 (file)
index 0000000..4f79576
--- /dev/null
+++ b/trb_net16_base_hub.vhd
@@ -0,0 +1,450 @@
+LIBRARY IEEE;\r
+USE IEEE.std_logic_1164.ALL;\r
+USE IEEE.std_logic_ARITH.ALL;\r
+USE IEEE.std_logic_UNSIGNED.ALL;\r
+\r
+use work.trb_net_std.all;\r
+\r
+\r
+entity trb_net16_base_hub is\r
+  generic{\r
+  --media interfaces\r
+    MII_NUMBER              : integer range 2 to 16 := 2;\r
+    MII_INIT_DEPTH          : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000";\r
+    MII_REPLY_DEPTH         : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000";\r
+  -- settings for apis\r
+    API_NUMBER              : integer range 0 to 16 := 1;\r
+    API_CHANNELS            : bit_vector(API_NUMBER*4-1 downto 0) := x"3";\r
+                                --channel, each api is connected to\r
+    API_TYPE                : bit_vector(API_NUMBER*4-1 downto 0) := x"1";\r
+    API_INIT_DEPTH          : bit_vector(API_NUMBER*4-1 downto 0) := x"1";\r
+    API_REPLY_DEPTH         : bit_vector(API_NUMBER*4-1 downto 0) := x"1";\r
+    API_FIFO_TO_INT_DEPTH   : bit_vector(API_NUMBER*4-1 downto 0) := x"1";\r
+    API_FIFO_TO_APL_DEPTH   : bit_vector(API_NUMBER*4-1 downto 0) := x"1";\r
+  --trigger reading interfaces\r
+    TRG_NUMBER              : integer range 0 to 16 := 2;\r
+    TRG_CHANNELS            : bit_vector(API_NUMBER*4-1 downto 0) := x"10";\r
+  --general settings\r
+    MUX_SECURE_MODE         : integer range 0 to 1 := 0;\r
+    MUX_WIDTH               : integer range 1 to 5 := 3;\r
+    MUX_CTRL_CHANNEL        : integer range 0 to 2**(MUX_WIDTH-1)-1 := 3;\r
+    DATA_WIDTH              : integer range 16 to 16 := 16;\r
+    NUM_WIDTH               : integer range 2 to 2 := 2\r
+    }\r
+  port {\r
+    CLK    : in std_logic;\r
+         RESET  : in std_logic;\r
+         CLK_EN : in std_logic;\r
+         \r
+    --Media interfacces\r
+    --each port is one bit bigger than actually necessary to avoid error messages\r
+       MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER downto 0);\r
+    MED_DATA_OUT      : out std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0);\r
+    MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0);\r
+    MED_READ_IN       : in  std_logic_vector (MII_NUMBER downto 0);\r
+    MED_DATAREADY_IN  : in  std_logic_vector (MII_NUMBER downto 0);\r
+    MED_DATA_IN       : in  std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0);\r
+    MED_PACKET_NUM_IN : in  std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0);\r
+    MED_READ_OUT      : out std_logic_vector (MII_NUMBER downto 0); -- buffer reads a word from media\r
+    MED_ERROR_IN      : in  std_logic_vector (MII_NUMBER*3 downto 0);\r
+    --API: interfaces\r
+    APL_DATA_IN       : in  std_logic_vector (APL_NUMBER*DATA_WIDTH downto 0);\r
+    APL_PACKET_NUM_IN : in  std_logic_vector (APL_NUMBER*NUM_WIDTH downto 0);\r
+    APL_WRITE_IN      : in  std_logic_vector (APL_NUMBER downto 0);\r
+    APL_FIFO_FULL_OUT : out std_logic_vector (APL_NUMBER downto 0);\r
+    APL_SHORT_TRANSFER_IN : in  std_logic_vector (APL_NUMBER downto 0);\r
+    APL_DTYPE_IN      : in  std_logic_vector (APL_NUMBER*4 downto 0);\r
+    APL_ERROR_PATTERN_IN : in  std_logic_vector (APL_NUMBER*32 downto 0);\r
+    APL_SEND_IN       : in  std_logic_vector (APL_NUMBER downto 0);\r
+    APL_TARGET_ADDRESS_IN : in  std_logic_vector (APL_NUMBER*16 downto 0);\r
+    APL_DATA_OUT      : out std_logic_vector (APL_NUMBER*16 downto 0);\r
+    APL_PACKET_NUM_OUT: out std_logic_vector (APL_NUMBER*NUM_WIDTH downto 0);\r
+    APL_TYP_OUT       : out std_logic_vector (APL_NUMBER*3 downto 0);\r
+    APL_DATAREADY_OUT : out std_logic_vector (APL_NUMBER downto 0);\r
+    APL_READ_IN       : in  std_logic_vector (APL_NUMBER downto 0);\r
+    APL_RUN_OUT       : out std_logic_vector (APL_NUMBER downto 0);\r
+    APL_MY_ADDRESS_IN : in  std_logic_vector (APL_NUMBRT*16 downto 0);\r
+    APL_SEQNR_OUT     : out std_logic_vector (APL_NUMBER*8 downto 0);\r
+    --TRG interfaces\r
+    TRG_GOT_TRIGGER_OUT   : out std_logic_vector (TRG_NUMBER downto 0);\r
+    TRG_ERROR_PATTERN_OUT : out std_logic_vector (TRG_NUMBER*32 downto 0);\r
+    TRG_DTYPE_OUT         : out std_logic_vector (TRG_NUMBER*4 downto 0);\r
+    TRG_SEQNR_OUT         : out std_logic_vector (TRG_NUMBER*8 downto 0);\r
+    TRG_ERROR_PATTERN_IN  : in  std_logic_vector (TRG_NUMBER*32 downto 0);\r
+    TRG_RELEASE_IN        : in  std_logic_vector (TRG_NUMBER downto 0);\r
+    --Status ports (for debugging)\r
+    HUB_CHANNEL_STAT   : out std_logic_vector (2**(MUX_WIDTH-1)*16 downto 0);\r
+    HUB_GEN_STAT       : out std_logic_vector (31 downto 0);\r
+    MPLEX_CTRL         : out std_logic_vector (MII_NUMBER*32-1 downto 0);\r
+    \r
+    }\r
+end entity;\r
+\r
+architecture trb_net16_base_hub_arch of trb_net16_base_hub is\r
+\r
+  signal m_DATAREADY_OUT : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);\r
+  signal m_DATA_OUT      : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0);\r
+  signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0);\r
+  signal m_READ_IN       : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);\r
+  signal m_DATAREADY_IN  : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);\r
+  signal m_DATA_IN       : std_logic_vector (MII_NUMBER*DATA_WIDTH*2**MUX_WIDTH-1 downto 0);\r
+  signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*NUM_WIDTH*2**MUX_WIDTH-1 downto 0);\r
+  signal m_READ_OUT      : std_logic_vector (MII_NUMBER*2**MUX_WIDTH-1 downto 0);\r
+\r
+  signal hub_to_buf_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
+  signal hub_to_buf_INIT_DATA     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);\r
+  signal hub_to_buf_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);\r
+  signal hub_to_buf_INIT_READ     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
+\r
+  signal buf_to_hub_INIT_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
+  signal buf_to_hub_INIT_DATA     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);\r
+  signal buf_to_hub_INIT_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);\r
+  signal buf_to_hub_INIT_READ     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
+\r
+  signal hub_to_buf_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
+  signal hub_to_buf_REPLY_DATA     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);\r
+  signal hub_to_buf_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);\r
+  signal hub_to_buf_REPLY_READ     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
+\r
+  signal buf_to_hub_REPLY_DATAREADY: std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);\r
+  signal buf_to_hub_REPLY_DATA     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*DATA_WIDTH-1 downto 0);\r
+  signal buf_to_hub_REPLY_PACKET_NUM:std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*NUM_WIDTH-1 downto 0);\r
+  signal buf_to_hub_REPLY_READ     : std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER-1 downto 0);  \r
+  \r
+  component trb_net16_base_hub_logic is\r
+  generic (\r
+  --media interfaces\r
+    POINT_NUMBER        : integer range 2 to 16 := 2;\r
+    INIT_DEPTH          : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111";\r
+    REPLY_DEPTH         : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111";\r
+  --general settings\r
+    DATA_WIDTH          : integer range 16 to 16 := 16;\r
+    NUM_WIDTH           : integer range 2 to 2 := 2\r
+    );\r
+  port (\r
+    CLK    : in std_logic;\r
+         RESET  : in std_logic;\r
+         CLK_EN : in std_logic;\r
+    INIT_DATAREADY_IN     : in  std_logic_vector (POINT_NUMBER downto 0);\r
+    INIT_DATA_IN          : in  std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0);\r
+    INIT_PACKET_NUM_IN    : in  std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0);\r
+    INIT_READ_OUT         : out std_logic_vector (POINT_NUMBER downto 0);\r
+    INIT_DATAREADY_OUT    : out std_logic_vector (POINT_NUMBER downto 0);\r
+    INIT_DATA_OUT         : out std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0);\r
+    INIT_PACKET_NUM_OUT   : out std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0);\r
+    INIT_READ_IN          : in  std_logic_vector (POINT_NUMBER downto 0);\r
+    REPLY_HEADER_OUT      : out std_logic_vector (POINT_NUMBER downto 0);\r
+    REPLY_DATAREADY_IN    : in  std_logic_vector (POINT_NUMBER downto 0);\r
+    REPLY_DATA_IN         : in  std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0);\r
+    REPLY_PACKET_NUM_IN   : in  std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0);\r
+    REPLY_READ_OUT        : out std_logic_vector (POINT_NUMBER downto 0);\r
+    REPLY_DATAREADY_OUT   : out std_logic_vector (POINT_NUMBER downto 0);\r
+    REPLY_DATA_OUT        : out std_logic_vector (DATA_WIDTH*POINT_NUMBER downto 0);\r
+    REPLY_PACKET_NUM_OUT  : out std_logic_vector (NUM_WIDTH*POINT_NUMBER downto 0);\r
+    REPLY_READ_IN         : in  std_logic_vector (POINT_NUMBER downto 0);\r
+    STAT_CHANNEL       : out std_logic_vector (15 downto 0);\r
+    STAT_GEN           : out std_logic_vector (31 downto 0);\r
+    CTRL_CHANNEL       : in  std_logic_vector (31 downto 0);\r
+    CTRL_GEN           : in  std_logic_vector (31 downto 0)    \r
+    );\r
+end component;\r
+\r
+ \r
+  component trb_net16_io_multiplexer is\r
+    generic (\r
+      DATA_WIDTH : integer := 16;\r
+      NUM_WIDTH : integer := 2;\r
+      MUX_WIDTH : integer range 1 to 5 := 3;\r
+      MUX_SECURE_MODE : integer range 0 to 1 := 0\r
+      );\r
+    port(\r
+      --  Misc\r
+      CLK    : in std_logic;\r
+      RESET  : in std_logic;\r
+      CLK_EN : in std_logic;\r
+      --  Media direction port\r
+      MED_DATAREADY_IN:  in  std_logic;\r
+      MED_DATA_IN:       in  std_logic_vector (DATA_WIDTH-1 downto 0);\r
+      MED_PACKET_NUM_IN: in  std_logic_vector (NUM_WIDTH-1 downto 0);\r
+      MED_READ_OUT:      out std_logic;\r
+      MED_DATAREADY_OUT: out std_logic;\r
+      MED_DATA_OUT:      out std_logic_vector (DATA_WIDTH-1 downto 0);\r
+      MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0);\r
+      MED_READ_IN:       in  std_logic;\r
+      -- Internal direction port\r
+      INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);\r
+      INT_DATA_OUT:      out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);\r
+      INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);\r
+      INT_READ_IN:       in  std_logic_vector (2**MUX_WIDTH-1 downto 0);\r
+      INT_DATAREADY_IN:  in  std_logic_vector (2**MUX_WIDTH-1 downto 0);\r
+      INT_DATA_IN:       in  std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);\r
+      INT_PACKET_NUM_IN: in  std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);\r
+      INT_READ_OUT:      out std_logic_vector (2**MUX_WIDTH-1 downto 0);\r
+      -- Status and control port\r
+      CTRL:              in  std_logic_vector (31 downto 0);\r
+      STAT:              out std_logic_vector (31 downto 0)\r
+      );\r
+  end component;\r
+\r
+  component trb_net16_iobuf is\r
+    generic (\r
+      INIT_DEPTH : integer := 1;\r
+      REPLY_DEPTH : integer := 1\r
+      );\r
+    port(\r
+      --  Misc\r
+      CLK    : in std_logic;      \r
+      RESET  : in std_logic;    \r
+      CLK_EN : in std_logic;\r
+      --  Media direction port\r
+      MED_INIT_DATAREADY_OUT: out std_logic;  --Data word ready to be read out\r
+      MED_INIT_DATA_OUT:      out std_logic_vector (15 downto 0); -- Data word\r
+      MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);\r
+      MED_INIT_READ_IN:       in  std_logic; -- Media is reading\r
+      MED_INIT_DATAREADY_IN:  in  std_logic; -- Data word is offered by the Media\r
+      MED_INIT_DATA_IN:       in  std_logic_vector (15 downto 0); -- Data word\r
+      MED_INIT_PACKET_NUM_IN: in  std_logic_vector (1 downto 0);\r
+      MED_INIT_READ_OUT:      out std_logic; -- buffer reads a word from media\r
+      MED_INIT_ERROR_IN:      in  std_logic_vector (2 downto 0);  -- Status bits\r
+      MED_REPLY_DATAREADY_OUT: out std_logic;  --Data word ready to be read out\r
+      MED_REPLY_DATA_OUT:      out std_logic_vector (15 downto 0); -- Data word\r
+      MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);\r
+      MED_REPLY_READ_IN:       in  std_logic; -- Media is reading\r
+      MED_REPLY_DATAREADY_IN:  in  std_logic; -- Data word is offered by the Media\r
+      MED_REPLY_DATA_IN:       in  std_logic_vector (15 downto 0); -- Data word\r
+      MED_REPLY_PACKET_NUM_IN: in  std_logic_vector (1 downto 0);\r
+      MED_REPLY_READ_OUT:      out std_logic; -- buffer reads a word from media\r
+      MED_REPLY_ERROR_IN:      in  std_logic_vector (2 downto 0);  -- Status bits\r
+      -- Internal direction port\r
+      INT_INIT_DATAREADY_OUT: out std_logic;\r
+      INT_INIT_DATA_OUT:      out std_logic_vector (15 downto 0); -- Data word\r
+      INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);\r
+      INT_INIT_READ_IN:       in  std_logic;\r
+      INT_INIT_DATAREADY_IN:  in  std_logic;\r
+      INT_INIT_DATA_IN:       in  std_logic_vector (15 downto 0); -- Data word\r
+      INT_INIT_PACKET_NUM_IN: in  std_logic_vector (1 downto 0);\r
+      INT_INIT_READ_OUT:      out std_logic;\r
+      INT_REPLY_HEADER_IN:     in  std_logic;\r
+      INT_REPLY_DATAREADY_OUT: out std_logic;\r
+      INT_REPLY_DATA_OUT:      out std_logic_vector (15 downto 0); -- Data word\r
+      INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);\r
+      INT_REPLY_READ_IN:       in  std_logic;\r
+      INT_REPLY_DATAREADY_IN:  in  std_logic;\r
+      INT_REPLY_DATA_IN:       in  std_logic_vector (15 downto 0); -- Data word\r
+      INT_REPLY_PACKET_NUM_IN: in  std_logic_vector (1 downto 0);\r
+      INT_REPLY_READ_OUT:      out std_logic;\r
+      -- Status and control port\r
+      STAT_GEN:          out std_logic_vector (31 downto 0); -- General Status\r
+      STAT_LOCKED:       out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control\r
+      STAT_INIT_BUFFER:  out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control\r
+      STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status\r
+      CTRL_GEN:          in  std_logic_vector (31 downto 0);\r
+      CTRL_LOCKED:       in  std_logic_vector (31 downto 0);\r
+      STAT_CTRL_INIT_BUFFER:  in  std_logic_vector (31 downto 0);\r
+      STAT_CTRL_REPLY_BUFFER: in  std_logic_vector (31 downto 0)\r
+      );\r
+  end component;\r
+  \r
+  \r
+  component trb_net16_base_api is\r
+    generic (\r
+      API_TYPE : integer := API_TYPE;\r
+      FIFO_TO_INT_DEPTH : integer := 1;\r
+      FIFO_TO_APL_DEPTH : integer := 1;\r
+      FIFO_TERM_BUFFER_DEPTH  : integer := 0);\r
+    port(\r
+      --  Misc\r
+      CLK    : in std_logic;\r
+      RESET  : in std_logic;\r
+      CLK_EN : in std_logic;\r
+      -- APL Transmitter port\r
+      APL_DATA_IN           : in  std_logic_vector (15 downto 0); -- Data word "application to network"\r
+      APL_PACKET_NUM_IN     : in  std_logic_vector (1 downto 0);\r
+      APL_WRITE_IN          : in  std_logic; -- Data word is valid and should be transmitted\r
+      APL_FIFO_FULL_OUT     : out std_logic; -- Stop transfer, the fifo is full\r
+      APL_SHORT_TRANSFER_IN : in  std_logic; --\r
+      APL_DTYPE_IN          : in  std_logic_vector (3 downto 0);  -- see NewTriggerBusNetworkDescr\r
+      APL_ERROR_PATTERN_IN  : in  std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr\r
+      APL_SEND_IN           : in  std_logic; -- Release sending of the data\r
+      APL_TARGET_ADDRESS_IN : in  std_logic_vector (15 downto 0); -- Address of\r
+      -- Receiver port\r
+      APL_DATA_OUT          : out std_logic_vector (15 downto 0); -- Data word "network to application"\r
+      APL_PACKET_NUM_OUT    : out std_logic_vector (1 downto 0);\r
+      APL_TYP_OUT           : out std_logic_vector (2 downto 0);  -- Which kind of data word: DAT, HDR or TRM\r
+      APL_DATAREADY_OUT     : out std_logic; -- Data word is valid and might be read out\r
+      APL_READ_IN           : in  std_logic; -- Read data word\r
+      -- APL Control port\r
+      APL_RUN_OUT           : out std_logic; -- Data transfer is running\r
+      APL_MY_ADDRESS_IN     : in  std_logic_vector (15 downto 0);  -- My own address (temporary solution!!!)\r
+      APL_SEQNR_OUT         : out std_logic_vector (7 downto 0);\r
+      -- Internal direction port\r
+      INT_MASTER_DATAREADY_OUT  : out std_logic;\r
+      INT_MASTER_DATA_OUT       : out std_logic_vector (15 downto 0); -- Data word\r
+      INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);\r
+      INT_MASTER_READ_IN        : in  std_logic;\r
+      INT_MASTER_DATAREADY_IN   : in  std_logic;\r
+      INT_MASTER_DATA_IN        : in  std_logic_vector (15 downto 0); -- Data word\r
+      INT_MASTER_PACKET_NUM_IN  : in  std_logic_vector (1 downto 0);\r
+      INT_MASTER_READ_OUT       : out std_logic;\r
+      INT_SLAVE_HEADER_IN       : in  std_logic; -- Concentrator kindly asks to resend the last HDR\r
+      INT_SLAVE_DATAREADY_OUT   : out std_logic;\r
+      INT_SLAVE_DATA_OUT        : out std_logic_vector (15 downto 0); -- Data word\r
+      INT_SLAVE_PACKET_NUM_OUT  : out std_logic_vector (1 downto 0);\r
+      INT_SLAVE_READ_IN         : in  std_logic;\r
+      INT_SLAVE_DATAREADY_IN    : in  std_logic;\r
+      INT_SLAVE_DATA_IN         : in  std_logic_vector (15 downto 0); -- Data word\r
+      INT_SLAVE_PACKET_NUM_IN   : in  std_logic_vector (1 downto 0);\r
+      INT_SLAVE_READ_OUT        : out std_logic;\r
+      -- Status and control port\r
+      STAT_FIFO_TO_INT          : out std_logic_vector(31 downto 0);\r
+      STAT_FIFO_TO_APL          : out std_logic_vector(31 downto 0)\r
+      );\r
+  end component;\r
+  \r
+  \r
+  \r
+begin\r
+\r
+--generate multiplexers\r
+  gen_muxes: for i in 0 to MII_NUMBER-1 generate\r
+    MPLEX: trb_net16_io_multiplexer\r
+      generic map (\r
+        DATA_WIDTH  => DATA_WIDTH,\r
+        NUM_WIDTH   => NUM_WIDTH,\r
+        MUX_WIDTH   => MUX_WIDTH,\r
+        MUX_SECURE_MODE => MUX_SECURE_MODE\r
+        )\r
+      port map (\r
+        CLK      => CLK,\r
+        RESET    => RESET,\r
+        CLK_EN   => CLK_EN,\r
+        MED_DATAREADY_IN   => MED_DATAREADY_IN(i*2+1 downto i*2),\r
+        MED_DATA_IN        => MED_DATA_IN((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
+        MED_PACKET_NUM_IN  => MED_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
+        MED_READ_OUT       => MED_READ_OUT(i*2+1 downto i*2),\r
+        MED_DATAREADY_OUT  => MED_DATAREADY_OUT(i*2+1 downto i*2),\r
+        MED_DATA_OUT       => MED_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
+        MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
+        MED_READ_IN        => MED_READ_IN(i*2+1 downto i*2),\r
+        INT_DATAREADY_OUT  => m_DATAREADY_IN(i*2+1 downto i*2),\r
+        INT_DATA_OUT       => m_DATA_IN((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
+        INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
+        INT_READ_IN        => m_READ_OUT(i*2+1 downto i*2),\r
+        INT_DATAREADY_IN   => m_DATAREADY_OUT(i*2+1 downto i*2),\r
+        INT_DATA_IN        => m_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
+        INT_PACKET_NUM_IN  => m_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
+        INT_READ_OUT       => m_READ_IN(i*2+1 downto i*2),\r
+        CTRL               => MPLEX_CTRL((i+1)*32-1) downto i*32)\r
+        );\r
+  end generate;\r
+\r
+--generate IOBufs for MII\r
+  gen_iobufs: for i in 0 to 2**(MUX_WIDTH-1)*MII_NUMBER-1 generate\r
+    IOBUF: trb_net16_iobuf\r
+      generic map (\r
+        INIT_DEPTH =>  to_integer(MII_INIT_DEPTH((i+1)*4-1 downto i)),\r
+        REPLY_DEPTH => to_integer(MII_REPLY_DEPTH((i+1)*4-1 downto i))\r
+        )\r
+      port map (\r
+        --  Misc\r
+        CLK     => CLK ,\r
+        RESET   => RESET,\r
+        CLK_EN  => CLK_EN,\r
+        --  Media direction port\r
+        MED_INIT_DATAREADY_OUT  => m_DATAREADY_OUT(i*2),\r
+        MED_INIT_DATA_OUT       => m_DATA_OUT((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
+        MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
+        MED_INIT_READ_IN        => m_READ_IN(i*2),\r
+        \r
+        MED_INIT_DATAREADY_IN   => m_DATAREADY_IN(i*2),\r
+        MED_INIT_DATA_IN        => m_DATA_ÌN((i+1)*DATA_WIDTH*2-1 downto i*DATA_WIDTH*2),\r
+        MED_INIT_PACKET_NUM_IN  => m_PACKET_NUM_IN((i+1)*NUM_WIDTH*2-1 downto i*NUM_WIDTH*2),\r
+        MED_INIT_READ_OUT       => m_READ_OUT(i*2),\r
+        MED_INIT_ERROR_IN       => m_ERROR_IN((i+1)*3-1 downto i*3),\r
+\r
+        MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),\r
+        MED_REPLY_DATA_OUT      => m_DATA_OUT((i+2)*DATA_WIDTH*2-1 downto (i+1)*DATA_WIDTH*2),\r
+        MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i+2)*NUM_WIDTH*2-1 downto (i+1)*NUM_WIDTH*2),\r
+        MED_REPLY_READ_IN       => m_READ_IN(i*2+1),\r
+        \r
+        MED_REPLY_DATAREADY_IN  => m_DATAREADY_OUT(i*2+1),\r
+        MED_REPLY_DATA_IN       => m_DATA_OUT((i+2)*DATA_WIDTH*2-1 downto (i+1)*DATA_WIDTH*2),\r
+        MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_OUT((i+2)*NUM_WIDTH*2-1 downto (i+1)*NUM_WIDTH*2),\r
+        MED_REPLY_READ_OUT      => m_READ_IN(i*2+1),\r
+        MED_REPLY_ERROR_IN      => m_ERROR_IN((i+1)*3-1 downto i*3),\r
+        \r
+        -- Internal direction port\r
+\r
+        INT_INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i),\r
+        INT_INIT_DATA_OUT      => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+        INT_INIT_PACKET_NUM_OUT=> buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+        INT_INIT_READ_IN       => buf_to_hub_INIT_READ(i),\r
+\r
+        INT_INIT_DATAREADY_IN  => hub_to_buf_INIT_DATAREADY(i),\r
+        INT_INIT_DATA_IN       => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+        INT_INIT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+        INT_INIT_READ_OUT      => hub_to_buf_INIT_READ(i),\r
+        \r
+        INT_REPLY_HEADER_IN     => buf_to_hub_REPLY_SEND_HEADER(i),\r
+        INT_REPLY_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i),\r
+        INT_REPLY_DATA_OUT      => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+        INT_REPLY_PACKET_NUM_OUT=> buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+        INT_REPLY_READ_IN       => buf_to_hub_REPLY_READ(i),\r
+\r
+        INT_REPLY_DATAREADY_IN  => hub_to_buf_REPLY_DATAREADY(i),\r
+        INT_REPLY_DATA_IN       => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+        INT_REPLY_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+        INT_REPLY_READ_OUT      => hub_to_buf_REPLY_READ(i),\r
+\r
+        -- Status and control port\r
+        STAT_GEN               => IOBUF_STAT_GEN((i+1)*32 downto i*32),\r
+        STAT_LOCKED            => IOBUF_STAT_LOCKED((i+1)*32 downto i*32),\r
+        STAT_INIT_BUFFER       => IOBUF_buf_STAT_INIT_BUFFER((i+1)*32 downto i*32),\r
+        STAT_REPLY_BUFFER      => IOBUF_STAT_REPLY_BUFFER((i+1)*32 downto i*32),\r
+        CTRL_GEN               => IOBUF_CTRL_GEN((i+1)*32 downto i*32),\r
+        CTRL_LOCKED            => IOBUF_CTRL_LOCKED((i+1)*32 downto i*32),\r
+        STAT_CTRL_INIT_BUFFER  => IOBUF_STAT_CTRL_INIT_BUFFER((i+1)*32 downto i*32),\r
+        STAT_CTRL_REPLY_BUFFER => IOBUF_STAT_CTRL_REPLY_BUFFER((i+1)*32 downto i*32)\r
+        );\r
+  end generate;\r
+  \r
+  gen_hub_logic: for i in 0 to 2**(MUX_WIDTH-1)-1 generate\r
+    HUBLOGIC : trb_net16_base_hub_logic\r
+      generic map{\r
+      --media interfaces\r
+        POINT_NUMBER        => MII_NUMBER,\r
+        INIT_DEPTH          => MII_INIT_DEPTH((i+1)*4 downto i*4),\r
+        REPLY_DEPTH         => MII_REPLY_DEPTH((i+1)*4 downto i*4),\r
+      --general settings\r
+        DATA_WIDTH          => DATA_WIDTH,\r
+        NUM_WIDTH           => NUM_WIDTH\r
+        )\r
+      port map(\r
+        CLK    => CLK,\r
+         RESET  => RESET,\r
+         CLK_EN => CLK_EN,\r
+        INIT_DATAREADY_IN    => buf_to_hub_INIT_DATAREADY(i),\r
+        INIT_DATA_IN         => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+        INIT_PACKET_NUM_IN   => buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+        INIT_READ_OUT        => buf_to_hub_INIT_READ(i),\r
+        INIT_DATAREADY_OUT   => buf_to_hub_INIT_DATAREADY(i),\r
+        INIT_DATA_OUT        => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+        INIT_PACKET_NUM_OUT  => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+        INIT_READ_IN         => hub_to_buf_INIT_READ(i),\r
+        REPLY_HEADER_OUT     => hub_to_buf_REPLY_HEADER_OUT(i),\r
+        REPLY_DATAREADY_IN   => buf_to_hub_REPLY_DATAREADY(i),\r
+        REPLY_DATA_IN        => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+        REPLY_PACKET_NUM_IN  => buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+        REPLY_READ_OUT       => buf_to_hub_REPLY_READ(i),\r
+        REPLY_DATAREADY_OUT  => hub_to_buf_REPLY_DATAREADY(i),\r
+        REPLY_DATA_OUT       => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH),\r
+        REPLY_PACKET_NUM_OUT => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH),\r
+        REPLY_READ_IN        => hub_to_buf_REPLY_READ(i),\r
+        STAT_INTERFACE           => HUB_STAT_CHANNEL((i+1)*32-1 downto i*32),\r
+        STAT_GEN                 => HUB_STAT_GEN((i+1)*32-1 downto i*32),\r
+        CTRL_INTERFACE           => HUB_CTRL_CHANNEL((i+1)*32-1 downto i*32),\r
+        CTRL_GEN                 => HUB_CTRL_GEN((i+1)*32-1 downto i*32)\r
+        )\r
+  end generate;\r
+  \r
+end architecture;\r

diff --git a/trb_net16_base_hub_logic.vhd b/trb_net16_base_hub_logic.vhd
new file mode 100644 (file)
index 0000000..1120fdb
--- /dev/null
+++ b/trb_net16_base_hub_logic.vhd
@@ -0,0 +1,107 @@
+LIBRARY IEEE;\r
+USE IEEE.std_logic_1164.ALL;\r
+USE IEEE.std_logic_ARITH.ALL;\r
+USE IEEE.std_logic_UNSIGNED.ALL;\r
+\r
+use work.trb_net_std.all;\r
+\r
+\r
+entity trb_net16_base_hub_logic is\r
+  generic (\r
+  --media interfaces\r
+    POINT_NUMBER        : integer range 2 to 16 := 2;\r
+    INIT_DEPTH          : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111";\r
+    REPLY_DEPTH         : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111";\r
+  --general settings\r
+    DATA_WIDTH          : integer range 16 to 16 := 16;\r
+    NUM_WIDTH           : integer range 2 to 2 := 2\r
+    );\r
+  port (\r
+    CLK    : in std_logic;\r
+         RESET  : in std_logic;\r
+         CLK_EN : in std_logic;\r
+    --Internal interfaccs to IOBufs\r
+    INIT_DATAREADY_IN     : in  std_logic_vector (PONUMBER downto 0);\r
+    INIT_DATA_IN          : in  std_logic_vector (DATA_WIDTH*PONUMBER downto 0);\r
+    INIT_PACKET_NUM_IN    : in  std_logic_vector (NUM_WIDTH*PONUMBER downto 0);\r
+    INIT_READ_OUT         : out std_logic_vector (PONUMBER downto 0);\r
+    INIT_DATAREADY_OUT    : out std_logic_vector (PONUMBER downto 0);\r
+    INIT_DATA_OUT         : out std_logic_vector (DATA_WIDTH*PONUMBER downto 0);\r
+    INIT_PACKET_NUM_OUT   : out std_logic_vector (NUM_WIDTH*PONUMBER downto 0);\r
+    INIT_READ_IN          : in  std_logic_vector (PONUMBER downto 0);\r
+    REPLY_HEADER_OUT      : out std_logic_vector (PONUMBER downto 0);\r
+    REPLY_DATAREADY_IN    : in  std_logic_vector (PONUMBER downto 0);\r
+    REPLY_DATA_IN         : in  std_logic_vector (DATA_WIDTH*PONUMBER downto 0);\r
+    REPLY_PACKET_NUM_IN   : in  std_logic_vector (NUM_WIDTH*PONUMBER downto 0);\r
+    REPLY_READ_OUT        : out std_logic_vector (PONUMBER downto 0);\r
+    REPLY_DATAREADY_OUT   : out std_logic_vector (PONUMBER downto 0);\r
+    REPLY_DATA_OUT        : out std_logic_vector (DATA_WIDTH*PONUMBER downto 0);\r
+    REPLY_PACKET_NUM_OUT  : out std_logic_vector (NUM_WIDTH*PONUMBER downto 0);\r
+    REPLY_READ_IN         : in  std_logic_vector (PONUMBER downto 0);\r
+    --Status ports (for debugging)\r
+    STAT_CHANNEL       : out std_logic_vector (15 downto 0);\r
+    STAT_GEN           : out std_logic_vector (31 downto 0);\r
+    CTRL_CHANNEL       : in  std_logic_vector (31 downto 0);\r
+    CTRL_GEN           : in  std_logic_vector (31 downto 0) \r
+    );\r
+end entity;\r
+\r
+architecture trb_net16_base_hub_logic_arch of trb_net16_base_hub_logic is\r
+begin\r
+--Datapool for Init-Channel\r
+  INIT_POOL_DATAREADY <= or_all(INIT_DATAREADY_IN(POINT_NUMBER-1 downto 0);\r
+  INIT_POOL_READ <=\r
+        and_all(INIT_READ_IN(POINT_NUMBER-1 downto 0) or init_pool_has_read(POINT_NUMBER-1 downto 0));\r
+    \r
+  gen_init_pool_data0: for i in 0 to DATA_WIDTH-1 generate\r
+    process(INIT_DATA_IN)\r
+      variable VAR_INIT_POOL_DATA : std_logic;\r
+    begin\r
+      VAR_INIT_POOL_DATA := 0;\r
+      gen_init_pool_data1: for j in 0 to POINT_NUMBER-1 loop\r
+        VAR_INIT_POOL_DATA := VAR_INIT_POOL_DATA or INIT_DATA_IN(j*DATA_WIDTH+i);\r
+      end loop;\r
+      INIT_POOL_DATA(i) <= VAR_INIT_POOL_DATA;\r
+    end process;\r
+  end generate;\r
+\r
+--Data for obuf output\r
+  gen_init_dataready_out: for i in 0 to POINT_NUMBER-1 generate  \r
+    INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_pool_has_read(i);\r
+  end generate;\r
+\r
+  gen_init_data_out: for i in 0 to POINT_NUMBER-1 generate  \r
+    INIT_DATA_OUT((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH) <= INIT_POOL_DATA;\r
+  end generate;  \r
+  \r
+  gen_init_read_in\r
+  \r
+  --DATAREADY for each OBUF is dataready from all ibufs and not already have been reading this word\r
+  -- gen_init_datapool_c: for CHANNEL in 0 to 2**(MUX_WIDTH-1)-1 generate\r
+    -- gen_init_datapool_m: for MEDIA in 0 to MII_NUMBER-1 generate\r
+      -- hub_to_buf_INIT_DATAREADY(CHANNEL*MII_NUMBER+MEDIA) <= \r
+                -- or_all(buf_to_hub_DATAREADY((CHANNEL+1)*MII_NUMBER-1 downto CHANNEL*MII_NUMBER) \r
+                -- and not buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA);\r
+      -- hub_to_buf_INIT_DATA((CHANNEL*MII_NUMBER+MEDIA)*(DATA_WIDTH+1)-1 downto CHANNEL*MII_NUMBER+MEDIA)*(DATA_WIDTH)) <=\r
+                -- or_all(\r
+    -- end generate;\r
+  -- end generate;\r
+\r
+  -- gen_init_has_read_c: for CHANNEL in 0 to 2**(MUX_WIDTH-1)-1 generate\r
+    -- gen_init_has_read_m: for MEDIA in 0 to MII_NUMBER-1 generate\r
+      -- process(CLK)\r
+        -- begin\r
+          -- if rising_edge(CLK) then\r
+            -- if RESET = '1' or buf_to_hub_INIT_CHANNEL_READ(CHANNEL) = '1' then\r
+              -- buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA) <= '0';\r
+            -- else\r
+              -- if hub_to_buf_INIT_DATAREADY(CHANNEL*MII_NUMBER+MEDIA) = '1' \r
+                    -- and hub_to_buf_INIT_READ(CHANNEL*MII_NUMBER+MEDIA) = '1' then\r
+                -- buf_init_has_read(CHANNEL*MII_NUMBER+MEDIA) <= '1';\r
+              -- end if;\r
+            -- end if;\r
+          -- end if;\r
+        -- end process;\r
+    -- end generate;\r
+  -- end generate; \r
+end architecture;
\ No newline at end of file

diff --git a/xilinx/trb_net_fifo_arch.vhd b/xilinx/trb_net_fifo_arch.vhd
index fae50607a80742cf7b9485de98f34b48698d80e8..7e8cafcfe050b6865bae64925a708e7cf265ef24 100644 (file)
--- a/xilinx/trb_net_fifo_arch.vhd
+++ b/xilinx/trb_net_fifo_arch.vhd
@@ -121,18 +121,16 @@ begin
     reg_output: process(CLK)
     begin
       if rising_edge(CLK) then
-      if RESET = '1' then
-        current_DOUT <= (others => '0');
-      elsif CLK_EN = '1' then
-        if current_EMPTY = '1' or real_ADDRESS_SRL(DEPTH+1) = '1' then
-          current_DOUT <= DATA_IN;
-        else
-          current_DOUT <= next_DOUT;
+        if RESET = '1' then
+          current_DOUT <= (others => '0');
+        elsif CLK_EN = '1' then
+          if current_EMPTY = '1' or real_ADDRESS_SRL(DEPTH+1) = '1' then
+            current_DOUT <= DATA_IN;
+          else
+            current_DOUT <= next_DOUT;
+          end if;
         end if;
-      else
-        current_DOUT <= current_DOUT;
       end if;
-          end if;
     end process;
   
   -- Comparator Block