port interface is updated - cu

diff --git a/tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd b/tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd
index 66df513327c57b407981853ac74e2ee99eb64b9e..bbadd10e5725fbdcc678bf5f832f6dfa0da1b903 100644 (file)
--- a/tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd
+++ b/tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd
@@ -5,7 +5,7 @@
 -- File       : LogicAnalyser.vhd
 -- Author     : cugur@gsi.de
 -- Created    : 2012-10-26
--- Last update: 2012-10-26
+-- Last update: 2013-03-27
 -------------------------------------------------------------------------------
 -- Description: 
 -------------------------------------------------------------------------------
@@ -21,8 +21,7 @@ use work.trb3_components.all;
 
 entity LogicAnalyser is
   generic (
-    CHANNEL_NUMBER : integer range 2 to 65;
-    STATUS_REG_NR  : integer range 0 to 6);
+    CHANNEL_NUMBER : integer range 2 to 65);
 
   port (
     CLK        : in  std_logic;