FWD_FULL_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
MAKE_RESET_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(127 downto 0)
+ DEBUG_OUT : out std_logic_vector(127 downto 0);
+ STATUS_OUT : out std_logic_vector(15 downto 0)
);
end entity gbe_wrapper;
STAT_ONEWIRE : out std_logic_vector (31 downto 0);
STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);
STAT_TRIGGER_OUT : out std_logic_vector (79 downto 0);
+ STATUS_GBE_OUT : out std_logic_vector (15 downto 0);
DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)
);
end trb_net16_endpoint_hades_full_gbe;
MAKE_RESET_OUT => open,
- DEBUG_OUT => open
+ STATUS_OUT => STATUS_GBE_OUT
);
end generate;
gen_no_gbe : if USE_GBE = 0 generate
STAT_ONEWIRE : out std_logic_vector (31 downto 0);
STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);
STAT_TRIGGER_OUT : out std_logic_vector (79 downto 0);
+ STATUS_GBE_OUT : out std_logic_vector (15 downto 0);
DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)
);
end entity;
STAT_ONEWIRE => open,
STAT_ADDR_DEBUG => open,
STAT_TRIGGER_OUT => STAT_TRIGGER_OUT,
+ STATUS_GBE_OUT => STATUS_GBE_OUT,
DEBUG_LVL1_HANDLER_OUT => DEBUG_LVL1_HANDLER_OUT
);
FWD_FULL_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);\r
\r
MAKE_RESET_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(127 downto 0)\r
+ DEBUG_OUT : out std_logic_vector(127 downto 0);\r
+ STATUS_OUT : out std_logic_vector(15 downto 0)\r
);\r
end component;\r
\r
STAT_ONEWIRE : out std_logic_vector (31 downto 0);\r
STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);\r
STAT_TRIGGER_OUT : out std_logic_vector (79 downto 0);\r
+ STATUS_GBE_OUT : out std_logic_vector (15 downto 0); \r
DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)\r
);\r
end component; \r